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IP and Reference Design
GOWIN and our design partners provide proven Intellectual Property (IP) for various market segments and applications to accelerate your design innovation, simplify your work, and let you focus on your key competence.
Access to GOWIN IP and Reference Designs is subject to the following End User License Agreement (EULA): Download GOWIN EULA
| Title | Version | Device Support | Provider | Type |
|---|---|---|---|---|
| Gowin PSRAM Memory Interface | 1.2 | GW1N(R/S/SR),GW2A(R) | GOWIN | IP Core |
| Gowin PSRAM Memory Interface 2CH | 1.0 | GW1NR, GW2AR | GOWIN | IP Core |
| Gowin PSRAM Memory Interface HS & HS 2CH | 1.0 | All Devices (except GW1N(R)(Z)-1,AroraV) | GOWIN | IP Core |
| Gowin_PSRAM_Memory_Interface_HS_V2.0 | 2.0 | 1N and 2A all Devices（except GW1N(R)(Z)-1） | GOWIN | IP Core |
| Gowin PicoRV32 | 1.0 | GW1NS-2C, GW1NSR-2C, GW1NSE-2C,GW1NS-4C, GW1NSR-4C, GW1NSE-4C, GW1NSER-4C,GW1N-9, GW1NR-9, GW2A-18, GW2AR-18, GW2A-55, GW1N-9, GW1NR-9, GW2A-18, GW2AR-18, GW2A-55 | GOWIN | IP Core |
| Gowin RAM Based Shift Register | 1.0 | All Devices | GOWIN | IP Core |
| Gowin RISC-V | 1.1 | GW2A(R/NR/N) | RISC-V | IP Core |
| Gowin Scaler | 3.3 | GW1N(R)-9,GW2A(R/NR/N),GW5A(S)(N)(R)(T) | GOWIN | IP Core |
| GOWIN SPI | 1.0 | GW2A | GOWIN | Reference Design |
| Gowin Scaler Lite | 2.3 | GW1N(R)-4/9,GW1NS(R)-4,GW1NSER-4C,GW1NRF-4B,GW2A(NR/R/N),GW5A(S)(N)(R)(T) | GOWIN | IP Core |