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HYPERBUS(TM) / PSRAM MEMORY INTERFACE

GOWIN's HyperBus(TM) / PSRAM Memory Interface IP is a common used HyperBus (TM) / PSRAM interface IP, in compliance with JESD79-F. The IP includes the HyperBus(TM) / PSRAM MC (Memory Controller) and the corresponding PHY (Physical Interface) design. GOWIN's HyperBus(TM) / PSRAM Memory Interface IP provides users with a generic command interface to connect with HyperRam, HyperFlash, and PSRAM chips for access and data storage.

 

Features

 

  •  Supports  all GOWIN FPGA devices;
  •  Interfaces with the HyperRAM, HyperFlash, and PSRAM devices;
  •  Support memory data path width of 8 bits, 16 bits, 24 bits, 32 bits, 40

 bits, 48 bits, 56 bits, and 64 bits;

  •  Supports x8 and x16 data widths memory chips;
  •  Programs 16, 32, 64 or 128 burst lengths;
  •  The clock rate is 1:2
  •  The initial delay is six clock cycles;
  •  Supports the fixed delay mode;
  •  Supports the power off options;
  •  Configurable drive strength;
  •  Configurable self-refresh area;
  •  Configurable refresh rate.
Documents Download
User Guide Gowin PSRAM Memory Interface IP User Guide** Download
Reference Design Gowin PSRAM Memory Interface RefDesign Download
Release Note Gowin PSRAM Memory Interface Release Note Download