Senior Engineer / Engineer, FPGA Design

Job Highlights

• FPGA / SoC design
• DSP algorithms
• RTL coding

Job Description

• Responsible for RTL design, coding, logic synthesis, functional verification, and timing analysis
• Develop IP cores for DSP, multimedia, error control, cryptography, and communications
• Work closely with algorithm and system teams to build FPGA prototypes
• Work location: Hong Kong Science Park

Job Requirements

• Bachelor’s degree or above in electronic engineering, integrated circuit, or related disciplines.
• Senior titles will be offered to candidates with more experience. Fresh graduates are welcome to apply.
• Knowledge in microprocessors, computer architecture and FPGA / SoC design methodology
• Experience in developing bit accurate models in Matlab and carrying out RTL coding plus module, top and board level verification is an advantage
• Strong programming skills in at least one of the following languages / libraries: Verilog, System Verilog, Matlab, Simulink, C/C++
• Must be a highly organized, detail-oriented self-starter, who can deliver independently as well as in a team environment
• Good verbal and written communication skills in English and Chinese

Interested parties please send full resume with expected salary to thomas@gowinsemi.com