In order to optimize your browsing experience we uses cookies. You agree to the usage of cookies when you browsing this site.
For more information regarding cookies and the processing of your personal data please read our Privacy Policy.
SUPPORT
Listen to Your Voices and Let Us Know Your Needs
Back
Gowin DDR2 PHY Interface
Introduction
Gowin DDR2 PHY Interface IP integrates DQS hardcore and other related hardcore resources to realize DDR2 PHY function, which requires customers to implement MC layer to interface with DDR2 PHY Interface IP, combining them into a complete MC+PHY IP.
Features
- Supports GW5A(R)(S)(T) devices
- Complies with the JESD79-2F standard
- Supports memory data path widths of 8, 16, 24, 32, 40, 48, 56, and 64bits
- Supports single-rank RDIMM, UDIMM, and SODIMM memory modules
- Supports x8 and x16 data width memory chips
- BURST MODE supports 4 or 8
- Memory clock to User clock frequency ratio is 4:1
- Configurable CL, AL, tFAW, tRAS, tRCD, tRFC, tRRD, tRTP, tWTR
- Supports on-chip ODT
Documents Download
| User Guide | Gowin DDR2 PHY Interface IP User Guide | Download |