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GOWIN Semiconductor Introduces Educational EDA Version V1.9.10.03 with macOS Support GOWIN Semiconductor Introduces Educational EDA Version V1.9.10.03 with macOS Support San Jose, California, and Guangzhou, China — November 29, 2024 GOWIN Semiconductor Corporation, the world's fastest-growing FPGA company, is thrilled to announce the release of GOWIN Educational EDA Version V1.9.10.03, a significant update to its license-free software platform. Designed for students, educators, and hobbyists, the educational version allows users to dive into FPGA programming without the need for a licensing process. In a groundbreaking first, this new version extends support to macOS, alongside Windows and Linux, making FPGA development accessible across all major operating systems. "A lot of university students and hobbyists are starting their college journey using a Mac, and I think we will see more CS students graduating and using macOS in the real world," said Jason Zhu, CEO of GOWIN Semiconductor. "We want GOWIN to be accessible for everyone, and we're excited to extend macOS support to our full EDA in the near future." GOWIN Educational EDA is tailored to remove barriers for entry-level users, offering reduced features in a lightweight, user-friendly environment. With macOS compatibility, GOWIN continues its mission to provide cutting-edge FPGA solutions that align with modern user needs. For more information and to download the educational EDA, visit www.gowinsemi.com. About GOWIN Semiconductor Corporation Founded in 2014, Gowin Semiconductor Corp., headquartered with major R&D in China, has the vision to accelerate customer innovation worldwide with our programmable solutions. We focus on optimizing our products and removing barriers for customers using programmable logic devices. Our commitment to technology and quality enables customers to reduce the total cost of ownership from using FPGA on their production boards. Our offerings include a broad portfolio of programmable logic devices, design software, intellectual property (IP) cores, reference designs, and development kits. We strive to serve customers in the consumer, industrial, communication, medical, and automotive markets worldwide. Copyright 2024 GOWIN Semiconductor Corp. GOWIN, LittleBee®, GW1N/NR/NS/1NSR/1NZ®, Arora®, Arora V®, GW2A/AR®, GOWIN EDA and other designated brands included herein are trademarks of GOWIN Semiconductor Corp. in China and other countries. All other trademarks are the property of their respective owners. For more information, please email info@gowinsemi.com Media Contact: Andrew Dudaronek andrew@gowinsemi.com

Growing demand for high-speed data in consumer devices gives rise to new generation of low-end FPGAs Growing demand for high-speed data in consumer devices gives rise to new generation of low-end FPGAs By Jason Zhu CEO, GOWIN Semiconductor When a designer of telecoms equipment such as a server or switch specifies an FPGA for a high-speed data interfacing function, performance is the most important criterion for choosing the preferred device. If the rule of thumb in specifying an electronics component is that the designer can have one or two of high speed, low power consumption, small size and low cost, but not three or all four of these attributes, the telecoms equipment manufacturer will prioritize high speed above the other factors. This has given the manufacturers of high-end, high-density FPGAs a strong incentive to develop products which are packed with high-performance SerDes capabilities, and which support the high-speed communications protocols – PCIe, Ethernet, Infiniband and so on – on which communications service providers’ fiber networks are based. These FPGAs might be large, they might be expensive, and they might be power-hungry – but this is of little importance to equipment manufacturers serving the telecoms market, as long as they are fast. How different it is in the market for portable and wearable consumer devices, where the cost, power consumption and size of an FPGA are impossible to overlook. This has meant that the FPGA’s role in consumer devices has generally been limited to functions which basic FPGAs – small, low-power, low-density and low-cost products – can perform, such as: Glue logic integration Simple counter Basic state machine Control logic I/O and interface bridging I/O expansion Aggregation of multiple sensor inputs Voltage monitoring For anything more demanding, the FPGA market did not in the past provide products which could meet the consumer market’s speed/cost/size requirements. In fact, there was no demand for the FPGA’s high-speed data interfacing capabilities for as long as consumer devices were handling relatively small amounts of data to support undemanding input and output devices such as a basic camera or a small display. But the consumer world is changing: technology and consumer demand are driving data throughput off the scale. We are discovering that there is almost no limit to people’s appetite for vivid, ultra high-definition (UHD) video and AI-enhanced high-resolution imaging, even in space- and power-deprived wearable products such as AR/VR headsets and smart glasses (see Figure 1). For instance, a VR headset will typically be required to cram the type of UHD content more normally viewed on a large TV screen on to two synchronized displays. Not only must the output achieve 4K or even 8K resolution, it must also be rendered at a higher frame rate – typically 128 frames/s – than a standard TV achieves, to avoid the risk of motion blur. Fig. 1: to create immersive experiences, a VR headset requires ultra high-definition display capability, and the internal data bandwidth to support it This is leading device manufacturers to migrate from interfaces such as MIPI D-PHY or DisplayPort for video to higher-speed alternatives such as MIPI C-PHY. And this calls for the type of high-speed SerDes capability that the telecoms equipment designer uses an FPGA to provide. But we know that the high-speed FPGAs developed for the telecoms market are not suitable for consumer devices. This is why I foresee the emergence of a new category of FPGA at the low-density, low-cost end of the market that has previously been limited to basic logic functions. This new-generation FPGA will be optimized for high-speed SerDes functions: it will offer not only raw high-speed SerDes capability, but will also specifically support the protocols that the new consumer devices is using, such as MIPI C-PHY and PCIe, either as soft-coded IP or even hard-coded into the silicon (see Figure 2). This SerDes capability will be backed by more generous provision of high-speed memory than is usual in low-end FPGAs. Fig. 2: examples of video bridging and processing use cases in the latest consumer devices Optimized for data-interfacing and data-bridging functions, this new generation of FPGA will provide limited scope for implementing other logic functions, with few general-purpose logic elements available to the application, in order to minimize die size and cost. GOWIN Semiconductor’s view is that such an FPGA demands a strategic shift from the manufacturers of low-density FPGAs. To date, they have met the requirement for low cost by stretching out the life of legacy process nodes used to fabricate their products, using a 40nm process or older, for which the investment in equipment and mask sets is relatively small. GOWIN itself has a strong position in consumer devices with its LittleBee family of low-density FPGAs, which are themselves built on a legacy process. The LittleBee FPGAs perform a data aggregation function in many wearable and mobile devices. Without data aggregation, sensor data would be transferred to the main microcontroller or system-on-chip (SoC), and commands or configuration data transferred from the SoC to sensors, over low-speed interfaces such as I2C, UART or SPI working as sideband communication channels. This results in the proliferation of wires between the SoC and sensor sub-systems, which are often mounted on a separate board from the main controller board. By implementing data aggregation in an FPGA, data from multiple sensors can be combined into a single high-speed data stream, reducing the number of physical network connections between the host and the various sub-systems. An example of the implementation of data aggregation is the OCP DC-SCM project in servers. While legacy fabrication processes might be adequate for the aggregation of low-speed I2C, UART or SPI interfaces, however, they are not going to meet the requirement for advanced SerDes circuitry: the MIPI C-PHY specification, for instance, supports a data rate of up to 13.7Gbps [1], offering as much as three times the bandwidth of the earlier MIPI D-PHY standard. This is why GOWIN took the radical decision to move to an advanced node – a TSMC 22nm ultra low-power process – for its Arora V family of low-density FPGAs. This 22nm process has allowed GOWIN to include a high-speed transceiver on-chip in the Arora V FPGAs. It has also enabled much larger memory provision: in the shift from the 55nm node used for LittleBee FPGAs to 22nm, the size of the memory cell shrinks by 90%. The practical consequence of the decision to adopt 22nm fabrication can be seen in the specifications of the Arora V GW5AT-60 product. It features four transceivers supporting a data-rate range of 270Mbps up to 12.5Gbps. A hardcore MIPI D-PHY interface offers four data lanes, and a hardcore MIPI C-PHY has three data lanes. Softcore interfaces include PCIe 2.0 (with 1, 2 and 4 lanes), and LVDS at up to 1.25Gbps, as well as a DDR3 interface operating at up to 1,333Mbps. Memory provision includes 118 blocks of 2,124kb block SRAM, and 468kb of shadow SRAM. The FPGA also includes 60k LUT4 logic elements. The device’s core voltage is 0.9V/1.0V/1.2V. This illustrates the way that, by fabricating at an advanced node, it becomes possible to create a low-density, low-power FPGA that provides for very high-speed data interfacing. And because of the small size of this FPGA, it can be offered at a unit cost which is affordable in wearable and portable consumer devices. In fact, the cost is attractive enough that OEMs can retain the FPGA in high-volume production, without having to contemplate replacing it with a custom ASIC, a step which is time consuming and risky, and which OEMs prefer to avoid. The commitment to an advanced silicon process in a product family which includes low-end FPGAs is now pointing the market in a new direction, one which combines the high-speed transceiver capabilities of traditional telecoms FPGAs with the low cost and low power consumption of traditional low-end FPGAs. There is a ready market for this new generation of FPGAs in consumer devices which use new high-speed transceiver capabilities to meet the needs, today, of ultra high-definition cameras and displays – and in future, potentially of additional high-speed peripherals supporting a new set of features and use cases driven by AI, AR and VR systems. Reference: [1] MIPI C-PHY maximum data rate, from: https://www.mipi.org/specifications/c-phy

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How silicon and circuit optimizations help FPGAs offer lower size, power and cost in video bridging applications How silicon and circuit optimizations help FPGAs offer lower size, power and cost in video bridging applications By Danny Fisher Director of International Marketing, GOWIN Semiconductor FPGAs are at home in the world of multi-gigabit-per-second signal conversion and bridging. In high-bandwidth telecoms, network and data center equipment, the FPGA is a mainstay of system designs, offering a valuable combination of high-speed SerDes capability, extensive logic resources, and programmability, giving designers the flexibility to modify features and functions without changing their board layout. Indeed, FPGA manufacturers have a long track record of creating products which are well suited to the telecoms central office or the data center environment: very fast and large chips which provide hundreds of I/Os, huge bandwidth, and built-in standard interfaces. The fact that they are also expensive and power-hungry is a bearable trade-off for telecoms and network equipment manufacturers. Increasingly, however, the need for multi-gigabit-per-second rates in signal bridging systems is extending from telecoms and network equipment into consumer and industrial devices. Here, too, the FPGA offers valuable benefits. But large, expensive, power-hungry ICs are a poor fit for sleek, battery-powered consumer devices in the ultra-competitive markets for products such as tablets, laptop computers, and augmented/virtual reality (AR/VR) headsets. This new demand in consumer electronics is forcing FPGA manufacturers to rethink the architecture of their products in a bid to provide high-speed SerDes functionality at lower cost and low power. Gamers lead the way The change which has precipitated a new wave of competition in the low-cost FPGA market has been led by demand from gamers: tablets and laptop computers have become the latest devices in which users want to play games in 4K resolution and – for smooth rendition of fast motion – at high frame rates of up to 160 frames/s. The requirement for high-speed video signal transmission to support 4K displays stretches the capability of the interfaces that have previously been used in consumer devices to shuttle data from the central system-on-chip (SoC) to a display. Older MIPI D-PHY interface technology is giving way to the newer MIPI C-PHY standard for the most demanding 4K display applications in tablets and laptop computers. The doubling of the data rate in the migration from D-PHY to C-PHY technology poses a demanding challenge for low-end FPGAs. Following the lead of the latest gaming tablets and computers, other use cases are now also starting to demand increased bandwidth in the link between an SoC and one or more displays, or between image sensors and an SoC. Examples include: Point-of-sale systems which split a single output from an SoC (typically in MIPI DSI format) to dual displays, one facing the consumer, one facing the sales counter. The FPGA typically converts the single DSI input to one DSI and one eDP output, with image processing to rescale the output and adjust the frame rate (see Figure 1) VR/AR headsets and goggles, splitting and converting a DisplayPort-over-USB Type-C® input from a host device such as a PC or smartphone to separate MIPI outputs to a left and right display in the headset Industrial machine vision systems, converting an image sensor’s MIPI D-PHY or C-PHY input to a high-speed USB 3.0 output to a host computer. Fig. 1: using the GW5AT-15 FPGA, a single MIPI DSI video input from an external SoC can be converted to feed two displays requiring one MIPI output and one eDP output Higher-speed SerDes at lower power and cost In all these use cases, an FPGA can provide the raw SerDes throughput for one or multiple display screens or image sensors, while enabling changes in the input or output specifications to be made just by changing the VHDL or Verilog programming of the device. The question the consumer and industrial markets are asking is, how far can power consumption, size and cost be reduced while providing the high SerDes bandwidth these applications require? GOWIN has provided a new answer to the question by combining application-specific optimizations at both the silicon and circuit design level in a way that no low-density FPGA has ever before attempted. In silicon, scaling provides PPAC benefits (power, performance, area and cost) for low-end FPGAs as much as for other semiconductors. In the past, however, low-density FPGAs have tended not to take advantage of more advanced process nodes – FGPA manufacturers have preferred to extend the life of IP developed for legacy processes. But high-speed video bridging places extreme demands on the FPGA. That is why for its Arora® V products, GOWIN shifted production from the 55nm process used in its Arora II products to TSMC’s ultra-low power 22nm process. Use of this process has enabled GOWIN to gain performance, power and cost benefits in low-density Arora V products such as the GW5AT-15, available in a compact 4.9mm x 5.3mm WLCSP package. Despite its small size, this FPGA combines various hard-core SerDes transceivers offering maximum SerDes throughput of 12.5Gbps, together with 15,120 logic elements alongside high-speed memory resources including: 118kb of shadow SRAM 630kb of block SRAM (BSRAM) arranged as 35 x 18kb Optional 64Mb (in MG132P package) or 128Mb (in CM90P package) of pseudo SRAM (pSRAM) Optional 8Mb of NOR Flash By limiting the programmable logic provision to 15,120 logic elements, GOWIN can produce a smaller die at a lower unit cost, while providing sufficient digital capability to perform important image processing functions such as frame scaling and frame rate adaptation. The application-specific circuit design optimizations in the Arora V family provide the higher SerDes throughput required for instance by the gamers viewing 4K content at 160 frames/s on a tablet. For instance, the GW5AT-15 features hardcore implementations of important SerDes interfaces: Three-lane MIPI C-PHY (5.7Gbps/lane) Four-lane MIPI D-PHY (2.5Gbps/lane) x4 PCIe 2.0 Alongside these circuit features, the GW5AT-15 includes various built-in softcore interfaces suitable for video bridging applications: a USB 2.0 PHY, USB 3.0 PHY, PCIe 3.0, and up to four lanes of 12.5Gbps/lane SerDes suitable for DisplayPort, eDP, SLVS-EC, LVDS and other types of video traffic. These capabilities are what is required for the gaming tablet rendering 4K video at a high frame rate, converting a typical SoC’s MIPI output to a tablet display’s eDP input (see Figure 2). Fig. 2: conversion of video data from MIPI to eDP format in a gaming tablet requires high SerDes throughput The implementation of fast video bridging and image processing is as important when interfacing to a camera as when rendering video on a display. In industrial machine vision systems, for instance, a GOWIN GW5AT-15 or -60 can connect to a camera’s MIPI D-PHY or C-PHY interface and bridge the video to a host PC’s high-speed USB Type-C interface (see Figure 3). The FPGA’s softcore USB 3.0 PHY and USB 3.0 controller enables a single-chip implementation that can interface directly to the host controller without an external USB 3.0 PHY. This solution has an extremely small footprint which can be integrated into the camera enclosure. The GW5AT-60, which offers 59,950 logic elements, provides sufficient resources to support image preprocessing and machine vision-related algorithms. It also provides high-speed four-channel SerDes transceivers, hardcore MIPI C-PHY and D-PHY interfaces, and softcore LVDS interfaces to support a wide variety of sensors. Fig. 3: in an industrial machine vision system, use of an Arora V FPGA enables the USB 3.0 interface to a host PC to be integrated into the camera enclosure A new direction for the low-density FPGA The optimization of an FPGA product for video bridging and image processing applications points this segment of the low-density FPGA market in a new direction: in pursuit of greater size, power and cost reduction, FPGA products are evolving to include more application-specific SerDes functionality hard-wired into small devices. And where previously FPGAs achieved low cost by maintaining older, legacy silicon fabrication processes, a new generation of low-density FPGAs are using advanced processes to provide the valuable advantages of low power and small footprint while reducing cost by limiting the provision of logic elements that are not required in the target applications. This brings the FPGA to center stage in the consumer device market, enabling a new generation of devices to benefit from improved display and camera performance without sacrificing battery power or competitive cost.

Why Transceiver-Rich FPGAs Are Suitable for Vehicle Infotainment System Designs Why Transceiver-Rich FPGAs Are Suitable for Vehicle Infotainment System Designs By Danny Fisher, director of International Marketing, GOWIN Semiconductor With the global transition in the automotive industry from the internal combustion engine (ICE) to electric drivetrains well under way, the basis of competition in this market is undergoing a paradigm shift. In the old automotive world, the drivetrain was the primary factor that distinguished one segment from another: Consumers understood the differences in cost and appeal between, for instance, a compact car with a 1-liter petrol engine, a family sedan with a two-liter diesel engine and a high-performance model with a four-liter turbocharged petrol engine. By contrast, there is no such hierarchy of electric drivetrains. Instead, the focus of competition in the electric vehicle (EV) market is more on other factors than on the drivetrain: styling, driving range, and, crucially, the in-cabin experience. It turns out that, given the choice, car buyers want the information, entertainment, user interface, audio and display features of the car to mirror those of the devices that they use outside the car, and especially the smartphone. This move to a design philosophy, in which the car is treated as a smartphone on wheels, is powerfully symbolized by the launch in 2024 by Xiaomi, a globally renowned manufacturer of smartphones and consumer devices, of its first car, the SU7. In a smartphone, however, rendering of video content and the user interface is limited to the area available in a single, small display screen; in a car, there is scope to show information and entertainment content on multiple display screens in various sizes, formats and resolutions. This makes display provision and performance one of the most important new battlegrounds over which car manufacturers will be fighting. And this is fueling demand for a new generation of video bridging and processing components that will enable the shift to a more consumer device-like interior in the car. The implications of new smartphone-based system architectures in the car In the new EV market, the functions that the car is asked to perform (beyond the basic act of mobility) are increasingly similar to those of a smartphone, including: Communication with people and things Provision of audio and video entertainment Navigation Internet search and other forms of information provision Work-related functions, including the use of productivity apps such as spreadsheets and documents Car manufacturers are finding that the most effective designs for supporting this range of smartphone-like functions are based on smartphone-like hardware: automotive infotainment systems increasingly use applications processor platforms borrowed from the smartphone world, such as Qualcomm Snapdragon products or MediaTek 86xx family SoCs. These SoCs readily support the implementation of smartphone emulation products such as the Apple AirPlay or Android Auto software companions. But the architecture of these Qualcomm, MediaTek and similar smartphone SoCs does not map perfectly on to the hardware configuration of the new type of car cabin design. The SoCs’ display output is optimized for a single, small display screen: This output is generally an HD signal carried over a MIPI DSI or an embedded DisplayPort (eDP) interface. With strong competition in the EV market driving waves of innovation in cabin design, manufacturers are packing more and bigger displays into the interior, including: A large center console display, sometimes running across the entire width of the dashboard A digitally rendered virtual instrument cluster A holographic heads-up display in front of the driver 4K displays in the rear of the headrests on each of the front seats A large 4K roof-mounted central display for passengers in the rear seats These displays feature a variety of specifications for resolution and refresh rate and are of various sizes and aspect ratios. A smartphone SoC with just a DSI and an eDP interface cannot meet the requirements of the four or more different displays in the cabin of the latest EV designs. This calls for new solutions to bridge the SoC’s output to multiple displays’ inputs. The engineering challenge is complicated even further by consumers’ desire to use inside the car content and apps that are on their other devices. This is reflected in the move to upgrade the USB ports provided in the front and rear of the car from the USB 2 specification to USB 3 grade, and in the latest USB Type-C connector format. In particular, this allows passengers in the rear seats to cast 4K content from a tablet, laptop computer or smartphone to a large roof-mounted rear center display via a DisplayPort-over-USB Type-C interface. It can also enable display extension for a laptop computer to enhance the cabin’s value as a workspace for a rear passenger. At the same time, the rear center display still needs to provide an interface to the car’s own infotainment SoC as the default content source when no USB Type-C device is connected (see Figure 1). Fig. 1: the rear roof-mounted display can take inputs separately from a USB Type-C device or from the car’s infotainment SoC This increase in the number, size and quality of displays inside the car’s cabin marks a profound shift in interior design philosophy, from the car as a mobility product to the car as an entertainment hub and workspace. This is a new philosophy forged in response to fast-moving shifts in consumer tastes and preferences. Car makers will continue to learn over time what appeals to car buyers, and to evolve their designs for the user interface in response to customers’ changing tastes. So car manufacturers need a way to meet the need to bridge from the limited display outputs of a smartphone SoC to the multiple display input requirements of the car, while also providing high-speed USB 3, LVDS and MIPI D-PHY or C-PHY signaling rates. At the same time, they need to maintain the ability to respond rapidly to changes in consumer demand, and to iterate designs repeatedly with the least possible hardware development effort. An expanded role for FPGAs in new designs for the car’s UI As telecoms equipment and server manufacturers know, FPGAs can implement very high-speed interfaces operating at high signaling rates. In networking equipment, FPGAs are widely used to provide interfaces that conform to the latest specifications of standards such as PCIe or Ethernet. Because an FPGA is a programmable device, it offers the flexibility to modify designs rapidly in response to changing design specifications without requiring a change to the board design. This is a valuable benefit in today’s EV market, in which product development cycles are dramatically shorter than was the case when the integration and assembly of complex, difficult petrol- or diesel-fueled drivetrains set a slower pace for the entire new product development process. The approach to developing new EV models is becoming more like that for developing new smartphone products: fast, and with innovation in display, camera and video technologies to the fore. This calls for automotive-qualified FPGA products that can meet the requirement for a growing range of video bridging and image processing functions. Today, the Chinese EV industry is widely acknowledged to be setting the pace for the rest of the world in car UI design. Design innovations and technology solutions developed for EVs in China are expected to find their way into new car designs under development elsewhere in east Asia, as well as in Europe and the US. This means that FPGA manufacturers that have a strong position in the Chinese automotive market are exposed to the cutting edge in EV design, and so are often the first to respond with FPGA product developments that meet the need for new and improved display interfacing and image processing capabilities which bridge between a smartphone SoC and a car’s infotainment system. Fig. 2: smartphone SoCs with limited output capability can use a specialist FPGA for bridging to multiple display screens This explains why the market is seeing the introduction of a new generation of automotive-grade FPGA products which fit EVs’ emerging application requirements, including: Multi-screen display outputs with signal translation over long cable runs. A single infotainment SoC derived from a smartphone platform typically produces limited video outputs. In new display-rich car interiors, this output needs to be bridged to displays in both the front and rear of the cabin, while potentially converting the signal to MIPI or LVDS format (see Figure 2). Screen extension – outputs from a tablet or laptop computer’s USB Type-C interface need to be converted to a MIPI or LVDS format that a large automotive display can handle (see Figure 1). When no external video source is connected, the default SoC’s video source is automatically supplied to these screens. This calls for a combination of logic functions (for source selection), bridging (for instance from MIPI D-PHY to LVDS) and video processing (for instance for display image scaling). Video bridging, splitting and frame-rate conversion (see Figure 3). Fig. 3: typical examples of the video processing applications required in new infotainment system designs based on smartphone SoC platforms The availability of these new high-speed, programmable image processing devices will enable automotive manufacturers everywhere to respond more quickly and flexibly to the dynamics of the car market in which consumers who no longer obsess about horsepower are starting to demand an interior design with more entertainment, information and productivity features – and more and bigger displays.

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New low-cost option for high-speed 4K video display interfacing as GOWIN launches small FPGA with hard-core MIPI C-PHY capability GOWIN GW5AT-15 FPGA combines hard-core PCIe, MIPI D-PHY and MIPI C-PHY interfaces, in-package fast memory and programmable logic to give consumer and automotive applications the ideal mix of high-speed video, small size and low cost Santa Clara, CA – 25 June 2024 - GOWIN Semiconductor Corporation, the world's fastest-growing FPGA manufacturer, today launched the GW5AT-15 FPGA to provide a programmable high-speed bridging solution for demanding consumer electronics and automotive use cases such as 4K video transfer at high frame rates up to 120 frames/s. The new GW5AT-15, the latest member of the Arora-V® FPGA family, combines various hard-core SerDes transceivers with high-speed memory and 15,120 logic elements. The product is available in package options including a compact 4.9mm x 5.3mm WLCSP, which offers maximum SerDes throughput of 12.5Gbps. Arora-V products and the GOWIN EDA development environment can be viewed at GOWIN’s booth 708 at the Sensors Converge Expo (Santa Clara, California, US, 25-26 June 2024). The features of the GW5AT-15 are ideal for an emerging set of use cases which call for very high bandwidth for video and other data-transfer applications, and which require a small board footprint – examples include consumer tablets, augmented/virtual reality headsets, and car infotainment systems. The high SerDes bandwidth offered by the GW5AT-15 makes it ideal for use in high-speed interfaces. This new FPGA features: 3-lane MIPI C-PHY operating at up to 5.75Gbps/lane 4-lane PCIe 3.0 4-lane MIPI D-PHY operating at up to 2.5Gbps/lane The GW5AT-15 also supports high-speed USB Type-C® and other USB connections with its on-chip USB 3.x and USB 2.x PHYs. GOWIN’s CEO Jason Zhu said: ‘The market for high-speed display and camera interfaces has been stuck with a choice of high-end FPGAs which are large, expensive and power-hungry, or low-end FPGAs with inadequate SerDes performance. Our latest Arora-V device perfectly fills the gap, offering a unique hard-core MIPI C-PHY and D-PHY capability in a small and highly affordable FPGA. New use cases include 4K gaming tablets The high throughput offered by the GW5AT-15 supports gamers’ requirement for high frame-rate 4K video in the latest consumer tablet designs. In vehicle infotainment systems, the GW5AT-15’s provision of high-speed USB and other interfaces enables cars to better emulate the smartphone user experience through applications such as the Android Auto™ or Apple CarPlay® software companions. All SerDes operations are backed by co-packaged fast memory resources including: 118kb of shadow SRAM 630kb of block SRAM (BSRAM) arranged as 35 x 18kb Optional 64Mb (in MG132P package) or 128Mb (in CM90P package) of pseudo SRAM (pSRAM) Optional 8Mb of NOR Flash The FPGA also features two on-chip PLLs, multiple clock sources, a JPEG codec, and an ADC. Like the other members of the Arora-V family, the GW5AT-15 is built on a low-power 22nm TSMC process. It is backed by the GOWIN EDA FPGA design environment, which includes an FPGA design tool, IP cores and reference designs. The FPGA design tool supports the SystemVerilog, Verilog and VHDL programming languages. There are no licensing restrictions on the use of GOWIN EDA, and it can be downloaded free from www.gowinsemi.com. The GW5AT-15 is available for sampling now directly from GOWIN or through any authorized distributor. About GOWIN Semiconductor Corporation Founded in 2014, Gowin Semiconductor Corp., headquartered with major R&D in China, has the vision to accelerate customer innovation worldwide with our programmable solutions. We focus on optimizing our products and removing barriers for customers using programmable logic devices. Our commitment to technology and quality enables customers to reduce the total cost of ownership from using FPGAs on their production boards. Our offerings include a broad portfolio of programmable logic devices, design software, intellectual property (IP) cores, reference designs, and development kits. We strive to serve customers in the consumer, industrial, communication, medical, and automotive markets worldwide. For more information about GOWIN Semiconductor, please visit: https://www.gowinsemi.com/en/ Copyright 2024 GOWIN Semiconductor Corp. GOWIN, LittleBee®, GW1N/NR/NS/1NSR/1NZ®, Arora®, Arora V®, GW2A/AR®, GOWIN EDA and other designated brands included herein are trademarks of GOWIN Semiconductor Corp. in China and other countries. All other trademarks are the property of their respective owners. For more information, please email info@gowinsemi.com. Media Contacts: Andrew Dudaronek andrew@gowinsemi.com Rhianna Ogle, TKO Marketing Consultants rhianna@tko.co.uk Tel: +44 1444 473555

InfoComm Flyer 2024 Website (2100 × 696 px)

GOWIN Semiconductor to attend InfoComm 2024 San Jose, United States, and Guangzhou, China 9th May 2024 - GOWIN Semiconductor Corporation, a global leader in FPGA technology and the fastest-growing provider in the industry, is thrilled to announce its debut participation at InfoComm 2024, taking place from June 12th to 14th in Las Vegas, United States. This milestone coincides with GOWIN's tenth anniversary, marking a significant moment in our journey. Join us at booth W1352, where we will unveil our latest FPGA innovations and demonstrate their transformative capabilities. InfoComm stands as North America's premier audiovisual trade show, uniting manufacturers, integrators, dealers, and end-users worldwide to explore cutting-edge technologies, products, and services. At this esteemed event, we will present our groundbreaking FPGA offerings, notably highlighting the Arora V series. Renowned for their unparalleled SerDes performance and energy efficiency, these devices leverage TSMC’s 22nm LP process with proven automotive grade-1 capability, poised to redefine the mid-density FPGA market. Moreover, our new lineup offers exceptional power efficiency paired with competitive pricing, alongside compatibility with various competitor pin-compatible package options, facilitating seamless integration without PCB hardware redesign. Our booth will feature live demonstrations showcasing the versatility and power of our FPGA solutions, including MIPI CSI camera to HDMI display bridging utilizing the Arora-V GW5A-25 family, a Universal Audio Class (UAC2) USB2.0 2x2 audio interface powered by the cost-effective LittleBee Flash-based GW1N-9 family, and a captivating beam forming demo. In a special highlight, we are thrilled to announce that our esteemed CEO, Jason Zhu, will be joining our field sales team to engage in exclusive meetings with invited customers and partners. For those seeking visionary insights into the FPGA industry, this is an unparalleled opportunity to connect with a leader driving innovation. Scott Casper, Senior Director of Sales, Americas, expressed his enthusiasm, stating, “We are incredibly excited to make our inaugural appearance at InfoComm, presenting our expanding portfolio of products, IP, and pioneering solutions. This event underscores our commitment to leadership in the evolving low and mid-density FPGA landscape.” GOWIN Semiconductor eagerly anticipates welcoming all prospective customers and partners to booth W1352, where together, we'll explore the boundless possibilities of FPGA technology. Supporting Resources: For more information about GOWIN Semiconductor, please visit: https://www.gowinsemi.com/en/ For more information about and to register for the conference, visit https://www.infocommshow.org/ About GOWIN Semiconductor Corporation Founded in 2014, Gowin Semiconductor Corp., headquartered with major R&D in China, has the vision to accelerate customer innovation worldwide with our programmable solutions. We focus on optimizing our products and removing barriers for customers using programmable logic devices. Our commitment to technology and quality enables customers to reduce the total cost of ownership from using FPGA on their production boards. Our offerings include a broad portfolio of programmable logic devices, design software, intellectual property (IP) cores, reference designs, and development kits. We strive to serve customers in the consumer, industrial, communication, medical, and automotive markets worldwide. Copyright 2024 GOWIN Semiconductor Corp. GOWIN, LittleBee®, GW1N/NR/NS/1NSR/1NZ®, Arora®, Arora V®, GW2A/AR®, GOWIN EDA and other designated brands included herein are trademarks of GOWIN Semiconductor Corp. in China and other countries. All other trademarks are the property of their respective owners. For more information, please email info@gowinsemi.com Media Contact: Andrew Dudaronek andrew@gowinsemi.com

ISO26262-EN(4)(1)

GOWIN’s progress in global automotive market gathers momentum with award of ISO 26262 certification for its FPGA design environment High safety and reliability ratings of the GOWIN mid- and low-density FPGAs prompt automotive OEMs to design them into applications including video bridging, display driving and image signal processing London, UK and Guangzhou, China - 30 April 2024 - GOWIN Semiconductor Corporation, the world's fastest-growing FPGA manufacturer, today announced that its GOWIN EDA FPGA design environment has been certified compliant with the ISO 26262 and IEC 61508 functional safety standards by the TUV testing laboratory. Certification of the FPGA design tool provides strong assurance to automotive OEMs that module designs featuring a GOWIN Arora-V (mid-density), Arora-II (low-/mid-density) or LittleBee (low-density) FPGA can meet the requirements for system-level functional safety specified in the ISO 26262 and IEC 61508 standards. The award of functional safety certification is expected to spark a new wave of interest in GOWIN’s FPGAs, which are available in versions qualified to AEC-Q100 Grade 2, with qualification to AEC-Q100 Grade 1 pending. Existing quality and reliability certificates applicable to the GOWIN product range include IATF16949, ISO 9001, ISO 14001 and ISO/IEC 17025. Thanks to a superior feature set – including a wider range of high-speed video, display and graphics interfaces than other FPGAs in the same segment of the market – and a strong reliability record for devices fabricated on TSMC’s 22nm LP process, GOWIN FPGAs are already used in vehicles for applications such as: Video bridging and local display dimming in infotainment systems Image signal processing of camera outputs in advanced driver assistance systems (ADAS) USB audio interfacing Display monitoring and safety back-up in the instrument cluster GOWIN’s CEO Jason Zhu said: ‘GOWIN is attracting growing interest in the automotive industry because of its innovations in FPGA design in the low- and mid-density segments. Notably, we uniquely provide hardcore MIPI interfaces in FPGAs alongside DDR3 memory and high-speed LVDS and PCIe interfaces.' ‘With the award of functional safety certification for our popular GOWIN EDA development environment, we are confident in our ability to make further inroads into the automotive markets in Europe, North America and Asia.’ The GOWIN EDA FPGA design environment includes an FPGA design tool, IP cores and reference designs. The FPGA design tool supports the SystemVerilog, Verilog and VHDL programming languages. There are no licensing restrictions on the use of GOWIN EDA, and it can be downloaded free from www.gowinsemi.com. GOWIN’s automotive-qualified FPGA product range and the GOWIN EDA development environment can be viewed at its stand 3A.340 at Embedded World (Nuremberg, Germany, 9-11 April 2024). About GOWIN Semiconductor Corporation Founded in 2014, Gowin Semiconductor Corp., headquartered with major R&D in China, has the vision to accelerate customer innovation worldwide with our programmable solutions. We focus on optimizing our products and removing barriers for customers using programmable logic devices. Our commitment to technology and quality enables customers to reduce the total cost of ownership from using FPGAs on their production boards. Our offerings include a broad portfolio of programmable logic devices, design software, intellectual property (IP) cores, reference designs, and development kits. We strive to serve customers in the consumer, industrial, communication, medical, and automotive markets worldwide. For more information about GOWIN Semiconductor, please visit: https://www.gowinsemi.com/en/ Copyright 2024 GOWIN Semiconductor Corp. GOWIN, LittleBee®, GW1N/NR/NS/1NSR/1NZ®, Arora®, Arora V®, GW2A/AR®, GOWIN EDA and other designated brands included herein are trademarks of GOWIN Semiconductor Corp. in China and other countries. All other trademarks are the property of their respective owners. For more information, please email info@gowinsemi.com. Media Contacts: Andrew Dudaronek andrew@gowinsemi.com Rhianna Ogle, TKO Marketing Consultants rhianna@tko.co.uk

Embedded World Flyer 2024 Website (2100 × 696 px)

GOWIN Semiconductor to attend Embedded World 2024 London, UK and Guangzhou, China 13th March 2024 - GOWIN Semiconductor Corporation, recognized as the world's fastest-growing FPGA provider, is set to participate in Embedded World 2024 from April 9th to 11th in Nuremberg, Germany. This will be our fourth consecutive appearance at the EW exhibition and coincides with GOWIN’s tenth anniversary year. Our home for this year’s event will be Hall 3A Stand 340 where we will be showcasing and demonstrating our latest FPGA technology. Embedded World, hosted annually in Germany, stands as Europe's premier trade show for embedded solutions and technologies. Boasting over 1000 exhibitors, it ranks among the world's largest fairs dedicated to cutting-edge embedded technologies for IoT and related market segments. Following significant automotive success in Asia, GOWIN will continue focusing on the European automotive market this year. We will showcase our latest FPGA offerings, including our new Arora V series devices, celebrated for their exceptional SerDes performance, and energy efficiency. Utilizing TSMC’s 22nm LP process with proven automotive grade-1 capability, this new lineup is primed to make a significant impression on the mid density FPGA market. In addition to featuring industry-leading power efficiency with very competitive pricing, this new device family is also available in a range of competitor pin-compatible package options, enabling customers to explore replacement options without redesigning their PCB hardware. Stand demos this year will include MIPI CSI camera to HDMI display bridging using our new Arora-V GW5A-25 family, Universal Audio Class (UAC2) USB2.0 2x2 audio interface using our low-cost LittleBee Flash-based GW1N-9 family, a AE350 hardcore RISC-V demo using our latest Arora-V GW5AST-138 µSoC FPGA and Field Oriented Motor Control (FOC) using our mid-range Arora-2 family devices. Finally, we are delighted to announce our field sales team will be accompanied by Jason Zhu, CEO of GOWIN, who will be conducting meetings with invited customers and partners. Please contact us if you are interested in scheduling time with a FPGA industry visionary. “We are extremely excited to be once again participating at Embedded World in Nuremberg, Germany, showcasing our growing portfolio of products, IP, and innovative solutions.” said Mike Furnival, Vice President of International Sales. “Additionally, to have our CEO, Jason Zhu, joining us clearly illustrates the importance of our global sales efforts and resultant customer relationships. We believe that participation at this show will further cement our position as the true leader in the much changed low and mid density FPGA marketplace”. GOWIN Semiconductor looks forward to welcoming all interested potential customers and partners to our booth in Hall 3A Stand 340. Supporting Resources: To schedule a meeting with GOWIN Semiconductor at Embedded World 2024, please fill out this Google Form here: https://docs.google.com/forms/d/e/1FAIpQLSfsROeh2n92rf3VWtl6-BBWNPMaem2aDyPBfHJSrHRnQ9FhDQ/viewform For more information about GOWIN Semiconductor, please visit: https://www.gowinsemi.com/en/ For more information about and to register for the conference, visit https://www.embedded-world.de/en About GOWIN Semiconductor Corporation Founded in 2014, Gowin Semiconductor Corp., headquartered with major R&D in China, has the vision to accelerate customer innovation worldwide with our programmable solutions. We focus on optimizing our products and removing barriers for customers using programmable logic devices. Our commitment to technology and quality enables customers to reduce the total cost of ownership from using FPGA on their production boards. Our offerings include a broad portfolio of programmable logic devices, design software, intellectual property (IP) cores, reference designs, and development kits. We strive to serve customers in the consumer, industrial, communication, medical, and automotive markets worldwide. Copyright 2024 GOWIN Semiconductor Corp. GOWIN, LittleBee®, GW1N/NR/NS/1NSR/1NZ®, Arora®, Arora V®, GW2A/AR®, GOWIN EDA and other designated brands included herein are trademarks of GOWIN Semiconductor Corp. in China and other countries. All other trademarks are the property of their respective owners. For more information, please email info@gowinsemi.com Media Contact: Andrew Dudaronek andrew@gowinsemi.com

GOWIN Arora V Expansion website pic

GOWIN Semiconductor Corporation Expands its Arora V FPGA Family with Advanced Features San Jose, California and Guangzhou, China, November 1, 2023 - GOWIN Semiconductor Corporation, recognized as the world's fastest-growing FPGA company, is excited to announce an expansion of its Arora V high-performance FPGA family. The latest offering leverages cutting-edge 22nm SRAM technology, 12.5Gbps high-speed SerDes interfaces, PCIe hardcore, MIPI hardcore D-phy and C-phy support, RISC-V microprocessor, and DDR3 interfaces. The extended family now includes 15K, 45K, 60K, and 75K LUT device offerings. The new Arora V family not only complements the previous Arora family but also offers a significant performance boost with lower power consumption. Specifically, the Arora V devices exhibit 30% higher performance and a remarkable 60% reduction in power consumption compared to the Arora GW2A family. Arora-V programming configuration provides designers with a wide array of options including JTAG, SSPI, MSPI, CPU, and the ability to directly program external SPI Flash in JTAG or SSPI Mode. In addition, it allows for indirect programming of external Flash in other modes using a soft-core IP bridge and supports background upgrades, bitstream file encryption, and security bit settings. Arora V further distinguishes itself by delivering exceptional Single Event Upset (SEU) resiliency compared to competitors. GOWIN has adopted an innovative approach by designing custom SRAM cells, significantly reducing soft error rate effects. To make the handling of SEU-related matters more accessible, GOWIN provides a "SEU Handler" wrapper IP, which allows users to seamlessly access SEU reports and correction functions, enhancing both reliability and efficiency. The new Arora V family also incorporates an advanced I/O structure capable of recovering received serial data containing an embedded clock using built-in CDR technology at each differential I/O pair. This feature facilitates easy cascading of multiple GPIOs for achieving high data throughput, all without the need for a SERDES-based solution. Solutions such as Ethernet, Industrial Field Buses, and LVDS Bus Applications to name a few, can easily be implemented using EasyCDR. “We are excited to be offering our latest 22nm technology products for next-generation applications during our innovation phase of growth,” states Scott Casper, Director of Sales, GOWIN Semiconductor, “The improvement in performance and speed as well as the added feature of EasyCDR will take us into solutions not realized by previous families.” For more information about GOWIN, please visit www.gowinsemi.com About GOWIN Semiconductor Corp. Founded in 2014, Gowin Semiconductor Corp., headquartered with major R&D in China, has the vision to accelerate customer innovation worldwide with our programmable solutions. We focus on optimizing our products and removing barriers for customers using programmable logic devices. Our commitment to technology and quality enables customers to reduce the total cost of ownership from using FPGA on their production boards. Our offerings include a broad portfolio of programmable logic devices, design software, intellectual property (IP) cores, reference designs, and development kits. We strive to serve customers in the consumer, industrial, communication, medical, and automotive markets worldwide. Copyright 2023 GOWIN Semiconductor Corp. GOWIN, LittleBee®, GW1N/NR/NS/1NSR/1NZ®, Arora®, Arora V®, GW2A/AR®, GOWIN EDA and other designated brands included herein are trademarks of GOWIN Semiconductor Corp. in China and other countries. All other trademarks are the property of their respective owners. For more information, please email info@gowinsemi.com Media Contact: Andrew Dudaronek andrew@gowinsemi.com