Synthesis Messages

Report Title	GowinSynthesis Report
Design File	D:\Gowin\Gowin_V1.9.12.01_x64\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\picorv32.v D:\Gowin\Gowin_V1.9.12.01_x64\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\picosoc.v D:\Gowin\Gowin_V1.9.12.01_x64\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\advspi.v D:\Gowin\Gowin_V1.9.12.01_x64\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\ahb_bus.v D:\Gowin\Gowin_V1.9.12.01_x64\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\picosoc_dtcm.v D:\Gowin\Gowin_V1.9.12.01_x64\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\picosoc_itcm.v D:\Gowin\Gowin_V1.9.12.01_x64\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\wb_bus.v D:\Gowin\Gowin_V1.9.12.01_x64\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\wb_brancher.v D:\Gowin\Gowin_V1.9.12.01_x64\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\wbgpio.v D:\Gowin\Gowin_V1.9.12.01_x64\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\wbi2c.v D:\Gowin\Gowin_V1.9.12.01_x64\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\wbspi.v D:\Gowin\Gowin_V1.9.12.01_x64\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\wbuart.v D:\Gowin\Gowin_V1.9.12.01_x64\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\simpleuart.v D:\Gowin\Gowin_V1.9.12.01_x64\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\dm.v
GowinSynthesis Constraints File	---
Tool Version	V1.9.12.01 (64-bit)
Part Number	GW5AT-LV60UG225C2/I1
Device	GW5AT-60
Device Version	B
Created Time	Tue Feb 10 11:23:49 2026
Legal Announcement	Copyright (C)2014-2025 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module	Gowin_PicoRV32_Top
Synthesis Process	Running parser: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 135.391MB Running netlist conversion: CPU time = 0h 0m 0.14s, Elapsed time = 0h 0m 0.143s, Peak memory usage = 135.391MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0.984s, Elapsed time = 0h 0m 0.983s, Peak memory usage = 135.391MB Optimizing Phase 1: CPU time = 0h 0m 0.437s, Elapsed time = 0h 0m 0.429s, Peak memory usage = 135.391MB Optimizing Phase 2: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 135.391MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0.953s, Elapsed time = 0h 0m 0.973s, Peak memory usage = 135.391MB Inferring Phase 1: CPU time = 0h 0m 0.562s, Elapsed time = 0h 0m 0.583s, Peak memory usage = 135.391MB Inferring Phase 2: CPU time = 0h 0m 0.093s, Elapsed time = 0h 0m 0.09s, Peak memory usage = 135.391MB Inferring Phase 3: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.05s, Peak memory usage = 135.391MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 135.391MB Tech-Mapping Phase 1: CPU time = 0h 0m 0.562s, Elapsed time = 0h 0m 0.558s, Peak memory usage = 135.391MB Tech-Mapping Phase 2: CPU time = 0h 0m 0.562s, Elapsed time = 0h 0m 0.574s, Peak memory usage = 135.391MB Tech-Mapping Phase 3: CPU time = 0h 0m 25s, Elapsed time = 0h 0m 25s, Peak memory usage = 149.090MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.906s, Elapsed time = 0h 0m 1s, Peak memory usage = 149.090MB Generate output files: CPU time = 0h 0m 0.953s, Elapsed time = 0h 0m 1s, Peak memory usage = 200.875MB
Total Time and Memory Usage	CPU time = 0h 0m 34s, Elapsed time = 0h 0m 34s, Peak memory usage = 200.875MB

Resource

Resource Usage Summary

Resource	Usage
I/O Port	239
I/O Buf	237
IBUF	84
OBUF	147
TBUF	1
IOBUF	5
Register	4525
DFFSE	96
DFFRE	3059
DFFPE	17
DFFCE	1353
LUT	6681
LUT2	522
LUT3	2285
LUT4	3874
ALU	629
ALU	629
INV	23
INV	23
DSP
MULT27X36	2
BSRAM	64
SDPB	64

Resource Utilization Summary

Resource	Usage	Utilization
Logic	7333(6704 LUT, 629 ALU) / 59904	13%
Register	4525 / 60228	8%
--Register as Latch	0 / 60228	0%
--Register as FF	4525 / 60228	8%
BSRAM	64 / 118	55%

Timing

Clock Summary:

NO.	Clock Name	Type	Period	Frequency(MHz)	Fall	Object
1	clk_in	Base	10.000	100.000	5.000	clk_in_ibuf/I
2	jtag_TCK	Base	10.000	100.000	5.000	jtag_TCK_ibuf/I
3	u_dualportspi/u_atcspi/u_spi_spiif/n316_3	Base	10.000	100.000	5.000	u_dualportspi/u_atcspi/u_spi_spiif/n316_s0/F

Max Frequency Summary:

NO.	Clock Name	Constraint	Actual Fmax	Logic Level	Entity
1	clk_in	100.000(MHz)	65.608(MHz)	11	TOP
2	jtag_TCK	100.000(MHz)	124.875(MHz)	6	TOP

Detail Timing Paths Information

Path 1

Path Summary:

Slack	-2.621
Data Arrival Time	12.870
Data Required Time	10.249
From	rstdly_15_s0
To	core/mem_rdata_q_28_s0
Launch Clk	clk_in[R]
Latch Clk	clk_in[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
5.000	0.000				clk_in
5.000	0.000	tCL	FF	1	clk_in_ibuf/I
5.000	0.000	tINS	FF	4469	clk_in_ibuf/O
5.280	0.280	tNET	FF	1	rstdly_15_s0/CLK
5.627	0.347	tC2Q	FR	30	rstdly_15_s0/Q
5.927	0.300	tNET	RR	1	core/n7226_s2/I3
6.137	0.210	tINS	RR	2	core/n7226_s2/F
6.437	0.300	tNET	RR	1	core/n7226_s1/I1
6.850	0.413	tINS	RR	4	core/n7226_s1/F
7.150	0.300	tNET	RR	1	core/mem_rdata_latched_11_s4/I0
7.571	0.421	tINS	RR	29	core/mem_rdata_latched_11_s4/F
7.871	0.300	tNET	RR	1	core/mem_rdata_latched_4_s2/I1
8.284	0.413	tINS	RR	10	core/mem_rdata_latched_4_s2/F
8.584	0.300	tNET	RR	1	core/n2098_s5/I1
8.997	0.413	tINS	RR	10	core/n2098_s5/F
9.297	0.300	tNET	RR	1	core/n2078_s11/I1
9.710	0.413	tINS	RR	2	core/n2078_s11/F
10.010	0.300	tNET	RR	1	core/n2078_s4/I1
10.423	0.413	tINS	RR	6	core/n2078_s4/F
10.723	0.300	tNET	RR	1	core/n2078_s16/I0
11.144	0.421	tINS	RR	1	core/n2078_s16/F
11.444	0.300	tNET	RR	1	core/n2078_s2/I1
11.857	0.413	tINS	RR	1	core/n2078_s2/F
12.157	0.300	tNET	RR	1	core/n2078_s0/I1
12.570	0.413	tINS	RR	1	core/n2078_s0/F
12.870	0.300	tNET	RR	1	core/mem_rdata_q_28_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
10.000	0.000				clk_in
10.000	0.000	tCL	RR	1	clk_in_ibuf/I
10.000	0.000	tINS	RR	4469	clk_in_ibuf/O
10.300	0.300	tNET	RR	1	core/mem_rdata_q_28_s0/CLK
10.249	-0.051	tSu		1	core/mem_rdata_q_28_s0

Path Statistics:

Clock Skew:	0.020
Setup Relationship:	5.000
Logic Level:	11
Arrival Clock Path Delay:	cell: 0.000, 0.000%; route: 0.280, 100.000%
Arrival Data Path Delay:	cell: 3.943, 51.950%; route: 3.300, 43.478%; tC2Q: 0.347, 4.572%
Required Clock Path Delay:	cell: 0.000, 0.000%; route: 0.280, 100.000%

Path 2

Path Summary:

Slack	-2.593
Data Arrival Time	12.842
Data Required Time	10.249
From	rstdly_15_s0
To	core/mem_rdata_q_22_s0
Launch Clk	clk_in[R]
Latch Clk	clk_in[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
5.000	0.000				clk_in
5.000	0.000	tCL	FF	1	clk_in_ibuf/I
5.000	0.000	tINS	FF	4469	clk_in_ibuf/O
5.280	0.280	tNET	FF	1	rstdly_15_s0/CLK
5.627	0.347	tC2Q	FR	30	rstdly_15_s0/Q
5.927	0.300	tNET	RR	1	core/n7226_s2/I3
6.137	0.210	tINS	RR	2	core/n7226_s2/F
6.437	0.300	tNET	RR	1	core/n7226_s1/I1
6.850	0.413	tINS	RR	4	core/n7226_s1/F
7.150	0.300	tNET	RR	1	core/mem_rdata_latched_11_s4/I0
7.571	0.421	tINS	RR	29	core/mem_rdata_latched_11_s4/F
7.871	0.300	tNET	RR	1	core/mem_rdata_latched_4_s2/I1
8.284	0.413	tINS	RR	10	core/mem_rdata_latched_4_s2/F
8.584	0.300	tNET	RR	1	core/n2098_s5/I1
8.997	0.413	tINS	RR	10	core/n2098_s5/F
9.297	0.300	tNET	RR	1	core/n2078_s11/I1
9.710	0.413	tINS	RR	2	core/n2078_s11/F
10.010	0.300	tNET	RR	1	core/n5587_s9/I2
10.379	0.369	tINS	RR	10	core/n5587_s9/F
10.679	0.300	tNET	RR	1	core/n2084_s4/I0
11.100	0.421	tINS	RR	1	core/n2084_s4/F
11.400	0.300	tNET	RR	1	core/n2084_s1/I0
11.821	0.421	tINS	RR	1	core/n2084_s1/F
12.121	0.300	tNET	RR	1	core/n2084_s0/I0
12.542	0.421	tINS	RR	1	core/n2084_s0/F
12.842	0.300	tNET	RR	1	core/mem_rdata_q_22_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
10.000	0.000				clk_in
10.000	0.000	tCL	RR	1	clk_in_ibuf/I
10.000	0.000	tINS	RR	4469	clk_in_ibuf/O
10.300	0.300	tNET	RR	1	core/mem_rdata_q_22_s0/CLK
10.249	-0.051	tSu		1	core/mem_rdata_q_22_s0

Path Statistics:

Clock Skew:	0.020
Setup Relationship:	5.000
Logic Level:	11
Arrival Clock Path Delay:	cell: 0.000, 0.000%; route: 0.280, 100.000%
Arrival Data Path Delay:	cell: 3.915, 51.772%; route: 3.300, 43.639%; tC2Q: 0.347, 4.589%
Required Clock Path Delay:	cell: 0.000, 0.000%; route: 0.280, 100.000%

Path 3

Path Summary:

Slack	-2.585
Data Arrival Time	12.834
Data Required Time	10.249
From	rstdly_15_s0
To	core/mem_rdata_q_26_s0
Launch Clk	clk_in[R]
Latch Clk	clk_in[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
5.000	0.000				clk_in
5.000	0.000	tCL	FF	1	clk_in_ibuf/I
5.000	0.000	tINS	FF	4469	clk_in_ibuf/O
5.280	0.280	tNET	FF	1	rstdly_15_s0/CLK
5.627	0.347	tC2Q	FR	30	rstdly_15_s0/Q
5.927	0.300	tNET	RR	1	core/n7226_s2/I3
6.137	0.210	tINS	RR	2	core/n7226_s2/F
6.437	0.300	tNET	RR	1	core/n7226_s1/I1
6.850	0.413	tINS	RR	4	core/n7226_s1/F
7.150	0.300	tNET	RR	1	core/mem_rdata_latched_11_s4/I0
7.571	0.421	tINS	RR	29	core/mem_rdata_latched_11_s4/F
7.871	0.300	tNET	RR	1	core/mem_rdata_latched_4_s2/I1
8.284	0.413	tINS	RR	10	core/mem_rdata_latched_4_s2/F
8.584	0.300	tNET	RR	1	core/n2098_s5/I1
8.997	0.413	tINS	RR	10	core/n2098_s5/F
9.297	0.300	tNET	RR	1	core/n2078_s11/I1
9.710	0.413	tINS	RR	2	core/n2078_s11/F
10.010	0.300	tNET	RR	1	core/n2078_s4/I1
10.423	0.413	tINS	RR	6	core/n2078_s4/F
10.723	0.300	tNET	RR	1	core/n2080_s4/I0
11.144	0.421	tINS	RR	1	core/n2080_s4/F
11.444	0.300	tNET	RR	1	core/n2080_s2/I0
11.865	0.421	tINS	RR	1	core/n2080_s2/F
12.165	0.300	tNET	RR	1	core/n2080_s0/I2
12.534	0.369	tINS	RR	1	core/n2080_s0/F
12.834	0.300	tNET	RR	1	core/mem_rdata_q_26_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
10.000	0.000				clk_in
10.000	0.000	tCL	RR	1	clk_in_ibuf/I
10.000	0.000	tINS	RR	4469	clk_in_ibuf/O
10.300	0.300	tNET	RR	1	core/mem_rdata_q_26_s0/CLK
10.249	-0.051	tSu		1	core/mem_rdata_q_26_s0

Path Statistics:

Clock Skew:	0.020
Setup Relationship:	5.000
Logic Level:	11
Arrival Clock Path Delay:	cell: 0.000, 0.000%; route: 0.280, 100.000%
Arrival Data Path Delay:	cell: 3.907, 51.721%; route: 3.300, 43.685%; tC2Q: 0.347, 4.594%
Required Clock Path Delay:	cell: 0.000, 0.000%; route: 0.280, 100.000%

Path 4

Path Summary:

Slack	-2.577
Data Arrival Time	12.826
Data Required Time	10.249
From	rstdly_15_s0
To	core/mem_rdata_q_14_s0
Launch Clk	clk_in[R]
Latch Clk	clk_in[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
5.000	0.000				clk_in
5.000	0.000	tCL	FF	1	clk_in_ibuf/I
5.000	0.000	tINS	FF	4469	clk_in_ibuf/O
5.280	0.280	tNET	FF	1	rstdly_15_s0/CLK
5.627	0.347	tC2Q	FR	30	rstdly_15_s0/Q
5.927	0.300	tNET	RR	1	core/n7226_s2/I3
6.137	0.210	tINS	RR	2	core/n7226_s2/F
6.437	0.300	tNET	RR	1	core/n7226_s1/I1
6.850	0.413	tINS	RR	4	core/n7226_s1/F
7.150	0.300	tNET	RR	1	core/mem_rdata_latched_11_s4/I0
7.571	0.421	tINS	RR	29	core/mem_rdata_latched_11_s4/F
7.871	0.300	tNET	RR	1	core/mem_rdata_latched_4_s2/I1
8.284	0.413	tINS	RR	10	core/mem_rdata_latched_4_s2/F
8.584	0.300	tNET	RR	1	core/n2098_s5/I1
8.997	0.413	tINS	RR	10	core/n2098_s5/F
9.297	0.300	tNET	RR	1	core/n2078_s11/I1
9.710	0.413	tINS	RR	2	core/n2078_s11/F
10.010	0.300	tNET	RR	1	core/n5587_s9/I2
10.379	0.369	tINS	RR	10	core/n5587_s9/F
10.679	0.300	tNET	RR	1	core/n2092_s9/I0
11.100	0.421	tINS	RR	1	core/n2092_s9/F
11.400	0.300	tNET	RR	1	core/n2092_s2/I1
11.813	0.413	tINS	RR	1	core/n2092_s2/F
12.113	0.300	tNET	RR	1	core/n2092_s0/I1
12.526	0.413	tINS	RR	1	core/n2092_s0/F
12.826	0.300	tNET	RR	1	core/mem_rdata_q_14_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
10.000	0.000				clk_in
10.000	0.000	tCL	RR	1	clk_in_ibuf/I
10.000	0.000	tINS	RR	4469	clk_in_ibuf/O
10.300	0.300	tNET	RR	1	core/mem_rdata_q_14_s0/CLK
10.249	-0.051	tSu		1	core/mem_rdata_q_14_s0

Path Statistics:

Clock Skew:	0.020
Setup Relationship:	5.000
Logic Level:	11
Arrival Clock Path Delay:	cell: 0.000, 0.000%; route: 0.280, 100.000%
Arrival Data Path Delay:	cell: 3.899, 51.670%; route: 3.300, 43.732%; tC2Q: 0.347, 4.598%
Required Clock Path Delay:	cell: 0.000, 0.000%; route: 0.280, 100.000%

Path 5

Path Summary:

Slack	-2.577
Data Arrival Time	12.826
Data Required Time	10.249
From	rstdly_15_s0
To	core/mem_rdata_q_25_s0
Launch Clk	clk_in[R]
Latch Clk	clk_in[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
5.000	0.000				clk_in
5.000	0.000	tCL	FF	1	clk_in_ibuf/I
5.000	0.000	tINS	FF	4469	clk_in_ibuf/O
5.280	0.280	tNET	FF	1	rstdly_15_s0/CLK
5.627	0.347	tC2Q	FR	30	rstdly_15_s0/Q
5.927	0.300	tNET	RR	1	core/n7226_s2/I3
6.137	0.210	tINS	RR	2	core/n7226_s2/F
6.437	0.300	tNET	RR	1	core/n7226_s1/I1
6.850	0.413	tINS	RR	4	core/n7226_s1/F
7.150	0.300	tNET	RR	1	core/mem_rdata_latched_11_s4/I0
7.571	0.421	tINS	RR	29	core/mem_rdata_latched_11_s4/F
7.871	0.300	tNET	RR	1	core/mem_rdata_latched_4_s2/I1
8.284	0.413	tINS	RR	10	core/mem_rdata_latched_4_s2/F
8.584	0.300	tNET	RR	1	core/n2098_s5/I1
8.997	0.413	tINS	RR	10	core/n2098_s5/F
9.297	0.300	tNET	RR	1	core/n2078_s11/I1
9.710	0.413	tINS	RR	2	core/n2078_s11/F
10.010	0.300	tNET	RR	1	core/n2078_s4/I1
10.423	0.413	tINS	RR	6	core/n2078_s4/F
10.723	0.300	tNET	RR	1	core/n2081_s4/I1
11.136	0.413	tINS	RR	1	core/n2081_s4/F
11.436	0.300	tNET	RR	1	core/n2081_s2/I0
11.857	0.421	tINS	RR	1	core/n2081_s2/F
12.157	0.300	tNET	RR	1	core/n2081_s0/I2
12.526	0.369	tINS	RR	1	core/n2081_s0/F
12.826	0.300	tNET	RR	1	core/mem_rdata_q_25_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
10.000	0.000				clk_in
10.000	0.000	tCL	RR	1	clk_in_ibuf/I
10.000	0.000	tINS	RR	4469	clk_in_ibuf/O
10.300	0.300	tNET	RR	1	core/mem_rdata_q_25_s0/CLK
10.249	-0.051	tSu		1	core/mem_rdata_q_25_s0

Path Statistics:

Clock Skew:	0.020
Setup Relationship:	5.000
Logic Level:	11
Arrival Clock Path Delay:	cell: 0.000, 0.000%; route: 0.280, 100.000%
Arrival Data Path Delay:	cell: 3.899, 51.670%; route: 3.300, 43.732%; tC2Q: 0.347, 4.598%
Required Clock Path Delay:	cell: 0.000, 0.000%; route: 0.280, 100.000%