Timing Messages
Report Title | Gowin Timing Analysis Report |
Design File | D:\user-bak\gqg\Desktop\DK-START-GW1N4(4K)LED_blink_test\DK-START-GW1N4(4K)LED_blink_test\DK-START-GW1N4_LED_blink\impl\synthesize\rev_1\LED_test.vm |
Physical Constraints File | D:\user-bak\gqg\Desktop\DK-START-GW1N4(4K)LED_blink_test\DK-START-GW1N4(4K)LED_blink_test\DK-START-GW1N4_LED_blink\src\LED_test.cst |
Timing Constraint File | --- |
GOWIN version | V1.9.1Beta |
Part Number | GW1N-LV4LQ144C6/I5 |
Created Time | Tue Aug 06 11:24:15 2019 |
Legal Announcement | Copyright (C)2014-2019 Gowin Semiconductor Corporation. All rights reserved. |
Timing Summaries
STA Tool Run Summary:
Setup Delay Model | Slow 1.14V 85C |
Hold Delay Model | Fast 1.26V 0C |
Numbers of Paths Analyzed | 76 |
Numbers of Endpoints Analyzed | 47 |
Numbers of Falling Endpoints | 0 |
Numbers of Setup Violated Endpoints | 0 |
Numbers of Hold Violated Endpoints | 0 |
Clock Summary:
Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Objects |
---|---|---|---|---|---|---|---|---|
DEFAULT_CLK | Base | 10.000 | 100.000 | 0.000 | 5.000 |
Max Frequency Summary:
NO. | Clock Name | Fmax | Entity |
---|---|---|---|
1 | DEFAULT_CLK | 113.447(MHz) | TOP |
Total Negative Slack Summary:
Clock Name | Analysis Type | Endpoints TNS | Number of Endpoints |
---|---|---|---|
DEFAULT_CLK | Setup | 0.000 | 0 |
DEFAULT_CLK | Hold | 0.000 | 0 |
Timing Details
Path Slacks Table:
Setup Paths Table
Report Command:report_timing -setup -max_paths 25 -max_common_paths 1
Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
---|---|---|---|---|---|---|---|---|
1 | 1.185 | \clk_cnt_Z[12] /Q | \clk_cnt_Z[24] /RESET | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 8.571 |
2 | 1.185 | \clk_cnt_Z[12] /Q | \clk_cnt_Z[22] /RESET | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 8.571 |
3 | 1.185 | \clk_cnt_Z[12] /Q | \clk_cnt_Z[23] /RESET | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 8.571 |
4 | 1.185 | \clk_cnt_Z[12] /Q | \clk_cnt_Z[25] /RESET | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 8.571 |
5 | 1.262 | \clk_cnt_Z[12] /Q | \clk_cnt_Z[21] /RESET | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 8.494 |
6 | 1.262 | \clk_cnt_Z[12] /Q | \clk_cnt_Z[20] /RESET | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 8.494 |
7 | 1.262 | \clk_cnt_Z[12] /Q | \clk_cnt_Z[16] /RESET | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 8.494 |
8 | 1.262 | \clk_cnt_Z[12] /Q | \clk_cnt_Z[19] /RESET | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 8.494 |
9 | 1.262 | \clk_cnt_Z[12] /Q | \clk_cnt_Z[17] /RESET | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 8.494 |
10 | 1.262 | \clk_cnt_Z[12] /Q | \clk_cnt_Z[18] /RESET | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 8.494 |
11 | 1.265 | \clk_cnt_Z[18] /Q | \clk_cnt_Z[11] /D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 8.135 |
12 | 1.557 | \clk_cnt_Z[12] /Q | \clk_cnt_Z[15] /RESET | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 8.199 |
13 | 1.557 | \clk_cnt_Z[12] /Q | \clk_cnt_Z[14] /RESET | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 8.199 |
14 | 1.557 | \clk_cnt_Z[12] /Q | \clk_cnt_Z[13] /RESET | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 8.199 |
15 | 1.570 | \clk_cnt_Z[18] /Q | \clk_cnt_Z[3] /D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 7.830 |
16 | 1.570 | \clk_cnt_Z[18] /Q | \clk_cnt_Z[7] /D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 7.830 |
17 | 1.570 | \clk_cnt_Z[18] /Q | \clk_cnt_Z[8] /D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 7.830 |
18 | 1.570 | \clk_cnt_Z[18] /Q | \clk_cnt_Z[10] /D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 7.830 |
19 | 1.645 | \clk_cnt_Z[12] /Q | \clk_cnt_Z[6] /RESET | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 8.112 |
20 | 1.663 | \clk_cnt_Z[18] /Q | \clk_cnt_Z[12] /D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 7.737 |
21 | 1.732 | \clk_cnt_Z[2] /Q | \clk_cnt_Z[4] /D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 7.668 |
22 | 1.753 | \clk_cnt_Z[2] /Q | \led_1[0] /D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 7.647 |
23 | 1.942 | \clk_cnt_Z[2] /Q | \clk_cnt_Z[5] /D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 7.458 |
24 | 2.015 | \clk_cnt_Z[2] /Q | \clk_cnt_Z[1] /D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 7.385 |
25 | 2.015 | \clk_cnt_Z[2] /Q | \clk_cnt_Z[9] /D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 7.385 |
Hold Paths Table
Report Command:report_timing -hold -max_paths 25 -max_common_paths 1
Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
---|---|---|---|---|---|---|---|---|
1 | 0.709 | \led_1[0] /Q | \led_1[0] /D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.709 |
2 | 0.853 | \clk_cnt_Z[25] /Q | \clk_cnt_Z[25] /D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.853 |
3 | 0.853 | \clk_cnt_Z[23] /Q | \clk_cnt_Z[23] /D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.853 |
4 | 0.853 | \clk_cnt_Z[19] /Q | \clk_cnt_Z[19] /D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.853 |
5 | 0.853 | \clk_cnt_Z[17] /Q | \clk_cnt_Z[17] /D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.853 |
6 | 0.853 | \clk_cnt_Z[13] /Q | \clk_cnt_Z[13] /D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.853 |
7 | 1.085 | \clk_cnt_Z[15] /Q | \clk_cnt_Z[15] /D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 1.085 |
8 | 1.088 | \clk_cnt_Z[20] /Q | \clk_cnt_Z[20] /D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 1.088 |
9 | 1.088 | \clk_cnt_Z[6] /Q | \clk_cnt_Z[6] /D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 1.088 |
10 | 1.088 | \clk_cnt_Z[14] /Q | \clk_cnt_Z[14] /D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 1.088 |
11 | 1.089 | \clk_cnt_Z[22] /Q | \clk_cnt_Z[22] /D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 1.089 |
12 | 1.089 | \clk_cnt_Z[16] /Q | \clk_cnt_Z[16] /D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 1.089 |
13 | 1.090 | \clk_cnt_Z[24] /Q | \clk_cnt_Z[24] /D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 1.090 |
14 | 1.095 | \clk_cnt_Z[18] /Q | \clk_cnt_Z[18] /D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 1.095 |
15 | 1.115 | \clk_cnt_Z[21] /Q | \clk_cnt_Z[21] /D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 1.115 |
16 | 1.938 | \clk_cnt_Z[16] /Q | \clk_cnt_Z[11] /D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 1.938 |
17 | 1.938 | \clk_cnt_Z[16] /Q | \clk_cnt_Z[12] /D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 1.938 |
18 | 1.962 | \clk_cnt_Z[16] /Q | \clk_cnt_Z[2] /D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 1.962 |
19 | 2.080 | \clk_cnt_Z[4] /Q | \clk_cnt_Z[4] /D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 2.080 |
20 | 2.090 | \clk_cnt_Z[23] /Q | \clk_cnt_Z[5] /D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 2.090 |
21 | 2.146 | \clk_cnt_Z[16] /Q | \clk_cnt_Z[0] /D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 2.146 |
22 | 2.211 | \clk_cnt_Z[16] /Q | \led_1[0] /CE | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 2.226 |
23 | 2.264 | \clk_cnt_Z[10] /Q | \clk_cnt_Z[10] /D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 2.264 |
24 | 2.274 | \clk_cnt_Z[23] /Q | \clk_cnt_Z[9] /D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 2.274 |
25 | 2.342 | \clk_cnt_Z[16] /Q | \clk_cnt_Z[3] /D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 2.342 |
Recovery Paths Table
Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1
Nothing to report!
Removal Paths Table
Report Command:report_timing -removal -max_paths 25 -max_common_paths 1
Nothing to report!
Minimum Pulse Width Table:
Number | Slack | Actual Width | Required Width | Type | Clock | Objects |
---|---|---|---|---|---|---|
1 | 2.329 | 3.579 | 1.250 | Low Pulse Width | DEFAULT_CLK | \clk_cnt_Z[12] |
2 | 2.329 | 3.579 | 1.250 | Low Pulse Width | DEFAULT_CLK | \clk_cnt_Z[10] |
3 | 2.329 | 3.579 | 1.250 | Low Pulse Width | DEFAULT_CLK | \clk_cnt_Z[5] |
4 | 2.329 | 3.579 | 1.250 | Low Pulse Width | DEFAULT_CLK | \clk_cnt_Z[14] |
5 | 2.329 | 3.579 | 1.250 | Low Pulse Width | DEFAULT_CLK | \clk_cnt_Z[13] |
6 | 2.329 | 3.579 | 1.250 | Low Pulse Width | DEFAULT_CLK | \clk_cnt_Z[7] |
7 | 2.329 | 3.579 | 1.250 | Low Pulse Width | DEFAULT_CLK | \clk_cnt_Z[6] |
8 | 2.329 | 3.579 | 1.250 | Low Pulse Width | DEFAULT_CLK | \led_1[0] |
9 | 2.329 | 3.579 | 1.250 | Low Pulse Width | DEFAULT_CLK | \clk_cnt_Z[25] |
10 | 2.329 | 3.579 | 1.250 | Low Pulse Width | DEFAULT_CLK | \clk_cnt_Z[0] |
Timing Report By Analysis Type:
Setup Analysis Report
Report Command:report_timing -setup -max_paths 25 -max_common_paths 1
Path1
Path Summary:
Slack | 1.185 |
Data Arrival Time | 12.941 |
Data Required Time | 14.126 |
From | \clk_cnt_Z[12] |
To | \clk_cnt_Z[24] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL3[B] | clk_ibuf/I |
0.982 | 0.982 | tINS | RR | 27 | IOL3[B] | clk_ibuf/O |
4.370 | 3.388 | tNET | RR | 1 | R11C11[2][A] | \clk_cnt_Z[12] /CLK |
4.828 | 0.458 | tC2Q | RF | 3 | R11C11[2][A] | \clk_cnt_Z[12] /Q |
6.152 | 1.324 | tNET | FF | 1 | R9C10[3][A] | un1_clk_cntlto15_2/I0 |
7.184 | 1.032 | tINS | FF | 3 | R9C10[3][A] | un1_clk_cntlto15_2/F |
8.482 | 1.298 | tNET | FF | 1 | R11C11[3][A] | clk_cnt11_0_m1_e_sx_cZ/I0 |
9.514 | 1.032 | tINS | FF | 8 | R11C11[3][A] | clk_cnt11_0_m1_e_sx_cZ/F |
10.366 | 0.853 | tNET | FF | 1 | R11C9[1][B] | clk_cnt11_0_m1_e/I1 |
11.392 | 1.026 | tINS | FR | 14 | R11C9[1][B] | clk_cnt11_0_m1_e/F |
12.941 | 1.549 | tNET | RR | 1 | R9C12[1][A] | \clk_cnt_Z[24] /RESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||||
10.000 | 0.000 | tCL | RR | 1 | IOL3[B] | clk_ibuf/I |
10.982 | 0.982 | tINS | RR | 27 | IOL3[B] | clk_ibuf/O |
14.370 | 3.388 | tNET | RR | 1 | R9C12[1][A] | \clk_cnt_Z[24] /CLK |
14.170 | -0.200 | tUnc | \clk_cnt_Z[24] | |||
14.126 | -0.043 | tSu | 1 | R9C12[1][A] | \clk_cnt_Z[24] |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 3 |
Arrival Clock Path Delay | cell: 0.982, 22.470%; route: 3.388, 77.530% |
Arrival Data Path Delay | cell: 3.090, 36.050%; route: 5.023, 58.602%; tC2Q: 0.458, 5.347% |
Required Clock Path Delay | cell: 0.982, 22.470%; route: 3.388, 77.530% |
Path2
Path Summary:
Slack | 1.185 |
Data Arrival Time | 12.941 |
Data Required Time | 14.126 |
From | \clk_cnt_Z[12] |
To | \clk_cnt_Z[22] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL3[B] | clk_ibuf/I |
0.982 | 0.982 | tINS | RR | 27 | IOL3[B] | clk_ibuf/O |
4.370 | 3.388 | tNET | RR | 1 | R11C11[2][A] | \clk_cnt_Z[12] /CLK |
4.828 | 0.458 | tC2Q | RF | 3 | R11C11[2][A] | \clk_cnt_Z[12] /Q |
6.152 | 1.324 | tNET | FF | 1 | R9C10[3][A] | un1_clk_cntlto15_2/I0 |
7.184 | 1.032 | tINS | FF | 3 | R9C10[3][A] | un1_clk_cntlto15_2/F |
8.482 | 1.298 | tNET | FF | 1 | R11C11[3][A] | clk_cnt11_0_m1_e_sx_cZ/I0 |
9.514 | 1.032 | tINS | FF | 8 | R11C11[3][A] | clk_cnt11_0_m1_e_sx_cZ/F |
10.366 | 0.853 | tNET | FF | 1 | R11C9[1][B] | clk_cnt11_0_m1_e/I1 |
11.392 | 1.026 | tINS | FR | 14 | R11C9[1][B] | clk_cnt11_0_m1_e/F |
12.941 | 1.549 | tNET | RR | 1 | R9C12[0][A] | \clk_cnt_Z[22] /RESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||||
10.000 | 0.000 | tCL | RR | 1 | IOL3[B] | clk_ibuf/I |
10.982 | 0.982 | tINS | RR | 27 | IOL3[B] | clk_ibuf/O |
14.370 | 3.388 | tNET | RR | 1 | R9C12[0][A] | \clk_cnt_Z[22] /CLK |
14.170 | -0.200 | tUnc | \clk_cnt_Z[22] | |||
14.126 | -0.043 | tSu | 1 | R9C12[0][A] | \clk_cnt_Z[22] |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 3 |
Arrival Clock Path Delay | cell: 0.982, 22.470%; route: 3.388, 77.530% |
Arrival Data Path Delay | cell: 3.090, 36.050%; route: 5.023, 58.602%; tC2Q: 0.458, 5.347% |
Required Clock Path Delay | cell: 0.982, 22.470%; route: 3.388, 77.530% |
Path3
Path Summary:
Slack | 1.185 |
Data Arrival Time | 12.941 |
Data Required Time | 14.126 |
From | \clk_cnt_Z[12] |
To | \clk_cnt_Z[23] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL3[B] | clk_ibuf/I |
0.982 | 0.982 | tINS | RR | 27 | IOL3[B] | clk_ibuf/O |
4.370 | 3.388 | tNET | RR | 1 | R11C11[2][A] | \clk_cnt_Z[12] /CLK |
4.828 | 0.458 | tC2Q | RF | 3 | R11C11[2][A] | \clk_cnt_Z[12] /Q |
6.152 | 1.324 | tNET | FF | 1 | R9C10[3][A] | un1_clk_cntlto15_2/I0 |
7.184 | 1.032 | tINS | FF | 3 | R9C10[3][A] | un1_clk_cntlto15_2/F |
8.482 | 1.298 | tNET | FF | 1 | R11C11[3][A] | clk_cnt11_0_m1_e_sx_cZ/I0 |
9.514 | 1.032 | tINS | FF | 8 | R11C11[3][A] | clk_cnt11_0_m1_e_sx_cZ/F |
10.366 | 0.853 | tNET | FF | 1 | R11C9[1][B] | clk_cnt11_0_m1_e/I1 |
11.392 | 1.026 | tINS | FR | 14 | R11C9[1][B] | clk_cnt11_0_m1_e/F |
12.941 | 1.549 | tNET | RR | 1 | R9C12[0][B] | \clk_cnt_Z[23] /RESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||||
10.000 | 0.000 | tCL | RR | 1 | IOL3[B] | clk_ibuf/I |
10.982 | 0.982 | tINS | RR | 27 | IOL3[B] | clk_ibuf/O |
14.370 | 3.388 | tNET | RR | 1 | R9C12[0][B] | \clk_cnt_Z[23] /CLK |
14.170 | -0.200 | tUnc | \clk_cnt_Z[23] | |||
14.126 | -0.043 | tSu | 1 | R9C12[0][B] | \clk_cnt_Z[23] |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 3 |
Arrival Clock Path Delay | cell: 0.982, 22.470%; route: 3.388, 77.530% |
Arrival Data Path Delay | cell: 3.090, 36.050%; route: 5.023, 58.602%; tC2Q: 0.458, 5.347% |
Required Clock Path Delay | cell: 0.982, 22.470%; route: 3.388, 77.530% |
Path4
Path Summary:
Slack | 1.185 |
Data Arrival Time | 12.941 |
Data Required Time | 14.126 |
From | \clk_cnt_Z[12] |
To | \clk_cnt_Z[25] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL3[B] | clk_ibuf/I |
0.982 | 0.982 | tINS | RR | 27 | IOL3[B] | clk_ibuf/O |
4.370 | 3.388 | tNET | RR | 1 | R11C11[2][A] | \clk_cnt_Z[12] /CLK |
4.828 | 0.458 | tC2Q | RF | 3 | R11C11[2][A] | \clk_cnt_Z[12] /Q |
6.152 | 1.324 | tNET | FF | 1 | R9C10[3][A] | un1_clk_cntlto15_2/I0 |
7.184 | 1.032 | tINS | FF | 3 | R9C10[3][A] | un1_clk_cntlto15_2/F |
8.482 | 1.298 | tNET | FF | 1 | R11C11[3][A] | clk_cnt11_0_m1_e_sx_cZ/I0 |
9.514 | 1.032 | tINS | FF | 8 | R11C11[3][A] | clk_cnt11_0_m1_e_sx_cZ/F |
10.366 | 0.853 | tNET | FF | 1 | R11C9[1][B] | clk_cnt11_0_m1_e/I1 |
11.392 | 1.026 | tINS | FR | 14 | R11C9[1][B] | clk_cnt11_0_m1_e/F |
12.941 | 1.549 | tNET | RR | 1 | R9C12[1][B] | \clk_cnt_Z[25] /RESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||||
10.000 | 0.000 | tCL | RR | 1 | IOL3[B] | clk_ibuf/I |
10.982 | 0.982 | tINS | RR | 27 | IOL3[B] | clk_ibuf/O |
14.370 | 3.388 | tNET | RR | 1 | R9C12[1][B] | \clk_cnt_Z[25] /CLK |
14.170 | -0.200 | tUnc | \clk_cnt_Z[25] | |||
14.126 | -0.043 | tSu | 1 | R9C12[1][B] | \clk_cnt_Z[25] |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 3 |
Arrival Clock Path Delay | cell: 0.982, 22.470%; route: 3.388, 77.530% |
Arrival Data Path Delay | cell: 3.090, 36.050%; route: 5.023, 58.602%; tC2Q: 0.458, 5.347% |
Required Clock Path Delay | cell: 0.982, 22.470%; route: 3.388, 77.530% |
Path5
Path Summary:
Slack | 1.262 |
Data Arrival Time | 12.864 |
Data Required Time | 14.126 |
From | \clk_cnt_Z[12] |
To | \clk_cnt_Z[21] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL3[B] | clk_ibuf/I |
0.982 | 0.982 | tINS | RR | 27 | IOL3[B] | clk_ibuf/O |
4.370 | 3.388 | tNET | RR | 1 | R11C11[2][A] | \clk_cnt_Z[12] /CLK |
4.828 | 0.458 | tC2Q | RF | 3 | R11C11[2][A] | \clk_cnt_Z[12] /Q |
6.152 | 1.324 | tNET | FF | 1 | R9C10[3][A] | un1_clk_cntlto15_2/I0 |
7.184 | 1.032 | tINS | FF | 3 | R9C10[3][A] | un1_clk_cntlto15_2/F |
8.482 | 1.298 | tNET | FF | 1 | R11C11[3][A] | clk_cnt11_0_m1_e_sx_cZ/I0 |
9.514 | 1.032 | tINS | FF | 8 | R11C11[3][A] | clk_cnt11_0_m1_e_sx_cZ/F |
10.366 | 0.853 | tNET | FF | 1 | R11C9[1][B] | clk_cnt11_0_m1_e/I1 |
11.392 | 1.026 | tINS | FR | 14 | R11C9[1][B] | clk_cnt11_0_m1_e/F |
12.864 | 1.472 | tNET | RR | 1 | R9C11[2][B] | \clk_cnt_Z[21] /RESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||||
10.000 | 0.000 | tCL | RR | 1 | IOL3[B] | clk_ibuf/I |
10.982 | 0.982 | tINS | RR | 27 | IOL3[B] | clk_ibuf/O |
14.370 | 3.388 | tNET | RR | 1 | R9C11[2][B] | \clk_cnt_Z[21] /CLK |
14.170 | -0.200 | tUnc | \clk_cnt_Z[21] | |||
14.126 | -0.043 | tSu | 1 | R9C11[2][B] | \clk_cnt_Z[21] |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 3 |
Arrival Clock Path Delay | cell: 0.982, 22.470%; route: 3.388, 77.530% |
Arrival Data Path Delay | cell: 3.090, 36.377%; route: 4.946, 58.227%; tC2Q: 0.458, 5.396% |
Required Clock Path Delay | cell: 0.982, 22.470%; route: 3.388, 77.530% |
Path6
Path Summary:
Slack | 1.262 |
Data Arrival Time | 12.864 |
Data Required Time | 14.126 |
From | \clk_cnt_Z[12] |
To | \clk_cnt_Z[20] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL3[B] | clk_ibuf/I |
0.982 | 0.982 | tINS | RR | 27 | IOL3[B] | clk_ibuf/O |
4.370 | 3.388 | tNET | RR | 1 | R11C11[2][A] | \clk_cnt_Z[12] /CLK |
4.828 | 0.458 | tC2Q | RF | 3 | R11C11[2][A] | \clk_cnt_Z[12] /Q |
6.152 | 1.324 | tNET | FF | 1 | R9C10[3][A] | un1_clk_cntlto15_2/I0 |
7.184 | 1.032 | tINS | FF | 3 | R9C10[3][A] | un1_clk_cntlto15_2/F |
8.482 | 1.298 | tNET | FF | 1 | R11C11[3][A] | clk_cnt11_0_m1_e_sx_cZ/I0 |
9.514 | 1.032 | tINS | FF | 8 | R11C11[3][A] | clk_cnt11_0_m1_e_sx_cZ/F |
10.366 | 0.853 | tNET | FF | 1 | R11C9[1][B] | clk_cnt11_0_m1_e/I1 |
11.392 | 1.026 | tINS | FR | 14 | R11C9[1][B] | clk_cnt11_0_m1_e/F |
12.864 | 1.472 | tNET | RR | 1 | R9C11[2][A] | \clk_cnt_Z[20] /RESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||||
10.000 | 0.000 | tCL | RR | 1 | IOL3[B] | clk_ibuf/I |
10.982 | 0.982 | tINS | RR | 27 | IOL3[B] | clk_ibuf/O |
14.370 | 3.388 | tNET | RR | 1 | R9C11[2][A] | \clk_cnt_Z[20] /CLK |
14.170 | -0.200 | tUnc | \clk_cnt_Z[20] | |||
14.126 | -0.043 | tSu | 1 | R9C11[2][A] | \clk_cnt_Z[20] |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 3 |
Arrival Clock Path Delay | cell: 0.982, 22.470%; route: 3.388, 77.530% |
Arrival Data Path Delay | cell: 3.090, 36.377%; route: 4.946, 58.227%; tC2Q: 0.458, 5.396% |
Required Clock Path Delay | cell: 0.982, 22.470%; route: 3.388, 77.530% |
Path7
Path Summary:
Slack | 1.262 |
Data Arrival Time | 12.864 |
Data Required Time | 14.126 |
From | \clk_cnt_Z[12] |
To | \clk_cnt_Z[16] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL3[B] | clk_ibuf/I |
0.982 | 0.982 | tINS | RR | 27 | IOL3[B] | clk_ibuf/O |
4.370 | 3.388 | tNET | RR | 1 | R11C11[2][A] | \clk_cnt_Z[12] /CLK |
4.828 | 0.458 | tC2Q | RF | 3 | R11C11[2][A] | \clk_cnt_Z[12] /Q |
6.152 | 1.324 | tNET | FF | 1 | R9C10[3][A] | un1_clk_cntlto15_2/I0 |
7.184 | 1.032 | tINS | FF | 3 | R9C10[3][A] | un1_clk_cntlto15_2/F |
8.482 | 1.298 | tNET | FF | 1 | R11C11[3][A] | clk_cnt11_0_m1_e_sx_cZ/I0 |
9.514 | 1.032 | tINS | FF | 8 | R11C11[3][A] | clk_cnt11_0_m1_e_sx_cZ/F |
10.366 | 0.853 | tNET | FF | 1 | R11C9[1][B] | clk_cnt11_0_m1_e/I1 |
11.392 | 1.026 | tINS | FR | 14 | R11C9[1][B] | clk_cnt11_0_m1_e/F |
12.864 | 1.472 | tNET | RR | 1 | R9C11[0][A] | \clk_cnt_Z[16] /RESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||||
10.000 | 0.000 | tCL | RR | 1 | IOL3[B] | clk_ibuf/I |
10.982 | 0.982 | tINS | RR | 27 | IOL3[B] | clk_ibuf/O |
14.370 | 3.388 | tNET | RR | 1 | R9C11[0][A] | \clk_cnt_Z[16] /CLK |
14.170 | -0.200 | tUnc | \clk_cnt_Z[16] | |||
14.126 | -0.043 | tSu | 1 | R9C11[0][A] | \clk_cnt_Z[16] |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 3 |
Arrival Clock Path Delay | cell: 0.982, 22.470%; route: 3.388, 77.530% |
Arrival Data Path Delay | cell: 3.090, 36.377%; route: 4.946, 58.227%; tC2Q: 0.458, 5.396% |
Required Clock Path Delay | cell: 0.982, 22.470%; route: 3.388, 77.530% |
Path8
Path Summary:
Slack | 1.262 |
Data Arrival Time | 12.864 |
Data Required Time | 14.126 |
From | \clk_cnt_Z[12] |
To | \clk_cnt_Z[19] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL3[B] | clk_ibuf/I |
0.982 | 0.982 | tINS | RR | 27 | IOL3[B] | clk_ibuf/O |
4.370 | 3.388 | tNET | RR | 1 | R11C11[2][A] | \clk_cnt_Z[12] /CLK |
4.828 | 0.458 | tC2Q | RF | 3 | R11C11[2][A] | \clk_cnt_Z[12] /Q |
6.152 | 1.324 | tNET | FF | 1 | R9C10[3][A] | un1_clk_cntlto15_2/I0 |
7.184 | 1.032 | tINS | FF | 3 | R9C10[3][A] | un1_clk_cntlto15_2/F |
8.482 | 1.298 | tNET | FF | 1 | R11C11[3][A] | clk_cnt11_0_m1_e_sx_cZ/I0 |
9.514 | 1.032 | tINS | FF | 8 | R11C11[3][A] | clk_cnt11_0_m1_e_sx_cZ/F |
10.366 | 0.853 | tNET | FF | 1 | R11C9[1][B] | clk_cnt11_0_m1_e/I1 |
11.392 | 1.026 | tINS | FR | 14 | R11C9[1][B] | clk_cnt11_0_m1_e/F |
12.864 | 1.472 | tNET | RR | 1 | R9C11[1][B] | \clk_cnt_Z[19] /RESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||||
10.000 | 0.000 | tCL | RR | 1 | IOL3[B] | clk_ibuf/I |
10.982 | 0.982 | tINS | RR | 27 | IOL3[B] | clk_ibuf/O |
14.370 | 3.388 | tNET | RR | 1 | R9C11[1][B] | \clk_cnt_Z[19] /CLK |
14.170 | -0.200 | tUnc | \clk_cnt_Z[19] | |||
14.126 | -0.043 | tSu | 1 | R9C11[1][B] | \clk_cnt_Z[19] |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 3 |
Arrival Clock Path Delay | cell: 0.982, 22.470%; route: 3.388, 77.530% |
Arrival Data Path Delay | cell: 3.090, 36.377%; route: 4.946, 58.227%; tC2Q: 0.458, 5.396% |
Required Clock Path Delay | cell: 0.982, 22.470%; route: 3.388, 77.530% |
Path9
Path Summary:
Slack | 1.262 |
Data Arrival Time | 12.864 |
Data Required Time | 14.126 |
From | \clk_cnt_Z[12] |
To | \clk_cnt_Z[17] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL3[B] | clk_ibuf/I |
0.982 | 0.982 | tINS | RR | 27 | IOL3[B] | clk_ibuf/O |
4.370 | 3.388 | tNET | RR | 1 | R11C11[2][A] | \clk_cnt_Z[12] /CLK |
4.828 | 0.458 | tC2Q | RF | 3 | R11C11[2][A] | \clk_cnt_Z[12] /Q |
6.152 | 1.324 | tNET | FF | 1 | R9C10[3][A] | un1_clk_cntlto15_2/I0 |
7.184 | 1.032 | tINS | FF | 3 | R9C10[3][A] | un1_clk_cntlto15_2/F |
8.482 | 1.298 | tNET | FF | 1 | R11C11[3][A] | clk_cnt11_0_m1_e_sx_cZ/I0 |
9.514 | 1.032 | tINS | FF | 8 | R11C11[3][A] | clk_cnt11_0_m1_e_sx_cZ/F |
10.366 | 0.853 | tNET | FF | 1 | R11C9[1][B] | clk_cnt11_0_m1_e/I1 |
11.392 | 1.026 | tINS | FR | 14 | R11C9[1][B] | clk_cnt11_0_m1_e/F |
12.864 | 1.472 | tNET | RR | 1 | R9C11[0][B] | \clk_cnt_Z[17] /RESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||||
10.000 | 0.000 | tCL | RR | 1 | IOL3[B] | clk_ibuf/I |
10.982 | 0.982 | tINS | RR | 27 | IOL3[B] | clk_ibuf/O |
14.370 | 3.388 | tNET | RR | 1 | R9C11[0][B] | \clk_cnt_Z[17] /CLK |
14.170 | -0.200 | tUnc | \clk_cnt_Z[17] | |||
14.126 | -0.043 | tSu | 1 | R9C11[0][B] | \clk_cnt_Z[17] |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 3 |
Arrival Clock Path Delay | cell: 0.982, 22.470%; route: 3.388, 77.530% |
Arrival Data Path Delay | cell: 3.090, 36.377%; route: 4.946, 58.227%; tC2Q: 0.458, 5.396% |
Required Clock Path Delay | cell: 0.982, 22.470%; route: 3.388, 77.530% |
Path10
Path Summary:
Slack | 1.262 |
Data Arrival Time | 12.864 |
Data Required Time | 14.126 |
From | \clk_cnt_Z[12] |
To | \clk_cnt_Z[18] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL3[B] | clk_ibuf/I |
0.982 | 0.982 | tINS | RR | 27 | IOL3[B] | clk_ibuf/O |
4.370 | 3.388 | tNET | RR | 1 | R11C11[2][A] | \clk_cnt_Z[12] /CLK |
4.828 | 0.458 | tC2Q | RF | 3 | R11C11[2][A] | \clk_cnt_Z[12] /Q |
6.152 | 1.324 | tNET | FF | 1 | R9C10[3][A] | un1_clk_cntlto15_2/I0 |
7.184 | 1.032 | tINS | FF | 3 | R9C10[3][A] | un1_clk_cntlto15_2/F |
8.482 | 1.298 | tNET | FF | 1 | R11C11[3][A] | clk_cnt11_0_m1_e_sx_cZ/I0 |
9.514 | 1.032 | tINS | FF | 8 | R11C11[3][A] | clk_cnt11_0_m1_e_sx_cZ/F |
10.366 | 0.853 | tNET | FF | 1 | R11C9[1][B] | clk_cnt11_0_m1_e/I1 |
11.392 | 1.026 | tINS | FR | 14 | R11C9[1][B] | clk_cnt11_0_m1_e/F |
12.864 | 1.472 | tNET | RR | 1 | R9C11[1][A] | \clk_cnt_Z[18] /RESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||||
10.000 | 0.000 | tCL | RR | 1 | IOL3[B] | clk_ibuf/I |
10.982 | 0.982 | tINS | RR | 27 | IOL3[B] | clk_ibuf/O |
14.370 | 3.388 | tNET | RR | 1 | R9C11[1][A] | \clk_cnt_Z[18] /CLK |
14.170 | -0.200 | tUnc | \clk_cnt_Z[18] | |||
14.126 | -0.043 | tSu | 1 | R9C11[1][A] | \clk_cnt_Z[18] |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 3 |
Arrival Clock Path Delay | cell: 0.982, 22.470%; route: 3.388, 77.530% |
Arrival Data Path Delay | cell: 3.090, 36.377%; route: 4.946, 58.227%; tC2Q: 0.458, 5.396% |
Required Clock Path Delay | cell: 0.982, 22.470%; route: 3.388, 77.530% |
Path11
Path Summary:
Slack | 1.265 |
Data Arrival Time | 12.505 |
Data Required Time | 13.770 |
From | \clk_cnt_Z[18] |
To | \clk_cnt_Z[11] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL3[B] | clk_ibuf/I |
0.982 | 0.982 | tINS | RR | 27 | IOL3[B] | clk_ibuf/O |
4.370 | 3.388 | tNET | RR | 1 | R9C11[1][A] | \clk_cnt_Z[18] /CLK |
4.828 | 0.458 | tC2Q | RF | 5 | R9C11[1][A] | \clk_cnt_Z[18] /Q |
5.639 | 0.811 | tNET | FF | 1 | R11C10[3][A] | clk_cnt11_0tt_m2_0_a2_3_N_2L1_cZ/I3 |
6.671 | 1.032 | tINS | FF | 1 | R11C10[3][A] | clk_cnt11_0tt_m2_0_a2_3_N_2L1_cZ/F |
7.476 | 0.804 | tNET | FF | 1 | R11C13[1][A] | clk_cnt11_0tt_m2_0_a2_3_cZ/S0 |
7.913 | 0.437 | tINS | FF | 8 | R11C13[1][A] | clk_cnt11_0tt_m2_0_a2_3_cZ/O |
10.064 | 2.152 | tNET | FF | 1 | R11C13[2][B] | \clk_cntd_1[3] /S0 |
10.566 | 0.502 | tINS | FF | 6 | R11C13[2][B] | \clk_cntd_1[3] /O |
11.406 | 0.840 | tNET | FF | 1 | R11C11[1][B] | \clk_cntd[11] /I3 |
12.505 | 1.099 | tINS | FF | 1 | R11C11[1][B] | \clk_cntd[11] /F |
12.505 | 0.000 | tNET | FF | 1 | R11C11[1][B] | \clk_cnt_Z[11] /D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||||
10.000 | 0.000 | tCL | RR | 1 | IOL3[B] | clk_ibuf/I |
10.982 | 0.982 | tINS | RR | 27 | IOL3[B] | clk_ibuf/O |
14.370 | 3.388 | tNET | RR | 1 | R11C11[1][B] | \clk_cnt_Z[11] /CLK |
14.170 | -0.200 | tUnc | \clk_cnt_Z[11] | |||
13.770 | -0.400 | tSu | 1 | R11C11[1][B] | \clk_cnt_Z[11] |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 4 |
Arrival Clock Path Delay | cell: 0.982, 22.470%; route: 3.388, 77.530% |
Arrival Data Path Delay | cell: 3.070, 37.738%; route: 4.607, 56.628%; tC2Q: 0.458, 5.634% |
Required Clock Path Delay | cell: 0.982, 22.470%; route: 3.388, 77.530% |
Path12
Path Summary:
Slack | 1.557 |
Data Arrival Time | 12.569 |
Data Required Time | 14.126 |
From | \clk_cnt_Z[12] |
To | \clk_cnt_Z[15] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL3[B] | clk_ibuf/I |
0.982 | 0.982 | tINS | RR | 27 | IOL3[B] | clk_ibuf/O |
4.370 | 3.388 | tNET | RR | 1 | R11C11[2][A] | \clk_cnt_Z[12] /CLK |
4.828 | 0.458 | tC2Q | RF | 3 | R11C11[2][A] | \clk_cnt_Z[12] /Q |
6.152 | 1.324 | tNET | FF | 1 | R9C10[3][A] | un1_clk_cntlto15_2/I0 |
7.184 | 1.032 | tINS | FF | 3 | R9C10[3][A] | un1_clk_cntlto15_2/F |
8.482 | 1.298 | tNET | FF | 1 | R11C11[3][A] | clk_cnt11_0_m1_e_sx_cZ/I0 |
9.514 | 1.032 | tINS | FF | 8 | R11C11[3][A] | clk_cnt11_0_m1_e_sx_cZ/F |
10.366 | 0.853 | tNET | FF | 1 | R11C9[1][B] | clk_cnt11_0_m1_e/I1 |
11.392 | 1.026 | tINS | FR | 14 | R11C9[1][B] | clk_cnt11_0_m1_e/F |
12.569 | 1.177 | tNET | RR | 1 | R9C10[2][B] | \clk_cnt_Z[15] /RESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||||
10.000 | 0.000 | tCL | RR | 1 | IOL3[B] | clk_ibuf/I |
10.982 | 0.982 | tINS | RR | 27 | IOL3[B] | clk_ibuf/O |
14.370 | 3.388 | tNET | RR | 1 | R9C10[2][B] | \clk_cnt_Z[15] /CLK |
14.170 | -0.200 | tUnc | \clk_cnt_Z[15] | |||
14.126 | -0.043 | tSu | 1 | R9C10[2][B] | \clk_cnt_Z[15] |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 3 |
Arrival Clock Path Delay | cell: 0.982, 22.470%; route: 3.388, 77.530% |
Arrival Data Path Delay | cell: 3.090, 37.687%; route: 4.651, 56.723%; tC2Q: 0.458, 5.590% |
Required Clock Path Delay | cell: 0.982, 22.470%; route: 3.388, 77.530% |
Path13
Path Summary:
Slack | 1.557 |
Data Arrival Time | 12.569 |
Data Required Time | 14.126 |
From | \clk_cnt_Z[12] |
To | \clk_cnt_Z[14] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL3[B] | clk_ibuf/I |
0.982 | 0.982 | tINS | RR | 27 | IOL3[B] | clk_ibuf/O |
4.370 | 3.388 | tNET | RR | 1 | R11C11[2][A] | \clk_cnt_Z[12] /CLK |
4.828 | 0.458 | tC2Q | RF | 3 | R11C11[2][A] | \clk_cnt_Z[12] /Q |
6.152 | 1.324 | tNET | FF | 1 | R9C10[3][A] | un1_clk_cntlto15_2/I0 |
7.184 | 1.032 | tINS | FF | 3 | R9C10[3][A] | un1_clk_cntlto15_2/F |
8.482 | 1.298 | tNET | FF | 1 | R11C11[3][A] | clk_cnt11_0_m1_e_sx_cZ/I0 |
9.514 | 1.032 | tINS | FF | 8 | R11C11[3][A] | clk_cnt11_0_m1_e_sx_cZ/F |
10.366 | 0.853 | tNET | FF | 1 | R11C9[1][B] | clk_cnt11_0_m1_e/I1 |
11.392 | 1.026 | tINS | FR | 14 | R11C9[1][B] | clk_cnt11_0_m1_e/F |
12.569 | 1.177 | tNET | RR | 1 | R9C10[2][A] | \clk_cnt_Z[14] /RESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||||
10.000 | 0.000 | tCL | RR | 1 | IOL3[B] | clk_ibuf/I |
10.982 | 0.982 | tINS | RR | 27 | IOL3[B] | clk_ibuf/O |
14.370 | 3.388 | tNET | RR | 1 | R9C10[2][A] | \clk_cnt_Z[14] /CLK |
14.170 | -0.200 | tUnc | \clk_cnt_Z[14] | |||
14.126 | -0.043 | tSu | 1 | R9C10[2][A] | \clk_cnt_Z[14] |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 3 |
Arrival Clock Path Delay | cell: 0.982, 22.470%; route: 3.388, 77.530% |
Arrival Data Path Delay | cell: 3.090, 37.687%; route: 4.651, 56.723%; tC2Q: 0.458, 5.590% |
Required Clock Path Delay | cell: 0.982, 22.470%; route: 3.388, 77.530% |
Path14
Path Summary:
Slack | 1.557 |
Data Arrival Time | 12.569 |
Data Required Time | 14.126 |
From | \clk_cnt_Z[12] |
To | \clk_cnt_Z[13] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL3[B] | clk_ibuf/I |
0.982 | 0.982 | tINS | RR | 27 | IOL3[B] | clk_ibuf/O |
4.370 | 3.388 | tNET | RR | 1 | R11C11[2][A] | \clk_cnt_Z[12] /CLK |
4.828 | 0.458 | tC2Q | RF | 3 | R11C11[2][A] | \clk_cnt_Z[12] /Q |
6.152 | 1.324 | tNET | FF | 1 | R9C10[3][A] | un1_clk_cntlto15_2/I0 |
7.184 | 1.032 | tINS | FF | 3 | R9C10[3][A] | un1_clk_cntlto15_2/F |
8.482 | 1.298 | tNET | FF | 1 | R11C11[3][A] | clk_cnt11_0_m1_e_sx_cZ/I0 |
9.514 | 1.032 | tINS | FF | 8 | R11C11[3][A] | clk_cnt11_0_m1_e_sx_cZ/F |
10.366 | 0.853 | tNET | FF | 1 | R11C9[1][B] | clk_cnt11_0_m1_e/I1 |
11.392 | 1.026 | tINS | FR | 14 | R11C9[1][B] | clk_cnt11_0_m1_e/F |
12.569 | 1.177 | tNET | RR | 1 | R9C10[1][B] | \clk_cnt_Z[13] /RESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||||
10.000 | 0.000 | tCL | RR | 1 | IOL3[B] | clk_ibuf/I |
10.982 | 0.982 | tINS | RR | 27 | IOL3[B] | clk_ibuf/O |
14.370 | 3.388 | tNET | RR | 1 | R9C10[1][B] | \clk_cnt_Z[13] /CLK |
14.170 | -0.200 | tUnc | \clk_cnt_Z[13] | |||
14.126 | -0.043 | tSu | 1 | R9C10[1][B] | \clk_cnt_Z[13] |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 3 |
Arrival Clock Path Delay | cell: 0.982, 22.470%; route: 3.388, 77.530% |
Arrival Data Path Delay | cell: 3.090, 37.687%; route: 4.651, 56.723%; tC2Q: 0.458, 5.590% |
Required Clock Path Delay | cell: 0.982, 22.470%; route: 3.388, 77.530% |
Path15
Path Summary:
Slack | 1.570 |
Data Arrival Time | 12.199 |
Data Required Time | 13.770 |
From | \clk_cnt_Z[18] |
To | \clk_cnt_Z[3] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL3[B] | clk_ibuf/I |
0.982 | 0.982 | tINS | RR | 27 | IOL3[B] | clk_ibuf/O |
4.370 | 3.388 | tNET | RR | 1 | R9C11[1][A] | \clk_cnt_Z[18] /CLK |
4.828 | 0.458 | tC2Q | RF | 5 | R9C11[1][A] | \clk_cnt_Z[18] /Q |
5.639 | 0.811 | tNET | FF | 1 | R11C10[3][A] | clk_cnt11_0tt_m2_0_a2_3_N_2L1_cZ/I3 |
6.671 | 1.032 | tINS | FF | 1 | R11C10[3][A] | clk_cnt11_0tt_m2_0_a2_3_N_2L1_cZ/F |
7.476 | 0.804 | tNET | FF | 1 | R11C13[1][A] | clk_cnt11_0tt_m2_0_a2_3_cZ/S0 |
7.913 | 0.437 | tINS | FF | 8 | R11C13[1][A] | clk_cnt11_0tt_m2_0_a2_3_cZ/O |
10.064 | 2.152 | tNET | FF | 1 | R11C13[2][B] | \clk_cntd_1[3] /S0 |
10.566 | 0.502 | tINS | FF | 6 | R11C13[2][B] | \clk_cntd_1[3] /O |
11.573 | 1.007 | tNET | FF | 1 | R11C10[1][A] | \clk_cntd[3] /I3 |
12.199 | 0.626 | tINS | FF | 1 | R11C10[1][A] | \clk_cntd[3] /F |
12.199 | 0.000 | tNET | FF | 1 | R11C10[1][A] | \clk_cnt_Z[3] /D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||||
10.000 | 0.000 | tCL | RR | 1 | IOL3[B] | clk_ibuf/I |
10.982 | 0.982 | tINS | RR | 27 | IOL3[B] | clk_ibuf/O |
14.370 | 3.388 | tNET | RR | 1 | R11C10[1][A] | \clk_cnt_Z[3] /CLK |
14.170 | -0.200 | tUnc | \clk_cnt_Z[3] | |||
13.770 | -0.400 | tSu | 1 | R11C10[1][A] | \clk_cnt_Z[3] |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 4 |
Arrival Clock Path Delay | cell: 0.982, 22.470%; route: 3.388, 77.530% |
Arrival Data Path Delay | cell: 2.597, 33.169%; route: 4.774, 60.977%; tC2Q: 0.458, 5.854% |
Required Clock Path Delay | cell: 0.982, 22.470%; route: 3.388, 77.530% |
Path16
Path Summary:
Slack | 1.570 |
Data Arrival Time | 12.199 |
Data Required Time | 13.770 |
From | \clk_cnt_Z[18] |
To | \clk_cnt_Z[7] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL3[B] | clk_ibuf/I |
0.982 | 0.982 | tINS | RR | 27 | IOL3[B] | clk_ibuf/O |
4.370 | 3.388 | tNET | RR | 1 | R9C11[1][A] | \clk_cnt_Z[18] /CLK |
4.828 | 0.458 | tC2Q | RF | 5 | R9C11[1][A] | \clk_cnt_Z[18] /Q |
5.639 | 0.811 | tNET | FF | 1 | R11C10[3][A] | clk_cnt11_0tt_m2_0_a2_3_N_2L1_cZ/I3 |
6.671 | 1.032 | tINS | FF | 1 | R11C10[3][A] | clk_cnt11_0tt_m2_0_a2_3_N_2L1_cZ/F |
7.476 | 0.804 | tNET | FF | 1 | R11C13[1][A] | clk_cnt11_0tt_m2_0_a2_3_cZ/S0 |
7.913 | 0.437 | tINS | FF | 8 | R11C13[1][A] | clk_cnt11_0tt_m2_0_a2_3_cZ/O |
10.064 | 2.152 | tNET | FF | 1 | R11C13[2][B] | \clk_cntd_1[3] /S0 |
10.566 | 0.502 | tINS | FF | 6 | R11C13[2][B] | \clk_cntd_1[3] /O |
11.573 | 1.007 | tNET | FF | 1 | R11C10[1][B] | \clk_cntd[7] /I3 |
12.199 | 0.626 | tINS | FF | 1 | R11C10[1][B] | \clk_cntd[7] /F |
12.199 | 0.000 | tNET | FF | 1 | R11C10[1][B] | \clk_cnt_Z[7] /D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||||
10.000 | 0.000 | tCL | RR | 1 | IOL3[B] | clk_ibuf/I |
10.982 | 0.982 | tINS | RR | 27 | IOL3[B] | clk_ibuf/O |
14.370 | 3.388 | tNET | RR | 1 | R11C10[1][B] | \clk_cnt_Z[7] /CLK |
14.170 | -0.200 | tUnc | \clk_cnt_Z[7] | |||
13.770 | -0.400 | tSu | 1 | R11C10[1][B] | \clk_cnt_Z[7] |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 4 |
Arrival Clock Path Delay | cell: 0.982, 22.470%; route: 3.388, 77.530% |
Arrival Data Path Delay | cell: 2.597, 33.169%; route: 4.774, 60.977%; tC2Q: 0.458, 5.854% |
Required Clock Path Delay | cell: 0.982, 22.470%; route: 3.388, 77.530% |
Path17
Path Summary:
Slack | 1.570 |
Data Arrival Time | 12.199 |
Data Required Time | 13.770 |
From | \clk_cnt_Z[18] |
To | \clk_cnt_Z[8] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL3[B] | clk_ibuf/I |
0.982 | 0.982 | tINS | RR | 27 | IOL3[B] | clk_ibuf/O |
4.370 | 3.388 | tNET | RR | 1 | R9C11[1][A] | \clk_cnt_Z[18] /CLK |
4.828 | 0.458 | tC2Q | RF | 5 | R9C11[1][A] | \clk_cnt_Z[18] /Q |
5.639 | 0.811 | tNET | FF | 1 | R11C10[3][A] | clk_cnt11_0tt_m2_0_a2_3_N_2L1_cZ/I3 |
6.671 | 1.032 | tINS | FF | 1 | R11C10[3][A] | clk_cnt11_0tt_m2_0_a2_3_N_2L1_cZ/F |
7.476 | 0.804 | tNET | FF | 1 | R11C13[1][A] | clk_cnt11_0tt_m2_0_a2_3_cZ/S0 |
7.913 | 0.437 | tINS | FF | 8 | R11C13[1][A] | clk_cnt11_0tt_m2_0_a2_3_cZ/O |
10.064 | 2.152 | tNET | FF | 1 | R11C13[2][B] | \clk_cntd_1[3] /S0 |
10.566 | 0.502 | tINS | FF | 6 | R11C13[2][B] | \clk_cntd_1[3] /O |
11.573 | 1.007 | tNET | FF | 1 | R11C10[2][A] | \clk_cntd[8] /I3 |
12.199 | 0.626 | tINS | FF | 1 | R11C10[2][A] | \clk_cntd[8] /F |
12.199 | 0.000 | tNET | FF | 1 | R11C10[2][A] | \clk_cnt_Z[8] /D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||||
10.000 | 0.000 | tCL | RR | 1 | IOL3[B] | clk_ibuf/I |
10.982 | 0.982 | tINS | RR | 27 | IOL3[B] | clk_ibuf/O |
14.370 | 3.388 | tNET | RR | 1 | R11C10[2][A] | \clk_cnt_Z[8] /CLK |
14.170 | -0.200 | tUnc | \clk_cnt_Z[8] | |||
13.770 | -0.400 | tSu | 1 | R11C10[2][A] | \clk_cnt_Z[8] |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 4 |
Arrival Clock Path Delay | cell: 0.982, 22.470%; route: 3.388, 77.530% |
Arrival Data Path Delay | cell: 2.597, 33.169%; route: 4.774, 60.977%; tC2Q: 0.458, 5.854% |
Required Clock Path Delay | cell: 0.982, 22.470%; route: 3.388, 77.530% |
Path18
Path Summary:
Slack | 1.570 |
Data Arrival Time | 12.199 |
Data Required Time | 13.770 |
From | \clk_cnt_Z[18] |
To | \clk_cnt_Z[10] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL3[B] | clk_ibuf/I |
0.982 | 0.982 | tINS | RR | 27 | IOL3[B] | clk_ibuf/O |
4.370 | 3.388 | tNET | RR | 1 | R9C11[1][A] | \clk_cnt_Z[18] /CLK |
4.828 | 0.458 | tC2Q | RF | 5 | R9C11[1][A] | \clk_cnt_Z[18] /Q |
5.639 | 0.811 | tNET | FF | 1 | R11C10[3][A] | clk_cnt11_0tt_m2_0_a2_3_N_2L1_cZ/I3 |
6.671 | 1.032 | tINS | FF | 1 | R11C10[3][A] | clk_cnt11_0tt_m2_0_a2_3_N_2L1_cZ/F |
7.476 | 0.804 | tNET | FF | 1 | R11C13[1][A] | clk_cnt11_0tt_m2_0_a2_3_cZ/S0 |
7.913 | 0.437 | tINS | FF | 8 | R11C13[1][A] | clk_cnt11_0tt_m2_0_a2_3_cZ/O |
10.064 | 2.152 | tNET | FF | 1 | R11C13[2][B] | \clk_cntd_1[3] /S0 |
10.566 | 0.502 | tINS | FF | 6 | R11C13[2][B] | \clk_cntd_1[3] /O |
11.573 | 1.007 | tNET | FF | 1 | R11C10[2][B] | \clk_cntd[10] /I3 |
12.199 | 0.626 | tINS | FF | 1 | R11C10[2][B] | \clk_cntd[10] /F |
12.199 | 0.000 | tNET | FF | 1 | R11C10[2][B] | \clk_cnt_Z[10] /D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||||
10.000 | 0.000 | tCL | RR | 1 | IOL3[B] | clk_ibuf/I |
10.982 | 0.982 | tINS | RR | 27 | IOL3[B] | clk_ibuf/O |
14.370 | 3.388 | tNET | RR | 1 | R11C10[2][B] | \clk_cnt_Z[10] /CLK |
14.170 | -0.200 | tUnc | \clk_cnt_Z[10] | |||
13.770 | -0.400 | tSu | 1 | R11C10[2][B] | \clk_cnt_Z[10] |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 4 |
Arrival Clock Path Delay | cell: 0.982, 22.470%; route: 3.388, 77.530% |
Arrival Data Path Delay | cell: 2.597, 33.169%; route: 4.774, 60.977%; tC2Q: 0.458, 5.854% |
Required Clock Path Delay | cell: 0.982, 22.470%; route: 3.388, 77.530% |
Path19
Path Summary:
Slack | 1.645 |
Data Arrival Time | 12.482 |
Data Required Time | 14.126 |
From | \clk_cnt_Z[12] |
To | \clk_cnt_Z[6] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL3[B] | clk_ibuf/I |
0.982 | 0.982 | tINS | RR | 27 | IOL3[B] | clk_ibuf/O |
4.370 | 3.388 | tNET | RR | 1 | R11C11[2][A] | \clk_cnt_Z[12] /CLK |
4.828 | 0.458 | tC2Q | RF | 3 | R11C11[2][A] | \clk_cnt_Z[12] /Q |
6.152 | 1.324 | tNET | FF | 1 | R9C10[3][A] | un1_clk_cntlto15_2/I0 |
7.184 | 1.032 | tINS | FF | 3 | R9C10[3][A] | un1_clk_cntlto15_2/F |
8.482 | 1.298 | tNET | FF | 1 | R11C11[3][A] | clk_cnt11_0_m1_e_sx_cZ/I0 |
9.514 | 1.032 | tINS | FF | 8 | R11C11[3][A] | clk_cnt11_0_m1_e_sx_cZ/F |
10.366 | 0.853 | tNET | FF | 1 | R11C9[1][B] | clk_cnt11_0_m1_e/I1 |
11.392 | 1.026 | tINS | FR | 14 | R11C9[1][B] | clk_cnt11_0_m1_e/F |
12.482 | 1.089 | tNET | RR | 1 | R9C9[1][A] | \clk_cnt_Z[6] /RESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||||
10.000 | 0.000 | tCL | RR | 1 | IOL3[B] | clk_ibuf/I |
10.982 | 0.982 | tINS | RR | 27 | IOL3[B] | clk_ibuf/O |
14.370 | 3.388 | tNET | RR | 1 | R9C9[1][A] | \clk_cnt_Z[6] /CLK |
14.170 | -0.200 | tUnc | \clk_cnt_Z[6] | |||
14.126 | -0.043 | tSu | 1 | R9C9[1][A] | \clk_cnt_Z[6] |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 3 |
Arrival Clock Path Delay | cell: 0.982, 22.470%; route: 3.388, 77.530% |
Arrival Data Path Delay | cell: 3.090, 38.092%; route: 4.564, 56.258%; tC2Q: 0.458, 5.650% |
Required Clock Path Delay | cell: 0.982, 22.470%; route: 3.388, 77.530% |
Path20
Path Summary:
Slack | 1.663 |
Data Arrival Time | 12.107 |
Data Required Time | 13.770 |
From | \clk_cnt_Z[18] |
To | \clk_cnt_Z[12] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL3[B] | clk_ibuf/I |
0.982 | 0.982 | tINS | RR | 27 | IOL3[B] | clk_ibuf/O |
4.370 | 3.388 | tNET | RR | 1 | R9C11[1][A] | \clk_cnt_Z[18] /CLK |
4.828 | 0.458 | tC2Q | RF | 5 | R9C11[1][A] | \clk_cnt_Z[18] /Q |
5.639 | 0.811 | tNET | FF | 1 | R11C10[3][A] | clk_cnt11_0tt_m2_0_a2_3_N_2L1_cZ/I3 |
6.671 | 1.032 | tINS | FF | 1 | R11C10[3][A] | clk_cnt11_0tt_m2_0_a2_3_N_2L1_cZ/F |
7.476 | 0.804 | tNET | FF | 1 | R11C13[1][A] | clk_cnt11_0tt_m2_0_a2_3_cZ/S0 |
7.913 | 0.437 | tINS | FF | 8 | R11C13[1][A] | clk_cnt11_0tt_m2_0_a2_3_cZ/O |
10.064 | 2.152 | tNET | FF | 1 | R11C13[2][B] | \clk_cntd_1[3] /S0 |
10.566 | 0.502 | tINS | FF | 6 | R11C13[2][B] | \clk_cntd_1[3] /O |
11.075 | 0.509 | tNET | FF | 1 | R11C11[2][A] | \clk_cntd[12] /I3 |
12.107 | 1.032 | tINS | FF | 1 | R11C11[2][A] | \clk_cntd[12] /F |
12.107 | 0.000 | tNET | FF | 1 | R11C11[2][A] | \clk_cnt_Z[12] /D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||||
10.000 | 0.000 | tCL | RR | 1 | IOL3[B] | clk_ibuf/I |
10.982 | 0.982 | tINS | RR | 27 | IOL3[B] | clk_ibuf/O |
14.370 | 3.388 | tNET | RR | 1 | R11C11[2][A] | \clk_cnt_Z[12] /CLK |
14.170 | -0.200 | tUnc | \clk_cnt_Z[12] | |||
13.770 | -0.400 | tSu | 1 | R11C11[2][A] | \clk_cnt_Z[12] |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 4 |
Arrival Clock Path Delay | cell: 0.982, 22.470%; route: 3.388, 77.530% |
Arrival Data Path Delay | cell: 3.003, 38.812%; route: 4.276, 55.264%; tC2Q: 0.458, 5.924% |
Required Clock Path Delay | cell: 0.982, 22.470%; route: 3.388, 77.530% |
Path21
Path Summary:
Slack | 1.732 |
Data Arrival Time | 12.038 |
Data Required Time | 13.770 |
From | \clk_cnt_Z[2] |
To | \clk_cnt_Z[4] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL3[B] | clk_ibuf/I |
0.982 | 0.982 | tINS | RR | 27 | IOL3[B] | clk_ibuf/O |
4.370 | 3.388 | tNET | RR | 1 | R11C10[0][B] | \clk_cnt_Z[2] /CLK |
4.828 | 0.458 | tC2Q | RF | 2 | R11C10[0][B] | \clk_cnt_Z[2] /Q |
6.120 | 1.292 | tNET | FF | 1 | R9C9[3][A] | un1_clk_cntlto6_4_cZ/I0 |
7.152 | 1.032 | tINS | FF | 9 | R9C9[3][A] | un1_clk_cntlto6_4_cZ/F |
8.452 | 1.300 | tNET | FF | 1 | R11C12[1][A] | clk_cnt11_0tt_m1_e_cZ/S0 |
8.889 | 0.437 | tINS | FF | 6 | R11C12[1][A] | clk_cnt11_0tt_m1_e_cZ/O |
9.902 | 1.013 | tNET | FF | 1 | R11C9[2][B] | clk_cntd_N_2L1_0/I0 |
11.001 | 1.099 | tINS | FF | 1 | R11C9[2][B] | clk_cntd_N_2L1_0/F |
11.006 | 0.005 | tNET | FF | 1 | R11C9[0][B] | \clk_cntd[4] /I3 |
12.038 | 1.032 | tINS | FF | 1 | R11C9[0][B] | \clk_cntd[4] /F |
12.038 | 0.000 | tNET | FF | 1 | R11C9[0][B] | \clk_cnt_Z[4] /D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||||
10.000 | 0.000 | tCL | RR | 1 | IOL3[B] | clk_ibuf/I |
10.982 | 0.982 | tINS | RR | 27 | IOL3[B] | clk_ibuf/O |
14.370 | 3.388 | tNET | RR | 1 | R11C9[0][B] | \clk_cnt_Z[4] /CLK |
14.170 | -0.200 | tUnc | \clk_cnt_Z[4] | |||
13.770 | -0.400 | tSu | 1 | R11C9[0][B] | \clk_cnt_Z[4] |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 4 |
Arrival Clock Path Delay | cell: 0.982, 22.470%; route: 3.388, 77.530% |
Arrival Data Path Delay | cell: 3.600, 46.946%; route: 3.610, 47.077%; tC2Q: 0.458, 5.977% |
Required Clock Path Delay | cell: 0.982, 22.470%; route: 3.388, 77.530% |
Path22
Path Summary:
Slack | 1.753 |
Data Arrival Time | 12.017 |
Data Required Time | 13.770 |
From | \clk_cnt_Z[2] |
To | \led_1[0] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL3[B] | clk_ibuf/I |
0.982 | 0.982 | tINS | RR | 27 | IOL3[B] | clk_ibuf/O |
4.370 | 3.388 | tNET | RR | 1 | R11C10[0][B] | \clk_cnt_Z[2] /CLK |
4.828 | 0.458 | tC2Q | RF | 2 | R11C10[0][B] | \clk_cnt_Z[2] /Q |
6.120 | 1.292 | tNET | FF | 1 | R9C9[3][A] | un1_clk_cntlto6_4_cZ/I0 |
7.152 | 1.032 | tINS | FF | 9 | R9C9[3][A] | un1_clk_cntlto6_4_cZ/F |
8.452 | 1.300 | tNET | FF | 1 | R11C12[1][A] | clk_cnt11_0tt_m1_e_cZ/S0 |
8.924 | 0.472 | tINS | FR | 6 | R11C12[1][A] | clk_cnt11_0tt_m1_e_cZ/O |
9.358 | 0.435 | tNET | RR | 1 | R11C12[0][A] | led_1e_N_3L3/I0 |
10.390 | 1.032 | tINS | RF | 1 | R11C12[0][A] | led_1e_N_3L3/F |
11.195 | 0.804 | tNET | FF | 1 | R12C13[0][A] | \led_1e[0] /I1 |
12.017 | 0.822 | tINS | FF | 1 | R12C13[0][A] | \led_1e[0] /F |
12.017 | 0.000 | tNET | FF | 1 | R12C13[0][A] | \led_1[0] /D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||||
10.000 | 0.000 | tCL | RR | 1 | IOL3[B] | clk_ibuf/I |
10.982 | 0.982 | tINS | RR | 27 | IOL3[B] | clk_ibuf/O |
14.370 | 3.388 | tNET | RR | 1 | R12C13[0][A] | \led_1[0] /CLK |
14.170 | -0.200 | tUnc | \led_1[0] | |||
13.770 | -0.400 | tSu | 1 | R12C13[0][A] | \led_1[0] |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 4 |
Arrival Clock Path Delay | cell: 0.982, 22.470%; route: 3.388, 77.530% |
Arrival Data Path Delay | cell: 3.358, 43.913%; route: 3.831, 50.094%; tC2Q: 0.458, 5.994% |
Required Clock Path Delay | cell: 0.982, 22.470%; route: 3.388, 77.530% |
Path23
Path Summary:
Slack | 1.942 |
Data Arrival Time | 11.828 |
Data Required Time | 13.770 |
From | \clk_cnt_Z[2] |
To | \clk_cnt_Z[5] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL3[B] | clk_ibuf/I |
0.982 | 0.982 | tINS | RR | 27 | IOL3[B] | clk_ibuf/O |
4.370 | 3.388 | tNET | RR | 1 | R11C10[0][B] | \clk_cnt_Z[2] /CLK |
4.828 | 0.458 | tC2Q | RF | 2 | R11C10[0][B] | \clk_cnt_Z[2] /Q |
6.120 | 1.292 | tNET | FF | 1 | R9C9[3][A] | un1_clk_cntlto6_4_cZ/I0 |
7.152 | 1.032 | tINS | FF | 9 | R9C9[3][A] | un1_clk_cntlto6_4_cZ/F |
8.452 | 1.300 | tNET | FF | 1 | R11C12[1][A] | clk_cnt11_0tt_m1_e_cZ/S0 |
8.889 | 0.437 | tINS | FF | 6 | R11C12[1][A] | clk_cnt11_0tt_m1_e_cZ/O |
9.902 | 1.013 | tNET | FF | 1 | R11C9[3][A] | clk_cntd_N_2L1/I0 |
11.001 | 1.099 | tINS | FF | 1 | R11C9[3][A] | clk_cntd_N_2L1/F |
11.006 | 0.005 | tNET | FF | 1 | R11C9[1][A] | \clk_cntd[5] /I3 |
11.828 | 0.822 | tINS | FF | 1 | R11C9[1][A] | \clk_cntd[5] /F |
11.828 | 0.000 | tNET | FF | 1 | R11C9[1][A] | \clk_cnt_Z[5] /D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||||
10.000 | 0.000 | tCL | RR | 1 | IOL3[B] | clk_ibuf/I |
10.982 | 0.982 | tINS | RR | 27 | IOL3[B] | clk_ibuf/O |
14.370 | 3.388 | tNET | RR | 1 | R11C9[1][A] | \clk_cnt_Z[5] /CLK |
14.170 | -0.200 | tUnc | \clk_cnt_Z[5] | |||
13.770 | -0.400 | tSu | 1 | R11C9[1][A] | \clk_cnt_Z[5] |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 4 |
Arrival Clock Path Delay | cell: 0.982, 22.470%; route: 3.388, 77.530% |
Arrival Data Path Delay | cell: 3.390, 45.452%; route: 3.610, 48.402%; tC2Q: 0.458, 6.145% |
Required Clock Path Delay | cell: 0.982, 22.470%; route: 3.388, 77.530% |
Path24
Path Summary:
Slack | 2.015 |
Data Arrival Time | 11.755 |
Data Required Time | 13.770 |
From | \clk_cnt_Z[2] |
To | \clk_cnt_Z[1] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL3[B] | clk_ibuf/I |
0.982 | 0.982 | tINS | RR | 27 | IOL3[B] | clk_ibuf/O |
4.370 | 3.388 | tNET | RR | 1 | R11C10[0][B] | \clk_cnt_Z[2] /CLK |
4.828 | 0.458 | tC2Q | RF | 2 | R11C10[0][B] | \clk_cnt_Z[2] /Q |
6.120 | 1.292 | tNET | FF | 1 | R9C9[3][A] | un1_clk_cntlto6_4_cZ/I0 |
7.152 | 1.032 | tINS | FF | 9 | R9C9[3][A] | un1_clk_cntlto6_4_cZ/F |
8.465 | 1.314 | tNET | FF | 1 | R11C12[3][B] | clk_cntd_N_2L1_1_0_1_cZ/I3 |
9.497 | 1.032 | tINS | FF | 1 | R11C12[3][B] | clk_cntd_N_2L1_1_0_1_cZ/F |
9.497 | 0.000 | tNET | FF | 1 | R11C12[3][A] | clk_cntd_N_2L1_1_0_cZ/I1 |
9.646 | 0.149 | tINS | FF | 1 | R11C12[3][A] | clk_cntd_N_2L1_1_0_cZ/O |
9.646 | 0.000 | tNET | FF | 1 | R11C12[2][B] | clk_cntd_N_2L1_1/I0 |
9.809 | 0.163 | tINS | FF | 2 | R11C12[2][B] | clk_cntd_N_2L1_1/O |
11.129 | 1.320 | tNET | FF | 1 | R11C9[0][A] | \clk_cntd[1] /I3 |
11.755 | 0.626 | tINS | FF | 1 | R11C9[0][A] | \clk_cntd[1] /F |
11.755 | 0.000 | tNET | FF | 1 | R11C9[0][A] | \clk_cnt_Z[1] /D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||||
10.000 | 0.000 | tCL | RR | 1 | IOL3[B] | clk_ibuf/I |
10.982 | 0.982 | tINS | RR | 27 | IOL3[B] | clk_ibuf/O |
14.370 | 3.388 | tNET | RR | 1 | R11C9[0][A] | \clk_cnt_Z[1] /CLK |
14.170 | -0.200 | tUnc | \clk_cnt_Z[1] | |||
13.770 | -0.400 | tSu | 1 | R11C9[0][A] | \clk_cnt_Z[1] |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 0.982, 22.470%; route: 3.388, 77.530% |
Arrival Data Path Delay | cell: 3.002, 40.649%; route: 3.925, 53.144%; tC2Q: 0.458, 6.206% |
Required Clock Path Delay | cell: 0.982, 22.470%; route: 3.388, 77.530% |
Path25
Path Summary:
Slack | 2.015 |
Data Arrival Time | 11.755 |
Data Required Time | 13.770 |
From | \clk_cnt_Z[2] |
To | \clk_cnt_Z[9] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL3[B] | clk_ibuf/I |
0.982 | 0.982 | tINS | RR | 27 | IOL3[B] | clk_ibuf/O |
4.370 | 3.388 | tNET | RR | 1 | R11C10[0][B] | \clk_cnt_Z[2] /CLK |
4.828 | 0.458 | tC2Q | RF | 2 | R11C10[0][B] | \clk_cnt_Z[2] /Q |
6.120 | 1.292 | tNET | FF | 1 | R9C9[3][A] | un1_clk_cntlto6_4_cZ/I0 |
7.152 | 1.032 | tINS | FF | 9 | R9C9[3][A] | un1_clk_cntlto6_4_cZ/F |
8.465 | 1.314 | tNET | FF | 1 | R11C12[3][A] | clk_cntd_N_2L1_1_0_0_cZ/I3 |
9.497 | 1.032 | tINS | FF | 1 | R11C12[3][A] | clk_cntd_N_2L1_1_0_0_cZ/F |
9.497 | 0.000 | tNET | FF | 1 | R11C12[3][A] | clk_cntd_N_2L1_1_0_cZ/I0 |
9.646 | 0.149 | tINS | FF | 1 | R11C12[3][A] | clk_cntd_N_2L1_1_0_cZ/O |
9.646 | 0.000 | tNET | FF | 1 | R11C12[2][B] | clk_cntd_N_2L1_1/I0 |
9.809 | 0.163 | tINS | FF | 2 | R11C12[2][B] | clk_cntd_N_2L1_1/O |
11.129 | 1.320 | tNET | FF | 1 | R11C9[2][A] | \clk_cntd[9] /I3 |
11.755 | 0.626 | tINS | FF | 1 | R11C9[2][A] | \clk_cntd[9] /F |
11.755 | 0.000 | tNET | FF | 1 | R11C9[2][A] | \clk_cnt_Z[9] /D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||||
10.000 | 0.000 | tCL | RR | 1 | IOL3[B] | clk_ibuf/I |
10.982 | 0.982 | tINS | RR | 27 | IOL3[B] | clk_ibuf/O |
14.370 | 3.388 | tNET | RR | 1 | R11C9[2][A] | \clk_cnt_Z[9] /CLK |
14.170 | -0.200 | tUnc | \clk_cnt_Z[9] | |||
13.770 | -0.400 | tSu | 1 | R11C9[2][A] | \clk_cnt_Z[9] |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 0.982, 22.470%; route: 3.388, 77.530% |
Arrival Data Path Delay | cell: 3.002, 40.649%; route: 3.925, 53.144%; tC2Q: 0.458, 6.206% |
Required Clock Path Delay | cell: 0.982, 22.470%; route: 3.388, 77.530% |
Hold Analysis Report
Report Command:report_timing -hold -max_paths 25 -max_common_paths 1
Path1
Path Summary:
Slack | 0.709 |
Data Arrival Time | 4.068 |
Data Required Time | 3.359 |
From | \led_1[0] |
To | \led_1[0] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL3[B] | clk_ibuf/I |
0.844 | 0.844 | tINS | RR | 27 | IOL3[B] | clk_ibuf/O |
3.359 | 2.515 | tNET | RR | 1 | R12C13[0][A] | \led_1[0] /CLK |
3.693 | 0.333 | tC2Q | RR | 5 | R12C13[0][A] | \led_1[0] /Q |
3.696 | 0.004 | tNET | RR | 1 | R12C13[0][A] | \led_1e[0] /I2 |
4.068 | 0.372 | tINS | RF | 1 | R12C13[0][A] | \led_1e[0] /F |
4.068 | 0.000 | tNET | FF | 1 | R12C13[0][A] | \led_1[0] /D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL3[B] | clk_ibuf/I |
0.844 | 0.844 | tINS | RR | 27 | IOL3[B] | clk_ibuf/O |
3.359 | 2.515 | tNET | RR | 1 | R12C13[0][A] | \led_1[0] /CLK |
3.359 | 0.000 | tUnc | \led_1[0] | |||
3.359 | 0.000 | tHld | 1 | R12C13[0][A] | \led_1[0] |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.844, 25.135%; route: 2.515, 74.865% |
Arrival Data Path Delay | cell: 0.372, 52.478%; route: 0.004, 0.500%; tC2Q: 0.333, 47.023% |
Required Clock Path Delay | cell: 0.844, 25.135%; route: 2.515, 74.865% |
Path2
Path Summary:
Slack | 0.853 |
Data Arrival Time | 4.212 |
Data Required Time | 3.359 |
From | \clk_cnt_Z[25] |
To | \clk_cnt_Z[25] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL3[B] | clk_ibuf/I |
0.844 | 0.844 | tINS | RR | 27 | IOL3[B] | clk_ibuf/O |
3.359 | 2.515 | tNET | RR | 1 | R9C12[1][B] | \clk_cnt_Z[25] /CLK |
3.693 | 0.333 | tC2Q | RR | 2 | R9C12[1][B] | \clk_cnt_Z[25] /Q |
3.695 | 0.002 | tNET | RR | 2 | R9C12[1][B] | \clk_cnt_s_0[25] /I0 |
4.212 | 0.517 | tINS | RF | 1 | R9C12[1][B] | \clk_cnt_s_0[25] /SUM |
4.212 | 0.000 | tNET | FF | 1 | R9C12[1][B] | \clk_cnt_Z[25] /D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL3[B] | clk_ibuf/I |
0.844 | 0.844 | tINS | RR | 27 | IOL3[B] | clk_ibuf/O |
3.359 | 2.515 | tNET | RR | 1 | R9C12[1][B] | \clk_cnt_Z[25] /CLK |
3.359 | 0.000 | tUnc | \clk_cnt_Z[25] | |||
3.359 | 0.000 | tHld | 1 | R9C12[1][B] | \clk_cnt_Z[25] |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.844, 25.135%; route: 2.515, 74.865% |
Arrival Data Path Delay | cell: 0.517, 60.631%; route: 0.002, 0.277%; tC2Q: 0.333, 39.092% |
Required Clock Path Delay | cell: 0.844, 25.135%; route: 2.515, 74.865% |
Path3
Path Summary:
Slack | 0.853 |
Data Arrival Time | 4.212 |
Data Required Time | 3.359 |
From | \clk_cnt_Z[23] |
To | \clk_cnt_Z[23] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL3[B] | clk_ibuf/I |
0.844 | 0.844 | tINS | RR | 27 | IOL3[B] | clk_ibuf/O |
3.359 | 2.515 | tNET | RR | 1 | R9C12[0][B] | \clk_cnt_Z[23] /CLK |
3.693 | 0.333 | tC2Q | RR | 6 | R9C12[0][B] | \clk_cnt_Z[23] /Q |
3.695 | 0.002 | tNET | RR | 2 | R9C12[0][B] | \clk_cnt_cry_0[23] /I0 |
4.212 | 0.517 | tINS | RF | 1 | R9C12[0][B] | \clk_cnt_cry_0[23] /SUM |
4.212 | 0.000 | tNET | FF | 1 | R9C12[0][B] | \clk_cnt_Z[23] /D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL3[B] | clk_ibuf/I |
0.844 | 0.844 | tINS | RR | 27 | IOL3[B] | clk_ibuf/O |
3.359 | 2.515 | tNET | RR | 1 | R9C12[0][B] | \clk_cnt_Z[23] /CLK |
3.359 | 0.000 | tUnc | \clk_cnt_Z[23] | |||
3.359 | 0.000 | tHld | 1 | R9C12[0][B] | \clk_cnt_Z[23] |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.844, 25.135%; route: 2.515, 74.865% |
Arrival Data Path Delay | cell: 0.517, 60.631%; route: 0.002, 0.277%; tC2Q: 0.333, 39.092% |
Required Clock Path Delay | cell: 0.844, 25.135%; route: 2.515, 74.865% |
Path4
Path Summary:
Slack | 0.853 |
Data Arrival Time | 4.212 |
Data Required Time | 3.359 |
From | \clk_cnt_Z[19] |
To | \clk_cnt_Z[19] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL3[B] | clk_ibuf/I |
0.844 | 0.844 | tINS | RR | 27 | IOL3[B] | clk_ibuf/O |
3.359 | 2.515 | tNET | RR | 1 | R9C11[1][B] | \clk_cnt_Z[19] /CLK |
3.693 | 0.333 | tC2Q | RR | 3 | R9C11[1][B] | \clk_cnt_Z[19] /Q |
3.695 | 0.002 | tNET | RR | 2 | R9C11[1][B] | \clk_cnt_cry_0[19] /I0 |
4.212 | 0.517 | tINS | RF | 1 | R9C11[1][B] | \clk_cnt_cry_0[19] /SUM |
4.212 | 0.000 | tNET | FF | 1 | R9C11[1][B] | \clk_cnt_Z[19] /D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL3[B] | clk_ibuf/I |
0.844 | 0.844 | tINS | RR | 27 | IOL3[B] | clk_ibuf/O |
3.359 | 2.515 | tNET | RR | 1 | R9C11[1][B] | \clk_cnt_Z[19] /CLK |
3.359 | 0.000 | tUnc | \clk_cnt_Z[19] | |||
3.359 | 0.000 | tHld | 1 | R9C11[1][B] | \clk_cnt_Z[19] |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.844, 25.135%; route: 2.515, 74.865% |
Arrival Data Path Delay | cell: 0.517, 60.631%; route: 0.002, 0.277%; tC2Q: 0.333, 39.092% |
Required Clock Path Delay | cell: 0.844, 25.135%; route: 2.515, 74.865% |
Path5
Path Summary:
Slack | 0.853 |
Data Arrival Time | 4.212 |
Data Required Time | 3.359 |
From | \clk_cnt_Z[17] |
To | \clk_cnt_Z[17] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL3[B] | clk_ibuf/I |
0.844 | 0.844 | tINS | RR | 27 | IOL3[B] | clk_ibuf/O |
3.359 | 2.515 | tNET | RR | 1 | R9C11[0][B] | \clk_cnt_Z[17] /CLK |
3.693 | 0.333 | tC2Q | RR | 2 | R9C11[0][B] | \clk_cnt_Z[17] /Q |
3.695 | 0.002 | tNET | RR | 2 | R9C11[0][B] | \clk_cnt_cry_0[17] /I0 |
4.212 | 0.517 | tINS | RF | 1 | R9C11[0][B] | \clk_cnt_cry_0[17] /SUM |
4.212 | 0.000 | tNET | FF | 1 | R9C11[0][B] | \clk_cnt_Z[17] /D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL3[B] | clk_ibuf/I |
0.844 | 0.844 | tINS | RR | 27 | IOL3[B] | clk_ibuf/O |
3.359 | 2.515 | tNET | RR | 1 | R9C11[0][B] | \clk_cnt_Z[17] /CLK |
3.359 | 0.000 | tUnc | \clk_cnt_Z[17] | |||
3.359 | 0.000 | tHld | 1 | R9C11[0][B] | \clk_cnt_Z[17] |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.844, 25.135%; route: 2.515, 74.865% |
Arrival Data Path Delay | cell: 0.517, 60.631%; route: 0.002, 0.277%; tC2Q: 0.333, 39.092% |
Required Clock Path Delay | cell: 0.844, 25.135%; route: 2.515, 74.865% |
Path6
Path Summary:
Slack | 0.853 |
Data Arrival Time | 4.212 |
Data Required Time | 3.359 |
From | \clk_cnt_Z[13] |
To | \clk_cnt_Z[13] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL3[B] | clk_ibuf/I |
0.844 | 0.844 | tINS | RR | 27 | IOL3[B] | clk_ibuf/O |
3.359 | 2.515 | tNET | RR | 1 | R9C10[1][B] | \clk_cnt_Z[13] /CLK |
3.693 | 0.333 | tC2Q | RR | 3 | R9C10[1][B] | \clk_cnt_Z[13] /Q |
3.695 | 0.002 | tNET | RR | 2 | R9C10[1][B] | \clk_cnt_cry_0[13] /I0 |
4.212 | 0.517 | tINS | RF | 1 | R9C10[1][B] | \clk_cnt_cry_0[13] /SUM |
4.212 | 0.000 | tNET | FF | 1 | R9C10[1][B] | \clk_cnt_Z[13] /D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL3[B] | clk_ibuf/I |
0.844 | 0.844 | tINS | RR | 27 | IOL3[B] | clk_ibuf/O |
3.359 | 2.515 | tNET | RR | 1 | R9C10[1][B] | \clk_cnt_Z[13] /CLK |
3.359 | 0.000 | tUnc | \clk_cnt_Z[13] | |||
3.359 | 0.000 | tHld | 1 | R9C10[1][B] | \clk_cnt_Z[13] |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.844, 25.135%; route: 2.515, 74.865% |
Arrival Data Path Delay | cell: 0.517, 60.631%; route: 0.002, 0.277%; tC2Q: 0.333, 39.092% |
Required Clock Path Delay | cell: 0.844, 25.135%; route: 2.515, 74.865% |
Path7
Path Summary:
Slack | 1.085 |
Data Arrival Time | 4.444 |
Data Required Time | 3.359 |
From | \clk_cnt_Z[15] |
To | \clk_cnt_Z[15] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL3[B] | clk_ibuf/I |
0.844 | 0.844 | tINS | RR | 27 | IOL3[B] | clk_ibuf/O |
3.359 | 2.515 | tNET | RR | 1 | R9C10[2][B] | \clk_cnt_Z[15] /CLK |
3.693 | 0.333 | tC2Q | RF | 3 | R9C10[2][B] | \clk_cnt_Z[15] /Q |
3.927 | 0.234 | tNET | FF | 2 | R9C10[2][B] | \clk_cnt_cry_0[15] /I0 |
4.444 | 0.517 | tINS | FF | 1 | R9C10[2][B] | \clk_cnt_cry_0[15] /SUM |
4.444 | 0.000 | tNET | FF | 1 | R9C10[2][B] | \clk_cnt_Z[15] /D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL3[B] | clk_ibuf/I |
0.844 | 0.844 | tINS | RR | 27 | IOL3[B] | clk_ibuf/O |
3.359 | 2.515 | tNET | RR | 1 | R9C10[2][B] | \clk_cnt_Z[15] /CLK |
3.359 | 0.000 | tUnc | \clk_cnt_Z[15] | |||
3.359 | 0.000 | tHld | 1 | R9C10[2][B] | \clk_cnt_Z[15] |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.844, 25.135%; route: 2.515, 74.865% |
Arrival Data Path Delay | cell: 0.517, 47.658%; route: 0.234, 21.615%; tC2Q: 0.333, 30.727% |
Required Clock Path Delay | cell: 0.844, 25.135%; route: 2.515, 74.865% |
Path8
Path Summary:
Slack | 1.088 |
Data Arrival Time | 4.447 |
Data Required Time | 3.359 |
From | \clk_cnt_Z[20] |
To | \clk_cnt_Z[20] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL3[B] | clk_ibuf/I |
0.844 | 0.844 | tINS | RR | 27 | IOL3[B] | clk_ibuf/O |
3.359 | 2.515 | tNET | RR | 1 | R9C11[2][A] | \clk_cnt_Z[20] /CLK |
3.693 | 0.333 | tC2Q | RR | 4 | R9C11[2][A] | \clk_cnt_Z[20] /Q |
3.930 | 0.238 | tNET | RR | 2 | R9C11[2][A] | \clk_cnt_cry_0[20] /I0 |
4.447 | 0.517 | tINS | RF | 1 | R9C11[2][A] | \clk_cnt_cry_0[20] /SUM |
4.447 | 0.000 | tNET | FF | 1 | R9C11[2][A] | \clk_cnt_Z[20] /D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL3[B] | clk_ibuf/I |
0.844 | 0.844 | tINS | RR | 27 | IOL3[B] | clk_ibuf/O |
3.359 | 2.515 | tNET | RR | 1 | R9C11[2][A] | \clk_cnt_Z[20] /CLK |
3.359 | 0.000 | tUnc | \clk_cnt_Z[20] | |||
3.359 | 0.000 | tHld | 1 | R9C11[2][A] | \clk_cnt_Z[20] |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.844, 25.135%; route: 2.515, 74.865% |
Arrival Data Path Delay | cell: 0.517, 47.522%; route: 0.238, 21.838%; tC2Q: 0.333, 30.640% |
Required Clock Path Delay | cell: 0.844, 25.135%; route: 2.515, 74.865% |
Path9
Path Summary:
Slack | 1.088 |
Data Arrival Time | 4.447 |
Data Required Time | 3.359 |
From | \clk_cnt_Z[6] |
To | \clk_cnt_Z[6] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL3[B] | clk_ibuf/I |
0.844 | 0.844 | tINS | RR | 27 | IOL3[B] | clk_ibuf/O |
3.359 | 2.515 | tNET | RR | 1 | R9C9[1][A] | \clk_cnt_Z[6] /CLK |
3.693 | 0.333 | tC2Q | RR | 2 | R9C9[1][A] | \clk_cnt_Z[6] /Q |
3.930 | 0.238 | tNET | RR | 2 | R9C9[1][A] | \clk_cnt_cry_0[6] /I0 |
4.447 | 0.517 | tINS | RF | 1 | R9C9[1][A] | \clk_cnt_cry_0[6] /SUM |
4.447 | 0.000 | tNET | FF | 1 | R9C9[1][A] | \clk_cnt_Z[6] /D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL3[B] | clk_ibuf/I |
0.844 | 0.844 | tINS | RR | 27 | IOL3[B] | clk_ibuf/O |
3.359 | 2.515 | tNET | RR | 1 | R9C9[1][A] | \clk_cnt_Z[6] /CLK |
3.359 | 0.000 | tUnc | \clk_cnt_Z[6] | |||
3.359 | 0.000 | tHld | 1 | R9C9[1][A] | \clk_cnt_Z[6] |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.844, 25.135%; route: 2.515, 74.865% |
Arrival Data Path Delay | cell: 0.517, 47.522%; route: 0.238, 21.838%; tC2Q: 0.333, 30.640% |
Required Clock Path Delay | cell: 0.844, 25.135%; route: 2.515, 74.865% |
Path10
Path Summary:
Slack | 1.088 |
Data Arrival Time | 4.447 |
Data Required Time | 3.359 |
From | \clk_cnt_Z[14] |
To | \clk_cnt_Z[14] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL3[B] | clk_ibuf/I |
0.844 | 0.844 | tINS | RR | 27 | IOL3[B] | clk_ibuf/O |
3.359 | 2.515 | tNET | RR | 1 | R9C10[2][A] | \clk_cnt_Z[14] /CLK |
3.693 | 0.333 | tC2Q | RR | 3 | R9C10[2][A] | \clk_cnt_Z[14] /Q |
3.930 | 0.238 | tNET | RR | 2 | R9C10[2][A] | \clk_cnt_cry_0[14] /I0 |
4.447 | 0.517 | tINS | RF | 1 | R9C10[2][A] | \clk_cnt_cry_0[14] /SUM |
4.447 | 0.000 | tNET | FF | 1 | R9C10[2][A] | \clk_cnt_Z[14] /D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL3[B] | clk_ibuf/I |
0.844 | 0.844 | tINS | RR | 27 | IOL3[B] | clk_ibuf/O |
3.359 | 2.515 | tNET | RR | 1 | R9C10[2][A] | \clk_cnt_Z[14] /CLK |
3.359 | 0.000 | tUnc | \clk_cnt_Z[14] | |||
3.359 | 0.000 | tHld | 1 | R9C10[2][A] | \clk_cnt_Z[14] |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.844, 25.135%; route: 2.515, 74.865% |
Arrival Data Path Delay | cell: 0.517, 47.522%; route: 0.238, 21.838%; tC2Q: 0.333, 30.640% |
Required Clock Path Delay | cell: 0.844, 25.135%; route: 2.515, 74.865% |
Path11
Path Summary:
Slack | 1.089 |
Data Arrival Time | 4.448 |
Data Required Time | 3.359 |
From | \clk_cnt_Z[22] |
To | \clk_cnt_Z[22] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL3[B] | clk_ibuf/I |
0.844 | 0.844 | tINS | RR | 27 | IOL3[B] | clk_ibuf/O |
3.359 | 2.515 | tNET | RR | 1 | R9C12[0][A] | \clk_cnt_Z[22] /CLK |
3.693 | 0.333 | tC2Q | RR | 6 | R9C12[0][A] | \clk_cnt_Z[22] /Q |
3.931 | 0.239 | tNET | RR | 2 | R9C12[0][A] | \clk_cnt_cry_0[22] /I0 |
4.448 | 0.517 | tINS | RF | 1 | R9C12[0][A] | \clk_cnt_cry_0[22] /SUM |
4.448 | 0.000 | tNET | FF | 1 | R9C12[0][A] | \clk_cnt_Z[22] /D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL3[B] | clk_ibuf/I |
0.844 | 0.844 | tINS | RR | 27 | IOL3[B] | clk_ibuf/O |
3.359 | 2.515 | tNET | RR | 1 | R9C12[0][A] | \clk_cnt_Z[22] /CLK |
3.359 | 0.000 | tUnc | \clk_cnt_Z[22] | |||
3.359 | 0.000 | tHld | 1 | R9C12[0][A] | \clk_cnt_Z[22] |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.844, 25.135%; route: 2.515, 74.865% |
Arrival Data Path Delay | cell: 0.517, 47.471%; route: 0.239, 21.922%; tC2Q: 0.333, 30.607% |
Required Clock Path Delay | cell: 0.844, 25.135%; route: 2.515, 74.865% |
Path12
Path Summary:
Slack | 1.089 |
Data Arrival Time | 4.448 |
Data Required Time | 3.359 |
From | \clk_cnt_Z[16] |
To | \clk_cnt_Z[16] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL3[B] | clk_ibuf/I |
0.844 | 0.844 | tINS | RR | 27 | IOL3[B] | clk_ibuf/O |
3.359 | 2.515 | tNET | RR | 1 | R9C11[0][A] | \clk_cnt_Z[16] /CLK |
3.693 | 0.333 | tC2Q | RR | 4 | R9C11[0][A] | \clk_cnt_Z[16] /Q |
3.931 | 0.239 | tNET | RR | 2 | R9C11[0][A] | \clk_cnt_cry_0[16] /I0 |
4.448 | 0.517 | tINS | RF | 1 | R9C11[0][A] | \clk_cnt_cry_0[16] /SUM |
4.448 | 0.000 | tNET | FF | 1 | R9C11[0][A] | \clk_cnt_Z[16] /D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL3[B] | clk_ibuf/I |
0.844 | 0.844 | tINS | RR | 27 | IOL3[B] | clk_ibuf/O |
3.359 | 2.515 | tNET | RR | 1 | R9C11[0][A] | \clk_cnt_Z[16] /CLK |
3.359 | 0.000 | tUnc | \clk_cnt_Z[16] | |||
3.359 | 0.000 | tHld | 1 | R9C11[0][A] | \clk_cnt_Z[16] |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.844, 25.135%; route: 2.515, 74.865% |
Arrival Data Path Delay | cell: 0.517, 47.471%; route: 0.239, 21.922%; tC2Q: 0.333, 30.607% |
Required Clock Path Delay | cell: 0.844, 25.135%; route: 2.515, 74.865% |
Path13
Path Summary:
Slack | 1.090 |
Data Arrival Time | 4.450 |
Data Required Time | 3.359 |
From | \clk_cnt_Z[24] |
To | \clk_cnt_Z[24] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL3[B] | clk_ibuf/I |
0.844 | 0.844 | tINS | RR | 27 | IOL3[B] | clk_ibuf/O |
3.359 | 2.515 | tNET | RR | 1 | R9C12[1][A] | \clk_cnt_Z[24] /CLK |
3.693 | 0.333 | tC2Q | RR | 11 | R9C12[1][A] | \clk_cnt_Z[24] /Q |
3.933 | 0.240 | tNET | RR | 2 | R9C12[1][A] | \clk_cnt_cry_0[24] /I0 |
4.450 | 0.517 | tINS | RF | 1 | R9C12[1][A] | \clk_cnt_cry_0[24] /SUM |
4.450 | 0.000 | tNET | FF | 1 | R9C12[1][A] | \clk_cnt_Z[24] /D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL3[B] | clk_ibuf/I |
0.844 | 0.844 | tINS | RR | 27 | IOL3[B] | clk_ibuf/O |
3.359 | 2.515 | tNET | RR | 1 | R9C12[1][A] | \clk_cnt_Z[24] /CLK |
3.359 | 0.000 | tUnc | \clk_cnt_Z[24] | |||
3.359 | 0.000 | tHld | 1 | R9C12[1][A] | \clk_cnt_Z[24] |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.844, 25.135%; route: 2.515, 74.865% |
Arrival Data Path Delay | cell: 0.517, 47.420%; route: 0.240, 22.007%; tC2Q: 0.333, 30.574% |
Required Clock Path Delay | cell: 0.844, 25.135%; route: 2.515, 74.865% |
Path14
Path Summary:
Slack | 1.095 |
Data Arrival Time | 4.455 |
Data Required Time | 3.359 |
From | \clk_cnt_Z[18] |
To | \clk_cnt_Z[18] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL3[B] | clk_ibuf/I |
0.844 | 0.844 | tINS | RR | 27 | IOL3[B] | clk_ibuf/O |
3.359 | 2.515 | tNET | RR | 1 | R9C11[1][A] | \clk_cnt_Z[18] /CLK |
3.693 | 0.333 | tC2Q | RR | 5 | R9C11[1][A] | \clk_cnt_Z[18] /Q |
3.938 | 0.245 | tNET | RR | 2 | R9C11[1][A] | \clk_cnt_cry_0[18] /I0 |
4.455 | 0.517 | tINS | RF | 1 | R9C11[1][A] | \clk_cnt_cry_0[18] /SUM |
4.455 | 0.000 | tNET | FF | 1 | R9C11[1][A] | \clk_cnt_Z[18] /D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL3[B] | clk_ibuf/I |
0.844 | 0.844 | tINS | RR | 27 | IOL3[B] | clk_ibuf/O |
3.359 | 2.515 | tNET | RR | 1 | R9C11[1][A] | \clk_cnt_Z[18] /CLK |
3.359 | 0.000 | tUnc | \clk_cnt_Z[18] | |||
3.359 | 0.000 | tHld | 1 | R9C11[1][A] | \clk_cnt_Z[18] |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.844, 25.135%; route: 2.515, 74.865% |
Arrival Data Path Delay | cell: 0.517, 47.202%; route: 0.245, 22.365%; tC2Q: 0.333, 30.433% |
Required Clock Path Delay | cell: 0.844, 25.135%; route: 2.515, 74.865% |
Path15
Path Summary:
Slack | 1.115 |
Data Arrival Time | 4.475 |
Data Required Time | 3.359 |
From | \clk_cnt_Z[21] |
To | \clk_cnt_Z[21] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL3[B] | clk_ibuf/I |
0.844 | 0.844 | tINS | RR | 27 | IOL3[B] | clk_ibuf/O |
3.359 | 2.515 | tNET | RR | 1 | R9C11[2][B] | \clk_cnt_Z[21] /CLK |
3.693 | 0.333 | tC2Q | RR | 6 | R9C11[2][B] | \clk_cnt_Z[21] /Q |
3.958 | 0.265 | tNET | RR | 2 | R9C11[2][B] | \clk_cnt_cry_0[21] /I0 |
4.475 | 0.517 | tINS | RF | 1 | R9C11[2][B] | \clk_cnt_cry_0[21] /SUM |
4.475 | 0.000 | tNET | FF | 1 | R9C11[2][B] | \clk_cnt_Z[21] /D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL3[B] | clk_ibuf/I |
0.844 | 0.844 | tINS | RR | 27 | IOL3[B] | clk_ibuf/O |
3.359 | 2.515 | tNET | RR | 1 | R9C11[2][B] | \clk_cnt_Z[21] /CLK |
3.359 | 0.000 | tUnc | \clk_cnt_Z[21] | |||
3.359 | 0.000 | tHld | 1 | R9C11[2][B] | \clk_cnt_Z[21] |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.844, 25.135%; route: 2.515, 74.865% |
Arrival Data Path Delay | cell: 0.517, 46.357%; route: 0.265, 23.755%; tC2Q: 0.333, 29.888% |
Required Clock Path Delay | cell: 0.844, 25.135%; route: 2.515, 74.865% |
Path16
Path Summary:
Slack | 1.938 |
Data Arrival Time | 5.298 |
Data Required Time | 3.359 |
From | \clk_cnt_Z[16] |
To | \clk_cnt_Z[11] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL3[B] | clk_ibuf/I |
0.844 | 0.844 | tINS | RR | 27 | IOL3[B] | clk_ibuf/O |
3.359 | 2.515 | tNET | RR | 1 | R9C11[0][A] | \clk_cnt_Z[16] /CLK |
3.693 | 0.333 | tC2Q | RR | 4 | R9C11[0][A] | \clk_cnt_Z[16] /Q |
3.964 | 0.271 | tNET | RR | 1 | R11C11[1][A] | clk_cnt11_0_m1_e_1_1_0/I0 |
4.336 | 0.372 | tINS | RF | 3 | R11C11[1][A] | clk_cnt11_0_m1_e_1_1_0/F |
4.349 | 0.013 | tNET | FF | 1 | R11C11[3][A] | clk_cnt11_0_m1_e_sx_cZ/I2 |
4.734 | 0.385 | tINS | FR | 8 | R11C11[3][A] | clk_cnt11_0_m1_e_sx_cZ/F |
4.742 | 0.008 | tNET | RR | 1 | R11C11[1][B] | \clk_cntd[11] /I1 |
5.298 | 0.556 | tINS | RR | 1 | R11C11[1][B] | \clk_cntd[11] /F |
5.298 | 0.000 | tNET | RR | 1 | R11C11[1][B] | \clk_cnt_Z[11] /D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL3[B] | clk_ibuf/I |
0.844 | 0.844 | tINS | RR | 27 | IOL3[B] | clk_ibuf/O |
3.359 | 2.515 | tNET | RR | 1 | R11C11[1][B] | \clk_cnt_Z[11] /CLK |
3.359 | 0.000 | tUnc | \clk_cnt_Z[11] | |||
3.359 | 0.000 | tHld | 1 | R11C11[1][B] | \clk_cnt_Z[11] |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 3 |
Arrival Clock Path Delay | cell: 0.844, 25.135%; route: 2.515, 74.865% |
Arrival Data Path Delay | cell: 1.313, 67.735%; route: 0.292, 15.070%; tC2Q: 0.333, 17.196% |
Required Clock Path Delay | cell: 0.844, 25.135%; route: 2.515, 74.865% |
Path17
Path Summary:
Slack | 1.938 |
Data Arrival Time | 5.298 |
Data Required Time | 3.359 |
From | \clk_cnt_Z[16] |
To | \clk_cnt_Z[12] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL3[B] | clk_ibuf/I |
0.844 | 0.844 | tINS | RR | 27 | IOL3[B] | clk_ibuf/O |
3.359 | 2.515 | tNET | RR | 1 | R9C11[0][A] | \clk_cnt_Z[16] /CLK |
3.693 | 0.333 | tC2Q | RR | 4 | R9C11[0][A] | \clk_cnt_Z[16] /Q |
3.964 | 0.271 | tNET | RR | 1 | R11C11[1][A] | clk_cnt11_0_m1_e_1_1_0/I0 |
4.336 | 0.372 | tINS | RF | 3 | R11C11[1][A] | clk_cnt11_0_m1_e_1_1_0/F |
4.349 | 0.013 | tNET | FF | 1 | R11C11[3][A] | clk_cnt11_0_m1_e_sx_cZ/I2 |
4.734 | 0.385 | tINS | FR | 8 | R11C11[3][A] | clk_cnt11_0_m1_e_sx_cZ/F |
4.742 | 0.008 | tNET | RR | 1 | R11C11[2][A] | \clk_cntd[12] /I1 |
5.298 | 0.556 | tINS | RR | 1 | R11C11[2][A] | \clk_cntd[12] /F |
5.298 | 0.000 | tNET | RR | 1 | R11C11[2][A] | \clk_cnt_Z[12] /D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL3[B] | clk_ibuf/I |
0.844 | 0.844 | tINS | RR | 27 | IOL3[B] | clk_ibuf/O |
3.359 | 2.515 | tNET | RR | 1 | R11C11[2][A] | \clk_cnt_Z[12] /CLK |
3.359 | 0.000 | tUnc | \clk_cnt_Z[12] | |||
3.359 | 0.000 | tHld | 1 | R11C11[2][A] | \clk_cnt_Z[12] |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 3 |
Arrival Clock Path Delay | cell: 0.844, 25.135%; route: 2.515, 74.865% |
Arrival Data Path Delay | cell: 1.313, 67.735%; route: 0.292, 15.070%; tC2Q: 0.333, 17.196% |
Required Clock Path Delay | cell: 0.844, 25.135%; route: 2.515, 74.865% |
Path18
Path Summary:
Slack | 1.962 |
Data Arrival Time | 5.321 |
Data Required Time | 3.359 |
From | \clk_cnt_Z[16] |
To | \clk_cnt_Z[2] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL3[B] | clk_ibuf/I |
0.844 | 0.844 | tINS | RR | 27 | IOL3[B] | clk_ibuf/O |
3.359 | 2.515 | tNET | RR | 1 | R9C11[0][A] | \clk_cnt_Z[16] /CLK |
3.693 | 0.333 | tC2Q | RR | 4 | R9C11[0][A] | \clk_cnt_Z[16] /Q |
3.964 | 0.271 | tNET | RR | 1 | R11C11[0][A] | \clk_cntd_1_1_0[0] /I0 |
4.336 | 0.372 | tINS | RF | 1 | R11C11[0][A] | \clk_cntd_1_1_0[0] /F |
4.340 | 0.004 | tNET | FF | 1 | R11C11[2][B] | \clk_cntd_1_cZ[0] /I0 |
4.712 | 0.372 | tINS | FF | 2 | R11C11[2][B] | \clk_cntd_1_cZ[0] /F |
4.949 | 0.237 | tNET | FF | 1 | R11C10[0][B] | \clk_cntd[2] /I3 |
5.321 | 0.372 | tINS | FF | 1 | R11C10[0][B] | \clk_cntd[2] /F |
5.321 | 0.000 | tNET | FF | 1 | R11C10[0][B] | \clk_cnt_Z[2] /D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL3[B] | clk_ibuf/I |
0.844 | 0.844 | tINS | RR | 27 | IOL3[B] | clk_ibuf/O |
3.359 | 2.515 | tNET | RR | 1 | R11C10[0][B] | \clk_cnt_Z[2] /CLK |
3.359 | 0.000 | tUnc | \clk_cnt_Z[2] | |||
3.359 | 0.000 | tHld | 1 | R11C10[0][B] | \clk_cnt_Z[2] |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 3 |
Arrival Clock Path Delay | cell: 0.844, 25.135%; route: 2.515, 74.865% |
Arrival Data Path Delay | cell: 1.116, 56.894%; route: 0.512, 26.113%; tC2Q: 0.333, 16.993% |
Required Clock Path Delay | cell: 0.844, 25.135%; route: 2.515, 74.865% |
Path19
Path Summary:
Slack | 2.080 |
Data Arrival Time | 5.440 |
Data Required Time | 3.359 |
From | \clk_cnt_Z[4] |
To | \clk_cnt_Z[4] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL3[B] | clk_ibuf/I |
0.844 | 0.844 | tINS | RR | 27 | IOL3[B] | clk_ibuf/O |
3.359 | 2.515 | tNET | RR | 1 | R11C9[0][B] | \clk_cnt_Z[4] /CLK |
3.693 | 0.333 | tC2Q | RR | 2 | R11C9[0][B] | \clk_cnt_Z[4] /Q |
4.264 | 0.572 | tNET | RR | 2 | R9C9[0][A] | \clk_cnt_cry_0[4] /I0 |
4.802 | 0.538 | tINS | RR | 1 | R9C9[0][A] | \clk_cnt_cry_0[4] /SUM |
5.068 | 0.265 | tNET | RR | 1 | R11C9[0][B] | \clk_cntd[4] /I2 |
5.440 | 0.372 | tINS | RF | 1 | R11C9[0][B] | \clk_cntd[4] /F |
5.440 | 0.000 | tNET | FF | 1 | R11C9[0][B] | \clk_cnt_Z[4] /D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL3[B] | clk_ibuf/I |
0.844 | 0.844 | tINS | RR | 27 | IOL3[B] | clk_ibuf/O |
3.359 | 2.515 | tNET | RR | 1 | R11C9[0][B] | \clk_cnt_Z[4] /CLK |
3.359 | 0.000 | tUnc | \clk_cnt_Z[4] | |||
3.359 | 0.000 | tHld | 1 | R11C9[0][B] | \clk_cnt_Z[4] |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.844, 25.135%; route: 2.515, 74.865% |
Arrival Data Path Delay | cell: 0.910, 43.745%; route: 0.837, 40.231%; tC2Q: 0.333, 16.024% |
Required Clock Path Delay | cell: 0.844, 25.135%; route: 2.515, 74.865% |
Path20
Path Summary:
Slack | 2.090 |
Data Arrival Time | 5.450 |
Data Required Time | 3.359 |
From | \clk_cnt_Z[23] |
To | \clk_cnt_Z[5] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL3[B] | clk_ibuf/I |
0.844 | 0.844 | tINS | RR | 27 | IOL3[B] | clk_ibuf/O |
3.359 | 2.515 | tNET | RR | 1 | R9C12[0][B] | \clk_cnt_Z[23] /CLK |
3.693 | 0.333 | tC2Q | RF | 6 | R9C12[0][B] | \clk_cnt_Z[23] /Q |
3.955 | 0.263 | tNET | FF | 1 | R9C13[0][B] | clk_cnt11_a3/I1 |
4.511 | 0.556 | tINS | FR | 12 | R9C13[0][B] | clk_cnt11_a3/F |
5.078 | 0.566 | tNET | RR | 1 | R11C9[1][A] | \clk_cntd[5] /I1 |
5.450 | 0.372 | tINS | RF | 1 | R11C9[1][A] | \clk_cntd[5] /F |
5.450 | 0.000 | tNET | FF | 1 | R11C9[1][A] | \clk_cnt_Z[5] /D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL3[B] | clk_ibuf/I |
0.844 | 0.844 | tINS | RR | 27 | IOL3[B] | clk_ibuf/O |
3.359 | 2.515 | tNET | RR | 1 | R11C9[1][A] | \clk_cnt_Z[5] /CLK |
3.359 | 0.000 | tUnc | \clk_cnt_Z[5] | |||
3.359 | 0.000 | tHld | 1 | R11C9[1][A] | \clk_cnt_Z[5] |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.844, 25.135%; route: 2.515, 74.865% |
Arrival Data Path Delay | cell: 0.928, 44.395%; route: 0.829, 39.658%; tC2Q: 0.333, 15.947% |
Required Clock Path Delay | cell: 0.844, 25.135%; route: 2.515, 74.865% |
Path21
Path Summary:
Slack | 2.146 |
Data Arrival Time | 5.505 |
Data Required Time | 3.359 |
From | \clk_cnt_Z[16] |
To | \clk_cnt_Z[0] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL3[B] | clk_ibuf/I |
0.844 | 0.844 | tINS | RR | 27 | IOL3[B] | clk_ibuf/O |
3.359 | 2.515 | tNET | RR | 1 | R9C11[0][A] | \clk_cnt_Z[16] /CLK |
3.693 | 0.333 | tC2Q | RR | 4 | R9C11[0][A] | \clk_cnt_Z[16] /Q |
3.964 | 0.271 | tNET | RR | 1 | R11C11[0][A] | \clk_cntd_1_1_0[0] /I0 |
4.336 | 0.372 | tINS | RF | 1 | R11C11[0][A] | \clk_cntd_1_1_0[0] /F |
4.340 | 0.004 | tNET | FF | 1 | R11C11[2][B] | \clk_cntd_1_cZ[0] /I0 |
4.712 | 0.372 | tINS | FF | 2 | R11C11[2][B] | \clk_cntd_1_cZ[0] /F |
4.949 | 0.237 | tNET | FF | 1 | R11C10[0][A] | \clk_cntd[0] /I3 |
5.505 | 0.556 | tINS | FR | 1 | R11C10[0][A] | \clk_cntd[0] /F |
5.505 | 0.000 | tNET | RR | 1 | R11C10[0][A] | \clk_cnt_Z[0] /D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL3[B] | clk_ibuf/I |
0.844 | 0.844 | tINS | RR | 27 | IOL3[B] | clk_ibuf/O |
3.359 | 2.515 | tNET | RR | 1 | R11C10[0][A] | \clk_cnt_Z[0] /CLK |
3.359 | 0.000 | tUnc | \clk_cnt_Z[0] | |||
3.359 | 0.000 | tHld | 1 | R11C10[0][A] | \clk_cnt_Z[0] |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 3 |
Arrival Clock Path Delay | cell: 0.844, 25.135%; route: 2.515, 74.865% |
Arrival Data Path Delay | cell: 1.300, 60.591%; route: 0.512, 23.873%; tC2Q: 0.333, 15.536% |
Required Clock Path Delay | cell: 0.844, 25.135%; route: 2.515, 74.865% |
Path22
Path Summary:
Slack | 2.211 |
Data Arrival Time | 5.586 |
Data Required Time | 3.374 |
From | \clk_cnt_Z[16] |
To | \led_1[0] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL3[B] | clk_ibuf/I |
0.844 | 0.844 | tINS | RR | 27 | IOL3[B] | clk_ibuf/O |
3.359 | 2.515 | tNET | RR | 1 | R9C11[0][A] | \clk_cnt_Z[16] /CLK |
3.693 | 0.333 | tC2Q | RR | 4 | R9C11[0][A] | \clk_cnt_Z[16] /Q |
3.964 | 0.271 | tNET | RR | 1 | R11C11[1][A] | clk_cnt11_0_m1_e_1_1_0/I0 |
4.336 | 0.372 | tINS | RF | 3 | R11C11[1][A] | clk_cnt11_0_m1_e_1_1_0/F |
4.349 | 0.013 | tNET | FF | 1 | R11C11[3][B] | led_1e_N_2L1/I2 |
4.734 | 0.385 | tINS | FR | 1 | R11C11[3][B] | led_1e_N_2L1/F |
5.586 | 0.852 | tNET | RR | 1 | R12C13[0][A] | \led_1[0] /CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL3[B] | clk_ibuf/I |
0.844 | 0.844 | tINS | RR | 27 | IOL3[B] | clk_ibuf/O |
3.359 | 2.515 | tNET | RR | 1 | R12C13[0][A] | \led_1[0] /CLK |
3.359 | 0.000 | tUnc | \led_1[0] | |||
3.374 | 0.015 | tHld | 1 | R12C13[0][A] | \led_1[0] |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.844, 25.135%; route: 2.515, 74.865% |
Arrival Data Path Delay | cell: 0.757, 34.002%; route: 1.136, 51.025%; tC2Q: 0.333, 14.972% |
Required Clock Path Delay | cell: 0.844, 25.135%; route: 2.515, 74.865% |
Path23
Path Summary:
Slack | 2.264 |
Data Arrival Time | 5.624 |
Data Required Time | 3.359 |
From | \clk_cnt_Z[10] |
To | \clk_cnt_Z[10] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL3[B] | clk_ibuf/I |
0.844 | 0.844 | tINS | RR | 27 | IOL3[B] | clk_ibuf/O |
3.359 | 2.515 | tNET | RR | 1 | R11C10[2][B] | \clk_cnt_Z[10] /CLK |
3.693 | 0.333 | tC2Q | RR | 3 | R11C10[2][B] | \clk_cnt_Z[10] /Q |
4.264 | 0.572 | tNET | RR | 2 | R9C10[0][A] | \clk_cnt_cry_0[10] /I0 |
4.802 | 0.538 | tINS | RR | 1 | R9C10[0][A] | \clk_cnt_cry_0[10] /SUM |
5.068 | 0.265 | tNET | RR | 1 | R11C10[2][B] | \clk_cntd[10] /I2 |
5.624 | 0.556 | tINS | RR | 1 | R11C10[2][B] | \clk_cntd[10] /F |
5.624 | 0.000 | tNET | RR | 1 | R11C10[2][B] | \clk_cnt_Z[10] /D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL3[B] | clk_ibuf/I |
0.844 | 0.844 | tINS | RR | 27 | IOL3[B] | clk_ibuf/O |
3.359 | 2.515 | tNET | RR | 1 | R11C10[2][B] | \clk_cnt_Z[10] /CLK |
3.359 | 0.000 | tUnc | \clk_cnt_Z[10] | |||
3.359 | 0.000 | tHld | 1 | R11C10[2][B] | \clk_cnt_Z[10] |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.844, 25.135%; route: 2.515, 74.865% |
Arrival Data Path Delay | cell: 1.094, 48.316%; route: 0.837, 36.962%; tC2Q: 0.333, 14.722% |
Required Clock Path Delay | cell: 0.844, 25.135%; route: 2.515, 74.865% |
Path24
Path Summary:
Slack | 2.274 |
Data Arrival Time | 5.634 |
Data Required Time | 3.359 |
From | \clk_cnt_Z[23] |
To | \clk_cnt_Z[9] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL3[B] | clk_ibuf/I |
0.844 | 0.844 | tINS | RR | 27 | IOL3[B] | clk_ibuf/O |
3.359 | 2.515 | tNET | RR | 1 | R9C12[0][B] | \clk_cnt_Z[23] /CLK |
3.693 | 0.333 | tC2Q | RF | 6 | R9C12[0][B] | \clk_cnt_Z[23] /Q |
3.955 | 0.263 | tNET | FF | 1 | R9C13[0][B] | clk_cnt11_a3/I1 |
4.511 | 0.556 | tINS | FR | 12 | R9C13[0][B] | clk_cnt11_a3/F |
5.078 | 0.566 | tNET | RR | 1 | R11C9[2][A] | \clk_cntd[9] /I0 |
5.634 | 0.556 | tINS | RR | 1 | R11C9[2][A] | \clk_cntd[9] /F |
5.634 | 0.000 | tNET | RR | 1 | R11C9[2][A] | \clk_cnt_Z[9] /D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL3[B] | clk_ibuf/I |
0.844 | 0.844 | tINS | RR | 27 | IOL3[B] | clk_ibuf/O |
3.359 | 2.515 | tNET | RR | 1 | R11C9[2][A] | \clk_cnt_Z[9] /CLK |
3.359 | 0.000 | tUnc | \clk_cnt_Z[9] | |||
3.359 | 0.000 | tHld | 1 | R11C9[2][A] | \clk_cnt_Z[9] |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.844, 25.135%; route: 2.515, 74.865% |
Arrival Data Path Delay | cell: 1.112, 48.894%; route: 0.829, 36.450%; tC2Q: 0.333, 14.656% |
Required Clock Path Delay | cell: 0.844, 25.135%; route: 2.515, 74.865% |
Path25
Path Summary:
Slack | 2.342 |
Data Arrival Time | 5.702 |
Data Required Time | 3.359 |
From | \clk_cnt_Z[16] |
To | \clk_cnt_Z[3] |
Launch Clk | DEFAULT_CLK:[R] |
Latch Clk | DEFAULT_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL3[B] | clk_ibuf/I |
0.844 | 0.844 | tINS | RR | 27 | IOL3[B] | clk_ibuf/O |
3.359 | 2.515 | tNET | RR | 1 | R9C11[0][A] | \clk_cnt_Z[16] /CLK |
3.693 | 0.333 | tC2Q | RR | 4 | R9C11[0][A] | \clk_cnt_Z[16] /Q |
3.964 | 0.271 | tNET | RR | 1 | R11C11[1][A] | clk_cnt11_0_m1_e_1_1_0/I0 |
4.336 | 0.372 | tINS | RF | 3 | R11C11[1][A] | clk_cnt11_0_m1_e_1_1_0/F |
4.349 | 0.013 | tNET | FF | 1 | R11C11[3][A] | clk_cnt11_0_m1_e_sx_cZ/I2 |
4.721 | 0.372 | tINS | FF | 8 | R11C11[3][A] | clk_cnt11_0_m1_e_sx_cZ/F |
4.978 | 0.257 | tNET | FF | 1 | R11C10[1][A] | \clk_cntd[3] /I1 |
5.702 | 0.724 | tINS | FR | 1 | R11C10[1][A] | \clk_cntd[3] /F |
5.702 | 0.000 | tNET | RR | 1 | R11C10[1][A] | \clk_cnt_Z[3] /D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | DEFAULT_CLK(clock) | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL3[B] | clk_ibuf/I |
0.844 | 0.844 | tINS | RR | 27 | IOL3[B] | clk_ibuf/O |
3.359 | 2.515 | tNET | RR | 1 | R11C10[1][A] | \clk_cnt_Z[3] /CLK |
3.359 | 0.000 | tUnc | \clk_cnt_Z[3] | |||
3.359 | 0.000 | tHld | 1 | R11C10[1][A] | \clk_cnt_Z[3] |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 3 |
Arrival Clock Path Delay | cell: 0.844, 25.135%; route: 2.515, 74.865% |
Arrival Data Path Delay | cell: 1.468, 62.669%; route: 0.541, 23.101%; tC2Q: 0.333, 14.230% |
Required Clock Path Delay | cell: 0.844, 25.135%; route: 2.515, 74.865% |
Recovery Analysis Report
Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1
No recovery paths to report!
Removal Analysis Report
Report Command:report_timing -removal -max_paths 25 -max_common_paths 1
No removal paths to report!
Minimum Pulse Width Report:
Report Command:report_min_pulse_width -nworst 10 -detail
MPW1
MPW Summary:
Slack: | 2.329 |
Actual Width: | 3.579 |
Required Width: | 1.250 |
Type: | Low Pulse Width |
Clock: | DEFAULT_CLK |
Objects: | \clk_cnt_Z[12] |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
5.000 | 0.000 | active clock edge time | ||
5.000 | 0.000 | DEFAULT_CLK(clock) | ||
5.000 | 0.000 | tCL | FF | clk_ibuf/I |
5.984 | 0.984 | tINS | FF | clk_ibuf/O |
9.780 | 3.796 | tNET | FF | \clk_cnt_Z[12] /CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||
10.000 | 0.000 | tCL | RR | clk_ibuf/I |
10.844 | 0.844 | tINS | RR | clk_ibuf/O |
13.359 | 2.515 | tNET | RR | \clk_cnt_Z[12] /CLK |
MPW2
MPW Summary:
Slack: | 2.329 |
Actual Width: | 3.579 |
Required Width: | 1.250 |
Type: | Low Pulse Width |
Clock: | DEFAULT_CLK |
Objects: | \clk_cnt_Z[10] |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
5.000 | 0.000 | active clock edge time | ||
5.000 | 0.000 | DEFAULT_CLK(clock) | ||
5.000 | 0.000 | tCL | FF | clk_ibuf/I |
5.984 | 0.984 | tINS | FF | clk_ibuf/O |
9.780 | 3.796 | tNET | FF | \clk_cnt_Z[10] /CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||
10.000 | 0.000 | tCL | RR | clk_ibuf/I |
10.844 | 0.844 | tINS | RR | clk_ibuf/O |
13.359 | 2.515 | tNET | RR | \clk_cnt_Z[10] /CLK |
MPW3
MPW Summary:
Slack: | 2.329 |
Actual Width: | 3.579 |
Required Width: | 1.250 |
Type: | Low Pulse Width |
Clock: | DEFAULT_CLK |
Objects: | \clk_cnt_Z[5] |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
5.000 | 0.000 | active clock edge time | ||
5.000 | 0.000 | DEFAULT_CLK(clock) | ||
5.000 | 0.000 | tCL | FF | clk_ibuf/I |
5.984 | 0.984 | tINS | FF | clk_ibuf/O |
9.780 | 3.796 | tNET | FF | \clk_cnt_Z[5] /CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||
10.000 | 0.000 | tCL | RR | clk_ibuf/I |
10.844 | 0.844 | tINS | RR | clk_ibuf/O |
13.359 | 2.515 | tNET | RR | \clk_cnt_Z[5] /CLK |
MPW4
MPW Summary:
Slack: | 2.329 |
Actual Width: | 3.579 |
Required Width: | 1.250 |
Type: | Low Pulse Width |
Clock: | DEFAULT_CLK |
Objects: | \clk_cnt_Z[14] |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
5.000 | 0.000 | active clock edge time | ||
5.000 | 0.000 | DEFAULT_CLK(clock) | ||
5.000 | 0.000 | tCL | FF | clk_ibuf/I |
5.984 | 0.984 | tINS | FF | clk_ibuf/O |
9.780 | 3.796 | tNET | FF | \clk_cnt_Z[14] /CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||
10.000 | 0.000 | tCL | RR | clk_ibuf/I |
10.844 | 0.844 | tINS | RR | clk_ibuf/O |
13.359 | 2.515 | tNET | RR | \clk_cnt_Z[14] /CLK |
MPW5
MPW Summary:
Slack: | 2.329 |
Actual Width: | 3.579 |
Required Width: | 1.250 |
Type: | Low Pulse Width |
Clock: | DEFAULT_CLK |
Objects: | \clk_cnt_Z[13] |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
5.000 | 0.000 | active clock edge time | ||
5.000 | 0.000 | DEFAULT_CLK(clock) | ||
5.000 | 0.000 | tCL | FF | clk_ibuf/I |
5.984 | 0.984 | tINS | FF | clk_ibuf/O |
9.780 | 3.796 | tNET | FF | \clk_cnt_Z[13] /CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||
10.000 | 0.000 | tCL | RR | clk_ibuf/I |
10.844 | 0.844 | tINS | RR | clk_ibuf/O |
13.359 | 2.515 | tNET | RR | \clk_cnt_Z[13] /CLK |
MPW6
MPW Summary:
Slack: | 2.329 |
Actual Width: | 3.579 |
Required Width: | 1.250 |
Type: | Low Pulse Width |
Clock: | DEFAULT_CLK |
Objects: | \clk_cnt_Z[7] |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
5.000 | 0.000 | active clock edge time | ||
5.000 | 0.000 | DEFAULT_CLK(clock) | ||
5.000 | 0.000 | tCL | FF | clk_ibuf/I |
5.984 | 0.984 | tINS | FF | clk_ibuf/O |
9.780 | 3.796 | tNET | FF | \clk_cnt_Z[7] /CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||
10.000 | 0.000 | tCL | RR | clk_ibuf/I |
10.844 | 0.844 | tINS | RR | clk_ibuf/O |
13.359 | 2.515 | tNET | RR | \clk_cnt_Z[7] /CLK |
MPW7
MPW Summary:
Slack: | 2.329 |
Actual Width: | 3.579 |
Required Width: | 1.250 |
Type: | Low Pulse Width |
Clock: | DEFAULT_CLK |
Objects: | \clk_cnt_Z[6] |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
5.000 | 0.000 | active clock edge time | ||
5.000 | 0.000 | DEFAULT_CLK(clock) | ||
5.000 | 0.000 | tCL | FF | clk_ibuf/I |
5.984 | 0.984 | tINS | FF | clk_ibuf/O |
9.780 | 3.796 | tNET | FF | \clk_cnt_Z[6] /CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||
10.000 | 0.000 | tCL | RR | clk_ibuf/I |
10.844 | 0.844 | tINS | RR | clk_ibuf/O |
13.359 | 2.515 | tNET | RR | \clk_cnt_Z[6] /CLK |
MPW8
MPW Summary:
Slack: | 2.329 |
Actual Width: | 3.579 |
Required Width: | 1.250 |
Type: | Low Pulse Width |
Clock: | DEFAULT_CLK |
Objects: | \led_1[0] |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
5.000 | 0.000 | active clock edge time | ||
5.000 | 0.000 | DEFAULT_CLK(clock) | ||
5.000 | 0.000 | tCL | FF | clk_ibuf/I |
5.984 | 0.984 | tINS | FF | clk_ibuf/O |
9.780 | 3.796 | tNET | FF | \led_1[0] /CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||
10.000 | 0.000 | tCL | RR | clk_ibuf/I |
10.844 | 0.844 | tINS | RR | clk_ibuf/O |
13.359 | 2.515 | tNET | RR | \led_1[0] /CLK |
MPW9
MPW Summary:
Slack: | 2.329 |
Actual Width: | 3.579 |
Required Width: | 1.250 |
Type: | Low Pulse Width |
Clock: | DEFAULT_CLK |
Objects: | \clk_cnt_Z[25] |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
5.000 | 0.000 | active clock edge time | ||
5.000 | 0.000 | DEFAULT_CLK(clock) | ||
5.000 | 0.000 | tCL | FF | clk_ibuf/I |
5.984 | 0.984 | tINS | FF | clk_ibuf/O |
9.780 | 3.796 | tNET | FF | \clk_cnt_Z[25] /CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||
10.000 | 0.000 | tCL | RR | clk_ibuf/I |
10.844 | 0.844 | tINS | RR | clk_ibuf/O |
13.359 | 2.515 | tNET | RR | \clk_cnt_Z[25] /CLK |
MPW10
MPW Summary:
Slack: | 2.329 |
Actual Width: | 3.579 |
Required Width: | 1.250 |
Type: | Low Pulse Width |
Clock: | DEFAULT_CLK |
Objects: | \clk_cnt_Z[0] |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
5.000 | 0.000 | active clock edge time | ||
5.000 | 0.000 | DEFAULT_CLK(clock) | ||
5.000 | 0.000 | tCL | FF | clk_ibuf/I |
5.984 | 0.984 | tINS | FF | clk_ibuf/O |
9.780 | 3.796 | tNET | FF | \clk_cnt_Z[0] /CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | DEFAULT_CLK(clock) | ||
10.000 | 0.000 | tCL | RR | clk_ibuf/I |
10.844 | 0.844 | tINS | RR | clk_ibuf/O |
13.359 | 2.515 | tNET | RR | \clk_cnt_Z[0] /CLK |
High Fanout Nets Report:
Report Command:report_high_fanout_nets -max_nets 10
FANOUT | NET NAME | WORST SLACK | MAX DELAY |
---|---|---|---|
27 | clk_c | 1.185 | 3.796 |
14 | clk_cnt11_0_N_3_mux | 1.185 | 1.703 |
12 | clk_cnt11_0_m1_e_1_0 | 3.715 | 1.333 |
11 | clk_cnt[1] | 3.842 | 0.995 |
11 | clk_cnt[5] | 3.593 | 1.333 |
11 | clk_cnt[7] | 4.059 | 0.862 |
11 | clk_cnt[24] | 2.631 | 0.865 |
9 | un1_clk_cntlto6_4 | 1.615 | 1.510 |
8 | clk_cnt11_0tt_m2_0_a2_3 | 1.265 | 2.152 |
8 | clk_cnt11_0_m1_e_sx | 1.185 | 0.853 |
Route Congestions Report:
Report Command:report_route_congestion -max_grids 10
GRID LOC | ROUTE CONGESTIONS |
---|---|
R11C10 | 0.333 |
R9C10 | 0.292 |
R9C11 | 0.292 |
R11C11 | 0.278 |
R11C9 | 0.278 |
R9C9 | 0.264 |
R11C12 | 0.194 |
R9C12 | 0.167 |
R9C13 | 0.167 |
R11C13 | 0.111 |
Timing Exceptions Report:
Setup Analysis Report
Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Hold Analysis Report
Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Recovery Analysis Report
Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Removal Analysis Report
Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Timing Constraints Report:
SDC Command Type | State | Detail Command |
---|