#Build: Synplify Pro (R) O-2018.09G-SP1, Build 099R, Feb 12 2019 #install: /share/gwsw/gowin_new/Gowin/Gowin_YunYuan_V1.9.xBeta/SynplifyPro #OS: Linux #Hostname: jinan9110.sdgowin.com # Fri Feb 15 17:22:56 2019 #Implementation: rev_1 Copyright (C) 1994-2019 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: O-2018.09G-SP1 Install: /share/gwsw/gowin_new/Gowin/Gowin_YunYuan_V1.9.xBeta/SynplifyPro OS: CentOS release 6.8 (Final) Hostname: jinan9110.sdgowin.com max virtual memory: unlimited (bytes) max user processes: 1024 max stack size: 10485760 (bytes) Implementation : rev_1 Synopsys HDL Compiler, Version comp2018q4p1, Build 115R, Built Feb 12 2019 09:44:44 @N: : | Running in 64-bit mode ###########################################################[ Copyright (C) 1994-2019 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: O-2018.09G-SP1 Install: /share/gwsw/gowin_new/Gowin/Gowin_YunYuan_V1.9.xBeta/SynplifyPro OS: CentOS release 6.8 (Final) Hostname: jinan9110.sdgowin.com max virtual memory: unlimited (bytes) max user processes: 1024 max stack size: 10485760 (bytes) Implementation : rev_1 Synopsys Verilog Compiler, Version comp2018q4p1, Build 115R, Built Feb 12 2019 09:44:44 @N: : | Running in 64-bit mode @N:CG1349 : | Running Verilog Compiler in System Verilog mode @N:CG1350 : | Running Verilog Compiler in Multiple File Compilation Unit mode @I::"/share/gwsw/gowin_new/Gowin/Gowin_YunYuan_V1.9.xBeta/SynplifyPro/lib/generic/gw2a.v" (library work) @I::"/share/gwsw/gowin_new/Gowin/Gowin_YunYuan_V1.9.xBeta/SynplifyPro/lib/vlog/hypermods.v" (library __hyper__lib__) @I::"/share/gwsw/gowin_new/Gowin/Gowin_YunYuan_V1.9.xBeta/SynplifyPro/lib/vlog/umr_capim.v" (library snps_haps) @I::"/share/gwsw/gowin_new/Gowin/Gowin_YunYuan_V1.9.xBeta/SynplifyPro/lib/vlog/scemi_objects.v" (library snps_haps) @I::"/share/gwsw/gowin_new/Gowin/Gowin_YunYuan_V1.9.xBeta/SynplifyPro/lib/vlog/scemi_pipes.svh" (library snps_haps) @I::"/share/gwsw/gowin_new/Gowin/Gowin_YunYuan_V1.9.xBeta/IDE/ipcore/INT_MULT_DIV/data/mdu.v" (library work) @I:"/share/gwsw/gowin_new/Gowin/Gowin_YunYuan_V1.9.xBeta/IDE/ipcore/INT_MULT_DIV/data/mdu.v":"/home/wenbo/Desktop/Integer_Multiply_Divider_pp/src/integer_multiply_divider/temp/integer_multiply_divider/define.v" (library work) @I:"/share/gwsw/gowin_new/Gowin/Gowin_YunYuan_V1.9.xBeta/IDE/ipcore/INT_MULT_DIV/data/mdu.v":"/share/gwsw/gowin_new/Gowin/Gowin_YunYuan_V1.9.xBeta/IDE/ipcore/INT_MULT_DIV/data/static_macro_define.v" (library work) @I:"/share/gwsw/gowin_new/Gowin/Gowin_YunYuan_V1.9.xBeta/IDE/ipcore/INT_MULT_DIV/data/mdu.v":"/home/wenbo/Desktop/Integer_Multiply_Divider_pp/src/integer_multiply_divider/temp/integer_multiply_divider/parameter.v" (library work) @I::"/share/gwsw/gowin_new/Gowin/Gowin_YunYuan_V1.9.xBeta/IDE/ipcore/INT_MULT_DIV/data/mdu_wrap.v" (library work) Verilog syntax check successful! Selecting top level module Integer_Multiply_Divider_Top Running optimization stage 1 on \(integerMultiplyDivider)/(Integer_Multiply_Divider_Top)_Z1 ....... @N:CG364 : mdu_wrap.v(3) | Synthesizing module Integer_Multiply_Divider_Top in library work. Running optimization stage 1 on Integer_Multiply_Divider_Top ....... Running optimization stage 2 on Integer_Multiply_Divider_Top ....... Running optimization stage 2 on \(integerMultiplyDivider)/(Integer_Multiply_Divider_Top)_Z1 ....... Extracted state machine for register state State machine has 7 reachable states with original encodings of: 000 001 010 011 100 101 110 For a summary of runtime and memory usage per design unit, please see file: ========================================================== Linked File: layer0.rt.csv At c_ver Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 80MB peak: 142MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. # Fri Feb 15 17:22:57 2019 ###########################################################] ###########################################################[ Copyright (C) 1994-2019 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: O-2018.09G-SP1 Install: /share/gwsw/gowin_new/Gowin/Gowin_YunYuan_V1.9.xBeta/SynplifyPro OS: CentOS release 6.8 (Final) Hostname: jinan9110.sdgowin.com max virtual memory: unlimited (bytes) max user processes: 1024 max stack size: 10485760 (bytes) Implementation : rev_1 Synopsys Synopsys Netlist Linker, Version comp2018q4p1, Build 115R, Built Feb 12 2019 09:44:44 @N: : | Running in 64-bit mode @N:NF107 : mdu_wrap.v(3) | Selected library: work cell: Integer_Multiply_Divider_Top view verilog as top level @N:NF107 : mdu_wrap.v(3) | Selected library: work cell: Integer_Multiply_Divider_Top view verilog as top level At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 68MB peak: 69MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. # Fri Feb 15 17:22:57 2019 ###########################################################] @END At c_hdl Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 3MB peak: 4MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. # Fri Feb 15 17:22:57 2019 ###########################################################] ###########################################################[ Copyright (C) 1994-2019 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: O-2018.09G-SP1 Install: /share/gwsw/gowin_new/Gowin/Gowin_YunYuan_V1.9.xBeta/SynplifyPro OS: CentOS release 6.8 (Final) Hostname: jinan9110.sdgowin.com max virtual memory: unlimited (bytes) max user processes: 1024 max stack size: 10485760 (bytes) Implementation : rev_1 Synopsys Synopsys Netlist Linker, Version comp2018q4p1, Build 115R, Built Feb 12 2019 09:44:44 @N: : | Running in 64-bit mode @N:NF107 : mdu_wrap.v(3) | Selected library: work cell: Integer_Multiply_Divider_Top view verilog as top level @N:NF107 : mdu_wrap.v(3) | Selected library: work cell: Integer_Multiply_Divider_Top view verilog as top level At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 68MB peak: 69MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. # Fri Feb 15 17:22:59 2019 ###########################################################] Premap Report # Fri Feb 15 17:22:59 2019 Copyright (C) 1994-2019 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: O-2018.09G-SP1 Install: /share/gwsw/gowin_new/Gowin/Gowin_YunYuan_V1.9.xBeta/SynplifyPro OS: CentOS release 6.8 (Final) Hostname: jinan9110.sdgowin.com max virtual memory: unlimited (bytes) max user processes: 1024 max stack size: 10485760 (bytes) Implementation : rev_1 Synopsys Generic Technology Pre-mapping, Version mapgw, Build 1290R, Built Feb 12 2019 09:57:51 Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 99MB) @A:MF827 : | No constraint file specified. @N:MF284 : | Setting synthesis effort to medium for the design Linked File: integer_multiply_divider_scck.rpt Printing clock summary report in "/home/wenbo/Desktop/Integer_Multiply_Divider_pp/src/integer_multiply_divider/temp/integer_multiply_divider/rev_1/integer_multiply_divider_scck.rpt" file @N:MF916 : | Option synthesis_strategy=base is enabled. @N:MF248 : | Running in 64-bit mode. @N:MF666 : | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 102MB) Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 102MB) Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 102MB peak: 103MB) Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 114MB peak: 116MB) @N:MF284 : | Setting synthesis effort to medium for the design @N:MH105 : | UMR3 is only supported for HAPS-80. @N:MH105 : | UMR3 is only supported for HAPS-80. Encoding state machine state[6:0] (in view: work.\\\(integerMultiplyDivider\)\/\(Integer_Multiply_Divider_Top\)_Z1(verilog)) original code -> new code 000 -> 0000001 001 -> 0000010 010 -> 0000100 011 -> 0001000 100 -> 0010000 101 -> 0100000 110 -> 1000000 Starting clock optimization phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 193MB peak: 193MB) Finished clock optimization phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 192MB peak: 193MB) Starting clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 192MB peak: 193MB) Finished clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 192MB peak: 193MB) Finished netlist restructuring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 192MB peak: 193MB) Clock Summary ****************** Start Requested Requested Clock Clock Clock Level Clock Frequency Period Type Group Load ----------------------------------------------------------------------------------------------------------------------- 0 - Integer_Multiply_Divider_Top|clk 199.9 MHz 5.003 inferred Autoconstr_clkgroup_0 167 ======================================================================================================================= Clock Load Summary *********************** Clock Source Clock Pin Non-clock Pin Non-clock Pin Clock Load Pin Seq Example Seq Example Comb Example ---------------------------------------------------------------------------------------------------------------------- Integer_Multiply_Divider_Top|clk 167 clk(port) u_mdu.func_reg[3:0].C - - ====================================================================================================================== ICG Latch Removal Summary: Number of ICG latches removed: 0 Number of ICG latches not removed: 0 @S |Clock Optimization Summary #### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[ 1 non-gated/non-generated clock tree(s) driving 167 clock pin(s) of sequential element(s) 0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s) 0 instances converted, 0 sequential instances remain driven by gated/generated clocks =========================== Non-Gated/Non-Generated Clocks ============================ Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance --------------------------------------------------------------------------------------- ClockId_0_0 clk Unconstrained_port 167 ENCRYPTED ======================================================================================= ##### END OF CLOCK OPTIMIZATION REPORT ###### @N:FX1143 : | Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized. Finished Pre Mapping Phase. @N:BN225 : | Writing default property annotation file /home/wenbo/Desktop/Integer_Multiply_Divider_pp/src/integer_multiply_divider/temp/integer_multiply_divider/rev_1/integer_multiply_divider.sap. Starting constraint checker (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 192MB peak: 193MB) Finished constraint checker preprocessing (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 192MB peak: 193MB) None None Finished constraint checker (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 192MB peak: 193MB) Pre-mapping successful! At Mapper Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 108MB peak: 193MB) Process took 0h:00m:02s realtime, 0h:00m:02s cputime # Fri Feb 15 17:23:01 2019 ###########################################################] Map & Optimize Report # Fri Feb 15 17:23:01 2019 Copyright (C) 1994-2019 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: O-2018.09G-SP1 Install: /share/gwsw/gowin_new/Gowin/Gowin_YunYuan_V1.9.xBeta/SynplifyPro OS: CentOS release 6.8 (Final) Hostname: jinan9110.sdgowin.com max virtual memory: unlimited (bytes) max user processes: 1024 max stack size: 10485760 (bytes) Implementation : rev_1 Synopsys Generic Technology Mapper, Version mapgw, Build 1290R, Built Feb 12 2019 09:57:51 Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 99MB) @N:MF284 : | Setting synthesis effort to medium for the design @N:MF916 : | Option synthesis_strategy=base is enabled. @N:MF248 : | Running in 64-bit mode. @N:MF666 : | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 100MB) Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 100MB) Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 102MB) Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 115MB) @N:MF284 : | Setting synthesis effort to medium for the design Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 191MB peak: 192MB) Available hyper_sources - for debug and ip models None Found @N:MT206 : | Auto Constrain mode is enabled Finished RTL optimizations (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 193MB peak: 194MB) Starting factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 196MB peak: 198MB) Finished factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 220MB peak: 220MB) Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 210MB peak: 245MB) Starting Early Timing Optimization (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 211MB peak: 245MB) Finished Early Timing Optimization (Real Time elapsed 0h:00m:07s; CPU Time elapsed 0h:00m:07s; Memory used current: 216MB peak: 245MB) Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:07s; CPU Time elapsed 0h:00m:07s; Memory used current: 215MB peak: 245MB) Finished preparing to map (Real Time elapsed 0h:00m:08s; CPU Time elapsed 0h:00m:08s; Memory used current: 214MB peak: 245MB) Finished technology mapping (Real Time elapsed 0h:00m:08s; CPU Time elapsed 0h:00m:08s; Memory used current: 249MB peak: 253MB) Pass CPU time Worst Slack Luts / Registers ------------------------------------------------------------ 1 0h:00m:09s -3.43ns 1487 / 166 2 0h:00m:09s -3.43ns 1440 / 166 3 0h:00m:09s -3.43ns 1442 / 166 4 0h:00m:09s -3.43ns 1442 / 166 Timing driven replication report Added 42 Registers via timing driven replication Added 39 LUTs via timing driven replication 5 0h:00m:09s -2.93ns 1488 / 208 6 0h:00m:09s -3.13ns 1488 / 208 7 0h:00m:09s -2.99ns 1490 / 208 8 0h:00m:09s -2.99ns 1491 / 208 9 0h:00m:10s -2.47ns 1502 / 208 10 0h:00m:10s -2.22ns 1503 / 208 11 0h:00m:10s -2.22ns 1509 / 208 Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:10s; CPU Time elapsed 0h:00m:10s; Memory used current: 254MB peak: 255MB) @N:FX164 : | The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute. Finished restoring hierarchy (Real Time elapsed 0h:00m:11s; CPU Time elapsed 0h:00m:11s; Memory used current: 253MB peak: 255MB) Start Writing Netlists (Real Time elapsed 0h:00m:11s; CPU Time elapsed 0h:00m:11s; Memory used current: 181MB peak: 256MB) Writing Analyst data base /home/wenbo/Desktop/Integer_Multiply_Divider_pp/src/integer_multiply_divider/temp/integer_multiply_divider/rev_1/synwork/integer_multiply_divider_m.srm Finished Writing Netlist Databases (Real Time elapsed 0h:00m:12s; CPU Time elapsed 0h:00m:12s; Memory used current: 251MB peak: 256MB) Writing Verilog Simulation files Writing scf file... (Real Time elapsed 0h:00m:14s; CPU Time elapsed 0h:00m:13s; Memory used current: 252MB peak: 256MB) @N:BW103 : | The default time unit for the Synopsys Constraint File (SDC or FDC) is 1ns. @N:BW107 : | Synopsys Constraint File capacitance units using default value of 1pF Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:14s; CPU Time elapsed 0h:00m:14s; Memory used current: 250MB peak: 256MB) Start final timing analysis (Real Time elapsed 0h:00m:15s; CPU Time elapsed 0h:00m:14s; Memory used current: 250MB peak: 256MB) @W:MT420 : | Found inferred clock Integer_Multiply_Divider_Top|clk with period 7.71ns. Please declare a user-defined clock on port clk. ##### START OF TIMING REPORT #####[ # Timing report written on Fri Feb 15 17:23:16 2019 # Top view: Integer_Multiply_Divider_Top Requested Frequency: 129.6 MHz Wire load mode: top Paths requested: 5 Constraint File(s): @N:MT320 : | This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report. @N:MT322 : | Clock constraints include only register-to-register paths associated with each individual clock. Performance Summary ******************* Worst slack in design: -1.361 Requested Estimated Requested Estimated Clock Clock Starting Clock Frequency Frequency Period Period Slack Type Group ------------------------------------------------------------------------------------------------------------------------------------------ Integer_Multiply_Divider_Top|clk 129.6 MHz 110.2 MHz 7.714 9.075 -1.361 inferred Autoconstr_clkgroup_0 System 150.0 MHz NA 6.667 NA 7.118 system system_clkgroup ========================================================================================================================================== Estimated period and frequency reported as NA means no slack depends directly on the clock waveform Clock Relationships ******************* Clocks | rise to rise | fall to fall | rise to fall | fall to rise ----------------------------------------------------------------------------------------------------------------------------------------------------------- Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack ----------------------------------------------------------------------------------------------------------------------------------------------------------- System Integer_Multiply_Divider_Top|clk | 7.714 7.118 | No paths - | No paths - | No paths - Integer_Multiply_Divider_Top|clk Integer_Multiply_Divider_Top|clk | 7.714 -1.361 | No paths - | No paths - | No paths - =========================================================================================================================================================== Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups. Interface Information ********************* No IO constraint found ==================================== Detailed Report for Clock: Integer_Multiply_Divider_Top|clk ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------------------------------------------------- u_mdu.div_shift_number[1] Integer_Multiply_Divider_Top|clk DFFRE Q div_shift_number[1] 0.243 -1.361 u_mdu.div_shift_number[0] Integer_Multiply_Divider_Top|clk DFFRE Q div_shift_number[0] 0.243 -1.337 u_mdu.reg1[0] Integer_Multiply_Divider_Top|clk DFFE Q reg1[0] 0.243 -1.262 u_mdu.func_reg_fast[2] Integer_Multiply_Divider_Top|clk DFFE Q func_reg_fast[2] 0.243 -1.240 u_mdu.reg1[1] Integer_Multiply_Divider_Top|clk DFFE Q reg1[1] 0.243 -1.226 u_mdu.reg1[2] Integer_Multiply_Divider_Top|clk DFFE Q reg1[2] 0.243 -1.192 u_mdu.reg1[3] Integer_Multiply_Divider_Top|clk DFFE Q reg1[3] 0.243 -1.157 u_mdu.rs1_mul[0] Integer_Multiply_Divider_Top|clk DFFRE Q rs1_mul[0] 0.243 -1.153 u_mdu.reg1[4] Integer_Multiply_Divider_Top|clk DFFE Q reg1[4] 0.243 -1.121 u_mdu.rs1_mul[1] Integer_Multiply_Divider_Top|clk DFFRE Q rs1_mul[1] 0.243 -1.119 =============================================================================================================================== Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ---------------------------------------------------------------------------------------------------------------------- u_mdu.reg0[28] Integer_Multiply_Divider_Top|clk DFFE D reg0_nx[28] 7.653 -1.361 u_mdu.reg0_fast[28] Integer_Multiply_Divider_Top|clk DFFE D reg0_nx_fast[28] 7.653 -1.361 u_mdu.reg0[30] Integer_Multiply_Divider_Top|clk DFFE D reg0_nx[30] 7.653 -1.340 u_mdu.reg0[31] Integer_Multiply_Divider_Top|clk DFFE D reg0_nx[31] 7.653 -1.340 u_mdu.reg0_31_rep1 Integer_Multiply_Divider_Top|clk DFFE D reg0_nx_rep1[31] 7.653 -1.340 u_mdu.reg0_fast[30] Integer_Multiply_Divider_Top|clk DFFE D reg0_nx_fast[30] 7.653 -1.340 u_mdu.reg0_fast[31] Integer_Multiply_Divider_Top|clk DFFE D reg0_nx_fast[31] 7.653 -1.340 u_mdu.reg0[7] Integer_Multiply_Divider_Top|clk DFFE D reg0_nx[7] 7.653 -1.262 u_mdu.reg0[64] Integer_Multiply_Divider_Top|clk DFFE D reg0_nx[64] 7.653 -1.031 u_mdu.reg0[29] Integer_Multiply_Divider_Top|clk DFFE D reg0_nx[29] 7.653 -0.986 ====================================================================================================================== Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 7.714 - Setup time: 0.061 + Clock delay at ending point: 0.000 (ideal) = Required time: 7.653 - Propagation time: 9.014 - Clock delay at starting point: 0.000 (ideal) = Slack (critical) : -1.361 Number of logic level(s): 8 Starting point: u_mdu.div_shift_number[1] / Q Ending point: u_mdu.reg0[28] / D The start point is clocked by Integer_Multiply_Divider_Top|clk [rising] on pin CLK The end point is clocked by Integer_Multiply_Divider_Top|clk [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) --------------------------------------------------------------------------------------------- u_mdu.div_shift_number[1] DFFRE Q Out 0.243 0.243 - div_shift_number[1] Net - - 1.062 - 114 u_mdu.m4_0_03_1_0 LUT4 I1 In - 1.305 - u_mdu.m4_0_03_1_0 LUT4 F Out 0.570 1.875 - m4_0_03_1_0 Net - - 0.535 - 2 u_mdu.m4_0_03_0_0_RNI1JV1 LUT2 I1 In - 2.410 - u_mdu.m4_0_03_0_0_RNI1JV1 LUT2 F Out 0.570 2.980 - m4_0_03 Net - - 0.535 - 3 u_mdu.m12_2_03_m1_e_1 LUT4 I1 In - 3.515 - u_mdu.m12_2_03_m1_e_1 LUT4 F Out 0.570 4.085 - m12_2_03_m1_e_1 Net - - 0.535 - 2 u_mdu.m12_2_03_m1_e_0_RNI7HT5 LUT2 I1 In - 4.620 - u_mdu.m12_2_03_m1_e_0_RNI7HT5 LUT2 F Out 0.570 5.190 - m12_2_03_N_3_mux Net - - 0.535 - 3 u_mdu.m28_4_01 LUT4 I1 In - 5.725 - u_mdu.m28_4_01 LUT4 F Out 0.570 6.295 - m28_4_01 Net - - 0.401 - 1 u_mdu.reg0_exe_nx_m2[28] LUT4 I2 In - 6.696 - u_mdu.reg0_exe_nx_m2[28] LUT4 F Out 0.462 7.158 - reg0_exe_nx_m2[28] Net - - 0.401 - 1 u_mdu.reg0_exe_nx[28] LUT4 I3 In - 7.559 - u_mdu.reg0_exe_nx[28] LUT4 F Out 0.371 7.930 - reg0_exe_nx[28] Net - - 0.535 - 2 u_mdu.reg0_nx[28] LUT4 I0 In - 8.465 - u_mdu.reg0_nx[28] LUT4 F Out 0.549 9.014 - reg0_nx[28] Net - - 0.000 - 1 u_mdu.reg0[28] DFFE D In - 9.014 - ============================================================================================= Total path delay (propagation time + setup) of 9.075 is 4.536(50.0%) logic and 4.539(50.0%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 2: Requested Period: 7.714 - Setup time: 0.061 + Clock delay at ending point: 0.000 (ideal) = Required time: 7.653 - Propagation time: 9.014 - Clock delay at starting point: 0.000 (ideal) = Slack (critical) : -1.361 Number of logic level(s): 8 Starting point: u_mdu.div_shift_number[1] / Q Ending point: u_mdu.reg0_fast[28] / D The start point is clocked by Integer_Multiply_Divider_Top|clk [rising] on pin CLK The end point is clocked by Integer_Multiply_Divider_Top|clk [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) --------------------------------------------------------------------------------------------- u_mdu.div_shift_number[1] DFFRE Q Out 0.243 0.243 - div_shift_number[1] Net - - 1.062 - 114 u_mdu.m4_0_03_1_0 LUT4 I1 In - 1.305 - u_mdu.m4_0_03_1_0 LUT4 F Out 0.570 1.875 - m4_0_03_1_0 Net - - 0.535 - 2 u_mdu.m4_0_03_0_0_RNI1JV1 LUT2 I1 In - 2.410 - u_mdu.m4_0_03_0_0_RNI1JV1 LUT2 F Out 0.570 2.980 - m4_0_03 Net - - 0.535 - 3 u_mdu.m12_2_03_m1_e_1 LUT4 I1 In - 3.515 - u_mdu.m12_2_03_m1_e_1 LUT4 F Out 0.570 4.085 - m12_2_03_m1_e_1 Net - - 0.535 - 2 u_mdu.m12_2_03_m1_e_0_RNI7HT5 LUT2 I1 In - 4.620 - u_mdu.m12_2_03_m1_e_0_RNI7HT5 LUT2 F Out 0.570 5.190 - m12_2_03_N_3_mux Net - - 0.535 - 3 u_mdu.m28_4_01 LUT4 I1 In - 5.725 - u_mdu.m28_4_01 LUT4 F Out 0.570 6.295 - m28_4_01 Net - - 0.401 - 1 u_mdu.reg0_exe_nx_m2[28] LUT4 I2 In - 6.696 - u_mdu.reg0_exe_nx_m2[28] LUT4 F Out 0.462 7.158 - reg0_exe_nx_m2[28] Net - - 0.401 - 1 u_mdu.reg0_exe_nx[28] LUT4 I3 In - 7.559 - u_mdu.reg0_exe_nx[28] LUT4 F Out 0.371 7.930 - reg0_exe_nx[28] Net - - 0.535 - 2 u_mdu.reg0_nx_fast[28] LUT4 I0 In - 8.465 - u_mdu.reg0_nx_fast[28] LUT4 F Out 0.549 9.014 - reg0_nx_fast[28] Net - - 0.000 - 1 u_mdu.reg0_fast[28] DFFE D In - 9.014 - ============================================================================================= Total path delay (propagation time + setup) of 9.075 is 4.536(50.0%) logic and 4.539(50.0%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 3: Requested Period: 7.714 - Setup time: 0.061 + Clock delay at ending point: 0.000 (ideal) = Required time: 7.653 - Propagation time: 8.993 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -1.340 Number of logic level(s): 8 Starting point: u_mdu.div_shift_number[1] / Q Ending point: u_mdu.reg0[30] / D The start point is clocked by Integer_Multiply_Divider_Top|clk [rising] on pin CLK The end point is clocked by Integer_Multiply_Divider_Top|clk [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------ u_mdu.div_shift_number[1] DFFRE Q Out 0.243 0.243 - div_shift_number[1] Net - - 1.062 - 114 u_mdu.m6_0_03_1_0 LUT4 I1 In - 1.305 - u_mdu.m6_0_03_1_0 LUT4 F Out 0.570 1.875 - m6_0_03_1_0 Net - - 0.535 - 2 u_mdu.m6_0_03_0_0_RNI5NGM LUT2 I1 In - 2.410 - u_mdu.m6_0_03_0_0_RNI5NGM LUT2 F Out 0.570 2.980 - m6_0_03 Net - - 0.535 - 3 u_mdu.m14_2_03_0_0 LUT4 I1 In - 3.515 - u_mdu.m14_2_03_0_0 LUT4 F Out 0.570 4.085 - m14_2_03_0_0 Net - - 0.535 - 2 u_mdu.m14_2_03_0_0_RNI70O1 LUT2 I0 In - 4.620 - u_mdu.m14_2_03_0_0_RNI70O1 LUT2 F Out 0.549 5.169 - m14_2_03 Net - - 0.535 - 3 u_mdu.m30_4_01 LUT4 I1 In - 5.704 - u_mdu.m30_4_01 LUT4 F Out 0.570 6.274 - m30_4_01 Net - - 0.401 - 1 u_mdu.reg0_exe_nx_m2[30] LUT4 I2 In - 6.675 - u_mdu.reg0_exe_nx_m2[30] LUT4 F Out 0.462 7.137 - reg0_exe_nx_m2[30] Net - - 0.401 - 1 u_mdu.reg0_exe_nx[30] LUT4 I3 In - 7.538 - u_mdu.reg0_exe_nx[30] LUT4 F Out 0.371 7.909 - reg0_exe_nx[30] Net - - 0.535 - 2 u_mdu.reg0_nx[30] LUT4 I0 In - 8.444 - u_mdu.reg0_nx[30] LUT4 F Out 0.549 8.993 - reg0_nx[30] Net - - 0.000 - 1 u_mdu.reg0[30] DFFE D In - 8.993 - ========================================================================================== Total path delay (propagation time + setup) of 9.054 is 4.515(49.9%) logic and 4.539(50.1%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 4: Requested Period: 7.714 - Setup time: 0.061 + Clock delay at ending point: 0.000 (ideal) = Required time: 7.653 - Propagation time: 8.993 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -1.340 Number of logic level(s): 8 Starting point: u_mdu.div_shift_number[1] / Q Ending point: u_mdu.reg0[31] / D The start point is clocked by Integer_Multiply_Divider_Top|clk [rising] on pin CLK The end point is clocked by Integer_Multiply_Divider_Top|clk [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------ u_mdu.div_shift_number[1] DFFRE Q Out 0.243 0.243 - div_shift_number[1] Net - - 1.062 - 114 u_mdu.m7_0_03_1_0 LUT4 I1 In - 1.305 - u_mdu.m7_0_03_1_0 LUT4 F Out 0.570 1.875 - m7_0_03_1_0 Net - - 0.535 - 2 u_mdu.m7_0_03_0_0_RNI79P LUT2 I1 In - 2.410 - u_mdu.m7_0_03_0_0_RNI79P LUT2 F Out 0.570 2.980 - m7_0_03 Net - - 0.535 - 3 u_mdu.m15_2_03_0_0 LUT4 I1 In - 3.515 - u_mdu.m15_2_03_0_0 LUT4 F Out 0.570 4.085 - m15_2_03_0_0 Net - - 0.535 - 2 u_mdu.m15_2_03_0_0_RNI9I0C LUT2 I0 In - 4.620 - u_mdu.m15_2_03_0_0_RNI9I0C LUT2 F Out 0.549 5.169 - m15_2_03 Net - - 0.535 - 3 u_mdu.m31_4_01 LUT4 I1 In - 5.704 - u_mdu.m31_4_01 LUT4 F Out 0.570 6.274 - m31_4_01 Net - - 0.401 - 1 u_mdu.reg0_exe_nx_m2[31] LUT4 I2 In - 6.675 - u_mdu.reg0_exe_nx_m2[31] LUT4 F Out 0.462 7.137 - reg0_exe_nx_m2[31] Net - - 0.401 - 1 u_mdu.reg0_exe_nx[31] LUT4 I3 In - 7.538 - u_mdu.reg0_exe_nx[31] LUT4 F Out 0.371 7.909 - reg0_exe_nx[31] Net - - 0.535 - 3 u_mdu.reg0_nx[31] LUT4 I0 In - 8.444 - u_mdu.reg0_nx[31] LUT4 F Out 0.549 8.993 - reg0_nx[31] Net - - 0.000 - 1 u_mdu.reg0[31] DFFE D In - 8.993 - ========================================================================================== Total path delay (propagation time + setup) of 9.054 is 4.515(49.9%) logic and 4.539(50.1%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 5: Requested Period: 7.714 - Setup time: 0.061 + Clock delay at ending point: 0.000 (ideal) = Required time: 7.653 - Propagation time: 8.993 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -1.340 Number of logic level(s): 8 Starting point: u_mdu.div_shift_number[1] / Q Ending point: u_mdu.reg0[28] / D The start point is clocked by Integer_Multiply_Divider_Top|clk [rising] on pin CLK The end point is clocked by Integer_Multiply_Divider_Top|clk [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) --------------------------------------------------------------------------------------------- u_mdu.div_shift_number[1] DFFRE Q Out 0.243 0.243 - div_shift_number[1] Net - - 1.062 - 114 u_mdu.m4_0_03_0_0 LUT4 I1 In - 1.305 - u_mdu.m4_0_03_0_0 LUT4 F Out 0.570 1.875 - m4_0_03_0_0 Net - - 0.535 - 2 u_mdu.m4_0_03_0_0_RNI1JV1 LUT2 I0 In - 2.410 - u_mdu.m4_0_03_0_0_RNI1JV1 LUT2 F Out 0.549 2.959 - m4_0_03 Net - - 0.535 - 3 u_mdu.m12_2_03_m1_e_1 LUT4 I1 In - 3.494 - u_mdu.m12_2_03_m1_e_1 LUT4 F Out 0.570 4.064 - m12_2_03_m1_e_1 Net - - 0.535 - 2 u_mdu.m12_2_03_m1_e_0_RNI7HT5 LUT2 I1 In - 4.599 - u_mdu.m12_2_03_m1_e_0_RNI7HT5 LUT2 F Out 0.570 5.169 - m12_2_03_N_3_mux Net - - 0.535 - 3 u_mdu.m28_4_01 LUT4 I1 In - 5.704 - u_mdu.m28_4_01 LUT4 F Out 0.570 6.274 - m28_4_01 Net - - 0.401 - 1 u_mdu.reg0_exe_nx_m2[28] LUT4 I2 In - 6.675 - u_mdu.reg0_exe_nx_m2[28] LUT4 F Out 0.462 7.137 - reg0_exe_nx_m2[28] Net - - 0.401 - 1 u_mdu.reg0_exe_nx[28] LUT4 I3 In - 7.538 - u_mdu.reg0_exe_nx[28] LUT4 F Out 0.371 7.909 - reg0_exe_nx[28] Net - - 0.535 - 2 u_mdu.reg0_nx[28] LUT4 I0 In - 8.444 - u_mdu.reg0_nx[28] LUT4 F Out 0.549 8.993 - reg0_nx[28] Net - - 0.000 - 1 u_mdu.reg0[28] DFFE D In - 8.993 - ============================================================================================= Total path delay (propagation time + setup) of 9.054 is 4.515(49.9%) logic and 4.539(50.1%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ==================================== Detailed Report for Clock: System ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock --------------------------------------------------------------------------------- u_mdu.rstn_RNI7UU System INV O rstn_i 0.000 7.118 ================================================================================= Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ---------------------------------------------------------------------------------- u_mdu.state[0] System DFFP PRESET rstn_i 7.653 7.118 ================================================================================== Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 7.714 - Setup time: 0.061 + Clock delay at ending point: 0.000 (ideal) = Required time: 7.653 - Propagation time: 0.535 - Clock delay at starting point: 0.000 (ideal) - Estimated clock delay at start point: -0.000 = Slack (non-critical) : 7.118 Number of logic level(s): 0 Starting point: u_mdu.rstn_RNI7UU / O Ending point: u_mdu.state[0] / PRESET The start point is clocked by System [rising] The end point is clocked by Integer_Multiply_Divider_Top|clk [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ---------------------------------------------------------------------------------- u_mdu.rstn_RNI7UU INV O Out 0.000 0.000 - rstn_i Net - - 0.535 - 14 u_mdu.state[0] DFFP PRESET In - 0.535 - ================================================================================== Total path delay (propagation time + setup) of 0.596 is 0.061(10.2%) logic and 0.535(89.8%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ##### END OF TIMING REPORT #####] Timing exceptions that could not be applied None Finished final timing analysis (Real Time elapsed 0h:00m:15s; CPU Time elapsed 0h:00m:14s; Memory used current: 251MB peak: 256MB) Finished timing report (Real Time elapsed 0h:00m:15s; CPU Time elapsed 0h:00m:14s; Memory used current: 251MB peak: 256MB) --------------------------------------- Resource Usage Report for Integer_Multiply_Divider_Top Mapping to part: gw2a_55pbga484-8 Cell usage: ALU 208 uses DFFC 7 uses DFFCE 6 uses DFFE 150 uses DFFP 1 use DFFRE 43 uses DFFSE 1 use GSR 1 use INV 1 use MUX2_LUT5 68 uses LUT2 132 uses LUT3 458 uses LUT4 817 uses I/O Register bits: 0 Register bits not including I/Os: 208 of 41040 (0%) Total load per clock: Integer_Multiply_Divider_Top|clk: 208 @S |Mapping Summary: Total LUTs: 1407 (2%) Mapper successful! At Mapper Exit (Real Time elapsed 0h:00m:15s; CPU Time elapsed 0h:00m:15s; Memory used current: 49MB peak: 256MB) Process took 0h:00m:15s realtime, 0h:00m:15s cputime # Fri Feb 15 17:23:17 2019 ###########################################################]