Timing Messages

Report Title	Gowin Timing Analysis Report
Design File	F:/user-bak/Users/FDELL/Desktop/IP/Integer_Multiply-Divider/ref_design/REM/Integer_Multiply_Divider_pp/project/impl/synplify/rev_1/Integer_Multiply_Divider_pp.vm
Physical Constraints File	F:\user-bak\Users\FDELL\Desktop\IP\Integer_Multiply-Divider\ref_design\REM\Integer_Multiply_Divider_pp\project\src\Integer_Multiply_Divider_pp.cst
Timing Constraints File	---
GOWIN version	v1.9.0Beta
Part Number	GW2A-LV55PG484C8/I7
Created Time	Tue Feb 19 18:07:38 2019
Legal Announcement	Copyright (C)2014-2019 Gowin Semiconductor Corporation. All rights reserved.

Timing Summaries

STA Tool Run Summary:

Setup Delay Model	Slow 0.95V 85C
Hold Delay Model	Fast 1.05V 0C
Numbers of Paths Analyzed	2793
Numbers of Endpoints Analyzed	6739
Numbers of Falling Endpoints	1
Numbers of Setup Violated Endpoints	0
Numbers of Hold Violated Endpoints	0

Clock Summary:

Clock Name	Type	Period	Frequency(MHz)	Rise	Fall	Source	Master	Objects
DEFAULT_CLK	Base	10.000	100.000	0.000	5.000

Max Frequency Summary:

NO.	Clock Name	Fmax	Entity
1	DEFAULT_CLK	106.967(MHz)	TOP

Total Negative Slack Summary:

Clock Name	Analysis Type	Endpoints TNS	Number of Endpoints
DEFAULT_CLK	Setup	0.000	0
DEFAULT_CLK	Hold	0.000	0

Timing Details

Path Slacks Table:

Setup Paths Table

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	0.651	Mdu/u_mdu/div_shift_number_Z[1]/Q	Mdu/u_mdu/reg0_fast_Z[30]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	0.000	9.114
2	0.651	Mdu/u_mdu/div_shift_number_Z[1]/Q	Mdu/u_mdu/reg0_Z[30]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	0.000	9.114
3	0.713	Mdu/u_mdu/div_shift_number_Z[0]/Q	Mdu/u_mdu/reg0_fast_Z[23]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	0.000	9.052
4	0.811	Mdu/u_mdu/div_shift_number_Z[0]/Q	Mdu/u_mdu/reg0_Z[23]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	0.000	8.954
5	0.855	Mdu/u_mdu/reg0_fast_Z[17]/Q	Mdu/u_mdu/reg0_Z[31]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	0.000	8.910
6	0.865	Mdu/u_mdu/reg0_fast_Z[17]/Q	Mdu/u_mdu/reg0_fast_Z[31]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	0.000	8.900
7	0.899	Mdu/u_mdu/div_shift_number_Z[0]/Q	Mdu/u_mdu/reg0_Z[56]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	0.000	8.866
8	0.924	Mdu/u_mdu/div_shift_number_Z[1]/Q	Mdu/u_mdu/reg0_Z[62]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	0.000	8.841
9	1.021	Mdu/u_mdu/reg1_Z[2]/Q	Mdu/u_mdu/div_shift_number_Z[5]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	0.000	8.744
10	1.108	Mdu/u_mdu/reg0_fast_Z[17]/Q	Mdu/u_mdu/reg0_31_rep1_Z/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	0.000	8.657
11	1.168	Mdu/u_mdu/div_shift_number_Z[1]/Q	Mdu/u_mdu/reg0_fast_Z[14]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	0.000	8.597
12	1.168	Mdu/u_mdu/div_shift_number_Z[1]/Q	Mdu/u_mdu/reg0_Z[14]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	0.000	8.597
13	1.180	Mdu/u_mdu/div_shift_number_Z[1]/Q	Mdu/u_mdu/reg0_Z[46]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	0.000	8.585
14	1.181	Mdu/u_mdu/reg1_Z[2]/Q	Mdu/u_mdu/reg0_Z[7]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	0.000	8.584
15	1.182	Mdu/u_mdu/reg0_6_rep1_Z/Q	Mdu/u_mdu/reg0_6_rep1_Z/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	0.000	8.583
16	1.182	Mdu/u_mdu/reg0_6_rep1_Z/Q	Mdu/u_mdu/reg0_Z[6]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	0.000	8.583
17	1.182	Mdu/u_mdu/div_shift_number_Z[2]/Q	Mdu/u_mdu/reg0_Z[41]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	0.000	8.583
18	1.203	Mdu/u_mdu/reg0_6_rep1_Z/Q	Mdu/u_mdu/reg0_fast_Z[6]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	0.000	8.562
19	1.206	Mdu/u_mdu/div_shift_number_Z[2]/Q	Mdu/u_mdu/reg0_Z[57]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	0.000	8.559
20	1.210	Mdu/u_mdu/reg1_Z[2]/Q	Mdu/u_mdu/div_shift_number_Z[4]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	0.000	8.555
21	1.213	Mdu/u_mdu/reg0_fast_Z[17]/Q	Mdu/u_mdu/reg0_fast_Z[24]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	0.000	8.552
22	1.218	Mdu/u_mdu/div_shift_number_Z[2]/Q	Mdu/u_mdu/reg0_Z[61]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	0.000	8.547
23	1.238	Mdu/u_mdu/div_shift_number_Z[2]/Q	Mdu/u_mdu/reg0_Z[53]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	0.000	8.527
24	1.246	Mdu/u_mdu/reg1_Z[2]/Q	Mdu/u_mdu/div_shift_number_Z[3]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	0.000	8.519
25	1.256	Mdu/u_mdu/reg0_6_rep1_Z/Q	Mdu/u_mdu/reg0_11_rep1_Z/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	0.000	8.509

Hold Paths Table

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	0.074	u_la0_top/u_ao_mem_ctrl/data_reg_Z[37]/Q	u_la0_top/u_ao_mem_ctrl/mem_mem_0_18/DI1	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.000	0.000	0.323
2	0.076	u_la0_top/u_ao_mem_ctrl/data_reg_Z[36]/Q	u_la0_top/u_ao_mem_ctrl/mem_mem_0_18/DI0	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.000	0.000	0.325
3	0.215	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8]/Q	u_la0_top/u_ao_mem_ctrl/mem_mem_0_21/ADA9	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.000	0.000	0.333
4	0.215	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[11]/Q	u_la0_top/u_ao_mem_ctrl/mem_mem_0_13/ADA12	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.000	0.000	0.333
5	0.230	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[12]/Q	u_la0_top/u_ao_mem_ctrl/mem_mem_0_13/ADA13	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.000	0.000	0.348
6	0.232	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[6]/Q	u_la0_top/u_ao_mem_ctrl/mem_mem_0_13/ADA7	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.000	0.000	0.350
7	0.324	u_la0_top/u_ao_mem_ctrl/data_reg_Z[90]/Q	u_la0_top/u_ao_mem_ctrl/mem_mem_0_45/DI0	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.000	0.000	0.573
8	0.335	cnt_1_Z[9]/Q	memr_memr_0_8/ADB10	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.000	0.000	0.453
9	0.335	u_la0_top/u_ao_mem_ctrl/data_reg_Z[91]/Q	u_la0_top/u_ao_mem_ctrl/mem_mem_0_45/DI1	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.000	0.000	0.584
10	0.341	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[4]/Q	u_la0_top/u_ao_mem_ctrl/mem_mem_0_18/ADA5	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.000	0.000	0.459
11	0.341	Mdu/u_mdu/reg0[33]/Q	memr_memr_0_0/DI0	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.000	0.000	0.590
12	0.345	cnt_1_Z[4]/Q	memr_memr_0_6/ADB5	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.000	0.000	0.463
13	0.345	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[7]/Q	u_la0_top/u_ao_mem_ctrl/mem_mem_0_21/ADA8	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.000	0.000	0.463
14	0.349	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[5]/Q	u_la0_top/u_ao_mem_ctrl/mem_mem_0_13/ADA6	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.000	0.000	0.467
15	0.352	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[1]/Q	u_la0_top/u_ao_mem_ctrl/mem_mem_0_21/ADA2	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.000	0.000	0.470
16	0.353	cnt_1_Z[9]/Q	memr_memr_0_6/ADB10	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.000	0.000	0.471
17	0.353	cnt_1_Z[12]/Q	memr_memr_0_6/ADB13	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.000	0.000	0.471
18	0.354	cnt_1_Z[8]/Q	memr_memr_0_6/ADB9	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.000	0.000	0.472
19	0.357	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[4]/Q	u_la0_top/u_ao_mem_ctrl/mem_mem_0_13/ADA5	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.000	0.000	0.475
20	0.363	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[3]/Q	u_la0_top/u_ao_mem_ctrl/mem_mem_0_13/ADA4	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.000	0.000	0.481
21	0.363	u_la0_top/u_ao_mem_ctrl/data_reg_Z[48]/Q	u_la0_top/u_ao_mem_ctrl/mem_mem_0_24/DI0	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.000	0.000	0.612
22	0.363	u_la0_top/u_ao_mem_ctrl/data_reg_Z[42]/Q	u_la0_top/u_ao_mem_ctrl/mem_mem_0_21/DI0	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.000	0.000	0.612
23	0.364	cnt_1_Z[3]/Q	memr_memr_0_8/ADB4	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.000	0.000	0.482
24	0.364	cnt_1_Z[8]/Q	memr_memr_0_5/ADB9	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.000	0.000	0.482
25	0.366	cnt_1_Z[8]/Q	memr_memr_0_12/ADB9	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.000	0.000	0.484

Recovery Paths Table

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	1.914	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	5.000	0.033	2.818
2	1.914	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_Z/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	5.000	0.033	2.818
3	1.914	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_loop_Z/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	5.000	0.033	2.818
4	1.914	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_length_Z[0]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	5.000	0.033	2.818
5	1.914	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_length_Z[1]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	5.000	0.033	2.818
6	1.914	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_length_Z[2]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	5.000	0.033	2.818
7	1.914	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_length_Z[3]/PRESET	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	5.000	0.033	2.818
8	1.914	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_length_Z[4]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	5.000	0.033	2.818
9	1.914	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_length_Z[5]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	5.000	0.033	2.818
10	1.914	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_length_Z[6]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	5.000	0.033	2.818
11	1.914	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_length_Z[7]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	5.000	0.033	2.818
12	1.914	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_length_Z[8]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	5.000	0.033	2.818
13	1.914	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_length_Z[9]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	5.000	0.033	2.818
14	1.914	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_length_Z[10]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	5.000	0.033	2.818
15	1.914	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_length_Z[11]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	5.000	0.033	2.818
16	1.914	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_length_Z[12]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	5.000	0.033	2.818
17	1.914	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	5.000	0.033	2.818
18	1.914	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[1]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	5.000	0.033	2.818
19	1.914	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[2]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	5.000	0.033	2.818
20	1.914	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[3]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	5.000	0.033	2.818
21	1.914	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[4]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	5.000	0.033	2.818
22	1.914	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[5]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	5.000	0.033	2.818
23	1.914	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[6]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	5.000	0.033	2.818
24	1.914	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[7]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	5.000	0.033	2.818
25	1.914	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	5.000	0.033	2.818

Removal Paths Table

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	6.623	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	-5.000	0.013	1.821
2	6.623	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_loop_Z/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	-5.000	0.013	1.821
3	6.623	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_length_Z[0]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	-5.000	0.013	1.821
4	6.623	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_length_Z[1]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	-5.000	0.013	1.821
5	6.623	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_length_Z[2]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	-5.000	0.013	1.821
6	6.623	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_length_Z[4]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	-5.000	0.013	1.821
7	6.623	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_length_Z[5]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	-5.000	0.013	1.821
8	6.623	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_length_Z[7]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	-5.000	0.013	1.821
9	6.623	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_length_Z[8]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	-5.000	0.013	1.821
10	6.623	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_length_Z[9]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	-5.000	0.013	1.821
11	6.623	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_length_Z[10]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	-5.000	0.013	1.821
12	6.623	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_length_Z[11]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	-5.000	0.013	1.821
13	6.623	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_length_Z[12]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	-5.000	0.013	1.821
14	6.623	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	-5.000	0.013	1.821
15	6.623	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[1]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	-5.000	0.013	1.821
16	6.623	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[2]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	-5.000	0.013	1.821
17	6.623	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[3]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	-5.000	0.013	1.821
18	6.623	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[4]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	-5.000	0.013	1.821
19	6.623	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[5]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	-5.000	0.013	1.821
20	6.623	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[6]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	-5.000	0.013	1.821
21	6.623	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[7]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	-5.000	0.013	1.821
22	6.623	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	-5.000	0.013	1.821
23	6.623	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[9]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	-5.000	0.013	1.821
24	6.623	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[10]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	-5.000	0.013	1.821
25	6.623	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[11]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	-5.000	0.013	1.821

Minimum Pulse Width Table:

Report Command:report_min_pulse_width -nworst 10 -detail

Number	Slack	Actual Width	Required Width	Type	Clock	Objects
1	3.662	4.662	1.000	Low Pulse Width	DEFAULT_CLK	cnt_1_Z[12]
2	3.662	4.662	1.000	Low Pulse Width	DEFAULT_CLK	cnt_1_Z[10]
3	3.662	4.662	1.000	Low Pulse Width	DEFAULT_CLK	cnt_1_Z[6]
4	3.662	4.662	1.000	Low Pulse Width	DEFAULT_CLK	cnt_Z[11]
5	3.662	4.662	1.000	Low Pulse Width	DEFAULT_CLK	n_Z[25]
6	3.662	4.662	1.000	Low Pulse Width	DEFAULT_CLK	m_Z[27]
7	3.662	4.662	1.000	Low Pulse Width	DEFAULT_CLK	Mdu/u_mdu/reg0_Z[26]
8	3.662	4.662	1.000	Low Pulse Width	DEFAULT_CLK	Mdu/u_mdu/reg0_fast_Z[27]
9	3.662	4.662	1.000	Low Pulse Width	DEFAULT_CLK	Mdu/u_mdu/reg0_26_rep1_Z
10	3.662	4.662	1.000	Low Pulse Width	DEFAULT_CLK	Mdu/u_mdu/reg0_Z[25]

Timing Report By Analysis Type:

Setup Analysis Report

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	0.651
Data Arrival Time	10.997
Data Required Time	11.648
From	Mdu/u_mdu/div_shift_number_Z[1]
To	Mdu/u_mdu/reg0_fast_Z[30]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.683	0.683	tINS	RR	501	IOT48[A]	clk_ibuf/O
1.883	1.201	tNET	RR	1	R38C40[1][B]	Mdu/u_mdu/div_shift_number_Z[1]/CLK
2.115	0.232	tC2Q	RF	114	R38C40[1][B]	Mdu/u_mdu/div_shift_number_Z[1]/Q
3.708	1.593	tNET	FF	1	R39C43[0][A]	Mdu/u_mdu/m14_0_03_1_cZ/I1
4.170	0.462	tINS	FR	1	R39C43[0][A]	Mdu/u_mdu/m14_0_03_1_cZ/F
4.342	0.172	tNET	RR	1	R39C42[2][B]	Mdu/u_mdu/m14_0_03_cZ/I1
4.795	0.453	tINS	RF	4	R39C42[2][B]	Mdu/u_mdu/m14_0_03_cZ/F
5.493	0.697	tNET	FF	1	R40C37[2][A]	Mdu/u_mdu/m14_2_03_1_0_cZ/I3
6.010	0.517	tINS	FF	2	R40C37[2][A]	Mdu/u_mdu/m14_2_03_1_0_cZ/F
6.427	0.418	tNET	FF	1	R43C37[0][B]	Mdu/u_mdu/m14_2_03_0_0_RNI70O1/I1
6.982	0.555	tINS	FF	3	R43C37[0][B]	Mdu/u_mdu/m14_2_03_0_0_RNI70O1/F
7.388	0.406	tNET	FF	1	R43C35[0][A]	Mdu/u_mdu/m30_4_01_cZ/I1
7.905	0.517	tINS	FF	1	R43C35[0][A]	Mdu/u_mdu/m30_4_01_cZ/F
8.318	0.413	tNET	FF	1	R46C35[1][B]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[30]/I2
8.835	0.517	tINS	FF	1	R46C35[1][B]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[30]/F
9.248	0.413	tNET	FF	1	R48C36[3][B]	Mdu/u_mdu/reg0_exe_nx_cZ[30]/I3
9.765	0.517	tINS	FF	2	R48C36[3][B]	Mdu/u_mdu/reg0_exe_nx_cZ[30]/F
10.427	0.662	tNET	FF	1	R50C39[2][A]	Mdu/u_mdu/reg0_nx_fast_cZ[30]/I0
10.997	0.570	tINS	FR	1	R50C39[2][A]	Mdu/u_mdu/reg0_nx_fast_cZ[30]/F
10.997	0.000	tNET	RR	1	R50C39[2][A]	Mdu/u_mdu/reg0_fast_Z[30]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	501	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R50C39[2][A]	Mdu/u_mdu/reg0_fast_Z[30]/CLK
11.683	-0.200	tUnc				Mdu/u_mdu/reg0_fast_Z[30]
11.648	-0.035	tSu		1	R50C39[2][A]	Mdu/u_mdu/reg0_fast_Z[30]

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	8
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 4.108, 45.075%; route: 4.774, 52.379%; tC2Q: 0.232, 2.546%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path2

Path Summary:

Slack	0.651
Data Arrival Time	10.997
Data Required Time	11.648
From	Mdu/u_mdu/div_shift_number_Z[1]
To	Mdu/u_mdu/reg0_Z[30]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.683	0.683	tINS	RR	501	IOT48[A]	clk_ibuf/O
1.883	1.201	tNET	RR	1	R38C40[1][B]	Mdu/u_mdu/div_shift_number_Z[1]/CLK
2.115	0.232	tC2Q	RF	114	R38C40[1][B]	Mdu/u_mdu/div_shift_number_Z[1]/Q
3.708	1.593	tNET	FF	1	R39C43[0][A]	Mdu/u_mdu/m14_0_03_1_cZ/I1
4.170	0.462	tINS	FR	1	R39C43[0][A]	Mdu/u_mdu/m14_0_03_1_cZ/F
4.342	0.172	tNET	RR	1	R39C42[2][B]	Mdu/u_mdu/m14_0_03_cZ/I1
4.795	0.453	tINS	RF	4	R39C42[2][B]	Mdu/u_mdu/m14_0_03_cZ/F
5.493	0.697	tNET	FF	1	R40C37[2][A]	Mdu/u_mdu/m14_2_03_1_0_cZ/I3
6.010	0.517	tINS	FF	2	R40C37[2][A]	Mdu/u_mdu/m14_2_03_1_0_cZ/F
6.427	0.418	tNET	FF	1	R43C37[0][B]	Mdu/u_mdu/m14_2_03_0_0_RNI70O1/I1
6.982	0.555	tINS	FF	3	R43C37[0][B]	Mdu/u_mdu/m14_2_03_0_0_RNI70O1/F
7.388	0.406	tNET	FF	1	R43C35[0][A]	Mdu/u_mdu/m30_4_01_cZ/I1
7.905	0.517	tINS	FF	1	R43C35[0][A]	Mdu/u_mdu/m30_4_01_cZ/F
8.318	0.413	tNET	FF	1	R46C35[1][B]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[30]/I2
8.835	0.517	tINS	FF	1	R46C35[1][B]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[30]/F
9.248	0.413	tNET	FF	1	R48C36[3][B]	Mdu/u_mdu/reg0_exe_nx_cZ[30]/I3
9.765	0.517	tINS	FF	2	R48C36[3][B]	Mdu/u_mdu/reg0_exe_nx_cZ[30]/F
10.427	0.662	tNET	FF	1	R50C39[2][B]	Mdu/u_mdu/reg0_nx_cZ[30]/I0
10.997	0.570	tINS	FR	1	R50C39[2][B]	Mdu/u_mdu/reg0_nx_cZ[30]/F
10.997	0.000	tNET	RR	1	R50C39[2][B]	Mdu/u_mdu/reg0_Z[30]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	501	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R50C39[2][B]	Mdu/u_mdu/reg0_Z[30]/CLK
11.683	-0.200	tUnc				Mdu/u_mdu/reg0_Z[30]
11.648	-0.035	tSu		1	R50C39[2][B]	Mdu/u_mdu/reg0_Z[30]

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	8
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 4.108, 45.075%; route: 4.774, 52.379%; tC2Q: 0.232, 2.546%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path3

Path Summary:

Slack	0.713
Data Arrival Time	10.935
Data Required Time	11.648
From	Mdu/u_mdu/div_shift_number_Z[0]
To	Mdu/u_mdu/reg0_fast_Z[23]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.683	0.683	tINS	RR	501	IOT48[A]	clk_ibuf/O
1.883	1.201	tNET	RR	1	R38C40[1][A]	Mdu/u_mdu/div_shift_number_Z[0]/CLK
2.115	0.232	tC2Q	RF	113	R38C40[1][A]	Mdu/u_mdu/div_shift_number_Z[0]/Q
3.112	0.997	tNET	FF	1	R38C35[2][B]	Mdu/u_mdu/m3_0_03_0_0_cZ/I0
3.667	0.555	tINS	FF	5	R38C35[2][B]	Mdu/u_mdu/m3_0_03_0_0_cZ/F
4.198	0.531	tNET	FF	1	R38C31[0][A]	Mdu/u_mdu/m3_0_03_0_0_RNIV0NN/I0
4.569	0.371	tINS	FF	3	R38C31[0][A]	Mdu/u_mdu/m3_0_03_0_0_RNIV0NN/F
5.234	0.665	tNET	FF	1	R40C34[3][B]	Mdu/u_mdu/m7_2_03_cZ/I2
5.751	0.517	tINS	FF	4	R40C34[3][B]	Mdu/u_mdu/m7_2_03_cZ/F
6.416	0.665	tNET	FF	1	R41C31[2][A]	Mdu/u_mdu/m23_4_01_cZ/I1
6.971	0.555	tINS	FF	1	R41C31[2][A]	Mdu/u_mdu/m23_4_01_cZ/F
7.384	0.413	tNET	FF	1	R43C32[0][B]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[23]/I2
7.755	0.371	tINS	FF	1	R43C32[0][B]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[23]/F
8.682	0.927	tNET	FF	1	R43C36[1][A]	Mdu/u_mdu/reg0_exe_nx_cZ[23]/I3
9.135	0.453	tINS	FF	2	R43C36[1][A]	Mdu/u_mdu/reg0_exe_nx_cZ[23]/F
10.365	1.231	tNET	FF	1	R30C43[2][B]	Mdu/u_mdu/reg0_nx_fast_cZ[23]/I0
10.935	0.570	tINS	FR	1	R30C43[2][B]	Mdu/u_mdu/reg0_nx_fast_cZ[23]/F
10.935	0.000	tNET	RR	1	R30C43[2][B]	Mdu/u_mdu/reg0_fast_Z[23]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	501	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R30C43[2][B]	Mdu/u_mdu/reg0_fast_Z[23]/CLK
11.683	-0.200	tUnc				Mdu/u_mdu/reg0_fast_Z[23]
11.648	-0.035	tSu		1	R30C43[2][B]	Mdu/u_mdu/reg0_fast_Z[23]

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 3.392, 37.472%; route: 5.428, 59.965%; tC2Q: 0.232, 2.563%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path4

Path Summary:

Slack	0.811
Data Arrival Time	10.838
Data Required Time	11.648
From	Mdu/u_mdu/div_shift_number_Z[0]
To	Mdu/u_mdu/reg0_Z[23]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.683	0.683	tINS	RR	501	IOT48[A]	clk_ibuf/O
1.883	1.201	tNET	RR	1	R38C40[1][A]	Mdu/u_mdu/div_shift_number_Z[0]/CLK
2.115	0.232	tC2Q	RF	113	R38C40[1][A]	Mdu/u_mdu/div_shift_number_Z[0]/Q
3.112	0.997	tNET	FF	1	R38C35[2][B]	Mdu/u_mdu/m3_0_03_0_0_cZ/I0
3.667	0.555	tINS	FF	5	R38C35[2][B]	Mdu/u_mdu/m3_0_03_0_0_cZ/F
4.198	0.531	tNET	FF	1	R38C31[0][A]	Mdu/u_mdu/m3_0_03_0_0_RNIV0NN/I0
4.569	0.371	tINS	FF	3	R38C31[0][A]	Mdu/u_mdu/m3_0_03_0_0_RNIV0NN/F
5.234	0.665	tNET	FF	1	R40C34[3][B]	Mdu/u_mdu/m7_2_03_cZ/I2
5.751	0.517	tINS	FF	4	R40C34[3][B]	Mdu/u_mdu/m7_2_03_cZ/F
6.416	0.665	tNET	FF	1	R41C31[2][A]	Mdu/u_mdu/m23_4_01_cZ/I1
6.971	0.555	tINS	FF	1	R41C31[2][A]	Mdu/u_mdu/m23_4_01_cZ/F
7.384	0.413	tNET	FF	1	R43C32[0][B]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[23]/I2
7.755	0.371	tINS	FF	1	R43C32[0][B]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[23]/F
8.682	0.927	tNET	FF	1	R43C36[1][A]	Mdu/u_mdu/reg0_exe_nx_cZ[23]/I3
9.135	0.453	tINS	FF	2	R43C36[1][A]	Mdu/u_mdu/reg0_exe_nx_cZ[23]/F
10.289	1.154	tNET	FF	1	R30C43[0][A]	Mdu/u_mdu/reg0_nx_cZ[23]/I0
10.838	0.549	tINS	FR	1	R30C43[0][A]	Mdu/u_mdu/reg0_nx_cZ[23]/F
10.838	0.000	tNET	RR	1	R30C43[0][A]	Mdu/u_mdu/reg0_Z[23]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	501	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R30C43[0][A]	Mdu/u_mdu/reg0_Z[23]/CLK
11.683	-0.200	tUnc				Mdu/u_mdu/reg0_Z[23]
11.648	-0.035	tSu		1	R30C43[0][A]	Mdu/u_mdu/reg0_Z[23]

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 3.371, 37.646%; route: 5.351, 59.763%; tC2Q: 0.232, 2.591%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path5

Path Summary:

Slack	0.855
Data Arrival Time	10.794
Data Required Time	11.648
From	Mdu/u_mdu/reg0_fast_Z[17]
To	Mdu/u_mdu/reg0_Z[31]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.683	0.683	tINS	RR	501	IOT48[A]	clk_ibuf/O
1.883	1.201	tNET	RR	1	R34C41[0][B]	Mdu/u_mdu/reg0_fast_Z[17]/CLK
2.115	0.232	tC2Q	RF	6	R34C41[0][B]	Mdu/u_mdu/reg0_fast_Z[17]/Q
3.430	1.315	tNET	FF	1	R48C43[2][A]	Mdu/u_mdu/reg0_neg_axb_16_par_0_cp_0_lofx_cZ/I2
3.985	0.555	tINS	FF	1	R48C43[2][A]	Mdu/u_mdu/reg0_neg_axb_16_par_0_cp_0_lofx_cZ/F
4.883	0.899	tNET	FF	2	R51C46[0][A]	Mdu/u_mdu/reg0_neg_axb_16_par_cp_0_0/I0
5.453	0.570	tINS	FR	1	R51C46[0][A]	Mdu/u_mdu/reg0_neg_axb_16_par_cp_0_0/COUT
5.453	0.000	tNET	RR	2	R51C46[0][B]	Mdu/u_mdu/reg0_neg_axb_19_par_cp_0/CIN
5.489	0.035	tINS	RF	1	R51C46[0][B]	Mdu/u_mdu/reg0_neg_axb_19_par_cp_0/COUT
5.489	0.000	tNET	FF	2	R51C46[1][A]	Mdu/u_mdu/reg0_neg_axb_23_par_cp_0/CIN
5.524	0.035	tINS	FF	1	R51C46[1][A]	Mdu/u_mdu/reg0_neg_axb_23_par_cp_0/COUT
5.524	0.000	tNET	FF	2	R51C46[1][B]	Mdu/u_mdu/reg0_neg_axb_27_par_cp_0/CIN
5.559	0.035	tINS	FF	1	R51C46[1][B]	Mdu/u_mdu/reg0_neg_axb_27_par_cp_0/COUT
5.559	0.000	tNET	FF	2	R51C46[2][A]	Mdu/u_mdu/reg0_neg_axb_31_par_cp_0/CIN
5.594	0.035	tINS	FF	1	R51C46[2][A]	Mdu/u_mdu/reg0_neg_axb_31_par_cp_0/COUT
5.594	0.000	tNET	FF	2	R51C46[2][B]	Mdu/u_mdu/reg0_neg_axb_34_par_1/CIN
5.629	0.035	tINS	FF	1	R51C46[2][B]	Mdu/u_mdu/reg0_neg_axb_34_par_1/COUT
5.629	0.000	tNET	FF	2	R51C47[0][A]	Mdu/u_mdu/reg0_neg_axb_38_par_1/CIN
5.665	0.035	tINS	FF	1	R51C47[0][A]	Mdu/u_mdu/reg0_neg_axb_38_par_1/COUT
5.665	0.000	tNET	FF	2	R51C47[0][B]	Mdu/u_mdu/reg0_neg_axb_42_par_1/CIN
5.700	0.035	tINS	FF	1	R51C47[0][B]	Mdu/u_mdu/reg0_neg_axb_42_par_1/COUT
5.700	0.000	tNET	FF	2	R51C47[1][A]	Mdu/u_mdu/reg0_neg_axb_46_par_1/CIN
5.735	0.035	tINS	FF	1	R51C47[1][A]	Mdu/u_mdu/reg0_neg_axb_46_par_1/COUT
5.735	0.000	tNET	FF	2	R51C47[1][B]	Mdu/u_mdu/reg0_neg_axb_50_par_1/CIN
5.770	0.035	tINS	FF	1	R51C47[1][B]	Mdu/u_mdu/reg0_neg_axb_50_par_1/COUT
5.770	0.000	tNET	FF	2	R51C47[2][A]	Mdu/u_mdu/reg0_neg_cry_54_0/CIN
5.805	0.035	tINS	FF	1	R51C47[2][A]	Mdu/u_mdu/reg0_neg_cry_54_0/COUT
5.805	0.000	tNET	FF	2	R51C47[2][B]	Mdu/u_mdu/reg0_neg_cry_55_0/CIN
5.841	0.035	tINS	FF	1	R51C47[2][B]	Mdu/u_mdu/reg0_neg_cry_55_0/COUT
5.841	0.000	tNET	FF	2	R51C48[0][A]	Mdu/u_mdu/reg0_neg_cry_56_0/CIN
5.876	0.035	tINS	FF	1	R51C48[0][A]	Mdu/u_mdu/reg0_neg_cry_56_0/COUT
5.876	0.000	tNET	FF	2	R51C48[0][B]	Mdu/u_mdu/reg0_neg_cry_57_0/CIN
5.911	0.035	tINS	FF	1	R51C48[0][B]	Mdu/u_mdu/reg0_neg_cry_57_0/COUT
5.911	0.000	tNET	FF	2	R51C48[1][A]	Mdu/u_mdu/reg0_neg_cry_58_0/CIN
5.946	0.035	tINS	FF	1	R51C48[1][A]	Mdu/u_mdu/reg0_neg_cry_58_0/COUT
5.946	0.000	tNET	FF	2	R51C48[1][B]	Mdu/u_mdu/reg0_neg_cry_59_0/CIN
5.981	0.035	tINS	FF	1	R51C48[1][B]	Mdu/u_mdu/reg0_neg_cry_59_0/COUT
5.981	0.000	tNET	FF	2	R51C48[2][A]	Mdu/u_mdu/reg0_neg_cry_60_0/CIN
6.017	0.035	tINS	FF	1	R51C48[2][A]	Mdu/u_mdu/reg0_neg_cry_60_0/COUT
6.017	0.000	tNET	FF	2	R51C48[2][B]	Mdu/u_mdu/reg0_neg_cry_61_0/CIN
6.052	0.035	tINS	FF	1	R51C48[2][B]	Mdu/u_mdu/reg0_neg_cry_61_0/COUT
6.052	0.000	tNET	FF	2	R51C49[0][A]	Mdu/u_mdu/reg0_neg_cry_62_0/CIN
6.087	0.035	tINS	FF	1	R51C49[0][A]	Mdu/u_mdu/reg0_neg_cry_62_0/COUT
6.087	0.000	tNET	FF	2	R51C49[0][B]	Mdu/u_mdu/reg0_neg_s_63_0/CIN
6.557	0.470	tINS	FF	1	R51C49[0][B]	Mdu/u_mdu/reg0_neg_s_63_0/SUM
7.512	0.955	tNET	FF	1	R44C44[3][A]	Mdu/u_mdu/reg0_post_swap_2[31]/I2
8.029	0.517	tINS	FF	1	R44C44[3][A]	Mdu/u_mdu/reg0_post_swap_2[31]/F
8.029	0.000	tNET	FF	1	R44C44[3][A]	Mdu/u_mdu/reg0_post_swap_4[31]/I0
8.132	0.103	tINS	FF	2	R44C44[3][A]	Mdu/u_mdu/reg0_post_swap_4[31]/O
8.560	0.428	tNET	FF	1	R44C41[3][A]	Mdu/u_mdu/un11_reg0_nx_cZ[31]_cZ/I1
9.115	0.555	tINS	FF	3	R44C41[3][A]	Mdu/u_mdu/un11_reg0_nx_cZ[31]_cZ/F
10.245	1.130	tNET	FF	1	R33C34[2][A]	Mdu/u_mdu/reg0_nx_cZ[31]/I3
10.794	0.549	tINS	FR	1	R33C34[2][A]	Mdu/u_mdu/reg0_nx_cZ[31]/F
10.794	0.000	tNET	RR	1	R33C34[2][A]	Mdu/u_mdu/reg0_Z[31]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	501	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R33C34[2][A]	Mdu/u_mdu/reg0_Z[31]/CLK
11.683	-0.200	tUnc				Mdu/u_mdu/reg0_Z[31]
11.648	-0.035	tSu		1	R33C34[2][A]	Mdu/u_mdu/reg0_Z[31]

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 3.953, 44.359%; route: 4.726, 53.037%; tC2Q: 0.232, 2.604%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path6

Path Summary:

Slack	0.865
Data Arrival Time	10.783
Data Required Time	11.648
From	Mdu/u_mdu/reg0_fast_Z[17]
To	Mdu/u_mdu/reg0_fast_Z[31]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.683	0.683	tINS	RR	501	IOT48[A]	clk_ibuf/O
1.883	1.201	tNET	RR	1	R34C41[0][B]	Mdu/u_mdu/reg0_fast_Z[17]/CLK
2.115	0.232	tC2Q	RF	6	R34C41[0][B]	Mdu/u_mdu/reg0_fast_Z[17]/Q
3.430	1.315	tNET	FF	1	R48C43[2][A]	Mdu/u_mdu/reg0_neg_axb_16_par_0_cp_0_lofx_cZ/I2
3.985	0.555	tINS	FF	1	R48C43[2][A]	Mdu/u_mdu/reg0_neg_axb_16_par_0_cp_0_lofx_cZ/F
4.883	0.899	tNET	FF	2	R51C46[0][A]	Mdu/u_mdu/reg0_neg_axb_16_par_cp_0_0/I0
5.453	0.570	tINS	FR	1	R51C46[0][A]	Mdu/u_mdu/reg0_neg_axb_16_par_cp_0_0/COUT
5.453	0.000	tNET	RR	2	R51C46[0][B]	Mdu/u_mdu/reg0_neg_axb_19_par_cp_0/CIN
5.489	0.035	tINS	RF	1	R51C46[0][B]	Mdu/u_mdu/reg0_neg_axb_19_par_cp_0/COUT
5.489	0.000	tNET	FF	2	R51C46[1][A]	Mdu/u_mdu/reg0_neg_axb_23_par_cp_0/CIN
5.524	0.035	tINS	FF	1	R51C46[1][A]	Mdu/u_mdu/reg0_neg_axb_23_par_cp_0/COUT
5.524	0.000	tNET	FF	2	R51C46[1][B]	Mdu/u_mdu/reg0_neg_axb_27_par_cp_0/CIN
5.559	0.035	tINS	FF	1	R51C46[1][B]	Mdu/u_mdu/reg0_neg_axb_27_par_cp_0/COUT
5.559	0.000	tNET	FF	2	R51C46[2][A]	Mdu/u_mdu/reg0_neg_axb_31_par_cp_0/CIN
5.594	0.035	tINS	FF	1	R51C46[2][A]	Mdu/u_mdu/reg0_neg_axb_31_par_cp_0/COUT
5.594	0.000	tNET	FF	2	R51C46[2][B]	Mdu/u_mdu/reg0_neg_axb_34_par_1/CIN
5.629	0.035	tINS	FF	1	R51C46[2][B]	Mdu/u_mdu/reg0_neg_axb_34_par_1/COUT
5.629	0.000	tNET	FF	2	R51C47[0][A]	Mdu/u_mdu/reg0_neg_axb_38_par_1/CIN
5.665	0.035	tINS	FF	1	R51C47[0][A]	Mdu/u_mdu/reg0_neg_axb_38_par_1/COUT
5.665	0.000	tNET	FF	2	R51C47[0][B]	Mdu/u_mdu/reg0_neg_axb_42_par_1/CIN
5.700	0.035	tINS	FF	1	R51C47[0][B]	Mdu/u_mdu/reg0_neg_axb_42_par_1/COUT
5.700	0.000	tNET	FF	2	R51C47[1][A]	Mdu/u_mdu/reg0_neg_axb_46_par_1/CIN
5.735	0.035	tINS	FF	1	R51C47[1][A]	Mdu/u_mdu/reg0_neg_axb_46_par_1/COUT
5.735	0.000	tNET	FF	2	R51C47[1][B]	Mdu/u_mdu/reg0_neg_axb_50_par_1/CIN
5.770	0.035	tINS	FF	1	R51C47[1][B]	Mdu/u_mdu/reg0_neg_axb_50_par_1/COUT
5.770	0.000	tNET	FF	2	R51C47[2][A]	Mdu/u_mdu/reg0_neg_cry_54_0/CIN
5.805	0.035	tINS	FF	1	R51C47[2][A]	Mdu/u_mdu/reg0_neg_cry_54_0/COUT
5.805	0.000	tNET	FF	2	R51C47[2][B]	Mdu/u_mdu/reg0_neg_cry_55_0/CIN
5.841	0.035	tINS	FF	1	R51C47[2][B]	Mdu/u_mdu/reg0_neg_cry_55_0/COUT
5.841	0.000	tNET	FF	2	R51C48[0][A]	Mdu/u_mdu/reg0_neg_cry_56_0/CIN
5.876	0.035	tINS	FF	1	R51C48[0][A]	Mdu/u_mdu/reg0_neg_cry_56_0/COUT
5.876	0.000	tNET	FF	2	R51C48[0][B]	Mdu/u_mdu/reg0_neg_cry_57_0/CIN
5.911	0.035	tINS	FF	1	R51C48[0][B]	Mdu/u_mdu/reg0_neg_cry_57_0/COUT
5.911	0.000	tNET	FF	2	R51C48[1][A]	Mdu/u_mdu/reg0_neg_cry_58_0/CIN
5.946	0.035	tINS	FF	1	R51C48[1][A]	Mdu/u_mdu/reg0_neg_cry_58_0/COUT
5.946	0.000	tNET	FF	2	R51C48[1][B]	Mdu/u_mdu/reg0_neg_cry_59_0/CIN
5.981	0.035	tINS	FF	1	R51C48[1][B]	Mdu/u_mdu/reg0_neg_cry_59_0/COUT
5.981	0.000	tNET	FF	2	R51C48[2][A]	Mdu/u_mdu/reg0_neg_cry_60_0/CIN
6.017	0.035	tINS	FF	1	R51C48[2][A]	Mdu/u_mdu/reg0_neg_cry_60_0/COUT
6.017	0.000	tNET	FF	2	R51C48[2][B]	Mdu/u_mdu/reg0_neg_cry_61_0/CIN
6.052	0.035	tINS	FF	1	R51C48[2][B]	Mdu/u_mdu/reg0_neg_cry_61_0/COUT
6.052	0.000	tNET	FF	2	R51C49[0][A]	Mdu/u_mdu/reg0_neg_cry_62_0/CIN
6.087	0.035	tINS	FF	1	R51C49[0][A]	Mdu/u_mdu/reg0_neg_cry_62_0/COUT
6.087	0.000	tNET	FF	2	R51C49[0][B]	Mdu/u_mdu/reg0_neg_s_63_0/CIN
6.557	0.470	tINS	FF	1	R51C49[0][B]	Mdu/u_mdu/reg0_neg_s_63_0/SUM
7.512	0.955	tNET	FF	1	R44C44[3][A]	Mdu/u_mdu/reg0_post_swap_2[31]/I2
8.029	0.517	tINS	FF	1	R44C44[3][A]	Mdu/u_mdu/reg0_post_swap_2[31]/F
8.029	0.000	tNET	FF	1	R44C44[3][A]	Mdu/u_mdu/reg0_post_swap_4[31]/I0
8.132	0.103	tINS	FF	2	R44C44[3][A]	Mdu/u_mdu/reg0_post_swap_4[31]/O
8.560	0.428	tNET	FF	1	R44C41[3][A]	Mdu/u_mdu/un11_reg0_nx_cZ[31]_cZ/I1
9.115	0.555	tINS	FF	3	R44C41[3][A]	Mdu/u_mdu/un11_reg0_nx_cZ[31]_cZ/F
10.321	1.206	tNET	FF	1	R33C35[1][A]	Mdu/u_mdu/reg0_nx_fast_cZ[31]/I3
10.783	0.462	tINS	FR	1	R33C35[1][A]	Mdu/u_mdu/reg0_nx_fast_cZ[31]/F
10.783	0.000	tNET	RR	1	R33C35[1][A]	Mdu/u_mdu/reg0_fast_Z[31]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	501	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R33C35[1][A]	Mdu/u_mdu/reg0_fast_Z[31]/CLK
11.683	-0.200	tUnc				Mdu/u_mdu/reg0_fast_Z[31]
11.648	-0.035	tSu		1	R33C35[1][A]	Mdu/u_mdu/reg0_fast_Z[31]

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 3.866, 43.433%; route: 4.803, 53.960%; tC2Q: 0.232, 2.607%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path7

Path Summary:

Slack	0.899
Data Arrival Time	10.749
Data Required Time	11.648
From	Mdu/u_mdu/div_shift_number_Z[0]
To	Mdu/u_mdu/reg0_Z[56]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.683	0.683	tINS	RR	501	IOT48[A]	clk_ibuf/O
1.883	1.201	tNET	RR	1	R38C40[1][A]	Mdu/u_mdu/div_shift_number_Z[0]/CLK
2.115	0.232	tC2Q	RF	113	R38C40[1][A]	Mdu/u_mdu/div_shift_number_Z[0]/Q
3.459	1.344	tNET	FF	1	R40C37[3][A]	Mdu/u_mdu/m52_0_03_1_cZ/I0
4.014	0.555	tINS	FF	1	R40C37[3][A]	Mdu/u_mdu/m52_0_03_1_cZ/F
4.411	0.397	tNET	FF	1	R40C35[3][A]	Mdu/u_mdu/m52_0_03_cZ/I1
4.966	0.555	tINS	FF	4	R40C35[3][A]	Mdu/u_mdu/m52_0_03_cZ/F
5.379	0.413	tNET	FF	1	R38C35[1][B]	Mdu/u_mdu/m56_2_03_1_0_cZ/I2
5.949	0.570	tINS	FR	1	R38C35[1][B]	Mdu/u_mdu/m56_2_03_1_0_cZ/F
5.950	0.001	tNET	RR	1	R38C35[3][B]	Mdu/u_mdu/m56_4_03_1_0_RNO/I1
6.505	0.555	tINS	RF	1	R38C35[3][B]	Mdu/u_mdu/m56_4_03_1_0_RNO/F
7.311	0.806	tNET	FF	1	R43C35[3][A]	Mdu/u_mdu/m56_4_03_1_0_cZ/I3
7.764	0.453	tINS	FF	1	R43C35[3][A]	Mdu/u_mdu/m56_4_03_1_0_cZ/F
8.420	0.656	tNET	FF	1	R43C37[1][A]	Mdu/u_mdu/reg0_exe_nx_m0_cZ[56]/I2
8.873	0.453	tINS	FF	1	R43C37[1][A]	Mdu/u_mdu/reg0_exe_nx_m0_cZ[56]/F
8.873	0.000	tNET	FF	1	R43C37[1][A]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[56]/I0
8.976	0.103	tINS	FF	1	R43C37[1][A]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[56]/O
10.179	1.203	tNET	FF	1	R50C44[2][A]	Mdu/u_mdu/reg0_nx_cZ[56]/I0
10.749	0.570	tINS	FR	1	R50C44[2][A]	Mdu/u_mdu/reg0_nx_cZ[56]/F
10.749	0.000	tNET	RR	1	R50C44[2][A]	Mdu/u_mdu/reg0_Z[56]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	501	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R50C44[2][A]	Mdu/u_mdu/reg0_Z[56]/CLK
11.683	-0.200	tUnc				Mdu/u_mdu/reg0_Z[56]
11.648	-0.035	tSu		1	R50C44[2][A]	Mdu/u_mdu/reg0_Z[56]

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	8
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 3.814, 43.017%; route: 4.820, 54.366%; tC2Q: 0.232, 2.617%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path8

Path Summary:

Slack	0.924
Data Arrival Time	10.724
Data Required Time	11.648
From	Mdu/u_mdu/div_shift_number_Z[1]
To	Mdu/u_mdu/reg0_Z[62]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.683	0.683	tINS	RR	501	IOT48[A]	clk_ibuf/O
1.883	1.201	tNET	RR	1	R38C40[1][B]	Mdu/u_mdu/div_shift_number_Z[1]/CLK
2.115	0.232	tC2Q	RF	114	R38C40[1][B]	Mdu/u_mdu/div_shift_number_Z[1]/Q
3.945	1.830	tNET	FF	1	R38C44[0][B]	Mdu/u_mdu/m26_0_03_1_cZ/I1
4.407	0.462	tINS	FR	1	R38C44[0][B]	Mdu/u_mdu/m26_0_03_1_cZ/F
4.408	0.001	tNET	RR	1	R38C44[0][A]	Mdu/u_mdu/m26_0_03_cZ/I1
4.963	0.555	tINS	RF	4	R38C44[0][A]	Mdu/u_mdu/m26_0_03_cZ/F
5.876	0.913	tNET	FF	1	R41C41[3][B]	Mdu/u_mdu/m30_2_03_1_0_cZ/I2
6.393	0.517	tINS	FF	2	R41C41[3][B]	Mdu/u_mdu/m30_2_03_1_0_cZ/F
7.249	0.856	tNET	FF	1	R43C35[3][B]	Mdu/u_mdu/m30_2_03_0_0_RNI30BU/I1
7.711	0.462	tINS	FR	2	R43C35[3][B]	Mdu/u_mdu/m30_2_03_0_0_RNI30BU/F
7.885	0.174	tNET	RR	1	R43C36[3][B]	Mdu/u_mdu/m62_4_03_0_0_cZ/I1
8.455	0.570	tINS	RR	1	R43C36[3][B]	Mdu/u_mdu/m62_4_03_0_0_cZ/F
8.456	0.001	tNET	RR	1	R43C36[2][A]	Mdu/u_mdu/reg0_exe_nx_m0_cZ[62]/I1
8.973	0.517	tINS	RF	1	R43C36[2][A]	Mdu/u_mdu/reg0_exe_nx_m0_cZ[62]/F
8.973	0.000	tNET	FF	1	R43C36[2][A]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[62]/I0
9.076	0.103	tINS	FF	1	R43C36[2][A]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[62]/O
10.353	1.277	tNET	FF	1	R34C31[2][B]	Mdu/u_mdu/reg0_nx_cZ[62]/I0
10.724	0.371	tINS	FF	1	R34C31[2][B]	Mdu/u_mdu/reg0_nx_cZ[62]/F
10.724	0.000	tNET	FF	1	R34C31[2][B]	Mdu/u_mdu/reg0_Z[62]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	501	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R34C31[2][B]	Mdu/u_mdu/reg0_Z[62]/CLK
11.683	-0.200	tUnc				Mdu/u_mdu/reg0_Z[62]
11.648	-0.035	tSu		1	R34C31[2][B]	Mdu/u_mdu/reg0_Z[62]

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	8
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 3.557, 40.234%; route: 5.052, 57.142%; tC2Q: 0.232, 2.624%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path9

Path Summary:

Slack	1.021
Data Arrival Time	10.627
Data Required Time	11.648
From	Mdu/u_mdu/reg1_Z[2]
To	Mdu/u_mdu/div_shift_number_Z[5]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.683	0.683	tINS	RR	501	IOT48[A]	clk_ibuf/O
1.883	1.201	tNET	RR	1	R48C31[1][A]	Mdu/u_mdu/reg1_Z[2]/CLK
2.115	0.232	tC2Q	RF	8	R48C31[1][A]	Mdu/u_mdu/reg1_Z[2]/Q
3.032	0.916	tNET	FF	1	R51C34[3][A]	Mdu/u_mdu/un5_op1_eq_zero_nx_17_cZ_cZ/I0
3.587	0.555	tINS	FF	1	R51C34[3][A]	Mdu/u_mdu/un5_op1_eq_zero_nx_17_cZ_cZ/F
3.834	0.247	tNET	FF	1	R51C33[3][A]	Mdu/u_mdu/un5_op1_eq_zero_nx_22_cZ_cZ/S0
4.085	0.251	tINS	FF	2	R51C33[3][A]	Mdu/u_mdu/un5_op1_eq_zero_nx_22_cZ_cZ/O
4.755	0.671	tNET	FF	1	R52C36[1][B]	Mdu/u_mdu/un5_op1_eq_zero_nx_x_cZ_cZ/I2
5.325	0.570	tINS	FR	1	R52C36[1][B]	Mdu/u_mdu/un5_op1_eq_zero_nx_x_cZ_cZ/F
5.327	0.001	tNET	RR	1	R52C36[1][A]	Mdu/u_mdu/un1_op1_lead_zero_detect_32_v[0]/I0
5.882	0.555	tINS	RF	2	R52C36[1][A]	Mdu/u_mdu/un1_op1_lead_zero_detect_32_v[0]/F
6.454	0.572	tNET	FF	1	R51C35[3][B]	Mdu/u_mdu/op1_lead_zero_detect_16_p[0]_m_cZ[1]/I3
7.009	0.555	tINS	FF	1	R51C35[3][B]	Mdu/u_mdu/op1_lead_zero_detect_16_p[0]_m_cZ[1]/F
7.693	0.684	tNET	FF	1	R51C38[1][A]	Mdu/u_mdu/un2_div_shift_number_nx_0_cry_1_0_0_RNO_cZ_cZ/I0
8.146	0.453	tINS	FF	1	R51C38[1][A]	Mdu/u_mdu/un2_div_shift_number_nx_0_cry_1_0_0_RNO_cZ_cZ/F
9.327	1.181	tNET	FF	2	R38C40[1][B]	Mdu/u_mdu/un2_div_shift_number_nx_0_cry_1_0_0/I0
9.897	0.570	tINS	FR	1	R38C40[1][B]	Mdu/u_mdu/un2_div_shift_number_nx_0_cry_1_0_0/COUT
9.897	0.000	tNET	RR	2	R38C40[2][A]	Mdu/u_mdu/un2_div_shift_number_nx_0_cry_2_0_0/CIN
9.932	0.035	tINS	RF	1	R38C40[2][A]	Mdu/u_mdu/un2_div_shift_number_nx_0_cry_2_0_0/COUT
9.932	0.000	tNET	FF	2	R38C40[2][B]	Mdu/u_mdu/un2_div_shift_number_nx_0_cry_3_0_0/CIN
9.968	0.035	tINS	FF	1	R38C40[2][B]	Mdu/u_mdu/un2_div_shift_number_nx_0_cry_3_0_0/COUT
9.968	0.000	tNET	FF	2	R38C41[0][A]	Mdu/u_mdu/un2_div_shift_number_nx_0_cry_4_0/CIN
10.003	0.035	tINS	FF	1	R38C41[0][A]	Mdu/u_mdu/un2_div_shift_number_nx_0_cry_4_0/COUT
10.003	0.000	tNET	FF	2	R38C41[0][B]	Mdu/u_mdu/un2_div_shift_number_nx_0_s_5_0/CIN
10.473	0.470	tINS	FF	1	R38C41[0][B]	Mdu/u_mdu/un2_div_shift_number_nx_0_s_5_0/SUM
10.627	0.154	tNET	FF	1	R38C41[1][A]	Mdu/u_mdu/div_shift_number_Z[5]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	501	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R38C41[1][A]	Mdu/u_mdu/div_shift_number_Z[5]/CLK
11.683	-0.200	tUnc				Mdu/u_mdu/div_shift_number_Z[5]
11.648	-0.035	tSu		1	R38C41[1][A]	Mdu/u_mdu/div_shift_number_Z[5]

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	8
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 4.085, 46.713%; route: 4.427, 50.633%; tC2Q: 0.232, 2.653%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path10

Path Summary:

Slack	1.108
Data Arrival Time	10.541
Data Required Time	11.648
From	Mdu/u_mdu/reg0_fast_Z[17]
To	Mdu/u_mdu/reg0_31_rep1_Z
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.683	0.683	tINS	RR	501	IOT48[A]	clk_ibuf/O
1.883	1.201	tNET	RR	1	R34C41[0][B]	Mdu/u_mdu/reg0_fast_Z[17]/CLK
2.115	0.232	tC2Q	RF	6	R34C41[0][B]	Mdu/u_mdu/reg0_fast_Z[17]/Q
3.430	1.315	tNET	FF	1	R48C43[2][A]	Mdu/u_mdu/reg0_neg_axb_16_par_0_cp_0_lofx_cZ/I2
3.985	0.555	tINS	FF	1	R48C43[2][A]	Mdu/u_mdu/reg0_neg_axb_16_par_0_cp_0_lofx_cZ/F
4.883	0.899	tNET	FF	2	R51C46[0][A]	Mdu/u_mdu/reg0_neg_axb_16_par_cp_0_0/I0
5.453	0.570	tINS	FR	1	R51C46[0][A]	Mdu/u_mdu/reg0_neg_axb_16_par_cp_0_0/COUT
5.453	0.000	tNET	RR	2	R51C46[0][B]	Mdu/u_mdu/reg0_neg_axb_19_par_cp_0/CIN
5.489	0.035	tINS	RF	1	R51C46[0][B]	Mdu/u_mdu/reg0_neg_axb_19_par_cp_0/COUT
5.489	0.000	tNET	FF	2	R51C46[1][A]	Mdu/u_mdu/reg0_neg_axb_23_par_cp_0/CIN
5.524	0.035	tINS	FF	1	R51C46[1][A]	Mdu/u_mdu/reg0_neg_axb_23_par_cp_0/COUT
5.524	0.000	tNET	FF	2	R51C46[1][B]	Mdu/u_mdu/reg0_neg_axb_27_par_cp_0/CIN
5.559	0.035	tINS	FF	1	R51C46[1][B]	Mdu/u_mdu/reg0_neg_axb_27_par_cp_0/COUT
5.559	0.000	tNET	FF	2	R51C46[2][A]	Mdu/u_mdu/reg0_neg_axb_31_par_cp_0/CIN
5.594	0.035	tINS	FF	1	R51C46[2][A]	Mdu/u_mdu/reg0_neg_axb_31_par_cp_0/COUT
5.594	0.000	tNET	FF	2	R51C46[2][B]	Mdu/u_mdu/reg0_neg_axb_34_par_1/CIN
5.629	0.035	tINS	FF	1	R51C46[2][B]	Mdu/u_mdu/reg0_neg_axb_34_par_1/COUT
5.629	0.000	tNET	FF	2	R51C47[0][A]	Mdu/u_mdu/reg0_neg_axb_38_par_1/CIN
5.665	0.035	tINS	FF	1	R51C47[0][A]	Mdu/u_mdu/reg0_neg_axb_38_par_1/COUT
5.665	0.000	tNET	FF	2	R51C47[0][B]	Mdu/u_mdu/reg0_neg_axb_42_par_1/CIN
5.700	0.035	tINS	FF	1	R51C47[0][B]	Mdu/u_mdu/reg0_neg_axb_42_par_1/COUT
5.700	0.000	tNET	FF	2	R51C47[1][A]	Mdu/u_mdu/reg0_neg_axb_46_par_1/CIN
5.735	0.035	tINS	FF	1	R51C47[1][A]	Mdu/u_mdu/reg0_neg_axb_46_par_1/COUT
5.735	0.000	tNET	FF	2	R51C47[1][B]	Mdu/u_mdu/reg0_neg_axb_50_par_1/CIN
5.770	0.035	tINS	FF	1	R51C47[1][B]	Mdu/u_mdu/reg0_neg_axb_50_par_1/COUT
5.770	0.000	tNET	FF	2	R51C47[2][A]	Mdu/u_mdu/reg0_neg_cry_54_0/CIN
5.805	0.035	tINS	FF	1	R51C47[2][A]	Mdu/u_mdu/reg0_neg_cry_54_0/COUT
5.805	0.000	tNET	FF	2	R51C47[2][B]	Mdu/u_mdu/reg0_neg_cry_55_0/CIN
5.841	0.035	tINS	FF	1	R51C47[2][B]	Mdu/u_mdu/reg0_neg_cry_55_0/COUT
5.841	0.000	tNET	FF	2	R51C48[0][A]	Mdu/u_mdu/reg0_neg_cry_56_0/CIN
5.876	0.035	tINS	FF	1	R51C48[0][A]	Mdu/u_mdu/reg0_neg_cry_56_0/COUT
5.876	0.000	tNET	FF	2	R51C48[0][B]	Mdu/u_mdu/reg0_neg_cry_57_0/CIN
5.911	0.035	tINS	FF	1	R51C48[0][B]	Mdu/u_mdu/reg0_neg_cry_57_0/COUT
5.911	0.000	tNET	FF	2	R51C48[1][A]	Mdu/u_mdu/reg0_neg_cry_58_0/CIN
5.946	0.035	tINS	FF	1	R51C48[1][A]	Mdu/u_mdu/reg0_neg_cry_58_0/COUT
5.946	0.000	tNET	FF	2	R51C48[1][B]	Mdu/u_mdu/reg0_neg_cry_59_0/CIN
5.981	0.035	tINS	FF	1	R51C48[1][B]	Mdu/u_mdu/reg0_neg_cry_59_0/COUT
5.981	0.000	tNET	FF	2	R51C48[2][A]	Mdu/u_mdu/reg0_neg_cry_60_0/CIN
6.017	0.035	tINS	FF	1	R51C48[2][A]	Mdu/u_mdu/reg0_neg_cry_60_0/COUT
6.017	0.000	tNET	FF	2	R51C48[2][B]	Mdu/u_mdu/reg0_neg_cry_61_0/CIN
6.052	0.035	tINS	FF	1	R51C48[2][B]	Mdu/u_mdu/reg0_neg_cry_61_0/COUT
6.052	0.000	tNET	FF	2	R51C49[0][A]	Mdu/u_mdu/reg0_neg_cry_62_0/CIN
6.087	0.035	tINS	FF	1	R51C49[0][A]	Mdu/u_mdu/reg0_neg_cry_62_0/COUT
6.087	0.000	tNET	FF	2	R51C49[0][B]	Mdu/u_mdu/reg0_neg_s_63_0/CIN
6.557	0.470	tINS	FF	1	R51C49[0][B]	Mdu/u_mdu/reg0_neg_s_63_0/SUM
7.512	0.955	tNET	FF	1	R44C44[3][A]	Mdu/u_mdu/reg0_post_swap_2[31]/I2
8.029	0.517	tINS	FF	1	R44C44[3][A]	Mdu/u_mdu/reg0_post_swap_2[31]/F
8.029	0.000	tNET	FF	1	R44C44[3][A]	Mdu/u_mdu/reg0_post_swap_4[31]/I0
8.132	0.103	tINS	FF	2	R44C44[3][A]	Mdu/u_mdu/reg0_post_swap_4[31]/O
8.560	0.428	tNET	FF	1	R44C41[3][A]	Mdu/u_mdu/un11_reg0_nx_cZ[31]_cZ/I1
9.115	0.555	tINS	FF	3	R44C41[3][A]	Mdu/u_mdu/un11_reg0_nx_cZ[31]_cZ/F
10.079	0.964	tNET	FF	1	R35C34[2][B]	Mdu/u_mdu/reg0_nx_rep1_cZ[31]/I3
10.541	0.462	tINS	FR	1	R35C34[2][B]	Mdu/u_mdu/reg0_nx_rep1_cZ[31]/F
10.541	0.000	tNET	RR	1	R35C34[2][B]	Mdu/u_mdu/reg0_31_rep1_Z/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	501	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R35C34[2][B]	Mdu/u_mdu/reg0_31_rep1_Z/CLK
11.683	-0.200	tUnc				Mdu/u_mdu/reg0_31_rep1_Z
11.648	-0.035	tSu		1	R35C34[2][B]	Mdu/u_mdu/reg0_31_rep1_Z

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 3.866, 44.651%; route: 4.560, 52.669%; tC2Q: 0.232, 2.680%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path11

Path Summary:

Slack	1.168
Data Arrival Time	10.480
Data Required Time	11.648
From	Mdu/u_mdu/div_shift_number_Z[1]
To	Mdu/u_mdu/reg0_fast_Z[14]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.683	0.683	tINS	RR	501	IOT48[A]	clk_ibuf/O
1.883	1.201	tNET	RR	1	R38C40[1][B]	Mdu/u_mdu/div_shift_number_Z[1]/CLK
2.115	0.232	tC2Q	RF	114	R38C40[1][B]	Mdu/u_mdu/div_shift_number_Z[1]/Q
3.708	1.593	tNET	FF	1	R39C43[0][A]	Mdu/u_mdu/m14_0_03_1_cZ/I1
4.170	0.462	tINS	FR	1	R39C43[0][A]	Mdu/u_mdu/m14_0_03_1_cZ/F
4.342	0.172	tNET	RR	1	R39C42[2][B]	Mdu/u_mdu/m14_0_03_cZ/I1
4.795	0.453	tINS	RF	4	R39C42[2][B]	Mdu/u_mdu/m14_0_03_cZ/F
5.493	0.697	tNET	FF	1	R40C37[2][A]	Mdu/u_mdu/m14_2_03_1_0_cZ/I3
6.010	0.517	tINS	FF	2	R40C37[2][A]	Mdu/u_mdu/m14_2_03_1_0_cZ/F
6.427	0.418	tNET	FF	1	R43C37[0][B]	Mdu/u_mdu/m14_2_03_0_0_RNI70O1/I1
6.982	0.555	tINS	FF	3	R43C37[0][B]	Mdu/u_mdu/m14_2_03_0_0_RNI70O1/F
7.675	0.693	tNET	FF	1	R39C34[0][B]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[14]/I2
8.128	0.453	tINS	FF	1	R39C34[0][B]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[14]/F
8.934	0.806	tNET	FF	1	R39C33[0][B]	Mdu/u_mdu/reg0_exe_nx_cZ[14]/I3
9.387	0.453	tINS	FF	2	R39C33[0][B]	Mdu/u_mdu/reg0_exe_nx_cZ[14]/F
9.910	0.524	tNET	FF	1	R35C34[1][B]	Mdu/u_mdu/reg0_nx_fast_cZ[14]/I0
10.480	0.570	tINS	FR	1	R35C34[1][B]	Mdu/u_mdu/reg0_nx_fast_cZ[14]/F
10.480	0.000	tNET	RR	1	R35C34[1][B]	Mdu/u_mdu/reg0_fast_Z[14]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	501	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R35C34[1][B]	Mdu/u_mdu/reg0_fast_Z[14]/CLK
11.683	-0.200	tUnc				Mdu/u_mdu/reg0_fast_Z[14]
11.648	-0.035	tSu		1	R35C34[1][B]	Mdu/u_mdu/reg0_fast_Z[14]

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 3.463, 40.280%; route: 4.902, 57.021%; tC2Q: 0.232, 2.699%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path12

Path Summary:

Slack	1.168
Data Arrival Time	10.480
Data Required Time	11.648
From	Mdu/u_mdu/div_shift_number_Z[1]
To	Mdu/u_mdu/reg0_Z[14]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.683	0.683	tINS	RR	501	IOT48[A]	clk_ibuf/O
1.883	1.201	tNET	RR	1	R38C40[1][B]	Mdu/u_mdu/div_shift_number_Z[1]/CLK
2.115	0.232	tC2Q	RF	114	R38C40[1][B]	Mdu/u_mdu/div_shift_number_Z[1]/Q
3.708	1.593	tNET	FF	1	R39C43[0][A]	Mdu/u_mdu/m14_0_03_1_cZ/I1
4.170	0.462	tINS	FR	1	R39C43[0][A]	Mdu/u_mdu/m14_0_03_1_cZ/F
4.342	0.172	tNET	RR	1	R39C42[2][B]	Mdu/u_mdu/m14_0_03_cZ/I1
4.795	0.453	tINS	RF	4	R39C42[2][B]	Mdu/u_mdu/m14_0_03_cZ/F
5.493	0.697	tNET	FF	1	R40C37[2][A]	Mdu/u_mdu/m14_2_03_1_0_cZ/I3
6.010	0.517	tINS	FF	2	R40C37[2][A]	Mdu/u_mdu/m14_2_03_1_0_cZ/F
6.427	0.418	tNET	FF	1	R43C37[0][B]	Mdu/u_mdu/m14_2_03_0_0_RNI70O1/I1
6.982	0.555	tINS	FF	3	R43C37[0][B]	Mdu/u_mdu/m14_2_03_0_0_RNI70O1/F
7.675	0.693	tNET	FF	1	R39C34[0][B]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[14]/I2
8.128	0.453	tINS	FF	1	R39C34[0][B]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[14]/F
8.934	0.806	tNET	FF	1	R39C33[0][B]	Mdu/u_mdu/reg0_exe_nx_cZ[14]/I3
9.387	0.453	tINS	FF	2	R39C33[0][B]	Mdu/u_mdu/reg0_exe_nx_cZ[14]/F
9.910	0.524	tNET	FF	1	R35C34[1][A]	Mdu/u_mdu/reg0_nx_cZ[14]/I0
10.480	0.570	tINS	FR	1	R35C34[1][A]	Mdu/u_mdu/reg0_nx_cZ[14]/F
10.480	0.000	tNET	RR	1	R35C34[1][A]	Mdu/u_mdu/reg0_Z[14]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	501	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R35C34[1][A]	Mdu/u_mdu/reg0_Z[14]/CLK
11.683	-0.200	tUnc				Mdu/u_mdu/reg0_Z[14]
11.648	-0.035	tSu		1	R35C34[1][A]	Mdu/u_mdu/reg0_Z[14]

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 3.463, 40.280%; route: 4.902, 57.021%; tC2Q: 0.232, 2.699%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path13

Path Summary:

Slack	1.180
Data Arrival Time	10.469
Data Required Time	11.648
From	Mdu/u_mdu/div_shift_number_Z[1]
To	Mdu/u_mdu/reg0_Z[46]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.683	0.683	tINS	RR	501	IOT48[A]	clk_ibuf/O
1.883	1.201	tNET	RR	1	R38C40[1][B]	Mdu/u_mdu/div_shift_number_Z[1]/CLK
2.115	0.232	tC2Q	RF	114	R38C40[1][B]	Mdu/u_mdu/div_shift_number_Z[1]/Q
3.945	1.830	tNET	FF	1	R38C44[0][B]	Mdu/u_mdu/m26_0_03_1_cZ/I1
4.407	0.462	tINS	FR	1	R38C44[0][B]	Mdu/u_mdu/m26_0_03_1_cZ/F
4.408	0.001	tNET	RR	1	R38C44[0][A]	Mdu/u_mdu/m26_0_03_cZ/I1
4.963	0.555	tINS	RF	4	R38C44[0][A]	Mdu/u_mdu/m26_0_03_cZ/F
5.876	0.913	tNET	FF	1	R41C41[3][B]	Mdu/u_mdu/m30_2_03_1_0_cZ/I2
6.393	0.517	tINS	FF	2	R41C41[3][B]	Mdu/u_mdu/m30_2_03_1_0_cZ/F
7.249	0.856	tNET	FF	1	R43C35[3][B]	Mdu/u_mdu/m30_2_03_0_0_RNI30BU/I1
7.702	0.453	tINS	FF	2	R43C35[3][B]	Mdu/u_mdu/m30_2_03_0_0_RNI30BU/F
8.120	0.418	tNET	FF	1	R44C37[0][A]	Mdu/u_mdu/m46_4_03_0_0_cZ/I0
8.690	0.570	tINS	FR	1	R44C37[0][A]	Mdu/u_mdu/m46_4_03_0_0_cZ/F
8.691	0.001	tNET	RR	1	R44C37[1][B]	Mdu/u_mdu/reg0_exe_nx_m1_cZ[46]/I2
9.062	0.371	tINS	RF	1	R44C37[1][B]	Mdu/u_mdu/reg0_exe_nx_m1_cZ[46]/F
9.062	0.000	tNET	FF	1	R44C37[1][A]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[46]/I1
9.165	0.103	tINS	FF	1	R44C37[1][A]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[46]/O
10.098	0.933	tNET	FF	1	R49C41[2][B]	Mdu/u_mdu/reg0_nx_cZ[46]/I0
10.469	0.371	tINS	FF	1	R49C41[2][B]	Mdu/u_mdu/reg0_nx_cZ[46]/F
10.469	0.000	tNET	FF	1	R49C41[2][B]	Mdu/u_mdu/reg0_Z[46]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	501	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R49C41[2][B]	Mdu/u_mdu/reg0_Z[46]/CLK
11.683	-0.200	tUnc				Mdu/u_mdu/reg0_Z[46]
11.648	-0.035	tSu		1	R49C41[2][B]	Mdu/u_mdu/reg0_Z[46]

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	8
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 3.402, 39.625%; route: 4.951, 57.673%; tC2Q: 0.232, 2.702%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path14

Path Summary:

Slack	1.181
Data Arrival Time	10.467
Data Required Time	11.648
From	Mdu/u_mdu/reg1_Z[2]
To	Mdu/u_mdu/reg0_Z[7]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.683	0.683	tINS	RR	501	IOT48[A]	clk_ibuf/O
1.883	1.201	tNET	RR	1	R48C31[1][A]	Mdu/u_mdu/reg1_Z[2]/CLK
2.115	0.232	tC2Q	RF	8	R48C31[1][A]	Mdu/u_mdu/reg1_Z[2]/Q
2.811	0.696	tNET	FF	1	R43C31[1][B]	Mdu/u_mdu/adder_sum_s_2_sf_lofx_cZ/I1
3.182	0.371	tINS	FF	1	R43C31[1][B]	Mdu/u_mdu/adder_sum_s_2_sf_lofx_cZ/F
3.915	0.733	tNET	FF	2	R44C31[2][A]	Mdu/u_mdu/adder_sum_cry_2_0/I0
4.485	0.570	tINS	FR	1	R44C31[2][A]	Mdu/u_mdu/adder_sum_cry_2_0/COUT
4.485	0.000	tNET	RR	2	R44C31[2][B]	Mdu/u_mdu/adder_sum_cry_3_0/CIN
4.520	0.035	tINS	RF	1	R44C31[2][B]	Mdu/u_mdu/adder_sum_cry_3_0/COUT
4.520	0.000	tNET	FF	2	R44C32[0][A]	Mdu/u_mdu/adder_sum_cry_4_0/CIN
4.555	0.035	tINS	FF	1	R44C32[0][A]	Mdu/u_mdu/adder_sum_cry_4_0/COUT
4.555	0.000	tNET	FF	2	R44C32[0][B]	Mdu/u_mdu/adder_sum_cry_5_0/CIN
4.590	0.035	tINS	FF	1	R44C32[0][B]	Mdu/u_mdu/adder_sum_cry_5_0/COUT
4.590	0.000	tNET	FF	2	R44C32[1][A]	Mdu/u_mdu/adder_sum_cry_6_0/CIN
4.626	0.035	tINS	FF	1	R44C32[1][A]	Mdu/u_mdu/adder_sum_cry_6_0/COUT
4.626	0.000	tNET	FF	2	R44C32[1][B]	Mdu/u_mdu/adder_sum_cry_7_0/CIN
4.661	0.035	tINS	FF	1	R44C32[1][B]	Mdu/u_mdu/adder_sum_cry_7_0/COUT
4.661	0.000	tNET	FF	2	R44C32[2][A]	Mdu/u_mdu/adder_sum_cry_8_0/CIN
4.696	0.035	tINS	FF	1	R44C32[2][A]	Mdu/u_mdu/adder_sum_cry_8_0/COUT
4.696	0.000	tNET	FF	2	R44C32[2][B]	Mdu/u_mdu/adder_sum_cry_9_0/CIN
4.731	0.035	tINS	FF	1	R44C32[2][B]	Mdu/u_mdu/adder_sum_cry_9_0/COUT
4.731	0.000	tNET	FF	2	R44C33[0][A]	Mdu/u_mdu/adder_sum_cry_10_0/CIN
4.766	0.035	tINS	FF	1	R44C33[0][A]	Mdu/u_mdu/adder_sum_cry_10_0/COUT
4.766	0.000	tNET	FF	2	R44C33[0][B]	Mdu/u_mdu/adder_sum_cry_11_0/CIN
4.802	0.035	tINS	FF	1	R44C33[0][B]	Mdu/u_mdu/adder_sum_cry_11_0/COUT
4.802	0.000	tNET	FF	2	R44C33[1][A]	Mdu/u_mdu/adder_sum_cry_12_0/CIN
4.837	0.035	tINS	FF	1	R44C33[1][A]	Mdu/u_mdu/adder_sum_cry_12_0/COUT
4.837	0.000	tNET	FF	2	R44C33[1][B]	Mdu/u_mdu/adder_sum_cry_13_0/CIN
4.872	0.035	tINS	FF	1	R44C33[1][B]	Mdu/u_mdu/adder_sum_cry_13_0/COUT
4.872	0.000	tNET	FF	2	R44C33[2][A]	Mdu/u_mdu/adder_sum_cry_14_0/CIN
4.907	0.035	tINS	FF	1	R44C33[2][A]	Mdu/u_mdu/adder_sum_cry_14_0/COUT
4.907	0.000	tNET	FF	2	R44C33[2][B]	Mdu/u_mdu/adder_sum_cry_15_0/CIN
4.942	0.035	tINS	FF	1	R44C33[2][B]	Mdu/u_mdu/adder_sum_cry_15_0/COUT
4.942	0.000	tNET	FF	2	R44C34[0][A]	Mdu/u_mdu/adder_sum_cry_16_0/CIN
4.978	0.035	tINS	FF	1	R44C34[0][A]	Mdu/u_mdu/adder_sum_cry_16_0/COUT
4.978	0.000	tNET	FF	2	R44C34[0][B]	Mdu/u_mdu/adder_sum_cry_17_0/CIN
5.013	0.035	tINS	FF	1	R44C34[0][B]	Mdu/u_mdu/adder_sum_cry_17_0/COUT
5.013	0.000	tNET	FF	2	R44C34[1][A]	Mdu/u_mdu/adder_sum_cry_18_0/CIN
5.048	0.035	tINS	FF	1	R44C34[1][A]	Mdu/u_mdu/adder_sum_cry_18_0/COUT
5.048	0.000	tNET	FF	2	R44C34[1][B]	Mdu/u_mdu/adder_sum_cry_19_0/CIN
5.083	0.035	tINS	FF	1	R44C34[1][B]	Mdu/u_mdu/adder_sum_cry_19_0/COUT
5.083	0.000	tNET	FF	2	R44C34[2][A]	Mdu/u_mdu/adder_sum_cry_20_0/CIN
5.118	0.035	tINS	FF	1	R44C34[2][A]	Mdu/u_mdu/adder_sum_cry_20_0/COUT
5.118	0.000	tNET	FF	2	R44C34[2][B]	Mdu/u_mdu/adder_sum_cry_21_0/CIN
5.154	0.035	tINS	FF	1	R44C34[2][B]	Mdu/u_mdu/adder_sum_cry_21_0/COUT
5.154	0.000	tNET	FF	2	R44C35[0][A]	Mdu/u_mdu/adder_sum_cry_22_0/CIN
5.189	0.035	tINS	FF	1	R44C35[0][A]	Mdu/u_mdu/adder_sum_cry_22_0/COUT
5.189	0.000	tNET	FF	2	R44C35[0][B]	Mdu/u_mdu/adder_sum_cry_23_0/CIN
5.224	0.035	tINS	FF	1	R44C35[0][B]	Mdu/u_mdu/adder_sum_cry_23_0/COUT
5.224	0.000	tNET	FF	2	R44C35[1][A]	Mdu/u_mdu/adder_sum_cry_24_0/CIN
5.259	0.035	tINS	FF	1	R44C35[1][A]	Mdu/u_mdu/adder_sum_cry_24_0/COUT
5.259	0.000	tNET	FF	2	R44C35[1][B]	Mdu/u_mdu/adder_sum_cry_25_0/CIN
5.294	0.035	tINS	FF	1	R44C35[1][B]	Mdu/u_mdu/adder_sum_cry_25_0/COUT
5.294	0.000	tNET	FF	2	R44C35[2][A]	Mdu/u_mdu/adder_sum_cry_26_0/CIN
5.330	0.035	tINS	FF	1	R44C35[2][A]	Mdu/u_mdu/adder_sum_cry_26_0/COUT
5.330	0.000	tNET	FF	2	R44C35[2][B]	Mdu/u_mdu/adder_sum_cry_27_0/CIN
5.365	0.035	tINS	FF	1	R44C35[2][B]	Mdu/u_mdu/adder_sum_cry_27_0/COUT
5.365	0.000	tNET	FF	2	R44C36[0][A]	Mdu/u_mdu/adder_sum_cry_28_0/CIN
5.400	0.035	tINS	FF	1	R44C36[0][A]	Mdu/u_mdu/adder_sum_cry_28_0/COUT
5.400	0.000	tNET	FF	2	R44C36[0][B]	Mdu/u_mdu/adder_sum_cry_29_0/CIN
5.435	0.035	tINS	FF	1	R44C36[0][B]	Mdu/u_mdu/adder_sum_cry_29_0/COUT
5.435	0.000	tNET	FF	2	R44C36[1][A]	Mdu/u_mdu/adder_sum_cry_30_0/CIN
5.470	0.035	tINS	FF	1	R44C36[1][A]	Mdu/u_mdu/adder_sum_cry_30_0/COUT
5.470	0.000	tNET	FF	2	R44C36[1][B]	Mdu/u_mdu/adder_sum_cry_31_0/CIN
5.506	0.035	tINS	FF	1	R44C36[1][B]	Mdu/u_mdu/adder_sum_cry_31_0/COUT
5.506	0.000	tNET	FF	2	R44C36[2][A]	Mdu/u_mdu/adder_sum_s_32_0/CIN
5.976	0.470	tINS	FF	6	R44C36[2][A]	Mdu/u_mdu/adder_sum_s_32_0/SUM
6.402	0.426	tNET	FF	1	R43C34[1][A]	Mdu/u_mdu/reg0_exe_nx_ss0_cZ/I0
6.773	0.371	tINS	FF	50	R43C34[1][A]	Mdu/u_mdu/reg0_exe_nx_ss0_cZ/F
7.515	0.742	tNET	FF	1	R39C37[2][B]	Mdu/u_mdu/reg0_exe_nx_m1_cZ[7]/I3
8.032	0.517	tINS	FF	1	R39C37[2][B]	Mdu/u_mdu/reg0_exe_nx_m1_cZ[7]/F
8.550	0.518	tNET	FF	1	R33C37[0][B]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[7]/I1
9.067	0.517	tINS	FF	1	R33C37[0][B]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[7]/F
9.630	0.563	tNET	FF	1	R32C37[3][A]	Mdu/u_mdu/reg0_exe_nx_cZ[7]/I3
10.001	0.371	tINS	FF	1	R32C37[3][A]	Mdu/u_mdu/reg0_exe_nx_cZ[7]/F
10.005	0.004	tNET	FF	1	R32C37[2][B]	Mdu/u_mdu/reg0_nx_cZ[7]/I0
10.467	0.462	tINS	FR	1	R32C37[2][B]	Mdu/u_mdu/reg0_nx_cZ[7]/F
10.467	0.000	tNET	RR	1	R32C37[2][B]	Mdu/u_mdu/reg0_Z[7]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	501	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R32C37[2][B]	Mdu/u_mdu/reg0_Z[7]/CLK
11.683	-0.200	tUnc				Mdu/u_mdu/reg0_Z[7]
11.648	-0.035	tSu		1	R32C37[2][B]	Mdu/u_mdu/reg0_Z[7]

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	8
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 4.670, 54.403%; route: 3.682, 42.895%; tC2Q: 0.232, 2.703%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path15

Path Summary:

Slack	1.182
Data Arrival Time	10.467
Data Required Time	11.648
From	Mdu/u_mdu/reg0_6_rep1_Z
To	Mdu/u_mdu/reg0_6_rep1_Z
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.683	0.683	tINS	RR	501	IOT48[A]	clk_ibuf/O
1.883	1.201	tNET	RR	1	R33C33[2][A]	Mdu/u_mdu/reg0_6_rep1_Z/CLK
2.115	0.232	tC2Q	RF	7	R33C33[2][A]	Mdu/u_mdu/reg0_6_rep1_Z/Q
2.792	0.677	tNET	FF	1	R34C37[1][B]	Mdu/u_mdu/reg0_neg_axb_4_par_0_cp_0_cZ/I1
3.347	0.555	tINS	FF	1	R34C37[1][B]	Mdu/u_mdu/reg0_neg_axb_4_par_0_cp_0_cZ/F
4.452	1.105	tNET	FF	2	R48C37[1][B]	Mdu/u_mdu/reg0_neg_axb_4_par_cp_0_0/I0
5.022	0.570	tINS	FR	1	R48C37[1][B]	Mdu/u_mdu/reg0_neg_axb_4_par_cp_0_0/COUT
5.022	0.000	tNET	RR	2	R48C37[2][A]	Mdu/u_mdu/reg0_neg_axb_8_par_cp_1/CIN
5.057	0.035	tINS	RF	1	R48C37[2][A]	Mdu/u_mdu/reg0_neg_axb_8_par_cp_1/COUT
5.057	0.000	tNET	FF	2	R48C37[2][B]	Mdu/u_mdu/reg0_neg_axb_12_par_cp_1/CIN
5.092	0.035	tINS	FF	1	R48C37[2][B]	Mdu/u_mdu/reg0_neg_axb_12_par_cp_1/COUT
5.092	0.000	tNET	FF	2	R48C38[0][A]	Mdu/u_mdu/reg0_neg_axb_16_par_cp_1/CIN
5.127	0.035	tINS	FF	1	R48C38[0][A]	Mdu/u_mdu/reg0_neg_axb_16_par_cp_1/COUT
5.127	0.000	tNET	FF	2	R48C38[0][B]	Mdu/u_mdu/reg0_neg_axb_19_par_1/CIN
5.162	0.035	tINS	FF	1	R48C38[0][B]	Mdu/u_mdu/reg0_neg_axb_19_par_1/COUT
5.162	0.000	tNET	FF	2	R48C38[1][A]	Mdu/u_mdu/reg0_neg_axb_23_par_1/CIN
5.198	0.035	tINS	FF	1	R48C38[1][A]	Mdu/u_mdu/reg0_neg_axb_23_par_1/COUT
5.198	0.000	tNET	FF	2	R48C38[1][B]	Mdu/u_mdu/reg0_neg_axb_27_par_1/CIN
5.233	0.035	tINS	FF	1	R48C38[1][B]	Mdu/u_mdu/reg0_neg_axb_27_par_1/COUT
5.233	0.000	tNET	FF	2	R48C38[2][A]	Mdu/u_mdu/reg0_neg_axb_31_par_1/CIN
5.268	0.035	tINS	FF	1	R48C38[2][A]	Mdu/u_mdu/reg0_neg_axb_31_par_1/COUT
5.268	0.000	tNET	FF	2	R48C38[2][B]	Mdu/u_mdu/reg0_neg_cry_34_0/CIN
5.303	0.035	tINS	FF	1	R48C38[2][B]	Mdu/u_mdu/reg0_neg_cry_34_0/COUT
5.303	0.000	tNET	FF	2	R48C39[0][A]	Mdu/u_mdu/reg0_neg_cry_35_0/CIN
5.338	0.035	tINS	FF	1	R48C39[0][A]	Mdu/u_mdu/reg0_neg_cry_35_0/COUT
5.338	0.000	tNET	FF	2	R48C39[0][B]	Mdu/u_mdu/reg0_neg_cry_36_0/CIN
5.374	0.035	tINS	FF	1	R48C39[0][B]	Mdu/u_mdu/reg0_neg_cry_36_0/COUT
5.374	0.000	tNET	FF	2	R48C39[1][A]	Mdu/u_mdu/reg0_neg_cry_37_0/CIN
5.409	0.035	tINS	FF	1	R48C39[1][A]	Mdu/u_mdu/reg0_neg_cry_37_0/COUT
5.409	0.000	tNET	FF	2	R48C39[1][B]	Mdu/u_mdu/reg0_neg_cry_38_0/CIN
5.879	0.470	tINS	FF	1	R48C39[1][B]	Mdu/u_mdu/reg0_neg_cry_38_0/SUM
6.563	0.684	tNET	FF	1	R42C40[3][A]	Mdu/u_mdu/reg0_post_swap_2[6]/I2
7.118	0.555	tINS	FF	1	R42C40[3][A]	Mdu/u_mdu/reg0_post_swap_2[6]/F
7.118	0.000	tNET	FF	1	R42C40[3][A]	Mdu/u_mdu/reg0_post_swap_4[6]/I0
7.221	0.103	tINS	FF	1	R42C40[3][A]	Mdu/u_mdu/reg0_post_swap_4[6]/O
8.501	1.280	tNET	FF	1	R35C40[0][B]	Mdu/u_mdu/reg0_post_swap_5[6]/I1
8.954	0.453	tINS	FF	4	R35C40[0][B]	Mdu/u_mdu/reg0_post_swap_5[6]/F
9.897	0.943	tNET	FF	1	R33C33[2][A]	Mdu/u_mdu/reg0_nx_rep1_cZ[6]/I1
10.467	0.570	tINS	FR	1	R33C33[2][A]	Mdu/u_mdu/reg0_nx_rep1_cZ[6]/F
10.467	0.000	tNET	RR	1	R33C33[2][A]	Mdu/u_mdu/reg0_6_rep1_Z/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	501	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R33C33[2][A]	Mdu/u_mdu/reg0_6_rep1_Z/CLK
11.683	-0.200	tUnc				Mdu/u_mdu/reg0_6_rep1_Z
11.648	-0.035	tSu		1	R33C33[2][A]	Mdu/u_mdu/reg0_6_rep1_Z

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 3.663, 42.678%; route: 4.688, 54.619%; tC2Q: 0.232, 2.703%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path16

Path Summary:

Slack	1.182
Data Arrival Time	10.467
Data Required Time	11.648
From	Mdu/u_mdu/reg0_6_rep1_Z
To	Mdu/u_mdu/reg0_Z[6]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.683	0.683	tINS	RR	501	IOT48[A]	clk_ibuf/O
1.883	1.201	tNET	RR	1	R33C33[2][A]	Mdu/u_mdu/reg0_6_rep1_Z/CLK
2.115	0.232	tC2Q	RF	7	R33C33[2][A]	Mdu/u_mdu/reg0_6_rep1_Z/Q
2.792	0.677	tNET	FF	1	R34C37[1][B]	Mdu/u_mdu/reg0_neg_axb_4_par_0_cp_0_cZ/I1
3.347	0.555	tINS	FF	1	R34C37[1][B]	Mdu/u_mdu/reg0_neg_axb_4_par_0_cp_0_cZ/F
4.452	1.105	tNET	FF	2	R48C37[1][B]	Mdu/u_mdu/reg0_neg_axb_4_par_cp_0_0/I0
5.022	0.570	tINS	FR	1	R48C37[1][B]	Mdu/u_mdu/reg0_neg_axb_4_par_cp_0_0/COUT
5.022	0.000	tNET	RR	2	R48C37[2][A]	Mdu/u_mdu/reg0_neg_axb_8_par_cp_1/CIN
5.057	0.035	tINS	RF	1	R48C37[2][A]	Mdu/u_mdu/reg0_neg_axb_8_par_cp_1/COUT
5.057	0.000	tNET	FF	2	R48C37[2][B]	Mdu/u_mdu/reg0_neg_axb_12_par_cp_1/CIN
5.092	0.035	tINS	FF	1	R48C37[2][B]	Mdu/u_mdu/reg0_neg_axb_12_par_cp_1/COUT
5.092	0.000	tNET	FF	2	R48C38[0][A]	Mdu/u_mdu/reg0_neg_axb_16_par_cp_1/CIN
5.127	0.035	tINS	FF	1	R48C38[0][A]	Mdu/u_mdu/reg0_neg_axb_16_par_cp_1/COUT
5.127	0.000	tNET	FF	2	R48C38[0][B]	Mdu/u_mdu/reg0_neg_axb_19_par_1/CIN
5.162	0.035	tINS	FF	1	R48C38[0][B]	Mdu/u_mdu/reg0_neg_axb_19_par_1/COUT
5.162	0.000	tNET	FF	2	R48C38[1][A]	Mdu/u_mdu/reg0_neg_axb_23_par_1/CIN
5.198	0.035	tINS	FF	1	R48C38[1][A]	Mdu/u_mdu/reg0_neg_axb_23_par_1/COUT
5.198	0.000	tNET	FF	2	R48C38[1][B]	Mdu/u_mdu/reg0_neg_axb_27_par_1/CIN
5.233	0.035	tINS	FF	1	R48C38[1][B]	Mdu/u_mdu/reg0_neg_axb_27_par_1/COUT
5.233	0.000	tNET	FF	2	R48C38[2][A]	Mdu/u_mdu/reg0_neg_axb_31_par_1/CIN
5.268	0.035	tINS	FF	1	R48C38[2][A]	Mdu/u_mdu/reg0_neg_axb_31_par_1/COUT
5.268	0.000	tNET	FF	2	R48C38[2][B]	Mdu/u_mdu/reg0_neg_cry_34_0/CIN
5.303	0.035	tINS	FF	1	R48C38[2][B]	Mdu/u_mdu/reg0_neg_cry_34_0/COUT
5.303	0.000	tNET	FF	2	R48C39[0][A]	Mdu/u_mdu/reg0_neg_cry_35_0/CIN
5.338	0.035	tINS	FF	1	R48C39[0][A]	Mdu/u_mdu/reg0_neg_cry_35_0/COUT
5.338	0.000	tNET	FF	2	R48C39[0][B]	Mdu/u_mdu/reg0_neg_cry_36_0/CIN
5.374	0.035	tINS	FF	1	R48C39[0][B]	Mdu/u_mdu/reg0_neg_cry_36_0/COUT
5.374	0.000	tNET	FF	2	R48C39[1][A]	Mdu/u_mdu/reg0_neg_cry_37_0/CIN
5.409	0.035	tINS	FF	1	R48C39[1][A]	Mdu/u_mdu/reg0_neg_cry_37_0/COUT
5.409	0.000	tNET	FF	2	R48C39[1][B]	Mdu/u_mdu/reg0_neg_cry_38_0/CIN
5.879	0.470	tINS	FF	1	R48C39[1][B]	Mdu/u_mdu/reg0_neg_cry_38_0/SUM
6.563	0.684	tNET	FF	1	R42C40[3][A]	Mdu/u_mdu/reg0_post_swap_2[6]/I2
7.118	0.555	tINS	FF	1	R42C40[3][A]	Mdu/u_mdu/reg0_post_swap_2[6]/F
7.118	0.000	tNET	FF	1	R42C40[3][A]	Mdu/u_mdu/reg0_post_swap_4[6]/I0
7.221	0.103	tINS	FF	1	R42C40[3][A]	Mdu/u_mdu/reg0_post_swap_4[6]/O
8.501	1.280	tNET	FF	1	R35C40[0][B]	Mdu/u_mdu/reg0_post_swap_5[6]/I1
8.954	0.453	tINS	FF	4	R35C40[0][B]	Mdu/u_mdu/reg0_post_swap_5[6]/F
9.897	0.943	tNET	FF	1	R33C33[2][B]	Mdu/u_mdu/reg0_nx_cZ[6]/I1
10.467	0.570	tINS	FR	1	R33C33[2][B]	Mdu/u_mdu/reg0_nx_cZ[6]/F
10.467	0.000	tNET	RR	1	R33C33[2][B]	Mdu/u_mdu/reg0_Z[6]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	501	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R33C33[2][B]	Mdu/u_mdu/reg0_Z[6]/CLK
11.683	-0.200	tUnc				Mdu/u_mdu/reg0_Z[6]
11.648	-0.035	tSu		1	R33C33[2][B]	Mdu/u_mdu/reg0_Z[6]

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 3.663, 42.678%; route: 4.688, 54.619%; tC2Q: 0.232, 2.703%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path17

Path Summary:

Slack	1.182
Data Arrival Time	10.466
Data Required Time	11.648
From	Mdu/u_mdu/div_shift_number_Z[2]
To	Mdu/u_mdu/reg0_Z[41]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.683	0.683	tINS	RR	501	IOT48[A]	clk_ibuf/O
1.883	1.201	tNET	RR	1	R38C40[2][A]	Mdu/u_mdu/div_shift_number_Z[2]/CLK
2.115	0.232	tC2Q	RF	12	R38C40[2][A]	Mdu/u_mdu/div_shift_number_Z[2]/Q
2.553	0.437	tNET	FF	1	R37C41[3][B]	Mdu/u_mdu/div_shift_number_RNI5MR3_2[2]/I0
3.108	0.555	tINS	FF	70	R37C41[3][B]	Mdu/u_mdu/div_shift_number_RNI5MR3_2[2]/F
5.698	2.591	tNET	FF	1	R42C43[3][B]	Mdu/u_mdu/m41_2_03_0_cZ/I0
6.268	0.570	tINS	FR	1	R42C43[3][B]	Mdu/u_mdu/m41_2_03_0_cZ/F
6.270	0.001	tNET	RR	1	R42C43[0][A]	Mdu/u_mdu/m41_2_03_cZ/I0
6.787	0.517	tINS	RF	2	R42C43[0][A]	Mdu/u_mdu/m41_2_03_cZ/F
7.475	0.688	tNET	FF	1	R44C38[0][A]	Mdu/u_mdu/m41_4_03_0_0_cZ/I3
8.030	0.555	tINS	FF	1	R44C38[0][A]	Mdu/u_mdu/m41_4_03_0_0_cZ/F
8.548	0.518	tNET	FF	1	R44C32[3][B]	Mdu/u_mdu/reg0_exe_nx_m1_cZ[41]/I1
9.103	0.555	tINS	FF	1	R44C32[3][B]	Mdu/u_mdu/reg0_exe_nx_m1_cZ[41]/F
9.103	0.000	tNET	FF	1	R44C32[3][A]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[41]/I1
9.206	0.103	tINS	FF	1	R44C32[3][A]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[41]/O
9.896	0.690	tNET	FF	1	R47C40[2][B]	Mdu/u_mdu/reg0_nx_cZ[41]/I0
10.466	0.570	tINS	FR	1	R47C40[2][B]	Mdu/u_mdu/reg0_nx_cZ[41]/F
10.466	0.000	tNET	RR	1	R47C40[2][B]	Mdu/u_mdu/reg0_Z[41]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	501	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R47C40[2][B]	Mdu/u_mdu/reg0_Z[41]/CLK
11.683	-0.200	tUnc				Mdu/u_mdu/reg0_Z[41]
11.648	-0.035	tSu		1	R47C40[2][B]	Mdu/u_mdu/reg0_Z[41]

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 3.425, 39.906%; route: 4.926, 57.391%; tC2Q: 0.232, 2.703%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path18

Path Summary:

Slack	1.203
Data Arrival Time	10.446
Data Required Time	11.648
From	Mdu/u_mdu/reg0_6_rep1_Z
To	Mdu/u_mdu/reg0_fast_Z[6]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.683	0.683	tINS	RR	501	IOT48[A]	clk_ibuf/O
1.883	1.201	tNET	RR	1	R33C33[2][A]	Mdu/u_mdu/reg0_6_rep1_Z/CLK
2.115	0.232	tC2Q	RF	7	R33C33[2][A]	Mdu/u_mdu/reg0_6_rep1_Z/Q
2.792	0.677	tNET	FF	1	R34C37[1][B]	Mdu/u_mdu/reg0_neg_axb_4_par_0_cp_0_cZ/I1
3.347	0.555	tINS	FF	1	R34C37[1][B]	Mdu/u_mdu/reg0_neg_axb_4_par_0_cp_0_cZ/F
4.452	1.105	tNET	FF	2	R48C37[1][B]	Mdu/u_mdu/reg0_neg_axb_4_par_cp_0_0/I0
5.022	0.570	tINS	FR	1	R48C37[1][B]	Mdu/u_mdu/reg0_neg_axb_4_par_cp_0_0/COUT
5.022	0.000	tNET	RR	2	R48C37[2][A]	Mdu/u_mdu/reg0_neg_axb_8_par_cp_1/CIN
5.057	0.035	tINS	RF	1	R48C37[2][A]	Mdu/u_mdu/reg0_neg_axb_8_par_cp_1/COUT
5.057	0.000	tNET	FF	2	R48C37[2][B]	Mdu/u_mdu/reg0_neg_axb_12_par_cp_1/CIN
5.092	0.035	tINS	FF	1	R48C37[2][B]	Mdu/u_mdu/reg0_neg_axb_12_par_cp_1/COUT
5.092	0.000	tNET	FF	2	R48C38[0][A]	Mdu/u_mdu/reg0_neg_axb_16_par_cp_1/CIN
5.127	0.035	tINS	FF	1	R48C38[0][A]	Mdu/u_mdu/reg0_neg_axb_16_par_cp_1/COUT
5.127	0.000	tNET	FF	2	R48C38[0][B]	Mdu/u_mdu/reg0_neg_axb_19_par_1/CIN
5.162	0.035	tINS	FF	1	R48C38[0][B]	Mdu/u_mdu/reg0_neg_axb_19_par_1/COUT
5.162	0.000	tNET	FF	2	R48C38[1][A]	Mdu/u_mdu/reg0_neg_axb_23_par_1/CIN
5.198	0.035	tINS	FF	1	R48C38[1][A]	Mdu/u_mdu/reg0_neg_axb_23_par_1/COUT
5.198	0.000	tNET	FF	2	R48C38[1][B]	Mdu/u_mdu/reg0_neg_axb_27_par_1/CIN
5.233	0.035	tINS	FF	1	R48C38[1][B]	Mdu/u_mdu/reg0_neg_axb_27_par_1/COUT
5.233	0.000	tNET	FF	2	R48C38[2][A]	Mdu/u_mdu/reg0_neg_axb_31_par_1/CIN
5.268	0.035	tINS	FF	1	R48C38[2][A]	Mdu/u_mdu/reg0_neg_axb_31_par_1/COUT
5.268	0.000	tNET	FF	2	R48C38[2][B]	Mdu/u_mdu/reg0_neg_cry_34_0/CIN
5.303	0.035	tINS	FF	1	R48C38[2][B]	Mdu/u_mdu/reg0_neg_cry_34_0/COUT
5.303	0.000	tNET	FF	2	R48C39[0][A]	Mdu/u_mdu/reg0_neg_cry_35_0/CIN
5.338	0.035	tINS	FF	1	R48C39[0][A]	Mdu/u_mdu/reg0_neg_cry_35_0/COUT
5.338	0.000	tNET	FF	2	R48C39[0][B]	Mdu/u_mdu/reg0_neg_cry_36_0/CIN
5.374	0.035	tINS	FF	1	R48C39[0][B]	Mdu/u_mdu/reg0_neg_cry_36_0/COUT
5.374	0.000	tNET	FF	2	R48C39[1][A]	Mdu/u_mdu/reg0_neg_cry_37_0/CIN
5.409	0.035	tINS	FF	1	R48C39[1][A]	Mdu/u_mdu/reg0_neg_cry_37_0/COUT
5.409	0.000	tNET	FF	2	R48C39[1][B]	Mdu/u_mdu/reg0_neg_cry_38_0/CIN
5.879	0.470	tINS	FF	1	R48C39[1][B]	Mdu/u_mdu/reg0_neg_cry_38_0/SUM
6.563	0.684	tNET	FF	1	R42C40[3][A]	Mdu/u_mdu/reg0_post_swap_2[6]/I2
7.118	0.555	tINS	FF	1	R42C40[3][A]	Mdu/u_mdu/reg0_post_swap_2[6]/F
7.118	0.000	tNET	FF	1	R42C40[3][A]	Mdu/u_mdu/reg0_post_swap_4[6]/I0
7.221	0.103	tINS	FF	1	R42C40[3][A]	Mdu/u_mdu/reg0_post_swap_4[6]/O
8.501	1.280	tNET	FF	1	R35C40[0][B]	Mdu/u_mdu/reg0_post_swap_5[6]/I1
8.954	0.453	tINS	FF	4	R35C40[0][B]	Mdu/u_mdu/reg0_post_swap_5[6]/F
9.897	0.943	tNET	FF	1	R33C33[0][B]	Mdu/u_mdu/reg0_nx_fast_cZ[6]/I1
10.446	0.549	tINS	FR	1	R33C33[0][B]	Mdu/u_mdu/reg0_nx_fast_cZ[6]/F
10.446	0.000	tNET	RR	1	R33C33[0][B]	Mdu/u_mdu/reg0_fast_Z[6]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	501	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R33C33[0][B]	Mdu/u_mdu/reg0_fast_Z[6]/CLK
11.683	-0.200	tUnc				Mdu/u_mdu/reg0_fast_Z[6]
11.648	-0.035	tSu		1	R33C33[0][B]	Mdu/u_mdu/reg0_fast_Z[6]

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 3.642, 42.537%; route: 4.688, 54.753%; tC2Q: 0.232, 2.710%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path19

Path Summary:

Slack	1.206
Data Arrival Time	10.443
Data Required Time	11.648
From	Mdu/u_mdu/div_shift_number_Z[2]
To	Mdu/u_mdu/reg0_Z[57]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.683	0.683	tINS	RR	501	IOT48[A]	clk_ibuf/O
1.883	1.201	tNET	RR	1	R38C40[2][A]	Mdu/u_mdu/div_shift_number_Z[2]/CLK
2.115	0.232	tC2Q	RF	12	R38C40[2][A]	Mdu/u_mdu/div_shift_number_Z[2]/Q
2.553	0.437	tNET	FF	1	R37C41[3][B]	Mdu/u_mdu/div_shift_number_RNI5MR3_2[2]/I0
3.108	0.555	tINS	FF	70	R37C41[3][B]	Mdu/u_mdu/div_shift_number_RNI5MR3_2[2]/F
5.456	2.348	tNET	FF	1	R42C44[1][B]	Mdu/u_mdu/m57_2_03_0_cZ/I0
6.026	0.570	tINS	FR	1	R42C44[1][B]	Mdu/u_mdu/m57_2_03_0_cZ/F
6.027	0.001	tNET	RR	1	R42C44[0][A]	Mdu/u_mdu/m57_2_03_cZ/I0
6.582	0.555	tINS	RF	1	R42C44[0][A]	Mdu/u_mdu/m57_2_03_cZ/F
7.238	0.656	tNET	FF	1	R44C41[1][A]	Mdu/u_mdu/m57_4_03_1_0_cZ/I3
7.793	0.555	tINS	FF	1	R44C41[1][A]	Mdu/u_mdu/m57_4_03_1_0_cZ/F
8.432	0.640	tNET	FF	1	R44C37[3][A]	Mdu/u_mdu/reg0_exe_nx_m0_cZ[57]/I2
8.885	0.453	tINS	FF	1	R44C37[3][A]	Mdu/u_mdu/reg0_exe_nx_m0_cZ[57]/F
8.885	0.000	tNET	FF	1	R44C37[3][A]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[57]/I0
8.988	0.103	tINS	FF	1	R44C37[3][A]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[57]/O
9.873	0.884	tNET	FF	1	R51C44[1][B]	Mdu/u_mdu/reg0_nx_cZ[57]/I0
10.443	0.570	tINS	FR	1	R51C44[1][B]	Mdu/u_mdu/reg0_nx_cZ[57]/F
10.443	0.000	tNET	RR	1	R51C44[1][B]	Mdu/u_mdu/reg0_Z[57]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	501	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R51C44[1][B]	Mdu/u_mdu/reg0_Z[57]/CLK
11.683	-0.200	tUnc				Mdu/u_mdu/reg0_Z[57]
11.648	-0.035	tSu		1	R51C44[1][B]	Mdu/u_mdu/reg0_Z[57]

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 3.361, 39.267%; route: 4.966, 58.022%; tC2Q: 0.232, 2.710%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path20

Path Summary:

Slack	1.210
Data Arrival Time	10.438
Data Required Time	11.648
From	Mdu/u_mdu/reg1_Z[2]
To	Mdu/u_mdu/div_shift_number_Z[4]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.683	0.683	tINS	RR	501	IOT48[A]	clk_ibuf/O
1.883	1.201	tNET	RR	1	R48C31[1][A]	Mdu/u_mdu/reg1_Z[2]/CLK
2.115	0.232	tC2Q	RF	8	R48C31[1][A]	Mdu/u_mdu/reg1_Z[2]/Q
3.032	0.916	tNET	FF	1	R51C34[3][A]	Mdu/u_mdu/un5_op1_eq_zero_nx_17_cZ_cZ/I0
3.587	0.555	tINS	FF	1	R51C34[3][A]	Mdu/u_mdu/un5_op1_eq_zero_nx_17_cZ_cZ/F
3.834	0.247	tNET	FF	1	R51C33[3][A]	Mdu/u_mdu/un5_op1_eq_zero_nx_22_cZ_cZ/S0
4.085	0.251	tINS	FF	2	R51C33[3][A]	Mdu/u_mdu/un5_op1_eq_zero_nx_22_cZ_cZ/O
4.755	0.671	tNET	FF	1	R52C36[1][B]	Mdu/u_mdu/un5_op1_eq_zero_nx_x_cZ_cZ/I2
5.325	0.570	tINS	FR	1	R52C36[1][B]	Mdu/u_mdu/un5_op1_eq_zero_nx_x_cZ_cZ/F
5.327	0.001	tNET	RR	1	R52C36[1][A]	Mdu/u_mdu/un1_op1_lead_zero_detect_32_v[0]/I0
5.882	0.555	tINS	RF	2	R52C36[1][A]	Mdu/u_mdu/un1_op1_lead_zero_detect_32_v[0]/F
6.454	0.572	tNET	FF	1	R51C35[3][B]	Mdu/u_mdu/op1_lead_zero_detect_16_p[0]_m_cZ[1]/I3
7.009	0.555	tINS	FF	1	R51C35[3][B]	Mdu/u_mdu/op1_lead_zero_detect_16_p[0]_m_cZ[1]/F
7.693	0.684	tNET	FF	1	R51C38[1][A]	Mdu/u_mdu/un2_div_shift_number_nx_0_cry_1_0_0_RNO_cZ_cZ/I0
8.146	0.453	tINS	FF	1	R51C38[1][A]	Mdu/u_mdu/un2_div_shift_number_nx_0_cry_1_0_0_RNO_cZ_cZ/F
9.327	1.181	tNET	FF	2	R38C40[1][B]	Mdu/u_mdu/un2_div_shift_number_nx_0_cry_1_0_0/I0
9.897	0.570	tINS	FR	1	R38C40[1][B]	Mdu/u_mdu/un2_div_shift_number_nx_0_cry_1_0_0/COUT
9.897	0.000	tNET	RR	2	R38C40[2][A]	Mdu/u_mdu/un2_div_shift_number_nx_0_cry_2_0_0/CIN
9.932	0.035	tINS	RF	1	R38C40[2][A]	Mdu/u_mdu/un2_div_shift_number_nx_0_cry_2_0_0/COUT
9.932	0.000	tNET	FF	2	R38C40[2][B]	Mdu/u_mdu/un2_div_shift_number_nx_0_cry_3_0_0/CIN
9.968	0.035	tINS	FF	1	R38C40[2][B]	Mdu/u_mdu/un2_div_shift_number_nx_0_cry_3_0_0/COUT
9.968	0.000	tNET	FF	2	R38C41[0][A]	Mdu/u_mdu/un2_div_shift_number_nx_0_cry_4_0/CIN
10.438	0.470	tINS	FF	1	R38C41[0][A]	Mdu/u_mdu/un2_div_shift_number_nx_0_cry_4_0/SUM
10.438	0.000	tNET	FF	1	R38C41[0][A]	Mdu/u_mdu/div_shift_number_Z[4]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	501	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R38C41[0][A]	Mdu/u_mdu/div_shift_number_Z[4]/CLK
11.683	-0.200	tUnc				Mdu/u_mdu/div_shift_number_Z[4]
11.648	-0.035	tSu		1	R38C41[0][A]	Mdu/u_mdu/div_shift_number_Z[4]

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	8
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 4.049, 47.336%; route: 4.273, 49.952%; tC2Q: 0.232, 2.712%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path21

Path Summary:

Slack	1.213
Data Arrival Time	10.435
Data Required Time	11.648
From	Mdu/u_mdu/reg0_fast_Z[17]
To	Mdu/u_mdu/reg0_fast_Z[24]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.683	0.683	tINS	RR	501	IOT48[A]	clk_ibuf/O
1.883	1.201	tNET	RR	1	R34C41[0][B]	Mdu/u_mdu/reg0_fast_Z[17]/CLK
2.115	0.232	tC2Q	RF	6	R34C41[0][B]	Mdu/u_mdu/reg0_fast_Z[17]/Q
3.430	1.315	tNET	FF	1	R48C43[2][A]	Mdu/u_mdu/reg0_neg_axb_16_par_0_cp_0_lofx_cZ/I2
3.985	0.555	tINS	FF	1	R48C43[2][A]	Mdu/u_mdu/reg0_neg_axb_16_par_0_cp_0_lofx_cZ/F
4.883	0.899	tNET	FF	2	R51C46[0][A]	Mdu/u_mdu/reg0_neg_axb_16_par_cp_0_0/I0
5.453	0.570	tINS	FR	1	R51C46[0][A]	Mdu/u_mdu/reg0_neg_axb_16_par_cp_0_0/COUT
5.453	0.000	tNET	RR	2	R51C46[0][B]	Mdu/u_mdu/reg0_neg_axb_19_par_cp_0/CIN
5.489	0.035	tINS	RF	1	R51C46[0][B]	Mdu/u_mdu/reg0_neg_axb_19_par_cp_0/COUT
5.489	0.000	tNET	FF	2	R51C46[1][A]	Mdu/u_mdu/reg0_neg_axb_23_par_cp_0/CIN
5.524	0.035	tINS	FF	1	R51C46[1][A]	Mdu/u_mdu/reg0_neg_axb_23_par_cp_0/COUT
5.524	0.000	tNET	FF	2	R51C46[1][B]	Mdu/u_mdu/reg0_neg_axb_27_par_cp_0/CIN
5.559	0.035	tINS	FF	1	R51C46[1][B]	Mdu/u_mdu/reg0_neg_axb_27_par_cp_0/COUT
5.559	0.000	tNET	FF	2	R51C46[2][A]	Mdu/u_mdu/reg0_neg_axb_31_par_cp_0/CIN
5.594	0.035	tINS	FF	1	R51C46[2][A]	Mdu/u_mdu/reg0_neg_axb_31_par_cp_0/COUT
5.594	0.000	tNET	FF	2	R51C46[2][B]	Mdu/u_mdu/reg0_neg_axb_34_par_1/CIN
5.629	0.035	tINS	FF	1	R51C46[2][B]	Mdu/u_mdu/reg0_neg_axb_34_par_1/COUT
5.629	0.000	tNET	FF	2	R51C47[0][A]	Mdu/u_mdu/reg0_neg_axb_38_par_1/CIN
5.665	0.035	tINS	FF	1	R51C47[0][A]	Mdu/u_mdu/reg0_neg_axb_38_par_1/COUT
5.665	0.000	tNET	FF	2	R51C47[0][B]	Mdu/u_mdu/reg0_neg_axb_42_par_1/CIN
5.700	0.035	tINS	FF	1	R51C47[0][B]	Mdu/u_mdu/reg0_neg_axb_42_par_1/COUT
5.700	0.000	tNET	FF	2	R51C47[1][A]	Mdu/u_mdu/reg0_neg_axb_46_par_1/CIN
5.735	0.035	tINS	FF	1	R51C47[1][A]	Mdu/u_mdu/reg0_neg_axb_46_par_1/COUT
5.735	0.000	tNET	FF	2	R51C47[1][B]	Mdu/u_mdu/reg0_neg_axb_50_par_1/CIN
5.770	0.035	tINS	FF	1	R51C47[1][B]	Mdu/u_mdu/reg0_neg_axb_50_par_1/COUT
5.770	0.000	tNET	FF	2	R51C47[2][A]	Mdu/u_mdu/reg0_neg_cry_54_0/CIN
5.805	0.035	tINS	FF	1	R51C47[2][A]	Mdu/u_mdu/reg0_neg_cry_54_0/COUT
5.805	0.000	tNET	FF	2	R51C47[2][B]	Mdu/u_mdu/reg0_neg_cry_55_0/CIN
5.841	0.035	tINS	FF	1	R51C47[2][B]	Mdu/u_mdu/reg0_neg_cry_55_0/COUT
5.841	0.000	tNET	FF	2	R51C48[0][A]	Mdu/u_mdu/reg0_neg_cry_56_0/CIN
6.311	0.470	tINS	FF	1	R51C48[0][A]	Mdu/u_mdu/reg0_neg_cry_56_0/SUM
7.237	0.927	tNET	FF	1	R43C43[3][A]	Mdu/u_mdu/reg0_post_swap_2[24]/I2
7.792	0.555	tINS	FF	1	R43C43[3][A]	Mdu/u_mdu/reg0_post_swap_2[24]/F
7.792	0.000	tNET	FF	1	R43C43[3][A]	Mdu/u_mdu/reg0_post_swap_4[24]/I0
7.895	0.103	tINS	FF	2	R43C43[3][A]	Mdu/u_mdu/reg0_post_swap_4[24]/O
8.323	0.428	tNET	FF	1	R44C41[3][B]	Mdu/u_mdu/un11_reg0_nx_cZ[24]_cZ/I1
8.776	0.453	tINS	FF	2	R44C41[3][B]	Mdu/u_mdu/un11_reg0_nx_cZ[24]_cZ/F
9.886	1.110	tNET	FF	1	R34C37[0][A]	Mdu/u_mdu/reg0_nx_fast_cZ[24]/I3
10.435	0.549	tINS	FR	1	R34C37[0][A]	Mdu/u_mdu/reg0_nx_fast_cZ[24]/F
10.435	0.000	tNET	RR	1	R34C37[0][A]	Mdu/u_mdu/reg0_fast_Z[24]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	501	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R34C37[0][A]	Mdu/u_mdu/reg0_fast_Z[24]/CLK
11.683	-0.200	tUnc				Mdu/u_mdu/reg0_fast_Z[24]
11.648	-0.035	tSu		1	R34C37[0][A]	Mdu/u_mdu/reg0_fast_Z[24]

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 3.642, 42.590%; route: 4.678, 54.697%; tC2Q: 0.232, 2.713%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path22

Path Summary:

Slack	1.218
Data Arrival Time	10.430
Data Required Time	11.648
From	Mdu/u_mdu/div_shift_number_Z[2]
To	Mdu/u_mdu/reg0_Z[61]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.683	0.683	tINS	RR	501	IOT48[A]	clk_ibuf/O
1.883	1.201	tNET	RR	1	R38C40[2][A]	Mdu/u_mdu/div_shift_number_Z[2]/CLK
2.115	0.232	tC2Q	RF	12	R38C40[2][A]	Mdu/u_mdu/div_shift_number_Z[2]/Q
2.553	0.437	tNET	FF	1	R37C41[3][B]	Mdu/u_mdu/div_shift_number_RNI5MR3_2[2]/I0
3.108	0.555	tINS	FF	70	R37C41[3][B]	Mdu/u_mdu/div_shift_number_RNI5MR3_2[2]/F
5.450	2.342	tNET	FF	1	R40C43[3][B]	Mdu/u_mdu/m45_2_03_0_cZ/I0
5.967	0.517	tINS	FF	1	R40C43[3][B]	Mdu/u_mdu/m45_2_03_0_cZ/F
6.364	0.397	tNET	FF	1	R42C43[1][B]	Mdu/u_mdu/m45_2_03_cZ/I0
6.919	0.555	tINS	FF	2	R42C43[1][B]	Mdu/u_mdu/m45_2_03_cZ/F
7.579	0.660	tNET	FF	1	R42C38[3][A]	Mdu/u_mdu/m61_4_03_0_0_cZ/I2
8.096	0.517	tINS	FF	1	R42C38[3][A]	Mdu/u_mdu/m61_4_03_0_0_cZ/F
8.343	0.247	tNET	FF	1	R42C36[1][B]	Mdu/u_mdu/reg0_exe_nx_m1_cZ[61]/I1
8.796	0.453	tINS	FF	1	R42C36[1][B]	Mdu/u_mdu/reg0_exe_nx_m1_cZ[61]/F
8.796	0.000	tNET	FF	1	R42C36[1][A]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[61]/I1
8.899	0.103	tINS	FF	1	R42C36[1][A]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[61]/O
9.860	0.961	tNET	FF	1	R35C30[0][B]	Mdu/u_mdu/reg0_nx_cZ[61]/I0
10.430	0.570	tINS	FR	1	R35C30[0][B]	Mdu/u_mdu/reg0_nx_cZ[61]/F
10.430	0.000	tNET	RR	1	R35C30[0][B]	Mdu/u_mdu/reg0_Z[61]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	501	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R35C30[0][B]	Mdu/u_mdu/reg0_Z[61]/CLK
11.683	-0.200	tUnc				Mdu/u_mdu/reg0_Z[61]
11.648	-0.035	tSu		1	R35C30[0][B]	Mdu/u_mdu/reg0_Z[61]

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 3.270, 38.260%; route: 5.045, 59.025%; tC2Q: 0.232, 2.714%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path23

Path Summary:

Slack	1.238
Data Arrival Time	10.411
Data Required Time	11.648
From	Mdu/u_mdu/div_shift_number_Z[2]
To	Mdu/u_mdu/reg0_Z[53]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.683	0.683	tINS	RR	501	IOT48[A]	clk_ibuf/O
1.883	1.201	tNET	RR	1	R38C40[2][A]	Mdu/u_mdu/div_shift_number_Z[2]/CLK
2.115	0.232	tC2Q	RF	12	R38C40[2][A]	Mdu/u_mdu/div_shift_number_Z[2]/Q
2.553	0.437	tNET	FF	1	R37C41[3][B]	Mdu/u_mdu/div_shift_number_RNI5MR3_2[2]/I0
3.108	0.555	tINS	FF	70	R37C41[3][B]	Mdu/u_mdu/div_shift_number_RNI5MR3_2[2]/F
5.389	2.281	tNET	FF	1	R40C44[3][A]	Mdu/u_mdu/m53_2_03_0_cZ/I0
5.842	0.453	tINS	FF	1	R40C44[3][A]	Mdu/u_mdu/m53_2_03_0_cZ/F
6.239	0.397	tNET	FF	1	R40C42[3][B]	Mdu/u_mdu/m53_2_03_cZ/I0
6.788	0.549	tINS	FR	1	R40C42[3][B]	Mdu/u_mdu/m53_2_03_cZ/F
6.960	0.172	tNET	RR	1	R41C42[3][B]	Mdu/u_mdu/m53_4_03_1_0_cZ/I3
7.331	0.371	tINS	RF	1	R41C42[3][B]	Mdu/u_mdu/m53_4_03_1_0_cZ/F
8.473	1.141	tNET	FF	1	R44C37[2][B]	Mdu/u_mdu/reg0_exe_nx_m1_cZ[53]/I2
8.990	0.517	tINS	FF	1	R44C37[2][B]	Mdu/u_mdu/reg0_exe_nx_m1_cZ[53]/F
8.990	0.000	tNET	FF	1	R44C37[2][A]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[53]/I1
9.093	0.103	tINS	FF	1	R44C37[2][A]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[53]/O
9.949	0.856	tNET	FF	1	R47C44[1][A]	Mdu/u_mdu/reg0_nx_0[53]/I2
10.411	0.462	tINS	FR	1	R47C44[1][A]	Mdu/u_mdu/reg0_nx_0[53]/F
10.411	0.000	tNET	RR	1	R47C44[1][A]	Mdu/u_mdu/reg0_Z[53]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	501	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R47C44[1][A]	Mdu/u_mdu/reg0_Z[53]/CLK
11.683	-0.200	tUnc				Mdu/u_mdu/reg0_Z[53]
11.648	-0.035	tSu		1	R47C44[1][A]	Mdu/u_mdu/reg0_Z[53]

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 3.010, 35.298%; route: 5.285, 61.981%; tC2Q: 0.232, 2.721%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path24

Path Summary:

Slack	1.246
Data Arrival Time	10.402
Data Required Time	11.648
From	Mdu/u_mdu/reg1_Z[2]
To	Mdu/u_mdu/div_shift_number_Z[3]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.683	0.683	tINS	RR	501	IOT48[A]	clk_ibuf/O
1.883	1.201	tNET	RR	1	R48C31[1][A]	Mdu/u_mdu/reg1_Z[2]/CLK
2.115	0.232	tC2Q	RF	8	R48C31[1][A]	Mdu/u_mdu/reg1_Z[2]/Q
3.032	0.916	tNET	FF	1	R51C34[3][A]	Mdu/u_mdu/un5_op1_eq_zero_nx_17_cZ_cZ/I0
3.587	0.555	tINS	FF	1	R51C34[3][A]	Mdu/u_mdu/un5_op1_eq_zero_nx_17_cZ_cZ/F
3.834	0.247	tNET	FF	1	R51C33[3][A]	Mdu/u_mdu/un5_op1_eq_zero_nx_22_cZ_cZ/S0
4.085	0.251	tINS	FF	2	R51C33[3][A]	Mdu/u_mdu/un5_op1_eq_zero_nx_22_cZ_cZ/O
4.755	0.671	tNET	FF	1	R52C36[1][B]	Mdu/u_mdu/un5_op1_eq_zero_nx_x_cZ_cZ/I2
5.325	0.570	tINS	FR	1	R52C36[1][B]	Mdu/u_mdu/un5_op1_eq_zero_nx_x_cZ_cZ/F
5.327	0.001	tNET	RR	1	R52C36[1][A]	Mdu/u_mdu/un1_op1_lead_zero_detect_32_v[0]/I0
5.882	0.555	tINS	RF	2	R52C36[1][A]	Mdu/u_mdu/un1_op1_lead_zero_detect_32_v[0]/F
6.454	0.572	tNET	FF	1	R51C35[3][B]	Mdu/u_mdu/op1_lead_zero_detect_16_p[0]_m_cZ[1]/I3
7.009	0.555	tINS	FF	1	R51C35[3][B]	Mdu/u_mdu/op1_lead_zero_detect_16_p[0]_m_cZ[1]/F
7.693	0.684	tNET	FF	1	R51C38[1][A]	Mdu/u_mdu/un2_div_shift_number_nx_0_cry_1_0_0_RNO_cZ_cZ/I0
8.146	0.453	tINS	FF	1	R51C38[1][A]	Mdu/u_mdu/un2_div_shift_number_nx_0_cry_1_0_0_RNO_cZ_cZ/F
9.327	1.181	tNET	FF	2	R38C40[1][B]	Mdu/u_mdu/un2_div_shift_number_nx_0_cry_1_0_0/I0
9.897	0.570	tINS	FR	1	R38C40[1][B]	Mdu/u_mdu/un2_div_shift_number_nx_0_cry_1_0_0/COUT
9.897	0.000	tNET	RR	2	R38C40[2][A]	Mdu/u_mdu/un2_div_shift_number_nx_0_cry_2_0_0/CIN
9.932	0.035	tINS	RF	1	R38C40[2][A]	Mdu/u_mdu/un2_div_shift_number_nx_0_cry_2_0_0/COUT
9.932	0.000	tNET	FF	2	R38C40[2][B]	Mdu/u_mdu/un2_div_shift_number_nx_0_cry_3_0_0/CIN
10.402	0.470	tINS	FF	1	R38C40[2][B]	Mdu/u_mdu/un2_div_shift_number_nx_0_cry_3_0_0/SUM
10.402	0.000	tNET	FF	1	R38C40[2][B]	Mdu/u_mdu/div_shift_number_Z[3]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	501	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R38C40[2][B]	Mdu/u_mdu/div_shift_number_Z[3]/CLK
11.683	-0.200	tUnc				Mdu/u_mdu/div_shift_number_Z[3]
11.648	-0.035	tSu		1	R38C40[2][B]	Mdu/u_mdu/div_shift_number_Z[3]

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	8
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 4.014, 47.119%; route: 4.273, 50.158%; tC2Q: 0.232, 2.723%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path25

Path Summary:

Slack	1.256
Data Arrival Time	10.392
Data Required Time	11.648
From	Mdu/u_mdu/reg0_6_rep1_Z
To	Mdu/u_mdu/reg0_11_rep1_Z
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.683	0.683	tINS	RR	501	IOT48[A]	clk_ibuf/O
1.883	1.201	tNET	RR	1	R33C33[2][A]	Mdu/u_mdu/reg0_6_rep1_Z/CLK
2.115	0.232	tC2Q	RF	7	R33C33[2][A]	Mdu/u_mdu/reg0_6_rep1_Z/Q
2.792	0.677	tNET	FF	1	R34C37[1][B]	Mdu/u_mdu/reg0_neg_axb_4_par_0_cp_0_cZ/I1
3.347	0.555	tINS	FF	1	R34C37[1][B]	Mdu/u_mdu/reg0_neg_axb_4_par_0_cp_0_cZ/F
4.452	1.105	tNET	FF	2	R48C37[1][B]	Mdu/u_mdu/reg0_neg_axb_4_par_cp_0_0/I0
5.022	0.570	tINS	FR	1	R48C37[1][B]	Mdu/u_mdu/reg0_neg_axb_4_par_cp_0_0/COUT
5.022	0.000	tNET	RR	2	R48C37[2][A]	Mdu/u_mdu/reg0_neg_axb_8_par_cp_1/CIN
5.057	0.035	tINS	RF	1	R48C37[2][A]	Mdu/u_mdu/reg0_neg_axb_8_par_cp_1/COUT
5.057	0.000	tNET	FF	2	R48C37[2][B]	Mdu/u_mdu/reg0_neg_axb_12_par_cp_1/CIN
5.092	0.035	tINS	FF	1	R48C37[2][B]	Mdu/u_mdu/reg0_neg_axb_12_par_cp_1/COUT
5.092	0.000	tNET	FF	2	R48C38[0][A]	Mdu/u_mdu/reg0_neg_axb_16_par_cp_1/CIN
5.127	0.035	tINS	FF	1	R48C38[0][A]	Mdu/u_mdu/reg0_neg_axb_16_par_cp_1/COUT
5.127	0.000	tNET	FF	2	R48C38[0][B]	Mdu/u_mdu/reg0_neg_axb_19_par_1/CIN
5.162	0.035	tINS	FF	1	R48C38[0][B]	Mdu/u_mdu/reg0_neg_axb_19_par_1/COUT
5.162	0.000	tNET	FF	2	R48C38[1][A]	Mdu/u_mdu/reg0_neg_axb_23_par_1/CIN
5.198	0.035	tINS	FF	1	R48C38[1][A]	Mdu/u_mdu/reg0_neg_axb_23_par_1/COUT
5.198	0.000	tNET	FF	2	R48C38[1][B]	Mdu/u_mdu/reg0_neg_axb_27_par_1/CIN
5.233	0.035	tINS	FF	1	R48C38[1][B]	Mdu/u_mdu/reg0_neg_axb_27_par_1/COUT
5.233	0.000	tNET	FF	2	R48C38[2][A]	Mdu/u_mdu/reg0_neg_axb_31_par_1/CIN
5.268	0.035	tINS	FF	1	R48C38[2][A]	Mdu/u_mdu/reg0_neg_axb_31_par_1/COUT
5.268	0.000	tNET	FF	2	R48C38[2][B]	Mdu/u_mdu/reg0_neg_cry_34_0/CIN
5.303	0.035	tINS	FF	1	R48C38[2][B]	Mdu/u_mdu/reg0_neg_cry_34_0/COUT
5.303	0.000	tNET	FF	2	R48C39[0][A]	Mdu/u_mdu/reg0_neg_cry_35_0/CIN
5.338	0.035	tINS	FF	1	R48C39[0][A]	Mdu/u_mdu/reg0_neg_cry_35_0/COUT
5.338	0.000	tNET	FF	2	R48C39[0][B]	Mdu/u_mdu/reg0_neg_cry_36_0/CIN
5.374	0.035	tINS	FF	1	R48C39[0][B]	Mdu/u_mdu/reg0_neg_cry_36_0/COUT
5.374	0.000	tNET	FF	2	R48C39[1][A]	Mdu/u_mdu/reg0_neg_cry_37_0/CIN
5.409	0.035	tINS	FF	1	R48C39[1][A]	Mdu/u_mdu/reg0_neg_cry_37_0/COUT
5.409	0.000	tNET	FF	2	R48C39[1][B]	Mdu/u_mdu/reg0_neg_cry_38_0/CIN
5.444	0.035	tINS	FF	1	R48C39[1][B]	Mdu/u_mdu/reg0_neg_cry_38_0/COUT
5.444	0.000	tNET	FF	2	R48C39[2][A]	Mdu/u_mdu/reg0_neg_cry_39_0/CIN
5.479	0.035	tINS	FF	1	R48C39[2][A]	Mdu/u_mdu/reg0_neg_cry_39_0/COUT
5.479	0.000	tNET	FF	2	R48C39[2][B]	Mdu/u_mdu/reg0_neg_cry_40_0/CIN
5.514	0.035	tINS	FF	1	R48C39[2][B]	Mdu/u_mdu/reg0_neg_cry_40_0/COUT
5.514	0.000	tNET	FF	2	R48C40[0][A]	Mdu/u_mdu/reg0_neg_cry_41_0/CIN
5.550	0.035	tINS	FF	1	R48C40[0][A]	Mdu/u_mdu/reg0_neg_cry_41_0/COUT
5.550	0.000	tNET	FF	2	R48C40[0][B]	Mdu/u_mdu/reg0_neg_cry_42_0/CIN
5.585	0.035	tINS	FF	1	R48C40[0][B]	Mdu/u_mdu/reg0_neg_cry_42_0/COUT
5.585	0.000	tNET	FF	2	R48C40[1][A]	Mdu/u_mdu/reg0_neg_cry_43_0/CIN
6.055	0.470	tINS	FF	1	R48C40[1][A]	Mdu/u_mdu/reg0_neg_cry_43_0/SUM
6.965	0.911	tNET	FF	1	R43C41[3][A]	Mdu/u_mdu/reg0_post_swap_2[11]/I2
7.520	0.555	tINS	FF	1	R43C41[3][A]	Mdu/u_mdu/reg0_post_swap_2[11]/F
7.520	0.000	tNET	FF	1	R43C41[3][A]	Mdu/u_mdu/reg0_post_swap_4[11]/I0
7.623	0.103	tINS	FF	1	R43C41[3][A]	Mdu/u_mdu/reg0_post_swap_4[11]/O
8.390	0.767	tNET	FF	1	R37C43[1][A]	Mdu/u_mdu/reg0_post_swap_5[11]/I1
8.907	0.517	tINS	FF	4	R37C43[1][A]	Mdu/u_mdu/reg0_post_swap_5[11]/F
9.843	0.936	tNET	FF	1	R34C37[1][A]	Mdu/u_mdu/reg0_nx_rep1_cZ[11]/I1
10.392	0.549	tINS	FR	1	R34C37[1][A]	Mdu/u_mdu/reg0_nx_rep1_cZ[11]/F
10.392	0.000	tNET	RR	1	R34C37[1][A]	Mdu/u_mdu/reg0_11_rep1_Z/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	501	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R34C37[1][A]	Mdu/u_mdu/reg0_11_rep1_Z/CLK
11.683	-0.200	tUnc				Mdu/u_mdu/reg0_11_rep1_Z
11.648	-0.035	tSu		1	R34C37[1][A]	Mdu/u_mdu/reg0_11_rep1_Z

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 3.882, 45.626%; route: 4.395, 51.647%; tC2Q: 0.232, 2.727%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Hold Analysis Report

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	0.074
Data Arrival Time	1.900
Data Required Time	1.826
From	u_la0_top/u_ao_mem_ctrl/data_reg_Z[37]
To	u_la0_top/u_ao_mem_ctrl/mem_mem_0_18
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	501	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R11C11[0][B]	u_la0_top/u_ao_mem_ctrl/data_reg_Z[37]/CLK
1.778	0.201	tC2Q	RF	1	R11C11[0][B]	u_la0_top/u_ao_mem_ctrl/data_reg_Z[37]/Q
1.900	0.122	tNET	FF	1	BSRAM_R10[2]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_18/DI1

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	501	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	BSRAM_R10[2]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_18/CLKA
1.577	0.000	tUnc				u_la0_top/u_ao_mem_ctrl/mem_mem_0_18
1.826	0.249	tHld		1	BSRAM_R10[2]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_18

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.122, 37.751%; tC2Q: 0.201, 62.249%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path2

Path Summary:

Slack	0.076
Data Arrival Time	1.903
Data Required Time	1.826
From	u_la0_top/u_ao_mem_ctrl/data_reg_Z[36]
To	u_la0_top/u_ao_mem_ctrl/mem_mem_0_18
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	501	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R11C11[0][A]	u_la0_top/u_ao_mem_ctrl/data_reg_Z[36]/CLK
1.779	0.202	tC2Q	RR	1	R11C11[0][A]	u_la0_top/u_ao_mem_ctrl/data_reg_Z[36]/Q
1.903	0.123	tNET	RR	1	BSRAM_R10[2]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_18/DI0

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	501	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	BSRAM_R10[2]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_18/CLKA
1.577	0.000	tUnc				u_la0_top/u_ao_mem_ctrl/mem_mem_0_18
1.826	0.249	tHld		1	BSRAM_R10[2]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_18

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.123, 37.889%; tC2Q: 0.202, 62.111%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path3

Path Summary:

Slack	0.215
Data Arrival Time	1.910
Data Required Time	1.695
From	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8]
To	u_la0_top/u_ao_mem_ctrl/mem_mem_0_21
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	501	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R12C5[2][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8]/CLK
1.779	0.202	tC2Q	RR	51	R12C5[2][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8]/Q
1.910	0.131	tNET	RR	1	BSRAM_R10[0]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_21/ADA9

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	501	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	BSRAM_R10[0]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_21/CLKA
1.577	0.000	tUnc				u_la0_top/u_ao_mem_ctrl/mem_mem_0_21
1.695	0.118	tHld		1	BSRAM_R10[0]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_21

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.131, 39.258%; tC2Q: 0.202, 60.742%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path4

Path Summary:

Slack	0.215
Data Arrival Time	1.910
Data Required Time	1.695
From	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[11]
To	u_la0_top/u_ao_mem_ctrl/mem_mem_0_13
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	501	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R9C9[2][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[11]/CLK
1.779	0.202	tC2Q	RR	51	R9C9[2][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[11]/Q
1.910	0.131	tNET	RR	1	BSRAM_R10[1]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_13/ADA12

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	501	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	BSRAM_R10[1]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_13/CLKA
1.577	0.000	tUnc				u_la0_top/u_ao_mem_ctrl/mem_mem_0_13
1.695	0.118	tHld		1	BSRAM_R10[1]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_13

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.131, 39.258%; tC2Q: 0.202, 60.742%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path5

Path Summary:

Slack	0.230
Data Arrival Time	1.926
Data Required Time	1.695
From	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[12]
To	u_la0_top/u_ao_mem_ctrl/mem_mem_0_13
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	501	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R9C9[2][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[12]/CLK
1.778	0.201	tC2Q	RF	51	R9C9[2][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[12]/Q
1.926	0.147	tNET	FF	1	BSRAM_R10[1]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_13/ADA13

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	501	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	BSRAM_R10[1]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_13/CLKA
1.577	0.000	tUnc				u_la0_top/u_ao_mem_ctrl/mem_mem_0_13
1.695	0.118	tHld		1	BSRAM_R10[1]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_13

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.147, 42.272%; tC2Q: 0.201, 57.728%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path6

Path Summary:

Slack	0.232
Data Arrival Time	1.927
Data Required Time	1.695
From	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[6]
To	u_la0_top/u_ao_mem_ctrl/mem_mem_0_13
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	501	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R11C8[0][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[6]/CLK
1.779	0.202	tC2Q	RR	51	R11C8[0][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[6]/Q
1.927	0.148	tNET	RR	1	BSRAM_R10[1]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_13/ADA7

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	501	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	BSRAM_R10[1]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_13/CLKA
1.577	0.000	tUnc				u_la0_top/u_ao_mem_ctrl/mem_mem_0_13
1.695	0.118	tHld		1	BSRAM_R10[1]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_13

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.148, 42.286%; tC2Q: 0.202, 57.714%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path7

Path Summary:

Slack	0.324
Data Arrival Time	2.151
Data Required Time	1.826
From	u_la0_top/u_ao_mem_ctrl/data_reg_Z[90]
To	u_la0_top/u_ao_mem_ctrl/mem_mem_0_45
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	501	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R8C12[0][B]	u_la0_top/u_ao_mem_ctrl/data_reg_Z[90]/CLK
1.779	0.202	tC2Q	RR	1	R8C12[0][B]	u_la0_top/u_ao_mem_ctrl/data_reg_Z[90]/Q
2.151	0.371	tNET	RR	1	BSRAM_R10[3]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_45/DI0

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	501	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	BSRAM_R10[3]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_45/CLKA
1.577	0.000	tUnc				u_la0_top/u_ao_mem_ctrl/mem_mem_0_45
1.826	0.249	tHld		1	BSRAM_R10[3]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_45

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.371, 64.759%; tC2Q: 0.202, 35.241%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path8

Path Summary:

Slack	0.335
Data Arrival Time	2.031
Data Required Time	1.695
From	cnt_1_Z[9]
To	memr_memr_0_8
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	501	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R34C51[2][B]	cnt_1_Z[9]/CLK
1.779	0.202	tC2Q	RR	17	R34C51[2][B]	cnt_1_Z[9]/Q
2.031	0.251	tNET	RR	1	BSRAM_R36[16]	memr_memr_0_8/ADB10

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	501	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	BSRAM_R36[16]	memr_memr_0_8/CLKB
1.577	0.000	tUnc				memr_memr_0_8
1.695	0.118	tHld		1	BSRAM_R36[16]	memr_memr_0_8

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.251, 55.441%; tC2Q: 0.202, 44.559%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path9

Path Summary:

Slack	0.335
Data Arrival Time	2.162
Data Required Time	1.826
From	u_la0_top/u_ao_mem_ctrl/data_reg_Z[91]
To	u_la0_top/u_ao_mem_ctrl/mem_mem_0_45
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	501	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R9C10[2][A]	u_la0_top/u_ao_mem_ctrl/data_reg_Z[91]/CLK
1.779	0.202	tC2Q	RR	1	R9C10[2][A]	u_la0_top/u_ao_mem_ctrl/data_reg_Z[91]/Q
2.162	0.382	tNET	RR	1	BSRAM_R10[3]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_45/DI1

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	501	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	BSRAM_R10[3]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_45/CLKA
1.577	0.000	tUnc				u_la0_top/u_ao_mem_ctrl/mem_mem_0_45
1.826	0.249	tHld		1	BSRAM_R10[3]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_45

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.382, 65.434%; tC2Q: 0.202, 34.566%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path10

Path Summary:

Slack	0.341
Data Arrival Time	2.037
Data Required Time	1.695
From	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[4]
To	u_la0_top/u_ao_mem_ctrl/mem_mem_0_18
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	501	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R12C10[2][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[4]/CLK
1.779	0.202	tC2Q	RR	51	R12C10[2][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[4]/Q
2.037	0.257	tNET	RR	1	BSRAM_R10[2]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_18/ADA5

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	501	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	BSRAM_R10[2]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_18/CLKA
1.577	0.000	tUnc				u_la0_top/u_ao_mem_ctrl/mem_mem_0_18
1.695	0.118	tHld		1	BSRAM_R10[2]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_18

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.257, 56.034%; tC2Q: 0.202, 43.966%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path11

Path Summary:

Slack	0.341
Data Arrival Time	2.168
Data Required Time	1.826
From	Mdu/u_mdu/reg0[33]
To	memr_memr_0_0
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	501	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R33C31[2][B]	Mdu/u_mdu/reg0[33]/CLK
1.779	0.202	tC2Q	RR	16	R33C31[2][B]	Mdu/u_mdu/reg0[33]/Q
2.168	0.388	tNET	RR	1	BSRAM_R36[9]	memr_memr_0_0/DI0

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	501	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	BSRAM_R36[9]	memr_memr_0_0/CLKA
1.577	0.000	tUnc				memr_memr_0_0
1.826	0.249	tHld		1	BSRAM_R36[9]	memr_memr_0_0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.388, 65.788%; tC2Q: 0.202, 34.212%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path12

Path Summary:

Slack	0.345
Data Arrival Time	2.040
Data Required Time	1.695
From	cnt_1_Z[4]
To	memr_memr_0_6
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	501	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R34C51[0][A]	cnt_1_Z[4]/CLK
1.779	0.202	tC2Q	RR	17	R34C51[0][A]	cnt_1_Z[4]/Q
2.040	0.261	tNET	RR	1	BSRAM_R36[15]	memr_memr_0_6/ADB5

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	501	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	BSRAM_R36[15]	memr_memr_0_6/CLKB
1.577	0.000	tUnc				memr_memr_0_6
1.695	0.118	tHld		1	BSRAM_R36[15]	memr_memr_0_6

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.261, 56.337%; tC2Q: 0.202, 43.663%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path13

Path Summary:

Slack	0.345
Data Arrival Time	2.041
Data Required Time	1.695
From	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[7]
To	u_la0_top/u_ao_mem_ctrl/mem_mem_0_21
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	501	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R12C5[1][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[7]/CLK
1.779	0.202	tC2Q	RR	51	R12C5[1][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[7]/Q
2.041	0.261	tNET	RR	1	BSRAM_R10[0]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_21/ADA8

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	501	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	BSRAM_R10[0]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_21/CLKA
1.577	0.000	tUnc				u_la0_top/u_ao_mem_ctrl/mem_mem_0_21
1.695	0.118	tHld		1	BSRAM_R10[0]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_21

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.261, 56.400%; tC2Q: 0.202, 43.600%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path14

Path Summary:

Slack	0.349
Data Arrival Time	2.045
Data Required Time	1.695
From	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[5]
To	u_la0_top/u_ao_mem_ctrl/mem_mem_0_13
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	501	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R11C8[0][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[5]/CLK
1.779	0.202	tC2Q	RR	51	R11C8[0][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[5]/Q
2.045	0.265	tNET	RR	1	BSRAM_R10[1]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_13/ADA6

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	501	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	BSRAM_R10[1]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_13/CLKA
1.577	0.000	tUnc				u_la0_top/u_ao_mem_ctrl/mem_mem_0_13
1.695	0.118	tHld		1	BSRAM_R10[1]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_13

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.265, 56.771%; tC2Q: 0.202, 43.229%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path15

Path Summary:

Slack	0.352
Data Arrival Time	2.047
Data Required Time	1.695
From	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[1]
To	u_la0_top/u_ao_mem_ctrl/mem_mem_0_21
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	501	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R11C4[0][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[1]/CLK
1.779	0.202	tC2Q	RR	51	R11C4[0][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[1]/Q
2.047	0.268	tNET	RR	1	BSRAM_R10[0]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_21/ADA2

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	501	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	BSRAM_R10[0]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_21/CLKA
1.577	0.000	tUnc				u_la0_top/u_ao_mem_ctrl/mem_mem_0_21
1.695	0.118	tHld		1	BSRAM_R10[0]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_21

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.268, 56.991%; tC2Q: 0.202, 43.009%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path16

Path Summary:

Slack	0.353
Data Arrival Time	2.048
Data Required Time	1.695
From	cnt_1_Z[9]
To	memr_memr_0_6
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	501	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R34C51[2][B]	cnt_1_Z[9]/CLK
1.779	0.202	tC2Q	RR	17	R34C51[2][B]	cnt_1_Z[9]/Q
2.048	0.269	tNET	RR	1	BSRAM_R36[15]	memr_memr_0_6/ADB10

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	501	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	BSRAM_R36[15]	memr_memr_0_6/CLKB
1.577	0.000	tUnc				memr_memr_0_6
1.695	0.118	tHld		1	BSRAM_R36[15]	memr_memr_0_6

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.269, 57.097%; tC2Q: 0.202, 42.903%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path17

Path Summary:

Slack	0.353
Data Arrival Time	2.048
Data Required Time	1.695
From	cnt_1_Z[12]
To	memr_memr_0_6
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	501	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R34C52[1][A]	cnt_1_Z[12]/CLK
1.779	0.202	tC2Q	RR	17	R34C52[1][A]	cnt_1_Z[12]/Q
2.048	0.269	tNET	RR	1	BSRAM_R36[15]	memr_memr_0_6/ADB13

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	501	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	BSRAM_R36[15]	memr_memr_0_6/CLKB
1.577	0.000	tUnc				memr_memr_0_6
1.695	0.118	tHld		1	BSRAM_R36[15]	memr_memr_0_6

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.269, 57.102%; tC2Q: 0.202, 42.898%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path18

Path Summary:

Slack	0.354
Data Arrival Time	2.049
Data Required Time	1.695
From	cnt_1_Z[8]
To	memr_memr_0_6
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	501	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R34C51[2][A]	cnt_1_Z[8]/CLK
1.779	0.202	tC2Q	RR	17	R34C51[2][A]	cnt_1_Z[8]/Q
2.049	0.270	tNET	RR	1	BSRAM_R36[15]	memr_memr_0_6/ADB9

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	501	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	BSRAM_R36[15]	memr_memr_0_6/CLKB
1.577	0.000	tUnc				memr_memr_0_6
1.695	0.118	tHld		1	BSRAM_R36[15]	memr_memr_0_6

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.270, 57.208%; tC2Q: 0.202, 42.792%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path19

Path Summary:

Slack	0.357
Data Arrival Time	2.052
Data Required Time	1.695
From	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[4]
To	u_la0_top/u_ao_mem_ctrl/mem_mem_0_13
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	501	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R12C10[2][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[4]/CLK
1.779	0.202	tC2Q	RR	51	R12C10[2][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[4]/Q
2.052	0.273	tNET	RR	1	BSRAM_R10[1]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_13/ADA5

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	501	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	BSRAM_R10[1]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_13/CLKA
1.577	0.000	tUnc				u_la0_top/u_ao_mem_ctrl/mem_mem_0_13
1.695	0.118	tHld		1	BSRAM_R10[1]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_13

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.273, 57.439%; tC2Q: 0.202, 42.561%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path20

Path Summary:

Slack	0.363
Data Arrival Time	2.058
Data Required Time	1.695
From	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[3]
To	u_la0_top/u_ao_mem_ctrl/mem_mem_0_13
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	501	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R12C5[2][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[3]/CLK
1.779	0.202	tC2Q	RR	51	R12C5[2][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[3]/Q
2.058	0.279	tNET	RR	1	BSRAM_R10[1]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_13/ADA4

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	501	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	BSRAM_R10[1]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_13/CLKA
1.577	0.000	tUnc				u_la0_top/u_ao_mem_ctrl/mem_mem_0_13
1.695	0.118	tHld		1	BSRAM_R10[1]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_13

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.279, 57.968%; tC2Q: 0.202, 42.032%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path21

Path Summary:

Slack	0.363
Data Arrival Time	2.189
Data Required Time	1.826
From	u_la0_top/u_ao_mem_ctrl/data_reg_Z[48]
To	u_la0_top/u_ao_mem_ctrl/mem_mem_0_24
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	501	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R11C10[0][A]	u_la0_top/u_ao_mem_ctrl/data_reg_Z[48]/CLK
1.779	0.202	tC2Q	RR	1	R11C10[0][A]	u_la0_top/u_ao_mem_ctrl/data_reg_Z[48]/Q
2.189	0.410	tNET	RR	1	BSRAM_R10[4]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_24/DI0

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	501	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	BSRAM_R10[4]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_24/CLKA
1.577	0.000	tUnc				u_la0_top/u_ao_mem_ctrl/mem_mem_0_24
1.826	0.249	tHld		1	BSRAM_R10[4]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_24

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.410, 66.974%; tC2Q: 0.202, 33.026%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path22

Path Summary:

Slack	0.363
Data Arrival Time	2.189
Data Required Time	1.826
From	u_la0_top/u_ao_mem_ctrl/data_reg_Z[42]
To	u_la0_top/u_ao_mem_ctrl/mem_mem_0_21
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	501	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R11C12[0][A]	u_la0_top/u_ao_mem_ctrl/data_reg_Z[42]/CLK
1.779	0.202	tC2Q	RR	1	R11C12[0][A]	u_la0_top/u_ao_mem_ctrl/data_reg_Z[42]/Q
2.189	0.410	tNET	RR	1	BSRAM_R10[0]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_21/DI0

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	501	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	BSRAM_R10[0]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_21/CLKA
1.577	0.000	tUnc				u_la0_top/u_ao_mem_ctrl/mem_mem_0_21
1.826	0.249	tHld		1	BSRAM_R10[0]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_21

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.410, 66.974%; tC2Q: 0.202, 33.026%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path23

Path Summary:

Slack	0.364
Data Arrival Time	2.059
Data Required Time	1.695
From	cnt_1_Z[3]
To	memr_memr_0_8
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	501	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R34C50[2][B]	cnt_1_Z[3]/CLK
1.779	0.202	tC2Q	RR	17	R34C50[2][B]	cnt_1_Z[3]/Q
2.059	0.280	tNET	RR	1	BSRAM_R36[16]	memr_memr_0_8/ADB4

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	501	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	BSRAM_R36[16]	memr_memr_0_8/CLKB
1.577	0.000	tUnc				memr_memr_0_8
1.695	0.118	tHld		1	BSRAM_R36[16]	memr_memr_0_8

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.280, 58.075%; tC2Q: 0.202, 41.925%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path24

Path Summary:

Slack	0.364
Data Arrival Time	2.059
Data Required Time	1.695
From	cnt_1_Z[8]
To	memr_memr_0_5
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	501	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R34C51[2][A]	cnt_1_Z[8]/CLK
1.779	0.202	tC2Q	RR	17	R34C51[2][A]	cnt_1_Z[8]/Q
2.059	0.280	tNET	RR	1	BSRAM_R36[14]	memr_memr_0_5/ADB9

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	501	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	BSRAM_R36[14]	memr_memr_0_5/CLKB
1.577	0.000	tUnc				memr_memr_0_5
1.695	0.118	tHld		1	BSRAM_R36[14]	memr_memr_0_5

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.280, 58.075%; tC2Q: 0.202, 41.925%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path25

Path Summary:

Slack	0.366
Data Arrival Time	2.061
Data Required Time	1.695
From	cnt_1_Z[8]
To	memr_memr_0_12
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	501	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R34C51[2][A]	cnt_1_Z[8]/CLK
1.779	0.202	tC2Q	RR	17	R34C51[2][A]	cnt_1_Z[8]/Q
2.061	0.282	tNET	RR	1	BSRAM_R36[18]	memr_memr_0_12/ADB9

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	501	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	BSRAM_R36[18]	memr_memr_0_12/CLKB
1.577	0.000	tUnc				memr_memr_0_12
1.695	0.118	tHld		1	BSRAM_R36[18]	memr_memr_0_12

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.282, 58.270%; tC2Q: 0.202, 41.730%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Recovery Analysis Report

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	1.914
Data Arrival Time	9.734
Data Required Time	11.648
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.688	0.688	tINS	FF	501	IOT48[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R7C12[1][B]	u_la0_top/rst_ao_Z/CLK
7.148	0.232	tC2Q	FF	49	R7C12[1][B]	u_la0_top/rst_ao_Z/Q
9.734	2.586	tNET	FF	1	R12C6[2][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	501	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R12C6[2][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z/CLK
11.683	-0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z
11.648	-0.035	tSu		1	R12C6[2][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z

Path Statistics:

Clock Skew	-0.033
Setup Relationship	5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.586, 91.769%; tC2Q: 0.232, 8.231%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path2

Path Summary:

Slack	1.914
Data Arrival Time	9.734
Data Required Time	11.648
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_Z
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.688	0.688	tINS	FF	501	IOT48[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R7C12[1][B]	u_la0_top/rst_ao_Z/CLK
7.148	0.232	tC2Q	FF	49	R7C12[1][B]	u_la0_top/rst_ao_Z/Q
9.734	2.586	tNET	FF	1	R2C5[1][A]	u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_Z/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	501	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R2C5[1][A]	u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_Z/CLK
11.683	-0.200	tUnc				u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_Z
11.648	-0.035	tSu		1	R2C5[1][A]	u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_Z

Path Statistics:

Clock Skew	-0.033
Setup Relationship	5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.586, 91.769%; tC2Q: 0.232, 8.231%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path3

Path Summary:

Slack	1.914
Data Arrival Time	9.734
Data Required Time	11.648
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_loop_Z
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.688	0.688	tINS	FF	501	IOT48[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R7C12[1][B]	u_la0_top/rst_ao_Z/CLK
7.148	0.232	tC2Q	FF	49	R7C12[1][B]	u_la0_top/rst_ao_Z/Q
9.734	2.586	tNET	FF	1	R12C6[1][A]	u_la0_top/u_ao_mem_ctrl/capture_loop_Z/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	501	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R12C6[1][A]	u_la0_top/u_ao_mem_ctrl/capture_loop_Z/CLK
11.683	-0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_loop_Z
11.648	-0.035	tSu		1	R12C6[1][A]	u_la0_top/u_ao_mem_ctrl/capture_loop_Z

Path Statistics:

Clock Skew	-0.033
Setup Relationship	5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.586, 91.769%; tC2Q: 0.232, 8.231%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path4

Path Summary:

Slack	1.914
Data Arrival Time	9.734
Data Required Time	11.648
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_length_Z[0]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.688	0.688	tINS	FF	501	IOT48[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R7C12[1][B]	u_la0_top/rst_ao_Z/CLK
7.148	0.232	tC2Q	FF	49	R7C12[1][B]	u_la0_top/rst_ao_Z/Q
9.734	2.586	tNET	FF	1	R7C12[2][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[0]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	501	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R7C12[2][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[0]/CLK
11.683	-0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_length_Z[0]
11.648	-0.035	tSu		1	R7C12[2][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[0]

Path Statistics:

Clock Skew	-0.033
Setup Relationship	5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.586, 91.769%; tC2Q: 0.232, 8.231%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path5

Path Summary:

Slack	1.914
Data Arrival Time	9.734
Data Required Time	11.648
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_length_Z[1]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.688	0.688	tINS	FF	501	IOT48[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R7C12[1][B]	u_la0_top/rst_ao_Z/CLK
7.148	0.232	tC2Q	FF	49	R7C12[1][B]	u_la0_top/rst_ao_Z/Q
9.734	2.586	tNET	FF	1	R11C8[2][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[1]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	501	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R11C8[2][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[1]/CLK
11.683	-0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_length_Z[1]
11.648	-0.035	tSu		1	R11C8[2][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[1]

Path Statistics:

Clock Skew	-0.033
Setup Relationship	5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.586, 91.769%; tC2Q: 0.232, 8.231%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path6

Path Summary:

Slack	1.914
Data Arrival Time	9.734
Data Required Time	11.648
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_length_Z[2]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.688	0.688	tINS	FF	501	IOT48[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R7C12[1][B]	u_la0_top/rst_ao_Z/CLK
7.148	0.232	tC2Q	FF	49	R7C12[1][B]	u_la0_top/rst_ao_Z/Q
9.734	2.586	tNET	FF	1	R6C12[2][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[2]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	501	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R6C12[2][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[2]/CLK
11.683	-0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_length_Z[2]
11.648	-0.035	tSu		1	R6C12[2][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[2]

Path Statistics:

Clock Skew	-0.033
Setup Relationship	5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.586, 91.769%; tC2Q: 0.232, 8.231%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path7

Path Summary:

Slack	1.914
Data Arrival Time	9.734
Data Required Time	11.648
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_length_Z[3]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.688	0.688	tINS	FF	501	IOT48[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R7C12[1][B]	u_la0_top/rst_ao_Z/CLK
7.148	0.232	tC2Q	FF	49	R7C12[1][B]	u_la0_top/rst_ao_Z/Q
9.734	2.586	tNET	FF	1	R8C11[2][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[3]/PRESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	501	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R8C11[2][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[3]/CLK
11.683	-0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_length_Z[3]
11.648	-0.035	tSu		1	R8C11[2][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[3]

Path Statistics:

Clock Skew	-0.033
Setup Relationship	5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.586, 91.769%; tC2Q: 0.232, 8.231%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path8

Path Summary:

Slack	1.914
Data Arrival Time	9.734
Data Required Time	11.648
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_length_Z[4]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.688	0.688	tINS	FF	501	IOT48[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R7C12[1][B]	u_la0_top/rst_ao_Z/CLK
7.148	0.232	tC2Q	FF	49	R7C12[1][B]	u_la0_top/rst_ao_Z/Q
9.734	2.586	tNET	FF	1	R8C2[2][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[4]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	501	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R8C2[2][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[4]/CLK
11.683	-0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_length_Z[4]
11.648	-0.035	tSu		1	R8C2[2][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[4]

Path Statistics:

Clock Skew	-0.033
Setup Relationship	5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.586, 91.769%; tC2Q: 0.232, 8.231%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path9

Path Summary:

Slack	1.914
Data Arrival Time	9.734
Data Required Time	11.648
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_length_Z[5]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.688	0.688	tINS	FF	501	IOT48[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R7C12[1][B]	u_la0_top/rst_ao_Z/CLK
7.148	0.232	tC2Q	FF	49	R7C12[1][B]	u_la0_top/rst_ao_Z/Q
9.734	2.586	tNET	FF	1	R8C2[2][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[5]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	501	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R8C2[2][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[5]/CLK
11.683	-0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_length_Z[5]
11.648	-0.035	tSu		1	R8C2[2][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[5]

Path Statistics:

Clock Skew	-0.033
Setup Relationship	5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.586, 91.769%; tC2Q: 0.232, 8.231%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path10

Path Summary:

Slack	1.914
Data Arrival Time	9.734
Data Required Time	11.648
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_length_Z[6]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.688	0.688	tINS	FF	501	IOT48[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R7C12[1][B]	u_la0_top/rst_ao_Z/CLK
7.148	0.232	tC2Q	FF	49	R7C12[1][B]	u_la0_top/rst_ao_Z/Q
9.734	2.586	tNET	FF	1	R3C2[2][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[6]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	501	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R3C2[2][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[6]/CLK
11.683	-0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_length_Z[6]
11.648	-0.035	tSu		1	R3C2[2][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[6]

Path Statistics:

Clock Skew	-0.033
Setup Relationship	5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.586, 91.769%; tC2Q: 0.232, 8.231%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path11

Path Summary:

Slack	1.914
Data Arrival Time	9.734
Data Required Time	11.648
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_length_Z[7]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.688	0.688	tINS	FF	501	IOT48[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R7C12[1][B]	u_la0_top/rst_ao_Z/CLK
7.148	0.232	tC2Q	FF	49	R7C12[1][B]	u_la0_top/rst_ao_Z/Q
9.734	2.586	tNET	FF	1	R11C8[2][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[7]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	501	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R11C8[2][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[7]/CLK
11.683	-0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_length_Z[7]
11.648	-0.035	tSu		1	R11C8[2][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[7]

Path Statistics:

Clock Skew	-0.033
Setup Relationship	5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.586, 91.769%; tC2Q: 0.232, 8.231%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path12

Path Summary:

Slack	1.914
Data Arrival Time	9.734
Data Required Time	11.648
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_length_Z[8]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.688	0.688	tINS	FF	501	IOT48[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R7C12[1][B]	u_la0_top/rst_ao_Z/CLK
7.148	0.232	tC2Q	FF	49	R7C12[1][B]	u_la0_top/rst_ao_Z/Q
9.734	2.586	tNET	FF	1	R11C8[1][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[8]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	501	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R11C8[1][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[8]/CLK
11.683	-0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_length_Z[8]
11.648	-0.035	tSu		1	R11C8[1][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[8]

Path Statistics:

Clock Skew	-0.033
Setup Relationship	5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.586, 91.769%; tC2Q: 0.232, 8.231%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path13

Path Summary:

Slack	1.914
Data Arrival Time	9.734
Data Required Time	11.648
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_length_Z[9]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.688	0.688	tINS	FF	501	IOT48[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R7C12[1][B]	u_la0_top/rst_ao_Z/CLK
7.148	0.232	tC2Q	FF	49	R7C12[1][B]	u_la0_top/rst_ao_Z/Q
9.734	2.586	tNET	FF	1	R11C8[1][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[9]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	501	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R11C8[1][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[9]/CLK
11.683	-0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_length_Z[9]
11.648	-0.035	tSu		1	R11C8[1][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[9]

Path Statistics:

Clock Skew	-0.033
Setup Relationship	5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.586, 91.769%; tC2Q: 0.232, 8.231%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path14

Path Summary:

Slack	1.914
Data Arrival Time	9.734
Data Required Time	11.648
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_length_Z[10]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.688	0.688	tINS	FF	501	IOT48[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R7C12[1][B]	u_la0_top/rst_ao_Z/CLK
7.148	0.232	tC2Q	FF	49	R7C12[1][B]	u_la0_top/rst_ao_Z/Q
9.734	2.586	tNET	FF	1	R3C3[2][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[10]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	501	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R3C3[2][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[10]/CLK
11.683	-0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_length_Z[10]
11.648	-0.035	tSu		1	R3C3[2][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[10]

Path Statistics:

Clock Skew	-0.033
Setup Relationship	5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.586, 91.769%; tC2Q: 0.232, 8.231%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path15

Path Summary:

Slack	1.914
Data Arrival Time	9.734
Data Required Time	11.648
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_length_Z[11]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.688	0.688	tINS	FF	501	IOT48[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R7C12[1][B]	u_la0_top/rst_ao_Z/CLK
7.148	0.232	tC2Q	FF	49	R7C12[1][B]	u_la0_top/rst_ao_Z/Q
9.734	2.586	tNET	FF	1	R3C3[2][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[11]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	501	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R3C3[2][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[11]/CLK
11.683	-0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_length_Z[11]
11.648	-0.035	tSu		1	R3C3[2][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[11]

Path Statistics:

Clock Skew	-0.033
Setup Relationship	5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.586, 91.769%; tC2Q: 0.232, 8.231%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path16

Path Summary:

Slack	1.914
Data Arrival Time	9.734
Data Required Time	11.648
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_length_Z[12]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.688	0.688	tINS	FF	501	IOT48[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R7C12[1][B]	u_la0_top/rst_ao_Z/CLK
7.148	0.232	tC2Q	FF	49	R7C12[1][B]	u_la0_top/rst_ao_Z/Q
9.734	2.586	tNET	FF	1	R2C5[0][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[12]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	501	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R2C5[0][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[12]/CLK
11.683	-0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_length_Z[12]
11.648	-0.035	tSu		1	R2C5[0][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[12]

Path Statistics:

Clock Skew	-0.033
Setup Relationship	5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.586, 91.769%; tC2Q: 0.232, 8.231%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path17

Path Summary:

Slack	1.914
Data Arrival Time	9.734
Data Required Time	11.648
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.688	0.688	tINS	FF	501	IOT48[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R7C12[1][B]	u_la0_top/rst_ao_Z/CLK
7.148	0.232	tC2Q	FF	49	R7C12[1][B]	u_la0_top/rst_ao_Z/Q
9.734	2.586	tNET	FF	1	R11C4[0][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	501	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R11C4[0][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0]/CLK
11.683	-0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0]
11.648	-0.035	tSu		1	R11C4[0][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0]

Path Statistics:

Clock Skew	-0.033
Setup Relationship	5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.586, 91.769%; tC2Q: 0.232, 8.231%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path18

Path Summary:

Slack	1.914
Data Arrival Time	9.734
Data Required Time	11.648
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[1]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.688	0.688	tINS	FF	501	IOT48[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R7C12[1][B]	u_la0_top/rst_ao_Z/CLK
7.148	0.232	tC2Q	FF	49	R7C12[1][B]	u_la0_top/rst_ao_Z/Q
9.734	2.586	tNET	FF	1	R11C4[0][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[1]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	501	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R11C4[0][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[1]/CLK
11.683	-0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[1]
11.648	-0.035	tSu		1	R11C4[0][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[1]

Path Statistics:

Clock Skew	-0.033
Setup Relationship	5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.586, 91.769%; tC2Q: 0.232, 8.231%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path19

Path Summary:

Slack	1.914
Data Arrival Time	9.734
Data Required Time	11.648
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[2]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.688	0.688	tINS	FF	501	IOT48[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R7C12[1][B]	u_la0_top/rst_ao_Z/CLK
7.148	0.232	tC2Q	FF	49	R7C12[1][B]	u_la0_top/rst_ao_Z/Q
9.734	2.586	tNET	FF	1	R11C4[1][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[2]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	501	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R11C4[1][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[2]/CLK
11.683	-0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[2]
11.648	-0.035	tSu		1	R11C4[1][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[2]

Path Statistics:

Clock Skew	-0.033
Setup Relationship	5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.586, 91.769%; tC2Q: 0.232, 8.231%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path20

Path Summary:

Slack	1.914
Data Arrival Time	9.734
Data Required Time	11.648
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[3]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.688	0.688	tINS	FF	501	IOT48[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R7C12[1][B]	u_la0_top/rst_ao_Z/CLK
7.148	0.232	tC2Q	FF	49	R7C12[1][B]	u_la0_top/rst_ao_Z/Q
9.734	2.586	tNET	FF	1	R12C5[2][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[3]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	501	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R12C5[2][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[3]/CLK
11.683	-0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[3]
11.648	-0.035	tSu		1	R12C5[2][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[3]

Path Statistics:

Clock Skew	-0.033
Setup Relationship	5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.586, 91.769%; tC2Q: 0.232, 8.231%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path21

Path Summary:

Slack	1.914
Data Arrival Time	9.734
Data Required Time	11.648
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[4]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.688	0.688	tINS	FF	501	IOT48[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R7C12[1][B]	u_la0_top/rst_ao_Z/CLK
7.148	0.232	tC2Q	FF	49	R7C12[1][B]	u_la0_top/rst_ao_Z/Q
9.734	2.586	tNET	FF	1	R12C10[2][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[4]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	501	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R12C10[2][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[4]/CLK
11.683	-0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[4]
11.648	-0.035	tSu		1	R12C10[2][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[4]

Path Statistics:

Clock Skew	-0.033
Setup Relationship	5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.586, 91.769%; tC2Q: 0.232, 8.231%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path22

Path Summary:

Slack	1.914
Data Arrival Time	9.734
Data Required Time	11.648
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[5]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.688	0.688	tINS	FF	501	IOT48[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R7C12[1][B]	u_la0_top/rst_ao_Z/CLK
7.148	0.232	tC2Q	FF	49	R7C12[1][B]	u_la0_top/rst_ao_Z/Q
9.734	2.586	tNET	FF	1	R11C8[0][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[5]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	501	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R11C8[0][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[5]/CLK
11.683	-0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[5]
11.648	-0.035	tSu		1	R11C8[0][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[5]

Path Statistics:

Clock Skew	-0.033
Setup Relationship	5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.586, 91.769%; tC2Q: 0.232, 8.231%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path23

Path Summary:

Slack	1.914
Data Arrival Time	9.734
Data Required Time	11.648
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[6]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.688	0.688	tINS	FF	501	IOT48[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R7C12[1][B]	u_la0_top/rst_ao_Z/CLK
7.148	0.232	tC2Q	FF	49	R7C12[1][B]	u_la0_top/rst_ao_Z/Q
9.734	2.586	tNET	FF	1	R11C8[0][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[6]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	501	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R11C8[0][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[6]/CLK
11.683	-0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[6]
11.648	-0.035	tSu		1	R11C8[0][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[6]

Path Statistics:

Clock Skew	-0.033
Setup Relationship	5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.586, 91.769%; tC2Q: 0.232, 8.231%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path24

Path Summary:

Slack	1.914
Data Arrival Time	9.734
Data Required Time	11.648
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[7]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.688	0.688	tINS	FF	501	IOT48[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R7C12[1][B]	u_la0_top/rst_ao_Z/CLK
7.148	0.232	tC2Q	FF	49	R7C12[1][B]	u_la0_top/rst_ao_Z/Q
9.734	2.586	tNET	FF	1	R12C5[1][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[7]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	501	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R12C5[1][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[7]/CLK
11.683	-0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[7]
11.648	-0.035	tSu		1	R12C5[1][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[7]

Path Statistics:

Clock Skew	-0.033
Setup Relationship	5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.586, 91.769%; tC2Q: 0.232, 8.231%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path25

Path Summary:

Slack	1.914
Data Arrival Time	9.734
Data Required Time	11.648
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.688	0.688	tINS	FF	501	IOT48[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R7C12[1][B]	u_la0_top/rst_ao_Z/CLK
7.148	0.232	tC2Q	FF	49	R7C12[1][B]	u_la0_top/rst_ao_Z/Q
9.734	2.586	tNET	FF	1	R12C5[2][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	501	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R12C5[2][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8]/CLK
11.683	-0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8]
11.648	-0.035	tSu		1	R12C5[2][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8]

Path Statistics:

Clock Skew	-0.033
Setup Relationship	5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.586, 91.769%; tC2Q: 0.232, 8.231%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Removal Analysis Report

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	6.623
Data Arrival Time	8.411
Data Required Time	1.788
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.677	0.678	tINS	FF	501	IOT48[A]	clk_ibuf/O
6.590	0.913	tNET	FF	1	R7C12[1][B]	u_la0_top/rst_ao_Z/CLK
6.792	0.202	tC2Q	FR	49	R7C12[1][B]	u_la0_top/rst_ao_Z/Q
8.411	1.619	tNET	RR	1	R12C6[2][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	501	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R12C6[2][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z/CLK
1.777	0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z
1.788	0.011	tHld		1	R12C6[2][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.619, 88.906%; tC2Q: 0.202, 11.094%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path2

Path Summary:

Slack	6.623
Data Arrival Time	8.411
Data Required Time	1.788
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_loop_Z
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.677	0.678	tINS	FF	501	IOT48[A]	clk_ibuf/O
6.590	0.913	tNET	FF	1	R7C12[1][B]	u_la0_top/rst_ao_Z/CLK
6.792	0.202	tC2Q	FR	49	R7C12[1][B]	u_la0_top/rst_ao_Z/Q
8.411	1.619	tNET	RR	1	R12C6[1][A]	u_la0_top/u_ao_mem_ctrl/capture_loop_Z/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	501	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R12C6[1][A]	u_la0_top/u_ao_mem_ctrl/capture_loop_Z/CLK
1.777	0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_loop_Z
1.788	0.011	tHld		1	R12C6[1][A]	u_la0_top/u_ao_mem_ctrl/capture_loop_Z

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.619, 88.906%; tC2Q: 0.202, 11.094%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path3

Path Summary:

Slack	6.623
Data Arrival Time	8.411
Data Required Time	1.788
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_length_Z[0]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.677	0.678	tINS	FF	501	IOT48[A]	clk_ibuf/O
6.590	0.913	tNET	FF	1	R7C12[1][B]	u_la0_top/rst_ao_Z/CLK
6.792	0.202	tC2Q	FR	49	R7C12[1][B]	u_la0_top/rst_ao_Z/Q
8.411	1.619	tNET	RR	1	R7C12[2][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[0]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	501	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R7C12[2][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[0]/CLK
1.777	0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_length_Z[0]
1.788	0.011	tHld		1	R7C12[2][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[0]

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.619, 88.906%; tC2Q: 0.202, 11.094%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path4

Path Summary:

Slack	6.623
Data Arrival Time	8.411
Data Required Time	1.788
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_length_Z[1]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.677	0.678	tINS	FF	501	IOT48[A]	clk_ibuf/O
6.590	0.913	tNET	FF	1	R7C12[1][B]	u_la0_top/rst_ao_Z/CLK
6.792	0.202	tC2Q	FR	49	R7C12[1][B]	u_la0_top/rst_ao_Z/Q
8.411	1.619	tNET	RR	1	R11C8[2][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[1]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	501	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R11C8[2][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[1]/CLK
1.777	0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_length_Z[1]
1.788	0.011	tHld		1	R11C8[2][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[1]

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.619, 88.906%; tC2Q: 0.202, 11.094%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path5

Path Summary:

Slack	6.623
Data Arrival Time	8.411
Data Required Time	1.788
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_length_Z[2]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.677	0.678	tINS	FF	501	IOT48[A]	clk_ibuf/O
6.590	0.913	tNET	FF	1	R7C12[1][B]	u_la0_top/rst_ao_Z/CLK
6.792	0.202	tC2Q	FR	49	R7C12[1][B]	u_la0_top/rst_ao_Z/Q
8.411	1.619	tNET	RR	1	R6C12[2][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[2]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	501	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R6C12[2][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[2]/CLK
1.777	0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_length_Z[2]
1.788	0.011	tHld		1	R6C12[2][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[2]

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.619, 88.906%; tC2Q: 0.202, 11.094%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path6

Path Summary:

Slack	6.623
Data Arrival Time	8.411
Data Required Time	1.788
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_length_Z[4]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.677	0.678	tINS	FF	501	IOT48[A]	clk_ibuf/O
6.590	0.913	tNET	FF	1	R7C12[1][B]	u_la0_top/rst_ao_Z/CLK
6.792	0.202	tC2Q	FR	49	R7C12[1][B]	u_la0_top/rst_ao_Z/Q
8.411	1.619	tNET	RR	1	R8C2[2][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[4]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	501	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R8C2[2][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[4]/CLK
1.777	0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_length_Z[4]
1.788	0.011	tHld		1	R8C2[2][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[4]

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.619, 88.906%; tC2Q: 0.202, 11.094%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path7

Path Summary:

Slack	6.623
Data Arrival Time	8.411
Data Required Time	1.788
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_length_Z[5]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.677	0.678	tINS	FF	501	IOT48[A]	clk_ibuf/O
6.590	0.913	tNET	FF	1	R7C12[1][B]	u_la0_top/rst_ao_Z/CLK
6.792	0.202	tC2Q	FR	49	R7C12[1][B]	u_la0_top/rst_ao_Z/Q
8.411	1.619	tNET	RR	1	R8C2[2][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[5]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	501	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R8C2[2][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[5]/CLK
1.777	0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_length_Z[5]
1.788	0.011	tHld		1	R8C2[2][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[5]

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.619, 88.906%; tC2Q: 0.202, 11.094%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path8

Path Summary:

Slack	6.623
Data Arrival Time	8.411
Data Required Time	1.788
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_length_Z[7]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.677	0.678	tINS	FF	501	IOT48[A]	clk_ibuf/O
6.590	0.913	tNET	FF	1	R7C12[1][B]	u_la0_top/rst_ao_Z/CLK
6.792	0.202	tC2Q	FR	49	R7C12[1][B]	u_la0_top/rst_ao_Z/Q
8.411	1.619	tNET	RR	1	R11C8[2][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[7]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	501	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R11C8[2][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[7]/CLK
1.777	0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_length_Z[7]
1.788	0.011	tHld		1	R11C8[2][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[7]

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.619, 88.906%; tC2Q: 0.202, 11.094%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path9

Path Summary:

Slack	6.623
Data Arrival Time	8.411
Data Required Time	1.788
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_length_Z[8]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.677	0.678	tINS	FF	501	IOT48[A]	clk_ibuf/O
6.590	0.913	tNET	FF	1	R7C12[1][B]	u_la0_top/rst_ao_Z/CLK
6.792	0.202	tC2Q	FR	49	R7C12[1][B]	u_la0_top/rst_ao_Z/Q
8.411	1.619	tNET	RR	1	R11C8[1][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[8]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	501	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R11C8[1][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[8]/CLK
1.777	0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_length_Z[8]
1.788	0.011	tHld		1	R11C8[1][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[8]

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.619, 88.906%; tC2Q: 0.202, 11.094%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path10

Path Summary:

Slack	6.623
Data Arrival Time	8.411
Data Required Time	1.788
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_length_Z[9]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.677	0.678	tINS	FF	501	IOT48[A]	clk_ibuf/O
6.590	0.913	tNET	FF	1	R7C12[1][B]	u_la0_top/rst_ao_Z/CLK
6.792	0.202	tC2Q	FR	49	R7C12[1][B]	u_la0_top/rst_ao_Z/Q
8.411	1.619	tNET	RR	1	R11C8[1][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[9]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	501	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R11C8[1][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[9]/CLK
1.777	0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_length_Z[9]
1.788	0.011	tHld		1	R11C8[1][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[9]

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.619, 88.906%; tC2Q: 0.202, 11.094%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path11

Path Summary:

Slack	6.623
Data Arrival Time	8.411
Data Required Time	1.788
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_length_Z[10]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.677	0.678	tINS	FF	501	IOT48[A]	clk_ibuf/O
6.590	0.913	tNET	FF	1	R7C12[1][B]	u_la0_top/rst_ao_Z/CLK
6.792	0.202	tC2Q	FR	49	R7C12[1][B]	u_la0_top/rst_ao_Z/Q
8.411	1.619	tNET	RR	1	R3C3[2][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[10]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	501	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R3C3[2][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[10]/CLK
1.777	0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_length_Z[10]
1.788	0.011	tHld		1	R3C3[2][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[10]

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.619, 88.906%; tC2Q: 0.202, 11.094%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path12

Path Summary:

Slack	6.623
Data Arrival Time	8.411
Data Required Time	1.788
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_length_Z[11]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.677	0.678	tINS	FF	501	IOT48[A]	clk_ibuf/O
6.590	0.913	tNET	FF	1	R7C12[1][B]	u_la0_top/rst_ao_Z/CLK
6.792	0.202	tC2Q	FR	49	R7C12[1][B]	u_la0_top/rst_ao_Z/Q
8.411	1.619	tNET	RR	1	R3C3[2][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[11]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	501	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R3C3[2][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[11]/CLK
1.777	0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_length_Z[11]
1.788	0.011	tHld		1	R3C3[2][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[11]

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.619, 88.906%; tC2Q: 0.202, 11.094%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path13

Path Summary:

Slack	6.623
Data Arrival Time	8.411
Data Required Time	1.788
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_length_Z[12]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.677	0.678	tINS	FF	501	IOT48[A]	clk_ibuf/O
6.590	0.913	tNET	FF	1	R7C12[1][B]	u_la0_top/rst_ao_Z/CLK
6.792	0.202	tC2Q	FR	49	R7C12[1][B]	u_la0_top/rst_ao_Z/Q
8.411	1.619	tNET	RR	1	R2C5[0][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[12]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	501	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R2C5[0][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[12]/CLK
1.777	0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_length_Z[12]
1.788	0.011	tHld		1	R2C5[0][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[12]

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.619, 88.906%; tC2Q: 0.202, 11.094%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path14

Path Summary:

Slack	6.623
Data Arrival Time	8.411
Data Required Time	1.788
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.677	0.678	tINS	FF	501	IOT48[A]	clk_ibuf/O
6.590	0.913	tNET	FF	1	R7C12[1][B]	u_la0_top/rst_ao_Z/CLK
6.792	0.202	tC2Q	FR	49	R7C12[1][B]	u_la0_top/rst_ao_Z/Q
8.411	1.619	tNET	RR	1	R11C4[0][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	501	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R11C4[0][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0]/CLK
1.777	0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0]
1.788	0.011	tHld		1	R11C4[0][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0]

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.619, 88.906%; tC2Q: 0.202, 11.094%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path15

Path Summary:

Slack	6.623
Data Arrival Time	8.411
Data Required Time	1.788
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[1]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.677	0.678	tINS	FF	501	IOT48[A]	clk_ibuf/O
6.590	0.913	tNET	FF	1	R7C12[1][B]	u_la0_top/rst_ao_Z/CLK
6.792	0.202	tC2Q	FR	49	R7C12[1][B]	u_la0_top/rst_ao_Z/Q
8.411	1.619	tNET	RR	1	R11C4[0][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[1]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	501	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R11C4[0][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[1]/CLK
1.777	0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[1]
1.788	0.011	tHld		1	R11C4[0][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[1]

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.619, 88.906%; tC2Q: 0.202, 11.094%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path16

Path Summary:

Slack	6.623
Data Arrival Time	8.411
Data Required Time	1.788
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[2]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.677	0.678	tINS	FF	501	IOT48[A]	clk_ibuf/O
6.590	0.913	tNET	FF	1	R7C12[1][B]	u_la0_top/rst_ao_Z/CLK
6.792	0.202	tC2Q	FR	49	R7C12[1][B]	u_la0_top/rst_ao_Z/Q
8.411	1.619	tNET	RR	1	R11C4[1][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[2]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	501	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R11C4[1][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[2]/CLK
1.777	0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[2]
1.788	0.011	tHld		1	R11C4[1][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[2]

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.619, 88.906%; tC2Q: 0.202, 11.094%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path17

Path Summary:

Slack	6.623
Data Arrival Time	8.411
Data Required Time	1.788
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[3]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.677	0.678	tINS	FF	501	IOT48[A]	clk_ibuf/O
6.590	0.913	tNET	FF	1	R7C12[1][B]	u_la0_top/rst_ao_Z/CLK
6.792	0.202	tC2Q	FR	49	R7C12[1][B]	u_la0_top/rst_ao_Z/Q
8.411	1.619	tNET	RR	1	R12C5[2][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[3]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	501	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R12C5[2][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[3]/CLK
1.777	0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[3]
1.788	0.011	tHld		1	R12C5[2][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[3]

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.619, 88.906%; tC2Q: 0.202, 11.094%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path18

Path Summary:

Slack	6.623
Data Arrival Time	8.411
Data Required Time	1.788
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[4]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.677	0.678	tINS	FF	501	IOT48[A]	clk_ibuf/O
6.590	0.913	tNET	FF	1	R7C12[1][B]	u_la0_top/rst_ao_Z/CLK
6.792	0.202	tC2Q	FR	49	R7C12[1][B]	u_la0_top/rst_ao_Z/Q
8.411	1.619	tNET	RR	1	R12C10[2][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[4]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	501	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R12C10[2][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[4]/CLK
1.777	0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[4]
1.788	0.011	tHld		1	R12C10[2][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[4]

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.619, 88.906%; tC2Q: 0.202, 11.094%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path19

Path Summary:

Slack	6.623
Data Arrival Time	8.411
Data Required Time	1.788
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[5]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.677	0.678	tINS	FF	501	IOT48[A]	clk_ibuf/O
6.590	0.913	tNET	FF	1	R7C12[1][B]	u_la0_top/rst_ao_Z/CLK
6.792	0.202	tC2Q	FR	49	R7C12[1][B]	u_la0_top/rst_ao_Z/Q
8.411	1.619	tNET	RR	1	R11C8[0][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[5]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	501	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R11C8[0][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[5]/CLK
1.777	0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[5]
1.788	0.011	tHld		1	R11C8[0][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[5]

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.619, 88.906%; tC2Q: 0.202, 11.094%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path20

Path Summary:

Slack	6.623
Data Arrival Time	8.411
Data Required Time	1.788
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[6]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.677	0.678	tINS	FF	501	IOT48[A]	clk_ibuf/O
6.590	0.913	tNET	FF	1	R7C12[1][B]	u_la0_top/rst_ao_Z/CLK
6.792	0.202	tC2Q	FR	49	R7C12[1][B]	u_la0_top/rst_ao_Z/Q
8.411	1.619	tNET	RR	1	R11C8[0][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[6]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	501	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R11C8[0][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[6]/CLK
1.777	0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[6]
1.788	0.011	tHld		1	R11C8[0][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[6]

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.619, 88.906%; tC2Q: 0.202, 11.094%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path21

Path Summary:

Slack	6.623
Data Arrival Time	8.411
Data Required Time	1.788
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[7]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.677	0.678	tINS	FF	501	IOT48[A]	clk_ibuf/O
6.590	0.913	tNET	FF	1	R7C12[1][B]	u_la0_top/rst_ao_Z/CLK
6.792	0.202	tC2Q	FR	49	R7C12[1][B]	u_la0_top/rst_ao_Z/Q
8.411	1.619	tNET	RR	1	R12C5[1][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[7]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	501	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R12C5[1][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[7]/CLK
1.777	0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[7]
1.788	0.011	tHld		1	R12C5[1][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[7]

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.619, 88.906%; tC2Q: 0.202, 11.094%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path22

Path Summary:

Slack	6.623
Data Arrival Time	8.411
Data Required Time	1.788
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.677	0.678	tINS	FF	501	IOT48[A]	clk_ibuf/O
6.590	0.913	tNET	FF	1	R7C12[1][B]	u_la0_top/rst_ao_Z/CLK
6.792	0.202	tC2Q	FR	49	R7C12[1][B]	u_la0_top/rst_ao_Z/Q
8.411	1.619	tNET	RR	1	R12C5[2][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	501	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R12C5[2][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8]/CLK
1.777	0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8]
1.788	0.011	tHld		1	R12C5[2][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8]

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.619, 88.906%; tC2Q: 0.202, 11.094%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path23

Path Summary:

Slack	6.623
Data Arrival Time	8.411
Data Required Time	1.788
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[9]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.677	0.678	tINS	FF	501	IOT48[A]	clk_ibuf/O
6.590	0.913	tNET	FF	1	R7C12[1][B]	u_la0_top/rst_ao_Z/CLK
6.792	0.202	tC2Q	FR	49	R7C12[1][B]	u_la0_top/rst_ao_Z/Q
8.411	1.619	tNET	RR	1	R12C2[0][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[9]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	501	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R12C2[0][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[9]/CLK
1.777	0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[9]
1.788	0.011	tHld		1	R12C2[0][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[9]

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.619, 88.906%; tC2Q: 0.202, 11.094%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path24

Path Summary:

Slack	6.623
Data Arrival Time	8.411
Data Required Time	1.788
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[10]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.677	0.678	tINS	FF	501	IOT48[A]	clk_ibuf/O
6.590	0.913	tNET	FF	1	R7C12[1][B]	u_la0_top/rst_ao_Z/CLK
6.792	0.202	tC2Q	FR	49	R7C12[1][B]	u_la0_top/rst_ao_Z/Q
8.411	1.619	tNET	RR	1	R12C2[0][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[10]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	501	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R12C2[0][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[10]/CLK
1.777	0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[10]
1.788	0.011	tHld		1	R12C2[0][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[10]

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.619, 88.906%; tC2Q: 0.202, 11.094%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path25

Path Summary:

Slack	6.623
Data Arrival Time	8.411
Data Required Time	1.788
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[11]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.677	0.678	tINS	FF	501	IOT48[A]	clk_ibuf/O
6.590	0.913	tNET	FF	1	R7C12[1][B]	u_la0_top/rst_ao_Z/CLK
6.792	0.202	tC2Q	FR	49	R7C12[1][B]	u_la0_top/rst_ao_Z/Q
8.411	1.619	tNET	RR	1	R9C9[2][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[11]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	501	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R9C9[2][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[11]/CLK
1.777	0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[11]
1.788	0.011	tHld		1	R9C9[2][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[11]

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.619, 88.906%; tC2Q: 0.202, 11.094%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Minimum Pulse Width Report:

Report Command:report_min_pulse_width -nworst 10 -detail

MPW1

MPW Summary:

Slack:	3.662
Actual Width:	4.662
Required Width:	1.000
Type:	Low Pulse Width
Clock:	DEFAULT_CLK
Objects:	cnt_1_Z[12]

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	clk_ibuf/I
5.688	0.688	tINS	FF	clk_ibuf/O
6.916	1.228	tNET	FF	cnt_1_Z[12]/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	clk_ibuf/I
10.675	0.675	tINS	RR	clk_ibuf/O
11.577	0.902	tNET	RR	cnt_1_Z[12]/CLK

MPW2

MPW Summary:

Slack:	3.662
Actual Width:	4.662
Required Width:	1.000
Type:	Low Pulse Width
Clock:	DEFAULT_CLK
Objects:	cnt_1_Z[10]

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	clk_ibuf/I
5.688	0.688	tINS	FF	clk_ibuf/O
6.916	1.228	tNET	FF	cnt_1_Z[10]/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	clk_ibuf/I
10.675	0.675	tINS	RR	clk_ibuf/O
11.577	0.902	tNET	RR	cnt_1_Z[10]/CLK

MPW3

MPW Summary:

Slack:	3.662
Actual Width:	4.662
Required Width:	1.000
Type:	Low Pulse Width
Clock:	DEFAULT_CLK
Objects:	cnt_1_Z[6]

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	clk_ibuf/I
5.688	0.688	tINS	FF	clk_ibuf/O
6.916	1.228	tNET	FF	cnt_1_Z[6]/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	clk_ibuf/I
10.675	0.675	tINS	RR	clk_ibuf/O
11.577	0.902	tNET	RR	cnt_1_Z[6]/CLK

MPW4

MPW Summary:

Slack:	3.662
Actual Width:	4.662
Required Width:	1.000
Type:	Low Pulse Width
Clock:	DEFAULT_CLK
Objects:	cnt_Z[11]

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	clk_ibuf/I
5.688	0.688	tINS	FF	clk_ibuf/O
6.916	1.228	tNET	FF	cnt_Z[11]/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	clk_ibuf/I
10.675	0.675	tINS	RR	clk_ibuf/O
11.577	0.902	tNET	RR	cnt_Z[11]/CLK

MPW5

MPW Summary:

Slack:	3.662
Actual Width:	4.662
Required Width:	1.000
Type:	Low Pulse Width
Clock:	DEFAULT_CLK
Objects:	n_Z[25]

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	clk_ibuf/I
5.688	0.688	tINS	FF	clk_ibuf/O
6.916	1.228	tNET	FF	n_Z[25]/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	clk_ibuf/I
10.675	0.675	tINS	RR	clk_ibuf/O
11.577	0.902	tNET	RR	n_Z[25]/CLK

MPW6

MPW Summary:

Slack:	3.662
Actual Width:	4.662
Required Width:	1.000
Type:	Low Pulse Width
Clock:	DEFAULT_CLK
Objects:	m_Z[27]

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	clk_ibuf/I
5.688	0.688	tINS	FF	clk_ibuf/O
6.916	1.228	tNET	FF	m_Z[27]/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	clk_ibuf/I
10.675	0.675	tINS	RR	clk_ibuf/O
11.577	0.902	tNET	RR	m_Z[27]/CLK

MPW7

MPW Summary:

Slack:	3.662
Actual Width:	4.662
Required Width:	1.000
Type:	Low Pulse Width
Clock:	DEFAULT_CLK
Objects:	Mdu/u_mdu/reg0_Z[26]

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	clk_ibuf/I
5.688	0.688	tINS	FF	clk_ibuf/O
6.916	1.228	tNET	FF	Mdu/u_mdu/reg0_Z[26]/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	clk_ibuf/I
10.675	0.675	tINS	RR	clk_ibuf/O
11.577	0.902	tNET	RR	Mdu/u_mdu/reg0_Z[26]/CLK

MPW8

MPW Summary:

Slack:	3.662
Actual Width:	4.662
Required Width:	1.000
Type:	Low Pulse Width
Clock:	DEFAULT_CLK
Objects:	Mdu/u_mdu/reg0_fast_Z[27]

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	clk_ibuf/I
5.688	0.688	tINS	FF	clk_ibuf/O
6.916	1.228	tNET	FF	Mdu/u_mdu/reg0_fast_Z[27]/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	clk_ibuf/I
10.675	0.675	tINS	RR	clk_ibuf/O
11.577	0.902	tNET	RR	Mdu/u_mdu/reg0_fast_Z[27]/CLK

MPW9

MPW Summary:

Slack:	3.662
Actual Width:	4.662
Required Width:	1.000
Type:	Low Pulse Width
Clock:	DEFAULT_CLK
Objects:	Mdu/u_mdu/reg0_26_rep1_Z

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	clk_ibuf/I
5.688	0.688	tINS	FF	clk_ibuf/O
6.916	1.228	tNET	FF	Mdu/u_mdu/reg0_26_rep1_Z/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	clk_ibuf/I
10.675	0.675	tINS	RR	clk_ibuf/O
11.577	0.902	tNET	RR	Mdu/u_mdu/reg0_26_rep1_Z/CLK

MPW10

MPW Summary:

Slack:	3.662
Actual Width:	4.662
Required Width:	1.000
Type:	Low Pulse Width
Clock:	DEFAULT_CLK
Objects:	Mdu/u_mdu/reg0_Z[25]

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	clk_ibuf/I
5.688	0.688	tINS	FF	clk_ibuf/O
6.916	1.228	tNET	FF	Mdu/u_mdu/reg0_Z[25]/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	clk_ibuf/I
10.675	0.675	tINS	RR	clk_ibuf/O
11.577	0.902	tNET	RR	Mdu/u_mdu/reg0_Z[25]/CLK

High Fanout Nets Report:

Report Command:report_high_fanout_nets -max_nets 10

FANOUT	NET NAME	WORST SLACK	MAX DELAY
307	clk_c	0.651	1.228
114	div_shift_number[1]	0.651	1.841
113	div_shift_number[0]	0.713	1.594
100	reg0_en	3.948	2.455
96	neg_result	4.599	1.571
92	state[1]	5.416	2.100
81	hi_result	4.237	1.522
74	reg0_exe_nx_sm0	1.988	2.259
71	state[3]	5.525	2.044
70	m0_2_03_1	1.182	2.591

Route Congestions Report:

Report Command:report_route_congestion -max_grids 10

GRID LOC	ROUTE CONGESTIONS
R33C51	0.750
R33C37	0.708
R33C40	0.681
R42C41	0.681
R38C41	0.681
R42C40	0.667
R34C37	0.667
R39C39	0.667
R34C51	0.667
R39C41	0.653

Timing Exceptions Report:

Setup Analysis Report

Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Hold Analysis Report

Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Recovery Analysis Report

Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Removal Analysis Report

Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Timing Constraints Report:

SDC Command Type	State	Detail Command