Project Settings
Project Name ao_0 Device Name rev_1: GOWIN-GW2A : GW2A_55
Implementation Name rev_1 Top Module [auto]
Pipelining 1 Retiming 0
Resource Sharing 1 Fanout Guide 10000
Disable I/O Insertion 0 Disable Sequential Optimizations 0
Clock Conversion 1 FSM Compiler 1

Run Status
Job Name Status CPU Time Real Time Memory Date/Time
(compiler)Complete 6 28 0 - 00m:01s - 2019/2/19
18:06:46
(premap)Complete 10 0 0 0m:01s 0m:02s 194MB 2019/2/19
18:06:50
(fpga_mapper)Complete 11 2 0 0m:08s 0m:09s 223MB 2019/2/19
18:07:00
Multi-srs Generator Complete2019/2/19
18:06:47

Area Summary
I/O ports (io_port) 110 Non I/O Register bits (non_io_reg) 546 (1%)
I/O Register bits (total_io_reg) 0 Block Rams (v_ram) 49 (140)
Block Multipliers (dsp_used) 0 (20) LUTs (total_luts) 475 (0%)

Timing Summary
Clock NameReq FreqEst FreqSlack
ao_top_0|clk_i219.0 MHz186.2 MHz-0.806
ao_top_0|control[0]172.0 MHz146.2 MHz-1.026
System150.0 MHz235.7 MHz2.423

Optimizations Summary
Combined Clock Conversion 2 / 0