@N: MF284 |Setting synthesis effort to medium for the design
@N: MF916 |Option synthesis_strategy=base is enabled. 
@N: MF248 |Running in 64-bit mode.
@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
@N: MF284 |Setting synthesis effort to medium for the design
@N: MT206 |Auto Constrain mode is enabled
@N: MF237 :"f:\user-bak\users\fdell\desktop\ip\integer_multiply-divider\ref_design\rem\integer_multiply_divider_pn\project\src\top.v":106:17:106:20|Generating a type srem remainder 
@N: FX493 |Applying initial value "0" on instance divisor[0].
@N: FX493 |Applying initial value "0" on instance ad[0].
@N: FX493 |Applying initial value "000000000" on instance dividend[31:23].
@N: FX493 |Applying initial value "000000000" on instance divisor[31:23].
@N: FX493 |Applying initial value "000000000" on instance m[31:23].
@N: FX493 |Applying initial value "00000000" on instance n[30:23].
@N: MO231 :"f:\user-bak\users\fdell\desktop\ip\integer_multiply-divider\ref_design\rem\integer_multiply_divider_pn\project\src\top.v":123:21:123:23|Found counter in view:work.top(verilog) instance cnt[12:0] 
@N: MO231 :"f:\user-bak\users\fdell\desktop\ip\integer_multiply-divider\ref_design\rem\integer_multiply_divider_pn\project\src\top.v":129:0:129:5|Found counter in view:work.top(verilog) instance cnt_1[12:0] 
@N: MF179 :"f:\user-bak\users\fdell\desktop\ip\integer_multiply-divider\ref_design\rem\integer_multiply_divider_pn\project\src\top.v":107:13:107:28|Found 32 by 32 bit equality operator ('==') LEDR2 (in view: work.top(verilog))
@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.  
@N: BW103 |The default time unit for the Synopsys Constraint File (SDC or FDC) is 1ns.
@N: BW107 |Synopsys Constraint File capacitance units using default value of 1pF 
@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.
@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock.
