Timing Messages

Report Title	Gowin Timing Analysis Report
Design File	F:/user-bak/Users/FDELL/Desktop/IP/Integer_Multiply-Divider/ref_design/REM/Integer_Multiply_Divider_pn/project/impl/synplify/rev_1/Integer_Multiply_Divider_pn.vm
Physical Constraints File	F:\user-bak\Users\FDELL\Desktop\IP\Integer_Multiply-Divider\ref_design\REM\Integer_Multiply_Divider_pn\project\src\Integer_Multiply_Divider_pn.cst
Timing Constraints File	---
GOWIN version	v1.9.0Beta
Part Number	GW2A-LV55PG484C8/I7
Created Time	Tue Feb 19 18:05:30 2019
Legal Announcement	Copyright (C)2014-2019 Gowin Semiconductor Corporation. All rights reserved.

Timing Summaries

STA Tool Run Summary:

Setup Delay Model	Slow 0.95V 85C
Hold Delay Model	Fast 1.05V 0C
Numbers of Paths Analyzed	2804
Numbers of Endpoints Analyzed	6744
Numbers of Falling Endpoints	1
Numbers of Setup Violated Endpoints	0
Numbers of Hold Violated Endpoints	0

Clock Summary:

Clock Name	Type	Period	Frequency(MHz)	Rise	Fall	Source	Master	Objects
DEFAULT_CLK	Base	10.000	100.000	0.000	5.000

Max Frequency Summary:

NO.	Clock Name	Fmax	Entity
1	DEFAULT_CLK	100.740(MHz)	TOP

Total Negative Slack Summary:

Clock Name	Analysis Type	Endpoints TNS	Number of Endpoints
DEFAULT_CLK	Setup	0.000	0
DEFAULT_CLK	Hold	0.000	0

Timing Details

Path Slacks Table:

Setup Paths Table

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Data Delay
1	0.073	Mdu/u_mdu/div_shift_number_Z[4]/Q	Mdu/u_mdu/reg0_Z[52]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	9.692
2	0.253	Mdu/u_mdu/reg0_fast_Z[4]/Q	Mdu/u_mdu/reg0_Z[29]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	9.512
3	0.254	Mdu/u_mdu/reg1_Z[4]/Q	Mdu/u_mdu/reg0_Z[7]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	9.511
4	0.374	Mdu/u_mdu/reg0_fast_Z[3]/Q	Mdu/u_mdu/reg0_Z[16]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	9.391
5	0.579	Mdu/u_mdu/reg1_Z[4]/Q	Mdu/u_mdu/reg0_Z[48]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	9.186
6	0.872	Mdu/u_mdu/div_shift_number_Z[1]/Q	Mdu/u_mdu/reg0_fast_Z[22]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	8.893
7	0.888	Mdu/u_mdu/reg0_fast_Z[3]/Q	Mdu/u_mdu/reg0_Z[21]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	8.877
8	0.938	Mdu/u_mdu/div_shift_number_Z[1]/Q	Mdu/u_mdu/reg0_fast_Z[15]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	8.827
9	0.938	Mdu/u_mdu/div_shift_number_Z[1]/Q	Mdu/u_mdu/reg0_Z[15]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	8.827
10	0.948	Mdu/u_mdu/reg0_Z[11]/Q	Mdu/u_mdu/reg0_fast_Z[28]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	8.817
11	0.948	Mdu/u_mdu/reg0_Z[11]/Q	Mdu/u_mdu/reg0_Z[28]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	8.817
12	1.005	Mdu/u_mdu/div_shift_number_Z[1]/Q	Mdu/u_mdu/reg0_Z[54]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	8.760
13	1.038	Mdu/u_mdu/div_shift_number_Z[1]/Q	Mdu/u_mdu/reg0_Z[58]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	8.727
14	1.038	Mdu/u_mdu/reg0_Z[11]/Q	Mdu/u_mdu/reg0_Z[56]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	8.727
15	1.050	Mdu/u_mdu/div_shift_number_Z[1]/Q	Mdu/u_mdu/reg0_22_rep1_Z/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	8.715
16	1.083	Mdu/u_mdu/div_shift_number_Z[1]/Q	Mdu/u_mdu/reg0_Z[63]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	8.682
17	1.108	Mdu/u_mdu/reg0_fast_Z[3]/Q	Mdu/u_mdu/reg0_fast_Z[20]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	8.657
18	1.108	Mdu/u_mdu/reg0_fast_Z[3]/Q	Mdu/u_mdu/reg0_Z[20]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	8.657
19	1.281	Mdu/u_mdu/div_shift_number_Z[3]/Q	Mdu/u_mdu/reg0_Z[57]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	8.484
20	1.313	Mdu/u_mdu/reg0_fast_Z[3]/Q	Mdu/u_mdu/reg0_19_rep1_Z/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	8.452
21	1.323	Mdu/u_mdu/reg0_fast_Z[3]/Q	Mdu/u_mdu/reg0_fast_Z[14]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	8.442
22	1.323	Mdu/u_mdu/reg0_fast_Z[3]/Q	Mdu/u_mdu/reg0_Z[14]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	8.442
23	1.326	Mdu/u_mdu/div_shift_number_Z[1]/Q	Mdu/u_mdu/reg0_Z[22]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	8.439
24	1.332	Mdu/u_mdu/reg0_Z[29]/Q	Mdu/u_mdu/div_shift_number_Z[0]/RESET	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	8.433
25	1.332	Mdu/u_mdu/reg0_Z[29]/Q	Mdu/u_mdu/div_shift_number_Z[1]/RESET	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	8.433

Hold Paths Table

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Data Delay
1	0.213	u_la0_top/u_ao_mem_ctrl/data_reg_Z[37]/Q	u_la0_top/u_ao_mem_ctrl/mem_mem_0_18/DI1	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.462
2	0.213	u_la0_top/u_ao_mem_ctrl/data_reg_Z[36]/Q	u_la0_top/u_ao_mem_ctrl/mem_mem_0_18/DI0	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.462
3	0.225	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[5]/Q	u_la0_top/u_ao_mem_ctrl/mem_mem_0_8/ADA6	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.343
4	0.334	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[2]/Q	u_la0_top/u_ao_mem_ctrl/mem_mem_0_8/ADA3	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.452
5	0.335	u_la0_top/u_ao_mem_ctrl/data_reg_Z[41]/Q	u_la0_top/u_ao_mem_ctrl/mem_mem_0_20/DI1	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.584
6	0.338	cnt_1_Z[1]/Q	memr_memr_0_5/ADB2	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.456
7	0.339	cnt_1_Z[0]/Q	memr_memr_0_5/ADB1	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.457
8	0.341	cnt_1_Z[2]/Q	memr_memr_0_5/ADB3	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.459
9	0.352	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[1]/Q	u_la0_top/u_ao_mem_ctrl/mem_mem_0_8/ADA2	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.470
10	0.352	cnt_Z[1]/Q	memr_memr_0_5/ADA2	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.470
11	0.352	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[3]/Q	u_la0_top/u_ao_mem_ctrl/mem_mem_0_8/ADA4	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.470
12	0.353	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[2]/Q	u_la0_top/u_ao_mem_ctrl/mem_mem_0_3/ADA3	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.471
13	0.353	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[7]/Q	u_la0_top/u_ao_mem_ctrl/mem_mem_0_3/ADA8	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.471
14	0.354	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[4]/Q	u_la0_top/u_ao_mem_ctrl/mem_mem_0_8/ADA5	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.472
15	0.354	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[6]/Q	u_la0_top/u_ao_mem_ctrl/mem_mem_0_13/ADA7	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.472
16	0.355	cnt_Z[2]/Q	memr_memr_0_5/ADA3	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.473
17	0.355	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8]/Q	u_la0_top/u_ao_mem_ctrl/mem_mem_0_8/ADA9	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.473
18	0.361	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[2]/Q	u_la0_top/u_ao_mem_ctrl/mem_mem_0_13/ADA3	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.479
19	0.361	cnt_1_Z[10]/Q	memr_memr_0_5/ADB11	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.479
20	0.363	cnt_1_Z[3]/Q	memr_memr_0_12/ADB4	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.481
21	0.363	cnt_Z[9]/Q	memr_memr_0_14/ADA10	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.481
22	0.363	cnt_1_Z[11]/Q	memr_memr_0_9/ADB12	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.481
23	0.364	cnt_1_Z[1]/Q	memr_memr_0_7/ADB2	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.482
24	0.364	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[11]/Q	u_la0_top/u_ao_mem_ctrl/mem_mem_0_3/ADA12	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.482
25	0.364	cnt_1_Z[10]/Q	memr_memr_0_14/ADB11	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.482

Recovery Paths Table

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	1.748	u_la0_top/rst_ao_Z/Q	u_la0_top/triger_level_cnt_Z[0]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	5.000	0.033	2.984
2	1.748	u_la0_top/rst_ao_Z/Q	u_la0_top/triger_level_cnt_Z[2]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	5.000	0.033	2.984
3	1.748	u_la0_top/rst_ao_Z/Q	u_la0_top/capture_window_sel[3]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	5.000	0.033	2.984
4	1.748	u_la0_top/rst_ao_Z/Q	u_la0_top/internal_reg_force_triger_syn_Z[0]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	5.000	0.033	2.984
5	1.748	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_length_Z[12]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	5.000	0.033	2.984
6	1.748	u_la0_top/rst_ao_Z/Q	u_la0_top/internal_reg_start_syn_Z[0]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	5.000	0.033	2.984
7	1.748	u_la0_top/rst_ao_Z/Q	u_la0_top/internal_reg_start_dly_Z[0]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	5.000	0.033	2.984
8	1.748	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	5.000	0.033	2.984
9	1.748	u_la0_top/rst_ao_Z/Q	u_la0_top/capture_window_sel_Z[2]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	5.000	0.033	2.984
10	1.748	u_la0_top/rst_ao_Z/Q	u_la0_top/capture_end_dly_Z/PRESET	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	5.000	0.033	2.984
11	1.748	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	5.000	0.033	2.984
12	1.748	u_la0_top/rst_ao_Z/Q	u_la0_top/capture_window_sel_Z[1]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	5.000	0.033	2.984
13	1.748	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_length_Z[4]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	5.000	0.033	2.984
14	1.748	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_length_Z[3]/PRESET	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	5.000	0.033	2.984
15	1.748	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_length_Z[9]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	5.000	0.033	2.984
16	1.748	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[12]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	5.000	0.033	2.984
17	1.748	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[2]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	5.000	0.033	2.984
18	1.748	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[1]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	5.000	0.033	2.984
19	1.748	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_length_Z[7]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	5.000	0.033	2.984
20	1.748	u_la0_top/rst_ao_Z/Q	u_la0_top/trigger_seq_start_Z/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	5.000	0.033	2.984
21	1.748	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[9]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	5.000	0.033	2.984
22	1.748	u_la0_top/rst_ao_Z/Q	u_la0_top/genblk1.u_ao_match_0/match_sep/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	5.000	0.033	2.984
23	1.748	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[3]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	5.000	0.033	2.984
24	1.748	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	5.000	0.033	2.984
25	1.748	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_length_Z[2]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	5.000	0.033	2.984

Removal Paths Table

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	6.760	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	-5.000	0.013	1.958
2	6.760	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_Z/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	-5.000	0.013	1.958
3	6.760	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_loop_Z/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	-5.000	0.013	1.958
4	6.760	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_length_Z[0]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	-5.000	0.013	1.958
5	6.760	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_length_Z[1]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	-5.000	0.013	1.958
6	6.760	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_length_Z[2]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	-5.000	0.013	1.958
7	6.760	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_length_Z[3]/PRESET	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	-5.000	0.013	1.958
8	6.760	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_length_Z[4]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	-5.000	0.013	1.958
9	6.760	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_length_Z[5]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	-5.000	0.013	1.958
10	6.760	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_length_Z[6]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	-5.000	0.013	1.958
11	6.760	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_length_Z[7]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	-5.000	0.013	1.958
12	6.760	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_length_Z[8]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	-5.000	0.013	1.958
13	6.760	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_length_Z[9]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	-5.000	0.013	1.958
14	6.760	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_length_Z[10]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	-5.000	0.013	1.958
15	6.760	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_length_Z[11]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	-5.000	0.013	1.958
16	6.760	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_length_Z[12]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	-5.000	0.013	1.958
17	6.760	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	-5.000	0.013	1.958
18	6.760	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[1]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	-5.000	0.013	1.958
19	6.760	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[2]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	-5.000	0.013	1.958
20	6.760	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[3]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	-5.000	0.013	1.958
21	6.760	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[4]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	-5.000	0.013	1.958
22	6.760	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[5]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	-5.000	0.013	1.958
23	6.760	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[6]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	-5.000	0.013	1.958
24	6.760	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[7]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	-5.000	0.013	1.958
25	6.760	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	-5.000	0.013	1.958

Minimum Pulse Width Table:

Report Command:report_min_pulse_width -nworst 10 -detail

Number	Slack	Actual Width	Required Width	Type	Clock	Objects
1	3.662	4.662	1.000	Low Pulse Width	DEFAULT_CLK	cnt_1_Z[12]
2	3.662	4.662	1.000	Low Pulse Width	DEFAULT_CLK	cnt_1_Z[10]
3	3.662	4.662	1.000	Low Pulse Width	DEFAULT_CLK	cnt_1_Z[6]
4	3.662	4.662	1.000	Low Pulse Width	DEFAULT_CLK	cnt_Z[11]
5	3.662	4.662	1.000	Low Pulse Width	DEFAULT_CLK	divisor[31]
6	3.662	4.662	1.000	Low Pulse Width	DEFAULT_CLK	n_Z[30]
7	3.662	4.662	1.000	Low Pulse Width	DEFAULT_CLK	Mdu/u_mdu/reg0_Z[30]
8	3.662	4.662	1.000	Low Pulse Width	DEFAULT_CLK	Mdu/u_mdu/reg0_1_rep1_Z
9	3.662	4.662	1.000	Low Pulse Width	DEFAULT_CLK	Mdu/u_mdu/reg0_fast_Z[1]
10	3.662	4.662	1.000	Low Pulse Width	DEFAULT_CLK	Mdu/u_mdu/reg0_Z[29]

Timing Report By Analysis Type:

Setup Analysis Report

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	0.073
Data Arrival Time	11.575
Data Required Time	11.648
From	Mdu/u_mdu/div_shift_number_Z[4]
To	Mdu/u_mdu/reg0_Z[52]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.683	0.683	tINS	RR	497	IOT48[A]	clk_ibuf/O
1.883	1.201	tNET	RR	1	R51C34[0][A]	Mdu/u_mdu/div_shift_number_Z[4]/CLK
2.115	0.232	tC2Q	RF	22	R51C34[0][A]	Mdu/u_mdu/div_shift_number_Z[4]/Q
3.304	1.189	tNET	FF	1	R37C30[1][A]	Mdu/u_mdu/div_shift_number_RNI9QR3_2[4]/I0
3.821	0.517	tINS	FF	41	R37C30[1][A]	Mdu/u_mdu/div_shift_number_RNI9QR3_2[4]/F
6.391	2.569	tNET	FF	1	R56C33[1][B]	Mdu/u_mdu/m52_4_03_1_0_1_cZ/I0
6.762	0.371	tINS	FF	1	R56C33[1][B]	Mdu/u_mdu/m52_4_03_1_0_1_cZ/F
7.446	0.684	tNET	FF	1	R51C34[2][B]	Mdu/u_mdu/m52_4_03_1_0_cZ/I3
7.817	0.371	tINS	FF	1	R51C34[2][B]	Mdu/u_mdu/m52_4_03_1_0_cZ/F
8.820	1.003	tNET	FF	1	R46C38[3][A]	Mdu/u_mdu/reg0_exe_nx_m0_cZ[52]/I2
9.375	0.555	tINS	FF	1	R46C38[3][A]	Mdu/u_mdu/reg0_exe_nx_m0_cZ[52]/F
9.375	0.000	tNET	FF	1	R46C38[3][A]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[52]/I0
9.478	0.103	tINS	FF	1	R46C38[3][A]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[52]/O
11.026	1.548	tNET	FF	1	R30C41[0][A]	Mdu/u_mdu/reg0_nx_0[52]/I2
11.575	0.549	tINS	FR	1	R30C41[0][A]	Mdu/u_mdu/reg0_nx_0[52]/F
11.575	0.000	tNET	RR	1	R30C41[0][A]	Mdu/u_mdu/reg0_Z[52]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	497	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R30C41[0][A]	Mdu/u_mdu/reg0_Z[52]/CLK
11.683	-0.200	tUnc				Mdu/u_mdu/reg0_Z[52]
11.648	-0.035	tSu		1	R30C41[0][A]	Mdu/u_mdu/reg0_Z[52]

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	6
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 2.466, 25.445%; route: 6.994, 72.161%; tC2Q: 0.232, 2.394%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path2

Path Summary:

Slack	0.253
Data Arrival Time	11.395
Data Required Time	11.648
From	Mdu/u_mdu/reg0_fast_Z[4]
To	Mdu/u_mdu/reg0_Z[29]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.683	0.683	tINS	RR	497	IOT48[A]	clk_ibuf/O
1.883	1.201	tNET	RR	1	R37C30[0][B]	Mdu/u_mdu/reg0_fast_Z[4]/CLK
2.115	0.232	tC2Q	RF	7	R37C30[0][B]	Mdu/u_mdu/reg0_fast_Z[4]/Q
3.060	0.945	tNET	FF	1	R35C35[0][A]	Mdu/u_mdu/reg0_neg_axb_4_par_0_cp_cZ/I2
3.513	0.453	tINS	FF	1	R35C35[0][A]	Mdu/u_mdu/reg0_neg_axb_4_par_0_cp_cZ/F
4.363	0.850	tNET	FF	2	R44C32[1][B]	Mdu/u_mdu/reg0_neg_axb_4_par_cp_2/I0
4.933	0.570	tINS	FR	1	R44C32[1][B]	Mdu/u_mdu/reg0_neg_axb_4_par_cp_2/COUT
4.933	0.000	tNET	RR	2	R44C32[2][A]	Mdu/u_mdu/reg0_neg_axb_8_par_1/CIN
4.968	0.035	tINS	RF	1	R44C32[2][A]	Mdu/u_mdu/reg0_neg_axb_8_par_1/COUT
4.968	0.000	tNET	FF	2	R44C32[2][B]	Mdu/u_mdu/reg0_neg_axb_12_par_1/CIN
5.003	0.035	tINS	FF	1	R44C32[2][B]	Mdu/u_mdu/reg0_neg_axb_12_par_1/COUT
5.003	0.000	tNET	FF	2	R44C33[0][A]	Mdu/u_mdu/reg0_neg_axb_16_par_1/CIN
5.038	0.035	tINS	FF	1	R44C33[0][A]	Mdu/u_mdu/reg0_neg_axb_16_par_1/COUT
5.038	0.000	tNET	FF	2	R44C33[0][B]	Mdu/u_mdu/reg0_neg_cry_19_0/CIN
5.074	0.035	tINS	FF	1	R44C33[0][B]	Mdu/u_mdu/reg0_neg_cry_19_0/COUT
5.074	0.000	tNET	FF	2	R44C33[1][A]	Mdu/u_mdu/reg0_neg_cry_20_0/CIN
5.109	0.035	tINS	FF	1	R44C33[1][A]	Mdu/u_mdu/reg0_neg_cry_20_0/COUT
5.109	0.000	tNET	FF	2	R44C33[1][B]	Mdu/u_mdu/reg0_neg_cry_21_0/CIN
5.144	0.035	tINS	FF	1	R44C33[1][B]	Mdu/u_mdu/reg0_neg_cry_21_0/COUT
5.144	0.000	tNET	FF	2	R44C33[2][A]	Mdu/u_mdu/reg0_neg_cry_22_0/CIN
5.179	0.035	tINS	FF	1	R44C33[2][A]	Mdu/u_mdu/reg0_neg_cry_22_0/COUT
5.179	0.000	tNET	FF	2	R44C33[2][B]	Mdu/u_mdu/reg0_neg_cry_23_0/CIN
5.214	0.035	tINS	FF	1	R44C33[2][B]	Mdu/u_mdu/reg0_neg_cry_23_0/COUT
5.214	0.000	tNET	FF	2	R44C34[0][A]	Mdu/u_mdu/reg0_neg_cry_24_0/CIN
5.250	0.035	tINS	FF	1	R44C34[0][A]	Mdu/u_mdu/reg0_neg_cry_24_0/COUT
5.250	0.000	tNET	FF	2	R44C34[0][B]	Mdu/u_mdu/reg0_neg_cry_25_0/CIN
5.285	0.035	tINS	FF	1	R44C34[0][B]	Mdu/u_mdu/reg0_neg_cry_25_0/COUT
5.285	0.000	tNET	FF	2	R44C34[1][A]	Mdu/u_mdu/reg0_neg_cry_26_0/CIN
5.320	0.035	tINS	FF	1	R44C34[1][A]	Mdu/u_mdu/reg0_neg_cry_26_0/COUT
5.320	0.000	tNET	FF	2	R44C34[1][B]	Mdu/u_mdu/reg0_neg_cry_27_0/CIN
5.355	0.035	tINS	FF	1	R44C34[1][B]	Mdu/u_mdu/reg0_neg_cry_27_0/COUT
5.355	0.000	tNET	FF	2	R44C34[2][A]	Mdu/u_mdu/reg0_neg_cry_28_0/CIN
5.390	0.035	tINS	FF	1	R44C34[2][A]	Mdu/u_mdu/reg0_neg_cry_28_0/COUT
5.390	0.000	tNET	FF	2	R44C34[2][B]	Mdu/u_mdu/reg0_neg_cry_29_0/CIN
5.860	0.470	tINS	FF	3	R44C34[2][B]	Mdu/u_mdu/reg0_neg_cry_29_0/SUM
7.024	1.163	tNET	FF	1	R34C33[2][B]	Mdu/u_mdu/reg0_exe_div_dbz_1_cZ[29]/I3
7.594	0.570	tINS	FR	2	R34C33[2][B]	Mdu/u_mdu/reg0_exe_div_dbz_1_cZ[29]/F
7.770	0.176	tNET	RR	1	R35C33[3][B]	Mdu/u_mdu/reg0_nx_sxcf0_1_cZ[29]/I1
8.340	0.570	tINS	RR	1	R35C33[3][B]	Mdu/u_mdu/reg0_nx_sxcf0_1_cZ[29]/F
8.341	0.001	tNET	RR	1	R35C33[3][A]	Mdu/u_mdu/reg0_nx_sxcf0_cZ[29]/I0
8.858	0.517	tINS	RF	2	R35C33[3][A]	Mdu/u_mdu/reg0_nx_sxcf0_cZ[29]/F
9.790	0.933	tNET	FF	1	R44C33[3][A]	Mdu/u_mdu/reg0_nx_sn_cZ[29]/I1
10.307	0.517	tINS	FF	1	R44C33[3][A]	Mdu/u_mdu/reg0_nx_sn_cZ[29]/F
10.825	0.518	tNET	FF	1	R37C33[2][A]	Mdu/u_mdu/reg0_nx_mb[29]/I0
11.395	0.570	tINS	FR	1	R37C33[2][A]	Mdu/u_mdu/reg0_nx_mb[29]/F
11.395	0.000	tNET	RR	1	R37C33[2][A]	Mdu/u_mdu/reg0_Z[29]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	497	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R37C33[2][A]	Mdu/u_mdu/reg0_Z[29]/CLK
11.683	-0.200	tUnc				Mdu/u_mdu/reg0_Z[29]
11.648	-0.035	tSu		1	R37C33[2][A]	Mdu/u_mdu/reg0_Z[29]

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	8
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 4.695, 49.353%; route: 4.586, 48.208%; tC2Q: 0.232, 2.439%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path3

Path Summary:

Slack	0.254
Data Arrival Time	11.394
Data Required Time	11.648
From	Mdu/u_mdu/reg1_Z[4]
To	Mdu/u_mdu/reg0_Z[7]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.683	0.683	tINS	RR	497	IOT48[A]	clk_ibuf/O
1.883	1.201	tNET	RR	1	R40C32[2][A]	Mdu/u_mdu/reg1_Z[4]/CLK
2.115	0.232	tC2Q	RF	8	R40C32[2][A]	Mdu/u_mdu/reg1_Z[4]/Q
3.061	0.945	tNET	FF	1	R42C37[3][B]	Mdu/u_mdu/adder_sum_s_4_sf_lofx_cZ/I1
3.616	0.555	tINS	FF	1	R42C37[3][B]	Mdu/u_mdu/adder_sum_s_4_sf_lofx_cZ/F
4.271	0.656	tNET	FF	2	R43C40[0][A]	Mdu/u_mdu/adder_sum_cry_4_0/I0
4.841	0.570	tINS	FR	1	R43C40[0][A]	Mdu/u_mdu/adder_sum_cry_4_0/COUT
4.841	0.000	tNET	RR	2	R43C40[0][B]	Mdu/u_mdu/adder_sum_cry_5_0/CIN
4.877	0.035	tINS	RF	1	R43C40[0][B]	Mdu/u_mdu/adder_sum_cry_5_0/COUT
4.877	0.000	tNET	FF	2	R43C40[1][A]	Mdu/u_mdu/adder_sum_cry_6_0/CIN
4.912	0.035	tINS	FF	1	R43C40[1][A]	Mdu/u_mdu/adder_sum_cry_6_0/COUT
4.912	0.000	tNET	FF	2	R43C40[1][B]	Mdu/u_mdu/adder_sum_cry_7_0/CIN
4.947	0.035	tINS	FF	1	R43C40[1][B]	Mdu/u_mdu/adder_sum_cry_7_0/COUT
4.947	0.000	tNET	FF	2	R43C40[2][A]	Mdu/u_mdu/adder_sum_cry_8_0/CIN
4.982	0.035	tINS	FF	1	R43C40[2][A]	Mdu/u_mdu/adder_sum_cry_8_0/COUT
4.982	0.000	tNET	FF	2	R43C40[2][B]	Mdu/u_mdu/adder_sum_cry_9_0/CIN
5.017	0.035	tINS	FF	1	R43C40[2][B]	Mdu/u_mdu/adder_sum_cry_9_0/COUT
5.017	0.000	tNET	FF	2	R43C41[0][A]	Mdu/u_mdu/adder_sum_cry_10_0/CIN
5.053	0.035	tINS	FF	1	R43C41[0][A]	Mdu/u_mdu/adder_sum_cry_10_0/COUT
5.053	0.000	tNET	FF	2	R43C41[0][B]	Mdu/u_mdu/adder_sum_cry_11_0/CIN
5.088	0.035	tINS	FF	1	R43C41[0][B]	Mdu/u_mdu/adder_sum_cry_11_0/COUT
5.088	0.000	tNET	FF	2	R43C41[1][A]	Mdu/u_mdu/adder_sum_cry_12_0/CIN
5.123	0.035	tINS	FF	1	R43C41[1][A]	Mdu/u_mdu/adder_sum_cry_12_0/COUT
5.123	0.000	tNET	FF	2	R43C41[1][B]	Mdu/u_mdu/adder_sum_cry_13_0/CIN
5.158	0.035	tINS	FF	1	R43C41[1][B]	Mdu/u_mdu/adder_sum_cry_13_0/COUT
5.158	0.000	tNET	FF	2	R43C41[2][A]	Mdu/u_mdu/adder_sum_cry_14_0/CIN
5.193	0.035	tINS	FF	1	R43C41[2][A]	Mdu/u_mdu/adder_sum_cry_14_0/COUT
5.193	0.000	tNET	FF	2	R43C41[2][B]	Mdu/u_mdu/adder_sum_cry_15_0/CIN
5.229	0.035	tINS	FF	1	R43C41[2][B]	Mdu/u_mdu/adder_sum_cry_15_0/COUT
5.229	0.000	tNET	FF	2	R43C42[0][A]	Mdu/u_mdu/adder_sum_cry_16_0/CIN
5.264	0.035	tINS	FF	1	R43C42[0][A]	Mdu/u_mdu/adder_sum_cry_16_0/COUT
5.264	0.000	tNET	FF	2	R43C42[0][B]	Mdu/u_mdu/adder_sum_cry_17_0/CIN
5.299	0.035	tINS	FF	1	R43C42[0][B]	Mdu/u_mdu/adder_sum_cry_17_0/COUT
5.299	0.000	tNET	FF	2	R43C42[1][A]	Mdu/u_mdu/adder_sum_cry_18_0/CIN
5.334	0.035	tINS	FF	1	R43C42[1][A]	Mdu/u_mdu/adder_sum_cry_18_0/COUT
5.334	0.000	tNET	FF	2	R43C42[1][B]	Mdu/u_mdu/adder_sum_cry_19_0/CIN
5.369	0.035	tINS	FF	1	R43C42[1][B]	Mdu/u_mdu/adder_sum_cry_19_0/COUT
5.369	0.000	tNET	FF	2	R43C42[2][A]	Mdu/u_mdu/adder_sum_cry_20_0/CIN
5.405	0.035	tINS	FF	1	R43C42[2][A]	Mdu/u_mdu/adder_sum_cry_20_0/COUT
5.405	0.000	tNET	FF	2	R43C42[2][B]	Mdu/u_mdu/adder_sum_cry_21_0/CIN
5.440	0.035	tINS	FF	1	R43C42[2][B]	Mdu/u_mdu/adder_sum_cry_21_0/COUT
5.440	0.000	tNET	FF	2	R43C43[0][A]	Mdu/u_mdu/adder_sum_cry_22_0/CIN
5.475	0.035	tINS	FF	1	R43C43[0][A]	Mdu/u_mdu/adder_sum_cry_22_0/COUT
5.475	0.000	tNET	FF	2	R43C43[0][B]	Mdu/u_mdu/adder_sum_cry_23_0/CIN
5.510	0.035	tINS	FF	1	R43C43[0][B]	Mdu/u_mdu/adder_sum_cry_23_0/COUT
5.510	0.000	tNET	FF	2	R43C43[1][A]	Mdu/u_mdu/adder_sum_cry_24_0/CIN
5.545	0.035	tINS	FF	1	R43C43[1][A]	Mdu/u_mdu/adder_sum_cry_24_0/COUT
5.545	0.000	tNET	FF	2	R43C43[1][B]	Mdu/u_mdu/adder_sum_cry_25_0/CIN
5.581	0.035	tINS	FF	1	R43C43[1][B]	Mdu/u_mdu/adder_sum_cry_25_0/COUT
5.581	0.000	tNET	FF	2	R43C43[2][A]	Mdu/u_mdu/adder_sum_cry_26_0/CIN
5.616	0.035	tINS	FF	1	R43C43[2][A]	Mdu/u_mdu/adder_sum_cry_26_0/COUT
5.616	0.000	tNET	FF	2	R43C43[2][B]	Mdu/u_mdu/adder_sum_cry_27_0/CIN
5.651	0.035	tINS	FF	1	R43C43[2][B]	Mdu/u_mdu/adder_sum_cry_27_0/COUT
5.651	0.000	tNET	FF	2	R43C44[0][A]	Mdu/u_mdu/adder_sum_cry_28_0/CIN
5.686	0.035	tINS	FF	1	R43C44[0][A]	Mdu/u_mdu/adder_sum_cry_28_0/COUT
5.686	0.000	tNET	FF	2	R43C44[0][B]	Mdu/u_mdu/adder_sum_cry_29_0/CIN
5.721	0.035	tINS	FF	1	R43C44[0][B]	Mdu/u_mdu/adder_sum_cry_29_0/COUT
5.721	0.000	tNET	FF	2	R43C44[1][A]	Mdu/u_mdu/adder_sum_cry_30_0/CIN
5.757	0.035	tINS	FF	1	R43C44[1][A]	Mdu/u_mdu/adder_sum_cry_30_0/COUT
5.757	0.000	tNET	FF	2	R43C44[1][B]	Mdu/u_mdu/adder_sum_cry_31_0/CIN
5.792	0.035	tINS	FF	1	R43C44[1][B]	Mdu/u_mdu/adder_sum_cry_31_0/COUT
5.792	0.000	tNET	FF	2	R43C44[2][A]	Mdu/u_mdu/adder_sum_s_32_0/CIN
6.262	0.470	tINS	FF	6	R43C44[2][A]	Mdu/u_mdu/adder_sum_s_32_0/SUM
7.068	0.806	tNET	FF	1	R47C39[2][B]	Mdu/u_mdu/reg0_exe_nx_ss0_cZ/I0
7.585	0.517	tINS	FF	50	R47C39[2][B]	Mdu/u_mdu/reg0_exe_nx_ss0_cZ/F
8.340	0.755	tNET	FF	1	R44C35[2][A]	Mdu/u_mdu/reg0_exe_nx_m1_cZ[7]/I3
8.895	0.555	tINS	FF	1	R44C35[2][A]	Mdu/u_mdu/reg0_exe_nx_m1_cZ[7]/F
9.413	0.518	tNET	FF	1	R38C35[3][B]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[7]/I1
9.784	0.371	tINS	FF	1	R38C35[3][B]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[7]/F
10.274	0.490	tNET	FF	1	R34C35[3][B]	Mdu/u_mdu/reg0_exe_nx_cZ[7]/I3
10.844	0.570	tINS	FR	1	R34C35[3][B]	Mdu/u_mdu/reg0_exe_nx_cZ[7]/F
10.845	0.001	tNET	RR	1	R34C35[0][A]	Mdu/u_mdu/reg0_nx_cZ[7]/I0
11.394	0.549	tINS	RR	1	R34C35[0][A]	Mdu/u_mdu/reg0_nx_cZ[7]/F
11.394	0.000	tNET	RR	1	R34C35[0][A]	Mdu/u_mdu/reg0_Z[7]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	497	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R34C35[0][A]	Mdu/u_mdu/reg0_Z[7]/CLK
11.683	-0.200	tUnc				Mdu/u_mdu/reg0_Z[7]
11.648	-0.035	tSu		1	R34C35[0][A]	Mdu/u_mdu/reg0_Z[7]

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	8
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 5.107, 53.700%; route: 4.172, 43.861%; tC2Q: 0.232, 2.439%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path4

Path Summary:

Slack	0.374
Data Arrival Time	11.274
Data Required Time	11.648
From	Mdu/u_mdu/reg0_fast_Z[3]
To	Mdu/u_mdu/reg0_Z[16]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.683	0.683	tINS	RR	497	IOT48[A]	clk_ibuf/O
1.883	1.201	tNET	RR	1	R34C30[2][A]	Mdu/u_mdu/reg0_fast_Z[3]/CLK
2.115	0.232	tC2Q	RF	7	R34C30[2][A]	Mdu/u_mdu/reg0_fast_Z[3]/Q
3.212	1.097	tNET	FF	1	R37C38[3][B]	Mdu/u_mdu/reg0_neg_axb_0_par_0_cp_0_cZ/I3
3.767	0.555	tINS	FF	1	R37C38[3][B]	Mdu/u_mdu/reg0_neg_axb_0_par_0_cp_0_cZ/F
4.374	0.607	tNET	FF	2	R46C38[1][A]	Mdu/u_mdu/reg0_neg_axb_0_par_cp_0_0/I0
4.944	0.570	tINS	FR	1	R46C38[1][A]	Mdu/u_mdu/reg0_neg_axb_0_par_cp_0_0/COUT
4.944	0.000	tNET	RR	2	R46C38[1][B]	Mdu/u_mdu/reg0_neg_axb_4_par_cp_0_0/CIN
4.979	0.035	tINS	RF	1	R46C38[1][B]	Mdu/u_mdu/reg0_neg_axb_4_par_cp_0_0/COUT
4.979	0.000	tNET	FF	2	R46C38[2][A]	Mdu/u_mdu/reg0_neg_axb_8_par_cp_1/CIN
5.015	0.035	tINS	FF	1	R46C38[2][A]	Mdu/u_mdu/reg0_neg_axb_8_par_cp_1/COUT
5.015	0.000	tNET	FF	2	R46C38[2][B]	Mdu/u_mdu/reg0_neg_axb_12_par_cp_1/CIN
5.050	0.035	tINS	FF	1	R46C38[2][B]	Mdu/u_mdu/reg0_neg_axb_12_par_cp_1/COUT
5.050	0.000	tNET	FF	2	R46C39[0][A]	Mdu/u_mdu/reg0_neg_axb_16_par_cp_1/CIN
5.085	0.035	tINS	FF	1	R46C39[0][A]	Mdu/u_mdu/reg0_neg_axb_16_par_cp_1/COUT
5.085	0.000	tNET	FF	2	R46C39[0][B]	Mdu/u_mdu/reg0_neg_axb_19_par_1/CIN
5.120	0.035	tINS	FF	1	R46C39[0][B]	Mdu/u_mdu/reg0_neg_axb_19_par_1/COUT
5.120	0.000	tNET	FF	2	R46C39[1][A]	Mdu/u_mdu/reg0_neg_axb_23_par_1/CIN
5.155	0.035	tINS	FF	1	R46C39[1][A]	Mdu/u_mdu/reg0_neg_axb_23_par_1/COUT
5.155	0.000	tNET	FF	2	R46C39[1][B]	Mdu/u_mdu/reg0_neg_axb_27_par_1/CIN
5.191	0.035	tINS	FF	1	R46C39[1][B]	Mdu/u_mdu/reg0_neg_axb_27_par_1/COUT
5.191	0.000	tNET	FF	2	R46C39[2][A]	Mdu/u_mdu/reg0_neg_axb_31_par_1/CIN
5.226	0.035	tINS	FF	1	R46C39[2][A]	Mdu/u_mdu/reg0_neg_axb_31_par_1/COUT
5.226	0.000	tNET	FF	2	R46C39[2][B]	Mdu/u_mdu/reg0_neg_cry_34_0/CIN
5.261	0.035	tINS	FF	1	R46C39[2][B]	Mdu/u_mdu/reg0_neg_cry_34_0/COUT
5.261	0.000	tNET	FF	2	R46C40[0][A]	Mdu/u_mdu/reg0_neg_cry_35_0/CIN
5.296	0.035	tINS	FF	1	R46C40[0][A]	Mdu/u_mdu/reg0_neg_cry_35_0/COUT
5.296	0.000	tNET	FF	2	R46C40[0][B]	Mdu/u_mdu/reg0_neg_cry_36_0/CIN
5.331	0.035	tINS	FF	1	R46C40[0][B]	Mdu/u_mdu/reg0_neg_cry_36_0/COUT
5.331	0.000	tNET	FF	2	R46C40[1][A]	Mdu/u_mdu/reg0_neg_cry_37_0/CIN
5.367	0.035	tINS	FF	1	R46C40[1][A]	Mdu/u_mdu/reg0_neg_cry_37_0/COUT
5.367	0.000	tNET	FF	2	R46C40[1][B]	Mdu/u_mdu/reg0_neg_cry_38_0/CIN
5.402	0.035	tINS	FF	1	R46C40[1][B]	Mdu/u_mdu/reg0_neg_cry_38_0/COUT
5.402	0.000	tNET	FF	2	R46C40[2][A]	Mdu/u_mdu/reg0_neg_cry_39_0/CIN
5.437	0.035	tINS	FF	1	R46C40[2][A]	Mdu/u_mdu/reg0_neg_cry_39_0/COUT
5.437	0.000	tNET	FF	2	R46C40[2][B]	Mdu/u_mdu/reg0_neg_cry_40_0/CIN
5.472	0.035	tINS	FF	1	R46C40[2][B]	Mdu/u_mdu/reg0_neg_cry_40_0/COUT
5.472	0.000	tNET	FF	2	R46C41[0][A]	Mdu/u_mdu/reg0_neg_cry_41_0/CIN
5.507	0.035	tINS	FF	1	R46C41[0][A]	Mdu/u_mdu/reg0_neg_cry_41_0/COUT
5.507	0.000	tNET	FF	2	R46C41[0][B]	Mdu/u_mdu/reg0_neg_cry_42_0/CIN
5.543	0.035	tINS	FF	1	R46C41[0][B]	Mdu/u_mdu/reg0_neg_cry_42_0/COUT
5.543	0.000	tNET	FF	2	R46C41[1][A]	Mdu/u_mdu/reg0_neg_cry_43_0/CIN
5.578	0.035	tINS	FF	1	R46C41[1][A]	Mdu/u_mdu/reg0_neg_cry_43_0/COUT
5.578	0.000	tNET	FF	2	R46C41[1][B]	Mdu/u_mdu/reg0_neg_cry_44_0/CIN
5.613	0.035	tINS	FF	1	R46C41[1][B]	Mdu/u_mdu/reg0_neg_cry_44_0/COUT
5.613	0.000	tNET	FF	2	R46C41[2][A]	Mdu/u_mdu/reg0_neg_cry_45_0/CIN
5.648	0.035	tINS	FF	1	R46C41[2][A]	Mdu/u_mdu/reg0_neg_cry_45_0/COUT
5.648	0.000	tNET	FF	2	R46C41[2][B]	Mdu/u_mdu/reg0_neg_cry_46_0/CIN
5.683	0.035	tINS	FF	1	R46C41[2][B]	Mdu/u_mdu/reg0_neg_cry_46_0/COUT
5.683	0.000	tNET	FF	2	R46C42[0][A]	Mdu/u_mdu/reg0_neg_cry_47_0/CIN
5.719	0.035	tINS	FF	1	R46C42[0][A]	Mdu/u_mdu/reg0_neg_cry_47_0/COUT
5.719	0.000	tNET	FF	2	R46C42[0][B]	Mdu/u_mdu/reg0_neg_cry_48_0/CIN
6.189	0.470	tINS	FF	1	R46C42[0][B]	Mdu/u_mdu/reg0_neg_cry_48_0/SUM
7.581	1.392	tNET	FF	1	R30C33[2][A]	Mdu/u_mdu/reg0_post_swap_2[16]/I2
7.952	0.371	tINS	FF	1	R30C33[2][A]	Mdu/u_mdu/reg0_post_swap_2[16]/F
7.952	0.000	tNET	FF	1	R30C33[2][A]	Mdu/u_mdu/reg0_post_swap_4[16]/I0
8.055	0.103	tINS	FF	1	R30C33[2][A]	Mdu/u_mdu/reg0_post_swap_4[16]/O
8.744	0.690	tNET	FF	1	R34C31[0][A]	Mdu/u_mdu/reg0_post_swap_5[16]/I1
9.197	0.453	tINS	FF	2	R34C31[0][A]	Mdu/u_mdu/reg0_post_swap_5[16]/F
10.262	1.065	tNET	FF	1	R46C35[3][B]	Mdu/u_mdu/reg0_nx_1_cZ[16]/I0
10.724	0.462	tINS	FR	1	R46C35[3][B]	Mdu/u_mdu/reg0_nx_1_cZ[16]/F
10.725	0.001	tNET	RR	1	R46C35[0][A]	Mdu/u_mdu/reg0_nx_cZ[16]/I1
11.274	0.549	tINS	RR	1	R46C35[0][A]	Mdu/u_mdu/reg0_nx_cZ[16]/F
11.274	0.000	tNET	RR	1	R46C35[0][A]	Mdu/u_mdu/reg0_Z[16]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	497	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R46C35[0][A]	Mdu/u_mdu/reg0_Z[16]/CLK
11.683	-0.200	tUnc				Mdu/u_mdu/reg0_Z[16]
11.648	-0.035	tSu		1	R46C35[0][A]	Mdu/u_mdu/reg0_Z[16]

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	8
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 4.307, 45.866%; route: 4.852, 51.664%; tC2Q: 0.232, 2.470%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path5

Path Summary:

Slack	0.579
Data Arrival Time	11.069
Data Required Time	11.648
From	Mdu/u_mdu/reg1_Z[4]
To	Mdu/u_mdu/reg0_Z[48]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.683	0.683	tINS	RR	497	IOT48[A]	clk_ibuf/O
1.883	1.201	tNET	RR	1	R40C32[2][A]	Mdu/u_mdu/reg1_Z[4]/CLK
2.115	0.232	tC2Q	RF	8	R40C32[2][A]	Mdu/u_mdu/reg1_Z[4]/Q
3.061	0.945	tNET	FF	1	R42C37[3][B]	Mdu/u_mdu/adder_sum_s_4_sf_lofx_cZ/I1
3.616	0.555	tINS	FF	1	R42C37[3][B]	Mdu/u_mdu/adder_sum_s_4_sf_lofx_cZ/F
4.271	0.656	tNET	FF	2	R43C40[0][A]	Mdu/u_mdu/adder_sum_cry_4_0/I0
4.841	0.570	tINS	FR	1	R43C40[0][A]	Mdu/u_mdu/adder_sum_cry_4_0/COUT
4.841	0.000	tNET	RR	2	R43C40[0][B]	Mdu/u_mdu/adder_sum_cry_5_0/CIN
4.877	0.035	tINS	RF	1	R43C40[0][B]	Mdu/u_mdu/adder_sum_cry_5_0/COUT
4.877	0.000	tNET	FF	2	R43C40[1][A]	Mdu/u_mdu/adder_sum_cry_6_0/CIN
4.912	0.035	tINS	FF	1	R43C40[1][A]	Mdu/u_mdu/adder_sum_cry_6_0/COUT
4.912	0.000	tNET	FF	2	R43C40[1][B]	Mdu/u_mdu/adder_sum_cry_7_0/CIN
4.947	0.035	tINS	FF	1	R43C40[1][B]	Mdu/u_mdu/adder_sum_cry_7_0/COUT
4.947	0.000	tNET	FF	2	R43C40[2][A]	Mdu/u_mdu/adder_sum_cry_8_0/CIN
4.982	0.035	tINS	FF	1	R43C40[2][A]	Mdu/u_mdu/adder_sum_cry_8_0/COUT
4.982	0.000	tNET	FF	2	R43C40[2][B]	Mdu/u_mdu/adder_sum_cry_9_0/CIN
5.017	0.035	tINS	FF	1	R43C40[2][B]	Mdu/u_mdu/adder_sum_cry_9_0/COUT
5.017	0.000	tNET	FF	2	R43C41[0][A]	Mdu/u_mdu/adder_sum_cry_10_0/CIN
5.053	0.035	tINS	FF	1	R43C41[0][A]	Mdu/u_mdu/adder_sum_cry_10_0/COUT
5.053	0.000	tNET	FF	2	R43C41[0][B]	Mdu/u_mdu/adder_sum_cry_11_0/CIN
5.088	0.035	tINS	FF	1	R43C41[0][B]	Mdu/u_mdu/adder_sum_cry_11_0/COUT
5.088	0.000	tNET	FF	2	R43C41[1][A]	Mdu/u_mdu/adder_sum_cry_12_0/CIN
5.123	0.035	tINS	FF	1	R43C41[1][A]	Mdu/u_mdu/adder_sum_cry_12_0/COUT
5.123	0.000	tNET	FF	2	R43C41[1][B]	Mdu/u_mdu/adder_sum_cry_13_0/CIN
5.158	0.035	tINS	FF	1	R43C41[1][B]	Mdu/u_mdu/adder_sum_cry_13_0/COUT
5.158	0.000	tNET	FF	2	R43C41[2][A]	Mdu/u_mdu/adder_sum_cry_14_0/CIN
5.193	0.035	tINS	FF	1	R43C41[2][A]	Mdu/u_mdu/adder_sum_cry_14_0/COUT
5.193	0.000	tNET	FF	2	R43C41[2][B]	Mdu/u_mdu/adder_sum_cry_15_0/CIN
5.229	0.035	tINS	FF	1	R43C41[2][B]	Mdu/u_mdu/adder_sum_cry_15_0/COUT
5.229	0.000	tNET	FF	2	R43C42[0][A]	Mdu/u_mdu/adder_sum_cry_16_0/CIN
5.264	0.035	tINS	FF	1	R43C42[0][A]	Mdu/u_mdu/adder_sum_cry_16_0/COUT
5.264	0.000	tNET	FF	2	R43C42[0][B]	Mdu/u_mdu/adder_sum_cry_17_0/CIN
5.299	0.035	tINS	FF	1	R43C42[0][B]	Mdu/u_mdu/adder_sum_cry_17_0/COUT
5.299	0.000	tNET	FF	2	R43C42[1][A]	Mdu/u_mdu/adder_sum_cry_18_0/CIN
5.334	0.035	tINS	FF	1	R43C42[1][A]	Mdu/u_mdu/adder_sum_cry_18_0/COUT
5.334	0.000	tNET	FF	2	R43C42[1][B]	Mdu/u_mdu/adder_sum_cry_19_0/CIN
5.369	0.035	tINS	FF	1	R43C42[1][B]	Mdu/u_mdu/adder_sum_cry_19_0/COUT
5.369	0.000	tNET	FF	2	R43C42[2][A]	Mdu/u_mdu/adder_sum_cry_20_0/CIN
5.405	0.035	tINS	FF	1	R43C42[2][A]	Mdu/u_mdu/adder_sum_cry_20_0/COUT
5.405	0.000	tNET	FF	2	R43C42[2][B]	Mdu/u_mdu/adder_sum_cry_21_0/CIN
5.440	0.035	tINS	FF	1	R43C42[2][B]	Mdu/u_mdu/adder_sum_cry_21_0/COUT
5.440	0.000	tNET	FF	2	R43C43[0][A]	Mdu/u_mdu/adder_sum_cry_22_0/CIN
5.475	0.035	tINS	FF	1	R43C43[0][A]	Mdu/u_mdu/adder_sum_cry_22_0/COUT
5.475	0.000	tNET	FF	2	R43C43[0][B]	Mdu/u_mdu/adder_sum_cry_23_0/CIN
5.510	0.035	tINS	FF	1	R43C43[0][B]	Mdu/u_mdu/adder_sum_cry_23_0/COUT
5.510	0.000	tNET	FF	2	R43C43[1][A]	Mdu/u_mdu/adder_sum_cry_24_0/CIN
5.545	0.035	tINS	FF	1	R43C43[1][A]	Mdu/u_mdu/adder_sum_cry_24_0/COUT
5.545	0.000	tNET	FF	2	R43C43[1][B]	Mdu/u_mdu/adder_sum_cry_25_0/CIN
5.581	0.035	tINS	FF	1	R43C43[1][B]	Mdu/u_mdu/adder_sum_cry_25_0/COUT
5.581	0.000	tNET	FF	2	R43C43[2][A]	Mdu/u_mdu/adder_sum_cry_26_0/CIN
5.616	0.035	tINS	FF	1	R43C43[2][A]	Mdu/u_mdu/adder_sum_cry_26_0/COUT
5.616	0.000	tNET	FF	2	R43C43[2][B]	Mdu/u_mdu/adder_sum_cry_27_0/CIN
5.651	0.035	tINS	FF	1	R43C43[2][B]	Mdu/u_mdu/adder_sum_cry_27_0/COUT
5.651	0.000	tNET	FF	2	R43C44[0][A]	Mdu/u_mdu/adder_sum_cry_28_0/CIN
5.686	0.035	tINS	FF	1	R43C44[0][A]	Mdu/u_mdu/adder_sum_cry_28_0/COUT
5.686	0.000	tNET	FF	2	R43C44[0][B]	Mdu/u_mdu/adder_sum_cry_29_0/CIN
5.721	0.035	tINS	FF	1	R43C44[0][B]	Mdu/u_mdu/adder_sum_cry_29_0/COUT
5.721	0.000	tNET	FF	2	R43C44[1][A]	Mdu/u_mdu/adder_sum_cry_30_0/CIN
5.757	0.035	tINS	FF	1	R43C44[1][A]	Mdu/u_mdu/adder_sum_cry_30_0/COUT
5.757	0.000	tNET	FF	2	R43C44[1][B]	Mdu/u_mdu/adder_sum_cry_31_0/CIN
5.792	0.035	tINS	FF	1	R43C44[1][B]	Mdu/u_mdu/adder_sum_cry_31_0/COUT
5.792	0.000	tNET	FF	2	R43C44[2][A]	Mdu/u_mdu/adder_sum_s_32_0/CIN
6.262	0.470	tINS	FF	6	R43C44[2][A]	Mdu/u_mdu/adder_sum_s_32_0/SUM
7.068	0.806	tNET	FF	1	R47C39[2][B]	Mdu/u_mdu/reg0_exe_nx_ss0_cZ/I0
7.585	0.517	tINS	FF	50	R47C39[2][B]	Mdu/u_mdu/reg0_exe_nx_ss0_cZ/F
8.433	0.847	tNET	FF	1	R43C34[3][A]	Mdu/u_mdu/reg0_exe_nx_m0_cZ[48]/I2
8.950	0.517	tINS	FF	1	R43C34[3][A]	Mdu/u_mdu/reg0_exe_nx_m0_cZ[48]/F
8.950	0.000	tNET	FF	1	R43C34[3][A]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[48]/I0
9.053	0.103	tINS	FF	1	R43C34[3][A]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[48]/O
10.499	1.446	tNET	FF	1	R33C38[2][B]	Mdu/u_mdu/reg0_nx_0[48]/I2
11.069	0.570	tINS	FR	1	R33C38[2][B]	Mdu/u_mdu/reg0_nx_0[48]/F
11.069	0.000	tNET	RR	1	R33C38[2][B]	Mdu/u_mdu/reg0_Z[48]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	497	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R33C38[2][B]	Mdu/u_mdu/reg0_Z[48]/CLK
11.683	-0.200	tUnc				Mdu/u_mdu/reg0_Z[48]
11.648	-0.035	tSu		1	R33C38[2][B]	Mdu/u_mdu/reg0_Z[48]

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 4.252, 46.294%; route: 4.701, 51.180%; tC2Q: 0.232, 2.526%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path6

Path Summary:

Slack	0.872
Data Arrival Time	10.776
Data Required Time	11.648
From	Mdu/u_mdu/div_shift_number_Z[1]
To	Mdu/u_mdu/reg0_fast_Z[22]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.683	0.683	tINS	RR	497	IOT48[A]	clk_ibuf/O
1.883	1.201	tNET	RR	1	R51C33[1][B]	Mdu/u_mdu/div_shift_number_Z[1]/CLK
2.115	0.232	tC2Q	RF	114	R51C33[1][B]	Mdu/u_mdu/div_shift_number_Z[1]/Q
3.802	1.686	tNET	FF	1	R35C33[2][A]	Mdu/u_mdu/m2_0_03_m1_e_1_cZ/I1
4.351	0.549	tINS	FR	1	R35C33[2][A]	Mdu/u_mdu/m2_0_03_m1_e_1_cZ/F
4.352	0.001	tNET	RR	1	R35C33[2][B]	Mdu/u_mdu/m2_0_03_m1_e/I2
4.805	0.453	tINS	RF	6	R35C33[2][B]	Mdu/u_mdu/m2_0_03_m1_e/F
5.531	0.726	tNET	FF	1	R51C33[3][A]	Mdu/u_mdu/m6_2_03_cZ/I2
5.902	0.371	tINS	FF	4	R51C33[3][A]	Mdu/u_mdu/m6_2_03_cZ/F
6.572	0.669	tNET	FF	1	R48C34[0][A]	Mdu/u_mdu/m22_4_01_cZ/I1
7.127	0.555	tINS	FF	1	R48C34[0][A]	Mdu/u_mdu/m22_4_01_cZ/F
7.961	0.834	tNET	FF	1	R40C31[3][B]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[22]/I2
8.531	0.570	tINS	FR	1	R40C31[3][B]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[22]/F
8.703	0.172	tNET	RR	1	R39C31[1][B]	Mdu/u_mdu/reg0_exe_nx_cZ[22]/I3
9.258	0.555	tINS	RF	3	R39C31[1][B]	Mdu/u_mdu/reg0_exe_nx_cZ[22]/F
10.206	0.948	tNET	FF	1	R35C37[0][B]	Mdu/u_mdu/reg0_nx_fast_cZ[22]/I0
10.776	0.570	tINS	FR	1	R35C37[0][B]	Mdu/u_mdu/reg0_nx_fast_cZ[22]/F
10.776	0.000	tNET	RR	1	R35C37[0][B]	Mdu/u_mdu/reg0_fast_Z[22]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	497	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R35C37[0][B]	Mdu/u_mdu/reg0_fast_Z[22]/CLK
11.683	-0.200	tUnc				Mdu/u_mdu/reg0_fast_Z[22]
11.648	-0.035	tSu		1	R35C37[0][B]	Mdu/u_mdu/reg0_fast_Z[22]

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 3.623, 40.740%; route: 5.038, 56.651%; tC2Q: 0.232, 2.609%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path7

Path Summary:

Slack	0.888
Data Arrival Time	10.760
Data Required Time	11.648
From	Mdu/u_mdu/reg0_fast_Z[3]
To	Mdu/u_mdu/reg0_Z[21]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.683	0.683	tINS	RR	497	IOT48[A]	clk_ibuf/O
1.883	1.201	tNET	RR	1	R34C30[2][A]	Mdu/u_mdu/reg0_fast_Z[3]/CLK
2.115	0.232	tC2Q	RF	7	R34C30[2][A]	Mdu/u_mdu/reg0_fast_Z[3]/Q
3.212	1.097	tNET	FF	1	R37C38[3][B]	Mdu/u_mdu/reg0_neg_axb_0_par_0_cp_0_cZ/I3
3.767	0.555	tINS	FF	1	R37C38[3][B]	Mdu/u_mdu/reg0_neg_axb_0_par_0_cp_0_cZ/F
4.374	0.607	tNET	FF	2	R46C38[1][A]	Mdu/u_mdu/reg0_neg_axb_0_par_cp_0_0/I0
4.944	0.570	tINS	FR	1	R46C38[1][A]	Mdu/u_mdu/reg0_neg_axb_0_par_cp_0_0/COUT
4.944	0.000	tNET	RR	2	R46C38[1][B]	Mdu/u_mdu/reg0_neg_axb_4_par_cp_0_0/CIN
4.979	0.035	tINS	RF	1	R46C38[1][B]	Mdu/u_mdu/reg0_neg_axb_4_par_cp_0_0/COUT
4.979	0.000	tNET	FF	2	R46C38[2][A]	Mdu/u_mdu/reg0_neg_axb_8_par_cp_1/CIN
5.015	0.035	tINS	FF	1	R46C38[2][A]	Mdu/u_mdu/reg0_neg_axb_8_par_cp_1/COUT
5.015	0.000	tNET	FF	2	R46C38[2][B]	Mdu/u_mdu/reg0_neg_axb_12_par_cp_1/CIN
5.050	0.035	tINS	FF	1	R46C38[2][B]	Mdu/u_mdu/reg0_neg_axb_12_par_cp_1/COUT
5.050	0.000	tNET	FF	2	R46C39[0][A]	Mdu/u_mdu/reg0_neg_axb_16_par_cp_1/CIN
5.085	0.035	tINS	FF	1	R46C39[0][A]	Mdu/u_mdu/reg0_neg_axb_16_par_cp_1/COUT
5.085	0.000	tNET	FF	2	R46C39[0][B]	Mdu/u_mdu/reg0_neg_axb_19_par_1/CIN
5.120	0.035	tINS	FF	1	R46C39[0][B]	Mdu/u_mdu/reg0_neg_axb_19_par_1/COUT
5.120	0.000	tNET	FF	2	R46C39[1][A]	Mdu/u_mdu/reg0_neg_axb_23_par_1/CIN
5.155	0.035	tINS	FF	1	R46C39[1][A]	Mdu/u_mdu/reg0_neg_axb_23_par_1/COUT
5.155	0.000	tNET	FF	2	R46C39[1][B]	Mdu/u_mdu/reg0_neg_axb_27_par_1/CIN
5.191	0.035	tINS	FF	1	R46C39[1][B]	Mdu/u_mdu/reg0_neg_axb_27_par_1/COUT
5.191	0.000	tNET	FF	2	R46C39[2][A]	Mdu/u_mdu/reg0_neg_axb_31_par_1/CIN
5.226	0.035	tINS	FF	1	R46C39[2][A]	Mdu/u_mdu/reg0_neg_axb_31_par_1/COUT
5.226	0.000	tNET	FF	2	R46C39[2][B]	Mdu/u_mdu/reg0_neg_cry_34_0/CIN
5.261	0.035	tINS	FF	1	R46C39[2][B]	Mdu/u_mdu/reg0_neg_cry_34_0/COUT
5.261	0.000	tNET	FF	2	R46C40[0][A]	Mdu/u_mdu/reg0_neg_cry_35_0/CIN
5.296	0.035	tINS	FF	1	R46C40[0][A]	Mdu/u_mdu/reg0_neg_cry_35_0/COUT
5.296	0.000	tNET	FF	2	R46C40[0][B]	Mdu/u_mdu/reg0_neg_cry_36_0/CIN
5.331	0.035	tINS	FF	1	R46C40[0][B]	Mdu/u_mdu/reg0_neg_cry_36_0/COUT
5.331	0.000	tNET	FF	2	R46C40[1][A]	Mdu/u_mdu/reg0_neg_cry_37_0/CIN
5.367	0.035	tINS	FF	1	R46C40[1][A]	Mdu/u_mdu/reg0_neg_cry_37_0/COUT
5.367	0.000	tNET	FF	2	R46C40[1][B]	Mdu/u_mdu/reg0_neg_cry_38_0/CIN
5.402	0.035	tINS	FF	1	R46C40[1][B]	Mdu/u_mdu/reg0_neg_cry_38_0/COUT
5.402	0.000	tNET	FF	2	R46C40[2][A]	Mdu/u_mdu/reg0_neg_cry_39_0/CIN
5.437	0.035	tINS	FF	1	R46C40[2][A]	Mdu/u_mdu/reg0_neg_cry_39_0/COUT
5.437	0.000	tNET	FF	2	R46C40[2][B]	Mdu/u_mdu/reg0_neg_cry_40_0/CIN
5.472	0.035	tINS	FF	1	R46C40[2][B]	Mdu/u_mdu/reg0_neg_cry_40_0/COUT
5.472	0.000	tNET	FF	2	R46C41[0][A]	Mdu/u_mdu/reg0_neg_cry_41_0/CIN
5.507	0.035	tINS	FF	1	R46C41[0][A]	Mdu/u_mdu/reg0_neg_cry_41_0/COUT
5.507	0.000	tNET	FF	2	R46C41[0][B]	Mdu/u_mdu/reg0_neg_cry_42_0/CIN
5.543	0.035	tINS	FF	1	R46C41[0][B]	Mdu/u_mdu/reg0_neg_cry_42_0/COUT
5.543	0.000	tNET	FF	2	R46C41[1][A]	Mdu/u_mdu/reg0_neg_cry_43_0/CIN
5.578	0.035	tINS	FF	1	R46C41[1][A]	Mdu/u_mdu/reg0_neg_cry_43_0/COUT
5.578	0.000	tNET	FF	2	R46C41[1][B]	Mdu/u_mdu/reg0_neg_cry_44_0/CIN
5.613	0.035	tINS	FF	1	R46C41[1][B]	Mdu/u_mdu/reg0_neg_cry_44_0/COUT
5.613	0.000	tNET	FF	2	R46C41[2][A]	Mdu/u_mdu/reg0_neg_cry_45_0/CIN
5.648	0.035	tINS	FF	1	R46C41[2][A]	Mdu/u_mdu/reg0_neg_cry_45_0/COUT
5.648	0.000	tNET	FF	2	R46C41[2][B]	Mdu/u_mdu/reg0_neg_cry_46_0/CIN
5.683	0.035	tINS	FF	1	R46C41[2][B]	Mdu/u_mdu/reg0_neg_cry_46_0/COUT
5.683	0.000	tNET	FF	2	R46C42[0][A]	Mdu/u_mdu/reg0_neg_cry_47_0/CIN
5.719	0.035	tINS	FF	1	R46C42[0][A]	Mdu/u_mdu/reg0_neg_cry_47_0/COUT
5.719	0.000	tNET	FF	2	R46C42[0][B]	Mdu/u_mdu/reg0_neg_cry_48_0/CIN
5.754	0.035	tINS	FF	1	R46C42[0][B]	Mdu/u_mdu/reg0_neg_cry_48_0/COUT
5.754	0.000	tNET	FF	2	R46C42[1][A]	Mdu/u_mdu/reg0_neg_cry_49_0/CIN
5.789	0.035	tINS	FF	1	R46C42[1][A]	Mdu/u_mdu/reg0_neg_cry_49_0/COUT
5.789	0.000	tNET	FF	2	R46C42[1][B]	Mdu/u_mdu/reg0_neg_cry_50_0/CIN
5.824	0.035	tINS	FF	1	R46C42[1][B]	Mdu/u_mdu/reg0_neg_cry_50_0/COUT
5.824	0.000	tNET	FF	2	R46C42[2][A]	Mdu/u_mdu/reg0_neg_cry_51_0/CIN
5.859	0.035	tINS	FF	1	R46C42[2][A]	Mdu/u_mdu/reg0_neg_cry_51_0/COUT
5.859	0.000	tNET	FF	2	R46C42[2][B]	Mdu/u_mdu/reg0_neg_cry_52_0/CIN
5.895	0.035	tINS	FF	1	R46C42[2][B]	Mdu/u_mdu/reg0_neg_cry_52_0/COUT
5.895	0.000	tNET	FF	2	R46C43[0][A]	Mdu/u_mdu/reg0_neg_s_53_0/CIN
6.365	0.470	tINS	FF	1	R46C43[0][A]	Mdu/u_mdu/reg0_neg_s_53_0/SUM
8.027	1.663	tNET	FF	1	R32C30[3][A]	Mdu/u_mdu/reg0_post_swap_2[21]/I2
8.480	0.453	tINS	FF	1	R32C30[3][A]	Mdu/u_mdu/reg0_post_swap_2[21]/F
8.480	0.000	tNET	FF	1	R32C30[3][A]	Mdu/u_mdu/reg0_post_swap_4[21]/I0
8.583	0.103	tINS	FF	1	R32C30[3][A]	Mdu/u_mdu/reg0_post_swap_4[21]/O
9.002	0.419	tNET	FF	1	R35C30[1][B]	Mdu/u_mdu/reg0_post_swap_5[21]/I1
9.455	0.453	tINS	FF	2	R35C30[1][B]	Mdu/u_mdu/reg0_post_swap_5[21]/F
10.298	0.843	tNET	FF	1	R46C30[0][A]	Mdu/u_mdu/reg0_nx_cZ[21]/I1
10.760	0.462	tINS	FR	1	R46C30[0][A]	Mdu/u_mdu/reg0_nx_cZ[21]/F
10.760	0.000	tNET	RR	1	R46C30[0][A]	Mdu/u_mdu/reg0_Z[21]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	497	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R46C30[0][A]	Mdu/u_mdu/reg0_Z[21]/CLK
11.683	-0.200	tUnc				Mdu/u_mdu/reg0_Z[21]
11.648	-0.035	tSu		1	R46C30[0][A]	Mdu/u_mdu/reg0_Z[21]

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 4.016, 45.244%; route: 4.629, 52.143%; tC2Q: 0.232, 2.613%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path8

Path Summary:

Slack	0.938
Data Arrival Time	10.710
Data Required Time	11.648
From	Mdu/u_mdu/div_shift_number_Z[1]
To	Mdu/u_mdu/reg0_fast_Z[15]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.683	0.683	tINS	RR	497	IOT48[A]	clk_ibuf/O
1.883	1.201	tNET	RR	1	R51C33[1][B]	Mdu/u_mdu/div_shift_number_Z[1]/CLK
2.115	0.232	tC2Q	RF	114	R51C33[1][B]	Mdu/u_mdu/div_shift_number_Z[1]/Q
3.606	1.491	tNET	FF	1	R37C38[0][B]	Mdu/u_mdu/m3_0_03_0_0_cZ/I1
4.123	0.517	tINS	FF	5	R37C38[0][B]	Mdu/u_mdu/m3_0_03_0_0_cZ/F
4.926	0.803	tNET	FF	1	R51C38[1][B]	Mdu/u_mdu/m3_0_03_0_0_RNIV0NN/I0
5.481	0.555	tINS	FF	3	R51C38[1][B]	Mdu/u_mdu/m3_0_03_0_0_RNIV0NN/F
5.903	0.422	tNET	FF	1	R51C35[3][B]	Mdu/u_mdu/m15_2_03_0_0_cZ/I0
6.473	0.570	tINS	FR	2	R51C35[3][B]	Mdu/u_mdu/m15_2_03_0_0_cZ/F
6.475	0.003	tNET	RR	1	R51C35[3][A]	Mdu/u_mdu/m15_2_03_0_0_RNI9I0C/I0
6.992	0.517	tINS	RF	3	R51C35[3][A]	Mdu/u_mdu/m15_2_03_0_0_RNI9I0C/F
8.199	1.206	tNET	FF	1	R37C32[3][B]	Mdu/u_mdu/reg0_exe_nx_m3_xx_mm[15]/I1
8.661	0.462	tINS	FR	1	R37C32[3][B]	Mdu/u_mdu/reg0_exe_nx_m3_xx_mm[15]/F
8.662	0.001	tNET	RR	1	R37C32[1][B]	Mdu/u_mdu/un6_reg0_nx_cZ[15]_cZ/I2
9.179	0.517	tINS	RF	2	R37C32[1][B]	Mdu/u_mdu/un6_reg0_nx_cZ[15]_cZ/F
10.140	0.961	tNET	FF	1	R42C35[0][A]	Mdu/u_mdu/reg0_nx_fast_cZ[15]/I3
10.710	0.570	tINS	FR	1	R42C35[0][A]	Mdu/u_mdu/reg0_nx_fast_cZ[15]/F
10.710	0.000	tNET	RR	1	R42C35[0][A]	Mdu/u_mdu/reg0_fast_Z[15]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	497	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R42C35[0][A]	Mdu/u_mdu/reg0_fast_Z[15]/CLK
11.683	-0.200	tUnc				Mdu/u_mdu/reg0_fast_Z[15]
11.648	-0.035	tSu		1	R42C35[0][A]	Mdu/u_mdu/reg0_fast_Z[15]

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 3.708, 42.009%; route: 4.887, 55.362%; tC2Q: 0.232, 2.628%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path9

Path Summary:

Slack	0.938
Data Arrival Time	10.710
Data Required Time	11.648
From	Mdu/u_mdu/div_shift_number_Z[1]
To	Mdu/u_mdu/reg0_Z[15]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.683	0.683	tINS	RR	497	IOT48[A]	clk_ibuf/O
1.883	1.201	tNET	RR	1	R51C33[1][B]	Mdu/u_mdu/div_shift_number_Z[1]/CLK
2.115	0.232	tC2Q	RF	114	R51C33[1][B]	Mdu/u_mdu/div_shift_number_Z[1]/Q
3.606	1.491	tNET	FF	1	R37C38[0][B]	Mdu/u_mdu/m3_0_03_0_0_cZ/I1
4.123	0.517	tINS	FF	5	R37C38[0][B]	Mdu/u_mdu/m3_0_03_0_0_cZ/F
4.926	0.803	tNET	FF	1	R51C38[1][B]	Mdu/u_mdu/m3_0_03_0_0_RNIV0NN/I0
5.481	0.555	tINS	FF	3	R51C38[1][B]	Mdu/u_mdu/m3_0_03_0_0_RNIV0NN/F
5.903	0.422	tNET	FF	1	R51C35[3][B]	Mdu/u_mdu/m15_2_03_0_0_cZ/I0
6.473	0.570	tINS	FR	2	R51C35[3][B]	Mdu/u_mdu/m15_2_03_0_0_cZ/F
6.475	0.003	tNET	RR	1	R51C35[3][A]	Mdu/u_mdu/m15_2_03_0_0_RNI9I0C/I0
6.992	0.517	tINS	RF	3	R51C35[3][A]	Mdu/u_mdu/m15_2_03_0_0_RNI9I0C/F
8.199	1.206	tNET	FF	1	R37C32[3][B]	Mdu/u_mdu/reg0_exe_nx_m3_xx_mm[15]/I1
8.661	0.462	tINS	FR	1	R37C32[3][B]	Mdu/u_mdu/reg0_exe_nx_m3_xx_mm[15]/F
8.662	0.001	tNET	RR	1	R37C32[1][B]	Mdu/u_mdu/un6_reg0_nx_cZ[15]_cZ/I2
9.179	0.517	tINS	RF	2	R37C32[1][B]	Mdu/u_mdu/un6_reg0_nx_cZ[15]_cZ/F
10.140	0.961	tNET	FF	1	R42C35[1][B]	Mdu/u_mdu/reg0_nx_cZ[15]/I3
10.710	0.570	tINS	FR	1	R42C35[1][B]	Mdu/u_mdu/reg0_nx_cZ[15]/F
10.710	0.000	tNET	RR	1	R42C35[1][B]	Mdu/u_mdu/reg0_Z[15]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	497	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R42C35[1][B]	Mdu/u_mdu/reg0_Z[15]/CLK
11.683	-0.200	tUnc				Mdu/u_mdu/reg0_Z[15]
11.648	-0.035	tSu		1	R42C35[1][B]	Mdu/u_mdu/reg0_Z[15]

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 3.708, 42.009%; route: 4.887, 55.362%; tC2Q: 0.232, 2.628%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path10

Path Summary:

Slack	0.948
Data Arrival Time	10.700
Data Required Time	11.648
From	Mdu/u_mdu/reg0_Z[11]
To	Mdu/u_mdu/reg0_fast_Z[28]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.683	0.683	tINS	RR	497	IOT48[A]	clk_ibuf/O
1.883	1.201	tNET	RR	1	R33C39[1][A]	Mdu/u_mdu/reg0_Z[11]/CLK
2.115	0.232	tC2Q	RF	10	R33C39[1][A]	Mdu/u_mdu/reg0_Z[11]/Q
3.599	1.484	tNET	FF	1	R52C33[0][B]	Mdu/u_mdu/m12_0_03_1_cZ/I3
4.169	0.570	tINS	FR	1	R52C33[0][B]	Mdu/u_mdu/m12_0_03_1_cZ/F
4.170	0.001	tNET	RR	1	R52C33[2][A]	Mdu/u_mdu/m12_0_03_cZ/I1
4.725	0.555	tINS	RF	4	R52C33[2][A]	Mdu/u_mdu/m12_0_03_cZ/F
5.147	0.422	tNET	FF	1	R53C34[1][A]	Mdu/u_mdu/m12_2_03_m1_e_1_cZ/I3
5.664	0.517	tINS	FF	2	R53C34[1][A]	Mdu/u_mdu/m12_2_03_m1_e_1_cZ/F
6.086	0.422	tNET	FF	1	R52C35[3][B]	Mdu/u_mdu/m12_2_03_m1_e_0_RNI7HT5/I1
6.539	0.453	tINS	FF	3	R52C35[3][B]	Mdu/u_mdu/m12_2_03_m1_e_0_RNI7HT5/F
7.354	0.815	tNET	FF	1	R55C33[3][A]	Mdu/u_mdu/m28_4_01_cZ/I1
7.871	0.517	tINS	FF	1	R55C33[3][A]	Mdu/u_mdu/m28_4_01_cZ/F
8.268	0.397	tNET	FF	1	R53C33[2][A]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[28]/I2
8.721	0.453	tINS	FF	1	R53C33[2][A]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[28]/F
9.405	0.684	tNET	FF	1	R46C33[3][B]	Mdu/u_mdu/reg0_exe_nx_cZ[28]/I3
9.954	0.549	tINS	FR	2	R46C33[3][B]	Mdu/u_mdu/reg0_exe_nx_cZ[28]/F
10.130	0.176	tNET	RR	1	R46C34[0][B]	Mdu/u_mdu/reg0_nx_fast_cZ[28]/I0
10.700	0.570	tINS	RR	1	R46C34[0][B]	Mdu/u_mdu/reg0_nx_fast_cZ[28]/F
10.700	0.000	tNET	RR	1	R46C34[0][B]	Mdu/u_mdu/reg0_fast_Z[28]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	497	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R46C34[0][B]	Mdu/u_mdu/reg0_fast_Z[28]/CLK
11.683	-0.200	tUnc				Mdu/u_mdu/reg0_fast_Z[28]
11.648	-0.035	tSu		1	R46C34[0][B]	Mdu/u_mdu/reg0_fast_Z[28]

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	8
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 4.184, 47.456%; route: 4.401, 49.912%; tC2Q: 0.232, 2.631%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path11

Path Summary:

Slack	0.948
Data Arrival Time	10.700
Data Required Time	11.648
From	Mdu/u_mdu/reg0_Z[11]
To	Mdu/u_mdu/reg0_Z[28]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.683	0.683	tINS	RR	497	IOT48[A]	clk_ibuf/O
1.883	1.201	tNET	RR	1	R33C39[1][A]	Mdu/u_mdu/reg0_Z[11]/CLK
2.115	0.232	tC2Q	RF	10	R33C39[1][A]	Mdu/u_mdu/reg0_Z[11]/Q
3.599	1.484	tNET	FF	1	R52C33[0][B]	Mdu/u_mdu/m12_0_03_1_cZ/I3
4.169	0.570	tINS	FR	1	R52C33[0][B]	Mdu/u_mdu/m12_0_03_1_cZ/F
4.170	0.001	tNET	RR	1	R52C33[2][A]	Mdu/u_mdu/m12_0_03_cZ/I1
4.725	0.555	tINS	RF	4	R52C33[2][A]	Mdu/u_mdu/m12_0_03_cZ/F
5.147	0.422	tNET	FF	1	R53C34[1][A]	Mdu/u_mdu/m12_2_03_m1_e_1_cZ/I3
5.664	0.517	tINS	FF	2	R53C34[1][A]	Mdu/u_mdu/m12_2_03_m1_e_1_cZ/F
6.086	0.422	tNET	FF	1	R52C35[3][B]	Mdu/u_mdu/m12_2_03_m1_e_0_RNI7HT5/I1
6.539	0.453	tINS	FF	3	R52C35[3][B]	Mdu/u_mdu/m12_2_03_m1_e_0_RNI7HT5/F
7.354	0.815	tNET	FF	1	R55C33[3][A]	Mdu/u_mdu/m28_4_01_cZ/I1
7.871	0.517	tINS	FF	1	R55C33[3][A]	Mdu/u_mdu/m28_4_01_cZ/F
8.268	0.397	tNET	FF	1	R53C33[2][A]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[28]/I2
8.721	0.453	tINS	FF	1	R53C33[2][A]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[28]/F
9.405	0.684	tNET	FF	1	R46C33[3][B]	Mdu/u_mdu/reg0_exe_nx_cZ[28]/I3
9.954	0.549	tINS	FR	2	R46C33[3][B]	Mdu/u_mdu/reg0_exe_nx_cZ[28]/F
10.130	0.176	tNET	RR	1	R46C34[0][A]	Mdu/u_mdu/reg0_nx_cZ[28]/I0
10.700	0.570	tINS	RR	1	R46C34[0][A]	Mdu/u_mdu/reg0_nx_cZ[28]/F
10.700	0.000	tNET	RR	1	R46C34[0][A]	Mdu/u_mdu/reg0_Z[28]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	497	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R46C34[0][A]	Mdu/u_mdu/reg0_Z[28]/CLK
11.683	-0.200	tUnc				Mdu/u_mdu/reg0_Z[28]
11.648	-0.035	tSu		1	R46C34[0][A]	Mdu/u_mdu/reg0_Z[28]

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	8
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 4.184, 47.456%; route: 4.401, 49.912%; tC2Q: 0.232, 2.631%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path12

Path Summary:

Slack	1.005
Data Arrival Time	10.643
Data Required Time	11.648
From	Mdu/u_mdu/div_shift_number_Z[1]
To	Mdu/u_mdu/reg0_Z[54]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.683	0.683	tINS	RR	497	IOT48[A]	clk_ibuf/O
1.883	1.201	tNET	RR	1	R51C33[1][B]	Mdu/u_mdu/div_shift_number_Z[1]/CLK
2.115	0.232	tC2Q	RF	114	R51C33[1][B]	Mdu/u_mdu/div_shift_number_Z[1]/Q
3.802	1.686	tNET	FF	1	R35C33[2][A]	Mdu/u_mdu/m2_0_03_m1_e_1_cZ/I1
4.351	0.549	tINS	FR	1	R35C33[2][A]	Mdu/u_mdu/m2_0_03_m1_e_1_cZ/F
4.352	0.001	tNET	RR	1	R35C33[2][B]	Mdu/u_mdu/m2_0_03_m1_e/I2
4.805	0.453	tINS	RF	6	R35C33[2][B]	Mdu/u_mdu/m2_0_03_m1_e/F
5.531	0.726	tNET	FF	1	R51C33[3][A]	Mdu/u_mdu/m6_2_03_cZ/I2
5.902	0.371	tINS	FF	4	R51C33[3][A]	Mdu/u_mdu/m6_2_03_cZ/F
7.060	1.158	tNET	FF	1	R47C39[0][B]	Mdu/u_mdu/m54_4_03_0_0_cZ/I0
7.577	0.517	tINS	FF	1	R47C39[0][B]	Mdu/u_mdu/m54_4_03_0_0_cZ/F
8.476	0.899	tNET	FF	1	R46C39[3][A]	Mdu/u_mdu/reg0_exe_nx_m0_cZ[54]/I1
9.031	0.555	tINS	FF	1	R46C39[3][A]	Mdu/u_mdu/reg0_exe_nx_m0_cZ[54]/F
9.031	0.000	tNET	FF	1	R46C39[3][A]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[54]/I0
9.134	0.103	tINS	FF	1	R46C39[3][A]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[54]/O
10.094	0.961	tNET	FF	1	R30C42[0][A]	Mdu/u_mdu/reg0_nx_0[54]/I2
10.643	0.549	tINS	FR	1	R30C42[0][A]	Mdu/u_mdu/reg0_nx_0[54]/F
10.643	0.000	tNET	RR	1	R30C42[0][A]	Mdu/u_mdu/reg0_Z[54]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	497	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R30C42[0][A]	Mdu/u_mdu/reg0_Z[54]/CLK
11.683	-0.200	tUnc				Mdu/u_mdu/reg0_Z[54]
11.648	-0.035	tSu		1	R30C42[0][A]	Mdu/u_mdu/reg0_Z[54]

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 3.097, 35.353%; route: 5.431, 61.999%; tC2Q: 0.232, 2.648%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path13

Path Summary:

Slack	1.038
Data Arrival Time	10.610
Data Required Time	11.648
From	Mdu/u_mdu/div_shift_number_Z[1]
To	Mdu/u_mdu/reg0_Z[58]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.683	0.683	tINS	RR	497	IOT48[A]	clk_ibuf/O
1.883	1.201	tNET	RR	1	R51C33[1][B]	Mdu/u_mdu/div_shift_number_Z[1]/CLK
2.115	0.232	tC2Q	RF	114	R51C33[1][B]	Mdu/u_mdu/div_shift_number_Z[1]/Q
3.802	1.686	tNET	FF	1	R35C33[2][A]	Mdu/u_mdu/m2_0_03_m1_e_1_cZ/I1
4.351	0.549	tINS	FR	1	R35C33[2][A]	Mdu/u_mdu/m2_0_03_m1_e_1_cZ/F
4.352	0.001	tNET	RR	1	R35C33[2][B]	Mdu/u_mdu/m2_0_03_m1_e/I2
4.805	0.453	tINS	RF	6	R35C33[2][B]	Mdu/u_mdu/m2_0_03_m1_e/F
5.540	0.735	tNET	FF	1	R52C33[3][A]	Mdu/u_mdu/m10_2_03_m1_e_1_cZ/I1
6.002	0.462	tINS	FR	1	R52C33[3][A]	Mdu/u_mdu/m10_2_03_m1_e_1_cZ/F
6.004	0.001	tNET	RR	1	R52C33[3][B]	Mdu/u_mdu/m10_2_03_m1_e/I3
6.457	0.453	tINS	RF	4	R52C33[3][B]	Mdu/u_mdu/m10_2_03_m1_e/F
7.360	0.903	tNET	FF	1	R49C36[2][A]	Mdu/u_mdu/m58_4_03_0_0_cZ/I0
7.813	0.453	tINS	FF	1	R49C36[2][A]	Mdu/u_mdu/m58_4_03_0_0_cZ/F
8.210	0.397	tNET	FF	1	R47C36[3][A]	Mdu/u_mdu/reg0_exe_nx_m0_cZ[58]/I1
8.727	0.517	tINS	FF	1	R47C36[3][A]	Mdu/u_mdu/reg0_exe_nx_m0_cZ[58]/F
8.727	0.000	tNET	FF	1	R47C36[3][A]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[58]/I0
8.830	0.103	tINS	FF	1	R47C36[3][A]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[58]/O
10.061	1.232	tNET	FF	1	R31C42[2][B]	Mdu/u_mdu/reg0_nx_cZ[58]/I0
10.610	0.549	tINS	FR	1	R31C42[2][B]	Mdu/u_mdu/reg0_nx_cZ[58]/F
10.610	0.000	tNET	RR	1	R31C42[2][B]	Mdu/u_mdu/reg0_Z[58]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	497	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R31C42[2][B]	Mdu/u_mdu/reg0_Z[58]/CLK
11.683	-0.200	tUnc				Mdu/u_mdu/reg0_Z[58]
11.648	-0.035	tSu		1	R31C42[2][B]	Mdu/u_mdu/reg0_Z[58]

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	8
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 3.539, 40.552%; route: 4.956, 56.790%; tC2Q: 0.232, 2.658%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path14

Path Summary:

Slack	1.038
Data Arrival Time	10.610
Data Required Time	11.648
From	Mdu/u_mdu/reg0_Z[11]
To	Mdu/u_mdu/reg0_Z[56]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.683	0.683	tINS	RR	497	IOT48[A]	clk_ibuf/O
1.883	1.201	tNET	RR	1	R33C39[1][A]	Mdu/u_mdu/reg0_Z[11]/CLK
2.115	0.232	tC2Q	RF	10	R33C39[1][A]	Mdu/u_mdu/reg0_Z[11]/Q
3.599	1.484	tNET	FF	1	R52C33[0][B]	Mdu/u_mdu/m12_0_03_1_cZ/I3
4.169	0.570	tINS	FR	1	R52C33[0][B]	Mdu/u_mdu/m12_0_03_1_cZ/F
4.170	0.001	tNET	RR	1	R52C33[2][A]	Mdu/u_mdu/m12_0_03_cZ/I1
4.725	0.555	tINS	RF	4	R52C33[2][A]	Mdu/u_mdu/m12_0_03_cZ/F
5.147	0.422	tNET	FF	1	R55C33[2][B]	Mdu/u_mdu/m24_2_03_0_0_cZ/I1
5.609	0.462	tINS	FR	2	R55C33[2][B]	Mdu/u_mdu/m24_2_03_0_0_cZ/F
5.783	0.174	tNET	RR	1	R55C34[1][B]	Mdu/u_mdu/m24_2_03_0_0_RNI9KIK/I0
6.338	0.555	tINS	RF	2	R55C34[1][B]	Mdu/u_mdu/m24_2_03_0_0_RNI9KIK/F
7.103	0.765	tNET	FF	1	R49C36[3][B]	Mdu/u_mdu/m56_4_03_0_0_cZ/I1
7.658	0.555	tINS	FF	1	R49C36[3][B]	Mdu/u_mdu/m56_4_03_0_0_cZ/F
8.314	0.656	tNET	FF	1	R47C39[1][A]	Mdu/u_mdu/reg0_exe_nx_m0_cZ[56]/I1
8.831	0.517	tINS	FF	1	R47C39[1][A]	Mdu/u_mdu/reg0_exe_nx_m0_cZ[56]/F
8.831	0.000	tNET	FF	1	R47C39[1][A]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[56]/I0
8.934	0.103	tINS	FF	1	R47C39[1][A]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[56]/O
10.061	1.127	tNET	FF	1	R33C41[2][B]	Mdu/u_mdu/reg0_nx_cZ[56]/I0
10.610	0.549	tINS	FR	1	R33C41[2][B]	Mdu/u_mdu/reg0_nx_cZ[56]/F
10.610	0.000	tNET	RR	1	R33C41[2][B]	Mdu/u_mdu/reg0_Z[56]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	497	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R33C41[2][B]	Mdu/u_mdu/reg0_Z[56]/CLK
11.683	-0.200	tUnc				Mdu/u_mdu/reg0_Z[56]
11.648	-0.035	tSu		1	R33C41[2][B]	Mdu/u_mdu/reg0_Z[56]

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	8
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 3.866, 44.301%; route: 4.629, 53.041%; tC2Q: 0.232, 2.658%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path15

Path Summary:

Slack	1.050
Data Arrival Time	10.598
Data Required Time	11.648
From	Mdu/u_mdu/div_shift_number_Z[1]
To	Mdu/u_mdu/reg0_22_rep1_Z
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.683	0.683	tINS	RR	497	IOT48[A]	clk_ibuf/O
1.883	1.201	tNET	RR	1	R51C33[1][B]	Mdu/u_mdu/div_shift_number_Z[1]/CLK
2.115	0.232	tC2Q	RF	114	R51C33[1][B]	Mdu/u_mdu/div_shift_number_Z[1]/Q
3.802	1.686	tNET	FF	1	R35C33[2][A]	Mdu/u_mdu/m2_0_03_m1_e_1_cZ/I1
4.351	0.549	tINS	FR	1	R35C33[2][A]	Mdu/u_mdu/m2_0_03_m1_e_1_cZ/F
4.352	0.001	tNET	RR	1	R35C33[2][B]	Mdu/u_mdu/m2_0_03_m1_e/I2
4.805	0.453	tINS	RF	6	R35C33[2][B]	Mdu/u_mdu/m2_0_03_m1_e/F
5.531	0.726	tNET	FF	1	R51C33[3][A]	Mdu/u_mdu/m6_2_03_cZ/I2
5.902	0.371	tINS	FF	4	R51C33[3][A]	Mdu/u_mdu/m6_2_03_cZ/F
6.572	0.669	tNET	FF	1	R48C34[0][A]	Mdu/u_mdu/m22_4_01_cZ/I1
7.127	0.555	tINS	FF	1	R48C34[0][A]	Mdu/u_mdu/m22_4_01_cZ/F
7.961	0.834	tNET	FF	1	R40C31[3][B]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[22]/I2
8.531	0.570	tINS	FR	1	R40C31[3][B]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[22]/F
8.703	0.172	tNET	RR	1	R39C31[1][B]	Mdu/u_mdu/reg0_exe_nx_cZ[22]/I3
9.258	0.555	tINS	RF	3	R39C31[1][B]	Mdu/u_mdu/reg0_exe_nx_cZ[22]/F
10.028	0.770	tNET	FF	1	R37C37[0][A]	Mdu/u_mdu/reg0_nx_rep1_cZ[22]/I0
10.598	0.570	tINS	FR	1	R37C37[0][A]	Mdu/u_mdu/reg0_nx_rep1_cZ[22]/F
10.598	0.000	tNET	RR	1	R37C37[0][A]	Mdu/u_mdu/reg0_22_rep1_Z/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	497	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R37C37[0][A]	Mdu/u_mdu/reg0_22_rep1_Z/CLK
11.683	-0.200	tUnc				Mdu/u_mdu/reg0_22_rep1_Z
11.648	-0.035	tSu		1	R37C37[0][A]	Mdu/u_mdu/reg0_22_rep1_Z

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 3.623, 41.572%; route: 4.860, 55.765%; tC2Q: 0.232, 2.662%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path16

Path Summary:

Slack	1.083
Data Arrival Time	10.566
Data Required Time	11.648
From	Mdu/u_mdu/div_shift_number_Z[1]
To	Mdu/u_mdu/reg0_Z[63]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.683	0.683	tINS	RR	497	IOT48[A]	clk_ibuf/O
1.883	1.201	tNET	RR	1	R51C33[1][B]	Mdu/u_mdu/div_shift_number_Z[1]/CLK
2.115	0.232	tC2Q	RF	114	R51C33[1][B]	Mdu/u_mdu/div_shift_number_Z[1]/Q
3.606	1.491	tNET	FF	1	R37C38[0][B]	Mdu/u_mdu/m3_0_03_0_0_cZ/I1
4.123	0.517	tINS	FF	5	R37C38[0][B]	Mdu/u_mdu/m3_0_03_0_0_cZ/F
4.926	0.803	tNET	FF	1	R51C38[1][B]	Mdu/u_mdu/m3_0_03_0_0_RNIV0NN/I0
5.481	0.555	tINS	FF	3	R51C38[1][B]	Mdu/u_mdu/m3_0_03_0_0_RNIV0NN/F
5.903	0.422	tNET	FF	1	R51C35[3][B]	Mdu/u_mdu/m15_2_03_0_0_cZ/I0
6.473	0.570	tINS	FR	2	R51C35[3][B]	Mdu/u_mdu/m15_2_03_0_0_cZ/F
6.475	0.003	tNET	RR	1	R51C35[3][A]	Mdu/u_mdu/m15_2_03_0_0_RNI9I0C/I0
6.992	0.517	tINS	RF	3	R51C35[3][A]	Mdu/u_mdu/m15_2_03_0_0_RNI9I0C/F
7.685	0.693	tNET	FF	1	R46C36[1][B]	Mdu/u_mdu/m63_4_03_0_0_cZ/I0
8.138	0.453	tINS	FF	1	R46C36[1][B]	Mdu/u_mdu/m63_4_03_0_0_cZ/F
8.794	0.656	tNET	FF	1	R43C37[3][A]	Mdu/u_mdu/reg0_exe_nx_m0_cZ[63]/I1
9.247	0.453	tINS	FF	1	R43C37[3][A]	Mdu/u_mdu/reg0_exe_nx_m0_cZ[63]/F
9.247	0.000	tNET	FF	1	R43C37[3][A]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[63]/I0
9.350	0.103	tINS	FF	1	R43C37[3][A]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[63]/O
9.996	0.645	tNET	FF	1	R41C38[2][A]	Mdu/u_mdu/reg0_nx_0[63]/I2
10.566	0.570	tINS	FR	1	R41C38[2][A]	Mdu/u_mdu/reg0_nx_0[63]/F
10.566	0.000	tNET	RR	1	R41C38[2][A]	Mdu/u_mdu/reg0_Z[63]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	497	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R41C38[2][A]	Mdu/u_mdu/reg0_Z[63]/CLK
11.683	-0.200	tUnc				Mdu/u_mdu/reg0_Z[63]
11.648	-0.035	tSu		1	R41C38[2][A]	Mdu/u_mdu/reg0_Z[63]

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	8
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 3.738, 43.053%; route: 4.712, 54.275%; tC2Q: 0.232, 2.672%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path17

Path Summary:

Slack	1.108
Data Arrival Time	10.541
Data Required Time	11.648
From	Mdu/u_mdu/reg0_fast_Z[3]
To	Mdu/u_mdu/reg0_fast_Z[20]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.683	0.683	tINS	RR	497	IOT48[A]	clk_ibuf/O
1.883	1.201	tNET	RR	1	R34C30[2][A]	Mdu/u_mdu/reg0_fast_Z[3]/CLK
2.115	0.232	tC2Q	RF	7	R34C30[2][A]	Mdu/u_mdu/reg0_fast_Z[3]/Q
3.212	1.097	tNET	FF	1	R37C38[3][B]	Mdu/u_mdu/reg0_neg_axb_0_par_0_cp_0_cZ/I3
3.767	0.555	tINS	FF	1	R37C38[3][B]	Mdu/u_mdu/reg0_neg_axb_0_par_0_cp_0_cZ/F
4.374	0.607	tNET	FF	2	R46C38[1][A]	Mdu/u_mdu/reg0_neg_axb_0_par_cp_0_0/I0
4.944	0.570	tINS	FR	1	R46C38[1][A]	Mdu/u_mdu/reg0_neg_axb_0_par_cp_0_0/COUT
4.944	0.000	tNET	RR	2	R46C38[1][B]	Mdu/u_mdu/reg0_neg_axb_4_par_cp_0_0/CIN
4.979	0.035	tINS	RF	1	R46C38[1][B]	Mdu/u_mdu/reg0_neg_axb_4_par_cp_0_0/COUT
4.979	0.000	tNET	FF	2	R46C38[2][A]	Mdu/u_mdu/reg0_neg_axb_8_par_cp_1/CIN
5.015	0.035	tINS	FF	1	R46C38[2][A]	Mdu/u_mdu/reg0_neg_axb_8_par_cp_1/COUT
5.015	0.000	tNET	FF	2	R46C38[2][B]	Mdu/u_mdu/reg0_neg_axb_12_par_cp_1/CIN
5.050	0.035	tINS	FF	1	R46C38[2][B]	Mdu/u_mdu/reg0_neg_axb_12_par_cp_1/COUT
5.050	0.000	tNET	FF	2	R46C39[0][A]	Mdu/u_mdu/reg0_neg_axb_16_par_cp_1/CIN
5.085	0.035	tINS	FF	1	R46C39[0][A]	Mdu/u_mdu/reg0_neg_axb_16_par_cp_1/COUT
5.085	0.000	tNET	FF	2	R46C39[0][B]	Mdu/u_mdu/reg0_neg_axb_19_par_1/CIN
5.120	0.035	tINS	FF	1	R46C39[0][B]	Mdu/u_mdu/reg0_neg_axb_19_par_1/COUT
5.120	0.000	tNET	FF	2	R46C39[1][A]	Mdu/u_mdu/reg0_neg_axb_23_par_1/CIN
5.155	0.035	tINS	FF	1	R46C39[1][A]	Mdu/u_mdu/reg0_neg_axb_23_par_1/COUT
5.155	0.000	tNET	FF	2	R46C39[1][B]	Mdu/u_mdu/reg0_neg_axb_27_par_1/CIN
5.191	0.035	tINS	FF	1	R46C39[1][B]	Mdu/u_mdu/reg0_neg_axb_27_par_1/COUT
5.191	0.000	tNET	FF	2	R46C39[2][A]	Mdu/u_mdu/reg0_neg_axb_31_par_1/CIN
5.226	0.035	tINS	FF	1	R46C39[2][A]	Mdu/u_mdu/reg0_neg_axb_31_par_1/COUT
5.226	0.000	tNET	FF	2	R46C39[2][B]	Mdu/u_mdu/reg0_neg_cry_34_0/CIN
5.261	0.035	tINS	FF	1	R46C39[2][B]	Mdu/u_mdu/reg0_neg_cry_34_0/COUT
5.261	0.000	tNET	FF	2	R46C40[0][A]	Mdu/u_mdu/reg0_neg_cry_35_0/CIN
5.296	0.035	tINS	FF	1	R46C40[0][A]	Mdu/u_mdu/reg0_neg_cry_35_0/COUT
5.296	0.000	tNET	FF	2	R46C40[0][B]	Mdu/u_mdu/reg0_neg_cry_36_0/CIN
5.331	0.035	tINS	FF	1	R46C40[0][B]	Mdu/u_mdu/reg0_neg_cry_36_0/COUT
5.331	0.000	tNET	FF	2	R46C40[1][A]	Mdu/u_mdu/reg0_neg_cry_37_0/CIN
5.367	0.035	tINS	FF	1	R46C40[1][A]	Mdu/u_mdu/reg0_neg_cry_37_0/COUT
5.367	0.000	tNET	FF	2	R46C40[1][B]	Mdu/u_mdu/reg0_neg_cry_38_0/CIN
5.402	0.035	tINS	FF	1	R46C40[1][B]	Mdu/u_mdu/reg0_neg_cry_38_0/COUT
5.402	0.000	tNET	FF	2	R46C40[2][A]	Mdu/u_mdu/reg0_neg_cry_39_0/CIN
5.437	0.035	tINS	FF	1	R46C40[2][A]	Mdu/u_mdu/reg0_neg_cry_39_0/COUT
5.437	0.000	tNET	FF	2	R46C40[2][B]	Mdu/u_mdu/reg0_neg_cry_40_0/CIN
5.472	0.035	tINS	FF	1	R46C40[2][B]	Mdu/u_mdu/reg0_neg_cry_40_0/COUT
5.472	0.000	tNET	FF	2	R46C41[0][A]	Mdu/u_mdu/reg0_neg_cry_41_0/CIN
5.507	0.035	tINS	FF	1	R46C41[0][A]	Mdu/u_mdu/reg0_neg_cry_41_0/COUT
5.507	0.000	tNET	FF	2	R46C41[0][B]	Mdu/u_mdu/reg0_neg_cry_42_0/CIN
5.543	0.035	tINS	FF	1	R46C41[0][B]	Mdu/u_mdu/reg0_neg_cry_42_0/COUT
5.543	0.000	tNET	FF	2	R46C41[1][A]	Mdu/u_mdu/reg0_neg_cry_43_0/CIN
5.578	0.035	tINS	FF	1	R46C41[1][A]	Mdu/u_mdu/reg0_neg_cry_43_0/COUT
5.578	0.000	tNET	FF	2	R46C41[1][B]	Mdu/u_mdu/reg0_neg_cry_44_0/CIN
5.613	0.035	tINS	FF	1	R46C41[1][B]	Mdu/u_mdu/reg0_neg_cry_44_0/COUT
5.613	0.000	tNET	FF	2	R46C41[2][A]	Mdu/u_mdu/reg0_neg_cry_45_0/CIN
5.648	0.035	tINS	FF	1	R46C41[2][A]	Mdu/u_mdu/reg0_neg_cry_45_0/COUT
5.648	0.000	tNET	FF	2	R46C41[2][B]	Mdu/u_mdu/reg0_neg_cry_46_0/CIN
5.683	0.035	tINS	FF	1	R46C41[2][B]	Mdu/u_mdu/reg0_neg_cry_46_0/COUT
5.683	0.000	tNET	FF	2	R46C42[0][A]	Mdu/u_mdu/reg0_neg_cry_47_0/CIN
5.719	0.035	tINS	FF	1	R46C42[0][A]	Mdu/u_mdu/reg0_neg_cry_47_0/COUT
5.719	0.000	tNET	FF	2	R46C42[0][B]	Mdu/u_mdu/reg0_neg_cry_48_0/CIN
5.754	0.035	tINS	FF	1	R46C42[0][B]	Mdu/u_mdu/reg0_neg_cry_48_0/COUT
5.754	0.000	tNET	FF	2	R46C42[1][A]	Mdu/u_mdu/reg0_neg_cry_49_0/CIN
5.789	0.035	tINS	FF	1	R46C42[1][A]	Mdu/u_mdu/reg0_neg_cry_49_0/COUT
5.789	0.000	tNET	FF	2	R46C42[1][B]	Mdu/u_mdu/reg0_neg_cry_50_0/CIN
5.824	0.035	tINS	FF	1	R46C42[1][B]	Mdu/u_mdu/reg0_neg_cry_50_0/COUT
5.824	0.000	tNET	FF	2	R46C42[2][A]	Mdu/u_mdu/reg0_neg_cry_51_0/CIN
5.859	0.035	tINS	FF	1	R46C42[2][A]	Mdu/u_mdu/reg0_neg_cry_51_0/COUT
5.859	0.000	tNET	FF	2	R46C42[2][B]	Mdu/u_mdu/reg0_neg_cry_52_0/CIN
6.329	0.470	tINS	FF	1	R46C42[2][B]	Mdu/u_mdu/reg0_neg_cry_52_0/SUM
7.479	1.149	tNET	FF	1	R29C37[3][A]	Mdu/u_mdu/reg0_post_swap_2[20]/I2
8.049	0.570	tINS	FR	1	R29C37[3][A]	Mdu/u_mdu/reg0_post_swap_2[20]/F
8.049	0.000	tNET	RR	1	R29C37[3][A]	Mdu/u_mdu/reg0_post_swap_4[20]/I0
8.154	0.105	tINS	RR	2	R29C37[3][A]	Mdu/u_mdu/reg0_post_swap_4[20]/O
8.335	0.181	tNET	RR	1	R29C37[1][A]	Mdu/u_mdu/un11_reg0_nx_cZ[20]_cZ/I1
8.788	0.453	tINS	RF	2	R29C37[1][A]	Mdu/u_mdu/un11_reg0_nx_cZ[20]_cZ/F
9.992	1.203	tNET	FF	1	R43C34[0][A]	Mdu/u_mdu/reg0_nx_fast_cZ[20]/I3
10.541	0.549	tINS	FR	1	R43C34[0][A]	Mdu/u_mdu/reg0_nx_fast_cZ[20]/F
10.541	0.000	tNET	RR	1	R43C34[0][A]	Mdu/u_mdu/reg0_fast_Z[20]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	497	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R43C34[0][A]	Mdu/u_mdu/reg0_fast_Z[20]/CLK
11.683	-0.200	tUnc				Mdu/u_mdu/reg0_fast_Z[20]
11.648	-0.035	tSu		1	R43C34[0][A]	Mdu/u_mdu/reg0_fast_Z[20]

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 4.187, 48.366%; route: 4.238, 48.954%; tC2Q: 0.232, 2.680%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path18

Path Summary:

Slack	1.108
Data Arrival Time	10.541
Data Required Time	11.648
From	Mdu/u_mdu/reg0_fast_Z[3]
To	Mdu/u_mdu/reg0_Z[20]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.683	0.683	tINS	RR	497	IOT48[A]	clk_ibuf/O
1.883	1.201	tNET	RR	1	R34C30[2][A]	Mdu/u_mdu/reg0_fast_Z[3]/CLK
2.115	0.232	tC2Q	RF	7	R34C30[2][A]	Mdu/u_mdu/reg0_fast_Z[3]/Q
3.212	1.097	tNET	FF	1	R37C38[3][B]	Mdu/u_mdu/reg0_neg_axb_0_par_0_cp_0_cZ/I3
3.767	0.555	tINS	FF	1	R37C38[3][B]	Mdu/u_mdu/reg0_neg_axb_0_par_0_cp_0_cZ/F
4.374	0.607	tNET	FF	2	R46C38[1][A]	Mdu/u_mdu/reg0_neg_axb_0_par_cp_0_0/I0
4.944	0.570	tINS	FR	1	R46C38[1][A]	Mdu/u_mdu/reg0_neg_axb_0_par_cp_0_0/COUT
4.944	0.000	tNET	RR	2	R46C38[1][B]	Mdu/u_mdu/reg0_neg_axb_4_par_cp_0_0/CIN
4.979	0.035	tINS	RF	1	R46C38[1][B]	Mdu/u_mdu/reg0_neg_axb_4_par_cp_0_0/COUT
4.979	0.000	tNET	FF	2	R46C38[2][A]	Mdu/u_mdu/reg0_neg_axb_8_par_cp_1/CIN
5.015	0.035	tINS	FF	1	R46C38[2][A]	Mdu/u_mdu/reg0_neg_axb_8_par_cp_1/COUT
5.015	0.000	tNET	FF	2	R46C38[2][B]	Mdu/u_mdu/reg0_neg_axb_12_par_cp_1/CIN
5.050	0.035	tINS	FF	1	R46C38[2][B]	Mdu/u_mdu/reg0_neg_axb_12_par_cp_1/COUT
5.050	0.000	tNET	FF	2	R46C39[0][A]	Mdu/u_mdu/reg0_neg_axb_16_par_cp_1/CIN
5.085	0.035	tINS	FF	1	R46C39[0][A]	Mdu/u_mdu/reg0_neg_axb_16_par_cp_1/COUT
5.085	0.000	tNET	FF	2	R46C39[0][B]	Mdu/u_mdu/reg0_neg_axb_19_par_1/CIN
5.120	0.035	tINS	FF	1	R46C39[0][B]	Mdu/u_mdu/reg0_neg_axb_19_par_1/COUT
5.120	0.000	tNET	FF	2	R46C39[1][A]	Mdu/u_mdu/reg0_neg_axb_23_par_1/CIN
5.155	0.035	tINS	FF	1	R46C39[1][A]	Mdu/u_mdu/reg0_neg_axb_23_par_1/COUT
5.155	0.000	tNET	FF	2	R46C39[1][B]	Mdu/u_mdu/reg0_neg_axb_27_par_1/CIN
5.191	0.035	tINS	FF	1	R46C39[1][B]	Mdu/u_mdu/reg0_neg_axb_27_par_1/COUT
5.191	0.000	tNET	FF	2	R46C39[2][A]	Mdu/u_mdu/reg0_neg_axb_31_par_1/CIN
5.226	0.035	tINS	FF	1	R46C39[2][A]	Mdu/u_mdu/reg0_neg_axb_31_par_1/COUT
5.226	0.000	tNET	FF	2	R46C39[2][B]	Mdu/u_mdu/reg0_neg_cry_34_0/CIN
5.261	0.035	tINS	FF	1	R46C39[2][B]	Mdu/u_mdu/reg0_neg_cry_34_0/COUT
5.261	0.000	tNET	FF	2	R46C40[0][A]	Mdu/u_mdu/reg0_neg_cry_35_0/CIN
5.296	0.035	tINS	FF	1	R46C40[0][A]	Mdu/u_mdu/reg0_neg_cry_35_0/COUT
5.296	0.000	tNET	FF	2	R46C40[0][B]	Mdu/u_mdu/reg0_neg_cry_36_0/CIN
5.331	0.035	tINS	FF	1	R46C40[0][B]	Mdu/u_mdu/reg0_neg_cry_36_0/COUT
5.331	0.000	tNET	FF	2	R46C40[1][A]	Mdu/u_mdu/reg0_neg_cry_37_0/CIN
5.367	0.035	tINS	FF	1	R46C40[1][A]	Mdu/u_mdu/reg0_neg_cry_37_0/COUT
5.367	0.000	tNET	FF	2	R46C40[1][B]	Mdu/u_mdu/reg0_neg_cry_38_0/CIN
5.402	0.035	tINS	FF	1	R46C40[1][B]	Mdu/u_mdu/reg0_neg_cry_38_0/COUT
5.402	0.000	tNET	FF	2	R46C40[2][A]	Mdu/u_mdu/reg0_neg_cry_39_0/CIN
5.437	0.035	tINS	FF	1	R46C40[2][A]	Mdu/u_mdu/reg0_neg_cry_39_0/COUT
5.437	0.000	tNET	FF	2	R46C40[2][B]	Mdu/u_mdu/reg0_neg_cry_40_0/CIN
5.472	0.035	tINS	FF	1	R46C40[2][B]	Mdu/u_mdu/reg0_neg_cry_40_0/COUT
5.472	0.000	tNET	FF	2	R46C41[0][A]	Mdu/u_mdu/reg0_neg_cry_41_0/CIN
5.507	0.035	tINS	FF	1	R46C41[0][A]	Mdu/u_mdu/reg0_neg_cry_41_0/COUT
5.507	0.000	tNET	FF	2	R46C41[0][B]	Mdu/u_mdu/reg0_neg_cry_42_0/CIN
5.543	0.035	tINS	FF	1	R46C41[0][B]	Mdu/u_mdu/reg0_neg_cry_42_0/COUT
5.543	0.000	tNET	FF	2	R46C41[1][A]	Mdu/u_mdu/reg0_neg_cry_43_0/CIN
5.578	0.035	tINS	FF	1	R46C41[1][A]	Mdu/u_mdu/reg0_neg_cry_43_0/COUT
5.578	0.000	tNET	FF	2	R46C41[1][B]	Mdu/u_mdu/reg0_neg_cry_44_0/CIN
5.613	0.035	tINS	FF	1	R46C41[1][B]	Mdu/u_mdu/reg0_neg_cry_44_0/COUT
5.613	0.000	tNET	FF	2	R46C41[2][A]	Mdu/u_mdu/reg0_neg_cry_45_0/CIN
5.648	0.035	tINS	FF	1	R46C41[2][A]	Mdu/u_mdu/reg0_neg_cry_45_0/COUT
5.648	0.000	tNET	FF	2	R46C41[2][B]	Mdu/u_mdu/reg0_neg_cry_46_0/CIN
5.683	0.035	tINS	FF	1	R46C41[2][B]	Mdu/u_mdu/reg0_neg_cry_46_0/COUT
5.683	0.000	tNET	FF	2	R46C42[0][A]	Mdu/u_mdu/reg0_neg_cry_47_0/CIN
5.719	0.035	tINS	FF	1	R46C42[0][A]	Mdu/u_mdu/reg0_neg_cry_47_0/COUT
5.719	0.000	tNET	FF	2	R46C42[0][B]	Mdu/u_mdu/reg0_neg_cry_48_0/CIN
5.754	0.035	tINS	FF	1	R46C42[0][B]	Mdu/u_mdu/reg0_neg_cry_48_0/COUT
5.754	0.000	tNET	FF	2	R46C42[1][A]	Mdu/u_mdu/reg0_neg_cry_49_0/CIN
5.789	0.035	tINS	FF	1	R46C42[1][A]	Mdu/u_mdu/reg0_neg_cry_49_0/COUT
5.789	0.000	tNET	FF	2	R46C42[1][B]	Mdu/u_mdu/reg0_neg_cry_50_0/CIN
5.824	0.035	tINS	FF	1	R46C42[1][B]	Mdu/u_mdu/reg0_neg_cry_50_0/COUT
5.824	0.000	tNET	FF	2	R46C42[2][A]	Mdu/u_mdu/reg0_neg_cry_51_0/CIN
5.859	0.035	tINS	FF	1	R46C42[2][A]	Mdu/u_mdu/reg0_neg_cry_51_0/COUT
5.859	0.000	tNET	FF	2	R46C42[2][B]	Mdu/u_mdu/reg0_neg_cry_52_0/CIN
6.329	0.470	tINS	FF	1	R46C42[2][B]	Mdu/u_mdu/reg0_neg_cry_52_0/SUM
7.479	1.149	tNET	FF	1	R29C37[3][A]	Mdu/u_mdu/reg0_post_swap_2[20]/I2
8.049	0.570	tINS	FR	1	R29C37[3][A]	Mdu/u_mdu/reg0_post_swap_2[20]/F
8.049	0.000	tNET	RR	1	R29C37[3][A]	Mdu/u_mdu/reg0_post_swap_4[20]/I0
8.154	0.105	tINS	RR	2	R29C37[3][A]	Mdu/u_mdu/reg0_post_swap_4[20]/O
8.335	0.181	tNET	RR	1	R29C37[1][A]	Mdu/u_mdu/un11_reg0_nx_cZ[20]_cZ/I1
8.788	0.453	tINS	RF	2	R29C37[1][A]	Mdu/u_mdu/un11_reg0_nx_cZ[20]_cZ/F
9.992	1.203	tNET	FF	1	R43C34[1][B]	Mdu/u_mdu/reg0_nx_cZ[20]/I3
10.541	0.549	tINS	FR	1	R43C34[1][B]	Mdu/u_mdu/reg0_nx_cZ[20]/F
10.541	0.000	tNET	RR	1	R43C34[1][B]	Mdu/u_mdu/reg0_Z[20]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	497	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R43C34[1][B]	Mdu/u_mdu/reg0_Z[20]/CLK
11.683	-0.200	tUnc				Mdu/u_mdu/reg0_Z[20]
11.648	-0.035	tSu		1	R43C34[1][B]	Mdu/u_mdu/reg0_Z[20]

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 4.187, 48.366%; route: 4.238, 48.954%; tC2Q: 0.232, 2.680%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path19

Path Summary:

Slack	1.281
Data Arrival Time	10.367
Data Required Time	11.648
From	Mdu/u_mdu/div_shift_number_Z[3]
To	Mdu/u_mdu/reg0_Z[57]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.683	0.683	tINS	RR	497	IOT48[A]	clk_ibuf/O
1.883	1.201	tNET	RR	1	R51C33[2][B]	Mdu/u_mdu/div_shift_number_Z[3]/CLK
2.115	0.232	tC2Q	RF	12	R51C33[2][B]	Mdu/u_mdu/div_shift_number_Z[3]/Q
2.808	0.693	tNET	FF	1	R55C31[3][A]	Mdu/u_mdu/div_shift_number_RNI5MR3_2[2]/I1
3.363	0.555	tINS	FF	70	R55C31[3][A]	Mdu/u_mdu/div_shift_number_RNI5MR3_2[2]/F
5.149	1.786	tNET	FF	1	R56C39[2][B]	Mdu/u_mdu/m41_2_03_0_cZ/I0
5.611	0.462	tINS	FR	1	R56C39[2][B]	Mdu/u_mdu/m41_2_03_0_cZ/F
5.613	0.001	tNET	RR	1	R56C39[0][B]	Mdu/u_mdu/m41_2_03_cZ/I0
6.130	0.517	tINS	RF	2	R56C39[0][B]	Mdu/u_mdu/m41_2_03_cZ/F
6.940	0.810	tNET	FF	1	R51C39[0][B]	Mdu/u_mdu/m57_4_03_1_0_cZ/I2
7.495	0.555	tINS	FF	1	R51C39[0][B]	Mdu/u_mdu/m57_4_03_1_0_cZ/F
8.134	0.640	tNET	FF	1	R47C39[3][A]	Mdu/u_mdu/reg0_exe_nx_m0_cZ[57]/I2
8.689	0.555	tINS	FF	1	R47C39[3][A]	Mdu/u_mdu/reg0_exe_nx_m0_cZ[57]/F
8.689	0.000	tNET	FF	1	R47C39[3][A]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[57]/I0
8.792	0.103	tINS	FF	1	R47C39[3][A]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[57]/O
9.996	1.203	tNET	FF	1	R31C39[2][A]	Mdu/u_mdu/reg0_nx_cZ[57]/I0
10.367	0.371	tINS	FF	1	R31C39[2][A]	Mdu/u_mdu/reg0_nx_cZ[57]/F
10.367	0.000	tNET	FF	1	R31C39[2][A]	Mdu/u_mdu/reg0_Z[57]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	497	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R31C39[2][A]	Mdu/u_mdu/reg0_Z[57]/CLK
11.683	-0.200	tUnc				Mdu/u_mdu/reg0_Z[57]
11.648	-0.035	tSu		1	R31C39[2][A]	Mdu/u_mdu/reg0_Z[57]

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 3.118, 36.753%; route: 5.134, 60.512%; tC2Q: 0.232, 2.735%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path20

Path Summary:

Slack	1.313
Data Arrival Time	10.335
Data Required Time	11.648
From	Mdu/u_mdu/reg0_fast_Z[3]
To	Mdu/u_mdu/reg0_19_rep1_Z
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.683	0.683	tINS	RR	497	IOT48[A]	clk_ibuf/O
1.883	1.201	tNET	RR	1	R34C30[2][A]	Mdu/u_mdu/reg0_fast_Z[3]/CLK
2.115	0.232	tC2Q	RF	7	R34C30[2][A]	Mdu/u_mdu/reg0_fast_Z[3]/Q
3.212	1.097	tNET	FF	1	R37C38[3][B]	Mdu/u_mdu/reg0_neg_axb_0_par_0_cp_0_cZ/I3
3.767	0.555	tINS	FF	1	R37C38[3][B]	Mdu/u_mdu/reg0_neg_axb_0_par_0_cp_0_cZ/F
4.374	0.607	tNET	FF	2	R46C38[1][A]	Mdu/u_mdu/reg0_neg_axb_0_par_cp_0_0/I0
4.944	0.570	tINS	FR	1	R46C38[1][A]	Mdu/u_mdu/reg0_neg_axb_0_par_cp_0_0/COUT
4.944	0.000	tNET	RR	2	R46C38[1][B]	Mdu/u_mdu/reg0_neg_axb_4_par_cp_0_0/CIN
4.979	0.035	tINS	RF	1	R46C38[1][B]	Mdu/u_mdu/reg0_neg_axb_4_par_cp_0_0/COUT
4.979	0.000	tNET	FF	2	R46C38[2][A]	Mdu/u_mdu/reg0_neg_axb_8_par_cp_1/CIN
5.015	0.035	tINS	FF	1	R46C38[2][A]	Mdu/u_mdu/reg0_neg_axb_8_par_cp_1/COUT
5.015	0.000	tNET	FF	2	R46C38[2][B]	Mdu/u_mdu/reg0_neg_axb_12_par_cp_1/CIN
5.050	0.035	tINS	FF	1	R46C38[2][B]	Mdu/u_mdu/reg0_neg_axb_12_par_cp_1/COUT
5.050	0.000	tNET	FF	2	R46C39[0][A]	Mdu/u_mdu/reg0_neg_axb_16_par_cp_1/CIN
5.085	0.035	tINS	FF	1	R46C39[0][A]	Mdu/u_mdu/reg0_neg_axb_16_par_cp_1/COUT
5.085	0.000	tNET	FF	2	R46C39[0][B]	Mdu/u_mdu/reg0_neg_axb_19_par_1/CIN
5.120	0.035	tINS	FF	1	R46C39[0][B]	Mdu/u_mdu/reg0_neg_axb_19_par_1/COUT
5.120	0.000	tNET	FF	2	R46C39[1][A]	Mdu/u_mdu/reg0_neg_axb_23_par_1/CIN
5.155	0.035	tINS	FF	1	R46C39[1][A]	Mdu/u_mdu/reg0_neg_axb_23_par_1/COUT
5.155	0.000	tNET	FF	2	R46C39[1][B]	Mdu/u_mdu/reg0_neg_axb_27_par_1/CIN
5.191	0.035	tINS	FF	1	R46C39[1][B]	Mdu/u_mdu/reg0_neg_axb_27_par_1/COUT
5.191	0.000	tNET	FF	2	R46C39[2][A]	Mdu/u_mdu/reg0_neg_axb_31_par_1/CIN
5.226	0.035	tINS	FF	1	R46C39[2][A]	Mdu/u_mdu/reg0_neg_axb_31_par_1/COUT
5.226	0.000	tNET	FF	2	R46C39[2][B]	Mdu/u_mdu/reg0_neg_cry_34_0/CIN
5.261	0.035	tINS	FF	1	R46C39[2][B]	Mdu/u_mdu/reg0_neg_cry_34_0/COUT
5.261	0.000	tNET	FF	2	R46C40[0][A]	Mdu/u_mdu/reg0_neg_cry_35_0/CIN
5.296	0.035	tINS	FF	1	R46C40[0][A]	Mdu/u_mdu/reg0_neg_cry_35_0/COUT
5.296	0.000	tNET	FF	2	R46C40[0][B]	Mdu/u_mdu/reg0_neg_cry_36_0/CIN
5.331	0.035	tINS	FF	1	R46C40[0][B]	Mdu/u_mdu/reg0_neg_cry_36_0/COUT
5.331	0.000	tNET	FF	2	R46C40[1][A]	Mdu/u_mdu/reg0_neg_cry_37_0/CIN
5.367	0.035	tINS	FF	1	R46C40[1][A]	Mdu/u_mdu/reg0_neg_cry_37_0/COUT
5.367	0.000	tNET	FF	2	R46C40[1][B]	Mdu/u_mdu/reg0_neg_cry_38_0/CIN
5.402	0.035	tINS	FF	1	R46C40[1][B]	Mdu/u_mdu/reg0_neg_cry_38_0/COUT
5.402	0.000	tNET	FF	2	R46C40[2][A]	Mdu/u_mdu/reg0_neg_cry_39_0/CIN
5.437	0.035	tINS	FF	1	R46C40[2][A]	Mdu/u_mdu/reg0_neg_cry_39_0/COUT
5.437	0.000	tNET	FF	2	R46C40[2][B]	Mdu/u_mdu/reg0_neg_cry_40_0/CIN
5.472	0.035	tINS	FF	1	R46C40[2][B]	Mdu/u_mdu/reg0_neg_cry_40_0/COUT
5.472	0.000	tNET	FF	2	R46C41[0][A]	Mdu/u_mdu/reg0_neg_cry_41_0/CIN
5.507	0.035	tINS	FF	1	R46C41[0][A]	Mdu/u_mdu/reg0_neg_cry_41_0/COUT
5.507	0.000	tNET	FF	2	R46C41[0][B]	Mdu/u_mdu/reg0_neg_cry_42_0/CIN
5.543	0.035	tINS	FF	1	R46C41[0][B]	Mdu/u_mdu/reg0_neg_cry_42_0/COUT
5.543	0.000	tNET	FF	2	R46C41[1][A]	Mdu/u_mdu/reg0_neg_cry_43_0/CIN
5.578	0.035	tINS	FF	1	R46C41[1][A]	Mdu/u_mdu/reg0_neg_cry_43_0/COUT
5.578	0.000	tNET	FF	2	R46C41[1][B]	Mdu/u_mdu/reg0_neg_cry_44_0/CIN
5.613	0.035	tINS	FF	1	R46C41[1][B]	Mdu/u_mdu/reg0_neg_cry_44_0/COUT
5.613	0.000	tNET	FF	2	R46C41[2][A]	Mdu/u_mdu/reg0_neg_cry_45_0/CIN
5.648	0.035	tINS	FF	1	R46C41[2][A]	Mdu/u_mdu/reg0_neg_cry_45_0/COUT
5.648	0.000	tNET	FF	2	R46C41[2][B]	Mdu/u_mdu/reg0_neg_cry_46_0/CIN
5.683	0.035	tINS	FF	1	R46C41[2][B]	Mdu/u_mdu/reg0_neg_cry_46_0/COUT
5.683	0.000	tNET	FF	2	R46C42[0][A]	Mdu/u_mdu/reg0_neg_cry_47_0/CIN
5.719	0.035	tINS	FF	1	R46C42[0][A]	Mdu/u_mdu/reg0_neg_cry_47_0/COUT
5.719	0.000	tNET	FF	2	R46C42[0][B]	Mdu/u_mdu/reg0_neg_cry_48_0/CIN
5.754	0.035	tINS	FF	1	R46C42[0][B]	Mdu/u_mdu/reg0_neg_cry_48_0/COUT
5.754	0.000	tNET	FF	2	R46C42[1][A]	Mdu/u_mdu/reg0_neg_cry_49_0/CIN
5.789	0.035	tINS	FF	1	R46C42[1][A]	Mdu/u_mdu/reg0_neg_cry_49_0/COUT
5.789	0.000	tNET	FF	2	R46C42[1][B]	Mdu/u_mdu/reg0_neg_cry_50_0/CIN
5.824	0.035	tINS	FF	1	R46C42[1][B]	Mdu/u_mdu/reg0_neg_cry_50_0/COUT
5.824	0.000	tNET	FF	2	R46C42[2][A]	Mdu/u_mdu/reg0_neg_cry_51_0/CIN
6.294	0.470	tINS	FF	1	R46C42[2][A]	Mdu/u_mdu/reg0_neg_cry_51_0/SUM
7.520	1.226	tNET	FF	1	R30C37[3][A]	Mdu/u_mdu/reg0_post_swap_2[19]/I2
8.090	0.570	tINS	FR	1	R30C37[3][A]	Mdu/u_mdu/reg0_post_swap_2[19]/F
8.090	0.000	tNET	RR	1	R30C37[3][A]	Mdu/u_mdu/reg0_post_swap_4[19]/I0
8.195	0.105	tINS	RR	2	R30C37[3][A]	Mdu/u_mdu/reg0_post_swap_4[19]/O
8.377	0.181	tNET	RR	1	R31C37[3][A]	Mdu/u_mdu/un11_reg0_nx_cZ[19]_cZ/I1
8.932	0.555	tINS	RF	3	R31C37[3][A]	Mdu/u_mdu/un11_reg0_nx_cZ[19]_cZ/F
9.786	0.854	tNET	FF	1	R43C37[2][A]	Mdu/u_mdu/reg0_nx_rep1_cZ[19]/I3
10.335	0.549	tINS	FR	1	R43C37[2][A]	Mdu/u_mdu/reg0_nx_rep1_cZ[19]/F
10.335	0.000	tNET	RR	1	R43C37[2][A]	Mdu/u_mdu/reg0_19_rep1_Z/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	497	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R43C37[2][A]	Mdu/u_mdu/reg0_19_rep1_Z/CLK
11.683	-0.200	tUnc				Mdu/u_mdu/reg0_19_rep1_Z
11.648	-0.035	tSu		1	R43C37[2][A]	Mdu/u_mdu/reg0_19_rep1_Z

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 4.254, 50.332%; route: 3.966, 46.923%; tC2Q: 0.232, 2.745%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path21

Path Summary:

Slack	1.323
Data Arrival Time	10.325
Data Required Time	11.648
From	Mdu/u_mdu/reg0_fast_Z[3]
To	Mdu/u_mdu/reg0_fast_Z[14]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.683	0.683	tINS	RR	497	IOT48[A]	clk_ibuf/O
1.883	1.201	tNET	RR	1	R34C30[2][A]	Mdu/u_mdu/reg0_fast_Z[3]/CLK
2.115	0.232	tC2Q	RF	7	R34C30[2][A]	Mdu/u_mdu/reg0_fast_Z[3]/Q
3.212	1.097	tNET	FF	1	R37C38[3][B]	Mdu/u_mdu/reg0_neg_axb_0_par_0_cp_0_cZ/I3
3.767	0.555	tINS	FF	1	R37C38[3][B]	Mdu/u_mdu/reg0_neg_axb_0_par_0_cp_0_cZ/F
4.374	0.607	tNET	FF	2	R46C38[1][A]	Mdu/u_mdu/reg0_neg_axb_0_par_cp_0_0/I0
4.944	0.570	tINS	FR	1	R46C38[1][A]	Mdu/u_mdu/reg0_neg_axb_0_par_cp_0_0/COUT
4.944	0.000	tNET	RR	2	R46C38[1][B]	Mdu/u_mdu/reg0_neg_axb_4_par_cp_0_0/CIN
4.979	0.035	tINS	RF	1	R46C38[1][B]	Mdu/u_mdu/reg0_neg_axb_4_par_cp_0_0/COUT
4.979	0.000	tNET	FF	2	R46C38[2][A]	Mdu/u_mdu/reg0_neg_axb_8_par_cp_1/CIN
5.015	0.035	tINS	FF	1	R46C38[2][A]	Mdu/u_mdu/reg0_neg_axb_8_par_cp_1/COUT
5.015	0.000	tNET	FF	2	R46C38[2][B]	Mdu/u_mdu/reg0_neg_axb_12_par_cp_1/CIN
5.050	0.035	tINS	FF	1	R46C38[2][B]	Mdu/u_mdu/reg0_neg_axb_12_par_cp_1/COUT
5.050	0.000	tNET	FF	2	R46C39[0][A]	Mdu/u_mdu/reg0_neg_axb_16_par_cp_1/CIN
5.085	0.035	tINS	FF	1	R46C39[0][A]	Mdu/u_mdu/reg0_neg_axb_16_par_cp_1/COUT
5.085	0.000	tNET	FF	2	R46C39[0][B]	Mdu/u_mdu/reg0_neg_axb_19_par_1/CIN
5.120	0.035	tINS	FF	1	R46C39[0][B]	Mdu/u_mdu/reg0_neg_axb_19_par_1/COUT
5.120	0.000	tNET	FF	2	R46C39[1][A]	Mdu/u_mdu/reg0_neg_axb_23_par_1/CIN
5.155	0.035	tINS	FF	1	R46C39[1][A]	Mdu/u_mdu/reg0_neg_axb_23_par_1/COUT
5.155	0.000	tNET	FF	2	R46C39[1][B]	Mdu/u_mdu/reg0_neg_axb_27_par_1/CIN
5.191	0.035	tINS	FF	1	R46C39[1][B]	Mdu/u_mdu/reg0_neg_axb_27_par_1/COUT
5.191	0.000	tNET	FF	2	R46C39[2][A]	Mdu/u_mdu/reg0_neg_axb_31_par_1/CIN
5.226	0.035	tINS	FF	1	R46C39[2][A]	Mdu/u_mdu/reg0_neg_axb_31_par_1/COUT
5.226	0.000	tNET	FF	2	R46C39[2][B]	Mdu/u_mdu/reg0_neg_cry_34_0/CIN
5.261	0.035	tINS	FF	1	R46C39[2][B]	Mdu/u_mdu/reg0_neg_cry_34_0/COUT
5.261	0.000	tNET	FF	2	R46C40[0][A]	Mdu/u_mdu/reg0_neg_cry_35_0/CIN
5.296	0.035	tINS	FF	1	R46C40[0][A]	Mdu/u_mdu/reg0_neg_cry_35_0/COUT
5.296	0.000	tNET	FF	2	R46C40[0][B]	Mdu/u_mdu/reg0_neg_cry_36_0/CIN
5.331	0.035	tINS	FF	1	R46C40[0][B]	Mdu/u_mdu/reg0_neg_cry_36_0/COUT
5.331	0.000	tNET	FF	2	R46C40[1][A]	Mdu/u_mdu/reg0_neg_cry_37_0/CIN
5.367	0.035	tINS	FF	1	R46C40[1][A]	Mdu/u_mdu/reg0_neg_cry_37_0/COUT
5.367	0.000	tNET	FF	2	R46C40[1][B]	Mdu/u_mdu/reg0_neg_cry_38_0/CIN
5.402	0.035	tINS	FF	1	R46C40[1][B]	Mdu/u_mdu/reg0_neg_cry_38_0/COUT
5.402	0.000	tNET	FF	2	R46C40[2][A]	Mdu/u_mdu/reg0_neg_cry_39_0/CIN
5.437	0.035	tINS	FF	1	R46C40[2][A]	Mdu/u_mdu/reg0_neg_cry_39_0/COUT
5.437	0.000	tNET	FF	2	R46C40[2][B]	Mdu/u_mdu/reg0_neg_cry_40_0/CIN
5.472	0.035	tINS	FF	1	R46C40[2][B]	Mdu/u_mdu/reg0_neg_cry_40_0/COUT
5.472	0.000	tNET	FF	2	R46C41[0][A]	Mdu/u_mdu/reg0_neg_cry_41_0/CIN
5.507	0.035	tINS	FF	1	R46C41[0][A]	Mdu/u_mdu/reg0_neg_cry_41_0/COUT
5.507	0.000	tNET	FF	2	R46C41[0][B]	Mdu/u_mdu/reg0_neg_cry_42_0/CIN
5.543	0.035	tINS	FF	1	R46C41[0][B]	Mdu/u_mdu/reg0_neg_cry_42_0/COUT
5.543	0.000	tNET	FF	2	R46C41[1][A]	Mdu/u_mdu/reg0_neg_cry_43_0/CIN
5.578	0.035	tINS	FF	1	R46C41[1][A]	Mdu/u_mdu/reg0_neg_cry_43_0/COUT
5.578	0.000	tNET	FF	2	R46C41[1][B]	Mdu/u_mdu/reg0_neg_cry_44_0/CIN
5.613	0.035	tINS	FF	1	R46C41[1][B]	Mdu/u_mdu/reg0_neg_cry_44_0/COUT
5.613	0.000	tNET	FF	2	R46C41[2][A]	Mdu/u_mdu/reg0_neg_cry_45_0/CIN
5.648	0.035	tINS	FF	1	R46C41[2][A]	Mdu/u_mdu/reg0_neg_cry_45_0/COUT
5.648	0.000	tNET	FF	2	R46C41[2][B]	Mdu/u_mdu/reg0_neg_cry_46_0/CIN
6.118	0.470	tINS	FF	1	R46C41[2][B]	Mdu/u_mdu/reg0_neg_cry_46_0/SUM
7.344	1.226	tNET	FF	1	R29C35[3][A]	Mdu/u_mdu/reg0_post_swap_2[14]/I2
7.899	0.555	tINS	FF	1	R29C35[3][A]	Mdu/u_mdu/reg0_post_swap_2[14]/F
7.899	0.000	tNET	FF	1	R29C35[3][A]	Mdu/u_mdu/reg0_post_swap_4[14]/I0
8.002	0.103	tINS	FF	2	R29C35[3][A]	Mdu/u_mdu/reg0_post_swap_4[14]/O
8.427	0.425	tNET	FF	1	R30C34[0][B]	Mdu/u_mdu/un11_reg0_nx_cZ[14]_cZ/I1
8.982	0.555	tINS	FF	2	R30C34[0][B]	Mdu/u_mdu/un11_reg0_nx_cZ[14]_cZ/F
9.776	0.795	tNET	FF	1	R42C35[2][B]	Mdu/u_mdu/reg0_nx_fast_cZ[14]/I3
10.325	0.549	tINS	FR	1	R42C35[2][B]	Mdu/u_mdu/reg0_nx_fast_cZ[14]/F
10.325	0.000	tNET	RR	1	R42C35[2][B]	Mdu/u_mdu/reg0_fast_Z[14]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	497	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R42C35[2][B]	Mdu/u_mdu/reg0_fast_Z[14]/CLK
11.683	-0.200	tUnc				Mdu/u_mdu/reg0_fast_Z[14]
11.648	-0.035	tSu		1	R42C35[2][B]	Mdu/u_mdu/reg0_fast_Z[14]

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 4.061, 48.103%; route: 4.149, 49.149%; tC2Q: 0.232, 2.748%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path22

Path Summary:

Slack	1.323
Data Arrival Time	10.325
Data Required Time	11.648
From	Mdu/u_mdu/reg0_fast_Z[3]
To	Mdu/u_mdu/reg0_Z[14]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.683	0.683	tINS	RR	497	IOT48[A]	clk_ibuf/O
1.883	1.201	tNET	RR	1	R34C30[2][A]	Mdu/u_mdu/reg0_fast_Z[3]/CLK
2.115	0.232	tC2Q	RF	7	R34C30[2][A]	Mdu/u_mdu/reg0_fast_Z[3]/Q
3.212	1.097	tNET	FF	1	R37C38[3][B]	Mdu/u_mdu/reg0_neg_axb_0_par_0_cp_0_cZ/I3
3.767	0.555	tINS	FF	1	R37C38[3][B]	Mdu/u_mdu/reg0_neg_axb_0_par_0_cp_0_cZ/F
4.374	0.607	tNET	FF	2	R46C38[1][A]	Mdu/u_mdu/reg0_neg_axb_0_par_cp_0_0/I0
4.944	0.570	tINS	FR	1	R46C38[1][A]	Mdu/u_mdu/reg0_neg_axb_0_par_cp_0_0/COUT
4.944	0.000	tNET	RR	2	R46C38[1][B]	Mdu/u_mdu/reg0_neg_axb_4_par_cp_0_0/CIN
4.979	0.035	tINS	RF	1	R46C38[1][B]	Mdu/u_mdu/reg0_neg_axb_4_par_cp_0_0/COUT
4.979	0.000	tNET	FF	2	R46C38[2][A]	Mdu/u_mdu/reg0_neg_axb_8_par_cp_1/CIN
5.015	0.035	tINS	FF	1	R46C38[2][A]	Mdu/u_mdu/reg0_neg_axb_8_par_cp_1/COUT
5.015	0.000	tNET	FF	2	R46C38[2][B]	Mdu/u_mdu/reg0_neg_axb_12_par_cp_1/CIN
5.050	0.035	tINS	FF	1	R46C38[2][B]	Mdu/u_mdu/reg0_neg_axb_12_par_cp_1/COUT
5.050	0.000	tNET	FF	2	R46C39[0][A]	Mdu/u_mdu/reg0_neg_axb_16_par_cp_1/CIN
5.085	0.035	tINS	FF	1	R46C39[0][A]	Mdu/u_mdu/reg0_neg_axb_16_par_cp_1/COUT
5.085	0.000	tNET	FF	2	R46C39[0][B]	Mdu/u_mdu/reg0_neg_axb_19_par_1/CIN
5.120	0.035	tINS	FF	1	R46C39[0][B]	Mdu/u_mdu/reg0_neg_axb_19_par_1/COUT
5.120	0.000	tNET	FF	2	R46C39[1][A]	Mdu/u_mdu/reg0_neg_axb_23_par_1/CIN
5.155	0.035	tINS	FF	1	R46C39[1][A]	Mdu/u_mdu/reg0_neg_axb_23_par_1/COUT
5.155	0.000	tNET	FF	2	R46C39[1][B]	Mdu/u_mdu/reg0_neg_axb_27_par_1/CIN
5.191	0.035	tINS	FF	1	R46C39[1][B]	Mdu/u_mdu/reg0_neg_axb_27_par_1/COUT
5.191	0.000	tNET	FF	2	R46C39[2][A]	Mdu/u_mdu/reg0_neg_axb_31_par_1/CIN
5.226	0.035	tINS	FF	1	R46C39[2][A]	Mdu/u_mdu/reg0_neg_axb_31_par_1/COUT
5.226	0.000	tNET	FF	2	R46C39[2][B]	Mdu/u_mdu/reg0_neg_cry_34_0/CIN
5.261	0.035	tINS	FF	1	R46C39[2][B]	Mdu/u_mdu/reg0_neg_cry_34_0/COUT
5.261	0.000	tNET	FF	2	R46C40[0][A]	Mdu/u_mdu/reg0_neg_cry_35_0/CIN
5.296	0.035	tINS	FF	1	R46C40[0][A]	Mdu/u_mdu/reg0_neg_cry_35_0/COUT
5.296	0.000	tNET	FF	2	R46C40[0][B]	Mdu/u_mdu/reg0_neg_cry_36_0/CIN
5.331	0.035	tINS	FF	1	R46C40[0][B]	Mdu/u_mdu/reg0_neg_cry_36_0/COUT
5.331	0.000	tNET	FF	2	R46C40[1][A]	Mdu/u_mdu/reg0_neg_cry_37_0/CIN
5.367	0.035	tINS	FF	1	R46C40[1][A]	Mdu/u_mdu/reg0_neg_cry_37_0/COUT
5.367	0.000	tNET	FF	2	R46C40[1][B]	Mdu/u_mdu/reg0_neg_cry_38_0/CIN
5.402	0.035	tINS	FF	1	R46C40[1][B]	Mdu/u_mdu/reg0_neg_cry_38_0/COUT
5.402	0.000	tNET	FF	2	R46C40[2][A]	Mdu/u_mdu/reg0_neg_cry_39_0/CIN
5.437	0.035	tINS	FF	1	R46C40[2][A]	Mdu/u_mdu/reg0_neg_cry_39_0/COUT
5.437	0.000	tNET	FF	2	R46C40[2][B]	Mdu/u_mdu/reg0_neg_cry_40_0/CIN
5.472	0.035	tINS	FF	1	R46C40[2][B]	Mdu/u_mdu/reg0_neg_cry_40_0/COUT
5.472	0.000	tNET	FF	2	R46C41[0][A]	Mdu/u_mdu/reg0_neg_cry_41_0/CIN
5.507	0.035	tINS	FF	1	R46C41[0][A]	Mdu/u_mdu/reg0_neg_cry_41_0/COUT
5.507	0.000	tNET	FF	2	R46C41[0][B]	Mdu/u_mdu/reg0_neg_cry_42_0/CIN
5.543	0.035	tINS	FF	1	R46C41[0][B]	Mdu/u_mdu/reg0_neg_cry_42_0/COUT
5.543	0.000	tNET	FF	2	R46C41[1][A]	Mdu/u_mdu/reg0_neg_cry_43_0/CIN
5.578	0.035	tINS	FF	1	R46C41[1][A]	Mdu/u_mdu/reg0_neg_cry_43_0/COUT
5.578	0.000	tNET	FF	2	R46C41[1][B]	Mdu/u_mdu/reg0_neg_cry_44_0/CIN
5.613	0.035	tINS	FF	1	R46C41[1][B]	Mdu/u_mdu/reg0_neg_cry_44_0/COUT
5.613	0.000	tNET	FF	2	R46C41[2][A]	Mdu/u_mdu/reg0_neg_cry_45_0/CIN
5.648	0.035	tINS	FF	1	R46C41[2][A]	Mdu/u_mdu/reg0_neg_cry_45_0/COUT
5.648	0.000	tNET	FF	2	R46C41[2][B]	Mdu/u_mdu/reg0_neg_cry_46_0/CIN
6.118	0.470	tINS	FF	1	R46C41[2][B]	Mdu/u_mdu/reg0_neg_cry_46_0/SUM
7.344	1.226	tNET	FF	1	R29C35[3][A]	Mdu/u_mdu/reg0_post_swap_2[14]/I2
7.899	0.555	tINS	FF	1	R29C35[3][A]	Mdu/u_mdu/reg0_post_swap_2[14]/F
7.899	0.000	tNET	FF	1	R29C35[3][A]	Mdu/u_mdu/reg0_post_swap_4[14]/I0
8.002	0.103	tINS	FF	2	R29C35[3][A]	Mdu/u_mdu/reg0_post_swap_4[14]/O
8.427	0.425	tNET	FF	1	R30C34[0][B]	Mdu/u_mdu/un11_reg0_nx_cZ[14]_cZ/I1
8.982	0.555	tINS	FF	2	R30C34[0][B]	Mdu/u_mdu/un11_reg0_nx_cZ[14]_cZ/F
9.776	0.795	tNET	FF	1	R42C35[2][A]	Mdu/u_mdu/reg0_nx_cZ[14]/I3
10.325	0.549	tINS	FR	1	R42C35[2][A]	Mdu/u_mdu/reg0_nx_cZ[14]/F
10.325	0.000	tNET	RR	1	R42C35[2][A]	Mdu/u_mdu/reg0_Z[14]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	497	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R42C35[2][A]	Mdu/u_mdu/reg0_Z[14]/CLK
11.683	-0.200	tUnc				Mdu/u_mdu/reg0_Z[14]
11.648	-0.035	tSu		1	R42C35[2][A]	Mdu/u_mdu/reg0_Z[14]

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 4.061, 48.103%; route: 4.149, 49.149%; tC2Q: 0.232, 2.748%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path23

Path Summary:

Slack	1.326
Data Arrival Time	10.322
Data Required Time	11.648
From	Mdu/u_mdu/div_shift_number_Z[1]
To	Mdu/u_mdu/reg0_Z[22]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.683	0.683	tINS	RR	497	IOT48[A]	clk_ibuf/O
1.883	1.201	tNET	RR	1	R51C33[1][B]	Mdu/u_mdu/div_shift_number_Z[1]/CLK
2.115	0.232	tC2Q	RF	114	R51C33[1][B]	Mdu/u_mdu/div_shift_number_Z[1]/Q
3.802	1.686	tNET	FF	1	R35C33[2][A]	Mdu/u_mdu/m2_0_03_m1_e_1_cZ/I1
4.351	0.549	tINS	FR	1	R35C33[2][A]	Mdu/u_mdu/m2_0_03_m1_e_1_cZ/F
4.352	0.001	tNET	RR	1	R35C33[2][B]	Mdu/u_mdu/m2_0_03_m1_e/I2
4.805	0.453	tINS	RF	6	R35C33[2][B]	Mdu/u_mdu/m2_0_03_m1_e/F
5.531	0.726	tNET	FF	1	R51C33[3][A]	Mdu/u_mdu/m6_2_03_cZ/I2
5.902	0.371	tINS	FF	4	R51C33[3][A]	Mdu/u_mdu/m6_2_03_cZ/F
6.572	0.669	tNET	FF	1	R48C34[0][A]	Mdu/u_mdu/m22_4_01_cZ/I1
7.127	0.555	tINS	FF	1	R48C34[0][A]	Mdu/u_mdu/m22_4_01_cZ/F
7.961	0.834	tNET	FF	1	R40C31[3][B]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[22]/I2
8.531	0.570	tINS	FR	1	R40C31[3][B]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[22]/F
8.703	0.172	tNET	RR	1	R39C31[1][B]	Mdu/u_mdu/reg0_exe_nx_cZ[22]/I3
9.258	0.555	tINS	RF	3	R39C31[1][B]	Mdu/u_mdu/reg0_exe_nx_cZ[22]/F
9.752	0.494	tNET	FF	1	R37C33[1][B]	Mdu/u_mdu/reg0_nx_cZ[22]/I0
10.322	0.570	tINS	FR	1	R37C33[1][B]	Mdu/u_mdu/reg0_nx_cZ[22]/F
10.322	0.000	tNET	RR	1	R37C33[1][B]	Mdu/u_mdu/reg0_Z[22]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	497	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R37C33[1][B]	Mdu/u_mdu/reg0_Z[22]/CLK
11.683	-0.200	tUnc				Mdu/u_mdu/reg0_Z[22]
11.648	-0.035	tSu		1	R37C33[1][B]	Mdu/u_mdu/reg0_Z[22]

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 3.623, 42.931%; route: 4.584, 54.320%; tC2Q: 0.232, 2.749%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path24

Path Summary:

Slack	1.332
Data Arrival Time	10.316
Data Required Time	11.648
From	Mdu/u_mdu/reg0_Z[29]
To	Mdu/u_mdu/div_shift_number_Z[0]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.683	0.683	tINS	RR	497	IOT48[A]	clk_ibuf/O
1.883	1.201	tNET	RR	1	R37C33[2][A]	Mdu/u_mdu/reg0_Z[29]/CLK
2.115	0.232	tC2Q	RF	18	R37C33[2][A]	Mdu/u_mdu/reg0_Z[29]/Q
3.026	0.911	tNET	FF	1	R43C33[0][A]	Mdu/u_mdu/g0_19/I0
3.479	0.453	tINS	FF	7	R43C33[0][A]	Mdu/u_mdu/g0_19/F
4.605	1.126	tNET	FF	1	R38C38[3][B]	Mdu/u_mdu/g0_4_cZ/I2
4.976	0.371	tINS	FF	10	R38C38[3][B]	Mdu/u_mdu/g0_4_cZ/F
5.187	0.211	tNET	FF	1	R38C37[3][B]	Mdu/u_mdu/un2_div_shift_number_nx_i_cZ_cZ/I3
5.742	0.555	tINS	FF	10	R38C37[3][B]	Mdu/u_mdu/un2_div_shift_number_nx_i_cZ_cZ/F
6.018	0.276	tNET	FF	1	R38C39[0][B]	Mdu/u_mdu/op0_leading_zero_cZ[3]/I1
6.535	0.517	tINS	FF	2	R38C39[0][B]	Mdu/u_mdu/op0_leading_zero_cZ[3]/F
6.936	0.401	tNET	FF	1	R38C40[3][A]	Mdu/u_mdu/div_shift_number_nx_axb_3_i_lfx_cZ/S0
7.187	0.251	tINS	FF	1	R38C40[3][A]	Mdu/u_mdu/div_shift_number_nx_axb_3_i_lfx_cZ/O
8.092	0.904	tNET	FF	2	R38C40[2][B]	Mdu/u_mdu/div_shift_number_nx_cry_3_0/I0
8.662	0.570	tINS	FR	1	R38C40[2][B]	Mdu/u_mdu/div_shift_number_nx_cry_3_0/COUT
8.662	0.000	tNET	RR	2	R38C41[0][A]	Mdu/u_mdu/div_shift_number_nx_cry_4_0/CIN
8.697	0.035	tINS	RF	1	R38C41[0][A]	Mdu/u_mdu/div_shift_number_nx_cry_4_0/COUT
8.697	0.000	tNET	FF	1	R38C34[3][B]	Mdu/u_mdu/g0_0_cZ/I0
9.246	0.549	tINS	FR	6	R38C34[3][B]	Mdu/u_mdu/g0_0_cZ/F
10.316	1.070	tNET	RR	1	R51C33[1][A]	Mdu/u_mdu/div_shift_number_Z[0]/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	497	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R51C33[1][A]	Mdu/u_mdu/div_shift_number_Z[0]/CLK
11.683	-0.200	tUnc				Mdu/u_mdu/div_shift_number_Z[0]
11.648	-0.035	tSu		1	R51C33[1][A]	Mdu/u_mdu/div_shift_number_Z[0]

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	8
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 3.301, 39.148%; route: 4.899, 58.101%; tC2Q: 0.232, 2.751%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path25

Path Summary:

Slack	1.332
Data Arrival Time	10.316
Data Required Time	11.648
From	Mdu/u_mdu/reg0_Z[29]
To	Mdu/u_mdu/div_shift_number_Z[1]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.683	0.683	tINS	RR	497	IOT48[A]	clk_ibuf/O
1.883	1.201	tNET	RR	1	R37C33[2][A]	Mdu/u_mdu/reg0_Z[29]/CLK
2.115	0.232	tC2Q	RF	18	R37C33[2][A]	Mdu/u_mdu/reg0_Z[29]/Q
3.026	0.911	tNET	FF	1	R43C33[0][A]	Mdu/u_mdu/g0_19/I0
3.479	0.453	tINS	FF	7	R43C33[0][A]	Mdu/u_mdu/g0_19/F
4.605	1.126	tNET	FF	1	R38C38[3][B]	Mdu/u_mdu/g0_4_cZ/I2
4.976	0.371	tINS	FF	10	R38C38[3][B]	Mdu/u_mdu/g0_4_cZ/F
5.187	0.211	tNET	FF	1	R38C37[3][B]	Mdu/u_mdu/un2_div_shift_number_nx_i_cZ_cZ/I3
5.742	0.555	tINS	FF	10	R38C37[3][B]	Mdu/u_mdu/un2_div_shift_number_nx_i_cZ_cZ/F
6.018	0.276	tNET	FF	1	R38C39[0][B]	Mdu/u_mdu/op0_leading_zero_cZ[3]/I1
6.535	0.517	tINS	FF	2	R38C39[0][B]	Mdu/u_mdu/op0_leading_zero_cZ[3]/F
6.936	0.401	tNET	FF	1	R38C40[3][A]	Mdu/u_mdu/div_shift_number_nx_axb_3_i_lfx_cZ/S0
7.187	0.251	tINS	FF	1	R38C40[3][A]	Mdu/u_mdu/div_shift_number_nx_axb_3_i_lfx_cZ/O
8.092	0.904	tNET	FF	2	R38C40[2][B]	Mdu/u_mdu/div_shift_number_nx_cry_3_0/I0
8.662	0.570	tINS	FR	1	R38C40[2][B]	Mdu/u_mdu/div_shift_number_nx_cry_3_0/COUT
8.662	0.000	tNET	RR	2	R38C41[0][A]	Mdu/u_mdu/div_shift_number_nx_cry_4_0/CIN
8.697	0.035	tINS	RF	1	R38C41[0][A]	Mdu/u_mdu/div_shift_number_nx_cry_4_0/COUT
8.697	0.000	tNET	FF	1	R38C34[3][B]	Mdu/u_mdu/g0_0_cZ/I0
9.246	0.549	tINS	FR	6	R38C34[3][B]	Mdu/u_mdu/g0_0_cZ/F
10.316	1.070	tNET	RR	1	R51C33[1][B]	Mdu/u_mdu/div_shift_number_Z[1]/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	497	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R51C33[1][B]	Mdu/u_mdu/div_shift_number_Z[1]/CLK
11.683	-0.200	tUnc				Mdu/u_mdu/div_shift_number_Z[1]
11.648	-0.035	tSu		1	R51C33[1][B]	Mdu/u_mdu/div_shift_number_Z[1]

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	8
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 3.301, 39.148%; route: 4.899, 58.101%; tC2Q: 0.232, 2.751%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Hold Analysis Report

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	0.213
Data Arrival Time	2.040
Data Required Time	1.826
From	u_la0_top/u_ao_mem_ctrl/data_reg_Z[37]
To	u_la0_top/u_ao_mem_ctrl/mem_mem_0_18
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	497	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R11C12[1][B]	u_la0_top/u_ao_mem_ctrl/data_reg_Z[37]/CLK
1.779	0.202	tC2Q	RR	1	R11C12[1][B]	u_la0_top/u_ao_mem_ctrl/data_reg_Z[37]/Q
2.040	0.260	tNET	RR	1	BSRAM_R10[3]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_18/DI1

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	497	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	BSRAM_R10[3]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_18/CLKA
1.577	0.000	tUnc				u_la0_top/u_ao_mem_ctrl/mem_mem_0_18
1.826	0.249	tHld		1	BSRAM_R10[3]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_18

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.260, 56.314%; tC2Q: 0.202, 43.686%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path2

Path Summary:

Slack	0.213
Data Arrival Time	2.040
Data Required Time	1.826
From	u_la0_top/u_ao_mem_ctrl/data_reg_Z[36]
To	u_la0_top/u_ao_mem_ctrl/mem_mem_0_18
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	497	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R11C12[1][A]	u_la0_top/u_ao_mem_ctrl/data_reg_Z[36]/CLK
1.779	0.202	tC2Q	RR	1	R11C12[1][A]	u_la0_top/u_ao_mem_ctrl/data_reg_Z[36]/Q
2.040	0.260	tNET	RR	1	BSRAM_R10[3]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_18/DI0

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	497	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	BSRAM_R10[3]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_18/CLKA
1.577	0.000	tUnc				u_la0_top/u_ao_mem_ctrl/mem_mem_0_18
1.826	0.249	tHld		1	BSRAM_R10[3]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_18

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.260, 56.314%; tC2Q: 0.202, 43.686%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path3

Path Summary:

Slack	0.225
Data Arrival Time	1.920
Data Required Time	1.695
From	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[5]
To	u_la0_top/u_ao_mem_ctrl/mem_mem_0_8
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	497	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R9C8[1][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[5]/CLK
1.778	0.201	tC2Q	RF	51	R9C8[1][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[5]/Q
1.920	0.142	tNET	FF	1	BSRAM_R10[1]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_8/ADA6

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	497	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	BSRAM_R10[1]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_8/CLKA
1.577	0.000	tUnc				u_la0_top/u_ao_mem_ctrl/mem_mem_0_8
1.695	0.118	tHld		1	BSRAM_R10[1]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_8

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.142, 41.325%; tC2Q: 0.201, 58.675%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path4

Path Summary:

Slack	0.334
Data Arrival Time	2.030
Data Required Time	1.695
From	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[2]
To	u_la0_top/u_ao_mem_ctrl/mem_mem_0_8
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	497	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R9C8[1][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[2]/CLK
1.779	0.202	tC2Q	RR	51	R9C8[1][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[2]/Q
2.030	0.250	tNET	RR	1	BSRAM_R10[1]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_8/ADA3

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	497	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	BSRAM_R10[1]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_8/CLKA
1.577	0.000	tUnc				u_la0_top/u_ao_mem_ctrl/mem_mem_0_8
1.695	0.118	tHld		1	BSRAM_R10[1]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_8

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.250, 55.321%; tC2Q: 0.202, 44.679%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path5

Path Summary:

Slack	0.335
Data Arrival Time	2.162
Data Required Time	1.826
From	u_la0_top/u_ao_mem_ctrl/data_reg_Z[41]
To	u_la0_top/u_ao_mem_ctrl/mem_mem_0_20
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	497	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R11C13[2][B]	u_la0_top/u_ao_mem_ctrl/data_reg_Z[41]/CLK
1.779	0.202	tC2Q	RR	1	R11C13[2][B]	u_la0_top/u_ao_mem_ctrl/data_reg_Z[41]/Q
2.162	0.382	tNET	RR	1	BSRAM_R10[4]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_20/DI1

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	497	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	BSRAM_R10[4]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_20/CLKA
1.577	0.000	tUnc				u_la0_top/u_ao_mem_ctrl/mem_mem_0_20
1.826	0.249	tHld		1	BSRAM_R10[4]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_20

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.382, 65.434%; tC2Q: 0.202, 34.566%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path6

Path Summary:

Slack	0.338
Data Arrival Time	2.034
Data Required Time	1.695
From	cnt_1_Z[1]
To	memr_memr_0_5
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	497	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R44C43[1][B]	cnt_1_Z[1]/CLK
1.779	0.202	tC2Q	RR	17	R44C43[1][B]	cnt_1_Z[1]/Q
2.034	0.254	tNET	RR	1	BSRAM_R45[13]	memr_memr_0_5/ADB2

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	497	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	BSRAM_R45[13]	memr_memr_0_5/CLKB
1.577	0.000	tUnc				memr_memr_0_5
1.695	0.118	tHld		1	BSRAM_R45[13]	memr_memr_0_5

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.254, 55.710%; tC2Q: 0.202, 44.290%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path7

Path Summary:

Slack	0.339
Data Arrival Time	2.035
Data Required Time	1.695
From	cnt_1_Z[0]
To	memr_memr_0_5
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	497	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R44C43[1][A]	cnt_1_Z[0]/CLK
1.779	0.202	tC2Q	RR	17	R44C43[1][A]	cnt_1_Z[0]/Q
2.035	0.255	tNET	RR	1	BSRAM_R45[13]	memr_memr_0_5/ADB1

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	497	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	BSRAM_R45[13]	memr_memr_0_5/CLKB
1.577	0.000	tUnc				memr_memr_0_5
1.695	0.118	tHld		1	BSRAM_R45[13]	memr_memr_0_5

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.255, 55.828%; tC2Q: 0.202, 44.172%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path8

Path Summary:

Slack	0.341
Data Arrival Time	2.036
Data Required Time	1.695
From	cnt_1_Z[2]
To	memr_memr_0_5
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	497	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R44C43[2][A]	cnt_1_Z[2]/CLK
1.779	0.202	tC2Q	RR	17	R44C43[2][A]	cnt_1_Z[2]/Q
2.036	0.257	tNET	RR	1	BSRAM_R45[13]	memr_memr_0_5/ADB3

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	497	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	BSRAM_R45[13]	memr_memr_0_5/CLKB
1.577	0.000	tUnc				memr_memr_0_5
1.695	0.118	tHld		1	BSRAM_R45[13]	memr_memr_0_5

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.257, 55.946%; tC2Q: 0.202, 44.054%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path9

Path Summary:

Slack	0.352
Data Arrival Time	2.047
Data Required Time	1.695
From	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[1]
To	u_la0_top/u_ao_mem_ctrl/mem_mem_0_8
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	497	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R9C8[0][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[1]/CLK
1.779	0.202	tC2Q	RR	51	R9C8[0][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[1]/Q
2.047	0.268	tNET	RR	1	BSRAM_R10[1]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_8/ADA2

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	497	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	BSRAM_R10[1]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_8/CLKA
1.577	0.000	tUnc				u_la0_top/u_ao_mem_ctrl/mem_mem_0_8
1.695	0.118	tHld		1	BSRAM_R10[1]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_8

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.268, 56.981%; tC2Q: 0.202, 43.019%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path10

Path Summary:

Slack	0.352
Data Arrival Time	2.047
Data Required Time	1.695
From	cnt_Z[1]
To	memr_memr_0_5
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	497	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R46C43[2][A]	cnt_Z[1]/CLK
1.779	0.202	tC2Q	RR	18	R46C43[2][A]	cnt_Z[1]/Q
2.047	0.268	tNET	RR	1	BSRAM_R45[13]	memr_memr_0_5/ADA2

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	497	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	BSRAM_R45[13]	memr_memr_0_5/CLKA
1.577	0.000	tUnc				memr_memr_0_5
1.695	0.118	tHld		1	BSRAM_R45[13]	memr_memr_0_5

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.268, 56.981%; tC2Q: 0.202, 43.019%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path11

Path Summary:

Slack	0.352
Data Arrival Time	2.047
Data Required Time	1.695
From	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[3]
To	u_la0_top/u_ao_mem_ctrl/mem_mem_0_8
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	497	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R8C10[0][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[3]/CLK
1.779	0.202	tC2Q	RR	51	R8C10[0][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[3]/Q
2.047	0.268	tNET	RR	1	BSRAM_R10[1]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_8/ADA4

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	497	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	BSRAM_R10[1]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_8/CLKA
1.577	0.000	tUnc				u_la0_top/u_ao_mem_ctrl/mem_mem_0_8
1.695	0.118	tHld		1	BSRAM_R10[1]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_8

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.268, 56.991%; tC2Q: 0.202, 43.009%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path12

Path Summary:

Slack	0.353
Data Arrival Time	2.048
Data Required Time	1.695
From	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[2]
To	u_la0_top/u_ao_mem_ctrl/mem_mem_0_3
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	497	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R9C8[1][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[2]/CLK
1.779	0.202	tC2Q	RR	51	R9C8[1][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[2]/Q
2.048	0.269	tNET	RR	1	BSRAM_R10[0]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_3/ADA3

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	497	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	BSRAM_R10[0]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_3/CLKA
1.577	0.000	tUnc				u_la0_top/u_ao_mem_ctrl/mem_mem_0_3
1.695	0.118	tHld		1	BSRAM_R10[0]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_3

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.269, 57.092%; tC2Q: 0.202, 42.908%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path13

Path Summary:

Slack	0.353
Data Arrival Time	2.048
Data Required Time	1.695
From	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[7]
To	u_la0_top/u_ao_mem_ctrl/mem_mem_0_3
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	497	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R11C6[2][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[7]/CLK
1.779	0.202	tC2Q	RR	51	R11C6[2][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[7]/Q
2.048	0.269	tNET	RR	1	BSRAM_R10[0]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_3/ADA8

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	497	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	BSRAM_R10[0]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_3/CLKA
1.577	0.000	tUnc				u_la0_top/u_ao_mem_ctrl/mem_mem_0_3
1.695	0.118	tHld		1	BSRAM_R10[0]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_3

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.269, 57.097%; tC2Q: 0.202, 42.903%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path14

Path Summary:

Slack	0.354
Data Arrival Time	2.049
Data Required Time	1.695
From	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[4]
To	u_la0_top/u_ao_mem_ctrl/mem_mem_0_8
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	497	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R12C8[0][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[4]/CLK
1.779	0.202	tC2Q	RR	51	R12C8[0][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[4]/Q
2.049	0.270	tNET	RR	1	BSRAM_R10[1]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_8/ADA5

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	497	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	BSRAM_R10[1]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_8/CLKA
1.577	0.000	tUnc				u_la0_top/u_ao_mem_ctrl/mem_mem_0_8
1.695	0.118	tHld		1	BSRAM_R10[1]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_8

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.270, 57.203%; tC2Q: 0.202, 42.797%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path15

Path Summary:

Slack	0.354
Data Arrival Time	2.049
Data Required Time	1.695
From	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[6]
To	u_la0_top/u_ao_mem_ctrl/mem_mem_0_13
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	497	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R8C10[0][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[6]/CLK
1.779	0.202	tC2Q	RR	51	R8C10[0][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[6]/Q
2.049	0.270	tNET	RR	1	BSRAM_R10[2]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_13/ADA7

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	497	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	BSRAM_R10[2]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_13/CLKA
1.577	0.000	tUnc				u_la0_top/u_ao_mem_ctrl/mem_mem_0_13
1.695	0.118	tHld		1	BSRAM_R10[2]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_13

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.270, 57.208%; tC2Q: 0.202, 42.792%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path16

Path Summary:

Slack	0.355
Data Arrival Time	2.051
Data Required Time	1.695
From	cnt_Z[2]
To	memr_memr_0_5
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	497	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R46C43[2][B]	cnt_Z[2]/CLK
1.779	0.202	tC2Q	RR	18	R46C43[2][B]	cnt_Z[2]/Q
2.051	0.271	tNET	RR	1	BSRAM_R45[13]	memr_memr_0_5/ADA3

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	497	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	BSRAM_R45[13]	memr_memr_0_5/CLKA
1.577	0.000	tUnc				memr_memr_0_5
1.695	0.118	tHld		1	BSRAM_R45[13]	memr_memr_0_5

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.271, 57.314%; tC2Q: 0.202, 42.686%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path17

Path Summary:

Slack	0.355
Data Arrival Time	2.051
Data Required Time	1.695
From	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8]
To	u_la0_top/u_ao_mem_ctrl/mem_mem_0_8
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	497	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R11C6[2][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8]/CLK
1.779	0.202	tC2Q	RR	51	R11C6[2][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8]/Q
2.051	0.271	tNET	RR	1	BSRAM_R10[1]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_8/ADA9

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	497	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	BSRAM_R10[1]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_8/CLKA
1.577	0.000	tUnc				u_la0_top/u_ao_mem_ctrl/mem_mem_0_8
1.695	0.118	tHld		1	BSRAM_R10[1]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_8

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.271, 57.319%; tC2Q: 0.202, 42.681%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path18

Path Summary:

Slack	0.361
Data Arrival Time	2.057
Data Required Time	1.695
From	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[2]
To	u_la0_top/u_ao_mem_ctrl/mem_mem_0_13
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	497	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R9C8[1][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[2]/CLK
1.779	0.202	tC2Q	RR	51	R9C8[1][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[2]/Q
2.057	0.277	tNET	RR	1	BSRAM_R10[2]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_13/ADA3

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	497	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	BSRAM_R10[2]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_13/CLKA
1.577	0.000	tUnc				u_la0_top/u_ao_mem_ctrl/mem_mem_0_13
1.695	0.118	tHld		1	BSRAM_R10[2]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_13

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.277, 57.861%; tC2Q: 0.202, 42.139%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path19

Path Summary:

Slack	0.361
Data Arrival Time	2.057
Data Required Time	1.695
From	cnt_1_Z[10]
To	memr_memr_0_5
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	497	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R44C45[0][A]	cnt_1_Z[10]/CLK
1.779	0.202	tC2Q	RR	17	R44C45[0][A]	cnt_1_Z[10]/Q
2.057	0.277	tNET	RR	1	BSRAM_R45[13]	memr_memr_0_5/ADB11

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	497	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	BSRAM_R45[13]	memr_memr_0_5/CLKB
1.577	0.000	tUnc				memr_memr_0_5
1.695	0.118	tHld		1	BSRAM_R45[13]	memr_memr_0_5

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.277, 57.861%; tC2Q: 0.202, 42.139%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path20

Path Summary:

Slack	0.363
Data Arrival Time	2.058
Data Required Time	1.695
From	cnt_1_Z[3]
To	memr_memr_0_12
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	497	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R44C43[2][B]	cnt_1_Z[3]/CLK
1.779	0.202	tC2Q	RR	17	R44C43[2][B]	cnt_1_Z[3]/Q
2.058	0.279	tNET	RR	1	BSRAM_R45[14]	memr_memr_0_12/ADB4

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	497	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	BSRAM_R45[14]	memr_memr_0_12/CLKB
1.577	0.000	tUnc				memr_memr_0_12
1.695	0.118	tHld		1	BSRAM_R45[14]	memr_memr_0_12

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.279, 57.968%; tC2Q: 0.202, 42.032%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path21

Path Summary:

Slack	0.363
Data Arrival Time	2.059
Data Required Time	1.695
From	cnt_Z[9]
To	memr_memr_0_14
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	497	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R46C45[0][A]	cnt_Z[9]/CLK
1.779	0.202	tC2Q	RR	18	R46C45[0][A]	cnt_Z[9]/Q
2.059	0.279	tNET	RR	1	BSRAM_R45[15]	memr_memr_0_14/ADA10

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	497	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	BSRAM_R45[15]	memr_memr_0_14/CLKA
1.577	0.000	tUnc				memr_memr_0_14
1.695	0.118	tHld		1	BSRAM_R45[15]	memr_memr_0_14

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.279, 58.042%; tC2Q: 0.202, 41.958%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path22

Path Summary:

Slack	0.363
Data Arrival Time	2.059
Data Required Time	1.695
From	cnt_1_Z[11]
To	memr_memr_0_9
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	497	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R44C45[0][B]	cnt_1_Z[11]/CLK
1.779	0.202	tC2Q	RR	17	R44C45[0][B]	cnt_1_Z[11]/Q
2.059	0.279	tNET	RR	1	BSRAM_R36[13]	memr_memr_0_9/ADB12

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	497	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	BSRAM_R36[13]	memr_memr_0_9/CLKB
1.577	0.000	tUnc				memr_memr_0_9
1.695	0.118	tHld		1	BSRAM_R36[13]	memr_memr_0_9

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.279, 58.042%; tC2Q: 0.202, 41.958%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path23

Path Summary:

Slack	0.364
Data Arrival Time	2.059
Data Required Time	1.695
From	cnt_1_Z[1]
To	memr_memr_0_7
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	497	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R44C43[1][B]	cnt_1_Z[1]/CLK
1.779	0.202	tC2Q	RR	17	R44C43[1][B]	cnt_1_Z[1]/Q
2.059	0.280	tNET	RR	1	BSRAM_R36[12]	memr_memr_0_7/ADB2

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	497	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	BSRAM_R36[12]	memr_memr_0_7/CLKB
1.577	0.000	tUnc				memr_memr_0_7
1.695	0.118	tHld		1	BSRAM_R36[12]	memr_memr_0_7

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.280, 58.058%; tC2Q: 0.202, 41.942%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path24

Path Summary:

Slack	0.364
Data Arrival Time	2.059
Data Required Time	1.695
From	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[11]
To	u_la0_top/u_ao_mem_ctrl/mem_mem_0_3
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	497	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R9C2[2][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[11]/CLK
1.779	0.202	tC2Q	RR	51	R9C2[2][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[11]/Q
2.059	0.280	tNET	RR	1	BSRAM_R10[0]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_3/ADA12

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	497	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	BSRAM_R10[0]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_3/CLKA
1.577	0.000	tUnc				u_la0_top/u_ao_mem_ctrl/mem_mem_0_3
1.695	0.118	tHld		1	BSRAM_R10[0]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_3

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.280, 58.075%; tC2Q: 0.202, 41.925%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path25

Path Summary:

Slack	0.364
Data Arrival Time	2.060
Data Required Time	1.695
From	cnt_1_Z[10]
To	memr_memr_0_14
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	497	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R44C45[0][A]	cnt_1_Z[10]/CLK
1.779	0.202	tC2Q	RR	17	R44C45[0][A]	cnt_1_Z[10]/Q
2.060	0.280	tNET	RR	1	BSRAM_R45[15]	memr_memr_0_14/ADB11

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	497	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	BSRAM_R45[15]	memr_memr_0_14/CLKB
1.577	0.000	tUnc				memr_memr_0_14
1.695	0.118	tHld		1	BSRAM_R45[15]	memr_memr_0_14

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.280, 58.123%; tC2Q: 0.202, 41.877%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Recovery Analysis Report

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	1.748
Data Arrival Time	9.900
Data Required Time	11.648
From	u_la0_top/rst_ao_Z
To	u_la0_top/triger_level_cnt_Z[0]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.688	0.688	tINS	FF	497	IOT48[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R7C10[1][B]	u_la0_top/rst_ao_Z/CLK
7.148	0.232	tC2Q	FF	49	R7C10[1][B]	u_la0_top/rst_ao_Z/Q
9.900	2.752	tNET	FF	1	R12C6[2][B]	u_la0_top/triger_level_cnt_Z[0]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	497	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R12C6[2][B]	u_la0_top/triger_level_cnt_Z[0]/CLK
11.683	-0.200	tUnc				u_la0_top/triger_level_cnt_Z[0]
11.648	-0.035	tSu		1	R12C6[2][B]	u_la0_top/triger_level_cnt_Z[0]

Path Statistics:

Clock Skew	-0.033
Setup Relationship	5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.752, 92.227%; tC2Q: 0.232, 7.773%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path2

Path Summary:

Slack	1.748
Data Arrival Time	9.900
Data Required Time	11.648
From	u_la0_top/rst_ao_Z
To	u_la0_top/triger_level_cnt_Z[2]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.688	0.688	tINS	FF	497	IOT48[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R7C10[1][B]	u_la0_top/rst_ao_Z/CLK
7.148	0.232	tC2Q	FF	49	R7C10[1][B]	u_la0_top/rst_ao_Z/Q
9.900	2.752	tNET	FF	1	R12C7[0][B]	u_la0_top/triger_level_cnt_Z[2]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	497	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R12C7[0][B]	u_la0_top/triger_level_cnt_Z[2]/CLK
11.683	-0.200	tUnc				u_la0_top/triger_level_cnt_Z[2]
11.648	-0.035	tSu		1	R12C7[0][B]	u_la0_top/triger_level_cnt_Z[2]

Path Statistics:

Clock Skew	-0.033
Setup Relationship	5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.752, 92.227%; tC2Q: 0.232, 7.773%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path3

Path Summary:

Slack	1.748
Data Arrival Time	9.900
Data Required Time	11.648
From	u_la0_top/rst_ao_Z
To	u_la0_top/capture_window_sel[3]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.688	0.688	tINS	FF	497	IOT48[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R7C10[1][B]	u_la0_top/rst_ao_Z/CLK
7.148	0.232	tC2Q	FF	49	R7C10[1][B]	u_la0_top/rst_ao_Z/Q
9.900	2.752	tNET	FF	1	R12C6[2][A]	u_la0_top/capture_window_sel[3]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	497	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R12C6[2][A]	u_la0_top/capture_window_sel[3]/CLK
11.683	-0.200	tUnc				u_la0_top/capture_window_sel[3]
11.648	-0.035	tSu		1	R12C6[2][A]	u_la0_top/capture_window_sel[3]

Path Statistics:

Clock Skew	-0.033
Setup Relationship	5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.752, 92.227%; tC2Q: 0.232, 7.773%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path4

Path Summary:

Slack	1.748
Data Arrival Time	9.900
Data Required Time	11.648
From	u_la0_top/rst_ao_Z
To	u_la0_top/internal_reg_force_triger_syn_Z[0]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.688	0.688	tINS	FF	497	IOT48[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R7C10[1][B]	u_la0_top/rst_ao_Z/CLK
7.148	0.232	tC2Q	FF	49	R7C10[1][B]	u_la0_top/rst_ao_Z/Q
9.900	2.752	tNET	FF	1	R3C2[1][A]	u_la0_top/internal_reg_force_triger_syn_Z[0]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	497	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R3C2[1][A]	u_la0_top/internal_reg_force_triger_syn_Z[0]/CLK
11.683	-0.200	tUnc				u_la0_top/internal_reg_force_triger_syn_Z[0]
11.648	-0.035	tSu		1	R3C2[1][A]	u_la0_top/internal_reg_force_triger_syn_Z[0]

Path Statistics:

Clock Skew	-0.033
Setup Relationship	5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.752, 92.227%; tC2Q: 0.232, 7.773%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path5

Path Summary:

Slack	1.748
Data Arrival Time	9.900
Data Required Time	11.648
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_length_Z[12]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.688	0.688	tINS	FF	497	IOT48[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R7C10[1][B]	u_la0_top/rst_ao_Z/CLK
7.148	0.232	tC2Q	FF	49	R7C10[1][B]	u_la0_top/rst_ao_Z/Q
9.900	2.752	tNET	FF	1	R2C5[0][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[12]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	497	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R2C5[0][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[12]/CLK
11.683	-0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_length_Z[12]
11.648	-0.035	tSu		1	R2C5[0][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[12]

Path Statistics:

Clock Skew	-0.033
Setup Relationship	5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.752, 92.227%; tC2Q: 0.232, 7.773%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path6

Path Summary:

Slack	1.748
Data Arrival Time	9.900
Data Required Time	11.648
From	u_la0_top/rst_ao_Z
To	u_la0_top/internal_reg_start_syn_Z[0]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.688	0.688	tINS	FF	497	IOT48[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R7C10[1][B]	u_la0_top/rst_ao_Z/CLK
7.148	0.232	tC2Q	FF	49	R7C10[1][B]	u_la0_top/rst_ao_Z/Q
9.900	2.752	tNET	FF	1	R12C8[1][B]	u_la0_top/internal_reg_start_syn_Z[0]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	497	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R12C8[1][B]	u_la0_top/internal_reg_start_syn_Z[0]/CLK
11.683	-0.200	tUnc				u_la0_top/internal_reg_start_syn_Z[0]
11.648	-0.035	tSu		1	R12C8[1][B]	u_la0_top/internal_reg_start_syn_Z[0]

Path Statistics:

Clock Skew	-0.033
Setup Relationship	5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.752, 92.227%; tC2Q: 0.232, 7.773%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path7

Path Summary:

Slack	1.748
Data Arrival Time	9.900
Data Required Time	11.648
From	u_la0_top/rst_ao_Z
To	u_la0_top/internal_reg_start_dly_Z[0]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.688	0.688	tINS	FF	497	IOT48[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R7C10[1][B]	u_la0_top/rst_ao_Z/CLK
7.148	0.232	tC2Q	FF	49	R7C10[1][B]	u_la0_top/rst_ao_Z/Q
9.900	2.752	tNET	FF	1	R5C3[2][A]	u_la0_top/internal_reg_start_dly_Z[0]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	497	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R5C3[2][A]	u_la0_top/internal_reg_start_dly_Z[0]/CLK
11.683	-0.200	tUnc				u_la0_top/internal_reg_start_dly_Z[0]
11.648	-0.035	tSu		1	R5C3[2][A]	u_la0_top/internal_reg_start_dly_Z[0]

Path Statistics:

Clock Skew	-0.033
Setup Relationship	5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.752, 92.227%; tC2Q: 0.232, 7.773%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path8

Path Summary:

Slack	1.748
Data Arrival Time	9.900
Data Required Time	11.648
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.688	0.688	tINS	FF	497	IOT48[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R7C10[1][B]	u_la0_top/rst_ao_Z/CLK
7.148	0.232	tC2Q	FF	49	R7C10[1][B]	u_la0_top/rst_ao_Z/Q
9.900	2.752	tNET	FF	1	R11C8[0][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	497	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R11C8[0][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z/CLK
11.683	-0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z
11.648	-0.035	tSu		1	R11C8[0][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z

Path Statistics:

Clock Skew	-0.033
Setup Relationship	5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.752, 92.227%; tC2Q: 0.232, 7.773%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path9

Path Summary:

Slack	1.748
Data Arrival Time	9.900
Data Required Time	11.648
From	u_la0_top/rst_ao_Z
To	u_la0_top/capture_window_sel_Z[2]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.688	0.688	tINS	FF	497	IOT48[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R7C10[1][B]	u_la0_top/rst_ao_Z/CLK
7.148	0.232	tC2Q	FF	49	R7C10[1][B]	u_la0_top/rst_ao_Z/Q
9.900	2.752	tNET	FF	1	R8C9[2][B]	u_la0_top/capture_window_sel_Z[2]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	497	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R8C9[2][B]	u_la0_top/capture_window_sel_Z[2]/CLK
11.683	-0.200	tUnc				u_la0_top/capture_window_sel_Z[2]
11.648	-0.035	tSu		1	R8C9[2][B]	u_la0_top/capture_window_sel_Z[2]

Path Statistics:

Clock Skew	-0.033
Setup Relationship	5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.752, 92.227%; tC2Q: 0.232, 7.773%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path10

Path Summary:

Slack	1.748
Data Arrival Time	9.900
Data Required Time	11.648
From	u_la0_top/rst_ao_Z
To	u_la0_top/capture_end_dly_Z
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.688	0.688	tINS	FF	497	IOT48[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R7C10[1][B]	u_la0_top/rst_ao_Z/CLK
7.148	0.232	tC2Q	FF	49	R7C10[1][B]	u_la0_top/rst_ao_Z/Q
9.900	2.752	tNET	FF	1	R7C10[2][A]	u_la0_top/capture_end_dly_Z/PRESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	497	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R7C10[2][A]	u_la0_top/capture_end_dly_Z/CLK
11.683	-0.200	tUnc				u_la0_top/capture_end_dly_Z
11.648	-0.035	tSu		1	R7C10[2][A]	u_la0_top/capture_end_dly_Z

Path Statistics:

Clock Skew	-0.033
Setup Relationship	5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.752, 92.227%; tC2Q: 0.232, 7.773%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path11

Path Summary:

Slack	1.748
Data Arrival Time	9.900
Data Required Time	11.648
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.688	0.688	tINS	FF	497	IOT48[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R7C10[1][B]	u_la0_top/rst_ao_Z/CLK
7.148	0.232	tC2Q	FF	49	R7C10[1][B]	u_la0_top/rst_ao_Z/Q
9.900	2.752	tNET	FF	1	R9C8[0][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	497	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R9C8[0][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0]/CLK
11.683	-0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0]
11.648	-0.035	tSu		1	R9C8[0][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0]

Path Statistics:

Clock Skew	-0.033
Setup Relationship	5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.752, 92.227%; tC2Q: 0.232, 7.773%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path12

Path Summary:

Slack	1.748
Data Arrival Time	9.900
Data Required Time	11.648
From	u_la0_top/rst_ao_Z
To	u_la0_top/capture_window_sel_Z[1]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.688	0.688	tINS	FF	497	IOT48[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R7C10[1][B]	u_la0_top/rst_ao_Z/CLK
7.148	0.232	tC2Q	FF	49	R7C10[1][B]	u_la0_top/rst_ao_Z/Q
9.900	2.752	tNET	FF	1	R8C9[2][A]	u_la0_top/capture_window_sel_Z[1]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	497	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R8C9[2][A]	u_la0_top/capture_window_sel_Z[1]/CLK
11.683	-0.200	tUnc				u_la0_top/capture_window_sel_Z[1]
11.648	-0.035	tSu		1	R8C9[2][A]	u_la0_top/capture_window_sel_Z[1]

Path Statistics:

Clock Skew	-0.033
Setup Relationship	5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.752, 92.227%; tC2Q: 0.232, 7.773%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path13

Path Summary:

Slack	1.748
Data Arrival Time	9.900
Data Required Time	11.648
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_length_Z[4]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.688	0.688	tINS	FF	497	IOT48[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R7C10[1][B]	u_la0_top/rst_ao_Z/CLK
7.148	0.232	tC2Q	FF	49	R7C10[1][B]	u_la0_top/rst_ao_Z/Q
9.900	2.752	tNET	FF	1	R8C2[1][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[4]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	497	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R8C2[1][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[4]/CLK
11.683	-0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_length_Z[4]
11.648	-0.035	tSu		1	R8C2[1][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[4]

Path Statistics:

Clock Skew	-0.033
Setup Relationship	5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.752, 92.227%; tC2Q: 0.232, 7.773%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path14

Path Summary:

Slack	1.748
Data Arrival Time	9.900
Data Required Time	11.648
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_length_Z[3]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.688	0.688	tINS	FF	497	IOT48[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R7C10[1][B]	u_la0_top/rst_ao_Z/CLK
7.148	0.232	tC2Q	FF	49	R7C10[1][B]	u_la0_top/rst_ao_Z/Q
9.900	2.752	tNET	FF	1	R6C10[2][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[3]/PRESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	497	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R6C10[2][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[3]/CLK
11.683	-0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_length_Z[3]
11.648	-0.035	tSu		1	R6C10[2][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[3]

Path Statistics:

Clock Skew	-0.033
Setup Relationship	5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.752, 92.227%; tC2Q: 0.232, 7.773%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path15

Path Summary:

Slack	1.748
Data Arrival Time	9.900
Data Required Time	11.648
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_length_Z[9]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.688	0.688	tINS	FF	497	IOT48[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R7C10[1][B]	u_la0_top/rst_ao_Z/CLK
7.148	0.232	tC2Q	FF	49	R7C10[1][B]	u_la0_top/rst_ao_Z/Q
9.900	2.752	tNET	FF	1	R7C10[2][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[9]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	497	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R7C10[2][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[9]/CLK
11.683	-0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_length_Z[9]
11.648	-0.035	tSu		1	R7C10[2][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[9]

Path Statistics:

Clock Skew	-0.033
Setup Relationship	5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.752, 92.227%; tC2Q: 0.232, 7.773%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path16

Path Summary:

Slack	1.748
Data Arrival Time	9.900
Data Required Time	11.648
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[12]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.688	0.688	tINS	FF	497	IOT48[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R7C10[1][B]	u_la0_top/rst_ao_Z/CLK
7.148	0.232	tC2Q	FF	49	R7C10[1][B]	u_la0_top/rst_ao_Z/Q
9.900	2.752	tNET	FF	1	R9C2[2][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[12]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	497	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R9C2[2][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[12]/CLK
11.683	-0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[12]
11.648	-0.035	tSu		1	R9C2[2][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[12]

Path Statistics:

Clock Skew	-0.033
Setup Relationship	5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.752, 92.227%; tC2Q: 0.232, 7.773%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path17

Path Summary:

Slack	1.748
Data Arrival Time	9.900
Data Required Time	11.648
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[2]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.688	0.688	tINS	FF	497	IOT48[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R7C10[1][B]	u_la0_top/rst_ao_Z/CLK
7.148	0.232	tC2Q	FF	49	R7C10[1][B]	u_la0_top/rst_ao_Z/Q
9.900	2.752	tNET	FF	1	R9C8[1][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[2]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	497	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R9C8[1][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[2]/CLK
11.683	-0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[2]
11.648	-0.035	tSu		1	R9C8[1][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[2]

Path Statistics:

Clock Skew	-0.033
Setup Relationship	5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.752, 92.227%; tC2Q: 0.232, 7.773%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path18

Path Summary:

Slack	1.748
Data Arrival Time	9.900
Data Required Time	11.648
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[1]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.688	0.688	tINS	FF	497	IOT48[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R7C10[1][B]	u_la0_top/rst_ao_Z/CLK
7.148	0.232	tC2Q	FF	49	R7C10[1][B]	u_la0_top/rst_ao_Z/Q
9.900	2.752	tNET	FF	1	R9C8[0][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[1]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	497	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R9C8[0][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[1]/CLK
11.683	-0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[1]
11.648	-0.035	tSu		1	R9C8[0][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[1]

Path Statistics:

Clock Skew	-0.033
Setup Relationship	5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.752, 92.227%; tC2Q: 0.232, 7.773%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path19

Path Summary:

Slack	1.748
Data Arrival Time	9.900
Data Required Time	11.648
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_length_Z[7]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.688	0.688	tINS	FF	497	IOT48[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R7C10[1][B]	u_la0_top/rst_ao_Z/CLK
7.148	0.232	tC2Q	FF	49	R7C10[1][B]	u_la0_top/rst_ao_Z/Q
9.900	2.752	tNET	FF	1	R8C10[1][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[7]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	497	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R8C10[1][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[7]/CLK
11.683	-0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_length_Z[7]
11.648	-0.035	tSu		1	R8C10[1][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[7]

Path Statistics:

Clock Skew	-0.033
Setup Relationship	5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.752, 92.227%; tC2Q: 0.232, 7.773%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path20

Path Summary:

Slack	1.748
Data Arrival Time	9.900
Data Required Time	11.648
From	u_la0_top/rst_ao_Z
To	u_la0_top/trigger_seq_start_Z
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.688	0.688	tINS	FF	497	IOT48[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R7C10[1][B]	u_la0_top/rst_ao_Z/CLK
7.148	0.232	tC2Q	FF	49	R7C10[1][B]	u_la0_top/rst_ao_Z/Q
9.900	2.752	tNET	FF	1	R3C2[0][A]	u_la0_top/trigger_seq_start_Z/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	497	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R3C2[0][A]	u_la0_top/trigger_seq_start_Z/CLK
11.683	-0.200	tUnc				u_la0_top/trigger_seq_start_Z
11.648	-0.035	tSu		1	R3C2[0][A]	u_la0_top/trigger_seq_start_Z

Path Statistics:

Clock Skew	-0.033
Setup Relationship	5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.752, 92.227%; tC2Q: 0.232, 7.773%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path21

Path Summary:

Slack	1.748
Data Arrival Time	9.900
Data Required Time	11.648
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[9]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.688	0.688	tINS	FF	497	IOT48[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R7C10[1][B]	u_la0_top/rst_ao_Z/CLK
7.148	0.232	tC2Q	FF	49	R7C10[1][B]	u_la0_top/rst_ao_Z/Q
9.900	2.752	tNET	FF	1	R11C2[2][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[9]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	497	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R11C2[2][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[9]/CLK
11.683	-0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[9]
11.648	-0.035	tSu		1	R11C2[2][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[9]

Path Statistics:

Clock Skew	-0.033
Setup Relationship	5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.752, 92.227%; tC2Q: 0.232, 7.773%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path22

Path Summary:

Slack	1.748
Data Arrival Time	9.900
Data Required Time	11.648
From	u_la0_top/rst_ao_Z
To	u_la0_top/genblk1.u_ao_match_0/match_sep
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.688	0.688	tINS	FF	497	IOT48[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R7C10[1][B]	u_la0_top/rst_ao_Z/CLK
7.148	0.232	tC2Q	FF	49	R7C10[1][B]	u_la0_top/rst_ao_Z/Q
9.900	2.752	tNET	FF	1	R9C8[2][B]	u_la0_top/genblk1.u_ao_match_0/match_sep/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	497	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R9C8[2][B]	u_la0_top/genblk1.u_ao_match_0/match_sep/CLK
11.683	-0.200	tUnc				u_la0_top/genblk1.u_ao_match_0/match_sep
11.648	-0.035	tSu		1	R9C8[2][B]	u_la0_top/genblk1.u_ao_match_0/match_sep

Path Statistics:

Clock Skew	-0.033
Setup Relationship	5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.752, 92.227%; tC2Q: 0.232, 7.773%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path23

Path Summary:

Slack	1.748
Data Arrival Time	9.900
Data Required Time	11.648
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[3]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.688	0.688	tINS	FF	497	IOT48[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R7C10[1][B]	u_la0_top/rst_ao_Z/CLK
7.148	0.232	tC2Q	FF	49	R7C10[1][B]	u_la0_top/rst_ao_Z/Q
9.900	2.752	tNET	FF	1	R8C10[0][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[3]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	497	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R8C10[0][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[3]/CLK
11.683	-0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[3]
11.648	-0.035	tSu		1	R8C10[0][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[3]

Path Statistics:

Clock Skew	-0.033
Setup Relationship	5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.752, 92.227%; tC2Q: 0.232, 7.773%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path24

Path Summary:

Slack	1.748
Data Arrival Time	9.900
Data Required Time	11.648
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.688	0.688	tINS	FF	497	IOT48[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R7C10[1][B]	u_la0_top/rst_ao_Z/CLK
7.148	0.232	tC2Q	FF	49	R7C10[1][B]	u_la0_top/rst_ao_Z/Q
9.900	2.752	tNET	FF	1	R11C6[2][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	497	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R11C6[2][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8]/CLK
11.683	-0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8]
11.648	-0.035	tSu		1	R11C6[2][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8]

Path Statistics:

Clock Skew	-0.033
Setup Relationship	5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.752, 92.227%; tC2Q: 0.232, 7.773%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path25

Path Summary:

Slack	1.748
Data Arrival Time	9.900
Data Required Time	11.648
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_length_Z[2]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.688	0.688	tINS	FF	497	IOT48[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R7C10[1][B]	u_la0_top/rst_ao_Z/CLK
7.148	0.232	tC2Q	FF	49	R7C10[1][B]	u_la0_top/rst_ao_Z/Q
9.900	2.752	tNET	FF	1	R6C10[2][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[2]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	497	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R6C10[2][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[2]/CLK
11.683	-0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_length_Z[2]
11.648	-0.035	tSu		1	R6C10[2][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[2]

Path Statistics:

Clock Skew	-0.033
Setup Relationship	5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.752, 92.227%; tC2Q: 0.232, 7.773%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Removal Analysis Report

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	6.760
Data Arrival Time	8.548
Data Required Time	1.788
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.677	0.678	tINS	FF	497	IOT48[A]	clk_ibuf/O
6.590	0.913	tNET	FF	1	R7C10[1][B]	u_la0_top/rst_ao_Z/CLK
6.792	0.202	tC2Q	FR	49	R7C10[1][B]	u_la0_top/rst_ao_Z/Q
8.548	1.756	tNET	RR	1	R11C8[0][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	497	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R11C8[0][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z/CLK
1.777	0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z
1.788	0.011	tHld		1	R11C8[0][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.756, 89.683%; tC2Q: 0.202, 10.317%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path2

Path Summary:

Slack	6.760
Data Arrival Time	8.548
Data Required Time	1.788
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_Z
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.677	0.678	tINS	FF	497	IOT48[A]	clk_ibuf/O
6.590	0.913	tNET	FF	1	R7C10[1][B]	u_la0_top/rst_ao_Z/CLK
6.792	0.202	tC2Q	FR	49	R7C10[1][B]	u_la0_top/rst_ao_Z/Q
8.548	1.756	tNET	RR	1	R2C5[1][A]	u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_Z/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	497	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R2C5[1][A]	u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_Z/CLK
1.777	0.200	tUnc				u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_Z
1.788	0.011	tHld		1	R2C5[1][A]	u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_Z

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.756, 89.683%; tC2Q: 0.202, 10.317%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path3

Path Summary:

Slack	6.760
Data Arrival Time	8.548
Data Required Time	1.788
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_loop_Z
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.677	0.678	tINS	FF	497	IOT48[A]	clk_ibuf/O
6.590	0.913	tNET	FF	1	R7C10[1][B]	u_la0_top/rst_ao_Z/CLK
6.792	0.202	tC2Q	FR	49	R7C10[1][B]	u_la0_top/rst_ao_Z/Q
8.548	1.756	tNET	RR	1	R11C7[2][A]	u_la0_top/u_ao_mem_ctrl/capture_loop_Z/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	497	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R11C7[2][A]	u_la0_top/u_ao_mem_ctrl/capture_loop_Z/CLK
1.777	0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_loop_Z
1.788	0.011	tHld		1	R11C7[2][A]	u_la0_top/u_ao_mem_ctrl/capture_loop_Z

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.756, 89.683%; tC2Q: 0.202, 10.317%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path4

Path Summary:

Slack	6.760
Data Arrival Time	8.548
Data Required Time	1.788
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_length_Z[0]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.677	0.678	tINS	FF	497	IOT48[A]	clk_ibuf/O
6.590	0.913	tNET	FF	1	R7C10[1][B]	u_la0_top/rst_ao_Z/CLK
6.792	0.202	tC2Q	FR	49	R7C10[1][B]	u_la0_top/rst_ao_Z/Q
8.548	1.756	tNET	RR	1	R8C10[2][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[0]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	497	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R8C10[2][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[0]/CLK
1.777	0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_length_Z[0]
1.788	0.011	tHld		1	R8C10[2][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[0]

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.756, 89.683%; tC2Q: 0.202, 10.317%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path5

Path Summary:

Slack	6.760
Data Arrival Time	8.548
Data Required Time	1.788
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_length_Z[1]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.677	0.678	tINS	FF	497	IOT48[A]	clk_ibuf/O
6.590	0.913	tNET	FF	1	R7C10[1][B]	u_la0_top/rst_ao_Z/CLK
6.792	0.202	tC2Q	FR	49	R7C10[1][B]	u_la0_top/rst_ao_Z/Q
8.548	1.756	tNET	RR	1	R8C10[2][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[1]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	497	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R8C10[2][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[1]/CLK
1.777	0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_length_Z[1]
1.788	0.011	tHld		1	R8C10[2][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[1]

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.756, 89.683%; tC2Q: 0.202, 10.317%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path6

Path Summary:

Slack	6.760
Data Arrival Time	8.548
Data Required Time	1.788
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_length_Z[2]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.677	0.678	tINS	FF	497	IOT48[A]	clk_ibuf/O
6.590	0.913	tNET	FF	1	R7C10[1][B]	u_la0_top/rst_ao_Z/CLK
6.792	0.202	tC2Q	FR	49	R7C10[1][B]	u_la0_top/rst_ao_Z/Q
8.548	1.756	tNET	RR	1	R6C10[2][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[2]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	497	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R6C10[2][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[2]/CLK
1.777	0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_length_Z[2]
1.788	0.011	tHld		1	R6C10[2][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[2]

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.756, 89.683%; tC2Q: 0.202, 10.317%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path7

Path Summary:

Slack	6.760
Data Arrival Time	8.548
Data Required Time	1.788
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_length_Z[3]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.677	0.678	tINS	FF	497	IOT48[A]	clk_ibuf/O
6.590	0.913	tNET	FF	1	R7C10[1][B]	u_la0_top/rst_ao_Z/CLK
6.792	0.202	tC2Q	FR	49	R7C10[1][B]	u_la0_top/rst_ao_Z/Q
8.548	1.756	tNET	RR	1	R6C10[2][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[3]/PRESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	497	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R6C10[2][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[3]/CLK
1.777	0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_length_Z[3]
1.788	0.011	tHld		1	R6C10[2][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[3]

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.756, 89.683%; tC2Q: 0.202, 10.317%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path8

Path Summary:

Slack	6.760
Data Arrival Time	8.548
Data Required Time	1.788
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_length_Z[4]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.677	0.678	tINS	FF	497	IOT48[A]	clk_ibuf/O
6.590	0.913	tNET	FF	1	R7C10[1][B]	u_la0_top/rst_ao_Z/CLK
6.792	0.202	tC2Q	FR	49	R7C10[1][B]	u_la0_top/rst_ao_Z/Q
8.548	1.756	tNET	RR	1	R8C2[1][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[4]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	497	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R8C2[1][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[4]/CLK
1.777	0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_length_Z[4]
1.788	0.011	tHld		1	R8C2[1][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[4]

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.756, 89.683%; tC2Q: 0.202, 10.317%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path9

Path Summary:

Slack	6.760
Data Arrival Time	8.548
Data Required Time	1.788
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_length_Z[5]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.677	0.678	tINS	FF	497	IOT48[A]	clk_ibuf/O
6.590	0.913	tNET	FF	1	R7C10[1][B]	u_la0_top/rst_ao_Z/CLK
6.792	0.202	tC2Q	FR	49	R7C10[1][B]	u_la0_top/rst_ao_Z/Q
8.548	1.756	tNET	RR	1	R8C2[1][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[5]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	497	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R8C2[1][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[5]/CLK
1.777	0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_length_Z[5]
1.788	0.011	tHld		1	R8C2[1][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[5]

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.756, 89.683%; tC2Q: 0.202, 10.317%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path10

Path Summary:

Slack	6.760
Data Arrival Time	8.548
Data Required Time	1.788
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_length_Z[6]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.677	0.678	tINS	FF	497	IOT48[A]	clk_ibuf/O
6.590	0.913	tNET	FF	1	R7C10[1][B]	u_la0_top/rst_ao_Z/CLK
6.792	0.202	tC2Q	FR	49	R7C10[1][B]	u_la0_top/rst_ao_Z/Q
8.548	1.756	tNET	RR	1	R3C2[1][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[6]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	497	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R3C2[1][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[6]/CLK
1.777	0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_length_Z[6]
1.788	0.011	tHld		1	R3C2[1][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[6]

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.756, 89.683%; tC2Q: 0.202, 10.317%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path11

Path Summary:

Slack	6.760
Data Arrival Time	8.548
Data Required Time	1.788
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_length_Z[7]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.677	0.678	tINS	FF	497	IOT48[A]	clk_ibuf/O
6.590	0.913	tNET	FF	1	R7C10[1][B]	u_la0_top/rst_ao_Z/CLK
6.792	0.202	tC2Q	FR	49	R7C10[1][B]	u_la0_top/rst_ao_Z/Q
8.548	1.756	tNET	RR	1	R8C10[1][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[7]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	497	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R8C10[1][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[7]/CLK
1.777	0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_length_Z[7]
1.788	0.011	tHld		1	R8C10[1][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[7]

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.756, 89.683%; tC2Q: 0.202, 10.317%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path12

Path Summary:

Slack	6.760
Data Arrival Time	8.548
Data Required Time	1.788
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_length_Z[8]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.677	0.678	tINS	FF	497	IOT48[A]	clk_ibuf/O
6.590	0.913	tNET	FF	1	R7C10[1][B]	u_la0_top/rst_ao_Z/CLK
6.792	0.202	tC2Q	FR	49	R7C10[1][B]	u_la0_top/rst_ao_Z/Q
8.548	1.756	tNET	RR	1	R8C10[1][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[8]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	497	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R8C10[1][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[8]/CLK
1.777	0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_length_Z[8]
1.788	0.011	tHld		1	R8C10[1][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[8]

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.756, 89.683%; tC2Q: 0.202, 10.317%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path13

Path Summary:

Slack	6.760
Data Arrival Time	8.548
Data Required Time	1.788
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_length_Z[9]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.677	0.678	tINS	FF	497	IOT48[A]	clk_ibuf/O
6.590	0.913	tNET	FF	1	R7C10[1][B]	u_la0_top/rst_ao_Z/CLK
6.792	0.202	tC2Q	FR	49	R7C10[1][B]	u_la0_top/rst_ao_Z/Q
8.548	1.756	tNET	RR	1	R7C10[2][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[9]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	497	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R7C10[2][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[9]/CLK
1.777	0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_length_Z[9]
1.788	0.011	tHld		1	R7C10[2][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[9]

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.756, 89.683%; tC2Q: 0.202, 10.317%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path14

Path Summary:

Slack	6.760
Data Arrival Time	8.548
Data Required Time	1.788
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_length_Z[10]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.677	0.678	tINS	FF	497	IOT48[A]	clk_ibuf/O
6.590	0.913	tNET	FF	1	R7C10[1][B]	u_la0_top/rst_ao_Z/CLK
6.792	0.202	tC2Q	FR	49	R7C10[1][B]	u_la0_top/rst_ao_Z/Q
8.548	1.756	tNET	RR	1	R3C3[2][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[10]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	497	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R3C3[2][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[10]/CLK
1.777	0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_length_Z[10]
1.788	0.011	tHld		1	R3C3[2][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[10]

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.756, 89.683%; tC2Q: 0.202, 10.317%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path15

Path Summary:

Slack	6.760
Data Arrival Time	8.548
Data Required Time	1.788
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_length_Z[11]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.677	0.678	tINS	FF	497	IOT48[A]	clk_ibuf/O
6.590	0.913	tNET	FF	1	R7C10[1][B]	u_la0_top/rst_ao_Z/CLK
6.792	0.202	tC2Q	FR	49	R7C10[1][B]	u_la0_top/rst_ao_Z/Q
8.548	1.756	tNET	RR	1	R3C3[2][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[11]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	497	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R3C3[2][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[11]/CLK
1.777	0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_length_Z[11]
1.788	0.011	tHld		1	R3C3[2][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[11]

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.756, 89.683%; tC2Q: 0.202, 10.317%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path16

Path Summary:

Slack	6.760
Data Arrival Time	8.548
Data Required Time	1.788
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_length_Z[12]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.677	0.678	tINS	FF	497	IOT48[A]	clk_ibuf/O
6.590	0.913	tNET	FF	1	R7C10[1][B]	u_la0_top/rst_ao_Z/CLK
6.792	0.202	tC2Q	FR	49	R7C10[1][B]	u_la0_top/rst_ao_Z/Q
8.548	1.756	tNET	RR	1	R2C5[0][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[12]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	497	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R2C5[0][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[12]/CLK
1.777	0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_length_Z[12]
1.788	0.011	tHld		1	R2C5[0][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[12]

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.756, 89.683%; tC2Q: 0.202, 10.317%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path17

Path Summary:

Slack	6.760
Data Arrival Time	8.548
Data Required Time	1.788
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.677	0.678	tINS	FF	497	IOT48[A]	clk_ibuf/O
6.590	0.913	tNET	FF	1	R7C10[1][B]	u_la0_top/rst_ao_Z/CLK
6.792	0.202	tC2Q	FR	49	R7C10[1][B]	u_la0_top/rst_ao_Z/Q
8.548	1.756	tNET	RR	1	R9C8[0][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	497	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R9C8[0][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0]/CLK
1.777	0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0]
1.788	0.011	tHld		1	R9C8[0][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0]

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.756, 89.683%; tC2Q: 0.202, 10.317%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path18

Path Summary:

Slack	6.760
Data Arrival Time	8.548
Data Required Time	1.788
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[1]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.677	0.678	tINS	FF	497	IOT48[A]	clk_ibuf/O
6.590	0.913	tNET	FF	1	R7C10[1][B]	u_la0_top/rst_ao_Z/CLK
6.792	0.202	tC2Q	FR	49	R7C10[1][B]	u_la0_top/rst_ao_Z/Q
8.548	1.756	tNET	RR	1	R9C8[0][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[1]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	497	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R9C8[0][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[1]/CLK
1.777	0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[1]
1.788	0.011	tHld		1	R9C8[0][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[1]

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.756, 89.683%; tC2Q: 0.202, 10.317%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path19

Path Summary:

Slack	6.760
Data Arrival Time	8.548
Data Required Time	1.788
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[2]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.677	0.678	tINS	FF	497	IOT48[A]	clk_ibuf/O
6.590	0.913	tNET	FF	1	R7C10[1][B]	u_la0_top/rst_ao_Z/CLK
6.792	0.202	tC2Q	FR	49	R7C10[1][B]	u_la0_top/rst_ao_Z/Q
8.548	1.756	tNET	RR	1	R9C8[1][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[2]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	497	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R9C8[1][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[2]/CLK
1.777	0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[2]
1.788	0.011	tHld		1	R9C8[1][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[2]

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.756, 89.683%; tC2Q: 0.202, 10.317%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path20

Path Summary:

Slack	6.760
Data Arrival Time	8.548
Data Required Time	1.788
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[3]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.677	0.678	tINS	FF	497	IOT48[A]	clk_ibuf/O
6.590	0.913	tNET	FF	1	R7C10[1][B]	u_la0_top/rst_ao_Z/CLK
6.792	0.202	tC2Q	FR	49	R7C10[1][B]	u_la0_top/rst_ao_Z/Q
8.548	1.756	tNET	RR	1	R8C10[0][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[3]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	497	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R8C10[0][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[3]/CLK
1.777	0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[3]
1.788	0.011	tHld		1	R8C10[0][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[3]

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.756, 89.683%; tC2Q: 0.202, 10.317%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path21

Path Summary:

Slack	6.760
Data Arrival Time	8.548
Data Required Time	1.788
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[4]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.677	0.678	tINS	FF	497	IOT48[A]	clk_ibuf/O
6.590	0.913	tNET	FF	1	R7C10[1][B]	u_la0_top/rst_ao_Z/CLK
6.792	0.202	tC2Q	FR	49	R7C10[1][B]	u_la0_top/rst_ao_Z/Q
8.548	1.756	tNET	RR	1	R12C8[0][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[4]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	497	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R12C8[0][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[4]/CLK
1.777	0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[4]
1.788	0.011	tHld		1	R12C8[0][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[4]

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.756, 89.683%; tC2Q: 0.202, 10.317%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path22

Path Summary:

Slack	6.760
Data Arrival Time	8.548
Data Required Time	1.788
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[5]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.677	0.678	tINS	FF	497	IOT48[A]	clk_ibuf/O
6.590	0.913	tNET	FF	1	R7C10[1][B]	u_la0_top/rst_ao_Z/CLK
6.792	0.202	tC2Q	FR	49	R7C10[1][B]	u_la0_top/rst_ao_Z/Q
8.548	1.756	tNET	RR	1	R9C8[1][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[5]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	497	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R9C8[1][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[5]/CLK
1.777	0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[5]
1.788	0.011	tHld		1	R9C8[1][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[5]

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.756, 89.683%; tC2Q: 0.202, 10.317%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path23

Path Summary:

Slack	6.760
Data Arrival Time	8.548
Data Required Time	1.788
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[6]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.677	0.678	tINS	FF	497	IOT48[A]	clk_ibuf/O
6.590	0.913	tNET	FF	1	R7C10[1][B]	u_la0_top/rst_ao_Z/CLK
6.792	0.202	tC2Q	FR	49	R7C10[1][B]	u_la0_top/rst_ao_Z/Q
8.548	1.756	tNET	RR	1	R8C10[0][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[6]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	497	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R8C10[0][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[6]/CLK
1.777	0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[6]
1.788	0.011	tHld		1	R8C10[0][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[6]

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.756, 89.683%; tC2Q: 0.202, 10.317%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path24

Path Summary:

Slack	6.760
Data Arrival Time	8.548
Data Required Time	1.788
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[7]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.677	0.678	tINS	FF	497	IOT48[A]	clk_ibuf/O
6.590	0.913	tNET	FF	1	R7C10[1][B]	u_la0_top/rst_ao_Z/CLK
6.792	0.202	tC2Q	FR	49	R7C10[1][B]	u_la0_top/rst_ao_Z/Q
8.548	1.756	tNET	RR	1	R11C6[2][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[7]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	497	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R11C6[2][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[7]/CLK
1.777	0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[7]
1.788	0.011	tHld		1	R11C6[2][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[7]

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.756, 89.683%; tC2Q: 0.202, 10.317%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path25

Path Summary:

Slack	6.760
Data Arrival Time	8.548
Data Required Time	1.788
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.677	0.678	tINS	FF	497	IOT48[A]	clk_ibuf/O
6.590	0.913	tNET	FF	1	R7C10[1][B]	u_la0_top/rst_ao_Z/CLK
6.792	0.202	tC2Q	FR	49	R7C10[1][B]	u_la0_top/rst_ao_Z/Q
8.548	1.756	tNET	RR	1	R11C6[2][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	497	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R11C6[2][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8]/CLK
1.777	0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8]
1.788	0.011	tHld		1	R11C6[2][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8]

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.756, 89.683%; tC2Q: 0.202, 10.317%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Minimum Pulse Width Report:

Report Command:report_min_pulse_width -nworst 10 -detail

MPW1

MPW Summary:

Slack:	3.662
Actual Width:	4.662
Required Width:	1.000
Type:	Low Pulse Width
Clock:	DEFAULT_CLK
Objects:	cnt_1_Z[12]

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	clk_ibuf/I
5.688	0.688	tINS	FF	clk_ibuf/O
6.916	1.228	tNET	FF	cnt_1_Z[12]/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	clk_ibuf/I
10.675	0.675	tINS	RR	clk_ibuf/O
11.577	0.902	tNET	RR	cnt_1_Z[12]/CLK

MPW2

MPW Summary:

Slack:	3.662
Actual Width:	4.662
Required Width:	1.000
Type:	Low Pulse Width
Clock:	DEFAULT_CLK
Objects:	cnt_1_Z[10]

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	clk_ibuf/I
5.688	0.688	tINS	FF	clk_ibuf/O
6.916	1.228	tNET	FF	cnt_1_Z[10]/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	clk_ibuf/I
10.675	0.675	tINS	RR	clk_ibuf/O
11.577	0.902	tNET	RR	cnt_1_Z[10]/CLK

MPW3

MPW Summary:

Slack:	3.662
Actual Width:	4.662
Required Width:	1.000
Type:	Low Pulse Width
Clock:	DEFAULT_CLK
Objects:	cnt_1_Z[6]

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	clk_ibuf/I
5.688	0.688	tINS	FF	clk_ibuf/O
6.916	1.228	tNET	FF	cnt_1_Z[6]/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	clk_ibuf/I
10.675	0.675	tINS	RR	clk_ibuf/O
11.577	0.902	tNET	RR	cnt_1_Z[6]/CLK

MPW4

MPW Summary:

Slack:	3.662
Actual Width:	4.662
Required Width:	1.000
Type:	Low Pulse Width
Clock:	DEFAULT_CLK
Objects:	cnt_Z[11]

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	clk_ibuf/I
5.688	0.688	tINS	FF	clk_ibuf/O
6.916	1.228	tNET	FF	cnt_Z[11]/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	clk_ibuf/I
10.675	0.675	tINS	RR	clk_ibuf/O
11.577	0.902	tNET	RR	cnt_Z[11]/CLK

MPW5

MPW Summary:

Slack:	3.662
Actual Width:	4.662
Required Width:	1.000
Type:	Low Pulse Width
Clock:	DEFAULT_CLK
Objects:	divisor[31]

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	clk_ibuf/I
5.688	0.688	tINS	FF	clk_ibuf/O
6.916	1.228	tNET	FF	divisor[31]/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	clk_ibuf/I
10.675	0.675	tINS	RR	clk_ibuf/O
11.577	0.902	tNET	RR	divisor[31]/CLK

MPW6

MPW Summary:

Slack:	3.662
Actual Width:	4.662
Required Width:	1.000
Type:	Low Pulse Width
Clock:	DEFAULT_CLK
Objects:	n_Z[30]

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	clk_ibuf/I
5.688	0.688	tINS	FF	clk_ibuf/O
6.916	1.228	tNET	FF	n_Z[30]/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	clk_ibuf/I
10.675	0.675	tINS	RR	clk_ibuf/O
11.577	0.902	tNET	RR	n_Z[30]/CLK

MPW7

MPW Summary:

Slack:	3.662
Actual Width:	4.662
Required Width:	1.000
Type:	Low Pulse Width
Clock:	DEFAULT_CLK
Objects:	Mdu/u_mdu/reg0_Z[30]

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	clk_ibuf/I
5.688	0.688	tINS	FF	clk_ibuf/O
6.916	1.228	tNET	FF	Mdu/u_mdu/reg0_Z[30]/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	clk_ibuf/I
10.675	0.675	tINS	RR	clk_ibuf/O
11.577	0.902	tNET	RR	Mdu/u_mdu/reg0_Z[30]/CLK

MPW8

MPW Summary:

Slack:	3.662
Actual Width:	4.662
Required Width:	1.000
Type:	Low Pulse Width
Clock:	DEFAULT_CLK
Objects:	Mdu/u_mdu/reg0_1_rep1_Z

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	clk_ibuf/I
5.688	0.688	tINS	FF	clk_ibuf/O
6.916	1.228	tNET	FF	Mdu/u_mdu/reg0_1_rep1_Z/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	clk_ibuf/I
10.675	0.675	tINS	RR	clk_ibuf/O
11.577	0.902	tNET	RR	Mdu/u_mdu/reg0_1_rep1_Z/CLK

MPW9

MPW Summary:

Slack:	3.662
Actual Width:	4.662
Required Width:	1.000
Type:	Low Pulse Width
Clock:	DEFAULT_CLK
Objects:	Mdu/u_mdu/reg0_fast_Z[1]

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	clk_ibuf/I
5.688	0.688	tINS	FF	clk_ibuf/O
6.916	1.228	tNET	FF	Mdu/u_mdu/reg0_fast_Z[1]/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	clk_ibuf/I
10.675	0.675	tINS	RR	clk_ibuf/O
11.577	0.902	tNET	RR	Mdu/u_mdu/reg0_fast_Z[1]/CLK

MPW10

MPW Summary:

Slack:	3.662
Actual Width:	4.662
Required Width:	1.000
Type:	Low Pulse Width
Clock:	DEFAULT_CLK
Objects:	Mdu/u_mdu/reg0_Z[29]

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	clk_ibuf/I
5.688	0.688	tINS	FF	clk_ibuf/O
6.916	1.228	tNET	FF	Mdu/u_mdu/reg0_Z[29]/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	clk_ibuf/I
10.675	0.675	tINS	RR	clk_ibuf/O
11.577	0.902	tNET	RR	Mdu/u_mdu/reg0_Z[29]/CLK

High Fanout Nets Report:

Report Command:report_high_fanout_nets -max_nets 10

FANOUT	NET NAME	WORST SLACK	MAX DELAY
303	clk_c	0.073	1.228
114	div_shift_number[1]	0.872	1.686
113	div_shift_number[0]	1.036	1.355
100	reg0_en	2.777	2.184
96	neg_result	4.204	1.836
92	state[1]	4.620	2.106
81	hi_result	2.723	1.883
74	reg0_exe_nx_sm0	1.844	1.574
71	state[3]	4.735	2.623
70	m0_2_03_1	0.919	2.555

Route Congestions Report:

Report Command:report_route_congestion -max_grids 10

GRID LOC	ROUTE CONGESTIONS
R51C33	0.875
R38C63	0.847
R38C65	0.819
R38C66	0.819
R38C64	0.806
R38C62	0.778
R43C34	0.750
R51C34	0.736
R42C33	0.722
R44C52	0.722

Timing Exceptions Report:

Setup Analysis Report

Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Hold Analysis Report

Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Recovery Analysis Report

Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Removal Analysis Report

Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Timing Constraints Report:

SDC Command Type	State	Detail Command