@N|Running in 64-bit mode
@N|Running in 64-bit mode
@N: CG1349 :	| Running Verilog Compiler in System Verilog mode
@N: CG1350 :	| Running Verilog Compiler in Multiple File Compilation Unit mode
@N: CG364 :"C:\Gowin\1.8\SynplifyPro\lib\generic\gw2a.v":1597:7:1597:9|Synthesizing module GSR in library work.
@N: CG364 :"F:\user-bak\Users\FDELL\Desktop\IP\Integer_Multiply-Divider\ref_design\REM\Integer_Multiply_Divider_np\project\src\integer_multiply_divider\integer_multiply_divider.v":17140:7:17140:34|Synthesizing module Integer_Multiply_Divider_Top in library work.
@N: CG364 :"F:\user-bak\Users\FDELL\Desktop\IP\Integer_Multiply-Divider\ref_design\REM\Integer_Multiply_Divider_np\project\src\top.v":4:7:4:9|Synthesizing module top in library work.
@N: CL134 :"F:\user-bak\Users\FDELL\Desktop\IP\Integer_Multiply-Divider\ref_design\REM\Integer_Multiply_Divider_np\project\src\top.v":121:0:121:5|Found RAM memr, depth=8192, width=32
@N: CL189 :"F:\user-bak\Users\FDELL\Desktop\IP\Integer_Multiply-Divider\ref_design\REM\Integer_Multiply_Divider_np\project\src\top.v":145:0:145:5|Register bit ad[1] is always 0.
@N: CL189 :"F:\user-bak\Users\FDELL\Desktop\IP\Integer_Multiply-Divider\ref_design\REM\Integer_Multiply_Divider_np\project\src\top.v":56:4:56:9|Register bit m[0] is always 1.
@N: CL189 :"F:\user-bak\Users\FDELL\Desktop\IP\Integer_Multiply-Divider\ref_design\REM\Integer_Multiply_Divider_np\project\src\top.v":56:4:56:9|Register bit m[1] is always 0.
@N: CL189 :"F:\user-bak\Users\FDELL\Desktop\IP\Integer_Multiply-Divider\ref_design\REM\Integer_Multiply_Divider_np\project\src\top.v":56:4:56:9|Register bit m[2] is always 0.
@N: CL189 :"F:\user-bak\Users\FDELL\Desktop\IP\Integer_Multiply-Divider\ref_design\REM\Integer_Multiply_Divider_np\project\src\top.v":56:4:56:9|Register bit m[3] is always 0.
@N: CL189 :"F:\user-bak\Users\FDELL\Desktop\IP\Integer_Multiply-Divider\ref_design\REM\Integer_Multiply_Divider_np\project\src\top.v":56:4:56:9|Register bit m[4] is always 0.
@N: CL189 :"F:\user-bak\Users\FDELL\Desktop\IP\Integer_Multiply-Divider\ref_design\REM\Integer_Multiply_Divider_np\project\src\top.v":56:4:56:9|Register bit m[5] is always 0.
@N: CL189 :"F:\user-bak\Users\FDELL\Desktop\IP\Integer_Multiply-Divider\ref_design\REM\Integer_Multiply_Divider_np\project\src\top.v":56:4:56:9|Register bit m[6] is always 0.
@N: CL189 :"F:\user-bak\Users\FDELL\Desktop\IP\Integer_Multiply-Divider\ref_design\REM\Integer_Multiply_Divider_np\project\src\top.v":56:4:56:9|Register bit m[7] is always 0.
@N: CL189 :"F:\user-bak\Users\FDELL\Desktop\IP\Integer_Multiply-Divider\ref_design\REM\Integer_Multiply_Divider_np\project\src\top.v":56:4:56:9|Register bit m[8] is always 0.
@N: CL189 :"F:\user-bak\Users\FDELL\Desktop\IP\Integer_Multiply-Divider\ref_design\REM\Integer_Multiply_Divider_np\project\src\top.v":56:4:56:9|Register bit m[9] is always 0.
@N: CL189 :"F:\user-bak\Users\FDELL\Desktop\IP\Integer_Multiply-Divider\ref_design\REM\Integer_Multiply_Divider_np\project\src\top.v":56:4:56:9|Register bit m[10] is always 0.
@N: CL189 :"F:\user-bak\Users\FDELL\Desktop\IP\Integer_Multiply-Divider\ref_design\REM\Integer_Multiply_Divider_np\project\src\top.v":56:4:56:9|Register bit m[11] is always 0.
@N: CL189 :"F:\user-bak\Users\FDELL\Desktop\IP\Integer_Multiply-Divider\ref_design\REM\Integer_Multiply_Divider_np\project\src\top.v":56:4:56:9|Register bit m[12] is always 0.
@N: CL189 :"F:\user-bak\Users\FDELL\Desktop\IP\Integer_Multiply-Divider\ref_design\REM\Integer_Multiply_Divider_np\project\src\top.v":56:4:56:9|Register bit m[13] is always 0.
@N: CL189 :"F:\user-bak\Users\FDELL\Desktop\IP\Integer_Multiply-Divider\ref_design\REM\Integer_Multiply_Divider_np\project\src\top.v":56:4:56:9|Register bit m[14] is always 0.
@N: CL189 :"F:\user-bak\Users\FDELL\Desktop\IP\Integer_Multiply-Divider\ref_design\REM\Integer_Multiply_Divider_np\project\src\top.v":56:4:56:9|Register bit m[15] is always 0.
@N: CL189 :"F:\user-bak\Users\FDELL\Desktop\IP\Integer_Multiply-Divider\ref_design\REM\Integer_Multiply_Divider_np\project\src\top.v":56:4:56:9|Register bit m[16] is always 0.
@N: CL189 :"F:\user-bak\Users\FDELL\Desktop\IP\Integer_Multiply-Divider\ref_design\REM\Integer_Multiply_Divider_np\project\src\top.v":56:4:56:9|Register bit m[17] is always 0.
@N: CL189 :"F:\user-bak\Users\FDELL\Desktop\IP\Integer_Multiply-Divider\ref_design\REM\Integer_Multiply_Divider_np\project\src\top.v":56:4:56:9|Register bit m[18] is always 0.
@N: CL189 :"F:\user-bak\Users\FDELL\Desktop\IP\Integer_Multiply-Divider\ref_design\REM\Integer_Multiply_Divider_np\project\src\top.v":56:4:56:9|Register bit m[19] is always 0.
@N: CL189 :"F:\user-bak\Users\FDELL\Desktop\IP\Integer_Multiply-Divider\ref_design\REM\Integer_Multiply_Divider_np\project\src\top.v":56:4:56:9|Register bit m[20] is always 0.
@N: CL189 :"F:\user-bak\Users\FDELL\Desktop\IP\Integer_Multiply-Divider\ref_design\REM\Integer_Multiply_Divider_np\project\src\top.v":56:4:56:9|Register bit m[21] is always 0.
@N: CL189 :"F:\user-bak\Users\FDELL\Desktop\IP\Integer_Multiply-Divider\ref_design\REM\Integer_Multiply_Divider_np\project\src\top.v":56:4:56:9|Register bit m[22] is always 0.
@N: CL189 :"F:\user-bak\Users\FDELL\Desktop\IP\Integer_Multiply-Divider\ref_design\REM\Integer_Multiply_Divider_np\project\src\top.v":72:4:72:9|Register bit n[0] is always 0.
@N: CL189 :"F:\user-bak\Users\FDELL\Desktop\IP\Integer_Multiply-Divider\ref_design\REM\Integer_Multiply_Divider_np\project\src\top.v":72:4:72:9|Register bit n[1] is always 0.
@N: CL189 :"F:\user-bak\Users\FDELL\Desktop\IP\Integer_Multiply-Divider\ref_design\REM\Integer_Multiply_Divider_np\project\src\top.v":72:4:72:9|Register bit n[2] is always 0.
@N: CL189 :"F:\user-bak\Users\FDELL\Desktop\IP\Integer_Multiply-Divider\ref_design\REM\Integer_Multiply_Divider_np\project\src\top.v":72:4:72:9|Register bit n[3] is always 0.
@N: CL189 :"F:\user-bak\Users\FDELL\Desktop\IP\Integer_Multiply-Divider\ref_design\REM\Integer_Multiply_Divider_np\project\src\top.v":72:4:72:9|Register bit n[4] is always 0.
@N: CL189 :"F:\user-bak\Users\FDELL\Desktop\IP\Integer_Multiply-Divider\ref_design\REM\Integer_Multiply_Divider_np\project\src\top.v":72:4:72:9|Register bit n[5] is always 0.
@N: CL189 :"F:\user-bak\Users\FDELL\Desktop\IP\Integer_Multiply-Divider\ref_design\REM\Integer_Multiply_Divider_np\project\src\top.v":72:4:72:9|Register bit n[6] is always 0.
@N: CL189 :"F:\user-bak\Users\FDELL\Desktop\IP\Integer_Multiply-Divider\ref_design\REM\Integer_Multiply_Divider_np\project\src\top.v":72:4:72:9|Register bit n[7] is always 0.
@N: CL189 :"F:\user-bak\Users\FDELL\Desktop\IP\Integer_Multiply-Divider\ref_design\REM\Integer_Multiply_Divider_np\project\src\top.v":72:4:72:9|Register bit n[8] is always 0.
@N: CL189 :"F:\user-bak\Users\FDELL\Desktop\IP\Integer_Multiply-Divider\ref_design\REM\Integer_Multiply_Divider_np\project\src\top.v":72:4:72:9|Register bit n[9] is always 0.
@N: CL189 :"F:\user-bak\Users\FDELL\Desktop\IP\Integer_Multiply-Divider\ref_design\REM\Integer_Multiply_Divider_np\project\src\top.v":72:4:72:9|Register bit n[10] is always 0.
@N: CL189 :"F:\user-bak\Users\FDELL\Desktop\IP\Integer_Multiply-Divider\ref_design\REM\Integer_Multiply_Divider_np\project\src\top.v":72:4:72:9|Register bit n[11] is always 0.
@N: CL189 :"F:\user-bak\Users\FDELL\Desktop\IP\Integer_Multiply-Divider\ref_design\REM\Integer_Multiply_Divider_np\project\src\top.v":72:4:72:9|Register bit n[12] is always 0.
@N: CL189 :"F:\user-bak\Users\FDELL\Desktop\IP\Integer_Multiply-Divider\ref_design\REM\Integer_Multiply_Divider_np\project\src\top.v":72:4:72:9|Register bit n[13] is always 0.
@N: CL189 :"F:\user-bak\Users\FDELL\Desktop\IP\Integer_Multiply-Divider\ref_design\REM\Integer_Multiply_Divider_np\project\src\top.v":72:4:72:9|Register bit n[14] is always 0.
@N: CL189 :"F:\user-bak\Users\FDELL\Desktop\IP\Integer_Multiply-Divider\ref_design\REM\Integer_Multiply_Divider_np\project\src\top.v":72:4:72:9|Register bit n[15] is always 0.
@N: CL189 :"F:\user-bak\Users\FDELL\Desktop\IP\Integer_Multiply-Divider\ref_design\REM\Integer_Multiply_Divider_np\project\src\top.v":72:4:72:9|Register bit n[16] is always 0.
@N: CL189 :"F:\user-bak\Users\FDELL\Desktop\IP\Integer_Multiply-Divider\ref_design\REM\Integer_Multiply_Divider_np\project\src\top.v":72:4:72:9|Register bit n[17] is always 0.
@N: CL189 :"F:\user-bak\Users\FDELL\Desktop\IP\Integer_Multiply-Divider\ref_design\REM\Integer_Multiply_Divider_np\project\src\top.v":72:4:72:9|Register bit n[18] is always 0.
@N: CL189 :"F:\user-bak\Users\FDELL\Desktop\IP\Integer_Multiply-Divider\ref_design\REM\Integer_Multiply_Divider_np\project\src\top.v":72:4:72:9|Register bit n[19] is always 0.
@N: CL189 :"F:\user-bak\Users\FDELL\Desktop\IP\Integer_Multiply-Divider\ref_design\REM\Integer_Multiply_Divider_np\project\src\top.v":72:4:72:9|Register bit n[20] is always 0.
@N: CL189 :"F:\user-bak\Users\FDELL\Desktop\IP\Integer_Multiply-Divider\ref_design\REM\Integer_Multiply_Divider_np\project\src\top.v":72:4:72:9|Register bit n[21] is always 0.
@N: CL189 :"F:\user-bak\Users\FDELL\Desktop\IP\Integer_Multiply-Divider\ref_design\REM\Integer_Multiply_Divider_np\project\src\top.v":72:4:72:9|Register bit n[22] is always 0.
@N: CL189 :"F:\user-bak\Users\FDELL\Desktop\IP\Integer_Multiply-Divider\ref_design\REM\Integer_Multiply_Divider_np\project\src\top.v":87:4:87:9|Register bit dividend[1] is always 0.
@N: CL189 :"F:\user-bak\Users\FDELL\Desktop\IP\Integer_Multiply-Divider\ref_design\REM\Integer_Multiply_Divider_np\project\src\top.v":87:4:87:9|Register bit dividend[2] is always 0.
@N: CL189 :"F:\user-bak\Users\FDELL\Desktop\IP\Integer_Multiply-Divider\ref_design\REM\Integer_Multiply_Divider_np\project\src\top.v":87:4:87:9|Register bit dividend[3] is always 0.
@N: CL189 :"F:\user-bak\Users\FDELL\Desktop\IP\Integer_Multiply-Divider\ref_design\REM\Integer_Multiply_Divider_np\project\src\top.v":87:4:87:9|Register bit dividend[4] is always 0.
@N: CL189 :"F:\user-bak\Users\FDELL\Desktop\IP\Integer_Multiply-Divider\ref_design\REM\Integer_Multiply_Divider_np\project\src\top.v":87:4:87:9|Register bit dividend[5] is always 0.
@N: CL189 :"F:\user-bak\Users\FDELL\Desktop\IP\Integer_Multiply-Divider\ref_design\REM\Integer_Multiply_Divider_np\project\src\top.v":87:4:87:9|Register bit dividend[6] is always 0.
@N: CL189 :"F:\user-bak\Users\FDELL\Desktop\IP\Integer_Multiply-Divider\ref_design\REM\Integer_Multiply_Divider_np\project\src\top.v":87:4:87:9|Register bit dividend[7] is always 0.
@N: CL189 :"F:\user-bak\Users\FDELL\Desktop\IP\Integer_Multiply-Divider\ref_design\REM\Integer_Multiply_Divider_np\project\src\top.v":87:4:87:9|Register bit dividend[8] is always 0.
@N: CL189 :"F:\user-bak\Users\FDELL\Desktop\IP\Integer_Multiply-Divider\ref_design\REM\Integer_Multiply_Divider_np\project\src\top.v":87:4:87:9|Register bit dividend[9] is always 0.
@N: CL189 :"F:\user-bak\Users\FDELL\Desktop\IP\Integer_Multiply-Divider\ref_design\REM\Integer_Multiply_Divider_np\project\src\top.v":87:4:87:9|Register bit dividend[10] is always 0.
@N: CL189 :"F:\user-bak\Users\FDELL\Desktop\IP\Integer_Multiply-Divider\ref_design\REM\Integer_Multiply_Divider_np\project\src\top.v":87:4:87:9|Register bit dividend[11] is always 0.
@N: CL189 :"F:\user-bak\Users\FDELL\Desktop\IP\Integer_Multiply-Divider\ref_design\REM\Integer_Multiply_Divider_np\project\src\top.v":87:4:87:9|Register bit dividend[12] is always 0.
@N: CL189 :"F:\user-bak\Users\FDELL\Desktop\IP\Integer_Multiply-Divider\ref_design\REM\Integer_Multiply_Divider_np\project\src\top.v":87:4:87:9|Register bit dividend[13] is always 0.
@N: CL189 :"F:\user-bak\Users\FDELL\Desktop\IP\Integer_Multiply-Divider\ref_design\REM\Integer_Multiply_Divider_np\project\src\top.v":87:4:87:9|Register bit dividend[14] is always 0.
@N: CL189 :"F:\user-bak\Users\FDELL\Desktop\IP\Integer_Multiply-Divider\ref_design\REM\Integer_Multiply_Divider_np\project\src\top.v":87:4:87:9|Register bit dividend[15] is always 0.
@N: CL189 :"F:\user-bak\Users\FDELL\Desktop\IP\Integer_Multiply-Divider\ref_design\REM\Integer_Multiply_Divider_np\project\src\top.v":87:4:87:9|Register bit dividend[16] is always 0.
@N: CL189 :"F:\user-bak\Users\FDELL\Desktop\IP\Integer_Multiply-Divider\ref_design\REM\Integer_Multiply_Divider_np\project\src\top.v":87:4:87:9|Register bit dividend[17] is always 0.
@N: CL189 :"F:\user-bak\Users\FDELL\Desktop\IP\Integer_Multiply-Divider\ref_design\REM\Integer_Multiply_Divider_np\project\src\top.v":87:4:87:9|Register bit dividend[18] is always 0.
@N: CL189 :"F:\user-bak\Users\FDELL\Desktop\IP\Integer_Multiply-Divider\ref_design\REM\Integer_Multiply_Divider_np\project\src\top.v":87:4:87:9|Register bit dividend[19] is always 0.
@N: CL189 :"F:\user-bak\Users\FDELL\Desktop\IP\Integer_Multiply-Divider\ref_design\REM\Integer_Multiply_Divider_np\project\src\top.v":87:4:87:9|Register bit dividend[20] is always 0.
@N: CL189 :"F:\user-bak\Users\FDELL\Desktop\IP\Integer_Multiply-Divider\ref_design\REM\Integer_Multiply_Divider_np\project\src\top.v":87:4:87:9|Register bit dividend[21] is always 0.
@N: CL189 :"F:\user-bak\Users\FDELL\Desktop\IP\Integer_Multiply-Divider\ref_design\REM\Integer_Multiply_Divider_np\project\src\top.v":87:4:87:9|Register bit dividend[22] is always 0.
@N: CL189 :"F:\user-bak\Users\FDELL\Desktop\IP\Integer_Multiply-Divider\ref_design\REM\Integer_Multiply_Divider_np\project\src\top.v":87:4:87:9|Register bit divisor[0] is always 0.
@N: CL189 :"F:\user-bak\Users\FDELL\Desktop\IP\Integer_Multiply-Divider\ref_design\REM\Integer_Multiply_Divider_np\project\src\top.v":87:4:87:9|Register bit divisor[1] is always 0.
@N: CL189 :"F:\user-bak\Users\FDELL\Desktop\IP\Integer_Multiply-Divider\ref_design\REM\Integer_Multiply_Divider_np\project\src\top.v":87:4:87:9|Register bit divisor[2] is always 0.
@N: CL189 :"F:\user-bak\Users\FDELL\Desktop\IP\Integer_Multiply-Divider\ref_design\REM\Integer_Multiply_Divider_np\project\src\top.v":87:4:87:9|Register bit divisor[3] is always 0.
@N: CL189 :"F:\user-bak\Users\FDELL\Desktop\IP\Integer_Multiply-Divider\ref_design\REM\Integer_Multiply_Divider_np\project\src\top.v":87:4:87:9|Register bit divisor[4] is always 0.
@N: CL189 :"F:\user-bak\Users\FDELL\Desktop\IP\Integer_Multiply-Divider\ref_design\REM\Integer_Multiply_Divider_np\project\src\top.v":87:4:87:9|Register bit divisor[5] is always 0.
@N: CL189 :"F:\user-bak\Users\FDELL\Desktop\IP\Integer_Multiply-Divider\ref_design\REM\Integer_Multiply_Divider_np\project\src\top.v":87:4:87:9|Register bit divisor[6] is always 0.
@N: CL189 :"F:\user-bak\Users\FDELL\Desktop\IP\Integer_Multiply-Divider\ref_design\REM\Integer_Multiply_Divider_np\project\src\top.v":87:4:87:9|Register bit divisor[7] is always 0.
@N: CL189 :"F:\user-bak\Users\FDELL\Desktop\IP\Integer_Multiply-Divider\ref_design\REM\Integer_Multiply_Divider_np\project\src\top.v":87:4:87:9|Register bit divisor[8] is always 0.
@N: CL189 :"F:\user-bak\Users\FDELL\Desktop\IP\Integer_Multiply-Divider\ref_design\REM\Integer_Multiply_Divider_np\project\src\top.v":87:4:87:9|Register bit divisor[9] is always 0.
@N: CL189 :"F:\user-bak\Users\FDELL\Desktop\IP\Integer_Multiply-Divider\ref_design\REM\Integer_Multiply_Divider_np\project\src\top.v":87:4:87:9|Register bit divisor[10] is always 0.
@N: CL189 :"F:\user-bak\Users\FDELL\Desktop\IP\Integer_Multiply-Divider\ref_design\REM\Integer_Multiply_Divider_np\project\src\top.v":87:4:87:9|Register bit divisor[11] is always 0.
@N: CL189 :"F:\user-bak\Users\FDELL\Desktop\IP\Integer_Multiply-Divider\ref_design\REM\Integer_Multiply_Divider_np\project\src\top.v":87:4:87:9|Register bit divisor[12] is always 0.
@N: CL189 :"F:\user-bak\Users\FDELL\Desktop\IP\Integer_Multiply-Divider\ref_design\REM\Integer_Multiply_Divider_np\project\src\top.v":87:4:87:9|Register bit divisor[13] is always 0.
@N: CL189 :"F:\user-bak\Users\FDELL\Desktop\IP\Integer_Multiply-Divider\ref_design\REM\Integer_Multiply_Divider_np\project\src\top.v":87:4:87:9|Register bit divisor[14] is always 0.
@N: CL189 :"F:\user-bak\Users\FDELL\Desktop\IP\Integer_Multiply-Divider\ref_design\REM\Integer_Multiply_Divider_np\project\src\top.v":87:4:87:9|Register bit divisor[15] is always 0.
@N: CL189 :"F:\user-bak\Users\FDELL\Desktop\IP\Integer_Multiply-Divider\ref_design\REM\Integer_Multiply_Divider_np\project\src\top.v":87:4:87:9|Register bit divisor[16] is always 0.
@N: CL189 :"F:\user-bak\Users\FDELL\Desktop\IP\Integer_Multiply-Divider\ref_design\REM\Integer_Multiply_Divider_np\project\src\top.v":87:4:87:9|Register bit divisor[17] is always 0.
@N: CL189 :"F:\user-bak\Users\FDELL\Desktop\IP\Integer_Multiply-Divider\ref_design\REM\Integer_Multiply_Divider_np\project\src\top.v":87:4:87:9|Register bit divisor[18] is always 0.
@N: CL189 :"F:\user-bak\Users\FDELL\Desktop\IP\Integer_Multiply-Divider\ref_design\REM\Integer_Multiply_Divider_np\project\src\top.v":87:4:87:9|Register bit divisor[19] is always 0.
@N: CL189 :"F:\user-bak\Users\FDELL\Desktop\IP\Integer_Multiply-Divider\ref_design\REM\Integer_Multiply_Divider_np\project\src\top.v":87:4:87:9|Register bit divisor[20] is always 0.
@N: CL189 :"F:\user-bak\Users\FDELL\Desktop\IP\Integer_Multiply-Divider\ref_design\REM\Integer_Multiply_Divider_np\project\src\top.v":87:4:87:9|Register bit divisor[21] is always 0.
@N: CL189 :"F:\user-bak\Users\FDELL\Desktop\IP\Integer_Multiply-Divider\ref_design\REM\Integer_Multiply_Divider_np\project\src\top.v":87:4:87:9|Register bit divisor[22] is always 0.
@N: CL189 :"F:\user-bak\Users\FDELL\Desktop\IP\Integer_Multiply-Divider\ref_design\REM\Integer_Multiply_Divider_np\project\src\top.v":72:4:72:9|Register bit n[31] is always 0.
@N: CL189 :"F:\user-bak\Users\FDELL\Desktop\IP\Integer_Multiply-Divider\ref_design\REM\Integer_Multiply_Divider_np\project\src\top.v":87:4:87:9|Register bit divisor[31] is always 0.
@N|Running in 64-bit mode
@N: NF107 :"f:\user-bak\users\fdell\desktop\ip\integer_multiply-divider\ref_design\rem\integer_multiply_divider_np\project\src\top.v":4:7:4:9|Selected library: work cell: top view verilog as top level
@N: NF107 :"f:\user-bak\users\fdell\desktop\ip\integer_multiply-divider\ref_design\rem\integer_multiply_divider_np\project\src\top.v":4:7:4:9|Selected library: work cell: top view verilog as top level

