Timing Messages

Report Title	Gowin Timing Analysis Report
Design File	F:/user-bak/Users/FDELL/Desktop/IP/Integer_Multiply-Divider/ref_design/REM/Integer_Multiply_Divider_np/project/impl/synplify/rev_1/Integer_Multiply_Divider_np.vm
Physical Constraints File	F:\user-bak\Users\FDELL\Desktop\IP\Integer_Multiply-Divider\ref_design\REM\Integer_Multiply_Divider_np\project\src\Integer_Multiply_Divider_np.cst
Timing Constraints File	---
GOWIN version	v1.9.0Beta
Part Number	GW2A-LV55PG484C8/I7
Created Time	Tue Feb 19 18:02:57 2019
Legal Announcement	Copyright (C)2014-2019 Gowin Semiconductor Corporation. All rights reserved.

Timing Summaries

STA Tool Run Summary:

Setup Delay Model	Slow 0.95V 85C
Hold Delay Model	Fast 1.05V 0C
Numbers of Paths Analyzed	2798
Numbers of Endpoints Analyzed	6743
Numbers of Falling Endpoints	1
Numbers of Setup Violated Endpoints	0
Numbers of Hold Violated Endpoints	0

Clock Summary:

Clock Name	Type	Period	Frequency(MHz)	Rise	Fall	Source	Master	Objects
DEFAULT_CLK	Base	10.000	100.000	0.000	5.000

Max Frequency Summary:

NO.	Clock Name	Fmax	Entity
1	DEFAULT_CLK	104.130(MHz)	TOP

Total Negative Slack Summary:

Clock Name	Analysis Type	Endpoints TNS	Number of Endpoints
DEFAULT_CLK	Setup	0.000	0
DEFAULT_CLK	Hold	0.000	0

Timing Details

Path Slacks Table:

Setup Paths Table

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	0.397	Mdu/u_mdu/div_shift_number_Z[3]/Q	Mdu/u_mdu/reg0_Z[61]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	0.000	9.368
2	0.607	Mdu/u_mdu/div_shift_number_Z[0]/Q	Mdu/u_mdu/reg0_Z[62]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	0.000	9.158
3	0.742	Mdu/u_mdu/div_shift_number_Z[0]/Q	Mdu/u_mdu/reg0_Z[30]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	0.000	9.023
4	0.800	Mdu/u_mdu/cnt_Z[1]/Q	Mdu/u_mdu/reg0_fast_Z[17]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	0.000	8.965
5	0.800	Mdu/u_mdu/cnt_Z[1]/Q	Mdu/u_mdu/reg0_Z[17]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	0.000	8.965
6	0.880	Mdu/u_mdu/div_shift_number_Z[3]/Q	Mdu/u_mdu/reg0_Z[53]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	0.000	8.885
7	0.901	Mdu/u_mdu/div_shift_number_Z[0]/Q	Mdu/u_mdu/reg0_Z[21]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	0.000	8.864
8	0.908	Mdu/u_mdu/cnt_Z[1]/Q	Mdu/u_mdu/reg0_fast_Z[19]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	0.000	8.857
9	0.908	Mdu/u_mdu/cnt_Z[1]/Q	Mdu/u_mdu/reg0_Z[19]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	0.000	8.857
10	0.923	Mdu/u_mdu/reg0_Z[16]/Q	Mdu/u_mdu/reg0_Z[16]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	0.000	8.842
11	0.975	Mdu/u_mdu/div_shift_number_Z[0]/Q	Mdu/u_mdu/reg0_Z[48]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	0.000	8.790
12	0.982	Mdu/u_mdu/div_shift_number_Z[0]/Q	Mdu/u_mdu/reg0_31_rep1_Z/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	0.000	8.783
13	0.982	Mdu/u_mdu/div_shift_number_Z[0]/Q	Mdu/u_mdu/reg0_fast_Z[31]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	0.000	8.783
14	0.985	Mdu/u_mdu/div_shift_number_Z[0]/Q	Mdu/u_mdu/reg0_fast_Z[30]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	0.000	8.780
15	1.023	Mdu/u_mdu/div_shift_number_Z[0]/Q	Mdu/u_mdu/reg0_Z[64]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	0.000	8.742
16	1.071	Mdu/u_mdu/div_shift_number_Z[0]/Q	Mdu/u_mdu/reg0_Z[63]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	0.000	8.694
17	1.073	Mdu/u_mdu/div_shift_number_Z[0]/Q	Mdu/u_mdu/reg0_fast_Z[28]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	0.000	8.692
18	1.073	Mdu/u_mdu/div_shift_number_Z[0]/Q	Mdu/u_mdu/reg0_Z[28]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	0.000	8.692
19	1.167	Mdu/u_mdu/cnt_Z[1]/Q	Mdu/u_mdu/reg0_Z[29]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	0.000	8.598
20	1.182	Mdu/u_mdu/reg1_Z[1]/Q	Mdu/u_mdu/reg0_Z[32]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	0.000	8.583
21	1.201	Mdu/u_mdu/div_shift_number_Z[0]/Q	Mdu/u_mdu/reg0_Z[47]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	0.000	8.564
22	1.212	Mdu/u_mdu/div_shift_number_Z[3]/Q	Mdu/u_mdu/reg0_Z[49]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	0.000	8.553
23	1.228	Mdu/u_mdu/reg0_fast_Z[5]/Q	Mdu/u_mdu/reg0_1_rep1_Z/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	0.000	8.537
24	1.234	Mdu/u_mdu/cnt_Z[1]/Q	Mdu/u_mdu/reg0_26_rep1_Z/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	0.000	8.531
25	1.234	Mdu/u_mdu/cnt_Z[1]/Q	Mdu/u_mdu/reg0_fast_Z[26]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	0.000	8.531

Hold Paths Table

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	0.213	u_la0_top/u_ao_mem_ctrl/data_reg_Z[45]/Q	u_la0_top/u_ao_mem_ctrl/mem_mem_0_22/DI1	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.000	0.000	0.462
2	0.213	u_la0_top/u_ao_mem_ctrl/data_reg_Z[44]/Q	u_la0_top/u_ao_mem_ctrl/mem_mem_0_22/DI0	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.000	0.000	0.462
3	0.213	u_la0_top/u_ao_mem_ctrl/data_reg_Z[34]/Q	u_la0_top/u_ao_mem_ctrl/mem_mem_0_17/DI0	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.000	0.000	0.462
4	0.215	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[2]/Q	u_la0_top/u_ao_mem_ctrl/mem_mem_0_17/ADA3	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.000	0.000	0.333
5	0.225	u_la0_top/u_ao_mem_ctrl/data_reg_Z[12]/Q	u_la0_top/u_ao_mem_ctrl/mem_mem_0_6/DI0	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.000	0.000	0.474
6	0.337	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[4]/Q	u_la0_top/u_ao_mem_ctrl/mem_mem_0_17/ADA5	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.000	0.000	0.455
7	0.351	u_la0_top/u_ao_mem_ctrl/data_reg_Z[13]/Q	u_la0_top/u_ao_mem_ctrl/mem_mem_0_6/DI1	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.000	0.000	0.600
8	0.352	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8]/Q	u_la0_top/u_ao_mem_ctrl/mem_mem_0_17/ADA9	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.000	0.000	0.470
9	0.352	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8]/Q	u_la0_top/u_ao_mem_ctrl/mem_mem_0_12/ADA9	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.000	0.000	0.470
10	0.352	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[11]/Q	u_la0_top/u_ao_mem_ctrl/mem_mem_0_17/ADA12	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.000	0.000	0.470
11	0.353	cnt_1_Z[0]/Q	memr_memr_0_7/ADB1	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.000	0.000	0.471
12	0.353	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[12]/Q	u_la0_top/u_ao_mem_ctrl/mem_mem_0_17/ADA13	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.000	0.000	0.471
13	0.353	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[12]/Q	u_la0_top/u_ao_mem_ctrl/mem_mem_0_12/ADA13	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.000	0.000	0.471
14	0.353	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[4]/Q	u_la0_top/u_ao_mem_ctrl/mem_mem_0_12/ADA5	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.000	0.000	0.471
15	0.353	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[6]/Q	u_la0_top/u_ao_mem_ctrl/mem_mem_0_22/ADA7	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.000	0.000	0.471
16	0.354	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[11]/Q	u_la0_top/u_ao_mem_ctrl/mem_mem_0_12/ADA12	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.000	0.000	0.472
17	0.354	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[5]/Q	u_la0_top/u_ao_mem_ctrl/mem_mem_0_22/ADA6	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.000	0.000	0.472
18	0.354	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[5]/Q	u_la0_top/u_ao_mem_ctrl/mem_mem_0_17/ADA6	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.000	0.000	0.472
19	0.355	cnt_1_Z[12]/Q	memr_memr_0_10/ADB13	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.000	0.000	0.473
20	0.358	cnt_1_Z[6]/Q	memr_memr_0_10/ADB7	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.000	0.000	0.476
21	0.359	cnt_1_Z[11]/Q	memr_memr_0_11/ADB12	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.000	0.000	0.477
22	0.361	cnt_1_Z[12]/Q	memr_memr_0_11/ADB13	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.000	0.000	0.479
23	0.363	u_la0_top/u_ao_mem_ctrl/data_reg_Z[55]/Q	u_la0_top/u_ao_mem_ctrl/mem_mem_0_27/DI1	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.000	0.000	0.612
24	0.364	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8]/Q	u_la0_top/u_ao_mem_ctrl/mem_mem_0_27/ADA9	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.000	0.000	0.482
25	0.373	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[4]/Q	u_la0_top/u_ao_mem_ctrl/mem_mem_0_27/ADA5	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.000	0.000	0.491

Recovery Paths Table

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	1.748	u_la0_top/rst_ao_Z/Q	u_la0_top/triger_level_cnt_Z[0]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	5.000	0.033	2.984
2	1.748	u_la0_top/rst_ao_Z/Q	u_la0_top/triger_level_cnt_Z[2]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	5.000	0.033	2.984
3	1.748	u_la0_top/rst_ao_Z/Q	u_la0_top/capture_window_sel[3]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	5.000	0.033	2.984
4	1.748	u_la0_top/rst_ao_Z/Q	u_la0_top/internal_reg_force_triger_syn_Z[0]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	5.000	0.033	2.984
5	1.748	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_length_Z[12]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	5.000	0.033	2.984
6	1.748	u_la0_top/rst_ao_Z/Q	u_la0_top/internal_reg_start_syn_Z[0]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	5.000	0.033	2.984
7	1.748	u_la0_top/rst_ao_Z/Q	u_la0_top/internal_reg_start_dly_Z[0]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	5.000	0.033	2.984
8	1.748	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	5.000	0.033	2.984
9	1.748	u_la0_top/rst_ao_Z/Q	u_la0_top/capture_window_sel_Z[2]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	5.000	0.033	2.984
10	1.748	u_la0_top/rst_ao_Z/Q	u_la0_top/capture_end_dly_Z/PRESET	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	5.000	0.033	2.984
11	1.748	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	5.000	0.033	2.984
12	1.748	u_la0_top/rst_ao_Z/Q	u_la0_top/capture_window_sel_Z[1]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	5.000	0.033	2.984
13	1.748	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_length_Z[4]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	5.000	0.033	2.984
14	1.748	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_length_Z[3]/PRESET	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	5.000	0.033	2.984
15	1.748	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_length_Z[9]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	5.000	0.033	2.984
16	1.748	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[12]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	5.000	0.033	2.984
17	1.748	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[2]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	5.000	0.033	2.984
18	1.748	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[1]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	5.000	0.033	2.984
19	1.748	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_length_Z[7]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	5.000	0.033	2.984
20	1.748	u_la0_top/rst_ao_Z/Q	u_la0_top/trigger_seq_start_Z/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	5.000	0.033	2.984
21	1.748	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[9]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	5.000	0.033	2.984
22	1.748	u_la0_top/rst_ao_Z/Q	u_la0_top/genblk1.u_ao_match_0/match_sep/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	5.000	0.033	2.984
23	1.748	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[3]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	5.000	0.033	2.984
24	1.748	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	5.000	0.033	2.984
25	1.748	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_length_Z[2]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	5.000	0.033	2.984

Removal Paths Table

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	6.760	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	-5.000	0.013	1.958
2	6.760	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_Z/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	-5.000	0.013	1.958
3	6.760	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_loop_Z/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	-5.000	0.013	1.958
4	6.760	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_length_Z[0]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	-5.000	0.013	1.958
5	6.760	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_length_Z[1]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	-5.000	0.013	1.958
6	6.760	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_length_Z[2]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	-5.000	0.013	1.958
7	6.760	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_length_Z[3]/PRESET	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	-5.000	0.013	1.958
8	6.760	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_length_Z[4]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	-5.000	0.013	1.958
9	6.760	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_length_Z[5]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	-5.000	0.013	1.958
10	6.760	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_length_Z[6]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	-5.000	0.013	1.958
11	6.760	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_length_Z[7]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	-5.000	0.013	1.958
12	6.760	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_length_Z[8]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	-5.000	0.013	1.958
13	6.760	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_length_Z[9]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	-5.000	0.013	1.958
14	6.760	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_length_Z[10]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	-5.000	0.013	1.958
15	6.760	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_length_Z[11]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	-5.000	0.013	1.958
16	6.760	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_length_Z[12]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	-5.000	0.013	1.958
17	6.760	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	-5.000	0.013	1.958
18	6.760	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[1]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	-5.000	0.013	1.958
19	6.760	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[2]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	-5.000	0.013	1.958
20	6.760	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[3]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	-5.000	0.013	1.958
21	6.760	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[4]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	-5.000	0.013	1.958
22	6.760	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[5]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	-5.000	0.013	1.958
23	6.760	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[6]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	-5.000	0.013	1.958
24	6.760	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[7]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	-5.000	0.013	1.958
25	6.760	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	-5.000	0.013	1.958

Minimum Pulse Width Table:

Report Command:report_min_pulse_width -nworst 10 -detail

Number	Slack	Actual Width	Required Width	Type	Clock	Objects
1	3.662	4.662	1.000	Low Pulse Width	DEFAULT_CLK	cnt_1_Z[12]
2	3.662	4.662	1.000	Low Pulse Width	DEFAULT_CLK	cnt_1_Z[10]
3	3.662	4.662	1.000	Low Pulse Width	DEFAULT_CLK	cnt_1_Z[6]
4	3.662	4.662	1.000	Low Pulse Width	DEFAULT_CLK	cnt_Z[11]
5	3.662	4.662	1.000	Low Pulse Width	DEFAULT_CLK	dividend[24]
6	3.662	4.662	1.000	Low Pulse Width	DEFAULT_CLK	memr_memr_0_0
7	3.662	4.662	1.000	Low Pulse Width	DEFAULT_CLK	Mdu/u_mdu/reg0_Z[31]
8	3.662	4.662	1.000	Low Pulse Width	DEFAULT_CLK	Mdu/u_mdu/reg0_fast_Z[24]
9	3.662	4.662	1.000	Low Pulse Width	DEFAULT_CLK	Mdu/u_mdu/reg0_1_rep1_Z
10	3.662	4.662	1.000	Low Pulse Width	DEFAULT_CLK	Mdu/u_mdu/reg0_Z[30]

Timing Report By Analysis Type:

Setup Analysis Report

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	0.397
Data Arrival Time	11.252
Data Required Time	11.648
From	Mdu/u_mdu/div_shift_number_Z[3]
To	Mdu/u_mdu/reg0_Z[61]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.683	0.683	tINS	RR	496	IOT48[A]	clk_ibuf/O
1.883	1.201	tNET	RR	1	R42C57[2][B]	Mdu/u_mdu/div_shift_number_Z[3]/CLK
2.115	0.232	tC2Q	RF	12	R42C57[2][B]	Mdu/u_mdu/div_shift_number_Z[3]/Q
2.552	0.437	tNET	FF	1	R43C55[1][A]	Mdu/u_mdu/div_shift_number_RNI5MR3_1[2]/I1
3.107	0.555	tINS	FF	57	R43C55[1][A]	Mdu/u_mdu/div_shift_number_RNI5MR3_1[2]/F
5.980	2.873	tNET	FF	1	R52C47[0][A]	Mdu/u_mdu/m45_2_03_1_cZ/I0
6.529	0.549	tINS	FR	1	R52C47[0][A]	Mdu/u_mdu/m45_2_03_1_cZ/F
6.673	0.144	tNET	RR	1	R52C47[0][B]	Mdu/u_mdu/m45_2_03_cZ/I1
7.228	0.555	tINS	RF	2	R52C47[0][B]	Mdu/u_mdu/m45_2_03_cZ/F
7.890	0.662	tNET	FF	1	R47C47[3][A]	Mdu/u_mdu/m61_4_03_0_0_cZ/I2
8.343	0.453	tINS	FF	1	R47C47[3][A]	Mdu/u_mdu/m61_4_03_0_0_cZ/F
9.270	0.927	tNET	FF	1	R37C50[2][B]	Mdu/u_mdu/reg0_exe_nx_m1_cZ[61]/I1
9.723	0.453	tINS	FF	1	R37C50[2][B]	Mdu/u_mdu/reg0_exe_nx_m1_cZ[61]/F
9.723	0.000	tNET	FF	1	R37C50[2][A]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[61]/I1
9.826	0.103	tINS	FF	1	R37C50[2][A]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[61]/O
10.682	0.856	tNET	FF	1	R44C52[2][A]	Mdu/u_mdu/reg0_nx_cZ[61]/I0
11.252	0.570	tINS	FR	1	R44C52[2][A]	Mdu/u_mdu/reg0_nx_cZ[61]/F
11.252	0.000	tNET	RR	1	R44C52[2][A]	Mdu/u_mdu/reg0_Z[61]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	496	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R44C52[2][A]	Mdu/u_mdu/reg0_Z[61]/CLK
11.683	-0.200	tUnc				Mdu/u_mdu/reg0_Z[61]
11.648	-0.035	tSu		1	R44C52[2][A]	Mdu/u_mdu/reg0_Z[61]

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 3.238, 34.563%; route: 5.898, 62.960%; tC2Q: 0.232, 2.476%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path2

Path Summary:

Slack	0.607
Data Arrival Time	11.042
Data Required Time	11.648
From	Mdu/u_mdu/div_shift_number_Z[0]
To	Mdu/u_mdu/reg0_Z[62]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.683	0.683	tINS	RR	496	IOT48[A]	clk_ibuf/O
1.883	1.201	tNET	RR	1	R42C57[1][A]	Mdu/u_mdu/div_shift_number_Z[0]/CLK
2.115	0.232	tC2Q	RF	113	R42C57[1][A]	Mdu/u_mdu/div_shift_number_Z[0]/Q
3.724	1.609	tNET	FF	1	R46C57[3][B]	Mdu/u_mdu/m2_0_03_m1_e_1_cZ/I0
4.273	0.549	tINS	FR	1	R46C57[3][B]	Mdu/u_mdu/m2_0_03_m1_e_1_cZ/F
4.274	0.001	tNET	RR	1	R46C57[2][B]	Mdu/u_mdu/m2_0_03_m1_e/I2
4.791	0.517	tINS	RF	6	R46C57[2][B]	Mdu/u_mdu/m2_0_03_m1_e/F
5.331	0.540	tNET	FF	1	R46C51[3][A]	Mdu/u_mdu/m14_2_03_0_0_cZ/I0
5.848	0.517	tINS	FF	2	R46C51[3][A]	Mdu/u_mdu/m14_2_03_0_0_cZ/F
6.510	0.662	tNET	FF	1	R46C46[3][B]	Mdu/u_mdu/m14_2_03_0_0_RNI70O1/I0
7.065	0.555	tINS	FF	3	R46C46[3][B]	Mdu/u_mdu/m14_2_03_0_0_RNI70O1/F
8.146	1.081	tNET	FF	1	R43C51[1][B]	Mdu/u_mdu/m62_4_03_0_0_cZ/I0
8.517	0.371	tINS	FF	1	R43C51[1][B]	Mdu/u_mdu/m62_4_03_0_0_cZ/F
9.173	0.656	tNET	FF	1	R38C51[2][A]	Mdu/u_mdu/reg0_exe_nx_m0_cZ[62]/I1
9.544	0.371	tINS	FF	1	R38C51[2][A]	Mdu/u_mdu/reg0_exe_nx_m0_cZ[62]/F
9.544	0.000	tNET	FF	1	R38C51[2][A]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[62]/I0
9.647	0.103	tINS	FF	1	R38C51[2][A]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[62]/O
10.580	0.933	tNET	FF	1	R46C49[0][A]	Mdu/u_mdu/reg0_nx_cZ[62]/I0
11.042	0.462	tINS	FR	1	R46C49[0][A]	Mdu/u_mdu/reg0_nx_cZ[62]/F
11.042	0.000	tNET	RR	1	R46C49[0][A]	Mdu/u_mdu/reg0_Z[62]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	496	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R46C49[0][A]	Mdu/u_mdu/reg0_Z[62]/CLK
11.683	-0.200	tUnc				Mdu/u_mdu/reg0_Z[62]
11.648	-0.035	tSu		1	R46C49[0][A]	Mdu/u_mdu/reg0_Z[62]

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	8
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 3.445, 37.616%; route: 5.481, 59.851%; tC2Q: 0.232, 2.533%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path3

Path Summary:

Slack	0.742
Data Arrival Time	10.906
Data Required Time	11.648
From	Mdu/u_mdu/div_shift_number_Z[0]
To	Mdu/u_mdu/reg0_Z[30]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.683	0.683	tINS	RR	496	IOT48[A]	clk_ibuf/O
1.883	1.201	tNET	RR	1	R42C57[1][A]	Mdu/u_mdu/div_shift_number_Z[0]/CLK
2.115	0.232	tC2Q	RF	113	R42C57[1][A]	Mdu/u_mdu/div_shift_number_Z[0]/Q
3.724	1.609	tNET	FF	1	R46C57[3][B]	Mdu/u_mdu/m2_0_03_m1_e_1_cZ/I0
4.273	0.549	tINS	FR	1	R46C57[3][B]	Mdu/u_mdu/m2_0_03_m1_e_1_cZ/F
4.274	0.001	tNET	RR	1	R46C57[2][B]	Mdu/u_mdu/m2_0_03_m1_e/I2
4.791	0.517	tINS	RF	6	R46C57[2][B]	Mdu/u_mdu/m2_0_03_m1_e/F
5.331	0.540	tNET	FF	1	R46C51[3][A]	Mdu/u_mdu/m14_2_03_0_0_cZ/I0
5.848	0.517	tINS	FF	2	R46C51[3][A]	Mdu/u_mdu/m14_2_03_0_0_cZ/F
6.510	0.662	tNET	FF	1	R46C46[3][B]	Mdu/u_mdu/m14_2_03_0_0_RNI70O1/I0
7.065	0.555	tINS	FF	3	R46C46[3][B]	Mdu/u_mdu/m14_2_03_0_0_RNI70O1/F
7.996	0.931	tNET	FF	1	R43C52[2][A]	Mdu/u_mdu/m30_4_01_cZ/I1
8.458	0.462	tINS	FR	1	R43C52[2][A]	Mdu/u_mdu/m30_4_01_cZ/F
8.460	0.001	tNET	RR	1	R43C52[0][B]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[30]/I2
8.913	0.453	tINS	RF	1	R43C52[0][B]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[30]/F
9.326	0.413	tNET	FF	1	R41C52[3][A]	Mdu/u_mdu/reg0_exe_nx_cZ[30]/I3
9.779	0.453	tINS	FF	2	R41C52[3][A]	Mdu/u_mdu/reg0_exe_nx_cZ[30]/F
10.444	0.665	tNET	FF	1	R42C49[2][A]	Mdu/u_mdu/reg0_nx_cZ[30]/I0
10.906	0.462	tINS	FR	1	R42C49[2][A]	Mdu/u_mdu/reg0_nx_cZ[30]/F
10.906	0.000	tNET	RR	1	R42C49[2][A]	Mdu/u_mdu/reg0_Z[30]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	496	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R42C49[2][A]	Mdu/u_mdu/reg0_Z[30]/CLK
11.683	-0.200	tUnc				Mdu/u_mdu/reg0_Z[30]
11.648	-0.035	tSu		1	R42C49[2][A]	Mdu/u_mdu/reg0_Z[30]

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	8
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 3.968, 43.979%; route: 4.823, 53.450%; tC2Q: 0.232, 2.571%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path4

Path Summary:

Slack	0.800
Data Arrival Time	10.848
Data Required Time	11.648
From	Mdu/u_mdu/cnt_Z[1]
To	Mdu/u_mdu/reg0_fast_Z[17]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.683	0.683	tINS	RR	496	IOT48[A]	clk_ibuf/O
1.883	1.201	tNET	RR	1	R43C58[2][A]	Mdu/u_mdu/cnt_Z[1]/CLK
2.115	0.232	tC2Q	RF	3	R43C58[2][A]	Mdu/u_mdu/cnt_Z[1]/Q
2.522	0.407	tNET	FF	1	R43C57[3][A]	Mdu/u_mdu/un1_cnt_1_0_a2_0_1_cZ_cZ/I0
3.039	0.517	tINS	FF	8	R43C57[3][A]	Mdu/u_mdu/un1_cnt_1_0_a2_0_1_cZ_cZ/F
4.151	1.112	tNET	FF	1	R40C46[3][B]	Mdu/u_mdu/reg0_exe_nx_m2s2/I2
4.668	0.517	tINS	FF	74	R40C46[3][B]	Mdu/u_mdu/reg0_exe_nx_m2s2/F
7.473	2.805	tNET	FF	1	R51C51[1][B]	Mdu/u_mdu/reg0_exe_nx_m2_d_cZ[17]/I2
7.935	0.462	tINS	FR	1	R51C51[1][B]	Mdu/u_mdu/reg0_exe_nx_m2_d_cZ[17]/F
7.936	0.001	tNET	RR	1	R51C51[2][A]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[17]/I0
8.491	0.555	tINS	RF	1	R51C51[2][A]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[17]/F
9.131	0.640	tNET	FF	1	R47C51[2][A]	Mdu/u_mdu/reg0_exe_nx_cZ[17]/I3
9.648	0.517	tINS	FF	2	R47C51[2][A]	Mdu/u_mdu/reg0_exe_nx_cZ[17]/F
10.386	0.738	tNET	FF	1	R43C53[0][A]	Mdu/u_mdu/reg0_nx_fast_cZ[17]/I0
10.848	0.462	tINS	FR	1	R43C53[0][A]	Mdu/u_mdu/reg0_nx_fast_cZ[17]/F
10.848	0.000	tNET	RR	1	R43C53[0][A]	Mdu/u_mdu/reg0_fast_Z[17]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	496	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R43C53[0][A]	Mdu/u_mdu/reg0_fast_Z[17]/CLK
11.683	-0.200	tUnc				Mdu/u_mdu/reg0_fast_Z[17]
11.648	-0.035	tSu		1	R43C53[0][A]	Mdu/u_mdu/reg0_fast_Z[17]

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	6
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 3.030, 33.798%; route: 5.703, 63.614%; tC2Q: 0.232, 2.588%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path5

Path Summary:

Slack	0.800
Data Arrival Time	10.848
Data Required Time	11.648
From	Mdu/u_mdu/cnt_Z[1]
To	Mdu/u_mdu/reg0_Z[17]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.683	0.683	tINS	RR	496	IOT48[A]	clk_ibuf/O
1.883	1.201	tNET	RR	1	R43C58[2][A]	Mdu/u_mdu/cnt_Z[1]/CLK
2.115	0.232	tC2Q	RF	3	R43C58[2][A]	Mdu/u_mdu/cnt_Z[1]/Q
2.522	0.407	tNET	FF	1	R43C57[3][A]	Mdu/u_mdu/un1_cnt_1_0_a2_0_1_cZ_cZ/I0
3.039	0.517	tINS	FF	8	R43C57[3][A]	Mdu/u_mdu/un1_cnt_1_0_a2_0_1_cZ_cZ/F
4.151	1.112	tNET	FF	1	R40C46[3][B]	Mdu/u_mdu/reg0_exe_nx_m2s2/I2
4.668	0.517	tINS	FF	74	R40C46[3][B]	Mdu/u_mdu/reg0_exe_nx_m2s2/F
7.473	2.805	tNET	FF	1	R51C51[1][B]	Mdu/u_mdu/reg0_exe_nx_m2_d_cZ[17]/I2
7.935	0.462	tINS	FR	1	R51C51[1][B]	Mdu/u_mdu/reg0_exe_nx_m2_d_cZ[17]/F
7.936	0.001	tNET	RR	1	R51C51[2][A]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[17]/I0
8.491	0.555	tINS	RF	1	R51C51[2][A]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[17]/F
9.131	0.640	tNET	FF	1	R47C51[2][A]	Mdu/u_mdu/reg0_exe_nx_cZ[17]/I3
9.648	0.517	tINS	FF	2	R47C51[2][A]	Mdu/u_mdu/reg0_exe_nx_cZ[17]/F
10.386	0.738	tNET	FF	1	R43C53[1][A]	Mdu/u_mdu/reg0_nx_cZ[17]/I0
10.848	0.462	tINS	FR	1	R43C53[1][A]	Mdu/u_mdu/reg0_nx_cZ[17]/F
10.848	0.000	tNET	RR	1	R43C53[1][A]	Mdu/u_mdu/reg0_Z[17]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	496	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R43C53[1][A]	Mdu/u_mdu/reg0_Z[17]/CLK
11.683	-0.200	tUnc				Mdu/u_mdu/reg0_Z[17]
11.648	-0.035	tSu		1	R43C53[1][A]	Mdu/u_mdu/reg0_Z[17]

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	6
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 3.030, 33.798%; route: 5.703, 63.614%; tC2Q: 0.232, 2.588%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path6

Path Summary:

Slack	0.880
Data Arrival Time	10.768
Data Required Time	11.648
From	Mdu/u_mdu/div_shift_number_Z[3]
To	Mdu/u_mdu/reg0_Z[53]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.683	0.683	tINS	RR	496	IOT48[A]	clk_ibuf/O
1.883	1.201	tNET	RR	1	R42C57[2][B]	Mdu/u_mdu/div_shift_number_Z[3]/CLK
2.115	0.232	tC2Q	RF	12	R42C57[2][B]	Mdu/u_mdu/div_shift_number_Z[3]/Q
2.552	0.437	tNET	FF	1	R43C55[1][A]	Mdu/u_mdu/div_shift_number_RNI5MR3_1[2]/I1
3.107	0.555	tINS	FF	57	R43C55[1][A]	Mdu/u_mdu/div_shift_number_RNI5MR3_1[2]/F
5.737	2.630	tNET	FF	1	R52C46[2][B]	Mdu/u_mdu/m37_2_03_1_cZ/I0
6.292	0.555	tINS	FF	2	R52C46[2][B]	Mdu/u_mdu/m37_2_03_1_cZ/F
6.714	0.422	tNET	FF	1	R51C48[2][A]	Mdu/u_mdu/m37_2_03_cZ/I2
7.284	0.570	tINS	FR	1	R51C48[2][A]	Mdu/u_mdu/m37_2_03_cZ/F
7.286	0.001	tNET	RR	1	R51C48[3][A]	Mdu/u_mdu/m53_4_03_1_0_cZ/I2
7.739	0.453	tINS	RF	1	R51C48[3][A]	Mdu/u_mdu/m53_4_03_1_0_cZ/F
8.617	0.878	tNET	FF	1	R35C48[1][B]	Mdu/u_mdu/reg0_exe_nx_m1_cZ[53]/I2
9.070	0.453	tINS	FF	1	R35C48[1][B]	Mdu/u_mdu/reg0_exe_nx_m1_cZ[53]/F
9.070	0.000	tNET	FF	1	R35C48[1][A]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[53]/I1
9.173	0.103	tINS	FF	1	R35C48[1][A]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[53]/O
10.397	1.224	tNET	FF	1	R34C48[0][B]	Mdu/u_mdu/reg0_nx_0[53]/I2
10.768	0.371	tINS	FF	1	R34C48[0][B]	Mdu/u_mdu/reg0_nx_0[53]/F
10.768	0.000	tNET	FF	1	R34C48[0][B]	Mdu/u_mdu/reg0_Z[53]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	496	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R34C48[0][B]	Mdu/u_mdu/reg0_Z[53]/CLK
11.683	-0.200	tUnc				Mdu/u_mdu/reg0_Z[53]
11.648	-0.035	tSu		1	R34C48[0][B]	Mdu/u_mdu/reg0_Z[53]

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 3.060, 34.441%; route: 5.593, 62.948%; tC2Q: 0.232, 2.611%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path7

Path Summary:

Slack	0.901
Data Arrival Time	10.747
Data Required Time	11.648
From	Mdu/u_mdu/div_shift_number_Z[0]
To	Mdu/u_mdu/reg0_Z[21]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.683	0.683	tINS	RR	496	IOT48[A]	clk_ibuf/O
1.883	1.201	tNET	RR	1	R42C57[1][A]	Mdu/u_mdu/div_shift_number_Z[0]/CLK
2.115	0.232	tC2Q	RF	113	R42C57[1][A]	Mdu/u_mdu/div_shift_number_Z[0]/Q
3.724	1.609	tNET	FF	1	R46C57[0][A]	Mdu/u_mdu/m5_0_03_1_cZ/I0
4.273	0.549	tINS	FR	1	R46C57[0][A]	Mdu/u_mdu/m5_0_03_1_cZ/F
4.445	0.172	tNET	RR	1	R47C57[1][A]	Mdu/u_mdu/m5_0_03_cZ/I1
4.962	0.517	tINS	RF	5	R47C57[1][A]	Mdu/u_mdu/m5_0_03_cZ/F
5.741	0.779	tNET	FF	1	R48C51[3][B]	Mdu/u_mdu/m5_2_03_cZ/I3
6.311	0.570	tINS	FR	4	R48C51[3][B]	Mdu/u_mdu/m5_2_03_cZ/F
6.486	0.175	tNET	RR	1	R49C51[2][B]	Mdu/u_mdu/m21_4_01_cZ/I1
6.939	0.453	tINS	RF	1	R49C51[2][B]	Mdu/u_mdu/m21_4_01_cZ/F
7.700	0.761	tNET	FF	1	R51C57[1][A]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[21]/I2
8.162	0.462	tINS	FR	1	R51C57[1][A]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[21]/F
8.334	0.172	tNET	RR	1	R52C57[3][A]	Mdu/u_mdu/reg0_exe_nx_cZ[21]/I3
8.796	0.462	tINS	RR	1	R52C57[3][A]	Mdu/u_mdu/reg0_exe_nx_cZ[21]/F
8.798	0.001	tNET	RR	1	R52C57[1][B]	Mdu/u_mdu/reg0_nx_sx_cZ[21]/I0
9.251	0.453	tINS	RF	1	R52C57[1][B]	Mdu/u_mdu/reg0_nx_sx_cZ[21]/F
10.177	0.927	tNET	FF	1	R49C50[2][A]	Mdu/u_mdu/reg0_nx_cZ[21]/I0
10.747	0.570	tINS	FR	1	R49C50[2][A]	Mdu/u_mdu/reg0_nx_cZ[21]/F
10.747	0.000	tNET	RR	1	R49C50[2][A]	Mdu/u_mdu/reg0_Z[21]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	496	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R49C50[2][A]	Mdu/u_mdu/reg0_Z[21]/CLK
11.683	-0.200	tUnc				Mdu/u_mdu/reg0_Z[21]
11.648	-0.035	tSu		1	R49C50[2][A]	Mdu/u_mdu/reg0_Z[21]

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	8
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 4.036, 45.531%; route: 4.596, 51.852%; tC2Q: 0.232, 2.617%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path8

Path Summary:

Slack	0.908
Data Arrival Time	10.740
Data Required Time	11.648
From	Mdu/u_mdu/cnt_Z[1]
To	Mdu/u_mdu/reg0_fast_Z[19]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.683	0.683	tINS	RR	496	IOT48[A]	clk_ibuf/O
1.883	1.201	tNET	RR	1	R43C58[2][A]	Mdu/u_mdu/cnt_Z[1]/CLK
2.115	0.232	tC2Q	RF	3	R43C58[2][A]	Mdu/u_mdu/cnt_Z[1]/Q
2.522	0.407	tNET	FF	1	R43C57[3][A]	Mdu/u_mdu/un1_cnt_1_0_a2_0_1_cZ_cZ/I0
3.039	0.517	tINS	FF	8	R43C57[3][A]	Mdu/u_mdu/un1_cnt_1_0_a2_0_1_cZ_cZ/F
4.151	1.112	tNET	FF	1	R40C46[3][B]	Mdu/u_mdu/reg0_exe_nx_m2s2/I2
4.668	0.517	tINS	FF	74	R40C46[3][B]	Mdu/u_mdu/reg0_exe_nx_m2s2/F
7.479	2.811	tNET	FF	1	R50C52[3][B]	Mdu/u_mdu/reg0_exe_nx_m2_d_cZ[19]/I2
8.049	0.570	tINS	FR	1	R50C52[3][B]	Mdu/u_mdu/reg0_exe_nx_m2_d_cZ[19]/F
8.221	0.172	tNET	RR	1	R50C51[3][A]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[19]/I0
8.674	0.453	tINS	RF	1	R50C51[3][A]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[19]/F
9.192	0.518	tNET	FF	1	R40C51[3][A]	Mdu/u_mdu/reg0_exe_nx_cZ[19]/I3
9.747	0.555	tINS	FF	3	R40C51[3][A]	Mdu/u_mdu/reg0_exe_nx_cZ[19]/F
10.170	0.423	tNET	FF	1	R42C50[0][A]	Mdu/u_mdu/reg0_nx_fast_cZ[19]/I0
10.740	0.570	tINS	FR	1	R42C50[0][A]	Mdu/u_mdu/reg0_nx_fast_cZ[19]/F
10.740	0.000	tNET	RR	1	R42C50[0][A]	Mdu/u_mdu/reg0_fast_Z[19]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	496	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R42C50[0][A]	Mdu/u_mdu/reg0_fast_Z[19]/CLK
11.683	-0.200	tUnc				Mdu/u_mdu/reg0_fast_Z[19]
11.648	-0.035	tSu		1	R42C50[0][A]	Mdu/u_mdu/reg0_fast_Z[19]

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	6
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 3.182, 35.925%; route: 5.443, 61.455%; tC2Q: 0.232, 2.619%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path9

Path Summary:

Slack	0.908
Data Arrival Time	10.740
Data Required Time	11.648
From	Mdu/u_mdu/cnt_Z[1]
To	Mdu/u_mdu/reg0_Z[19]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.683	0.683	tINS	RR	496	IOT48[A]	clk_ibuf/O
1.883	1.201	tNET	RR	1	R43C58[2][A]	Mdu/u_mdu/cnt_Z[1]/CLK
2.115	0.232	tC2Q	RF	3	R43C58[2][A]	Mdu/u_mdu/cnt_Z[1]/Q
2.522	0.407	tNET	FF	1	R43C57[3][A]	Mdu/u_mdu/un1_cnt_1_0_a2_0_1_cZ_cZ/I0
3.039	0.517	tINS	FF	8	R43C57[3][A]	Mdu/u_mdu/un1_cnt_1_0_a2_0_1_cZ_cZ/F
4.151	1.112	tNET	FF	1	R40C46[3][B]	Mdu/u_mdu/reg0_exe_nx_m2s2/I2
4.668	0.517	tINS	FF	74	R40C46[3][B]	Mdu/u_mdu/reg0_exe_nx_m2s2/F
7.479	2.811	tNET	FF	1	R50C52[3][B]	Mdu/u_mdu/reg0_exe_nx_m2_d_cZ[19]/I2
8.049	0.570	tINS	FR	1	R50C52[3][B]	Mdu/u_mdu/reg0_exe_nx_m2_d_cZ[19]/F
8.221	0.172	tNET	RR	1	R50C51[3][A]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[19]/I0
8.674	0.453	tINS	RF	1	R50C51[3][A]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[19]/F
9.192	0.518	tNET	FF	1	R40C51[3][A]	Mdu/u_mdu/reg0_exe_nx_cZ[19]/I3
9.747	0.555	tINS	FF	3	R40C51[3][A]	Mdu/u_mdu/reg0_exe_nx_cZ[19]/F
10.170	0.423	tNET	FF	1	R42C50[1][B]	Mdu/u_mdu/reg0_nx_cZ[19]/I0
10.740	0.570	tINS	FR	1	R42C50[1][B]	Mdu/u_mdu/reg0_nx_cZ[19]/F
10.740	0.000	tNET	RR	1	R42C50[1][B]	Mdu/u_mdu/reg0_Z[19]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	496	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R42C50[1][B]	Mdu/u_mdu/reg0_Z[19]/CLK
11.683	-0.200	tUnc				Mdu/u_mdu/reg0_Z[19]
11.648	-0.035	tSu		1	R42C50[1][B]	Mdu/u_mdu/reg0_Z[19]

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	6
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 3.182, 35.925%; route: 5.443, 61.455%; tC2Q: 0.232, 2.619%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path10

Path Summary:

Slack	0.923
Data Arrival Time	10.725
Data Required Time	11.648
From	Mdu/u_mdu/reg0_Z[16]
To	Mdu/u_mdu/reg0_Z[16]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.683	0.683	tINS	RR	496	IOT48[A]	clk_ibuf/O
1.883	1.201	tNET	RR	1	R51C59[0][B]	Mdu/u_mdu/reg0_Z[16]/CLK
2.115	0.232	tC2Q	RF	17	R51C59[0][B]	Mdu/u_mdu/reg0_Z[16]/Q
3.104	0.989	tNET	FF	1	R42C53[3][B]	Mdu/u_mdu/reg0_neg_axb_16_par_0_cp_lofx_cZ/I0
3.659	0.555	tINS	FF	1	R42C53[3][B]	Mdu/u_mdu/reg0_neg_axb_16_par_0_cp_lofx_cZ/F
4.327	0.668	tNET	FF	2	R42C44[0][A]	Mdu/u_mdu/reg0_neg_axb_16_par_cp_1/I0
4.897	0.570	tINS	FR	1	R42C44[0][A]	Mdu/u_mdu/reg0_neg_axb_16_par_cp_1/COUT
4.897	0.000	tNET	RR	2	R42C44[0][B]	Mdu/u_mdu/reg0_neg_axb_19_par_1/CIN
4.932	0.035	tINS	RF	1	R42C44[0][B]	Mdu/u_mdu/reg0_neg_axb_19_par_1/COUT
4.932	0.000	tNET	FF	2	R42C44[1][A]	Mdu/u_mdu/reg0_neg_axb_23_par_1/CIN
4.968	0.035	tINS	FF	1	R42C44[1][A]	Mdu/u_mdu/reg0_neg_axb_23_par_1/COUT
4.968	0.000	tNET	FF	2	R42C44[1][B]	Mdu/u_mdu/reg0_neg_axb_27_par_1/CIN
5.003	0.035	tINS	FF	1	R42C44[1][B]	Mdu/u_mdu/reg0_neg_axb_27_par_1/COUT
5.003	0.000	tNET	FF	2	R42C44[2][A]	Mdu/u_mdu/reg0_neg_axb_31_par_1/CIN
5.038	0.035	tINS	FF	1	R42C44[2][A]	Mdu/u_mdu/reg0_neg_axb_31_par_1/COUT
5.038	0.000	tNET	FF	2	R42C44[2][B]	Mdu/u_mdu/reg0_neg_cry_34_0/CIN
5.073	0.035	tINS	FF	1	R42C44[2][B]	Mdu/u_mdu/reg0_neg_cry_34_0/COUT
5.073	0.000	tNET	FF	2	R42C45[0][A]	Mdu/u_mdu/reg0_neg_cry_35_0/CIN
5.108	0.035	tINS	FF	1	R42C45[0][A]	Mdu/u_mdu/reg0_neg_cry_35_0/COUT
5.108	0.000	tNET	FF	2	R42C45[0][B]	Mdu/u_mdu/reg0_neg_cry_36_0/CIN
5.144	0.035	tINS	FF	1	R42C45[0][B]	Mdu/u_mdu/reg0_neg_cry_36_0/COUT
5.144	0.000	tNET	FF	2	R42C45[1][A]	Mdu/u_mdu/reg0_neg_cry_37_0/CIN
5.179	0.035	tINS	FF	1	R42C45[1][A]	Mdu/u_mdu/reg0_neg_cry_37_0/COUT
5.179	0.000	tNET	FF	2	R42C45[1][B]	Mdu/u_mdu/reg0_neg_cry_38_0/CIN
5.214	0.035	tINS	FF	1	R42C45[1][B]	Mdu/u_mdu/reg0_neg_cry_38_0/COUT
5.214	0.000	tNET	FF	2	R42C45[2][A]	Mdu/u_mdu/reg0_neg_cry_39_0/CIN
5.249	0.035	tINS	FF	1	R42C45[2][A]	Mdu/u_mdu/reg0_neg_cry_39_0/COUT
5.249	0.000	tNET	FF	2	R42C45[2][B]	Mdu/u_mdu/reg0_neg_cry_40_0/CIN
5.284	0.035	tINS	FF	1	R42C45[2][B]	Mdu/u_mdu/reg0_neg_cry_40_0/COUT
5.284	0.000	tNET	FF	2	R42C46[0][A]	Mdu/u_mdu/reg0_neg_cry_41_0/CIN
5.320	0.035	tINS	FF	1	R42C46[0][A]	Mdu/u_mdu/reg0_neg_cry_41_0/COUT
5.320	0.000	tNET	FF	2	R42C46[0][B]	Mdu/u_mdu/reg0_neg_cry_42_0/CIN
5.355	0.035	tINS	FF	1	R42C46[0][B]	Mdu/u_mdu/reg0_neg_cry_42_0/COUT
5.355	0.000	tNET	FF	2	R42C46[1][A]	Mdu/u_mdu/reg0_neg_cry_43_0/CIN
5.390	0.035	tINS	FF	1	R42C46[1][A]	Mdu/u_mdu/reg0_neg_cry_43_0/COUT
5.390	0.000	tNET	FF	2	R42C46[1][B]	Mdu/u_mdu/reg0_neg_cry_44_0/CIN
5.425	0.035	tINS	FF	1	R42C46[1][B]	Mdu/u_mdu/reg0_neg_cry_44_0/COUT
5.425	0.000	tNET	FF	2	R42C46[2][A]	Mdu/u_mdu/reg0_neg_cry_45_0/CIN
5.460	0.035	tINS	FF	1	R42C46[2][A]	Mdu/u_mdu/reg0_neg_cry_45_0/COUT
5.460	0.000	tNET	FF	2	R42C46[2][B]	Mdu/u_mdu/reg0_neg_cry_46_0/CIN
5.496	0.035	tINS	FF	1	R42C46[2][B]	Mdu/u_mdu/reg0_neg_cry_46_0/COUT
5.496	0.000	tNET	FF	2	R42C47[0][A]	Mdu/u_mdu/reg0_neg_cry_47_0/CIN
5.531	0.035	tINS	FF	1	R42C47[0][A]	Mdu/u_mdu/reg0_neg_cry_47_0/COUT
5.531	0.000	tNET	FF	2	R42C47[0][B]	Mdu/u_mdu/reg0_neg_cry_48_0/CIN
6.001	0.470	tINS	FF	1	R42C47[0][B]	Mdu/u_mdu/reg0_neg_cry_48_0/SUM
6.519	0.518	tNET	FF	1	R35C47[1][A]	Mdu/u_mdu/reg0_post_swap_2[16]/I2
6.890	0.371	tINS	FF	1	R35C47[1][A]	Mdu/u_mdu/reg0_post_swap_2[16]/F
6.890	0.000	tNET	FF	1	R35C47[1][A]	Mdu/u_mdu/reg0_post_swap_4[16]/I0
6.993	0.103	tINS	FF	1	R35C47[1][A]	Mdu/u_mdu/reg0_post_swap_4[16]/O
7.953	0.961	tNET	FF	1	R42C52[1][A]	Mdu/u_mdu/reg0_post_swap_5[16]/I1
8.508	0.555	tINS	FF	2	R42C52[1][A]	Mdu/u_mdu/reg0_post_swap_5[16]/F
9.225	0.717	tNET	FF	1	R51C56[1][A]	Mdu/u_mdu/reg0_nx_1_cZ[16]/I0
9.742	0.517	tINS	FF	1	R51C56[1][A]	Mdu/u_mdu/reg0_nx_1_cZ[16]/F
10.155	0.413	tNET	FF	1	R51C59[0][B]	Mdu/u_mdu/reg0_nx_cZ[16]/I1
10.725	0.570	tINS	FR	1	R51C59[0][B]	Mdu/u_mdu/reg0_nx_cZ[16]/F
10.725	0.000	tNET	RR	1	R51C59[0][B]	Mdu/u_mdu/reg0_Z[16]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	496	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R51C59[0][B]	Mdu/u_mdu/reg0_Z[16]/CLK
11.683	-0.200	tUnc				Mdu/u_mdu/reg0_Z[16]
11.648	-0.035	tSu		1	R51C59[0][B]	Mdu/u_mdu/reg0_Z[16]

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	8
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 4.345, 49.136%; route: 4.265, 48.241%; tC2Q: 0.232, 2.624%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path11

Path Summary:

Slack	0.975
Data Arrival Time	10.673
Data Required Time	11.648
From	Mdu/u_mdu/div_shift_number_Z[0]
To	Mdu/u_mdu/reg0_Z[48]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.683	0.683	tINS	RR	496	IOT48[A]	clk_ibuf/O
1.883	1.201	tNET	RR	1	R42C57[1][A]	Mdu/u_mdu/div_shift_number_Z[0]/CLK
2.115	0.232	tC2Q	RF	113	R42C57[1][A]	Mdu/u_mdu/div_shift_number_Z[0]/Q
3.724	1.609	tNET	FF	1	R46C57[0][B]	Mdu/u_mdu/m20_0_03_1_cZ/I0
4.273	0.549	tINS	FR	1	R46C57[0][B]	Mdu/u_mdu/m20_0_03_1_cZ/F
4.274	0.001	tNET	RR	1	R46C57[3][A]	Mdu/u_mdu/m20_0_03_cZ/I1
4.829	0.555	tINS	RF	4	R46C57[3][A]	Mdu/u_mdu/m20_0_03_cZ/F
5.255	0.426	tNET	FF	1	R48C56[2][B]	Mdu/u_mdu/m32_2_03_0_0_cZ/I2
5.804	0.549	tINS	FR	2	R48C56[2][B]	Mdu/u_mdu/m32_2_03_0_0_cZ/F
5.980	0.176	tNET	RR	1	R48C57[2][B]	Mdu/u_mdu/m32_2_03_0_0_RNI74SI/I0
6.535	0.555	tINS	RF	2	R48C57[2][B]	Mdu/u_mdu/m32_2_03_0_0_RNI74SI/F
7.682	1.147	tNET	FF	1	R46C54[0][B]	Mdu/u_mdu/m48_4_03_1_0_cZ/I0
8.135	0.453	tINS	FF	1	R46C54[0][B]	Mdu/u_mdu/m48_4_03_1_0_cZ/F
9.333	1.198	tNET	FF	1	R34C50[3][B]	Mdu/u_mdu/reg0_exe_nx_m1_cZ[48]/I2
9.704	0.371	tINS	FF	1	R34C50[3][B]	Mdu/u_mdu/reg0_exe_nx_m1_cZ[48]/F
9.704	0.000	tNET	FF	1	R34C50[3][A]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[48]/I1
9.807	0.103	tINS	FF	1	R34C50[3][A]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[48]/O
10.302	0.496	tNET	FF	1	R32C48[2][A]	Mdu/u_mdu/reg0_nx_0[48]/I2
10.673	0.371	tINS	FF	1	R32C48[2][A]	Mdu/u_mdu/reg0_nx_0[48]/F
10.673	0.000	tNET	FF	1	R32C48[2][A]	Mdu/u_mdu/reg0_Z[48]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	496	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R32C48[2][A]	Mdu/u_mdu/reg0_Z[48]/CLK
11.683	-0.200	tUnc				Mdu/u_mdu/reg0_Z[48]
11.648	-0.035	tSu		1	R32C48[2][A]	Mdu/u_mdu/reg0_Z[48]

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	8
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 3.506, 39.885%; route: 5.052, 57.476%; tC2Q: 0.232, 2.639%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path12

Path Summary:

Slack	0.982
Data Arrival Time	10.666
Data Required Time	11.648
From	Mdu/u_mdu/div_shift_number_Z[0]
To	Mdu/u_mdu/reg0_31_rep1_Z
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.683	0.683	tINS	RR	496	IOT48[A]	clk_ibuf/O
1.883	1.201	tNET	RR	1	R42C57[1][A]	Mdu/u_mdu/div_shift_number_Z[0]/CLK
2.115	0.232	tC2Q	RF	113	R42C57[1][A]	Mdu/u_mdu/div_shift_number_Z[0]/Q
3.766	1.651	tNET	FF	1	R48C49[3][B]	Mdu/u_mdu/m3_0_03_1_0_cZ/I0
4.336	0.570	tINS	FR	5	R48C49[3][B]	Mdu/u_mdu/m3_0_03_1_0_cZ/F
4.514	0.178	tNET	RR	1	R48C50[1][B]	Mdu/u_mdu/m3_0_03_0_0_RNIV0NN/I1
5.069	0.555	tINS	RF	3	R48C50[1][B]	Mdu/u_mdu/m3_0_03_0_0_RNIV0NN/F
5.496	0.427	tNET	FF	1	R49C49[2][A]	Mdu/u_mdu/m15_2_03_0_0_cZ/I0
6.051	0.555	tINS	FF	2	R49C49[2][A]	Mdu/u_mdu/m15_2_03_0_0_cZ/F
6.545	0.494	tNET	FF	1	R47C47[1][B]	Mdu/u_mdu/m15_2_03_0_0_RNI9I0C/I0
6.998	0.453	tINS	FF	3	R47C47[1][B]	Mdu/u_mdu/m15_2_03_0_0_RNI9I0C/F
7.525	0.527	tNET	FF	1	R49C55[3][B]	Mdu/u_mdu/m31_4_01_cZ/I1
8.042	0.517	tINS	FF	1	R49C55[3][B]	Mdu/u_mdu/m31_4_01_cZ/F
8.698	0.656	tNET	FF	1	R44C55[0][A]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[31]/I2
9.069	0.371	tINS	FF	1	R44C55[0][A]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[31]/F
9.073	0.004	tNET	FF	1	R44C55[1][A]	Mdu/u_mdu/reg0_exe_nx_cZ[31]/I3
9.444	0.371	tINS	FF	3	R44C55[1][A]	Mdu/u_mdu/reg0_exe_nx_cZ[31]/F
10.096	0.652	tNET	FF	1	R48C55[0][B]	Mdu/u_mdu/reg0_nx_rep1_cZ[31]/I0
10.666	0.570	tINS	FR	1	R48C55[0][B]	Mdu/u_mdu/reg0_nx_rep1_cZ[31]/F
10.666	0.000	tNET	RR	1	R48C55[0][B]	Mdu/u_mdu/reg0_31_rep1_Z/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	496	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R48C55[0][B]	Mdu/u_mdu/reg0_31_rep1_Z/CLK
11.683	-0.200	tUnc				Mdu/u_mdu/reg0_31_rep1_Z
11.648	-0.035	tSu		1	R48C55[0][B]	Mdu/u_mdu/reg0_31_rep1_Z

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	8
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 3.962, 45.109%; route: 4.589, 52.250%; tC2Q: 0.232, 2.641%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path13

Path Summary:

Slack	0.982
Data Arrival Time	10.666
Data Required Time	11.648
From	Mdu/u_mdu/div_shift_number_Z[0]
To	Mdu/u_mdu/reg0_fast_Z[31]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.683	0.683	tINS	RR	496	IOT48[A]	clk_ibuf/O
1.883	1.201	tNET	RR	1	R42C57[1][A]	Mdu/u_mdu/div_shift_number_Z[0]/CLK
2.115	0.232	tC2Q	RF	113	R42C57[1][A]	Mdu/u_mdu/div_shift_number_Z[0]/Q
3.766	1.651	tNET	FF	1	R48C49[3][B]	Mdu/u_mdu/m3_0_03_1_0_cZ/I0
4.336	0.570	tINS	FR	5	R48C49[3][B]	Mdu/u_mdu/m3_0_03_1_0_cZ/F
4.514	0.178	tNET	RR	1	R48C50[1][B]	Mdu/u_mdu/m3_0_03_0_0_RNIV0NN/I1
5.069	0.555	tINS	RF	3	R48C50[1][B]	Mdu/u_mdu/m3_0_03_0_0_RNIV0NN/F
5.496	0.427	tNET	FF	1	R49C49[2][A]	Mdu/u_mdu/m15_2_03_0_0_cZ/I0
6.051	0.555	tINS	FF	2	R49C49[2][A]	Mdu/u_mdu/m15_2_03_0_0_cZ/F
6.545	0.494	tNET	FF	1	R47C47[1][B]	Mdu/u_mdu/m15_2_03_0_0_RNI9I0C/I0
6.998	0.453	tINS	FF	3	R47C47[1][B]	Mdu/u_mdu/m15_2_03_0_0_RNI9I0C/F
7.525	0.527	tNET	FF	1	R49C55[3][B]	Mdu/u_mdu/m31_4_01_cZ/I1
8.042	0.517	tINS	FF	1	R49C55[3][B]	Mdu/u_mdu/m31_4_01_cZ/F
8.698	0.656	tNET	FF	1	R44C55[0][A]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[31]/I2
9.069	0.371	tINS	FF	1	R44C55[0][A]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[31]/F
9.073	0.004	tNET	FF	1	R44C55[1][A]	Mdu/u_mdu/reg0_exe_nx_cZ[31]/I3
9.444	0.371	tINS	FF	3	R44C55[1][A]	Mdu/u_mdu/reg0_exe_nx_cZ[31]/F
10.096	0.652	tNET	FF	1	R48C55[0][A]	Mdu/u_mdu/reg0_nx_fast_cZ[31]/I0
10.666	0.570	tINS	FR	1	R48C55[0][A]	Mdu/u_mdu/reg0_nx_fast_cZ[31]/F
10.666	0.000	tNET	RR	1	R48C55[0][A]	Mdu/u_mdu/reg0_fast_Z[31]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	496	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R48C55[0][A]	Mdu/u_mdu/reg0_fast_Z[31]/CLK
11.683	-0.200	tUnc				Mdu/u_mdu/reg0_fast_Z[31]
11.648	-0.035	tSu		1	R48C55[0][A]	Mdu/u_mdu/reg0_fast_Z[31]

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	8
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 3.962, 45.109%; route: 4.589, 52.250%; tC2Q: 0.232, 2.641%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path14

Path Summary:

Slack	0.985
Data Arrival Time	10.663
Data Required Time	11.648
From	Mdu/u_mdu/div_shift_number_Z[0]
To	Mdu/u_mdu/reg0_fast_Z[30]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.683	0.683	tINS	RR	496	IOT48[A]	clk_ibuf/O
1.883	1.201	tNET	RR	1	R42C57[1][A]	Mdu/u_mdu/div_shift_number_Z[0]/CLK
2.115	0.232	tC2Q	RF	113	R42C57[1][A]	Mdu/u_mdu/div_shift_number_Z[0]/Q
3.724	1.609	tNET	FF	1	R46C57[3][B]	Mdu/u_mdu/m2_0_03_m1_e_1_cZ/I0
4.273	0.549	tINS	FR	1	R46C57[3][B]	Mdu/u_mdu/m2_0_03_m1_e_1_cZ/F
4.274	0.001	tNET	RR	1	R46C57[2][B]	Mdu/u_mdu/m2_0_03_m1_e/I2
4.791	0.517	tINS	RF	6	R46C57[2][B]	Mdu/u_mdu/m2_0_03_m1_e/F
5.331	0.540	tNET	FF	1	R46C51[3][A]	Mdu/u_mdu/m14_2_03_0_0_cZ/I0
5.848	0.517	tINS	FF	2	R46C51[3][A]	Mdu/u_mdu/m14_2_03_0_0_cZ/F
6.510	0.662	tNET	FF	1	R46C46[3][B]	Mdu/u_mdu/m14_2_03_0_0_RNI70O1/I0
7.065	0.555	tINS	FF	3	R46C46[3][B]	Mdu/u_mdu/m14_2_03_0_0_RNI70O1/F
7.996	0.931	tNET	FF	1	R43C52[2][A]	Mdu/u_mdu/m30_4_01_cZ/I1
8.458	0.462	tINS	FR	1	R43C52[2][A]	Mdu/u_mdu/m30_4_01_cZ/F
8.460	0.001	tNET	RR	1	R43C52[0][B]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[30]/I2
8.913	0.453	tINS	RF	1	R43C52[0][B]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[30]/F
9.326	0.413	tNET	FF	1	R41C52[3][A]	Mdu/u_mdu/reg0_exe_nx_cZ[30]/I3
9.779	0.453	tINS	FF	2	R41C52[3][A]	Mdu/u_mdu/reg0_exe_nx_cZ[30]/F
10.201	0.422	tNET	FF	1	R41C49[2][A]	Mdu/u_mdu/reg0_nx_fast_cZ[30]/I0
10.663	0.462	tINS	FR	1	R41C49[2][A]	Mdu/u_mdu/reg0_nx_fast_cZ[30]/F
10.663	0.000	tNET	RR	1	R41C49[2][A]	Mdu/u_mdu/reg0_fast_Z[30]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	496	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R41C49[2][A]	Mdu/u_mdu/reg0_fast_Z[30]/CLK
11.683	-0.200	tUnc				Mdu/u_mdu/reg0_fast_Z[30]
11.648	-0.035	tSu		1	R41C49[2][A]	Mdu/u_mdu/reg0_fast_Z[30]

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	8
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 3.968, 45.195%; route: 4.580, 52.163%; tC2Q: 0.232, 2.642%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path15

Path Summary:

Slack	1.023
Data Arrival Time	10.625
Data Required Time	11.648
From	Mdu/u_mdu/div_shift_number_Z[0]
To	Mdu/u_mdu/reg0_Z[64]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.683	0.683	tINS	RR	496	IOT48[A]	clk_ibuf/O
1.883	1.201	tNET	RR	1	R42C57[1][A]	Mdu/u_mdu/div_shift_number_Z[0]/CLK
2.115	0.232	tC2Q	RF	113	R42C57[1][A]	Mdu/u_mdu/div_shift_number_Z[0]/Q
3.724	1.609	tNET	FF	1	R46C57[0][B]	Mdu/u_mdu/m20_0_03_1_cZ/I0
4.273	0.549	tINS	FR	1	R46C57[0][B]	Mdu/u_mdu/m20_0_03_1_cZ/F
4.274	0.001	tNET	RR	1	R46C57[3][A]	Mdu/u_mdu/m20_0_03_cZ/I1
4.829	0.555	tINS	RF	4	R46C57[3][A]	Mdu/u_mdu/m20_0_03_cZ/F
5.255	0.426	tNET	FF	1	R48C56[2][B]	Mdu/u_mdu/m32_2_03_0_0_cZ/I2
5.804	0.549	tINS	FR	2	R48C56[2][B]	Mdu/u_mdu/m32_2_03_0_0_cZ/F
5.980	0.176	tNET	RR	1	R48C57[2][B]	Mdu/u_mdu/m32_2_03_0_0_RNI74SI/I0
6.535	0.555	tINS	RF	2	R48C57[2][B]	Mdu/u_mdu/m32_2_03_0_0_RNI74SI/F
6.954	0.419	tNET	FF	1	R46C56[1][A]	Mdu/u_mdu/m64_4_03_0_0_cZ/I1
7.509	0.555	tINS	FF	1	R46C56[1][A]	Mdu/u_mdu/m64_4_03_0_0_cZ/F
8.241	0.733	tNET	FF	1	R46C51[3][B]	Mdu/u_mdu/m64_4_03_cZ/I2
8.796	0.555	tINS	FF	1	R46C51[3][B]	Mdu/u_mdu/m64_4_03_cZ/F
9.044	0.247	tNET	FF	1	R44C51[3][B]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[64]/I3
9.599	0.555	tINS	FF	1	R44C51[3][B]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[64]/F
10.254	0.656	tNET	FF	1	R44C52[0][B]	Mdu/u_mdu/reg0_nx_cZ[64]/I0
10.625	0.371	tINS	FF	1	R44C52[0][B]	Mdu/u_mdu/reg0_nx_cZ[64]/F
10.625	0.000	tNET	FF	1	R44C52[0][B]	Mdu/u_mdu/reg0_Z[64]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	496	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R44C52[0][B]	Mdu/u_mdu/reg0_Z[64]/CLK
11.683	-0.200	tUnc				Mdu/u_mdu/reg0_Z[64]
11.648	-0.035	tSu		1	R44C52[0][B]	Mdu/u_mdu/reg0_Z[64]

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	8
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 4.244, 48.545%; route: 4.266, 48.801%; tC2Q: 0.232, 2.654%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path16

Path Summary:

Slack	1.071
Data Arrival Time	10.577
Data Required Time	11.648
From	Mdu/u_mdu/div_shift_number_Z[0]
To	Mdu/u_mdu/reg0_Z[63]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.683	0.683	tINS	RR	496	IOT48[A]	clk_ibuf/O
1.883	1.201	tNET	RR	1	R42C57[1][A]	Mdu/u_mdu/div_shift_number_Z[0]/CLK
2.115	0.232	tC2Q	RF	113	R42C57[1][A]	Mdu/u_mdu/div_shift_number_Z[0]/Q
3.424	1.309	tNET	FF	1	R41C51[3][A]	Mdu/u_mdu/m55_0_03_1_cZ/I0
3.973	0.549	tINS	FR	1	R41C51[3][A]	Mdu/u_mdu/m55_0_03_1_cZ/F
3.975	0.001	tNET	RR	1	R41C51[3][B]	Mdu/u_mdu/m55_0_03_cZ/I1
4.428	0.453	tINS	RF	3	R41C51[3][B]	Mdu/u_mdu/m55_0_03_cZ/F
5.287	0.859	tNET	FF	1	R50C54[2][B]	Mdu/u_mdu/m63_2_03_0_0_cZ/I3
5.842	0.555	tINS	FF	1	R50C54[2][B]	Mdu/u_mdu/m63_2_03_0_0_cZ/F
6.497	0.656	tNET	FF	1	R46C54[2][A]	Mdu/u_mdu/m63_2_03_cZ/I1
7.014	0.517	tINS	FF	1	R46C54[2][A]	Mdu/u_mdu/m63_2_03_cZ/F
7.262	0.247	tNET	FF	1	R46C52[3][A]	Mdu/u_mdu/m63_4_03_1_0_cZ/I3
7.715	0.453	tINS	FF	1	R46C52[3][A]	Mdu/u_mdu/m63_4_03_1_0_cZ/F
8.399	0.684	tNET	FF	1	R38C49[2][A]	Mdu/u_mdu/reg0_exe_nx_m0_cZ[63]/I2
8.916	0.517	tINS	FF	1	R38C49[2][A]	Mdu/u_mdu/reg0_exe_nx_m0_cZ[63]/F
8.916	0.000	tNET	FF	1	R38C49[2][A]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[63]/I0
9.019	0.103	tINS	FF	1	R38C49[2][A]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[63]/O
10.028	1.009	tNET	FF	1	R44C53[2][A]	Mdu/u_mdu/reg0_nx_0[63]/I2
10.577	0.549	tINS	FR	1	R44C53[2][A]	Mdu/u_mdu/reg0_nx_0[63]/F
10.577	0.000	tNET	RR	1	R44C53[2][A]	Mdu/u_mdu/reg0_Z[63]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	496	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R44C53[2][A]	Mdu/u_mdu/reg0_Z[63]/CLK
11.683	-0.200	tUnc				Mdu/u_mdu/reg0_Z[63]
11.648	-0.035	tSu		1	R44C53[2][A]	Mdu/u_mdu/reg0_Z[63]

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	8
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 3.696, 42.513%; route: 4.766, 54.818%; tC2Q: 0.232, 2.669%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path17

Path Summary:

Slack	1.073
Data Arrival Time	10.575
Data Required Time	11.648
From	Mdu/u_mdu/div_shift_number_Z[0]
To	Mdu/u_mdu/reg0_fast_Z[28]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.683	0.683	tINS	RR	496	IOT48[A]	clk_ibuf/O
1.883	1.201	tNET	RR	1	R42C57[1][A]	Mdu/u_mdu/div_shift_number_Z[0]/CLK
2.115	0.232	tC2Q	RF	113	R42C57[1][A]	Mdu/u_mdu/div_shift_number_Z[0]/Q
3.700	1.585	tNET	FF	1	R46C54[3][B]	Mdu/u_mdu/m4_0_03_0_0_cZ/I0
4.217	0.517	tINS	FF	2	R46C54[3][B]	Mdu/u_mdu/m4_0_03_0_0_cZ/F
4.618	0.401	tNET	FF	1	R48C54[1][B]	Mdu/u_mdu/m4_0_03_0_0_RNI1JV1/I0
4.989	0.371	tINS	FF	3	R48C54[1][B]	Mdu/u_mdu/m4_0_03_0_0_RNI1JV1/F
5.169	0.179	tNET	FF	1	R48C55[1][A]	Mdu/u_mdu/m12_2_03_m1_e_1_cZ/I1
5.686	0.517	tINS	FF	2	R48C55[1][A]	Mdu/u_mdu/m12_2_03_m1_e_1_cZ/F
6.103	0.418	tNET	FF	1	R47C54[2][B]	Mdu/u_mdu/m12_2_03_m1_e_0_RNI7HT5/I1
6.620	0.517	tINS	FF	3	R47C54[2][B]	Mdu/u_mdu/m12_2_03_m1_e_0_RNI7HT5/F
7.047	0.427	tNET	FF	1	R46C55[0][A]	Mdu/u_mdu/m28_4_01_cZ/I1
7.617	0.570	tINS	FR	1	R46C55[0][A]	Mdu/u_mdu/m28_4_01_cZ/F
7.789	0.172	tNET	RR	1	R46C54[3][A]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[28]/I2
8.242	0.453	tINS	RF	1	R46C54[3][A]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[28]/F
8.760	0.518	tNET	FF	1	R40C54[2][A]	Mdu/u_mdu/reg0_exe_nx_cZ[28]/I3
9.315	0.555	tINS	FF	2	R40C54[2][A]	Mdu/u_mdu/reg0_exe_nx_cZ[28]/F
10.005	0.690	tNET	FF	1	R41C48[2][B]	Mdu/u_mdu/reg0_nx_fast_cZ[28]/I0
10.575	0.570	tINS	FR	1	R41C48[2][B]	Mdu/u_mdu/reg0_nx_fast_cZ[28]/F
10.575	0.000	tNET	RR	1	R41C48[2][B]	Mdu/u_mdu/reg0_fast_Z[28]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	496	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R41C48[2][B]	Mdu/u_mdu/reg0_fast_Z[28]/CLK
11.683	-0.200	tUnc				Mdu/u_mdu/reg0_fast_Z[28]
11.648	-0.035	tSu		1	R41C48[2][B]	Mdu/u_mdu/reg0_fast_Z[28]

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	8
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 4.070, 46.825%; route: 4.390, 50.506%; tC2Q: 0.232, 2.669%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path18

Path Summary:

Slack	1.073
Data Arrival Time	10.575
Data Required Time	11.648
From	Mdu/u_mdu/div_shift_number_Z[0]
To	Mdu/u_mdu/reg0_Z[28]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.683	0.683	tINS	RR	496	IOT48[A]	clk_ibuf/O
1.883	1.201	tNET	RR	1	R42C57[1][A]	Mdu/u_mdu/div_shift_number_Z[0]/CLK
2.115	0.232	tC2Q	RF	113	R42C57[1][A]	Mdu/u_mdu/div_shift_number_Z[0]/Q
3.700	1.585	tNET	FF	1	R46C54[3][B]	Mdu/u_mdu/m4_0_03_0_0_cZ/I0
4.217	0.517	tINS	FF	2	R46C54[3][B]	Mdu/u_mdu/m4_0_03_0_0_cZ/F
4.618	0.401	tNET	FF	1	R48C54[1][B]	Mdu/u_mdu/m4_0_03_0_0_RNI1JV1/I0
4.989	0.371	tINS	FF	3	R48C54[1][B]	Mdu/u_mdu/m4_0_03_0_0_RNI1JV1/F
5.169	0.179	tNET	FF	1	R48C55[1][A]	Mdu/u_mdu/m12_2_03_m1_e_1_cZ/I1
5.686	0.517	tINS	FF	2	R48C55[1][A]	Mdu/u_mdu/m12_2_03_m1_e_1_cZ/F
6.103	0.418	tNET	FF	1	R47C54[2][B]	Mdu/u_mdu/m12_2_03_m1_e_0_RNI7HT5/I1
6.620	0.517	tINS	FF	3	R47C54[2][B]	Mdu/u_mdu/m12_2_03_m1_e_0_RNI7HT5/F
7.047	0.427	tNET	FF	1	R46C55[0][A]	Mdu/u_mdu/m28_4_01_cZ/I1
7.617	0.570	tINS	FR	1	R46C55[0][A]	Mdu/u_mdu/m28_4_01_cZ/F
7.789	0.172	tNET	RR	1	R46C54[3][A]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[28]/I2
8.242	0.453	tINS	RF	1	R46C54[3][A]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[28]/F
8.760	0.518	tNET	FF	1	R40C54[2][A]	Mdu/u_mdu/reg0_exe_nx_cZ[28]/I3
9.315	0.555	tINS	FF	2	R40C54[2][A]	Mdu/u_mdu/reg0_exe_nx_cZ[28]/F
10.005	0.690	tNET	FF	1	R41C48[2][A]	Mdu/u_mdu/reg0_nx_cZ[28]/I0
10.575	0.570	tINS	FR	1	R41C48[2][A]	Mdu/u_mdu/reg0_nx_cZ[28]/F
10.575	0.000	tNET	RR	1	R41C48[2][A]	Mdu/u_mdu/reg0_Z[28]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	496	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R41C48[2][A]	Mdu/u_mdu/reg0_Z[28]/CLK
11.683	-0.200	tUnc				Mdu/u_mdu/reg0_Z[28]
11.648	-0.035	tSu		1	R41C48[2][A]	Mdu/u_mdu/reg0_Z[28]

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	8
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 4.070, 46.825%; route: 4.390, 50.506%; tC2Q: 0.232, 2.669%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path19

Path Summary:

Slack	1.167
Data Arrival Time	10.482
Data Required Time	11.648
From	Mdu/u_mdu/cnt_Z[1]
To	Mdu/u_mdu/reg0_Z[29]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.683	0.683	tINS	RR	496	IOT48[A]	clk_ibuf/O
1.883	1.201	tNET	RR	1	R43C58[2][A]	Mdu/u_mdu/cnt_Z[1]/CLK
2.115	0.232	tC2Q	RF	3	R43C58[2][A]	Mdu/u_mdu/cnt_Z[1]/Q
2.522	0.407	tNET	FF	1	R43C57[3][A]	Mdu/u_mdu/un1_cnt_1_0_a2_0_1_cZ_cZ/I0
3.039	0.517	tINS	FF	8	R43C57[3][A]	Mdu/u_mdu/un1_cnt_1_0_a2_0_1_cZ_cZ/F
4.151	1.112	tNET	FF	1	R40C46[3][B]	Mdu/u_mdu/reg0_exe_nx_m2s2/I2
4.668	0.517	tINS	FF	74	R40C46[3][B]	Mdu/u_mdu/reg0_exe_nx_m2s2/F
7.721	3.053	tNET	FF	1	R51C52[0][B]	Mdu/u_mdu/reg0_exe_nx_m2_d_cZ[29]/I2
8.291	0.570	tINS	FR	1	R51C52[0][B]	Mdu/u_mdu/reg0_exe_nx_m2_d_cZ[29]/F
8.293	0.001	tNET	RR	1	R51C52[1][A]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[29]/I0
8.848	0.555	tINS	RF	2	R51C52[1][A]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[29]/F
9.298	0.450	tNET	FF	1	R51C59[3][A]	Mdu/u_mdu/reg0_nx_sn_cZ[29]/I0
9.847	0.549	tINS	FR	1	R51C59[3][A]	Mdu/u_mdu/reg0_nx_sn_cZ[29]/F
10.020	0.172	tNET	RR	1	R51C58[0][A]	Mdu/u_mdu/reg0_nx_mb[29]/I0
10.482	0.462	tINS	RR	1	R51C58[0][A]	Mdu/u_mdu/reg0_nx_mb[29]/F
10.482	0.000	tNET	RR	1	R51C58[0][A]	Mdu/u_mdu/reg0_Z[29]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	496	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R51C58[0][A]	Mdu/u_mdu/reg0_Z[29]/CLK
11.683	-0.200	tUnc				Mdu/u_mdu/reg0_Z[29]
11.648	-0.035	tSu		1	R51C58[0][A]	Mdu/u_mdu/reg0_Z[29]

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	6
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 3.170, 36.867%; route: 5.196, 60.434%; tC2Q: 0.232, 2.698%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path20

Path Summary:

Slack	1.182
Data Arrival Time	10.466
Data Required Time	11.648
From	Mdu/u_mdu/reg1_Z[1]
To	Mdu/u_mdu/reg0_Z[32]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.683	0.683	tINS	RR	496	IOT48[A]	clk_ibuf/O
1.883	1.201	tNET	RR	1	R38C58[0][A]	Mdu/u_mdu/reg1_Z[1]/CLK
2.115	0.232	tC2Q	RF	8	R38C58[0][A]	Mdu/u_mdu/reg1_Z[1]/Q
3.340	1.224	tNET	FF	1	R34C51[1][A]	Mdu/u_mdu/adder_sum_s_1_sf_lofx_cZ/I1
3.793	0.453	tINS	FF	1	R34C51[1][A]	Mdu/u_mdu/adder_sum_s_1_sf_lofx_cZ/F
4.449	0.656	tNET	FF	2	R35C49[1][B]	Mdu/u_mdu/adder_sum_cry_1_0/I0
5.019	0.570	tINS	FR	1	R35C49[1][B]	Mdu/u_mdu/adder_sum_cry_1_0/COUT
5.019	0.000	tNET	RR	2	R35C49[2][A]	Mdu/u_mdu/adder_sum_cry_2_0/CIN
5.054	0.035	tINS	RF	1	R35C49[2][A]	Mdu/u_mdu/adder_sum_cry_2_0/COUT
5.054	0.000	tNET	FF	2	R35C49[2][B]	Mdu/u_mdu/adder_sum_cry_3_0/CIN
5.089	0.035	tINS	FF	1	R35C49[2][B]	Mdu/u_mdu/adder_sum_cry_3_0/COUT
5.089	0.000	tNET	FF	2	R35C50[0][A]	Mdu/u_mdu/adder_sum_cry_4_0/CIN
5.124	0.035	tINS	FF	1	R35C50[0][A]	Mdu/u_mdu/adder_sum_cry_4_0/COUT
5.124	0.000	tNET	FF	2	R35C50[0][B]	Mdu/u_mdu/adder_sum_cry_5_0/CIN
5.159	0.035	tINS	FF	1	R35C50[0][B]	Mdu/u_mdu/adder_sum_cry_5_0/COUT
5.159	0.000	tNET	FF	2	R35C50[1][A]	Mdu/u_mdu/adder_sum_cry_6_0/CIN
5.195	0.035	tINS	FF	1	R35C50[1][A]	Mdu/u_mdu/adder_sum_cry_6_0/COUT
5.195	0.000	tNET	FF	2	R35C50[1][B]	Mdu/u_mdu/adder_sum_cry_7_0/CIN
5.230	0.035	tINS	FF	1	R35C50[1][B]	Mdu/u_mdu/adder_sum_cry_7_0/COUT
5.230	0.000	tNET	FF	2	R35C50[2][A]	Mdu/u_mdu/adder_sum_cry_8_0/CIN
5.265	0.035	tINS	FF	1	R35C50[2][A]	Mdu/u_mdu/adder_sum_cry_8_0/COUT
5.265	0.000	tNET	FF	2	R35C50[2][B]	Mdu/u_mdu/adder_sum_cry_9_0/CIN
5.300	0.035	tINS	FF	1	R35C50[2][B]	Mdu/u_mdu/adder_sum_cry_9_0/COUT
5.300	0.000	tNET	FF	2	R35C51[0][A]	Mdu/u_mdu/adder_sum_cry_10_0/CIN
5.335	0.035	tINS	FF	1	R35C51[0][A]	Mdu/u_mdu/adder_sum_cry_10_0/COUT
5.335	0.000	tNET	FF	2	R35C51[0][B]	Mdu/u_mdu/adder_sum_cry_11_0/CIN
5.371	0.035	tINS	FF	1	R35C51[0][B]	Mdu/u_mdu/adder_sum_cry_11_0/COUT
5.371	0.000	tNET	FF	2	R35C51[1][A]	Mdu/u_mdu/adder_sum_cry_12_0/CIN
5.406	0.035	tINS	FF	1	R35C51[1][A]	Mdu/u_mdu/adder_sum_cry_12_0/COUT
5.406	0.000	tNET	FF	2	R35C51[1][B]	Mdu/u_mdu/adder_sum_cry_13_0/CIN
5.441	0.035	tINS	FF	1	R35C51[1][B]	Mdu/u_mdu/adder_sum_cry_13_0/COUT
5.441	0.000	tNET	FF	2	R35C51[2][A]	Mdu/u_mdu/adder_sum_cry_14_0/CIN
5.476	0.035	tINS	FF	1	R35C51[2][A]	Mdu/u_mdu/adder_sum_cry_14_0/COUT
5.476	0.000	tNET	FF	2	R35C51[2][B]	Mdu/u_mdu/adder_sum_cry_15_0/CIN
5.511	0.035	tINS	FF	1	R35C51[2][B]	Mdu/u_mdu/adder_sum_cry_15_0/COUT
5.511	0.000	tNET	FF	2	R35C52[0][A]	Mdu/u_mdu/adder_sum_cry_16_0/CIN
5.547	0.035	tINS	FF	1	R35C52[0][A]	Mdu/u_mdu/adder_sum_cry_16_0/COUT
5.547	0.000	tNET	FF	2	R35C52[0][B]	Mdu/u_mdu/adder_sum_cry_17_0/CIN
5.582	0.035	tINS	FF	1	R35C52[0][B]	Mdu/u_mdu/adder_sum_cry_17_0/COUT
5.582	0.000	tNET	FF	2	R35C52[1][A]	Mdu/u_mdu/adder_sum_cry_18_0/CIN
5.617	0.035	tINS	FF	1	R35C52[1][A]	Mdu/u_mdu/adder_sum_cry_18_0/COUT
5.617	0.000	tNET	FF	2	R35C52[1][B]	Mdu/u_mdu/adder_sum_cry_19_0/CIN
5.652	0.035	tINS	FF	1	R35C52[1][B]	Mdu/u_mdu/adder_sum_cry_19_0/COUT
5.652	0.000	tNET	FF	2	R35C52[2][A]	Mdu/u_mdu/adder_sum_cry_20_0/CIN
5.687	0.035	tINS	FF	1	R35C52[2][A]	Mdu/u_mdu/adder_sum_cry_20_0/COUT
5.687	0.000	tNET	FF	2	R35C52[2][B]	Mdu/u_mdu/adder_sum_cry_21_0/CIN
5.723	0.035	tINS	FF	1	R35C52[2][B]	Mdu/u_mdu/adder_sum_cry_21_0/COUT
5.723	0.000	tNET	FF	2	R35C53[0][A]	Mdu/u_mdu/adder_sum_cry_22_0/CIN
5.758	0.035	tINS	FF	1	R35C53[0][A]	Mdu/u_mdu/adder_sum_cry_22_0/COUT
5.758	0.000	tNET	FF	2	R35C53[0][B]	Mdu/u_mdu/adder_sum_cry_23_0/CIN
5.793	0.035	tINS	FF	1	R35C53[0][B]	Mdu/u_mdu/adder_sum_cry_23_0/COUT
5.793	0.000	tNET	FF	2	R35C53[1][A]	Mdu/u_mdu/adder_sum_cry_24_0/CIN
5.828	0.035	tINS	FF	1	R35C53[1][A]	Mdu/u_mdu/adder_sum_cry_24_0/COUT
5.828	0.000	tNET	FF	2	R35C53[1][B]	Mdu/u_mdu/adder_sum_cry_25_0/CIN
5.863	0.035	tINS	FF	1	R35C53[1][B]	Mdu/u_mdu/adder_sum_cry_25_0/COUT
5.863	0.000	tNET	FF	2	R35C53[2][A]	Mdu/u_mdu/adder_sum_cry_26_0/CIN
5.899	0.035	tINS	FF	1	R35C53[2][A]	Mdu/u_mdu/adder_sum_cry_26_0/COUT
5.899	0.000	tNET	FF	2	R35C53[2][B]	Mdu/u_mdu/adder_sum_cry_27_0/CIN
5.934	0.035	tINS	FF	1	R35C53[2][B]	Mdu/u_mdu/adder_sum_cry_27_0/COUT
5.934	0.000	tNET	FF	2	R35C54[0][A]	Mdu/u_mdu/adder_sum_cry_28_0/CIN
5.969	0.035	tINS	FF	1	R35C54[0][A]	Mdu/u_mdu/adder_sum_cry_28_0/COUT
5.969	0.000	tNET	FF	2	R35C54[0][B]	Mdu/u_mdu/adder_sum_cry_29_0/CIN
6.004	0.035	tINS	FF	1	R35C54[0][B]	Mdu/u_mdu/adder_sum_cry_29_0/COUT
6.004	0.000	tNET	FF	2	R35C54[1][A]	Mdu/u_mdu/adder_sum_cry_30_0/CIN
6.039	0.035	tINS	FF	1	R35C54[1][A]	Mdu/u_mdu/adder_sum_cry_30_0/COUT
6.039	0.000	tNET	FF	2	R35C54[1][B]	Mdu/u_mdu/adder_sum_cry_31_0/CIN
6.075	0.035	tINS	FF	1	R35C54[1][B]	Mdu/u_mdu/adder_sum_cry_31_0/COUT
6.075	0.000	tNET	FF	2	R35C54[2][A]	Mdu/u_mdu/adder_sum_s_32_0/CIN
6.545	0.470	tINS	FF	6	R35C54[2][A]	Mdu/u_mdu/adder_sum_s_32_0/SUM
7.003	0.459	tNET	FF	1	R35C46[0][A]	Mdu/u_mdu/reg0_exe_nx_ss0_cZ/I0
7.374	0.371	tINS	FF	50	R35C46[0][A]	Mdu/u_mdu/reg0_exe_nx_ss0_cZ/F
8.598	1.224	tNET	FF	1	R49C56[2][A]	Mdu/u_mdu/reg0_exe_nx_m1_cZ[32]/I3
9.051	0.453	tINS	FF	1	R49C56[2][A]	Mdu/u_mdu/reg0_exe_nx_m1_cZ[32]/F
9.541	0.490	tNET	FF	1	R51C58[3][A]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[32]/I1
10.003	0.462	tINS	FR	1	R51C58[3][A]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[32]/F
10.004	0.001	tNET	RR	1	R51C58[2][A]	Mdu/u_mdu/reg0_nx_cZ[32]/I0
10.466	0.462	tINS	RR	1	R51C58[2][A]	Mdu/u_mdu/reg0_nx_cZ[32]/F
10.466	0.000	tNET	RR	1	R51C58[2][A]	Mdu/u_mdu/reg0_Z[32]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	496	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R51C58[2][A]	Mdu/u_mdu/reg0_Z[32]/CLK
11.683	-0.200	tUnc				Mdu/u_mdu/reg0_Z[32]
11.648	-0.035	tSu		1	R51C58[2][A]	Mdu/u_mdu/reg0_Z[32]

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 4.297, 50.064%; route: 4.054, 47.233%; tC2Q: 0.232, 2.703%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path21

Path Summary:

Slack	1.201
Data Arrival Time	10.447
Data Required Time	11.648
From	Mdu/u_mdu/div_shift_number_Z[0]
To	Mdu/u_mdu/reg0_Z[47]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.683	0.683	tINS	RR	496	IOT48[A]	clk_ibuf/O
1.883	1.201	tNET	RR	1	R42C57[1][A]	Mdu/u_mdu/div_shift_number_Z[0]/CLK
2.115	0.232	tC2Q	RF	113	R42C57[1][A]	Mdu/u_mdu/div_shift_number_Z[0]/Q
3.724	1.609	tNET	FF	1	R51C56[1][B]	Mdu/u_mdu/m35_0_03_1_cZ/I0
4.273	0.549	tINS	FR	1	R51C56[1][B]	Mdu/u_mdu/m35_0_03_1_cZ/F
4.274	0.001	tNET	RR	1	R51C56[2][B]	Mdu/u_mdu/m35_0_03_cZ/I1
4.829	0.555	tINS	RF	4	R51C56[2][B]	Mdu/u_mdu/m35_0_03_cZ/F
5.251	0.422	tNET	FF	1	R52C54[2][B]	Mdu/u_mdu/m47_2_03_0_0_cZ/I2
5.800	0.549	tINS	FR	1	R52C54[2][B]	Mdu/u_mdu/m47_2_03_0_0_cZ/F
5.801	0.001	tNET	RR	1	R52C54[0][A]	Mdu/u_mdu/m47_2_03_0_0_RNIJI1P/I0
6.318	0.517	tINS	RF	2	R52C54[0][A]	Mdu/u_mdu/m47_2_03_0_0_RNIJI1P/F
7.444	1.125	tNET	FF	1	R46C49[1][B]	Mdu/u_mdu/m47_4_03_0_0_cZ/I3
7.961	0.517	tINS	FF	1	R46C49[1][B]	Mdu/u_mdu/m47_4_03_0_0_cZ/F
8.859	0.899	tNET	FF	1	R43C46[3][B]	Mdu/u_mdu/reg0_exe_nx_m1_cZ[47]/I1
9.376	0.517	tINS	FF	1	R43C46[3][B]	Mdu/u_mdu/reg0_exe_nx_m1_cZ[47]/F
9.376	0.000	tNET	FF	1	R43C46[3][A]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[47]/I1
9.479	0.103	tINS	FF	1	R43C46[3][A]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[47]/O
9.898	0.419	tNET	FF	1	R44C45[2][B]	Mdu/u_mdu/reg0_nx_cZ[47]/I0
10.447	0.549	tINS	FR	1	R44C45[2][B]	Mdu/u_mdu/reg0_nx_cZ[47]/F
10.447	0.000	tNET	RR	1	R44C45[2][B]	Mdu/u_mdu/reg0_Z[47]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	496	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R44C45[2][B]	Mdu/u_mdu/reg0_Z[47]/CLK
11.683	-0.200	tUnc				Mdu/u_mdu/reg0_Z[47]
11.648	-0.035	tSu		1	R44C45[2][B]	Mdu/u_mdu/reg0_Z[47]

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	8
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 3.856, 45.025%; route: 4.476, 52.266%; tC2Q: 0.232, 2.709%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path22

Path Summary:

Slack	1.212
Data Arrival Time	10.436
Data Required Time	11.648
From	Mdu/u_mdu/div_shift_number_Z[3]
To	Mdu/u_mdu/reg0_Z[49]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.683	0.683	tINS	RR	496	IOT48[A]	clk_ibuf/O
1.883	1.201	tNET	RR	1	R42C57[2][B]	Mdu/u_mdu/div_shift_number_Z[3]/CLK
2.115	0.232	tC2Q	RF	12	R42C57[2][B]	Mdu/u_mdu/div_shift_number_Z[3]/Q
2.552	0.437	tNET	FF	1	R43C55[1][A]	Mdu/u_mdu/div_shift_number_RNI5MR3_1[2]/I1
3.107	0.555	tINS	FF	57	R43C55[1][A]	Mdu/u_mdu/div_shift_number_RNI5MR3_1[2]/F
5.980	2.873	tNET	FF	1	R52C48[1][A]	Mdu/u_mdu/m49_2_03_1_cZ/I0
6.529	0.549	tINS	FR	1	R52C48[1][A]	Mdu/u_mdu/m49_2_03_1_cZ/F
6.673	0.144	tNET	RR	1	R52C48[1][B]	Mdu/u_mdu/m49_2_03_cZ/I1
7.190	0.517	tINS	RF	1	R52C48[1][B]	Mdu/u_mdu/m49_2_03_cZ/F
7.587	0.397	tNET	FF	1	R50C48[2][B]	Mdu/u_mdu/m49_4_03_1_0_cZ/I3
8.142	0.555	tINS	FF	1	R50C48[2][B]	Mdu/u_mdu/m49_4_03_1_0_cZ/F
9.247	1.105	tNET	FF	1	R34C48[3][B]	Mdu/u_mdu/reg0_exe_nx_m1_cZ[49]/I2
9.618	0.371	tINS	FF	1	R34C48[3][B]	Mdu/u_mdu/reg0_exe_nx_m1_cZ[49]/F
9.618	0.000	tNET	FF	1	R34C48[3][A]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[49]/I1
9.721	0.103	tINS	FF	1	R34C48[3][A]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[49]/O
9.974	0.253	tNET	FF	1	R34C47[0][A]	Mdu/u_mdu/reg0_nx_0[49]/I2
10.436	0.462	tINS	FR	1	R34C47[0][A]	Mdu/u_mdu/reg0_nx_0[49]/F
10.436	0.000	tNET	RR	1	R34C47[0][A]	Mdu/u_mdu/reg0_Z[49]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	496	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R34C47[0][A]	Mdu/u_mdu/reg0_Z[49]/CLK
11.683	-0.200	tUnc				Mdu/u_mdu/reg0_Z[49]
11.648	-0.035	tSu		1	R34C47[0][A]	Mdu/u_mdu/reg0_Z[49]

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 3.112, 36.386%; route: 5.209, 60.901%; tC2Q: 0.232, 2.713%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path23

Path Summary:

Slack	1.228
Data Arrival Time	10.420
Data Required Time	11.648
From	Mdu/u_mdu/reg0_fast_Z[5]
To	Mdu/u_mdu/reg0_1_rep1_Z
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.683	0.683	tINS	RR	496	IOT48[A]	clk_ibuf/O
1.883	1.201	tNET	RR	1	R48C48[1][B]	Mdu/u_mdu/reg0_fast_Z[5]/CLK
2.115	0.232	tC2Q	RF	8	R48C48[1][B]	Mdu/u_mdu/reg0_fast_Z[5]/Q
3.062	0.947	tNET	FF	1	R42C51[2][B]	Mdu/u_mdu/reg0_neg_axb_4_par_0_cp_cZ/I3
3.617	0.555	tINS	FF	1	R42C51[2][B]	Mdu/u_mdu/reg0_neg_axb_4_par_0_cp_cZ/F
4.273	0.656	tNET	FF	2	R39C52[1][B]	Mdu/u_mdu/reg0_neg_axb_4_par_cp_2/I0
4.843	0.570	tINS	FR	1	R39C52[1][B]	Mdu/u_mdu/reg0_neg_axb_4_par_cp_2/COUT
4.843	0.000	tNET	RR	2	R39C52[2][A]	Mdu/u_mdu/reg0_neg_axb_8_par_1/CIN
4.878	0.035	tINS	RF	1	R39C52[2][A]	Mdu/u_mdu/reg0_neg_axb_8_par_1/COUT
4.878	0.000	tNET	FF	2	R39C52[2][B]	Mdu/u_mdu/reg0_neg_axb_12_par_1/CIN
4.913	0.035	tINS	FF	1	R39C52[2][B]	Mdu/u_mdu/reg0_neg_axb_12_par_1/COUT
4.913	0.000	tNET	FF	2	R39C53[0][A]	Mdu/u_mdu/reg0_neg_axb_16_par_1/CIN
4.949	0.035	tINS	FF	1	R39C53[0][A]	Mdu/u_mdu/reg0_neg_axb_16_par_1/COUT
4.949	0.000	tNET	FF	2	R39C53[0][B]	Mdu/u_mdu/reg0_neg_cry_19_0/CIN
4.984	0.035	tINS	FF	1	R39C53[0][B]	Mdu/u_mdu/reg0_neg_cry_19_0/COUT
4.984	0.000	tNET	FF	2	R39C53[1][A]	Mdu/u_mdu/reg0_neg_cry_20_0/CIN
5.019	0.035	tINS	FF	1	R39C53[1][A]	Mdu/u_mdu/reg0_neg_cry_20_0/COUT
5.019	0.000	tNET	FF	2	R39C53[1][B]	Mdu/u_mdu/reg0_neg_cry_21_0/CIN
5.054	0.035	tINS	FF	1	R39C53[1][B]	Mdu/u_mdu/reg0_neg_cry_21_0/COUT
5.054	0.000	tNET	FF	2	R39C53[2][A]	Mdu/u_mdu/reg0_neg_cry_22_0/CIN
5.089	0.035	tINS	FF	1	R39C53[2][A]	Mdu/u_mdu/reg0_neg_cry_22_0/COUT
5.089	0.000	tNET	FF	2	R39C53[2][B]	Mdu/u_mdu/reg0_neg_cry_23_0/CIN
5.125	0.035	tINS	FF	1	R39C53[2][B]	Mdu/u_mdu/reg0_neg_cry_23_0/COUT
5.125	0.000	tNET	FF	2	R39C54[0][A]	Mdu/u_mdu/reg0_neg_cry_24_0/CIN
5.160	0.035	tINS	FF	1	R39C54[0][A]	Mdu/u_mdu/reg0_neg_cry_24_0/COUT
5.160	0.000	tNET	FF	2	R39C54[0][B]	Mdu/u_mdu/reg0_neg_cry_25_0/CIN
5.195	0.035	tINS	FF	1	R39C54[0][B]	Mdu/u_mdu/reg0_neg_cry_25_0/COUT
5.195	0.000	tNET	FF	2	R39C54[1][A]	Mdu/u_mdu/reg0_neg_cry_26_0/CIN
5.230	0.035	tINS	FF	1	R39C54[1][A]	Mdu/u_mdu/reg0_neg_cry_26_0/COUT
5.230	0.000	tNET	FF	2	R39C54[1][B]	Mdu/u_mdu/reg0_neg_cry_27_0/CIN
5.265	0.035	tINS	FF	1	R39C54[1][B]	Mdu/u_mdu/reg0_neg_cry_27_0/COUT
5.265	0.000	tNET	FF	2	R39C54[2][A]	Mdu/u_mdu/reg0_neg_cry_28_0/CIN
5.301	0.035	tINS	FF	1	R39C54[2][A]	Mdu/u_mdu/reg0_neg_cry_28_0/COUT
5.301	0.000	tNET	FF	2	R39C54[2][B]	Mdu/u_mdu/reg0_neg_cry_29_0/CIN
5.336	0.035	tINS	FF	1	R39C54[2][B]	Mdu/u_mdu/reg0_neg_cry_29_0/COUT
5.336	0.000	tNET	FF	2	R39C55[0][A]	Mdu/u_mdu/reg0_neg_cry_30_0/CIN
5.371	0.035	tINS	FF	1	R39C55[0][A]	Mdu/u_mdu/reg0_neg_cry_30_0/COUT
5.371	0.000	tNET	FF	2	R39C55[0][B]	Mdu/u_mdu/reg0_neg_cry_31_0/CIN
5.406	0.035	tINS	FF	1	R39C55[0][B]	Mdu/u_mdu/reg0_neg_cry_31_0/COUT
5.406	0.000	tNET	FF	2	R39C55[1][A]	Mdu/u_mdu/reg0_neg_cry_32_0/CIN
5.441	0.035	tINS	FF	1	R39C55[1][A]	Mdu/u_mdu/reg0_neg_cry_32_0/COUT
5.441	0.000	tNET	FF	2	R39C55[1][B]	Mdu/u_mdu/reg0_neg_s_33_0/CIN
5.911	0.470	tINS	FF	1	R39C55[1][B]	Mdu/u_mdu/reg0_neg_s_33_0/SUM
6.866	0.955	tNET	FF	1	R34C49[3][A]	Mdu/u_mdu/reg0_post_swap_2[1]/I1
7.421	0.555	tINS	FF	1	R34C49[3][A]	Mdu/u_mdu/reg0_post_swap_2[1]/F
7.421	0.000	tNET	FF	1	R34C49[3][A]	Mdu/u_mdu/reg0_post_swap_4[1]/I0
7.524	0.103	tINS	FF	1	R34C49[3][A]	Mdu/u_mdu/reg0_post_swap_4[1]/O
8.186	0.662	tNET	FF	1	R38C49[3][A]	Mdu/u_mdu/reg0_post_swap_5[1]/I1
8.741	0.555	tINS	FF	4	R38C49[3][A]	Mdu/u_mdu/reg0_post_swap_5[1]/F
9.850	1.109	tNET	FF	1	R44C54[0][A]	Mdu/u_mdu/reg0_nx_rep1_cZ[1]/I1
10.420	0.570	tINS	FR	1	R44C54[0][A]	Mdu/u_mdu/reg0_nx_rep1_cZ[1]/F
10.420	0.000	tNET	RR	1	R44C54[0][A]	Mdu/u_mdu/reg0_1_rep1_Z/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	496	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R44C54[0][A]	Mdu/u_mdu/reg0_1_rep1_Z/CLK
11.683	-0.200	tUnc				Mdu/u_mdu/reg0_1_rep1_Z
11.648	-0.035	tSu		1	R44C54[0][A]	Mdu/u_mdu/reg0_1_rep1_Z

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 3.976, 46.578%; route: 4.329, 50.704%; tC2Q: 0.232, 2.718%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path24

Path Summary:

Slack	1.234
Data Arrival Time	10.414
Data Required Time	11.648
From	Mdu/u_mdu/cnt_Z[1]
To	Mdu/u_mdu/reg0_26_rep1_Z
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.683	0.683	tINS	RR	496	IOT48[A]	clk_ibuf/O
1.883	1.201	tNET	RR	1	R43C58[2][A]	Mdu/u_mdu/cnt_Z[1]/CLK
2.115	0.232	tC2Q	RF	3	R43C58[2][A]	Mdu/u_mdu/cnt_Z[1]/Q
2.522	0.407	tNET	FF	1	R43C57[3][A]	Mdu/u_mdu/un1_cnt_1_0_a2_0_1_cZ_cZ/I0
3.039	0.517	tINS	FF	8	R43C57[3][A]	Mdu/u_mdu/un1_cnt_1_0_a2_0_1_cZ_cZ/F
4.151	1.112	tNET	FF	1	R40C46[3][B]	Mdu/u_mdu/reg0_exe_nx_m2s2/I2
4.668	0.517	tINS	FF	74	R40C46[3][B]	Mdu/u_mdu/reg0_exe_nx_m2s2/F
7.177	2.509	tNET	FF	1	R47C59[0][A]	Mdu/u_mdu/reg0_exe_nx_m2_d_cZ[26]/I2
7.639	0.462	tINS	FR	1	R47C59[0][A]	Mdu/u_mdu/reg0_exe_nx_m2_d_cZ[26]/F
7.640	0.001	tNET	RR	1	R47C59[1][A]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[26]/I0
8.011	0.371	tINS	RF	1	R47C59[1][A]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[26]/F
8.966	0.955	tNET	FF	1	R41C54[3][A]	Mdu/u_mdu/reg0_exe_nx_cZ[26]/I3
9.337	0.371	tINS	FF	3	R41C54[3][A]	Mdu/u_mdu/reg0_exe_nx_cZ[26]/F
9.865	0.528	tNET	FF	1	R51C54[0][A]	Mdu/u_mdu/reg0_nx_rep1_cZ[26]/I0
10.414	0.549	tINS	FR	1	R51C54[0][A]	Mdu/u_mdu/reg0_nx_rep1_cZ[26]/F
10.414	0.000	tNET	RR	1	R51C54[0][A]	Mdu/u_mdu/reg0_26_rep1_Z/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	496	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R51C54[0][A]	Mdu/u_mdu/reg0_26_rep1_Z/CLK
11.683	-0.200	tUnc				Mdu/u_mdu/reg0_26_rep1_Z
11.648	-0.035	tSu		1	R51C54[0][A]	Mdu/u_mdu/reg0_26_rep1_Z

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	6
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 2.787, 32.668%; route: 5.512, 64.613%; tC2Q: 0.232, 2.719%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path25

Path Summary:

Slack	1.234
Data Arrival Time	10.414
Data Required Time	11.648
From	Mdu/u_mdu/cnt_Z[1]
To	Mdu/u_mdu/reg0_fast_Z[26]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.683	0.683	tINS	RR	496	IOT48[A]	clk_ibuf/O
1.883	1.201	tNET	RR	1	R43C58[2][A]	Mdu/u_mdu/cnt_Z[1]/CLK
2.115	0.232	tC2Q	RF	3	R43C58[2][A]	Mdu/u_mdu/cnt_Z[1]/Q
2.522	0.407	tNET	FF	1	R43C57[3][A]	Mdu/u_mdu/un1_cnt_1_0_a2_0_1_cZ_cZ/I0
3.039	0.517	tINS	FF	8	R43C57[3][A]	Mdu/u_mdu/un1_cnt_1_0_a2_0_1_cZ_cZ/F
4.151	1.112	tNET	FF	1	R40C46[3][B]	Mdu/u_mdu/reg0_exe_nx_m2s2/I2
4.668	0.517	tINS	FF	74	R40C46[3][B]	Mdu/u_mdu/reg0_exe_nx_m2s2/F
7.177	2.509	tNET	FF	1	R47C59[0][A]	Mdu/u_mdu/reg0_exe_nx_m2_d_cZ[26]/I2
7.639	0.462	tINS	FR	1	R47C59[0][A]	Mdu/u_mdu/reg0_exe_nx_m2_d_cZ[26]/F
7.640	0.001	tNET	RR	1	R47C59[1][A]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[26]/I0
8.011	0.371	tINS	RF	1	R47C59[1][A]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[26]/F
8.966	0.955	tNET	FF	1	R41C54[3][A]	Mdu/u_mdu/reg0_exe_nx_cZ[26]/I3
9.337	0.371	tINS	FF	3	R41C54[3][A]	Mdu/u_mdu/reg0_exe_nx_cZ[26]/F
9.865	0.528	tNET	FF	1	R51C54[0][B]	Mdu/u_mdu/reg0_nx_fast_cZ[26]/I0
10.414	0.549	tINS	FR	1	R51C54[0][B]	Mdu/u_mdu/reg0_nx_fast_cZ[26]/F
10.414	0.000	tNET	RR	1	R51C54[0][B]	Mdu/u_mdu/reg0_fast_Z[26]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	496	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R51C54[0][B]	Mdu/u_mdu/reg0_fast_Z[26]/CLK
11.683	-0.200	tUnc				Mdu/u_mdu/reg0_fast_Z[26]
11.648	-0.035	tSu		1	R51C54[0][B]	Mdu/u_mdu/reg0_fast_Z[26]

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	6
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 2.787, 32.668%; route: 5.512, 64.613%; tC2Q: 0.232, 2.719%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Hold Analysis Report

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	0.213
Data Arrival Time	2.040
Data Required Time	1.826
From	u_la0_top/u_ao_mem_ctrl/data_reg_Z[45]
To	u_la0_top/u_ao_mem_ctrl/mem_mem_0_22
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	496	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R11C13[0][A]	u_la0_top/u_ao_mem_ctrl/data_reg_Z[45]/CLK
1.779	0.202	tC2Q	RR	1	R11C13[0][A]	u_la0_top/u_ao_mem_ctrl/data_reg_Z[45]/Q
2.040	0.260	tNET	RR	1	BSRAM_R10[2]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_22/DI1

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	496	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	BSRAM_R10[2]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_22/CLKA
1.577	0.000	tUnc				u_la0_top/u_ao_mem_ctrl/mem_mem_0_22
1.826	0.249	tHld		1	BSRAM_R10[2]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_22

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.260, 56.314%; tC2Q: 0.202, 43.686%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path2

Path Summary:

Slack	0.213
Data Arrival Time	2.040
Data Required Time	1.826
From	u_la0_top/u_ao_mem_ctrl/data_reg_Z[44]
To	u_la0_top/u_ao_mem_ctrl/mem_mem_0_22
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	496	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R12C10[2][B]	u_la0_top/u_ao_mem_ctrl/data_reg_Z[44]/CLK
1.779	0.202	tC2Q	RR	1	R12C10[2][B]	u_la0_top/u_ao_mem_ctrl/data_reg_Z[44]/Q
2.040	0.260	tNET	RR	1	BSRAM_R10[2]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_22/DI0

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	496	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	BSRAM_R10[2]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_22/CLKA
1.577	0.000	tUnc				u_la0_top/u_ao_mem_ctrl/mem_mem_0_22
1.826	0.249	tHld		1	BSRAM_R10[2]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_22

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.260, 56.314%; tC2Q: 0.202, 43.686%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path3

Path Summary:

Slack	0.213
Data Arrival Time	2.040
Data Required Time	1.826
From	u_la0_top/u_ao_mem_ctrl/data_reg_Z[34]
To	u_la0_top/u_ao_mem_ctrl/mem_mem_0_17
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	496	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R9C10[0][A]	u_la0_top/u_ao_mem_ctrl/data_reg_Z[34]/CLK
1.779	0.202	tC2Q	RR	1	R9C10[0][A]	u_la0_top/u_ao_mem_ctrl/data_reg_Z[34]/Q
2.040	0.260	tNET	RR	1	BSRAM_R10[1]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_17/DI0

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	496	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	BSRAM_R10[1]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_17/CLKA
1.577	0.000	tUnc				u_la0_top/u_ao_mem_ctrl/mem_mem_0_17
1.826	0.249	tHld		1	BSRAM_R10[1]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_17

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.260, 56.314%; tC2Q: 0.202, 43.686%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path4

Path Summary:

Slack	0.215
Data Arrival Time	1.910
Data Required Time	1.695
From	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[2]
To	u_la0_top/u_ao_mem_ctrl/mem_mem_0_17
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	496	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R9C9[1][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[2]/CLK
1.779	0.202	tC2Q	RR	51	R9C9[1][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[2]/Q
1.910	0.131	tNET	RR	1	BSRAM_R10[1]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_17/ADA3

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	496	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	BSRAM_R10[1]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_17/CLKA
1.577	0.000	tUnc				u_la0_top/u_ao_mem_ctrl/mem_mem_0_17
1.695	0.118	tHld		1	BSRAM_R10[1]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_17

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.131, 39.258%; tC2Q: 0.202, 60.742%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path5

Path Summary:

Slack	0.225
Data Arrival Time	2.052
Data Required Time	1.826
From	u_la0_top/u_ao_mem_ctrl/data_reg_Z[12]
To	u_la0_top/u_ao_mem_ctrl/mem_mem_0_6
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	496	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R18C19[1][B]	u_la0_top/u_ao_mem_ctrl/data_reg_Z[12]/CLK
1.779	0.202	tC2Q	RR	1	R18C19[1][B]	u_la0_top/u_ao_mem_ctrl/data_reg_Z[12]/Q
2.052	0.272	tNET	RR	1	BSRAM_R10[5]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_6/DI0

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	496	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	BSRAM_R10[5]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_6/CLKA
1.577	0.000	tUnc				u_la0_top/u_ao_mem_ctrl/mem_mem_0_6
1.826	0.249	tHld		1	BSRAM_R10[5]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_6

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.272, 57.427%; tC2Q: 0.202, 42.573%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path6

Path Summary:

Slack	0.337
Data Arrival Time	2.032
Data Required Time	1.695
From	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[4]
To	u_la0_top/u_ao_mem_ctrl/mem_mem_0_17
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	496	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R12C7[2][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[4]/CLK
1.779	0.202	tC2Q	RR	51	R12C7[2][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[4]/Q
2.032	0.253	tNET	RR	1	BSRAM_R10[1]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_17/ADA5

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	496	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	BSRAM_R10[1]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_17/CLKA
1.577	0.000	tUnc				u_la0_top/u_ao_mem_ctrl/mem_mem_0_17
1.695	0.118	tHld		1	BSRAM_R10[1]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_17

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.253, 55.561%; tC2Q: 0.202, 44.439%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path7

Path Summary:

Slack	0.351
Data Arrival Time	2.178
Data Required Time	1.826
From	u_la0_top/u_ao_mem_ctrl/data_reg_Z[13]
To	u_la0_top/u_ao_mem_ctrl/mem_mem_0_6
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	496	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R18C19[2][A]	u_la0_top/u_ao_mem_ctrl/data_reg_Z[13]/CLK
1.779	0.202	tC2Q	RR	1	R18C19[2][A]	u_la0_top/u_ao_mem_ctrl/data_reg_Z[13]/Q
2.178	0.398	tNET	RR	1	BSRAM_R10[5]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_6/DI1

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	496	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	BSRAM_R10[5]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_6/CLKA
1.577	0.000	tUnc				u_la0_top/u_ao_mem_ctrl/mem_mem_0_6
1.826	0.249	tHld		1	BSRAM_R10[5]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_6

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.398, 66.358%; tC2Q: 0.202, 33.642%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path8

Path Summary:

Slack	0.352
Data Arrival Time	2.047
Data Required Time	1.695
From	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8]
To	u_la0_top/u_ao_mem_ctrl/mem_mem_0_17
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	496	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R11C6[2][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8]/CLK
1.779	0.202	tC2Q	RR	51	R11C6[2][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8]/Q
2.047	0.268	tNET	RR	1	BSRAM_R10[1]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_17/ADA9

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	496	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	BSRAM_R10[1]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_17/CLKA
1.577	0.000	tUnc				u_la0_top/u_ao_mem_ctrl/mem_mem_0_17
1.695	0.118	tHld		1	BSRAM_R10[1]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_17

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.268, 56.986%; tC2Q: 0.202, 43.014%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path9

Path Summary:

Slack	0.352
Data Arrival Time	2.047
Data Required Time	1.695
From	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8]
To	u_la0_top/u_ao_mem_ctrl/mem_mem_0_12
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	496	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R11C6[2][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8]/CLK
1.779	0.202	tC2Q	RR	51	R11C6[2][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8]/Q
2.047	0.268	tNET	RR	1	BSRAM_R10[0]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_12/ADA9

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	496	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	BSRAM_R10[0]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_12/CLKA
1.577	0.000	tUnc				u_la0_top/u_ao_mem_ctrl/mem_mem_0_12
1.695	0.118	tHld		1	BSRAM_R10[0]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_12

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.268, 56.986%; tC2Q: 0.202, 43.014%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path10

Path Summary:

Slack	0.352
Data Arrival Time	2.047
Data Required Time	1.695
From	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[11]
To	u_la0_top/u_ao_mem_ctrl/mem_mem_0_17
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	496	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R9C7[1][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[11]/CLK
1.779	0.202	tC2Q	RR	51	R9C7[1][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[11]/Q
2.047	0.268	tNET	RR	1	BSRAM_R10[1]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_17/ADA12

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	496	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	BSRAM_R10[1]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_17/CLKA
1.577	0.000	tUnc				u_la0_top/u_ao_mem_ctrl/mem_mem_0_17
1.695	0.118	tHld		1	BSRAM_R10[1]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_17

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.268, 56.991%; tC2Q: 0.202, 43.009%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path11

Path Summary:

Slack	0.353
Data Arrival Time	2.048
Data Required Time	1.695
From	cnt_1_Z[0]
To	memr_memr_0_7
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	496	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R39C40[2][B]	cnt_1_Z[0]/CLK
1.779	0.202	tC2Q	RR	17	R39C40[2][B]	cnt_1_Z[0]/Q
2.048	0.269	tNET	RR	1	BSRAM_R36[11]	memr_memr_0_7/ADB1

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	496	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	BSRAM_R36[11]	memr_memr_0_7/CLKB
1.577	0.000	tUnc				memr_memr_0_7
1.695	0.118	tHld		1	BSRAM_R36[11]	memr_memr_0_7

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.269, 57.092%; tC2Q: 0.202, 42.908%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path12

Path Summary:

Slack	0.353
Data Arrival Time	2.048
Data Required Time	1.695
From	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[12]
To	u_la0_top/u_ao_mem_ctrl/mem_mem_0_17
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	496	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R9C7[1][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[12]/CLK
1.779	0.202	tC2Q	RR	51	R9C7[1][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[12]/Q
2.048	0.269	tNET	RR	1	BSRAM_R10[1]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_17/ADA13

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	496	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	BSRAM_R10[1]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_17/CLKA
1.577	0.000	tUnc				u_la0_top/u_ao_mem_ctrl/mem_mem_0_17
1.695	0.118	tHld		1	BSRAM_R10[1]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_17

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.269, 57.102%; tC2Q: 0.202, 42.898%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path13

Path Summary:

Slack	0.353
Data Arrival Time	2.048
Data Required Time	1.695
From	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[12]
To	u_la0_top/u_ao_mem_ctrl/mem_mem_0_12
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	496	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R9C7[1][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[12]/CLK
1.779	0.202	tC2Q	RR	51	R9C7[1][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[12]/Q
2.048	0.269	tNET	RR	1	BSRAM_R10[0]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_12/ADA13

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	496	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	BSRAM_R10[0]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_12/CLKA
1.577	0.000	tUnc				u_la0_top/u_ao_mem_ctrl/mem_mem_0_12
1.695	0.118	tHld		1	BSRAM_R10[0]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_12

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.269, 57.102%; tC2Q: 0.202, 42.898%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path14

Path Summary:

Slack	0.353
Data Arrival Time	2.048
Data Required Time	1.695
From	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[4]
To	u_la0_top/u_ao_mem_ctrl/mem_mem_0_12
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	496	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R12C7[2][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[4]/CLK
1.779	0.202	tC2Q	RR	51	R12C7[2][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[4]/Q
2.048	0.269	tNET	RR	1	BSRAM_R10[0]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_12/ADA5

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	496	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	BSRAM_R10[0]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_12/CLKA
1.577	0.000	tUnc				u_la0_top/u_ao_mem_ctrl/mem_mem_0_12
1.695	0.118	tHld		1	BSRAM_R10[0]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_12

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.269, 57.102%; tC2Q: 0.202, 42.898%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path15

Path Summary:

Slack	0.353
Data Arrival Time	2.048
Data Required Time	1.695
From	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[6]
To	u_la0_top/u_ao_mem_ctrl/mem_mem_0_22
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	496	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R8C10[1][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[6]/CLK
1.779	0.202	tC2Q	RR	51	R8C10[1][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[6]/Q
2.048	0.269	tNET	RR	1	BSRAM_R10[2]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_22/ADA7

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	496	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	BSRAM_R10[2]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_22/CLKA
1.577	0.000	tUnc				u_la0_top/u_ao_mem_ctrl/mem_mem_0_22
1.695	0.118	tHld		1	BSRAM_R10[2]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_22

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.269, 57.107%; tC2Q: 0.202, 42.893%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path16

Path Summary:

Slack	0.354
Data Arrival Time	2.049
Data Required Time	1.695
From	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[11]
To	u_la0_top/u_ao_mem_ctrl/mem_mem_0_12
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	496	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R9C7[1][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[11]/CLK
1.779	0.202	tC2Q	RR	51	R9C7[1][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[11]/Q
2.049	0.270	tNET	RR	1	BSRAM_R10[0]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_12/ADA12

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	496	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	BSRAM_R10[0]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_12/CLKA
1.577	0.000	tUnc				u_la0_top/u_ao_mem_ctrl/mem_mem_0_12
1.695	0.118	tHld		1	BSRAM_R10[0]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_12

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.270, 57.203%; tC2Q: 0.202, 42.797%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path17

Path Summary:

Slack	0.354
Data Arrival Time	2.049
Data Required Time	1.695
From	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[5]
To	u_la0_top/u_ao_mem_ctrl/mem_mem_0_22
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	496	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R9C9[1][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[5]/CLK
1.779	0.202	tC2Q	RR	51	R9C9[1][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[5]/Q
2.049	0.270	tNET	RR	1	BSRAM_R10[2]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_22/ADA6

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	496	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	BSRAM_R10[2]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_22/CLKA
1.577	0.000	tUnc				u_la0_top/u_ao_mem_ctrl/mem_mem_0_22
1.695	0.118	tHld		1	BSRAM_R10[2]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_22

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.270, 57.208%; tC2Q: 0.202, 42.792%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path18

Path Summary:

Slack	0.354
Data Arrival Time	2.049
Data Required Time	1.695
From	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[5]
To	u_la0_top/u_ao_mem_ctrl/mem_mem_0_17
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	496	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R9C9[1][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[5]/CLK
1.779	0.202	tC2Q	RR	51	R9C9[1][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[5]/Q
2.049	0.270	tNET	RR	1	BSRAM_R10[1]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_17/ADA6

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	496	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	BSRAM_R10[1]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_17/CLKA
1.577	0.000	tUnc				u_la0_top/u_ao_mem_ctrl/mem_mem_0_17
1.695	0.118	tHld		1	BSRAM_R10[1]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_17

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.270, 57.208%; tC2Q: 0.202, 42.792%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path19

Path Summary:

Slack	0.355
Data Arrival Time	2.051
Data Required Time	1.695
From	cnt_1_Z[12]
To	memr_memr_0_10
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	496	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R39C42[2][B]	cnt_1_Z[12]/CLK
1.779	0.202	tC2Q	RR	17	R39C42[2][B]	cnt_1_Z[12]/Q
2.051	0.271	tNET	RR	1	BSRAM_R36[12]	memr_memr_0_10/ADB13

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	496	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	BSRAM_R36[12]	memr_memr_0_10/CLKB
1.577	0.000	tUnc				memr_memr_0_10
1.695	0.118	tHld		1	BSRAM_R36[12]	memr_memr_0_10

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.271, 57.304%; tC2Q: 0.202, 42.696%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path20

Path Summary:

Slack	0.358
Data Arrival Time	2.053
Data Required Time	1.695
From	cnt_1_Z[6]
To	memr_memr_0_10
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	496	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R39C41[2][B]	cnt_1_Z[6]/CLK
1.779	0.202	tC2Q	RR	17	R39C41[2][B]	cnt_1_Z[6]/Q
2.053	0.274	tNET	RR	1	BSRAM_R36[12]	memr_memr_0_10/ADB7

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	496	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	BSRAM_R36[12]	memr_memr_0_10/CLKB
1.577	0.000	tUnc				memr_memr_0_10
1.695	0.118	tHld		1	BSRAM_R36[12]	memr_memr_0_10

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.274, 57.533%; tC2Q: 0.202, 42.467%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path21

Path Summary:

Slack	0.359
Data Arrival Time	2.054
Data Required Time	1.695
From	cnt_1_Z[11]
To	memr_memr_0_11
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	496	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R39C42[2][A]	cnt_1_Z[11]/CLK
1.779	0.202	tC2Q	RR	17	R39C42[2][A]	cnt_1_Z[11]/Q
2.054	0.275	tNET	RR	1	BSRAM_R45[13]	memr_memr_0_11/ADB12

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	496	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	BSRAM_R45[13]	memr_memr_0_11/CLKB
1.577	0.000	tUnc				memr_memr_0_11
1.695	0.118	tHld		1	BSRAM_R45[13]	memr_memr_0_11

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.275, 57.645%; tC2Q: 0.202, 42.355%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path22

Path Summary:

Slack	0.361
Data Arrival Time	2.057
Data Required Time	1.695
From	cnt_1_Z[12]
To	memr_memr_0_11
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	496	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R39C42[2][B]	cnt_1_Z[12]/CLK
1.779	0.202	tC2Q	RR	17	R39C42[2][B]	cnt_1_Z[12]/Q
2.057	0.277	tNET	RR	1	BSRAM_R45[13]	memr_memr_0_11/ADB13

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	496	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	BSRAM_R45[13]	memr_memr_0_11/CLKB
1.577	0.000	tUnc				memr_memr_0_11
1.695	0.118	tHld		1	BSRAM_R45[13]	memr_memr_0_11

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.277, 57.861%; tC2Q: 0.202, 42.139%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path23

Path Summary:

Slack	0.363
Data Arrival Time	2.189
Data Required Time	1.826
From	u_la0_top/u_ao_mem_ctrl/data_reg_Z[55]
To	u_la0_top/u_ao_mem_ctrl/mem_mem_0_27
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	496	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R9C9[0][A]	u_la0_top/u_ao_mem_ctrl/data_reg_Z[55]/CLK
1.779	0.202	tC2Q	RR	1	R9C9[0][A]	u_la0_top/u_ao_mem_ctrl/data_reg_Z[55]/Q
2.189	0.410	tNET	RR	1	BSRAM_R10[3]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_27/DI1

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	496	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	BSRAM_R10[3]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_27/CLKA
1.577	0.000	tUnc				u_la0_top/u_ao_mem_ctrl/mem_mem_0_27
1.826	0.249	tHld		1	BSRAM_R10[3]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_27

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.410, 66.974%; tC2Q: 0.202, 33.026%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path24

Path Summary:

Slack	0.364
Data Arrival Time	2.059
Data Required Time	1.695
From	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8]
To	u_la0_top/u_ao_mem_ctrl/mem_mem_0_27
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	496	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R11C6[2][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8]/CLK
1.779	0.202	tC2Q	RR	51	R11C6[2][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8]/Q
2.059	0.280	tNET	RR	1	BSRAM_R10[3]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_27/ADA9

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	496	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	BSRAM_R10[3]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_27/CLKA
1.577	0.000	tUnc				u_la0_top/u_ao_mem_ctrl/mem_mem_0_27
1.695	0.118	tHld		1	BSRAM_R10[3]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_27

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.280, 58.058%; tC2Q: 0.202, 41.942%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path25

Path Summary:

Slack	0.373
Data Arrival Time	2.068
Data Required Time	1.695
From	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[4]
To	u_la0_top/u_ao_mem_ctrl/mem_mem_0_27
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	496	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R12C7[2][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[4]/CLK
1.779	0.202	tC2Q	RR	51	R12C7[2][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[4]/Q
2.068	0.289	tNET	RR	1	BSRAM_R10[3]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_27/ADA5

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	496	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	BSRAM_R10[3]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_27/CLKA
1.577	0.000	tUnc				u_la0_top/u_ao_mem_ctrl/mem_mem_0_27
1.695	0.118	tHld		1	BSRAM_R10[3]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_27

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.289, 58.845%; tC2Q: 0.202, 41.155%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Recovery Analysis Report

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	1.748
Data Arrival Time	9.900
Data Required Time	11.648
From	u_la0_top/rst_ao_Z
To	u_la0_top/triger_level_cnt_Z[0]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.688	0.688	tINS	FF	496	IOT48[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R7C10[2][B]	u_la0_top/rst_ao_Z/CLK
7.148	0.232	tC2Q	FF	49	R7C10[2][B]	u_la0_top/rst_ao_Z/Q
9.900	2.752	tNET	FF	1	R8C11[2][A]	u_la0_top/triger_level_cnt_Z[0]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	496	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R8C11[2][A]	u_la0_top/triger_level_cnt_Z[0]/CLK
11.683	-0.200	tUnc				u_la0_top/triger_level_cnt_Z[0]
11.648	-0.035	tSu		1	R8C11[2][A]	u_la0_top/triger_level_cnt_Z[0]

Path Statistics:

Clock Skew	-0.033
Setup Relationship	5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.752, 92.227%; tC2Q: 0.232, 7.773%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path2

Path Summary:

Slack	1.748
Data Arrival Time	9.900
Data Required Time	11.648
From	u_la0_top/rst_ao_Z
To	u_la0_top/triger_level_cnt_Z[2]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.688	0.688	tINS	FF	496	IOT48[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R7C10[2][B]	u_la0_top/rst_ao_Z/CLK
7.148	0.232	tC2Q	FF	49	R7C10[2][B]	u_la0_top/rst_ao_Z/Q
9.900	2.752	tNET	FF	1	R12C7[0][A]	u_la0_top/triger_level_cnt_Z[2]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	496	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R12C7[0][A]	u_la0_top/triger_level_cnt_Z[2]/CLK
11.683	-0.200	tUnc				u_la0_top/triger_level_cnt_Z[2]
11.648	-0.035	tSu		1	R12C7[0][A]	u_la0_top/triger_level_cnt_Z[2]

Path Statistics:

Clock Skew	-0.033
Setup Relationship	5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.752, 92.227%; tC2Q: 0.232, 7.773%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path3

Path Summary:

Slack	1.748
Data Arrival Time	9.900
Data Required Time	11.648
From	u_la0_top/rst_ao_Z
To	u_la0_top/capture_window_sel[3]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.688	0.688	tINS	FF	496	IOT48[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R7C10[2][B]	u_la0_top/rst_ao_Z/CLK
7.148	0.232	tC2Q	FF	49	R7C10[2][B]	u_la0_top/rst_ao_Z/Q
9.900	2.752	tNET	FF	1	R12C6[2][B]	u_la0_top/capture_window_sel[3]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	496	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R12C6[2][B]	u_la0_top/capture_window_sel[3]/CLK
11.683	-0.200	tUnc				u_la0_top/capture_window_sel[3]
11.648	-0.035	tSu		1	R12C6[2][B]	u_la0_top/capture_window_sel[3]

Path Statistics:

Clock Skew	-0.033
Setup Relationship	5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.752, 92.227%; tC2Q: 0.232, 7.773%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path4

Path Summary:

Slack	1.748
Data Arrival Time	9.900
Data Required Time	11.648
From	u_la0_top/rst_ao_Z
To	u_la0_top/internal_reg_force_triger_syn_Z[0]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.688	0.688	tINS	FF	496	IOT48[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R7C10[2][B]	u_la0_top/rst_ao_Z/CLK
7.148	0.232	tC2Q	FF	49	R7C10[2][B]	u_la0_top/rst_ao_Z/Q
9.900	2.752	tNET	FF	1	R3C2[0][A]	u_la0_top/internal_reg_force_triger_syn_Z[0]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	496	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R3C2[0][A]	u_la0_top/internal_reg_force_triger_syn_Z[0]/CLK
11.683	-0.200	tUnc				u_la0_top/internal_reg_force_triger_syn_Z[0]
11.648	-0.035	tSu		1	R3C2[0][A]	u_la0_top/internal_reg_force_triger_syn_Z[0]

Path Statistics:

Clock Skew	-0.033
Setup Relationship	5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.752, 92.227%; tC2Q: 0.232, 7.773%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path5

Path Summary:

Slack	1.748
Data Arrival Time	9.900
Data Required Time	11.648
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_length_Z[12]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.688	0.688	tINS	FF	496	IOT48[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R7C10[2][B]	u_la0_top/rst_ao_Z/CLK
7.148	0.232	tC2Q	FF	49	R7C10[2][B]	u_la0_top/rst_ao_Z/Q
9.900	2.752	tNET	FF	1	R2C5[0][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[12]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	496	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R2C5[0][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[12]/CLK
11.683	-0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_length_Z[12]
11.648	-0.035	tSu		1	R2C5[0][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[12]

Path Statistics:

Clock Skew	-0.033
Setup Relationship	5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.752, 92.227%; tC2Q: 0.232, 7.773%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path6

Path Summary:

Slack	1.748
Data Arrival Time	9.900
Data Required Time	11.648
From	u_la0_top/rst_ao_Z
To	u_la0_top/internal_reg_start_syn_Z[0]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.688	0.688	tINS	FF	496	IOT48[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R7C10[2][B]	u_la0_top/rst_ao_Z/CLK
7.148	0.232	tC2Q	FF	49	R7C10[2][B]	u_la0_top/rst_ao_Z/Q
9.900	2.752	tNET	FF	1	R12C8[1][A]	u_la0_top/internal_reg_start_syn_Z[0]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	496	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R12C8[1][A]	u_la0_top/internal_reg_start_syn_Z[0]/CLK
11.683	-0.200	tUnc				u_la0_top/internal_reg_start_syn_Z[0]
11.648	-0.035	tSu		1	R12C8[1][A]	u_la0_top/internal_reg_start_syn_Z[0]

Path Statistics:

Clock Skew	-0.033
Setup Relationship	5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.752, 92.227%; tC2Q: 0.232, 7.773%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path7

Path Summary:

Slack	1.748
Data Arrival Time	9.900
Data Required Time	11.648
From	u_la0_top/rst_ao_Z
To	u_la0_top/internal_reg_start_dly_Z[0]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.688	0.688	tINS	FF	496	IOT48[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R7C10[2][B]	u_la0_top/rst_ao_Z/CLK
7.148	0.232	tC2Q	FF	49	R7C10[2][B]	u_la0_top/rst_ao_Z/Q
9.900	2.752	tNET	FF	1	R5C3[2][A]	u_la0_top/internal_reg_start_dly_Z[0]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	496	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R5C3[2][A]	u_la0_top/internal_reg_start_dly_Z[0]/CLK
11.683	-0.200	tUnc				u_la0_top/internal_reg_start_dly_Z[0]
11.648	-0.035	tSu		1	R5C3[2][A]	u_la0_top/internal_reg_start_dly_Z[0]

Path Statistics:

Clock Skew	-0.033
Setup Relationship	5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.752, 92.227%; tC2Q: 0.232, 7.773%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path8

Path Summary:

Slack	1.748
Data Arrival Time	9.900
Data Required Time	11.648
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.688	0.688	tINS	FF	496	IOT48[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R7C10[2][B]	u_la0_top/rst_ao_Z/CLK
7.148	0.232	tC2Q	FF	49	R7C10[2][B]	u_la0_top/rst_ao_Z/Q
9.900	2.752	tNET	FF	1	R11C8[0][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	496	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R11C8[0][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z/CLK
11.683	-0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z
11.648	-0.035	tSu		1	R11C8[0][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z

Path Statistics:

Clock Skew	-0.033
Setup Relationship	5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.752, 92.227%; tC2Q: 0.232, 7.773%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path9

Path Summary:

Slack	1.748
Data Arrival Time	9.900
Data Required Time	11.648
From	u_la0_top/rst_ao_Z
To	u_la0_top/capture_window_sel_Z[2]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.688	0.688	tINS	FF	496	IOT48[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R7C10[2][B]	u_la0_top/rst_ao_Z/CLK
7.148	0.232	tC2Q	FF	49	R7C10[2][B]	u_la0_top/rst_ao_Z/Q
9.900	2.752	tNET	FF	1	R9C2[0][B]	u_la0_top/capture_window_sel_Z[2]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	496	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R9C2[0][B]	u_la0_top/capture_window_sel_Z[2]/CLK
11.683	-0.200	tUnc				u_la0_top/capture_window_sel_Z[2]
11.648	-0.035	tSu		1	R9C2[0][B]	u_la0_top/capture_window_sel_Z[2]

Path Statistics:

Clock Skew	-0.033
Setup Relationship	5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.752, 92.227%; tC2Q: 0.232, 7.773%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path10

Path Summary:

Slack	1.748
Data Arrival Time	9.900
Data Required Time	11.648
From	u_la0_top/rst_ao_Z
To	u_la0_top/capture_end_dly_Z
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.688	0.688	tINS	FF	496	IOT48[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R7C10[2][B]	u_la0_top/rst_ao_Z/CLK
7.148	0.232	tC2Q	FF	49	R7C10[2][B]	u_la0_top/rst_ao_Z/Q
9.900	2.752	tNET	FF	1	R8C10[0][A]	u_la0_top/capture_end_dly_Z/PRESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	496	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R8C10[0][A]	u_la0_top/capture_end_dly_Z/CLK
11.683	-0.200	tUnc				u_la0_top/capture_end_dly_Z
11.648	-0.035	tSu		1	R8C10[0][A]	u_la0_top/capture_end_dly_Z

Path Statistics:

Clock Skew	-0.033
Setup Relationship	5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.752, 92.227%; tC2Q: 0.232, 7.773%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path11

Path Summary:

Slack	1.748
Data Arrival Time	9.900
Data Required Time	11.648
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.688	0.688	tINS	FF	496	IOT48[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R7C10[2][B]	u_la0_top/rst_ao_Z/CLK
7.148	0.232	tC2Q	FF	49	R7C10[2][B]	u_la0_top/rst_ao_Z/Q
9.900	2.752	tNET	FF	1	R9C7[2][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	496	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R9C7[2][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0]/CLK
11.683	-0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0]
11.648	-0.035	tSu		1	R9C7[2][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0]

Path Statistics:

Clock Skew	-0.033
Setup Relationship	5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.752, 92.227%; tC2Q: 0.232, 7.773%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path12

Path Summary:

Slack	1.748
Data Arrival Time	9.900
Data Required Time	11.648
From	u_la0_top/rst_ao_Z
To	u_la0_top/capture_window_sel_Z[1]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.688	0.688	tINS	FF	496	IOT48[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R7C10[2][B]	u_la0_top/rst_ao_Z/CLK
7.148	0.232	tC2Q	FF	49	R7C10[2][B]	u_la0_top/rst_ao_Z/Q
9.900	2.752	tNET	FF	1	R9C2[0][A]	u_la0_top/capture_window_sel_Z[1]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	496	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R9C2[0][A]	u_la0_top/capture_window_sel_Z[1]/CLK
11.683	-0.200	tUnc				u_la0_top/capture_window_sel_Z[1]
11.648	-0.035	tSu		1	R9C2[0][A]	u_la0_top/capture_window_sel_Z[1]

Path Statistics:

Clock Skew	-0.033
Setup Relationship	5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.752, 92.227%; tC2Q: 0.232, 7.773%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path13

Path Summary:

Slack	1.748
Data Arrival Time	9.900
Data Required Time	11.648
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_length_Z[4]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.688	0.688	tINS	FF	496	IOT48[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R7C10[2][B]	u_la0_top/rst_ao_Z/CLK
7.148	0.232	tC2Q	FF	49	R7C10[2][B]	u_la0_top/rst_ao_Z/Q
9.900	2.752	tNET	FF	1	R8C2[0][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[4]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	496	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R8C2[0][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[4]/CLK
11.683	-0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_length_Z[4]
11.648	-0.035	tSu		1	R8C2[0][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[4]

Path Statistics:

Clock Skew	-0.033
Setup Relationship	5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.752, 92.227%; tC2Q: 0.232, 7.773%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path14

Path Summary:

Slack	1.748
Data Arrival Time	9.900
Data Required Time	11.648
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_length_Z[3]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.688	0.688	tINS	FF	496	IOT48[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R7C10[2][B]	u_la0_top/rst_ao_Z/CLK
7.148	0.232	tC2Q	FF	49	R7C10[2][B]	u_la0_top/rst_ao_Z/Q
9.900	2.752	tNET	FF	1	R7C10[0][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[3]/PRESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	496	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R7C10[0][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[3]/CLK
11.683	-0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_length_Z[3]
11.648	-0.035	tSu		1	R7C10[0][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[3]

Path Statistics:

Clock Skew	-0.033
Setup Relationship	5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.752, 92.227%; tC2Q: 0.232, 7.773%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path15

Path Summary:

Slack	1.748
Data Arrival Time	9.900
Data Required Time	11.648
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_length_Z[9]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.688	0.688	tINS	FF	496	IOT48[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R7C10[2][B]	u_la0_top/rst_ao_Z/CLK
7.148	0.232	tC2Q	FF	49	R7C10[2][B]	u_la0_top/rst_ao_Z/Q
9.900	2.752	tNET	FF	1	R8C10[0][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[9]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	496	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R8C10[0][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[9]/CLK
11.683	-0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_length_Z[9]
11.648	-0.035	tSu		1	R8C10[0][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[9]

Path Statistics:

Clock Skew	-0.033
Setup Relationship	5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.752, 92.227%; tC2Q: 0.232, 7.773%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path16

Path Summary:

Slack	1.748
Data Arrival Time	9.900
Data Required Time	11.648
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[12]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.688	0.688	tINS	FF	496	IOT48[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R7C10[2][B]	u_la0_top/rst_ao_Z/CLK
7.148	0.232	tC2Q	FF	49	R7C10[2][B]	u_la0_top/rst_ao_Z/Q
9.900	2.752	tNET	FF	1	R9C7[1][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[12]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	496	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R9C7[1][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[12]/CLK
11.683	-0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[12]
11.648	-0.035	tSu		1	R9C7[1][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[12]

Path Statistics:

Clock Skew	-0.033
Setup Relationship	5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.752, 92.227%; tC2Q: 0.232, 7.773%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path17

Path Summary:

Slack	1.748
Data Arrival Time	9.900
Data Required Time	11.648
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[2]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.688	0.688	tINS	FF	496	IOT48[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R7C10[2][B]	u_la0_top/rst_ao_Z/CLK
7.148	0.232	tC2Q	FF	49	R7C10[2][B]	u_la0_top/rst_ao_Z/Q
9.900	2.752	tNET	FF	1	R9C9[1][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[2]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	496	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R9C9[1][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[2]/CLK
11.683	-0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[2]
11.648	-0.035	tSu		1	R9C9[1][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[2]

Path Statistics:

Clock Skew	-0.033
Setup Relationship	5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.752, 92.227%; tC2Q: 0.232, 7.773%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path18

Path Summary:

Slack	1.748
Data Arrival Time	9.900
Data Required Time	11.648
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[1]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.688	0.688	tINS	FF	496	IOT48[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R7C10[2][B]	u_la0_top/rst_ao_Z/CLK
7.148	0.232	tC2Q	FF	49	R7C10[2][B]	u_la0_top/rst_ao_Z/Q
9.900	2.752	tNET	FF	1	R9C7[2][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[1]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	496	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R9C7[2][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[1]/CLK
11.683	-0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[1]
11.648	-0.035	tSu		1	R9C7[2][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[1]

Path Statistics:

Clock Skew	-0.033
Setup Relationship	5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.752, 92.227%; tC2Q: 0.232, 7.773%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path19

Path Summary:

Slack	1.748
Data Arrival Time	9.900
Data Required Time	11.648
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_length_Z[7]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.688	0.688	tINS	FF	496	IOT48[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R7C10[2][B]	u_la0_top/rst_ao_Z/CLK
7.148	0.232	tC2Q	FF	49	R7C10[2][B]	u_la0_top/rst_ao_Z/Q
9.900	2.752	tNET	FF	1	R8C10[2][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[7]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	496	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R8C10[2][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[7]/CLK
11.683	-0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_length_Z[7]
11.648	-0.035	tSu		1	R8C10[2][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[7]

Path Statistics:

Clock Skew	-0.033
Setup Relationship	5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.752, 92.227%; tC2Q: 0.232, 7.773%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path20

Path Summary:

Slack	1.748
Data Arrival Time	9.900
Data Required Time	11.648
From	u_la0_top/rst_ao_Z
To	u_la0_top/trigger_seq_start_Z
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.688	0.688	tINS	FF	496	IOT48[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R7C10[2][B]	u_la0_top/rst_ao_Z/CLK
7.148	0.232	tC2Q	FF	49	R7C10[2][B]	u_la0_top/rst_ao_Z/Q
9.900	2.752	tNET	FF	1	R3C3[2][A]	u_la0_top/trigger_seq_start_Z/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	496	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R3C3[2][A]	u_la0_top/trigger_seq_start_Z/CLK
11.683	-0.200	tUnc				u_la0_top/trigger_seq_start_Z
11.648	-0.035	tSu		1	R3C3[2][A]	u_la0_top/trigger_seq_start_Z

Path Statistics:

Clock Skew	-0.033
Setup Relationship	5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.752, 92.227%; tC2Q: 0.232, 7.773%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path21

Path Summary:

Slack	1.748
Data Arrival Time	9.900
Data Required Time	11.648
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[9]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.688	0.688	tINS	FF	496	IOT48[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R7C10[2][B]	u_la0_top/rst_ao_Z/CLK
7.148	0.232	tC2Q	FF	49	R7C10[2][B]	u_la0_top/rst_ao_Z/Q
9.900	2.752	tNET	FF	1	R11C2[2][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[9]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	496	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R11C2[2][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[9]/CLK
11.683	-0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[9]
11.648	-0.035	tSu		1	R11C2[2][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[9]

Path Statistics:

Clock Skew	-0.033
Setup Relationship	5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.752, 92.227%; tC2Q: 0.232, 7.773%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path22

Path Summary:

Slack	1.748
Data Arrival Time	9.900
Data Required Time	11.648
From	u_la0_top/rst_ao_Z
To	u_la0_top/genblk1.u_ao_match_0/match_sep
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.688	0.688	tINS	FF	496	IOT48[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R7C10[2][B]	u_la0_top/rst_ao_Z/CLK
7.148	0.232	tC2Q	FF	49	R7C10[2][B]	u_la0_top/rst_ao_Z/Q
9.900	2.752	tNET	FF	1	R9C9[2][B]	u_la0_top/genblk1.u_ao_match_0/match_sep/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	496	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R9C9[2][B]	u_la0_top/genblk1.u_ao_match_0/match_sep/CLK
11.683	-0.200	tUnc				u_la0_top/genblk1.u_ao_match_0/match_sep
11.648	-0.035	tSu		1	R9C9[2][B]	u_la0_top/genblk1.u_ao_match_0/match_sep

Path Statistics:

Clock Skew	-0.033
Setup Relationship	5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.752, 92.227%; tC2Q: 0.232, 7.773%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path23

Path Summary:

Slack	1.748
Data Arrival Time	9.900
Data Required Time	11.648
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[3]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.688	0.688	tINS	FF	496	IOT48[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R7C10[2][B]	u_la0_top/rst_ao_Z/CLK
7.148	0.232	tC2Q	FF	49	R7C10[2][B]	u_la0_top/rst_ao_Z/Q
9.900	2.752	tNET	FF	1	R8C10[1][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[3]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	496	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R8C10[1][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[3]/CLK
11.683	-0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[3]
11.648	-0.035	tSu		1	R8C10[1][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[3]

Path Statistics:

Clock Skew	-0.033
Setup Relationship	5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.752, 92.227%; tC2Q: 0.232, 7.773%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path24

Path Summary:

Slack	1.748
Data Arrival Time	9.900
Data Required Time	11.648
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.688	0.688	tINS	FF	496	IOT48[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R7C10[2][B]	u_la0_top/rst_ao_Z/CLK
7.148	0.232	tC2Q	FF	49	R7C10[2][B]	u_la0_top/rst_ao_Z/Q
9.900	2.752	tNET	FF	1	R11C6[2][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	496	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R11C6[2][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8]/CLK
11.683	-0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8]
11.648	-0.035	tSu		1	R11C6[2][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8]

Path Statistics:

Clock Skew	-0.033
Setup Relationship	5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.752, 92.227%; tC2Q: 0.232, 7.773%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path25

Path Summary:

Slack	1.748
Data Arrival Time	9.900
Data Required Time	11.648
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_length_Z[2]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.688	0.688	tINS	FF	496	IOT48[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R7C10[2][B]	u_la0_top/rst_ao_Z/CLK
7.148	0.232	tC2Q	FF	49	R7C10[2][B]	u_la0_top/rst_ao_Z/Q
9.900	2.752	tNET	FF	1	R7C10[0][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[2]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	496	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R7C10[0][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[2]/CLK
11.683	-0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_length_Z[2]
11.648	-0.035	tSu		1	R7C10[0][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[2]

Path Statistics:

Clock Skew	-0.033
Setup Relationship	5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.752, 92.227%; tC2Q: 0.232, 7.773%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Removal Analysis Report

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	6.760
Data Arrival Time	8.548
Data Required Time	1.788
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.677	0.678	tINS	FF	496	IOT48[A]	clk_ibuf/O
6.590	0.913	tNET	FF	1	R7C10[2][B]	u_la0_top/rst_ao_Z/CLK
6.792	0.202	tC2Q	FR	49	R7C10[2][B]	u_la0_top/rst_ao_Z/Q
8.548	1.756	tNET	RR	1	R11C8[0][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	496	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R11C8[0][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z/CLK
1.777	0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z
1.788	0.011	tHld		1	R11C8[0][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.756, 89.683%; tC2Q: 0.202, 10.317%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path2

Path Summary:

Slack	6.760
Data Arrival Time	8.548
Data Required Time	1.788
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_Z
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.677	0.678	tINS	FF	496	IOT48[A]	clk_ibuf/O
6.590	0.913	tNET	FF	1	R7C10[2][B]	u_la0_top/rst_ao_Z/CLK
6.792	0.202	tC2Q	FR	49	R7C10[2][B]	u_la0_top/rst_ao_Z/Q
8.548	1.756	tNET	RR	1	R2C5[1][A]	u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_Z/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	496	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R2C5[1][A]	u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_Z/CLK
1.777	0.200	tUnc				u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_Z
1.788	0.011	tHld		1	R2C5[1][A]	u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_Z

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.756, 89.683%; tC2Q: 0.202, 10.317%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path3

Path Summary:

Slack	6.760
Data Arrival Time	8.548
Data Required Time	1.788
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_loop_Z
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.677	0.678	tINS	FF	496	IOT48[A]	clk_ibuf/O
6.590	0.913	tNET	FF	1	R7C10[2][B]	u_la0_top/rst_ao_Z/CLK
6.792	0.202	tC2Q	FR	49	R7C10[2][B]	u_la0_top/rst_ao_Z/Q
8.548	1.756	tNET	RR	1	R11C7[2][A]	u_la0_top/u_ao_mem_ctrl/capture_loop_Z/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	496	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R11C7[2][A]	u_la0_top/u_ao_mem_ctrl/capture_loop_Z/CLK
1.777	0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_loop_Z
1.788	0.011	tHld		1	R11C7[2][A]	u_la0_top/u_ao_mem_ctrl/capture_loop_Z

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.756, 89.683%; tC2Q: 0.202, 10.317%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path4

Path Summary:

Slack	6.760
Data Arrival Time	8.548
Data Required Time	1.788
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_length_Z[0]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.677	0.678	tINS	FF	496	IOT48[A]	clk_ibuf/O
6.590	0.913	tNET	FF	1	R7C10[2][B]	u_la0_top/rst_ao_Z/CLK
6.792	0.202	tC2Q	FR	49	R7C10[2][B]	u_la0_top/rst_ao_Z/Q
8.548	1.756	tNET	RR	1	R6C11[2][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[0]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	496	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R6C11[2][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[0]/CLK
1.777	0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_length_Z[0]
1.788	0.011	tHld		1	R6C11[2][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[0]

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.756, 89.683%; tC2Q: 0.202, 10.317%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path5

Path Summary:

Slack	6.760
Data Arrival Time	8.548
Data Required Time	1.788
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_length_Z[1]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.677	0.678	tINS	FF	496	IOT48[A]	clk_ibuf/O
6.590	0.913	tNET	FF	1	R7C10[2][B]	u_la0_top/rst_ao_Z/CLK
6.792	0.202	tC2Q	FR	49	R7C10[2][B]	u_la0_top/rst_ao_Z/Q
8.548	1.756	tNET	RR	1	R6C11[2][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[1]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	496	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R6C11[2][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[1]/CLK
1.777	0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_length_Z[1]
1.788	0.011	tHld		1	R6C11[2][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[1]

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.756, 89.683%; tC2Q: 0.202, 10.317%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path6

Path Summary:

Slack	6.760
Data Arrival Time	8.548
Data Required Time	1.788
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_length_Z[2]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.677	0.678	tINS	FF	496	IOT48[A]	clk_ibuf/O
6.590	0.913	tNET	FF	1	R7C10[2][B]	u_la0_top/rst_ao_Z/CLK
6.792	0.202	tC2Q	FR	49	R7C10[2][B]	u_la0_top/rst_ao_Z/Q
8.548	1.756	tNET	RR	1	R7C10[0][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[2]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	496	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R7C10[0][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[2]/CLK
1.777	0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_length_Z[2]
1.788	0.011	tHld		1	R7C10[0][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[2]

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.756, 89.683%; tC2Q: 0.202, 10.317%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path7

Path Summary:

Slack	6.760
Data Arrival Time	8.548
Data Required Time	1.788
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_length_Z[3]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.677	0.678	tINS	FF	496	IOT48[A]	clk_ibuf/O
6.590	0.913	tNET	FF	1	R7C10[2][B]	u_la0_top/rst_ao_Z/CLK
6.792	0.202	tC2Q	FR	49	R7C10[2][B]	u_la0_top/rst_ao_Z/Q
8.548	1.756	tNET	RR	1	R7C10[0][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[3]/PRESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	496	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R7C10[0][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[3]/CLK
1.777	0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_length_Z[3]
1.788	0.011	tHld		1	R7C10[0][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[3]

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.756, 89.683%; tC2Q: 0.202, 10.317%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path8

Path Summary:

Slack	6.760
Data Arrival Time	8.548
Data Required Time	1.788
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_length_Z[4]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.677	0.678	tINS	FF	496	IOT48[A]	clk_ibuf/O
6.590	0.913	tNET	FF	1	R7C10[2][B]	u_la0_top/rst_ao_Z/CLK
6.792	0.202	tC2Q	FR	49	R7C10[2][B]	u_la0_top/rst_ao_Z/Q
8.548	1.756	tNET	RR	1	R8C2[0][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[4]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	496	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R8C2[0][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[4]/CLK
1.777	0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_length_Z[4]
1.788	0.011	tHld		1	R8C2[0][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[4]

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.756, 89.683%; tC2Q: 0.202, 10.317%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path9

Path Summary:

Slack	6.760
Data Arrival Time	8.548
Data Required Time	1.788
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_length_Z[5]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.677	0.678	tINS	FF	496	IOT48[A]	clk_ibuf/O
6.590	0.913	tNET	FF	1	R7C10[2][B]	u_la0_top/rst_ao_Z/CLK
6.792	0.202	tC2Q	FR	49	R7C10[2][B]	u_la0_top/rst_ao_Z/Q
8.548	1.756	tNET	RR	1	R8C2[0][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[5]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	496	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R8C2[0][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[5]/CLK
1.777	0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_length_Z[5]
1.788	0.011	tHld		1	R8C2[0][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[5]

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.756, 89.683%; tC2Q: 0.202, 10.317%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path10

Path Summary:

Slack	6.760
Data Arrival Time	8.548
Data Required Time	1.788
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_length_Z[6]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.677	0.678	tINS	FF	496	IOT48[A]	clk_ibuf/O
6.590	0.913	tNET	FF	1	R7C10[2][B]	u_la0_top/rst_ao_Z/CLK
6.792	0.202	tC2Q	FR	49	R7C10[2][B]	u_la0_top/rst_ao_Z/Q
8.548	1.756	tNET	RR	1	R3C2[0][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[6]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	496	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R3C2[0][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[6]/CLK
1.777	0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_length_Z[6]
1.788	0.011	tHld		1	R3C2[0][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[6]

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.756, 89.683%; tC2Q: 0.202, 10.317%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path11

Path Summary:

Slack	6.760
Data Arrival Time	8.548
Data Required Time	1.788
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_length_Z[7]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.677	0.678	tINS	FF	496	IOT48[A]	clk_ibuf/O
6.590	0.913	tNET	FF	1	R7C10[2][B]	u_la0_top/rst_ao_Z/CLK
6.792	0.202	tC2Q	FR	49	R7C10[2][B]	u_la0_top/rst_ao_Z/Q
8.548	1.756	tNET	RR	1	R8C10[2][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[7]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	496	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R8C10[2][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[7]/CLK
1.777	0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_length_Z[7]
1.788	0.011	tHld		1	R8C10[2][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[7]

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.756, 89.683%; tC2Q: 0.202, 10.317%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path12

Path Summary:

Slack	6.760
Data Arrival Time	8.548
Data Required Time	1.788
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_length_Z[8]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.677	0.678	tINS	FF	496	IOT48[A]	clk_ibuf/O
6.590	0.913	tNET	FF	1	R7C10[2][B]	u_la0_top/rst_ao_Z/CLK
6.792	0.202	tC2Q	FR	49	R7C10[2][B]	u_la0_top/rst_ao_Z/Q
8.548	1.756	tNET	RR	1	R8C10[2][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[8]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	496	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R8C10[2][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[8]/CLK
1.777	0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_length_Z[8]
1.788	0.011	tHld		1	R8C10[2][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[8]

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.756, 89.683%; tC2Q: 0.202, 10.317%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path13

Path Summary:

Slack	6.760
Data Arrival Time	8.548
Data Required Time	1.788
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_length_Z[9]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.677	0.678	tINS	FF	496	IOT48[A]	clk_ibuf/O
6.590	0.913	tNET	FF	1	R7C10[2][B]	u_la0_top/rst_ao_Z/CLK
6.792	0.202	tC2Q	FR	49	R7C10[2][B]	u_la0_top/rst_ao_Z/Q
8.548	1.756	tNET	RR	1	R8C10[0][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[9]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	496	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R8C10[0][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[9]/CLK
1.777	0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_length_Z[9]
1.788	0.011	tHld		1	R8C10[0][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[9]

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.756, 89.683%; tC2Q: 0.202, 10.317%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path14

Path Summary:

Slack	6.760
Data Arrival Time	8.548
Data Required Time	1.788
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_length_Z[10]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.677	0.678	tINS	FF	496	IOT48[A]	clk_ibuf/O
6.590	0.913	tNET	FF	1	R7C10[2][B]	u_la0_top/rst_ao_Z/CLK
6.792	0.202	tC2Q	FR	49	R7C10[2][B]	u_la0_top/rst_ao_Z/Q
8.548	1.756	tNET	RR	1	R3C3[0][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[10]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	496	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R3C3[0][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[10]/CLK
1.777	0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_length_Z[10]
1.788	0.011	tHld		1	R3C3[0][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[10]

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.756, 89.683%; tC2Q: 0.202, 10.317%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path15

Path Summary:

Slack	6.760
Data Arrival Time	8.548
Data Required Time	1.788
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_length_Z[11]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.677	0.678	tINS	FF	496	IOT48[A]	clk_ibuf/O
6.590	0.913	tNET	FF	1	R7C10[2][B]	u_la0_top/rst_ao_Z/CLK
6.792	0.202	tC2Q	FR	49	R7C10[2][B]	u_la0_top/rst_ao_Z/Q
8.548	1.756	tNET	RR	1	R3C3[0][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[11]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	496	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R3C3[0][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[11]/CLK
1.777	0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_length_Z[11]
1.788	0.011	tHld		1	R3C3[0][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[11]

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.756, 89.683%; tC2Q: 0.202, 10.317%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path16

Path Summary:

Slack	6.760
Data Arrival Time	8.548
Data Required Time	1.788
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_length_Z[12]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.677	0.678	tINS	FF	496	IOT48[A]	clk_ibuf/O
6.590	0.913	tNET	FF	1	R7C10[2][B]	u_la0_top/rst_ao_Z/CLK
6.792	0.202	tC2Q	FR	49	R7C10[2][B]	u_la0_top/rst_ao_Z/Q
8.548	1.756	tNET	RR	1	R2C5[0][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[12]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	496	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R2C5[0][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[12]/CLK
1.777	0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_length_Z[12]
1.788	0.011	tHld		1	R2C5[0][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[12]

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.756, 89.683%; tC2Q: 0.202, 10.317%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path17

Path Summary:

Slack	6.760
Data Arrival Time	8.548
Data Required Time	1.788
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.677	0.678	tINS	FF	496	IOT48[A]	clk_ibuf/O
6.590	0.913	tNET	FF	1	R7C10[2][B]	u_la0_top/rst_ao_Z/CLK
6.792	0.202	tC2Q	FR	49	R7C10[2][B]	u_la0_top/rst_ao_Z/Q
8.548	1.756	tNET	RR	1	R9C7[2][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	496	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R9C7[2][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0]/CLK
1.777	0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0]
1.788	0.011	tHld		1	R9C7[2][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0]

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.756, 89.683%; tC2Q: 0.202, 10.317%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path18

Path Summary:

Slack	6.760
Data Arrival Time	8.548
Data Required Time	1.788
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[1]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.677	0.678	tINS	FF	496	IOT48[A]	clk_ibuf/O
6.590	0.913	tNET	FF	1	R7C10[2][B]	u_la0_top/rst_ao_Z/CLK
6.792	0.202	tC2Q	FR	49	R7C10[2][B]	u_la0_top/rst_ao_Z/Q
8.548	1.756	tNET	RR	1	R9C7[2][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[1]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	496	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R9C7[2][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[1]/CLK
1.777	0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[1]
1.788	0.011	tHld		1	R9C7[2][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[1]

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.756, 89.683%; tC2Q: 0.202, 10.317%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path19

Path Summary:

Slack	6.760
Data Arrival Time	8.548
Data Required Time	1.788
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[2]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.677	0.678	tINS	FF	496	IOT48[A]	clk_ibuf/O
6.590	0.913	tNET	FF	1	R7C10[2][B]	u_la0_top/rst_ao_Z/CLK
6.792	0.202	tC2Q	FR	49	R7C10[2][B]	u_la0_top/rst_ao_Z/Q
8.548	1.756	tNET	RR	1	R9C9[1][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[2]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	496	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R9C9[1][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[2]/CLK
1.777	0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[2]
1.788	0.011	tHld		1	R9C9[1][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[2]

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.756, 89.683%; tC2Q: 0.202, 10.317%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path20

Path Summary:

Slack	6.760
Data Arrival Time	8.548
Data Required Time	1.788
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[3]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.677	0.678	tINS	FF	496	IOT48[A]	clk_ibuf/O
6.590	0.913	tNET	FF	1	R7C10[2][B]	u_la0_top/rst_ao_Z/CLK
6.792	0.202	tC2Q	FR	49	R7C10[2][B]	u_la0_top/rst_ao_Z/Q
8.548	1.756	tNET	RR	1	R8C10[1][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[3]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	496	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R8C10[1][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[3]/CLK
1.777	0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[3]
1.788	0.011	tHld		1	R8C10[1][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[3]

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.756, 89.683%; tC2Q: 0.202, 10.317%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path21

Path Summary:

Slack	6.760
Data Arrival Time	8.548
Data Required Time	1.788
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[4]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.677	0.678	tINS	FF	496	IOT48[A]	clk_ibuf/O
6.590	0.913	tNET	FF	1	R7C10[2][B]	u_la0_top/rst_ao_Z/CLK
6.792	0.202	tC2Q	FR	49	R7C10[2][B]	u_la0_top/rst_ao_Z/Q
8.548	1.756	tNET	RR	1	R12C7[2][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[4]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	496	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R12C7[2][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[4]/CLK
1.777	0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[4]
1.788	0.011	tHld		1	R12C7[2][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[4]

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.756, 89.683%; tC2Q: 0.202, 10.317%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path22

Path Summary:

Slack	6.760
Data Arrival Time	8.548
Data Required Time	1.788
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[5]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.677	0.678	tINS	FF	496	IOT48[A]	clk_ibuf/O
6.590	0.913	tNET	FF	1	R7C10[2][B]	u_la0_top/rst_ao_Z/CLK
6.792	0.202	tC2Q	FR	49	R7C10[2][B]	u_la0_top/rst_ao_Z/Q
8.548	1.756	tNET	RR	1	R9C9[1][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[5]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	496	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R9C9[1][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[5]/CLK
1.777	0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[5]
1.788	0.011	tHld		1	R9C9[1][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[5]

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.756, 89.683%; tC2Q: 0.202, 10.317%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path23

Path Summary:

Slack	6.760
Data Arrival Time	8.548
Data Required Time	1.788
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[6]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.677	0.678	tINS	FF	496	IOT48[A]	clk_ibuf/O
6.590	0.913	tNET	FF	1	R7C10[2][B]	u_la0_top/rst_ao_Z/CLK
6.792	0.202	tC2Q	FR	49	R7C10[2][B]	u_la0_top/rst_ao_Z/Q
8.548	1.756	tNET	RR	1	R8C10[1][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[6]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	496	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R8C10[1][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[6]/CLK
1.777	0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[6]
1.788	0.011	tHld		1	R8C10[1][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[6]

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.756, 89.683%; tC2Q: 0.202, 10.317%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path24

Path Summary:

Slack	6.760
Data Arrival Time	8.548
Data Required Time	1.788
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[7]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.677	0.678	tINS	FF	496	IOT48[A]	clk_ibuf/O
6.590	0.913	tNET	FF	1	R7C10[2][B]	u_la0_top/rst_ao_Z/CLK
6.792	0.202	tC2Q	FR	49	R7C10[2][B]	u_la0_top/rst_ao_Z/Q
8.548	1.756	tNET	RR	1	R11C6[2][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[7]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	496	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R11C6[2][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[7]/CLK
1.777	0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[7]
1.788	0.011	tHld		1	R11C6[2][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[7]

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.756, 89.683%; tC2Q: 0.202, 10.317%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path25

Path Summary:

Slack	6.760
Data Arrival Time	8.548
Data Required Time	1.788
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.677	0.678	tINS	FF	496	IOT48[A]	clk_ibuf/O
6.590	0.913	tNET	FF	1	R7C10[2][B]	u_la0_top/rst_ao_Z/CLK
6.792	0.202	tC2Q	FR	49	R7C10[2][B]	u_la0_top/rst_ao_Z/Q
8.548	1.756	tNET	RR	1	R11C6[2][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	496	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R11C6[2][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8]/CLK
1.777	0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8]
1.788	0.011	tHld		1	R11C6[2][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8]

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.756, 89.683%; tC2Q: 0.202, 10.317%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Minimum Pulse Width Report:

Report Command:report_min_pulse_width -nworst 10 -detail

MPW1

MPW Summary:

Slack:	3.662
Actual Width:	4.662
Required Width:	1.000
Type:	Low Pulse Width
Clock:	DEFAULT_CLK
Objects:	cnt_1_Z[12]

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	clk_ibuf/I
5.688	0.688	tINS	FF	clk_ibuf/O
6.916	1.228	tNET	FF	cnt_1_Z[12]/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	clk_ibuf/I
10.675	0.675	tINS	RR	clk_ibuf/O
11.577	0.902	tNET	RR	cnt_1_Z[12]/CLK

MPW2

MPW Summary:

Slack:	3.662
Actual Width:	4.662
Required Width:	1.000
Type:	Low Pulse Width
Clock:	DEFAULT_CLK
Objects:	cnt_1_Z[10]

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	clk_ibuf/I
5.688	0.688	tINS	FF	clk_ibuf/O
6.916	1.228	tNET	FF	cnt_1_Z[10]/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	clk_ibuf/I
10.675	0.675	tINS	RR	clk_ibuf/O
11.577	0.902	tNET	RR	cnt_1_Z[10]/CLK

MPW3

MPW Summary:

Slack:	3.662
Actual Width:	4.662
Required Width:	1.000
Type:	Low Pulse Width
Clock:	DEFAULT_CLK
Objects:	cnt_1_Z[6]

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	clk_ibuf/I
5.688	0.688	tINS	FF	clk_ibuf/O
6.916	1.228	tNET	FF	cnt_1_Z[6]/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	clk_ibuf/I
10.675	0.675	tINS	RR	clk_ibuf/O
11.577	0.902	tNET	RR	cnt_1_Z[6]/CLK

MPW4

MPW Summary:

Slack:	3.662
Actual Width:	4.662
Required Width:	1.000
Type:	Low Pulse Width
Clock:	DEFAULT_CLK
Objects:	cnt_Z[11]

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	clk_ibuf/I
5.688	0.688	tINS	FF	clk_ibuf/O
6.916	1.228	tNET	FF	cnt_Z[11]/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	clk_ibuf/I
10.675	0.675	tINS	RR	clk_ibuf/O
11.577	0.902	tNET	RR	cnt_Z[11]/CLK

MPW5

MPW Summary:

Slack:	3.662
Actual Width:	4.662
Required Width:	1.000
Type:	Low Pulse Width
Clock:	DEFAULT_CLK
Objects:	dividend[24]

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	clk_ibuf/I
5.688	0.688	tINS	FF	clk_ibuf/O
6.916	1.228	tNET	FF	dividend[24]/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	clk_ibuf/I
10.675	0.675	tINS	RR	clk_ibuf/O
11.577	0.902	tNET	RR	dividend[24]/CLK

MPW6

MPW Summary:

Slack:	3.662
Actual Width:	4.662
Required Width:	1.000
Type:	Low Pulse Width
Clock:	DEFAULT_CLK
Objects:	memr_memr_0_0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	clk_ibuf/I
5.688	0.688	tINS	FF	clk_ibuf/O
6.916	1.228	tNET	FF	memr_memr_0_0/CLKA

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	clk_ibuf/I
10.675	0.675	tINS	RR	clk_ibuf/O
11.577	0.902	tNET	RR	memr_memr_0_0/CLKA

MPW7

MPW Summary:

Slack:	3.662
Actual Width:	4.662
Required Width:	1.000
Type:	Low Pulse Width
Clock:	DEFAULT_CLK
Objects:	Mdu/u_mdu/reg0_Z[31]

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	clk_ibuf/I
5.688	0.688	tINS	FF	clk_ibuf/O
6.916	1.228	tNET	FF	Mdu/u_mdu/reg0_Z[31]/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	clk_ibuf/I
10.675	0.675	tINS	RR	clk_ibuf/O
11.577	0.902	tNET	RR	Mdu/u_mdu/reg0_Z[31]/CLK

MPW8

MPW Summary:

Slack:	3.662
Actual Width:	4.662
Required Width:	1.000
Type:	Low Pulse Width
Clock:	DEFAULT_CLK
Objects:	Mdu/u_mdu/reg0_fast_Z[24]

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	clk_ibuf/I
5.688	0.688	tINS	FF	clk_ibuf/O
6.916	1.228	tNET	FF	Mdu/u_mdu/reg0_fast_Z[24]/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	clk_ibuf/I
10.675	0.675	tINS	RR	clk_ibuf/O
11.577	0.902	tNET	RR	Mdu/u_mdu/reg0_fast_Z[24]/CLK

MPW9

MPW Summary:

Slack:	3.662
Actual Width:	4.662
Required Width:	1.000
Type:	Low Pulse Width
Clock:	DEFAULT_CLK
Objects:	Mdu/u_mdu/reg0_1_rep1_Z

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	clk_ibuf/I
5.688	0.688	tINS	FF	clk_ibuf/O
6.916	1.228	tNET	FF	Mdu/u_mdu/reg0_1_rep1_Z/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	clk_ibuf/I
10.675	0.675	tINS	RR	clk_ibuf/O
11.577	0.902	tNET	RR	Mdu/u_mdu/reg0_1_rep1_Z/CLK

MPW10

MPW Summary:

Slack:	3.662
Actual Width:	4.662
Required Width:	1.000
Type:	Low Pulse Width
Clock:	DEFAULT_CLK
Objects:	Mdu/u_mdu/reg0_Z[30]

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	clk_ibuf/I
5.688	0.688	tINS	FF	clk_ibuf/O
6.916	1.228	tNET	FF	Mdu/u_mdu/reg0_Z[30]/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	clk_ibuf/I
10.675	0.675	tINS	RR	clk_ibuf/O
11.577	0.902	tNET	RR	Mdu/u_mdu/reg0_Z[30]/CLK

High Fanout Nets Report:

Report Command:report_high_fanout_nets -max_nets 10

FANOUT	NET NAME	WORST SLACK	MAX DELAY
302	clk_c	0.397	1.228
114	div_shift_number[1]	0.454	2.328
113	div_shift_number[0]	0.568	2.176
100	reg0_en	4.131	1.670
96	neg_result	3.879	3.064
92	state[1]	4.466	3.697
81	hi_result	2.842	2.509
74	reg0_exe_nx_sm0	0.800	3.470
71	state[3]	5.811	2.682
70	m0_2_03_1	0.917	1.977

Route Congestions Report:

Report Command:report_route_congestion -max_grids 10

GRID LOC	ROUTE CONGESTIONS
R39C42	0.750
R43C52	0.736
R48C48	0.694
R48C49	0.681
R44C51	0.653
R39C49	0.653
R34C47	0.653
R39C40	0.639
R39C41	0.639
R44C52	0.625

Timing Exceptions Report:

Setup Analysis Report

Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Hold Analysis Report

Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Recovery Analysis Report

Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Removal Analysis Report

Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Timing Constraints Report:

SDC Command Type	State	Detail Command