Timing Messages

Report Title	Gowin Timing Analysis Report
Design File	F:/user-bak/Users/FDELL/Desktop/IP/Integer_Multiply-Divider/ref_design/REM/Integer_Multiply_Divider_nn/project/impl/synplify/rev_1/Integer_Multiply_Divider_nn.vm
Physical Constraints File	F:\user-bak\Users\FDELL\Desktop\IP\Integer_Multiply-Divider\ref_design\REM\Integer_Multiply_Divider_nn\project\src\Integer_Multiply_Divider_nn.cst
Timing Constraints File	---
GOWIN version	v1.9.0Beta
Part Number	GW2A-LV55PG484C8/I7
Created Time	Tue Feb 19 18:00:50 2019
Legal Announcement	Copyright (C)2014-2019 Gowin Semiconductor Corporation. All rights reserved.

Timing Summaries

STA Tool Run Summary:

Setup Delay Model	Slow 0.95V 85C
Hold Delay Model	Fast 1.05V 0C
Numbers of Paths Analyzed	2800
Numbers of Endpoints Analyzed	6737
Numbers of Falling Endpoints	1
Numbers of Setup Violated Endpoints	1
Numbers of Hold Violated Endpoints	0

Clock Summary:

Clock Name	Type	Period	Frequency(MHz)	Rise	Fall	Source	Master	Objects
DEFAULT_CLK	Base	10.000	100.000	0.000	5.000

Max Frequency Summary:

NO.	Clock Name	Fmax	Entity
1	DEFAULT_CLK	95.748(MHz)	TOP

Total Negative Slack Summary:

Clock Name	Analysis Type	Endpoints TNS	Number of Endpoints
DEFAULT_CLK	Setup	-0.444	1
DEFAULT_CLK	Hold	0.000	0

Timing Details

Path Slacks Table:

Setup Paths Table

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Data Delay
1	-0.444	Mdu/u_mdu/reg1_Z[0]/Q	Mdu/u_mdu/reg0_Z[7]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	10.209
2	0.217	Mdu/u_mdu/div_shift_number_Z[0]/Q	Mdu/u_mdu/reg0_31_rep1_Z/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	9.548
3	0.217	Mdu/u_mdu/div_shift_number_Z[0]/Q	Mdu/u_mdu/reg0_fast_Z[31]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	9.548
4	0.336	Mdu/u_mdu/div_shift_number_Z[1]/Q	Mdu/u_mdu/reg0_Z[55]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	9.429
5	0.406	Mdu/u_mdu/div_shift_number_Z[0]/Q	Mdu/u_mdu/reg0_Z[31]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	9.359
6	0.723	Mdu/u_mdu/reg1_Z[30]/Q	Mdu/u_mdu/div_shift_number_Z[5]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	9.042
7	0.747	Mdu/u_mdu/div_shift_number_Z[1]/Q	Mdu/u_mdu/reg0_Z[63]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	9.018
8	0.752	Mdu/u_mdu/div_shift_number_Z[1]/Q	Mdu/u_mdu/reg0_Z[64]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	9.013
9	0.900	Mdu/u_mdu/div_shift_number_Z[1]/Q	Mdu/u_mdu/reg0_Z[59]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	8.865
10	0.915	Mdu/u_mdu/reg1_Z[0]/Q	Mdu/u_mdu/reg0_Z[36]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	8.850
11	0.967	Mdu/u_mdu/reg1_Z[0]/Q	Mdu/u_mdu/reg0_Z[41]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	8.798
12	0.998	Mdu/u_mdu/reg0_Z[8]/Q	Mdu/u_mdu/reg0_Z[37]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	8.767
13	1.018	Mdu/u_mdu/div_shift_number_Z[1]/Q	Mdu/u_mdu/reg0_fast_Z[20]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	8.747
14	1.018	Mdu/u_mdu/div_shift_number_Z[1]/Q	Mdu/u_mdu/reg0_Z[20]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	8.747
15	1.037	Mdu/u_mdu/reg1_Z[0]/Q	Mdu/u_mdu/reg0_Z[61]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	8.728
16	1.039	Mdu/u_mdu/reg0_fast_Z[2]/Q	Mdu/u_mdu/reg0_Z[16]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	8.726
17	1.086	Mdu/u_mdu/reg0_Z[8]/Q	Mdu/u_mdu/reg0_Z[49]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	8.679
18	1.091	Mdu/u_mdu/reg0_Z[5]/Q	Mdu/u_mdu/reg0_fast_Z[19]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	8.674
19	1.191	Mdu/u_mdu/div_shift_number_Z[0]/Q	Mdu/u_mdu/reg0_Z[10]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	8.574
20	1.199	Mdu/u_mdu/div_shift_number_Z[1]/Q	Mdu/u_mdu/reg0_fast_Z[12]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	8.566
21	1.199	Mdu/u_mdu/div_shift_number_Z[1]/Q	Mdu/u_mdu/reg0_Z[12]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	8.566
22	1.200	Mdu/u_mdu/reg0_fast_Z[23]/Q	Mdu/u_mdu/div_shift_number_Z[0]/RESET	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	8.565
23	1.200	Mdu/u_mdu/reg0_fast_Z[23]/Q	Mdu/u_mdu/div_shift_number_Z[1]/RESET	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	8.565
24	1.200	Mdu/u_mdu/reg0_fast_Z[23]/Q	Mdu/u_mdu/div_shift_number_Z[2]/RESET	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	8.565
25	1.200	Mdu/u_mdu/reg0_fast_Z[23]/Q	Mdu/u_mdu/div_shift_number_Z[3]/RESET	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	8.565

Hold Paths Table

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Data Delay
1	0.213	u_la0_top/u_ao_mem_ctrl/data_reg_Z[65]/Q	u_la0_top/u_ao_mem_ctrl/mem_mem_0_32/DI1	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.462
2	0.213	u_la0_top/u_ao_mem_ctrl/data_reg_Z[64]/Q	u_la0_top/u_ao_mem_ctrl/mem_mem_0_32/DI0	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.462
3	0.225	u_la0_top/u_ao_mem_ctrl/data_reg_Z[85]/Q	u_la0_top/u_ao_mem_ctrl/mem_mem_0_42/DI1	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.474
4	0.225	u_la0_top/u_ao_mem_ctrl/data_reg_Z[84]/Q	u_la0_top/u_ao_mem_ctrl/mem_mem_0_42/DI0	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.474
5	0.231	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[2]/Q	u_la0_top/u_ao_mem_ctrl/mem_mem_0_9/ADA3	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.349
6	0.233	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8]/Q	u_la0_top/u_ao_mem_ctrl/mem_mem_0_9/ADA9	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.351
7	0.343	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[4]/Q	u_la0_top/u_ao_mem_ctrl/mem_mem_0_9/ADA5	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.461
8	0.351	u_la0_top/u_ao_mem_ctrl/data_reg_Z[75]/Q	u_la0_top/u_ao_mem_ctrl/mem_mem_0_37/DI1	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.600
9	0.353	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[9]/Q	u_la0_top/u_ao_mem_ctrl/mem_mem_0_4/ADA10	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.471
10	0.354	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[5]/Q	u_la0_top/u_ao_mem_ctrl/mem_mem_0_32/ADA6	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.472
11	0.354	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[5]/Q	u_la0_top/u_ao_mem_ctrl/mem_mem_0_9/ADA6	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.472
12	0.355	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[10]/Q	u_la0_top/u_ao_mem_ctrl/mem_mem_0_9/ADA11	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.473
13	0.355	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[10]/Q	u_la0_top/u_ao_mem_ctrl/mem_mem_0_4/ADA11	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.473
14	0.363	cnt_Z[8]/Q	memr_memr_0_10/ADA9	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.481
15	0.364	cnt_Z[10]/Q	memr_memr_0_9/ADA11	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.482
16	0.364	cnt_Z[3]/Q	memr_memr_0_7/ADA4	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.482
17	0.364	cnt_Z[1]/Q	memr_memr_0_7/ADA2	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.482
18	0.364	cnt_Z[0]/Q	memr_memr_0_7/ADA1	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.482
19	0.367	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[9]/Q	u_la0_top/u_ao_mem_ctrl/mem_mem_0_37/ADA10	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.485
20	0.367	cnt_1_Z[10]/Q	memr_memr_0_8/ADB11	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.485
21	0.367	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[10]/Q	u_la0_top/u_ao_mem_ctrl/mem_mem_0_37/ADA11	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.485
22	0.369	cnt_Z[8]/Q	memr_memr_0_8/ADA9	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.487
23	0.369	cnt_Z[8]/Q	memr_memr_0_6/ADA9	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.487
24	0.378	u_la0_top/u_ao_mem_ctrl/data_reg_Z[40]/Q	u_la0_top/u_ao_mem_ctrl/mem_mem_0_20/DI0	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.627
25	0.386	cnt_Z[0]/Q	memr_memr_0_6/ADA1	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.504

Recovery Paths Table

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	1.748	u_la0_top/rst_ao_Z/Q	u_la0_top/triger_level_cnt_Z[0]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	5.000	0.033	2.984
2	1.748	u_la0_top/rst_ao_Z/Q	u_la0_top/triger_level_cnt_Z[2]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	5.000	0.033	2.984
3	1.748	u_la0_top/rst_ao_Z/Q	u_la0_top/capture_window_sel[3]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	5.000	0.033	2.984
4	1.748	u_la0_top/rst_ao_Z/Q	u_la0_top/internal_reg_force_triger_syn_Z[0]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	5.000	0.033	2.984
5	1.748	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_length_Z[12]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	5.000	0.033	2.984
6	1.748	u_la0_top/rst_ao_Z/Q	u_la0_top/internal_reg_start_syn_Z[0]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	5.000	0.033	2.984
7	1.748	u_la0_top/rst_ao_Z/Q	u_la0_top/internal_reg_start_dly_Z[0]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	5.000	0.033	2.984
8	1.748	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	5.000	0.033	2.984
9	1.748	u_la0_top/rst_ao_Z/Q	u_la0_top/capture_window_sel_Z[2]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	5.000	0.033	2.984
10	1.748	u_la0_top/rst_ao_Z/Q	u_la0_top/capture_end_dly_Z/PRESET	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	5.000	0.033	2.984
11	1.748	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	5.000	0.033	2.984
12	1.748	u_la0_top/rst_ao_Z/Q	u_la0_top/capture_window_sel_Z[1]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	5.000	0.033	2.984
13	1.748	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_length_Z[4]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	5.000	0.033	2.984
14	1.748	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_length_Z[3]/PRESET	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	5.000	0.033	2.984
15	1.748	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_length_Z[9]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	5.000	0.033	2.984
16	1.748	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[12]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	5.000	0.033	2.984
17	1.748	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[2]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	5.000	0.033	2.984
18	1.748	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[1]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	5.000	0.033	2.984
19	1.748	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_length_Z[7]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	5.000	0.033	2.984
20	1.748	u_la0_top/rst_ao_Z/Q	u_la0_top/trigger_seq_start_Z/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	5.000	0.033	2.984
21	1.748	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[9]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	5.000	0.033	2.984
22	1.748	u_la0_top/rst_ao_Z/Q	u_la0_top/genblk1.u_ao_match_0/match_sep/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	5.000	0.033	2.984
23	1.748	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[3]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	5.000	0.033	2.984
24	1.748	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	5.000	0.033	2.984
25	1.748	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_length_Z[2]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	5.000	0.033	2.984

Removal Paths Table

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	6.760	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	-5.000	0.013	1.958
2	6.760	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_Z/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	-5.000	0.013	1.958
3	6.760	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_loop_Z/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	-5.000	0.013	1.958
4	6.760	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_length_Z[0]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	-5.000	0.013	1.958
5	6.760	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_length_Z[1]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	-5.000	0.013	1.958
6	6.760	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_length_Z[2]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	-5.000	0.013	1.958
7	6.760	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_length_Z[3]/PRESET	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	-5.000	0.013	1.958
8	6.760	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_length_Z[4]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	-5.000	0.013	1.958
9	6.760	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_length_Z[5]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	-5.000	0.013	1.958
10	6.760	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_length_Z[6]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	-5.000	0.013	1.958
11	6.760	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_length_Z[7]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	-5.000	0.013	1.958
12	6.760	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_length_Z[8]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	-5.000	0.013	1.958
13	6.760	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_length_Z[9]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	-5.000	0.013	1.958
14	6.760	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_length_Z[10]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	-5.000	0.013	1.958
15	6.760	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_length_Z[11]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	-5.000	0.013	1.958
16	6.760	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_length_Z[12]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	-5.000	0.013	1.958
17	6.760	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	-5.000	0.013	1.958
18	6.760	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[1]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	-5.000	0.013	1.958
19	6.760	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[2]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	-5.000	0.013	1.958
20	6.760	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[3]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	-5.000	0.013	1.958
21	6.760	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[4]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	-5.000	0.013	1.958
22	6.760	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[5]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	-5.000	0.013	1.958
23	6.760	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[6]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	-5.000	0.013	1.958
24	6.760	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[7]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	-5.000	0.013	1.958
25	6.760	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	-5.000	0.013	1.958

Minimum Pulse Width Table:

Report Command:report_min_pulse_width -nworst 10 -detail

Number	Slack	Actual Width	Required Width	Type	Clock	Objects
1	3.662	4.662	1.000	Low Pulse Width	DEFAULT_CLK	cnt_1_Z[12]
2	3.662	4.662	1.000	Low Pulse Width	DEFAULT_CLK	cnt_1_Z[10]
3	3.662	4.662	1.000	Low Pulse Width	DEFAULT_CLK	cnt_1_Z[6]
4	3.662	4.662	1.000	Low Pulse Width	DEFAULT_CLK	cnt_Z[11]
5	3.662	4.662	1.000	Low Pulse Width	DEFAULT_CLK	divisor[29]
6	3.662	4.662	1.000	Low Pulse Width	DEFAULT_CLK	m_Z[30]
7	3.662	4.662	1.000	Low Pulse Width	DEFAULT_CLK	Mdu/u_mdu/reg0_Z[29]
8	3.662	4.662	1.000	Low Pulse Width	DEFAULT_CLK	Mdu/u_mdu/reg0_fast_Z[1]
9	3.662	4.662	1.000	Low Pulse Width	DEFAULT_CLK	Mdu/u_mdu/reg0_fast_Z[0]
10	3.662	4.662	1.000	Low Pulse Width	DEFAULT_CLK	Mdu/u_mdu/reg0_Z[28]

Timing Report By Analysis Type:

Setup Analysis Report

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	-0.444
Data Arrival Time	12.092
Data Required Time	11.648
From	Mdu/u_mdu/reg1_Z[0]
To	Mdu/u_mdu/reg0_Z[7]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.683	0.683	tINS	RR	498	IOT48[A]	clk_ibuf/O
1.883	1.201	tNET	RR	1	R37C38[0][B]	Mdu/u_mdu/reg1_Z[0]/CLK
2.115	0.232	tC2Q	RF	6	R37C38[0][B]	Mdu/u_mdu/reg1_Z[0]/Q
3.057	0.942	tNET	FF	1	R40C32[3][B]	Mdu/u_mdu/adder_sum_s_0_sf_lofx_cZ/I1
3.428	0.371	tINS	FF	1	R40C32[3][B]	Mdu/u_mdu/adder_sum_s_0_sf_lofx_cZ/F
3.841	0.413	tNET	FF	2	R42C32[1][A]	Mdu/u_mdu/adder_sum_cry_0_0/I0
4.411	0.570	tINS	FR	1	R42C32[1][A]	Mdu/u_mdu/adder_sum_cry_0_0/COUT
4.411	0.000	tNET	RR	2	R42C32[1][B]	Mdu/u_mdu/adder_sum_cry_1_0/CIN
4.447	0.035	tINS	RF	1	R42C32[1][B]	Mdu/u_mdu/adder_sum_cry_1_0/COUT
4.447	0.000	tNET	FF	2	R42C32[2][A]	Mdu/u_mdu/adder_sum_cry_2_0/CIN
4.482	0.035	tINS	FF	1	R42C32[2][A]	Mdu/u_mdu/adder_sum_cry_2_0/COUT
4.482	0.000	tNET	FF	2	R42C32[2][B]	Mdu/u_mdu/adder_sum_cry_3_0/CIN
4.517	0.035	tINS	FF	1	R42C32[2][B]	Mdu/u_mdu/adder_sum_cry_3_0/COUT
4.517	0.000	tNET	FF	2	R42C33[0][A]	Mdu/u_mdu/adder_sum_cry_4_0/CIN
4.552	0.035	tINS	FF	1	R42C33[0][A]	Mdu/u_mdu/adder_sum_cry_4_0/COUT
4.552	0.000	tNET	FF	2	R42C33[0][B]	Mdu/u_mdu/adder_sum_cry_5_0/CIN
4.587	0.035	tINS	FF	1	R42C33[0][B]	Mdu/u_mdu/adder_sum_cry_5_0/COUT
4.587	0.000	tNET	FF	2	R42C33[1][A]	Mdu/u_mdu/adder_sum_cry_6_0/CIN
4.623	0.035	tINS	FF	1	R42C33[1][A]	Mdu/u_mdu/adder_sum_cry_6_0/COUT
4.623	0.000	tNET	FF	2	R42C33[1][B]	Mdu/u_mdu/adder_sum_cry_7_0/CIN
4.658	0.035	tINS	FF	1	R42C33[1][B]	Mdu/u_mdu/adder_sum_cry_7_0/COUT
4.658	0.000	tNET	FF	2	R42C33[2][A]	Mdu/u_mdu/adder_sum_cry_8_0/CIN
4.693	0.035	tINS	FF	1	R42C33[2][A]	Mdu/u_mdu/adder_sum_cry_8_0/COUT
4.693	0.000	tNET	FF	2	R42C33[2][B]	Mdu/u_mdu/adder_sum_cry_9_0/CIN
4.728	0.035	tINS	FF	1	R42C33[2][B]	Mdu/u_mdu/adder_sum_cry_9_0/COUT
4.728	0.000	tNET	FF	2	R42C34[0][A]	Mdu/u_mdu/adder_sum_cry_10_0/CIN
4.763	0.035	tINS	FF	1	R42C34[0][A]	Mdu/u_mdu/adder_sum_cry_10_0/COUT
4.763	0.000	tNET	FF	2	R42C34[0][B]	Mdu/u_mdu/adder_sum_cry_11_0/CIN
4.799	0.035	tINS	FF	1	R42C34[0][B]	Mdu/u_mdu/adder_sum_cry_11_0/COUT
4.799	0.000	tNET	FF	2	R42C34[1][A]	Mdu/u_mdu/adder_sum_cry_12_0/CIN
4.834	0.035	tINS	FF	1	R42C34[1][A]	Mdu/u_mdu/adder_sum_cry_12_0/COUT
4.834	0.000	tNET	FF	2	R42C34[1][B]	Mdu/u_mdu/adder_sum_cry_13_0/CIN
4.869	0.035	tINS	FF	1	R42C34[1][B]	Mdu/u_mdu/adder_sum_cry_13_0/COUT
4.869	0.000	tNET	FF	2	R42C34[2][A]	Mdu/u_mdu/adder_sum_cry_14_0/CIN
4.904	0.035	tINS	FF	1	R42C34[2][A]	Mdu/u_mdu/adder_sum_cry_14_0/COUT
4.904	0.000	tNET	FF	2	R42C34[2][B]	Mdu/u_mdu/adder_sum_cry_15_0/CIN
4.939	0.035	tINS	FF	1	R42C34[2][B]	Mdu/u_mdu/adder_sum_cry_15_0/COUT
4.939	0.000	tNET	FF	2	R42C35[0][A]	Mdu/u_mdu/adder_sum_cry_16_0/CIN
4.975	0.035	tINS	FF	1	R42C35[0][A]	Mdu/u_mdu/adder_sum_cry_16_0/COUT
4.975	0.000	tNET	FF	2	R42C35[0][B]	Mdu/u_mdu/adder_sum_cry_17_0/CIN
5.010	0.035	tINS	FF	1	R42C35[0][B]	Mdu/u_mdu/adder_sum_cry_17_0/COUT
5.010	0.000	tNET	FF	2	R42C35[1][A]	Mdu/u_mdu/adder_sum_cry_18_0/CIN
5.045	0.035	tINS	FF	1	R42C35[1][A]	Mdu/u_mdu/adder_sum_cry_18_0/COUT
5.045	0.000	tNET	FF	2	R42C35[1][B]	Mdu/u_mdu/adder_sum_cry_19_0/CIN
5.080	0.035	tINS	FF	1	R42C35[1][B]	Mdu/u_mdu/adder_sum_cry_19_0/COUT
5.080	0.000	tNET	FF	2	R42C35[2][A]	Mdu/u_mdu/adder_sum_cry_20_0/CIN
5.115	0.035	tINS	FF	1	R42C35[2][A]	Mdu/u_mdu/adder_sum_cry_20_0/COUT
5.115	0.000	tNET	FF	2	R42C35[2][B]	Mdu/u_mdu/adder_sum_cry_21_0/CIN
5.151	0.035	tINS	FF	1	R42C35[2][B]	Mdu/u_mdu/adder_sum_cry_21_0/COUT
5.151	0.000	tNET	FF	2	R42C36[0][A]	Mdu/u_mdu/adder_sum_cry_22_0/CIN
5.186	0.035	tINS	FF	1	R42C36[0][A]	Mdu/u_mdu/adder_sum_cry_22_0/COUT
5.186	0.000	tNET	FF	2	R42C36[0][B]	Mdu/u_mdu/adder_sum_cry_23_0/CIN
5.221	0.035	tINS	FF	1	R42C36[0][B]	Mdu/u_mdu/adder_sum_cry_23_0/COUT
5.221	0.000	tNET	FF	2	R42C36[1][A]	Mdu/u_mdu/adder_sum_cry_24_0/CIN
5.256	0.035	tINS	FF	1	R42C36[1][A]	Mdu/u_mdu/adder_sum_cry_24_0/COUT
5.256	0.000	tNET	FF	2	R42C36[1][B]	Mdu/u_mdu/adder_sum_cry_25_0/CIN
5.291	0.035	tINS	FF	1	R42C36[1][B]	Mdu/u_mdu/adder_sum_cry_25_0/COUT
5.291	0.000	tNET	FF	2	R42C36[2][A]	Mdu/u_mdu/adder_sum_cry_26_0/CIN
5.327	0.035	tINS	FF	1	R42C36[2][A]	Mdu/u_mdu/adder_sum_cry_26_0/COUT
5.327	0.000	tNET	FF	2	R42C36[2][B]	Mdu/u_mdu/adder_sum_cry_27_0/CIN
5.362	0.035	tINS	FF	1	R42C36[2][B]	Mdu/u_mdu/adder_sum_cry_27_0/COUT
5.362	0.000	tNET	FF	2	R42C37[0][A]	Mdu/u_mdu/adder_sum_cry_28_0/CIN
5.397	0.035	tINS	FF	1	R42C37[0][A]	Mdu/u_mdu/adder_sum_cry_28_0/COUT
5.397	0.000	tNET	FF	2	R42C37[0][B]	Mdu/u_mdu/adder_sum_cry_29_0/CIN
5.432	0.035	tINS	FF	1	R42C37[0][B]	Mdu/u_mdu/adder_sum_cry_29_0/COUT
5.432	0.000	tNET	FF	2	R42C37[1][A]	Mdu/u_mdu/adder_sum_cry_30_0/CIN
5.467	0.035	tINS	FF	1	R42C37[1][A]	Mdu/u_mdu/adder_sum_cry_30_0/COUT
5.467	0.000	tNET	FF	2	R42C37[1][B]	Mdu/u_mdu/adder_sum_cry_31_0/CIN
5.503	0.035	tINS	FF	1	R42C37[1][B]	Mdu/u_mdu/adder_sum_cry_31_0/COUT
5.503	0.000	tNET	FF	2	R42C37[2][A]	Mdu/u_mdu/adder_sum_s_32_0/CIN
5.973	0.470	tINS	FF	6	R42C37[2][A]	Mdu/u_mdu/adder_sum_s_32_0/SUM
6.941	0.968	tNET	FF	1	R35C31[1][A]	Mdu/u_mdu/reg0_exe_nx_ss0_cZ/I0
7.312	0.371	tINS	FF	50	R35C31[1][A]	Mdu/u_mdu/reg0_exe_nx_ss0_cZ/F
8.393	1.081	tNET	FF	1	R49C33[3][B]	Mdu/u_mdu/reg0_exe_nx_m1_cZ[7]/I3
8.764	0.371	tINS	FF	1	R49C33[3][B]	Mdu/u_mdu/reg0_exe_nx_m1_cZ[7]/F
9.552	0.789	tNET	FF	1	R37C34[2][B]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[7]/I1
10.005	0.453	tINS	FF	1	R37C34[2][B]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[7]/F
10.495	0.490	tNET	FF	1	R33C34[0][A]	Mdu/u_mdu/reg0_exe_nx_cZ[7]/I3
10.866	0.371	tINS	FF	1	R33C34[0][A]	Mdu/u_mdu/reg0_exe_nx_cZ[7]/F
11.522	0.656	tNET	FF	1	R30C35[2][B]	Mdu/u_mdu/reg0_nx_cZ[7]/I0
12.092	0.570	tINS	FR	1	R30C35[2][B]	Mdu/u_mdu/reg0_nx_cZ[7]/F
12.092	0.000	tNET	RR	1	R30C35[2][B]	Mdu/u_mdu/reg0_Z[7]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	498	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R30C35[2][B]	Mdu/u_mdu/reg0_Z[7]/CLK
11.683	-0.200	tUnc				Mdu/u_mdu/reg0_Z[7]
11.648	-0.035	tSu		1	R30C35[2][B]	Mdu/u_mdu/reg0_Z[7]

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	8
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 4.638, 45.432%; route: 5.339, 52.295%; tC2Q: 0.232, 2.272%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path2

Path Summary:

Slack	0.217
Data Arrival Time	11.431
Data Required Time	11.648
From	Mdu/u_mdu/div_shift_number_Z[0]
To	Mdu/u_mdu/reg0_31_rep1_Z
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.683	0.683	tINS	RR	498	IOT48[A]	clk_ibuf/O
1.883	1.201	tNET	RR	1	R51C37[1][A]	Mdu/u_mdu/div_shift_number_Z[0]/CLK
2.115	0.232	tC2Q	RF	113	R51C37[1][A]	Mdu/u_mdu/div_shift_number_Z[0]/Q
3.444	1.329	tNET	FF	1	R41C34[2][A]	Mdu/u_mdu/m3_0_03_0_0_cZ/I0
3.961	0.517	tINS	FF	5	R41C34[2][A]	Mdu/u_mdu/m3_0_03_0_0_cZ/F
4.635	0.673	tNET	FF	1	R44C32[2][A]	Mdu/u_mdu/m3_0_03_0_0_RNIV0NN/I0
5.006	0.371	tINS	FF	3	R44C32[2][A]	Mdu/u_mdu/m3_0_03_0_0_RNIV0NN/F
5.700	0.694	tNET	FF	1	R51C33[2][B]	Mdu/u_mdu/m15_2_03_0_0_cZ/I0
6.071	0.371	tINS	FF	2	R51C33[2][B]	Mdu/u_mdu/m15_2_03_0_0_cZ/F
6.760	0.688	tNET	FF	1	R51C38[3][B]	Mdu/u_mdu/m15_2_03_0_0_RNI9I0C/I0
7.277	0.517	tINS	FF	3	R51C38[3][B]	Mdu/u_mdu/m15_2_03_0_0_RNI9I0C/F
8.135	0.859	tNET	FF	1	R44C35[0][A]	Mdu/u_mdu/m31_4_01_cZ/I1
8.506	0.371	tINS	FF	1	R44C35[0][A]	Mdu/u_mdu/m31_4_01_cZ/F
9.146	0.640	tNET	FF	1	R40C35[3][A]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[31]/I2
9.716	0.570	tINS	FR	1	R40C35[3][A]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[31]/F
9.717	0.001	tNET	RR	1	R40C35[2][B]	Mdu/u_mdu/reg0_exe_nx_cZ[31]/I3
10.170	0.453	tINS	RF	3	R40C35[2][B]	Mdu/u_mdu/reg0_exe_nx_cZ[31]/F
10.969	0.799	tNET	FF	1	R32C40[2][A]	Mdu/u_mdu/reg0_nx_rep1_cZ[31]/I0
11.431	0.462	tINS	FR	1	R32C40[2][A]	Mdu/u_mdu/reg0_nx_rep1_cZ[31]/F
11.431	0.000	tNET	RR	1	R32C40[2][A]	Mdu/u_mdu/reg0_31_rep1_Z/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	498	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R32C40[2][A]	Mdu/u_mdu/reg0_31_rep1_Z/CLK
11.683	-0.200	tUnc				Mdu/u_mdu/reg0_31_rep1_Z
11.648	-0.035	tSu		1	R32C40[2][A]	Mdu/u_mdu/reg0_31_rep1_Z

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	8
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 3.632, 38.038%; route: 5.684, 59.532%; tC2Q: 0.232, 2.430%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path3

Path Summary:

Slack	0.217
Data Arrival Time	11.431
Data Required Time	11.648
From	Mdu/u_mdu/div_shift_number_Z[0]
To	Mdu/u_mdu/reg0_fast_Z[31]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.683	0.683	tINS	RR	498	IOT48[A]	clk_ibuf/O
1.883	1.201	tNET	RR	1	R51C37[1][A]	Mdu/u_mdu/div_shift_number_Z[0]/CLK
2.115	0.232	tC2Q	RF	113	R51C37[1][A]	Mdu/u_mdu/div_shift_number_Z[0]/Q
3.444	1.329	tNET	FF	1	R41C34[2][A]	Mdu/u_mdu/m3_0_03_0_0_cZ/I0
3.961	0.517	tINS	FF	5	R41C34[2][A]	Mdu/u_mdu/m3_0_03_0_0_cZ/F
4.635	0.673	tNET	FF	1	R44C32[2][A]	Mdu/u_mdu/m3_0_03_0_0_RNIV0NN/I0
5.006	0.371	tINS	FF	3	R44C32[2][A]	Mdu/u_mdu/m3_0_03_0_0_RNIV0NN/F
5.700	0.694	tNET	FF	1	R51C33[2][B]	Mdu/u_mdu/m15_2_03_0_0_cZ/I0
6.071	0.371	tINS	FF	2	R51C33[2][B]	Mdu/u_mdu/m15_2_03_0_0_cZ/F
6.760	0.688	tNET	FF	1	R51C38[3][B]	Mdu/u_mdu/m15_2_03_0_0_RNI9I0C/I0
7.277	0.517	tINS	FF	3	R51C38[3][B]	Mdu/u_mdu/m15_2_03_0_0_RNI9I0C/F
8.135	0.859	tNET	FF	1	R44C35[0][A]	Mdu/u_mdu/m31_4_01_cZ/I1
8.506	0.371	tINS	FF	1	R44C35[0][A]	Mdu/u_mdu/m31_4_01_cZ/F
9.146	0.640	tNET	FF	1	R40C35[3][A]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[31]/I2
9.716	0.570	tINS	FR	1	R40C35[3][A]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[31]/F
9.717	0.001	tNET	RR	1	R40C35[2][B]	Mdu/u_mdu/reg0_exe_nx_cZ[31]/I3
10.170	0.453	tINS	RF	3	R40C35[2][B]	Mdu/u_mdu/reg0_exe_nx_cZ[31]/F
10.969	0.799	tNET	FF	1	R32C40[2][B]	Mdu/u_mdu/reg0_nx_fast_cZ[31]/I0
11.431	0.462	tINS	FR	1	R32C40[2][B]	Mdu/u_mdu/reg0_nx_fast_cZ[31]/F
11.431	0.000	tNET	RR	1	R32C40[2][B]	Mdu/u_mdu/reg0_fast_Z[31]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	498	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R32C40[2][B]	Mdu/u_mdu/reg0_fast_Z[31]/CLK
11.683	-0.200	tUnc				Mdu/u_mdu/reg0_fast_Z[31]
11.648	-0.035	tSu		1	R32C40[2][B]	Mdu/u_mdu/reg0_fast_Z[31]

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	8
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 3.632, 38.038%; route: 5.684, 59.532%; tC2Q: 0.232, 2.430%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path4

Path Summary:

Slack	0.336
Data Arrival Time	11.313
Data Required Time	11.648
From	Mdu/u_mdu/div_shift_number_Z[1]
To	Mdu/u_mdu/reg0_Z[55]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.683	0.683	tINS	RR	498	IOT48[A]	clk_ibuf/O
1.883	1.201	tNET	RR	1	R51C37[1][B]	Mdu/u_mdu/div_shift_number_Z[1]/CLK
2.115	0.232	tC2Q	RF	114	R51C37[1][B]	Mdu/u_mdu/div_shift_number_Z[1]/Q
4.249	2.133	tNET	FF	1	R34C40[2][B]	Mdu/u_mdu/m55_0_03_1_cZ/I1
4.620	0.371	tINS	FF	1	R34C40[2][B]	Mdu/u_mdu/m55_0_03_1_cZ/F
4.624	0.004	tNET	FF	1	R34C40[3][A]	Mdu/u_mdu/m55_0_03_cZ/I1
5.141	0.517	tINS	FF	3	R34C40[3][A]	Mdu/u_mdu/m55_0_03_cZ/F
6.210	1.069	tNET	FF	1	R48C36[2][B]	Mdu/u_mdu/m55_2_03_1_0_cZ/I3
6.663	0.453	tINS	FF	1	R48C36[2][B]	Mdu/u_mdu/m55_2_03_1_0_cZ/F
7.318	0.656	tNET	FF	1	R53C36[3][A]	Mdu/u_mdu/m55_4_03_1_0_1_cZ/I2
7.689	0.371	tINS	FF	1	R53C36[3][A]	Mdu/u_mdu/m55_4_03_1_0_1_cZ/F
8.086	0.397	tNET	FF	1	R53C34[1][B]	Mdu/u_mdu/m55_4_03_1_0_cZ/I3
8.457	0.371	tINS	FF	1	R53C34[1][B]	Mdu/u_mdu/m55_4_03_1_0_cZ/F
9.218	0.761	tNET	FF	1	R43C36[2][A]	Mdu/u_mdu/reg0_exe_nx_m0_cZ[55]/I2
9.735	0.517	tINS	FF	1	R43C36[2][A]	Mdu/u_mdu/reg0_exe_nx_m0_cZ[55]/F
9.735	0.000	tNET	FF	1	R43C36[2][A]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[55]/I0
9.838	0.103	tINS	FF	1	R43C36[2][A]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[55]/O
10.743	0.904	tNET	FF	1	R40C39[2][B]	Mdu/u_mdu/reg0_nx_cZ[55]/I0
11.313	0.570	tINS	FR	1	R40C39[2][B]	Mdu/u_mdu/reg0_nx_cZ[55]/F
11.313	0.000	tNET	RR	1	R40C39[2][B]	Mdu/u_mdu/reg0_Z[55]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	498	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R40C39[2][B]	Mdu/u_mdu/reg0_Z[55]/CLK
11.683	-0.200	tUnc				Mdu/u_mdu/reg0_Z[55]
11.648	-0.035	tSu		1	R40C39[2][B]	Mdu/u_mdu/reg0_Z[55]

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	8
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 3.273, 34.711%; route: 5.924, 62.829%; tC2Q: 0.232, 2.460%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path5

Path Summary:

Slack	0.406
Data Arrival Time	11.242
Data Required Time	11.648
From	Mdu/u_mdu/div_shift_number_Z[0]
To	Mdu/u_mdu/reg0_Z[31]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.683	0.683	tINS	RR	498	IOT48[A]	clk_ibuf/O
1.883	1.201	tNET	RR	1	R51C37[1][A]	Mdu/u_mdu/div_shift_number_Z[0]/CLK
2.115	0.232	tC2Q	RF	113	R51C37[1][A]	Mdu/u_mdu/div_shift_number_Z[0]/Q
3.444	1.329	tNET	FF	1	R41C34[2][A]	Mdu/u_mdu/m3_0_03_0_0_cZ/I0
3.961	0.517	tINS	FF	5	R41C34[2][A]	Mdu/u_mdu/m3_0_03_0_0_cZ/F
4.635	0.673	tNET	FF	1	R44C32[2][A]	Mdu/u_mdu/m3_0_03_0_0_RNIV0NN/I0
5.006	0.371	tINS	FF	3	R44C32[2][A]	Mdu/u_mdu/m3_0_03_0_0_RNIV0NN/F
5.700	0.694	tNET	FF	1	R51C33[2][B]	Mdu/u_mdu/m15_2_03_0_0_cZ/I0
6.071	0.371	tINS	FF	2	R51C33[2][B]	Mdu/u_mdu/m15_2_03_0_0_cZ/F
6.760	0.688	tNET	FF	1	R51C38[3][B]	Mdu/u_mdu/m15_2_03_0_0_RNI9I0C/I0
7.277	0.517	tINS	FF	3	R51C38[3][B]	Mdu/u_mdu/m15_2_03_0_0_RNI9I0C/F
8.135	0.859	tNET	FF	1	R44C35[0][A]	Mdu/u_mdu/m31_4_01_cZ/I1
8.506	0.371	tINS	FF	1	R44C35[0][A]	Mdu/u_mdu/m31_4_01_cZ/F
9.146	0.640	tNET	FF	1	R40C35[3][A]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[31]/I2
9.716	0.570	tINS	FR	1	R40C35[3][A]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[31]/F
9.717	0.001	tNET	RR	1	R40C35[2][B]	Mdu/u_mdu/reg0_exe_nx_cZ[31]/I3
10.170	0.453	tINS	RF	3	R40C35[2][B]	Mdu/u_mdu/reg0_exe_nx_cZ[31]/F
10.693	0.522	tNET	FF	1	R32C36[2][B]	Mdu/u_mdu/reg0_nx_cZ[31]/I0
11.242	0.549	tINS	FR	1	R32C36[2][B]	Mdu/u_mdu/reg0_nx_cZ[31]/F
11.242	0.000	tNET	RR	1	R32C36[2][B]	Mdu/u_mdu/reg0_Z[31]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	498	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R32C36[2][B]	Mdu/u_mdu/reg0_Z[31]/CLK
11.683	-0.200	tUnc				Mdu/u_mdu/reg0_Z[31]
11.648	-0.035	tSu		1	R32C36[2][B]	Mdu/u_mdu/reg0_Z[31]

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	8
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 3.719, 39.739%; route: 5.408, 57.782%; tC2Q: 0.232, 2.479%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path6

Path Summary:

Slack	0.723
Data Arrival Time	10.925
Data Required Time	11.648
From	Mdu/u_mdu/reg1_Z[30]
To	Mdu/u_mdu/div_shift_number_Z[5]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.683	0.683	tINS	RR	498	IOT48[A]	clk_ibuf/O
1.883	1.201	tNET	RR	1	R39C40[0][A]	Mdu/u_mdu/reg1_Z[30]/CLK
2.115	0.232	tC2Q	RF	8	R39C40[0][A]	Mdu/u_mdu/reg1_Z[30]/Q
3.210	1.094	tNET	FF	1	R38C33[3][A]	Mdu/u_mdu/un5_op1_eq_zero_nx_15_cZ_cZ/I3
3.727	0.517	tINS	FF	2	R38C33[3][A]	Mdu/u_mdu/un5_op1_eq_zero_nx_15_cZ_cZ/F
4.541	0.815	tNET	FF	1	R39C30[1][A]	Mdu/u_mdu/un5_op1_eq_zero_nx_21_cZ_cZ/S0
4.810	0.269	tINS	FR	1	R39C30[1][A]	Mdu/u_mdu/un5_op1_eq_zero_nx_21_cZ_cZ/O
4.989	0.178	tNET	RR	1	R38C30[2][A]	Mdu/u_mdu/un5_op1_eq_zero_nx_cZ_cZ/I0
5.544	0.555	tINS	RF	9	R38C30[2][A]	Mdu/u_mdu/un5_op1_eq_zero_nx_cZ_cZ/F
5.988	0.444	tNET	FF	1	R37C31[1][A]	Mdu/u_mdu/op1_lead_zero_detect_8_v[1]_i_m_cZ/I3
6.543	0.555	tINS	FF	3	R37C31[1][A]	Mdu/u_mdu/op1_lead_zero_detect_8_v[1]_i_m_cZ/F
6.960	0.418	tNET	FF	1	R39C32[3][A]	Mdu/u_mdu/un2_div_shift_number_nx_0_cry_3_0_0_RNO_cZ_cZ/I0
7.515	0.555	tINS	FF	1	R39C32[3][A]	Mdu/u_mdu/un2_div_shift_number_nx_0_cry_3_0_0_RNO_cZ_cZ/F
8.725	1.210	tNET	FF	2	R51C37[2][B]	Mdu/u_mdu/un2_div_shift_number_nx_0_cry_3_0_0/I0
9.295	0.570	tINS	FR	1	R51C37[2][B]	Mdu/u_mdu/un2_div_shift_number_nx_0_cry_3_0_0/COUT
9.295	0.000	tNET	RR	2	R51C38[0][A]	Mdu/u_mdu/un2_div_shift_number_nx_0_cry_4_0/CIN
9.330	0.035	tINS	RF	1	R51C38[0][A]	Mdu/u_mdu/un2_div_shift_number_nx_0_cry_4_0/COUT
9.330	0.000	tNET	FF	2	R51C38[0][B]	Mdu/u_mdu/un2_div_shift_number_nx_0_s_5_0/CIN
9.800	0.470	tINS	FF	1	R51C38[0][B]	Mdu/u_mdu/un2_div_shift_number_nx_0_s_5_0/SUM
10.925	1.125	tNET	FF	1	R51C38[1][A]	Mdu/u_mdu/div_shift_number_Z[5]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	498	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R51C38[1][A]	Mdu/u_mdu/div_shift_number_Z[5]/CLK
11.683	-0.200	tUnc				Mdu/u_mdu/div_shift_number_Z[5]
11.648	-0.035	tSu		1	R51C38[1][A]	Mdu/u_mdu/div_shift_number_Z[5]

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 3.526, 38.997%; route: 5.284, 58.437%; tC2Q: 0.232, 2.566%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path7

Path Summary:

Slack	0.747
Data Arrival Time	10.901
Data Required Time	11.648
From	Mdu/u_mdu/div_shift_number_Z[1]
To	Mdu/u_mdu/reg0_Z[63]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.683	0.683	tINS	RR	498	IOT48[A]	clk_ibuf/O
1.883	1.201	tNET	RR	1	R51C37[1][B]	Mdu/u_mdu/div_shift_number_Z[1]/CLK
2.115	0.232	tC2Q	RF	114	R51C37[1][B]	Mdu/u_mdu/div_shift_number_Z[1]/Q
4.249	2.133	tNET	FF	1	R34C40[2][B]	Mdu/u_mdu/m55_0_03_1_cZ/I1
4.620	0.371	tINS	FF	1	R34C40[2][B]	Mdu/u_mdu/m55_0_03_1_cZ/F
4.624	0.004	tNET	FF	1	R34C40[3][A]	Mdu/u_mdu/m55_0_03_cZ/I1
5.141	0.517	tINS	FF	3	R34C40[3][A]	Mdu/u_mdu/m55_0_03_cZ/F
6.105	0.964	tNET	FF	1	R48C39[1][B]	Mdu/u_mdu/m63_2_03_0_0_cZ/I3
6.476	0.371	tINS	FF	1	R48C39[1][B]	Mdu/u_mdu/m63_2_03_0_0_cZ/F
7.402	0.927	tNET	FF	1	R35C39[1][A]	Mdu/u_mdu/m63_2_03_cZ/I1
7.957	0.555	tINS	FF	1	R35C39[1][A]	Mdu/u_mdu/m63_2_03_cZ/F
8.642	0.684	tNET	FF	1	R44C37[0][A]	Mdu/u_mdu/m63_4_03_1_0_cZ/I3
9.095	0.453	tINS	FF	1	R44C37[0][A]	Mdu/u_mdu/m63_4_03_1_0_cZ/F
9.491	0.397	tNET	FF	1	R46C37[2][A]	Mdu/u_mdu/reg0_exe_nx_m0_cZ[63]/I2
10.008	0.517	tINS	FF	1	R46C37[2][A]	Mdu/u_mdu/reg0_exe_nx_m0_cZ[63]/F
10.008	0.000	tNET	FF	1	R46C37[2][A]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[63]/I0
10.111	0.103	tINS	FF	1	R46C37[2][A]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[63]/O
10.530	0.419	tNET	FF	1	R46C34[1][B]	Mdu/u_mdu/reg0_nx_0[63]/I2
10.901	0.371	tINS	FF	1	R46C34[1][B]	Mdu/u_mdu/reg0_nx_0[63]/F
10.901	0.000	tNET	FF	1	R46C34[1][B]	Mdu/u_mdu/reg0_Z[63]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	498	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R46C34[1][B]	Mdu/u_mdu/reg0_Z[63]/CLK
11.683	-0.200	tUnc				Mdu/u_mdu/reg0_Z[63]
11.648	-0.035	tSu		1	R46C34[1][B]	Mdu/u_mdu/reg0_Z[63]

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	8
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 3.258, 36.127%; route: 5.528, 61.301%; tC2Q: 0.232, 2.573%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path8

Path Summary:

Slack	0.752
Data Arrival Time	10.897
Data Required Time	11.648
From	Mdu/u_mdu/div_shift_number_Z[1]
To	Mdu/u_mdu/reg0_Z[64]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.683	0.683	tINS	RR	498	IOT48[A]	clk_ibuf/O
1.883	1.201	tNET	RR	1	R51C37[1][B]	Mdu/u_mdu/div_shift_number_Z[1]/CLK
2.115	0.232	tC2Q	RF	114	R51C37[1][B]	Mdu/u_mdu/div_shift_number_Z[1]/Q
3.704	1.588	tNET	FF	1	R41C38[2][B]	Mdu/u_mdu/m4_0_03_0_0_cZ/I1
4.166	0.462	tINS	FR	2	R41C38[2][B]	Mdu/u_mdu/m4_0_03_0_0_cZ/F
4.341	0.176	tNET	RR	1	R42C38[3][B]	Mdu/u_mdu/m4_0_03_0_0_RNI1JV1/I0
4.858	0.517	tINS	RF	3	R42C38[3][B]	Mdu/u_mdu/m4_0_03_0_0_RNI1JV1/F
5.656	0.798	tNET	FF	1	R50C32[3][A]	Mdu/u_mdu/m16_2_03_0_0_cZ/I0
6.109	0.453	tINS	FF	4	R50C32[3][A]	Mdu/u_mdu/m16_2_03_0_0_cZ/F
6.775	0.666	tNET	FF	1	R47C34[1][B]	Mdu/u_mdu/m64_4_03_0_0_RNO/I0
7.324	0.549	tINS	FR	1	R47C34[1][B]	Mdu/u_mdu/m64_4_03_0_0_RNO/F
7.325	0.001	tNET	RR	1	R47C34[2][B]	Mdu/u_mdu/m64_4_03_0_0_cZ/I0
7.880	0.555	tINS	RF	1	R47C34[2][B]	Mdu/u_mdu/m64_4_03_0_0_cZ/F
9.106	1.226	tNET	FF	1	R34C39[1][B]	Mdu/u_mdu/m64_4_03_cZ/I2
9.559	0.453	tINS	FF	1	R34C39[1][B]	Mdu/u_mdu/m64_4_03_cZ/F
9.972	0.413	tNET	FF	1	R31C39[3][B]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[64]/I3
10.343	0.371	tINS	FF	1	R31C39[3][B]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[64]/F
10.348	0.004	tNET	FF	1	R31C39[2][A]	Mdu/u_mdu/reg0_nx_cZ[64]/I0
10.897	0.549	tINS	FR	1	R31C39[2][A]	Mdu/u_mdu/reg0_nx_cZ[64]/F
10.897	0.000	tNET	RR	1	R31C39[2][A]	Mdu/u_mdu/reg0_Z[64]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	498	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R31C39[2][A]	Mdu/u_mdu/reg0_Z[64]/CLK
11.683	-0.200	tUnc				Mdu/u_mdu/reg0_Z[64]
11.648	-0.035	tSu		1	R31C39[2][A]	Mdu/u_mdu/reg0_Z[64]

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	8
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 3.909, 43.368%; route: 4.872, 54.058%; tC2Q: 0.232, 2.574%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path9

Path Summary:

Slack	0.900
Data Arrival Time	10.748
Data Required Time	11.648
From	Mdu/u_mdu/div_shift_number_Z[1]
To	Mdu/u_mdu/reg0_Z[59]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.683	0.683	tINS	RR	498	IOT48[A]	clk_ibuf/O
1.883	1.201	tNET	RR	1	R51C37[1][B]	Mdu/u_mdu/div_shift_number_Z[1]/CLK
2.115	0.232	tC2Q	RF	114	R51C37[1][B]	Mdu/u_mdu/div_shift_number_Z[1]/Q
4.460	2.345	tNET	FF	1	R35C41[0][B]	Mdu/u_mdu/m59_0_03_1_0_cZ/I1
5.015	0.555	tINS	FF	2	R35C41[0][B]	Mdu/u_mdu/m59_0_03_1_0_cZ/F
5.437	0.422	tNET	FF	1	R37C40[0][A]	Mdu/u_mdu/m59_2_03_1_0_RNO/I1
5.899	0.462	tINS	FR	1	R37C40[0][A]	Mdu/u_mdu/m59_2_03_1_0_RNO/F
6.072	0.172	tNET	RR	1	R38C40[3][B]	Mdu/u_mdu/m59_2_03_1_0_cZ/I3
6.443	0.371	tINS	RF	1	R38C40[3][B]	Mdu/u_mdu/m59_2_03_1_0_cZ/F
7.474	1.032	tNET	FF	1	R52C38[2][A]	Mdu/u_mdu/m59_4_03_1_0_RNO/I1
7.991	0.517	tINS	FF	1	R52C38[2][A]	Mdu/u_mdu/m59_4_03_1_0_RNO/F
8.238	0.247	tNET	FF	1	R52C36[1][A]	Mdu/u_mdu/m59_4_03_1_0_cZ/I3
8.691	0.453	tINS	FF	1	R52C36[1][A]	Mdu/u_mdu/m59_4_03_1_0_cZ/F
9.209	0.518	tNET	FF	1	R46C36[0][A]	Mdu/u_mdu/reg0_exe_nx_m0_cZ[59]/I2
9.764	0.555	tINS	FF	1	R46C36[0][A]	Mdu/u_mdu/reg0_exe_nx_m0_cZ[59]/F
9.764	0.000	tNET	FF	1	R46C36[0][A]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[59]/I0
9.867	0.103	tINS	FF	1	R46C36[0][A]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[59]/O
10.286	0.419	tNET	FF	1	R44C37[2][B]	Mdu/u_mdu/reg0_nx_0[59]/I2
10.748	0.462	tINS	FR	1	R44C37[2][B]	Mdu/u_mdu/reg0_nx_0[59]/F
10.748	0.000	tNET	RR	1	R44C37[2][B]	Mdu/u_mdu/reg0_Z[59]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	498	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R44C37[2][B]	Mdu/u_mdu/reg0_Z[59]/CLK
11.683	-0.200	tUnc				Mdu/u_mdu/reg0_Z[59]
11.648	-0.035	tSu		1	R44C37[2][B]	Mdu/u_mdu/reg0_Z[59]

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	8
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 3.478, 39.232%; route: 5.155, 58.151%; tC2Q: 0.232, 2.617%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path10

Path Summary:

Slack	0.915
Data Arrival Time	10.733
Data Required Time	11.648
From	Mdu/u_mdu/reg1_Z[0]
To	Mdu/u_mdu/reg0_Z[36]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.683	0.683	tINS	RR	498	IOT48[A]	clk_ibuf/O
1.883	1.201	tNET	RR	1	R37C38[0][B]	Mdu/u_mdu/reg1_Z[0]/CLK
2.115	0.232	tC2Q	RF	6	R37C38[0][B]	Mdu/u_mdu/reg1_Z[0]/Q
3.057	0.942	tNET	FF	1	R40C32[3][B]	Mdu/u_mdu/adder_sum_s_0_sf_lofx_cZ/I1
3.428	0.371	tINS	FF	1	R40C32[3][B]	Mdu/u_mdu/adder_sum_s_0_sf_lofx_cZ/F
3.841	0.413	tNET	FF	2	R42C32[1][A]	Mdu/u_mdu/adder_sum_cry_0_0/I0
4.411	0.570	tINS	FR	1	R42C32[1][A]	Mdu/u_mdu/adder_sum_cry_0_0/COUT
4.411	0.000	tNET	RR	2	R42C32[1][B]	Mdu/u_mdu/adder_sum_cry_1_0/CIN
4.447	0.035	tINS	RF	1	R42C32[1][B]	Mdu/u_mdu/adder_sum_cry_1_0/COUT
4.447	0.000	tNET	FF	2	R42C32[2][A]	Mdu/u_mdu/adder_sum_cry_2_0/CIN
4.482	0.035	tINS	FF	1	R42C32[2][A]	Mdu/u_mdu/adder_sum_cry_2_0/COUT
4.482	0.000	tNET	FF	2	R42C32[2][B]	Mdu/u_mdu/adder_sum_cry_3_0/CIN
4.517	0.035	tINS	FF	1	R42C32[2][B]	Mdu/u_mdu/adder_sum_cry_3_0/COUT
4.517	0.000	tNET	FF	2	R42C33[0][A]	Mdu/u_mdu/adder_sum_cry_4_0/CIN
4.552	0.035	tINS	FF	1	R42C33[0][A]	Mdu/u_mdu/adder_sum_cry_4_0/COUT
4.552	0.000	tNET	FF	2	R42C33[0][B]	Mdu/u_mdu/adder_sum_cry_5_0/CIN
4.587	0.035	tINS	FF	1	R42C33[0][B]	Mdu/u_mdu/adder_sum_cry_5_0/COUT
4.587	0.000	tNET	FF	2	R42C33[1][A]	Mdu/u_mdu/adder_sum_cry_6_0/CIN
4.623	0.035	tINS	FF	1	R42C33[1][A]	Mdu/u_mdu/adder_sum_cry_6_0/COUT
4.623	0.000	tNET	FF	2	R42C33[1][B]	Mdu/u_mdu/adder_sum_cry_7_0/CIN
4.658	0.035	tINS	FF	1	R42C33[1][B]	Mdu/u_mdu/adder_sum_cry_7_0/COUT
4.658	0.000	tNET	FF	2	R42C33[2][A]	Mdu/u_mdu/adder_sum_cry_8_0/CIN
4.693	0.035	tINS	FF	1	R42C33[2][A]	Mdu/u_mdu/adder_sum_cry_8_0/COUT
4.693	0.000	tNET	FF	2	R42C33[2][B]	Mdu/u_mdu/adder_sum_cry_9_0/CIN
4.728	0.035	tINS	FF	1	R42C33[2][B]	Mdu/u_mdu/adder_sum_cry_9_0/COUT
4.728	0.000	tNET	FF	2	R42C34[0][A]	Mdu/u_mdu/adder_sum_cry_10_0/CIN
4.763	0.035	tINS	FF	1	R42C34[0][A]	Mdu/u_mdu/adder_sum_cry_10_0/COUT
4.763	0.000	tNET	FF	2	R42C34[0][B]	Mdu/u_mdu/adder_sum_cry_11_0/CIN
4.799	0.035	tINS	FF	1	R42C34[0][B]	Mdu/u_mdu/adder_sum_cry_11_0/COUT
4.799	0.000	tNET	FF	2	R42C34[1][A]	Mdu/u_mdu/adder_sum_cry_12_0/CIN
4.834	0.035	tINS	FF	1	R42C34[1][A]	Mdu/u_mdu/adder_sum_cry_12_0/COUT
4.834	0.000	tNET	FF	2	R42C34[1][B]	Mdu/u_mdu/adder_sum_cry_13_0/CIN
4.869	0.035	tINS	FF	1	R42C34[1][B]	Mdu/u_mdu/adder_sum_cry_13_0/COUT
4.869	0.000	tNET	FF	2	R42C34[2][A]	Mdu/u_mdu/adder_sum_cry_14_0/CIN
4.904	0.035	tINS	FF	1	R42C34[2][A]	Mdu/u_mdu/adder_sum_cry_14_0/COUT
4.904	0.000	tNET	FF	2	R42C34[2][B]	Mdu/u_mdu/adder_sum_cry_15_0/CIN
4.939	0.035	tINS	FF	1	R42C34[2][B]	Mdu/u_mdu/adder_sum_cry_15_0/COUT
4.939	0.000	tNET	FF	2	R42C35[0][A]	Mdu/u_mdu/adder_sum_cry_16_0/CIN
4.975	0.035	tINS	FF	1	R42C35[0][A]	Mdu/u_mdu/adder_sum_cry_16_0/COUT
4.975	0.000	tNET	FF	2	R42C35[0][B]	Mdu/u_mdu/adder_sum_cry_17_0/CIN
5.010	0.035	tINS	FF	1	R42C35[0][B]	Mdu/u_mdu/adder_sum_cry_17_0/COUT
5.010	0.000	tNET	FF	2	R42C35[1][A]	Mdu/u_mdu/adder_sum_cry_18_0/CIN
5.045	0.035	tINS	FF	1	R42C35[1][A]	Mdu/u_mdu/adder_sum_cry_18_0/COUT
5.045	0.000	tNET	FF	2	R42C35[1][B]	Mdu/u_mdu/adder_sum_cry_19_0/CIN
5.080	0.035	tINS	FF	1	R42C35[1][B]	Mdu/u_mdu/adder_sum_cry_19_0/COUT
5.080	0.000	tNET	FF	2	R42C35[2][A]	Mdu/u_mdu/adder_sum_cry_20_0/CIN
5.115	0.035	tINS	FF	1	R42C35[2][A]	Mdu/u_mdu/adder_sum_cry_20_0/COUT
5.115	0.000	tNET	FF	2	R42C35[2][B]	Mdu/u_mdu/adder_sum_cry_21_0/CIN
5.151	0.035	tINS	FF	1	R42C35[2][B]	Mdu/u_mdu/adder_sum_cry_21_0/COUT
5.151	0.000	tNET	FF	2	R42C36[0][A]	Mdu/u_mdu/adder_sum_cry_22_0/CIN
5.186	0.035	tINS	FF	1	R42C36[0][A]	Mdu/u_mdu/adder_sum_cry_22_0/COUT
5.186	0.000	tNET	FF	2	R42C36[0][B]	Mdu/u_mdu/adder_sum_cry_23_0/CIN
5.221	0.035	tINS	FF	1	R42C36[0][B]	Mdu/u_mdu/adder_sum_cry_23_0/COUT
5.221	0.000	tNET	FF	2	R42C36[1][A]	Mdu/u_mdu/adder_sum_cry_24_0/CIN
5.256	0.035	tINS	FF	1	R42C36[1][A]	Mdu/u_mdu/adder_sum_cry_24_0/COUT
5.256	0.000	tNET	FF	2	R42C36[1][B]	Mdu/u_mdu/adder_sum_cry_25_0/CIN
5.291	0.035	tINS	FF	1	R42C36[1][B]	Mdu/u_mdu/adder_sum_cry_25_0/COUT
5.291	0.000	tNET	FF	2	R42C36[2][A]	Mdu/u_mdu/adder_sum_cry_26_0/CIN
5.327	0.035	tINS	FF	1	R42C36[2][A]	Mdu/u_mdu/adder_sum_cry_26_0/COUT
5.327	0.000	tNET	FF	2	R42C36[2][B]	Mdu/u_mdu/adder_sum_cry_27_0/CIN
5.362	0.035	tINS	FF	1	R42C36[2][B]	Mdu/u_mdu/adder_sum_cry_27_0/COUT
5.362	0.000	tNET	FF	2	R42C37[0][A]	Mdu/u_mdu/adder_sum_cry_28_0/CIN
5.397	0.035	tINS	FF	1	R42C37[0][A]	Mdu/u_mdu/adder_sum_cry_28_0/COUT
5.397	0.000	tNET	FF	2	R42C37[0][B]	Mdu/u_mdu/adder_sum_cry_29_0/CIN
5.432	0.035	tINS	FF	1	R42C37[0][B]	Mdu/u_mdu/adder_sum_cry_29_0/COUT
5.432	0.000	tNET	FF	2	R42C37[1][A]	Mdu/u_mdu/adder_sum_cry_30_0/CIN
5.467	0.035	tINS	FF	1	R42C37[1][A]	Mdu/u_mdu/adder_sum_cry_30_0/COUT
5.467	0.000	tNET	FF	2	R42C37[1][B]	Mdu/u_mdu/adder_sum_cry_31_0/CIN
5.503	0.035	tINS	FF	1	R42C37[1][B]	Mdu/u_mdu/adder_sum_cry_31_0/COUT
5.503	0.000	tNET	FF	2	R42C37[2][A]	Mdu/u_mdu/adder_sum_s_32_0/CIN
5.973	0.470	tINS	FF	6	R42C37[2][A]	Mdu/u_mdu/adder_sum_s_32_0/SUM
6.941	0.968	tNET	FF	1	R35C31[1][A]	Mdu/u_mdu/reg0_exe_nx_ss0_cZ/I0
7.312	0.371	tINS	FF	50	R35C31[1][A]	Mdu/u_mdu/reg0_exe_nx_ss0_cZ/F
8.298	0.986	tNET	FF	1	R48C31[2][A]	Mdu/u_mdu/reg0_exe_nx_m0_cZ[36]/I2
8.815	0.517	tINS	FF	1	R48C31[2][A]	Mdu/u_mdu/reg0_exe_nx_m0_cZ[36]/F
8.815	0.000	tNET	FF	1	R48C31[2][A]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[36]/I0
8.918	0.103	tINS	FF	1	R48C31[2][A]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[36]/O
10.271	1.353	tNET	FF	1	R48C34[0][A]	Mdu/u_mdu/reg0_nx_0[36]/I2
10.733	0.462	tINS	FR	1	R48C34[0][A]	Mdu/u_mdu/reg0_nx_0[36]/F
10.733	0.000	tNET	RR	1	R48C34[0][A]	Mdu/u_mdu/reg0_Z[36]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	498	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R48C34[0][A]	Mdu/u_mdu/reg0_Z[36]/CLK
11.683	-0.200	tUnc				Mdu/u_mdu/reg0_Z[36]
11.648	-0.035	tSu		1	R48C34[0][A]	Mdu/u_mdu/reg0_Z[36]

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 3.955, 44.693%; route: 4.663, 52.686%; tC2Q: 0.232, 2.622%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path11

Path Summary:

Slack	0.967
Data Arrival Time	10.681
Data Required Time	11.648
From	Mdu/u_mdu/reg1_Z[0]
To	Mdu/u_mdu/reg0_Z[41]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.683	0.683	tINS	RR	498	IOT48[A]	clk_ibuf/O
1.883	1.201	tNET	RR	1	R37C38[0][B]	Mdu/u_mdu/reg1_Z[0]/CLK
2.115	0.232	tC2Q	RF	6	R37C38[0][B]	Mdu/u_mdu/reg1_Z[0]/Q
3.057	0.942	tNET	FF	1	R40C32[3][B]	Mdu/u_mdu/adder_sum_s_0_sf_lofx_cZ/I1
3.428	0.371	tINS	FF	1	R40C32[3][B]	Mdu/u_mdu/adder_sum_s_0_sf_lofx_cZ/F
3.841	0.413	tNET	FF	2	R42C32[1][A]	Mdu/u_mdu/adder_sum_cry_0_0/I0
4.411	0.570	tINS	FR	1	R42C32[1][A]	Mdu/u_mdu/adder_sum_cry_0_0/COUT
4.411	0.000	tNET	RR	2	R42C32[1][B]	Mdu/u_mdu/adder_sum_cry_1_0/CIN
4.447	0.035	tINS	RF	1	R42C32[1][B]	Mdu/u_mdu/adder_sum_cry_1_0/COUT
4.447	0.000	tNET	FF	2	R42C32[2][A]	Mdu/u_mdu/adder_sum_cry_2_0/CIN
4.482	0.035	tINS	FF	1	R42C32[2][A]	Mdu/u_mdu/adder_sum_cry_2_0/COUT
4.482	0.000	tNET	FF	2	R42C32[2][B]	Mdu/u_mdu/adder_sum_cry_3_0/CIN
4.517	0.035	tINS	FF	1	R42C32[2][B]	Mdu/u_mdu/adder_sum_cry_3_0/COUT
4.517	0.000	tNET	FF	2	R42C33[0][A]	Mdu/u_mdu/adder_sum_cry_4_0/CIN
4.552	0.035	tINS	FF	1	R42C33[0][A]	Mdu/u_mdu/adder_sum_cry_4_0/COUT
4.552	0.000	tNET	FF	2	R42C33[0][B]	Mdu/u_mdu/adder_sum_cry_5_0/CIN
4.587	0.035	tINS	FF	1	R42C33[0][B]	Mdu/u_mdu/adder_sum_cry_5_0/COUT
4.587	0.000	tNET	FF	2	R42C33[1][A]	Mdu/u_mdu/adder_sum_cry_6_0/CIN
4.623	0.035	tINS	FF	1	R42C33[1][A]	Mdu/u_mdu/adder_sum_cry_6_0/COUT
4.623	0.000	tNET	FF	2	R42C33[1][B]	Mdu/u_mdu/adder_sum_cry_7_0/CIN
4.658	0.035	tINS	FF	1	R42C33[1][B]	Mdu/u_mdu/adder_sum_cry_7_0/COUT
4.658	0.000	tNET	FF	2	R42C33[2][A]	Mdu/u_mdu/adder_sum_cry_8_0/CIN
4.693	0.035	tINS	FF	1	R42C33[2][A]	Mdu/u_mdu/adder_sum_cry_8_0/COUT
4.693	0.000	tNET	FF	2	R42C33[2][B]	Mdu/u_mdu/adder_sum_cry_9_0/CIN
4.728	0.035	tINS	FF	1	R42C33[2][B]	Mdu/u_mdu/adder_sum_cry_9_0/COUT
4.728	0.000	tNET	FF	2	R42C34[0][A]	Mdu/u_mdu/adder_sum_cry_10_0/CIN
4.763	0.035	tINS	FF	1	R42C34[0][A]	Mdu/u_mdu/adder_sum_cry_10_0/COUT
4.763	0.000	tNET	FF	2	R42C34[0][B]	Mdu/u_mdu/adder_sum_cry_11_0/CIN
4.799	0.035	tINS	FF	1	R42C34[0][B]	Mdu/u_mdu/adder_sum_cry_11_0/COUT
4.799	0.000	tNET	FF	2	R42C34[1][A]	Mdu/u_mdu/adder_sum_cry_12_0/CIN
4.834	0.035	tINS	FF	1	R42C34[1][A]	Mdu/u_mdu/adder_sum_cry_12_0/COUT
4.834	0.000	tNET	FF	2	R42C34[1][B]	Mdu/u_mdu/adder_sum_cry_13_0/CIN
4.869	0.035	tINS	FF	1	R42C34[1][B]	Mdu/u_mdu/adder_sum_cry_13_0/COUT
4.869	0.000	tNET	FF	2	R42C34[2][A]	Mdu/u_mdu/adder_sum_cry_14_0/CIN
4.904	0.035	tINS	FF	1	R42C34[2][A]	Mdu/u_mdu/adder_sum_cry_14_0/COUT
4.904	0.000	tNET	FF	2	R42C34[2][B]	Mdu/u_mdu/adder_sum_cry_15_0/CIN
4.939	0.035	tINS	FF	1	R42C34[2][B]	Mdu/u_mdu/adder_sum_cry_15_0/COUT
4.939	0.000	tNET	FF	2	R42C35[0][A]	Mdu/u_mdu/adder_sum_cry_16_0/CIN
4.975	0.035	tINS	FF	1	R42C35[0][A]	Mdu/u_mdu/adder_sum_cry_16_0/COUT
4.975	0.000	tNET	FF	2	R42C35[0][B]	Mdu/u_mdu/adder_sum_cry_17_0/CIN
5.010	0.035	tINS	FF	1	R42C35[0][B]	Mdu/u_mdu/adder_sum_cry_17_0/COUT
5.010	0.000	tNET	FF	2	R42C35[1][A]	Mdu/u_mdu/adder_sum_cry_18_0/CIN
5.045	0.035	tINS	FF	1	R42C35[1][A]	Mdu/u_mdu/adder_sum_cry_18_0/COUT
5.045	0.000	tNET	FF	2	R42C35[1][B]	Mdu/u_mdu/adder_sum_cry_19_0/CIN
5.080	0.035	tINS	FF	1	R42C35[1][B]	Mdu/u_mdu/adder_sum_cry_19_0/COUT
5.080	0.000	tNET	FF	2	R42C35[2][A]	Mdu/u_mdu/adder_sum_cry_20_0/CIN
5.115	0.035	tINS	FF	1	R42C35[2][A]	Mdu/u_mdu/adder_sum_cry_20_0/COUT
5.115	0.000	tNET	FF	2	R42C35[2][B]	Mdu/u_mdu/adder_sum_cry_21_0/CIN
5.151	0.035	tINS	FF	1	R42C35[2][B]	Mdu/u_mdu/adder_sum_cry_21_0/COUT
5.151	0.000	tNET	FF	2	R42C36[0][A]	Mdu/u_mdu/adder_sum_cry_22_0/CIN
5.186	0.035	tINS	FF	1	R42C36[0][A]	Mdu/u_mdu/adder_sum_cry_22_0/COUT
5.186	0.000	tNET	FF	2	R42C36[0][B]	Mdu/u_mdu/adder_sum_cry_23_0/CIN
5.221	0.035	tINS	FF	1	R42C36[0][B]	Mdu/u_mdu/adder_sum_cry_23_0/COUT
5.221	0.000	tNET	FF	2	R42C36[1][A]	Mdu/u_mdu/adder_sum_cry_24_0/CIN
5.256	0.035	tINS	FF	1	R42C36[1][A]	Mdu/u_mdu/adder_sum_cry_24_0/COUT
5.256	0.000	tNET	FF	2	R42C36[1][B]	Mdu/u_mdu/adder_sum_cry_25_0/CIN
5.291	0.035	tINS	FF	1	R42C36[1][B]	Mdu/u_mdu/adder_sum_cry_25_0/COUT
5.291	0.000	tNET	FF	2	R42C36[2][A]	Mdu/u_mdu/adder_sum_cry_26_0/CIN
5.327	0.035	tINS	FF	1	R42C36[2][A]	Mdu/u_mdu/adder_sum_cry_26_0/COUT
5.327	0.000	tNET	FF	2	R42C36[2][B]	Mdu/u_mdu/adder_sum_cry_27_0/CIN
5.362	0.035	tINS	FF	1	R42C36[2][B]	Mdu/u_mdu/adder_sum_cry_27_0/COUT
5.362	0.000	tNET	FF	2	R42C37[0][A]	Mdu/u_mdu/adder_sum_cry_28_0/CIN
5.397	0.035	tINS	FF	1	R42C37[0][A]	Mdu/u_mdu/adder_sum_cry_28_0/COUT
5.397	0.000	tNET	FF	2	R42C37[0][B]	Mdu/u_mdu/adder_sum_cry_29_0/CIN
5.432	0.035	tINS	FF	1	R42C37[0][B]	Mdu/u_mdu/adder_sum_cry_29_0/COUT
5.432	0.000	tNET	FF	2	R42C37[1][A]	Mdu/u_mdu/adder_sum_cry_30_0/CIN
5.467	0.035	tINS	FF	1	R42C37[1][A]	Mdu/u_mdu/adder_sum_cry_30_0/COUT
5.467	0.000	tNET	FF	2	R42C37[1][B]	Mdu/u_mdu/adder_sum_cry_31_0/CIN
5.503	0.035	tINS	FF	1	R42C37[1][B]	Mdu/u_mdu/adder_sum_cry_31_0/COUT
5.503	0.000	tNET	FF	2	R42C37[2][A]	Mdu/u_mdu/adder_sum_s_32_0/CIN
5.973	0.470	tINS	FF	6	R42C37[2][A]	Mdu/u_mdu/adder_sum_s_32_0/SUM
6.941	0.968	tNET	FF	1	R35C31[1][A]	Mdu/u_mdu/reg0_exe_nx_ss0_cZ/I0
7.312	0.371	tINS	FF	50	R35C31[1][A]	Mdu/u_mdu/reg0_exe_nx_ss0_cZ/F
8.437	1.125	tNET	FF	1	R47C37[3][A]	Mdu/u_mdu/reg0_exe_nx_m0_cZ[41]/I2
8.954	0.517	tINS	FF	1	R47C37[3][A]	Mdu/u_mdu/reg0_exe_nx_m0_cZ[41]/F
8.954	0.000	tNET	FF	1	R47C37[3][A]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[41]/I0
9.057	0.103	tINS	FF	1	R47C37[3][A]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[41]/O
10.111	1.054	tNET	FF	1	R48C37[1][B]	Mdu/u_mdu/reg0_nx_cZ[41]/I0
10.681	0.570	tINS	FR	1	R48C37[1][B]	Mdu/u_mdu/reg0_nx_cZ[41]/F
10.681	0.000	tNET	RR	1	R48C37[1][B]	Mdu/u_mdu/reg0_Z[41]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	498	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R48C37[1][B]	Mdu/u_mdu/reg0_Z[41]/CLK
11.683	-0.200	tUnc				Mdu/u_mdu/reg0_Z[41]
11.648	-0.035	tSu		1	R48C37[1][B]	Mdu/u_mdu/reg0_Z[41]

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 4.063, 46.182%; route: 4.503, 51.181%; tC2Q: 0.232, 2.637%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path12

Path Summary:

Slack	0.998
Data Arrival Time	10.650
Data Required Time	11.648
From	Mdu/u_mdu/reg0_Z[8]
To	Mdu/u_mdu/reg0_Z[37]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.683	0.683	tINS	RR	498	IOT48[A]	clk_ibuf/O
1.883	1.201	tNET	RR	1	R33C36[0][B]	Mdu/u_mdu/reg0_Z[8]/CLK
2.115	0.232	tC2Q	RF	18	R33C36[0][B]	Mdu/u_mdu/reg0_Z[8]/Q
3.699	1.584	tNET	FF	1	R51C32[2][A]	Mdu/u_mdu/m9_0_03_1_0_cZ/I2
4.152	0.453	tINS	FF	3	R51C32[2][A]	Mdu/u_mdu/m9_0_03_1_0_cZ/F
4.565	0.413	tNET	FF	1	R51C30[3][A]	Mdu/u_mdu/m9_0_03_0_0_RNIBDAL/I1
5.120	0.555	tINS	FF	2	R51C30[3][A]	Mdu/u_mdu/m9_0_03_0_0_RNIBDAL/F
5.765	0.645	tNET	FF	1	R53C32[1][A]	Mdu/u_mdu/m21_2_03_0_0_cZ/I1
6.335	0.570	tINS	FR	2	R53C32[1][A]	Mdu/u_mdu/m21_2_03_0_0_cZ/F
6.511	0.176	tNET	RR	1	R53C33[2][B]	Mdu/u_mdu/m21_2_03_0_0_RNI3UOL/I0
7.028	0.517	tINS	RF	2	R53C33[2][B]	Mdu/u_mdu/m21_2_03_0_0_RNI3UOL/F
7.429	0.401	tNET	FF	1	R51C33[2][A]	Mdu/u_mdu/m37_4_03_0_0_cZ/I1
7.882	0.453	tINS	FF	1	R51C33[2][A]	Mdu/u_mdu/m37_4_03_0_0_cZ/F
8.781	0.899	tNET	FF	1	R48C33[3][B]	Mdu/u_mdu/reg0_exe_nx_m1_cZ[37]/I2
9.336	0.555	tINS	FF	1	R48C33[3][B]	Mdu/u_mdu/reg0_exe_nx_m1_cZ[37]/F
9.336	0.000	tNET	FF	1	R48C33[3][A]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[37]/I1
9.439	0.103	tINS	FF	1	R48C33[3][A]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[37]/O
10.279	0.840	tNET	FF	1	R48C38[1][A]	Mdu/u_mdu/reg0_nx_cZ[37]/I0
10.650	0.371	tINS	FF	1	R48C38[1][A]	Mdu/u_mdu/reg0_nx_cZ[37]/F
10.650	0.000	tNET	FF	1	R48C38[1][A]	Mdu/u_mdu/reg0_Z[37]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	498	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R48C38[1][A]	Mdu/u_mdu/reg0_Z[37]/CLK
11.683	-0.200	tUnc				Mdu/u_mdu/reg0_Z[37]
11.648	-0.035	tSu		1	R48C38[1][A]	Mdu/u_mdu/reg0_Z[37]

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	8
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 3.577, 40.802%; route: 4.958, 56.551%; tC2Q: 0.232, 2.646%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path13

Path Summary:

Slack	1.018
Data Arrival Time	10.630
Data Required Time	11.648
From	Mdu/u_mdu/div_shift_number_Z[1]
To	Mdu/u_mdu/reg0_fast_Z[20]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.683	0.683	tINS	RR	498	IOT48[A]	clk_ibuf/O
1.883	1.201	tNET	RR	1	R51C37[1][B]	Mdu/u_mdu/div_shift_number_Z[1]/CLK
2.115	0.232	tC2Q	RF	114	R51C37[1][B]	Mdu/u_mdu/div_shift_number_Z[1]/Q
3.704	1.588	tNET	FF	1	R41C38[2][B]	Mdu/u_mdu/m4_0_03_0_0_cZ/I1
4.166	0.462	tINS	FR	2	R41C38[2][B]	Mdu/u_mdu/m4_0_03_0_0_cZ/F
4.341	0.176	tNET	RR	1	R42C38[3][B]	Mdu/u_mdu/m4_0_03_0_0_RNI1JV1/I0
4.858	0.517	tINS	RF	3	R42C38[3][B]	Mdu/u_mdu/m4_0_03_0_0_RNI1JV1/F
5.745	0.887	tNET	FF	1	R51C31[2][B]	Mdu/u_mdu/m4_2_03_cZ/I3
6.315	0.570	tINS	FR	4	R51C31[2][B]	Mdu/u_mdu/m4_2_03_cZ/F
6.319	0.004	tNET	RR	1	R51C31[2][A]	Mdu/u_mdu/m20_4_01_cZ/I1
6.836	0.517	tINS	RF	1	R51C31[2][A]	Mdu/u_mdu/m20_4_01_cZ/F
8.046	1.210	tNET	FF	1	R37C35[3][B]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[20]/I2
8.595	0.549	tINS	FR	1	R37C35[3][B]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[20]/F
8.596	0.001	tNET	RR	1	R37C35[2][A]	Mdu/u_mdu/reg0_exe_nx_cZ[20]/I3
9.113	0.517	tINS	RF	2	R37C35[2][A]	Mdu/u_mdu/reg0_exe_nx_cZ[20]/F
10.060	0.947	tNET	FF	1	R41C32[2][B]	Mdu/u_mdu/reg0_nx_fast_cZ[20]/I0
10.630	0.570	tINS	FR	1	R41C32[2][B]	Mdu/u_mdu/reg0_nx_fast_cZ[20]/F
10.630	0.000	tNET	RR	1	R41C32[2][B]	Mdu/u_mdu/reg0_fast_Z[20]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	498	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R41C32[2][B]	Mdu/u_mdu/reg0_fast_Z[20]/CLK
11.683	-0.200	tUnc				Mdu/u_mdu/reg0_fast_Z[20]
11.648	-0.035	tSu		1	R41C32[2][B]	Mdu/u_mdu/reg0_fast_Z[20]

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 3.702, 42.325%; route: 4.813, 55.023%; tC2Q: 0.232, 2.652%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path14

Path Summary:

Slack	1.018
Data Arrival Time	10.630
Data Required Time	11.648
From	Mdu/u_mdu/div_shift_number_Z[1]
To	Mdu/u_mdu/reg0_Z[20]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.683	0.683	tINS	RR	498	IOT48[A]	clk_ibuf/O
1.883	1.201	tNET	RR	1	R51C37[1][B]	Mdu/u_mdu/div_shift_number_Z[1]/CLK
2.115	0.232	tC2Q	RF	114	R51C37[1][B]	Mdu/u_mdu/div_shift_number_Z[1]/Q
3.704	1.588	tNET	FF	1	R41C38[2][B]	Mdu/u_mdu/m4_0_03_0_0_cZ/I1
4.166	0.462	tINS	FR	2	R41C38[2][B]	Mdu/u_mdu/m4_0_03_0_0_cZ/F
4.341	0.176	tNET	RR	1	R42C38[3][B]	Mdu/u_mdu/m4_0_03_0_0_RNI1JV1/I0
4.858	0.517	tINS	RF	3	R42C38[3][B]	Mdu/u_mdu/m4_0_03_0_0_RNI1JV1/F
5.745	0.887	tNET	FF	1	R51C31[2][B]	Mdu/u_mdu/m4_2_03_cZ/I3
6.315	0.570	tINS	FR	4	R51C31[2][B]	Mdu/u_mdu/m4_2_03_cZ/F
6.319	0.004	tNET	RR	1	R51C31[2][A]	Mdu/u_mdu/m20_4_01_cZ/I1
6.836	0.517	tINS	RF	1	R51C31[2][A]	Mdu/u_mdu/m20_4_01_cZ/F
8.046	1.210	tNET	FF	1	R37C35[3][B]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[20]/I2
8.595	0.549	tINS	FR	1	R37C35[3][B]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[20]/F
8.596	0.001	tNET	RR	1	R37C35[2][A]	Mdu/u_mdu/reg0_exe_nx_cZ[20]/I3
9.113	0.517	tINS	RF	2	R37C35[2][A]	Mdu/u_mdu/reg0_exe_nx_cZ[20]/F
10.060	0.947	tNET	FF	1	R41C32[2][A]	Mdu/u_mdu/reg0_nx_cZ[20]/I0
10.630	0.570	tINS	FR	1	R41C32[2][A]	Mdu/u_mdu/reg0_nx_cZ[20]/F
10.630	0.000	tNET	RR	1	R41C32[2][A]	Mdu/u_mdu/reg0_Z[20]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	498	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R41C32[2][A]	Mdu/u_mdu/reg0_Z[20]/CLK
11.683	-0.200	tUnc				Mdu/u_mdu/reg0_Z[20]
11.648	-0.035	tSu		1	R41C32[2][A]	Mdu/u_mdu/reg0_Z[20]

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 3.702, 42.325%; route: 4.813, 55.023%; tC2Q: 0.232, 2.652%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path15

Path Summary:

Slack	1.037
Data Arrival Time	10.611
Data Required Time	11.648
From	Mdu/u_mdu/reg1_Z[0]
To	Mdu/u_mdu/reg0_Z[61]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.683	0.683	tINS	RR	498	IOT48[A]	clk_ibuf/O
1.883	1.201	tNET	RR	1	R37C38[0][B]	Mdu/u_mdu/reg1_Z[0]/CLK
2.115	0.232	tC2Q	RF	6	R37C38[0][B]	Mdu/u_mdu/reg1_Z[0]/Q
3.057	0.942	tNET	FF	1	R40C32[3][B]	Mdu/u_mdu/adder_sum_s_0_sf_lofx_cZ/I1
3.428	0.371	tINS	FF	1	R40C32[3][B]	Mdu/u_mdu/adder_sum_s_0_sf_lofx_cZ/F
3.841	0.413	tNET	FF	2	R42C32[1][A]	Mdu/u_mdu/adder_sum_cry_0_0/I0
4.411	0.570	tINS	FR	1	R42C32[1][A]	Mdu/u_mdu/adder_sum_cry_0_0/COUT
4.411	0.000	tNET	RR	2	R42C32[1][B]	Mdu/u_mdu/adder_sum_cry_1_0/CIN
4.447	0.035	tINS	RF	1	R42C32[1][B]	Mdu/u_mdu/adder_sum_cry_1_0/COUT
4.447	0.000	tNET	FF	2	R42C32[2][A]	Mdu/u_mdu/adder_sum_cry_2_0/CIN
4.482	0.035	tINS	FF	1	R42C32[2][A]	Mdu/u_mdu/adder_sum_cry_2_0/COUT
4.482	0.000	tNET	FF	2	R42C32[2][B]	Mdu/u_mdu/adder_sum_cry_3_0/CIN
4.517	0.035	tINS	FF	1	R42C32[2][B]	Mdu/u_mdu/adder_sum_cry_3_0/COUT
4.517	0.000	tNET	FF	2	R42C33[0][A]	Mdu/u_mdu/adder_sum_cry_4_0/CIN
4.552	0.035	tINS	FF	1	R42C33[0][A]	Mdu/u_mdu/adder_sum_cry_4_0/COUT
4.552	0.000	tNET	FF	2	R42C33[0][B]	Mdu/u_mdu/adder_sum_cry_5_0/CIN
4.587	0.035	tINS	FF	1	R42C33[0][B]	Mdu/u_mdu/adder_sum_cry_5_0/COUT
4.587	0.000	tNET	FF	2	R42C33[1][A]	Mdu/u_mdu/adder_sum_cry_6_0/CIN
4.623	0.035	tINS	FF	1	R42C33[1][A]	Mdu/u_mdu/adder_sum_cry_6_0/COUT
4.623	0.000	tNET	FF	2	R42C33[1][B]	Mdu/u_mdu/adder_sum_cry_7_0/CIN
4.658	0.035	tINS	FF	1	R42C33[1][B]	Mdu/u_mdu/adder_sum_cry_7_0/COUT
4.658	0.000	tNET	FF	2	R42C33[2][A]	Mdu/u_mdu/adder_sum_cry_8_0/CIN
4.693	0.035	tINS	FF	1	R42C33[2][A]	Mdu/u_mdu/adder_sum_cry_8_0/COUT
4.693	0.000	tNET	FF	2	R42C33[2][B]	Mdu/u_mdu/adder_sum_cry_9_0/CIN
4.728	0.035	tINS	FF	1	R42C33[2][B]	Mdu/u_mdu/adder_sum_cry_9_0/COUT
4.728	0.000	tNET	FF	2	R42C34[0][A]	Mdu/u_mdu/adder_sum_cry_10_0/CIN
4.763	0.035	tINS	FF	1	R42C34[0][A]	Mdu/u_mdu/adder_sum_cry_10_0/COUT
4.763	0.000	tNET	FF	2	R42C34[0][B]	Mdu/u_mdu/adder_sum_cry_11_0/CIN
4.799	0.035	tINS	FF	1	R42C34[0][B]	Mdu/u_mdu/adder_sum_cry_11_0/COUT
4.799	0.000	tNET	FF	2	R42C34[1][A]	Mdu/u_mdu/adder_sum_cry_12_0/CIN
4.834	0.035	tINS	FF	1	R42C34[1][A]	Mdu/u_mdu/adder_sum_cry_12_0/COUT
4.834	0.000	tNET	FF	2	R42C34[1][B]	Mdu/u_mdu/adder_sum_cry_13_0/CIN
4.869	0.035	tINS	FF	1	R42C34[1][B]	Mdu/u_mdu/adder_sum_cry_13_0/COUT
4.869	0.000	tNET	FF	2	R42C34[2][A]	Mdu/u_mdu/adder_sum_cry_14_0/CIN
4.904	0.035	tINS	FF	1	R42C34[2][A]	Mdu/u_mdu/adder_sum_cry_14_0/COUT
4.904	0.000	tNET	FF	2	R42C34[2][B]	Mdu/u_mdu/adder_sum_cry_15_0/CIN
4.939	0.035	tINS	FF	1	R42C34[2][B]	Mdu/u_mdu/adder_sum_cry_15_0/COUT
4.939	0.000	tNET	FF	2	R42C35[0][A]	Mdu/u_mdu/adder_sum_cry_16_0/CIN
4.975	0.035	tINS	FF	1	R42C35[0][A]	Mdu/u_mdu/adder_sum_cry_16_0/COUT
4.975	0.000	tNET	FF	2	R42C35[0][B]	Mdu/u_mdu/adder_sum_cry_17_0/CIN
5.010	0.035	tINS	FF	1	R42C35[0][B]	Mdu/u_mdu/adder_sum_cry_17_0/COUT
5.010	0.000	tNET	FF	2	R42C35[1][A]	Mdu/u_mdu/adder_sum_cry_18_0/CIN
5.045	0.035	tINS	FF	1	R42C35[1][A]	Mdu/u_mdu/adder_sum_cry_18_0/COUT
5.045	0.000	tNET	FF	2	R42C35[1][B]	Mdu/u_mdu/adder_sum_cry_19_0/CIN
5.080	0.035	tINS	FF	1	R42C35[1][B]	Mdu/u_mdu/adder_sum_cry_19_0/COUT
5.080	0.000	tNET	FF	2	R42C35[2][A]	Mdu/u_mdu/adder_sum_cry_20_0/CIN
5.115	0.035	tINS	FF	1	R42C35[2][A]	Mdu/u_mdu/adder_sum_cry_20_0/COUT
5.115	0.000	tNET	FF	2	R42C35[2][B]	Mdu/u_mdu/adder_sum_cry_21_0/CIN
5.151	0.035	tINS	FF	1	R42C35[2][B]	Mdu/u_mdu/adder_sum_cry_21_0/COUT
5.151	0.000	tNET	FF	2	R42C36[0][A]	Mdu/u_mdu/adder_sum_cry_22_0/CIN
5.186	0.035	tINS	FF	1	R42C36[0][A]	Mdu/u_mdu/adder_sum_cry_22_0/COUT
5.186	0.000	tNET	FF	2	R42C36[0][B]	Mdu/u_mdu/adder_sum_cry_23_0/CIN
5.221	0.035	tINS	FF	1	R42C36[0][B]	Mdu/u_mdu/adder_sum_cry_23_0/COUT
5.221	0.000	tNET	FF	2	R42C36[1][A]	Mdu/u_mdu/adder_sum_cry_24_0/CIN
5.256	0.035	tINS	FF	1	R42C36[1][A]	Mdu/u_mdu/adder_sum_cry_24_0/COUT
5.256	0.000	tNET	FF	2	R42C36[1][B]	Mdu/u_mdu/adder_sum_cry_25_0/CIN
5.291	0.035	tINS	FF	1	R42C36[1][B]	Mdu/u_mdu/adder_sum_cry_25_0/COUT
5.291	0.000	tNET	FF	2	R42C36[2][A]	Mdu/u_mdu/adder_sum_cry_26_0/CIN
5.327	0.035	tINS	FF	1	R42C36[2][A]	Mdu/u_mdu/adder_sum_cry_26_0/COUT
5.327	0.000	tNET	FF	2	R42C36[2][B]	Mdu/u_mdu/adder_sum_cry_27_0/CIN
5.362	0.035	tINS	FF	1	R42C36[2][B]	Mdu/u_mdu/adder_sum_cry_27_0/COUT
5.362	0.000	tNET	FF	2	R42C37[0][A]	Mdu/u_mdu/adder_sum_cry_28_0/CIN
5.397	0.035	tINS	FF	1	R42C37[0][A]	Mdu/u_mdu/adder_sum_cry_28_0/COUT
5.397	0.000	tNET	FF	2	R42C37[0][B]	Mdu/u_mdu/adder_sum_cry_29_0/CIN
5.432	0.035	tINS	FF	1	R42C37[0][B]	Mdu/u_mdu/adder_sum_cry_29_0/COUT
5.432	0.000	tNET	FF	2	R42C37[1][A]	Mdu/u_mdu/adder_sum_cry_30_0/CIN
5.467	0.035	tINS	FF	1	R42C37[1][A]	Mdu/u_mdu/adder_sum_cry_30_0/COUT
5.467	0.000	tNET	FF	2	R42C37[1][B]	Mdu/u_mdu/adder_sum_cry_31_0/CIN
5.503	0.035	tINS	FF	1	R42C37[1][B]	Mdu/u_mdu/adder_sum_cry_31_0/COUT
5.503	0.000	tNET	FF	2	R42C37[2][A]	Mdu/u_mdu/adder_sum_s_32_0/CIN
5.973	0.470	tINS	FF	6	R42C37[2][A]	Mdu/u_mdu/adder_sum_s_32_0/SUM
6.941	0.968	tNET	FF	1	R35C31[1][A]	Mdu/u_mdu/reg0_exe_nx_ss0_cZ/I0
7.312	0.371	tINS	FF	50	R35C31[1][A]	Mdu/u_mdu/reg0_exe_nx_ss0_cZ/F
8.558	1.246	tNET	FF	1	R46C37[3][B]	Mdu/u_mdu/reg0_exe_nx_m1_cZ[61]/I3
8.929	0.371	tINS	FF	1	R46C37[3][B]	Mdu/u_mdu/reg0_exe_nx_m1_cZ[61]/F
8.929	0.000	tNET	FF	1	R46C37[3][A]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[61]/I1
9.032	0.103	tINS	FF	1	R46C37[3][A]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[61]/O
10.041	1.009	tNET	FF	1	R35C37[2][A]	Mdu/u_mdu/reg0_nx_cZ[61]/I0
10.611	0.570	tINS	FR	1	R35C37[2][A]	Mdu/u_mdu/reg0_nx_cZ[61]/F
10.611	0.000	tNET	RR	1	R35C37[2][A]	Mdu/u_mdu/reg0_Z[61]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	498	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R35C37[2][A]	Mdu/u_mdu/reg0_Z[61]/CLK
11.683	-0.200	tUnc				Mdu/u_mdu/reg0_Z[61]
11.648	-0.035	tSu		1	R35C37[2][A]	Mdu/u_mdu/reg0_Z[61]

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 3.917, 44.881%; route: 4.579, 52.461%; tC2Q: 0.232, 2.658%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path16

Path Summary:

Slack	1.039
Data Arrival Time	10.609
Data Required Time	11.648
From	Mdu/u_mdu/reg0_fast_Z[2]
To	Mdu/u_mdu/reg0_Z[16]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.683	0.683	tINS	RR	498	IOT48[A]	clk_ibuf/O
1.883	1.201	tNET	RR	1	R30C33[1][A]	Mdu/u_mdu/reg0_fast_Z[2]/CLK
2.115	0.232	tC2Q	RF	7	R30C33[1][A]	Mdu/u_mdu/reg0_fast_Z[2]/Q
3.325	1.210	tNET	FF	1	R41C38[3][B]	Mdu/u_mdu/reg0_neg_axb_0_par_0_cp_0_cZ/I2
3.778	0.453	tINS	FF	1	R41C38[3][B]	Mdu/u_mdu/reg0_neg_axb_0_par_0_cp_0_cZ/F
4.434	0.656	tNET	FF	2	R46C38[1][A]	Mdu/u_mdu/reg0_neg_axb_0_par_cp_0_0/I0
5.004	0.570	tINS	FR	1	R46C38[1][A]	Mdu/u_mdu/reg0_neg_axb_0_par_cp_0_0/COUT
5.004	0.000	tNET	RR	2	R46C38[1][B]	Mdu/u_mdu/reg0_neg_axb_4_par_cp_0_0/CIN
5.039	0.035	tINS	RF	1	R46C38[1][B]	Mdu/u_mdu/reg0_neg_axb_4_par_cp_0_0/COUT
5.039	0.000	tNET	FF	2	R46C38[2][A]	Mdu/u_mdu/reg0_neg_axb_8_par_cp_1/CIN
5.074	0.035	tINS	FF	1	R46C38[2][A]	Mdu/u_mdu/reg0_neg_axb_8_par_cp_1/COUT
5.074	0.000	tNET	FF	2	R46C38[2][B]	Mdu/u_mdu/reg0_neg_axb_12_par_cp_1/CIN
5.109	0.035	tINS	FF	1	R46C38[2][B]	Mdu/u_mdu/reg0_neg_axb_12_par_cp_1/COUT
5.109	0.000	tNET	FF	2	R46C39[0][A]	Mdu/u_mdu/reg0_neg_axb_16_par_cp_1/CIN
5.145	0.035	tINS	FF	1	R46C39[0][A]	Mdu/u_mdu/reg0_neg_axb_16_par_cp_1/COUT
5.145	0.000	tNET	FF	2	R46C39[0][B]	Mdu/u_mdu/reg0_neg_axb_19_par_1/CIN
5.180	0.035	tINS	FF	1	R46C39[0][B]	Mdu/u_mdu/reg0_neg_axb_19_par_1/COUT
5.180	0.000	tNET	FF	2	R46C39[1][A]	Mdu/u_mdu/reg0_neg_axb_23_par_1/CIN
5.215	0.035	tINS	FF	1	R46C39[1][A]	Mdu/u_mdu/reg0_neg_axb_23_par_1/COUT
5.215	0.000	tNET	FF	2	R46C39[1][B]	Mdu/u_mdu/reg0_neg_axb_27_par_1/CIN
5.250	0.035	tINS	FF	1	R46C39[1][B]	Mdu/u_mdu/reg0_neg_axb_27_par_1/COUT
5.250	0.000	tNET	FF	2	R46C39[2][A]	Mdu/u_mdu/reg0_neg_axb_31_par_1/CIN
5.285	0.035	tINS	FF	1	R46C39[2][A]	Mdu/u_mdu/reg0_neg_axb_31_par_1/COUT
5.285	0.000	tNET	FF	2	R46C39[2][B]	Mdu/u_mdu/reg0_neg_cry_34_0/CIN
5.321	0.035	tINS	FF	1	R46C39[2][B]	Mdu/u_mdu/reg0_neg_cry_34_0/COUT
5.321	0.000	tNET	FF	2	R46C40[0][A]	Mdu/u_mdu/reg0_neg_cry_35_0/CIN
5.356	0.035	tINS	FF	1	R46C40[0][A]	Mdu/u_mdu/reg0_neg_cry_35_0/COUT
5.356	0.000	tNET	FF	2	R46C40[0][B]	Mdu/u_mdu/reg0_neg_cry_36_0/CIN
5.391	0.035	tINS	FF	1	R46C40[0][B]	Mdu/u_mdu/reg0_neg_cry_36_0/COUT
5.391	0.000	tNET	FF	2	R46C40[1][A]	Mdu/u_mdu/reg0_neg_cry_37_0/CIN
5.426	0.035	tINS	FF	1	R46C40[1][A]	Mdu/u_mdu/reg0_neg_cry_37_0/COUT
5.426	0.000	tNET	FF	2	R46C40[1][B]	Mdu/u_mdu/reg0_neg_cry_38_0/CIN
5.461	0.035	tINS	FF	1	R46C40[1][B]	Mdu/u_mdu/reg0_neg_cry_38_0/COUT
5.461	0.000	tNET	FF	2	R46C40[2][A]	Mdu/u_mdu/reg0_neg_cry_39_0/CIN
5.497	0.035	tINS	FF	1	R46C40[2][A]	Mdu/u_mdu/reg0_neg_cry_39_0/COUT
5.497	0.000	tNET	FF	2	R46C40[2][B]	Mdu/u_mdu/reg0_neg_cry_40_0/CIN
5.532	0.035	tINS	FF	1	R46C40[2][B]	Mdu/u_mdu/reg0_neg_cry_40_0/COUT
5.532	0.000	tNET	FF	2	R46C41[0][A]	Mdu/u_mdu/reg0_neg_cry_41_0/CIN
5.567	0.035	tINS	FF	1	R46C41[0][A]	Mdu/u_mdu/reg0_neg_cry_41_0/COUT
5.567	0.000	tNET	FF	2	R46C41[0][B]	Mdu/u_mdu/reg0_neg_cry_42_0/CIN
5.602	0.035	tINS	FF	1	R46C41[0][B]	Mdu/u_mdu/reg0_neg_cry_42_0/COUT
5.602	0.000	tNET	FF	2	R46C41[1][A]	Mdu/u_mdu/reg0_neg_cry_43_0/CIN
5.637	0.035	tINS	FF	1	R46C41[1][A]	Mdu/u_mdu/reg0_neg_cry_43_0/COUT
5.637	0.000	tNET	FF	2	R46C41[1][B]	Mdu/u_mdu/reg0_neg_cry_44_0/CIN
5.673	0.035	tINS	FF	1	R46C41[1][B]	Mdu/u_mdu/reg0_neg_cry_44_0/COUT
5.673	0.000	tNET	FF	2	R46C41[2][A]	Mdu/u_mdu/reg0_neg_cry_45_0/CIN
5.708	0.035	tINS	FF	1	R46C41[2][A]	Mdu/u_mdu/reg0_neg_cry_45_0/COUT
5.708	0.000	tNET	FF	2	R46C41[2][B]	Mdu/u_mdu/reg0_neg_cry_46_0/CIN
5.743	0.035	tINS	FF	1	R46C41[2][B]	Mdu/u_mdu/reg0_neg_cry_46_0/COUT
5.743	0.000	tNET	FF	2	R46C42[0][A]	Mdu/u_mdu/reg0_neg_cry_47_0/CIN
5.778	0.035	tINS	FF	1	R46C42[0][A]	Mdu/u_mdu/reg0_neg_cry_47_0/COUT
5.778	0.000	tNET	FF	2	R46C42[0][B]	Mdu/u_mdu/reg0_neg_cry_48_0/CIN
6.248	0.470	tINS	FF	1	R46C42[0][B]	Mdu/u_mdu/reg0_neg_cry_48_0/SUM
7.175	0.927	tNET	FF	1	R35C40[2][A]	Mdu/u_mdu/reg0_post_swap_2[16]/I2
7.546	0.371	tINS	FF	1	R35C40[2][A]	Mdu/u_mdu/reg0_post_swap_2[16]/F
7.546	0.000	tNET	FF	1	R35C40[2][A]	Mdu/u_mdu/reg0_post_swap_4[16]/I0
7.649	0.103	tINS	FF	1	R35C40[2][A]	Mdu/u_mdu/reg0_post_swap_4[16]/O
7.825	0.176	tNET	FF	1	R35C40[1][A]	Mdu/u_mdu/reg0_post_swap_5[16]/I1
8.342	0.517	tINS	FF	2	R35C40[1][A]	Mdu/u_mdu/reg0_post_swap_5[16]/F
9.468	1.125	tNET	FF	1	R46C33[1][B]	Mdu/u_mdu/reg0_nx_1_cZ[16]/I0
10.038	0.570	tINS	FR	1	R46C33[1][B]	Mdu/u_mdu/reg0_nx_1_cZ[16]/F
10.039	0.001	tNET	RR	1	R46C33[0][A]	Mdu/u_mdu/reg0_nx_cZ[16]/I1
10.609	0.570	tINS	RR	1	R46C33[0][A]	Mdu/u_mdu/reg0_nx_cZ[16]/F
10.609	0.000	tNET	RR	1	R46C33[0][A]	Mdu/u_mdu/reg0_Z[16]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	498	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R46C33[0][A]	Mdu/u_mdu/reg0_Z[16]/CLK
11.683	-0.200	tUnc				Mdu/u_mdu/reg0_Z[16]
11.648	-0.035	tSu		1	R46C33[0][A]	Mdu/u_mdu/reg0_Z[16]

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	8
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 4.398, 50.407%; route: 4.095, 46.934%; tC2Q: 0.232, 2.659%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path17

Path Summary:

Slack	1.086
Data Arrival Time	10.562
Data Required Time	11.648
From	Mdu/u_mdu/reg0_Z[8]
To	Mdu/u_mdu/reg0_Z[49]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.683	0.683	tINS	RR	498	IOT48[A]	clk_ibuf/O
1.883	1.201	tNET	RR	1	R33C36[0][B]	Mdu/u_mdu/reg0_Z[8]/CLK
2.115	0.232	tC2Q	RF	18	R33C36[0][B]	Mdu/u_mdu/reg0_Z[8]/Q
3.699	1.584	tNET	FF	1	R51C32[2][A]	Mdu/u_mdu/m9_0_03_1_0_cZ/I2
4.152	0.453	tINS	FF	3	R51C32[2][A]	Mdu/u_mdu/m9_0_03_1_0_cZ/F
4.565	0.413	tNET	FF	1	R51C30[3][A]	Mdu/u_mdu/m9_0_03_0_0_RNIBDAL/I1
5.120	0.555	tINS	FF	2	R51C30[3][A]	Mdu/u_mdu/m9_0_03_0_0_RNIBDAL/F
5.765	0.645	tNET	FF	1	R53C32[0][A]	Mdu/u_mdu/m17_2_03_0_0_cZ/I2
6.320	0.555	tINS	FF	3	R53C32[0][A]	Mdu/u_mdu/m17_2_03_0_0_cZ/F
7.091	0.771	tNET	FF	1	R55C38[3][B]	Mdu/u_mdu/m49_4_03_0_0_cZ/I0
7.544	0.453	tINS	FF	1	R55C38[3][B]	Mdu/u_mdu/m49_4_03_0_0_cZ/F
8.305	0.761	tNET	FF	1	R43C38[1][B]	Mdu/u_mdu/reg0_exe_nx_m1_cZ[49]/I1
8.758	0.453	tINS	FF	1	R43C38[1][B]	Mdu/u_mdu/reg0_exe_nx_m1_cZ[49]/F
8.758	0.000	tNET	FF	1	R43C38[1][A]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[49]/I1
8.861	0.103	tINS	FF	1	R43C38[1][A]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[49]/O
9.992	1.131	tNET	FF	1	R43C38[0][A]	Mdu/u_mdu/reg0_nx_0[49]/I2
10.562	0.570	tINS	FR	1	R43C38[0][A]	Mdu/u_mdu/reg0_nx_0[49]/F
10.562	0.000	tNET	RR	1	R43C38[0][A]	Mdu/u_mdu/reg0_Z[49]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	498	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R43C38[0][A]	Mdu/u_mdu/reg0_Z[49]/CLK
11.683	-0.200	tUnc				Mdu/u_mdu/reg0_Z[49]
11.648	-0.035	tSu		1	R43C38[0][A]	Mdu/u_mdu/reg0_Z[49]

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 3.142, 36.203%; route: 5.305, 61.124%; tC2Q: 0.232, 2.673%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path18

Path Summary:

Slack	1.091
Data Arrival Time	10.557
Data Required Time	11.648
From	Mdu/u_mdu/reg0_Z[5]
To	Mdu/u_mdu/reg0_fast_Z[19]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.683	0.683	tINS	RR	498	IOT48[A]	clk_ibuf/O
1.883	1.201	tNET	RR	1	R29C33[0][A]	Mdu/u_mdu/reg0_Z[5]/CLK
2.115	0.232	tC2Q	RF	12	R29C33[0][A]	Mdu/u_mdu/reg0_Z[5]/Q
3.389	1.274	tNET	FF	1	R52C32[0][A]	Mdu/u_mdu/m7_0_03_0_0_cZ/I3
3.959	0.570	tINS	FR	2	R52C32[0][A]	Mdu/u_mdu/m7_0_03_0_0_cZ/F
4.135	0.176	tNET	RR	1	R52C33[2][B]	Mdu/u_mdu/m7_0_03_0_0_RNI79P/I0
4.652	0.517	tINS	RF	3	R52C33[2][B]	Mdu/u_mdu/m7_0_03_0_0_RNI79P/F
5.660	1.008	tNET	FF	1	R51C33[1][B]	Mdu/u_mdu/m19_2_03_0_0_cZ/I0
6.031	0.371	tINS	FF	3	R51C33[1][B]	Mdu/u_mdu/m19_2_03_0_0_cZ/F
7.140	1.109	tNET	FF	1	R44C31[0][B]	Mdu/u_mdu/m19_4_01_cZ/I2
7.593	0.453	tINS	FF	1	R44C31[0][B]	Mdu/u_mdu/m19_4_01_cZ/F
8.427	0.834	tNET	FF	1	R40C34[2][B]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[19]/I2
8.889	0.462	tINS	FR	1	R40C34[2][B]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[19]/F
8.890	0.001	tNET	RR	1	R40C34[2][A]	Mdu/u_mdu/reg0_exe_nx_cZ[19]/I3
9.407	0.517	tINS	RF	3	R40C34[2][A]	Mdu/u_mdu/reg0_exe_nx_cZ[19]/F
10.095	0.688	tNET	FF	1	R33C32[1][B]	Mdu/u_mdu/reg0_nx_fast_cZ[19]/I0
10.557	0.462	tINS	FR	1	R33C32[1][B]	Mdu/u_mdu/reg0_nx_fast_cZ[19]/F
10.557	0.000	tNET	RR	1	R33C32[1][B]	Mdu/u_mdu/reg0_fast_Z[19]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	498	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R33C32[1][B]	Mdu/u_mdu/reg0_fast_Z[19]/CLK
11.683	-0.200	tUnc				Mdu/u_mdu/reg0_fast_Z[19]
11.648	-0.035	tSu		1	R33C32[1][B]	Mdu/u_mdu/reg0_fast_Z[19]

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 3.352, 38.643%; route: 5.090, 58.682%; tC2Q: 0.232, 2.675%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path19

Path Summary:

Slack	1.191
Data Arrival Time	10.457
Data Required Time	11.648
From	Mdu/u_mdu/div_shift_number_Z[0]
To	Mdu/u_mdu/reg0_Z[10]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.683	0.683	tINS	RR	498	IOT48[A]	clk_ibuf/O
1.883	1.201	tNET	RR	1	R51C37[1][A]	Mdu/u_mdu/div_shift_number_Z[0]/CLK
2.115	0.232	tC2Q	RF	113	R51C37[1][A]	Mdu/u_mdu/div_shift_number_Z[0]/Q
3.368	1.253	tNET	FF	1	R41C36[2][B]	Mdu/u_mdu/m2_0_03_m1_e_1_cZ/I0
3.923	0.555	tINS	FF	1	R41C36[2][B]	Mdu/u_mdu/m2_0_03_m1_e_1_cZ/F
4.486	0.563	tNET	FF	1	R44C36[0][B]	Mdu/u_mdu/m2_0_03_m1_e/I2
5.041	0.555	tINS	FF	6	R44C36[0][B]	Mdu/u_mdu/m2_0_03_m1_e/F
5.811	0.770	tNET	FF	1	R52C32[0][B]	Mdu/u_mdu/m10_2_03_m1_e_1_cZ/I1
6.182	0.371	tINS	FF	1	R52C32[0][B]	Mdu/u_mdu/m10_2_03_m1_e_1_cZ/F
6.353	0.170	tNET	FF	1	R52C32[1][A]	Mdu/u_mdu/m10_2_03_m1_e/I3
6.870	0.517	tINS	FF	4	R52C32[1][A]	Mdu/u_mdu/m10_2_03_m1_e/F
7.995	1.125	tNET	FF	1	R35C35[3][A]	Mdu/u_mdu/reg0_exe_nx_m3_xx_mm[10]/I1
8.512	0.517	tINS	FF	1	R35C35[3][A]	Mdu/u_mdu/reg0_exe_nx_m3_xx_mm[10]/F
8.925	0.413	tNET	FF	1	R33C35[1][B]	Mdu/u_mdu/un6_reg0_nx_cZ[10]_cZ/I2
9.442	0.517	tINS	FF	2	R33C35[1][B]	Mdu/u_mdu/un6_reg0_nx_cZ[10]_cZ/F
10.086	0.644	tNET	FF	1	R29C35[1][B]	Mdu/u_mdu/reg0_nx_cZ[10]/I3
10.457	0.371	tINS	FF	1	R29C35[1][B]	Mdu/u_mdu/reg0_nx_cZ[10]/F
10.457	0.000	tNET	FF	1	R29C35[1][B]	Mdu/u_mdu/reg0_Z[10]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	498	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R29C35[1][B]	Mdu/u_mdu/reg0_Z[10]/CLK
11.683	-0.200	tUnc				Mdu/u_mdu/reg0_Z[10]
11.648	-0.035	tSu		1	R29C35[1][B]	Mdu/u_mdu/reg0_Z[10]

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 3.403, 39.689%; route: 4.939, 57.605%; tC2Q: 0.232, 2.706%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path20

Path Summary:

Slack	1.199
Data Arrival Time	10.449
Data Required Time	11.648
From	Mdu/u_mdu/div_shift_number_Z[1]
To	Mdu/u_mdu/reg0_fast_Z[12]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.683	0.683	tINS	RR	498	IOT48[A]	clk_ibuf/O
1.883	1.201	tNET	RR	1	R51C37[1][B]	Mdu/u_mdu/div_shift_number_Z[1]/CLK
2.115	0.232	tC2Q	RF	114	R51C37[1][B]	Mdu/u_mdu/div_shift_number_Z[1]/Q
3.704	1.588	tNET	FF	1	R41C38[2][B]	Mdu/u_mdu/m4_0_03_0_0_cZ/I1
4.166	0.462	tINS	FR	2	R41C38[2][B]	Mdu/u_mdu/m4_0_03_0_0_cZ/F
4.341	0.176	tNET	RR	1	R42C38[3][B]	Mdu/u_mdu/m4_0_03_0_0_RNI1JV1/I0
4.858	0.517	tINS	RF	3	R42C38[3][B]	Mdu/u_mdu/m4_0_03_0_0_RNI1JV1/F
5.745	0.887	tNET	FF	1	R51C33[0][B]	Mdu/u_mdu/m12_2_03_m1_e_1_cZ/I1
6.294	0.549	tINS	FR	2	R51C33[0][B]	Mdu/u_mdu/m12_2_03_m1_e_1_cZ/F
6.470	0.176	tNET	RR	1	R50C33[3][A]	Mdu/u_mdu/m12_2_03_m1_e_0_RNI7HT5/I1
6.923	0.453	tINS	RF	3	R50C33[3][A]	Mdu/u_mdu/m12_2_03_m1_e_0_RNI7HT5/F
7.592	0.669	tNET	FF	1	R47C34[3][A]	Mdu/u_mdu/reg0_exe_nx_m3_xx_mm[12]/I1
7.963	0.371	tINS	FF	1	R47C34[3][A]	Mdu/u_mdu/reg0_exe_nx_m3_xx_mm[12]/F
8.946	0.983	tNET	FF	1	R35C38[1][B]	Mdu/u_mdu/un6_reg0_nx_cZ[12]_cZ/I2
9.463	0.517	tINS	FF	2	R35C38[1][B]	Mdu/u_mdu/un6_reg0_nx_cZ[12]_cZ/F
9.987	0.524	tNET	FF	1	R33C42[2][A]	Mdu/u_mdu/reg0_nx_fast_cZ[12]/I3
10.449	0.462	tINS	FR	1	R33C42[2][A]	Mdu/u_mdu/reg0_nx_fast_cZ[12]/F
10.449	0.000	tNET	RR	1	R33C42[2][A]	Mdu/u_mdu/reg0_fast_Z[12]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	498	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R33C42[2][A]	Mdu/u_mdu/reg0_fast_Z[12]/CLK
11.683	-0.200	tUnc				Mdu/u_mdu/reg0_fast_Z[12]
11.648	-0.035	tSu		1	R33C42[2][A]	Mdu/u_mdu/reg0_fast_Z[12]

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 3.331, 38.887%; route: 5.003, 58.405%; tC2Q: 0.232, 2.708%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path21

Path Summary:

Slack	1.199
Data Arrival Time	10.449
Data Required Time	11.648
From	Mdu/u_mdu/div_shift_number_Z[1]
To	Mdu/u_mdu/reg0_Z[12]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.683	0.683	tINS	RR	498	IOT48[A]	clk_ibuf/O
1.883	1.201	tNET	RR	1	R51C37[1][B]	Mdu/u_mdu/div_shift_number_Z[1]/CLK
2.115	0.232	tC2Q	RF	114	R51C37[1][B]	Mdu/u_mdu/div_shift_number_Z[1]/Q
3.704	1.588	tNET	FF	1	R41C38[2][B]	Mdu/u_mdu/m4_0_03_0_0_cZ/I1
4.166	0.462	tINS	FR	2	R41C38[2][B]	Mdu/u_mdu/m4_0_03_0_0_cZ/F
4.341	0.176	tNET	RR	1	R42C38[3][B]	Mdu/u_mdu/m4_0_03_0_0_RNI1JV1/I0
4.858	0.517	tINS	RF	3	R42C38[3][B]	Mdu/u_mdu/m4_0_03_0_0_RNI1JV1/F
5.745	0.887	tNET	FF	1	R51C33[0][B]	Mdu/u_mdu/m12_2_03_m1_e_1_cZ/I1
6.294	0.549	tINS	FR	2	R51C33[0][B]	Mdu/u_mdu/m12_2_03_m1_e_1_cZ/F
6.470	0.176	tNET	RR	1	R50C33[3][A]	Mdu/u_mdu/m12_2_03_m1_e_0_RNI7HT5/I1
6.923	0.453	tINS	RF	3	R50C33[3][A]	Mdu/u_mdu/m12_2_03_m1_e_0_RNI7HT5/F
7.592	0.669	tNET	FF	1	R47C34[3][A]	Mdu/u_mdu/reg0_exe_nx_m3_xx_mm[12]/I1
7.963	0.371	tINS	FF	1	R47C34[3][A]	Mdu/u_mdu/reg0_exe_nx_m3_xx_mm[12]/F
8.946	0.983	tNET	FF	1	R35C38[1][B]	Mdu/u_mdu/un6_reg0_nx_cZ[12]_cZ/I2
9.463	0.517	tINS	FF	2	R35C38[1][B]	Mdu/u_mdu/un6_reg0_nx_cZ[12]_cZ/F
9.987	0.524	tNET	FF	1	R33C42[2][B]	Mdu/u_mdu/reg0_nx_cZ[12]/I3
10.449	0.462	tINS	FR	1	R33C42[2][B]	Mdu/u_mdu/reg0_nx_cZ[12]/F
10.449	0.000	tNET	RR	1	R33C42[2][B]	Mdu/u_mdu/reg0_Z[12]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	498	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R33C42[2][B]	Mdu/u_mdu/reg0_Z[12]/CLK
11.683	-0.200	tUnc				Mdu/u_mdu/reg0_Z[12]
11.648	-0.035	tSu		1	R33C42[2][B]	Mdu/u_mdu/reg0_Z[12]

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 3.331, 38.887%; route: 5.003, 58.405%; tC2Q: 0.232, 2.708%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path22

Path Summary:

Slack	1.200
Data Arrival Time	10.448
Data Required Time	11.648
From	Mdu/u_mdu/reg0_fast_Z[23]
To	Mdu/u_mdu/div_shift_number_Z[0]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.683	0.683	tINS	RR	498	IOT48[A]	clk_ibuf/O
1.883	1.201	tNET	RR	1	R44C35[2][A]	Mdu/u_mdu/reg0_fast_Z[23]/CLK
2.115	0.232	tC2Q	RF	5	R44C35[2][A]	Mdu/u_mdu/reg0_fast_Z[23]/Q
2.967	0.852	tNET	FF	1	R40C32[2][A]	Mdu/u_mdu/g0_5/I3
3.522	0.555	tINS	FF	4	R40C32[2][A]	Mdu/u_mdu/g0_5/F
4.191	0.669	tNET	FF	1	R37C33[1][B]	Mdu/u_mdu/g0_4_cZ/I1
4.746	0.555	tINS	FF	10	R37C33[1][B]	Mdu/u_mdu/g0_4_cZ/F
4.956	0.210	tNET	FF	1	R38C33[1][A]	Mdu/u_mdu/un2_div_shift_number_nx_i_cZ_cZ/I3
5.473	0.517	tINS	FF	10	R38C33[1][A]	Mdu/u_mdu/un2_div_shift_number_nx_i_cZ_cZ/F
5.918	0.444	tNET	FF	1	R38C32[0][B]	Mdu/u_mdu/op0_leading_zero_cZ[3]/I1
6.435	0.517	tINS	FF	2	R38C32[0][B]	Mdu/u_mdu/op0_leading_zero_cZ[3]/F
7.003	0.569	tNET	FF	1	R37C32[3][A]	Mdu/u_mdu/div_shift_number_nx_axb_3_i_lfx_cZ/S0
7.254	0.251	tINS	FF	1	R37C32[3][A]	Mdu/u_mdu/div_shift_number_nx_axb_3_i_lfx_cZ/O
8.159	0.904	tNET	FF	2	R37C32[2][B]	Mdu/u_mdu/div_shift_number_nx_cry_3_0/I0
8.729	0.570	tINS	FR	1	R37C32[2][B]	Mdu/u_mdu/div_shift_number_nx_cry_3_0/COUT
8.729	0.000	tNET	RR	2	R37C33[0][A]	Mdu/u_mdu/div_shift_number_nx_cry_4_0/CIN
8.764	0.035	tINS	RF	1	R37C33[0][A]	Mdu/u_mdu/div_shift_number_nx_cry_4_0/COUT
8.764	0.000	tNET	FF	1	R37C34[1][A]	Mdu/u_mdu/g0_0_cZ/I0
9.334	0.570	tINS	FR	6	R37C34[1][A]	Mdu/u_mdu/g0_0_cZ/F
10.448	1.114	tNET	RR	1	R51C37[1][A]	Mdu/u_mdu/div_shift_number_Z[0]/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	498	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R51C37[1][A]	Mdu/u_mdu/div_shift_number_Z[0]/CLK
11.683	-0.200	tUnc				Mdu/u_mdu/div_shift_number_Z[0]
11.648	-0.035	tSu		1	R51C37[1][A]	Mdu/u_mdu/div_shift_number_Z[0]

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	8
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 3.570, 41.684%; route: 4.763, 55.608%; tC2Q: 0.232, 2.709%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path23

Path Summary:

Slack	1.200
Data Arrival Time	10.448
Data Required Time	11.648
From	Mdu/u_mdu/reg0_fast_Z[23]
To	Mdu/u_mdu/div_shift_number_Z[1]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.683	0.683	tINS	RR	498	IOT48[A]	clk_ibuf/O
1.883	1.201	tNET	RR	1	R44C35[2][A]	Mdu/u_mdu/reg0_fast_Z[23]/CLK
2.115	0.232	tC2Q	RF	5	R44C35[2][A]	Mdu/u_mdu/reg0_fast_Z[23]/Q
2.967	0.852	tNET	FF	1	R40C32[2][A]	Mdu/u_mdu/g0_5/I3
3.522	0.555	tINS	FF	4	R40C32[2][A]	Mdu/u_mdu/g0_5/F
4.191	0.669	tNET	FF	1	R37C33[1][B]	Mdu/u_mdu/g0_4_cZ/I1
4.746	0.555	tINS	FF	10	R37C33[1][B]	Mdu/u_mdu/g0_4_cZ/F
4.956	0.210	tNET	FF	1	R38C33[1][A]	Mdu/u_mdu/un2_div_shift_number_nx_i_cZ_cZ/I3
5.473	0.517	tINS	FF	10	R38C33[1][A]	Mdu/u_mdu/un2_div_shift_number_nx_i_cZ_cZ/F
5.918	0.444	tNET	FF	1	R38C32[0][B]	Mdu/u_mdu/op0_leading_zero_cZ[3]/I1
6.435	0.517	tINS	FF	2	R38C32[0][B]	Mdu/u_mdu/op0_leading_zero_cZ[3]/F
7.003	0.569	tNET	FF	1	R37C32[3][A]	Mdu/u_mdu/div_shift_number_nx_axb_3_i_lfx_cZ/S0
7.254	0.251	tINS	FF	1	R37C32[3][A]	Mdu/u_mdu/div_shift_number_nx_axb_3_i_lfx_cZ/O
8.159	0.904	tNET	FF	2	R37C32[2][B]	Mdu/u_mdu/div_shift_number_nx_cry_3_0/I0
8.729	0.570	tINS	FR	1	R37C32[2][B]	Mdu/u_mdu/div_shift_number_nx_cry_3_0/COUT
8.729	0.000	tNET	RR	2	R37C33[0][A]	Mdu/u_mdu/div_shift_number_nx_cry_4_0/CIN
8.764	0.035	tINS	RF	1	R37C33[0][A]	Mdu/u_mdu/div_shift_number_nx_cry_4_0/COUT
8.764	0.000	tNET	FF	1	R37C34[1][A]	Mdu/u_mdu/g0_0_cZ/I0
9.334	0.570	tINS	FR	6	R37C34[1][A]	Mdu/u_mdu/g0_0_cZ/F
10.448	1.114	tNET	RR	1	R51C37[1][B]	Mdu/u_mdu/div_shift_number_Z[1]/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	498	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R51C37[1][B]	Mdu/u_mdu/div_shift_number_Z[1]/CLK
11.683	-0.200	tUnc				Mdu/u_mdu/div_shift_number_Z[1]
11.648	-0.035	tSu		1	R51C37[1][B]	Mdu/u_mdu/div_shift_number_Z[1]

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	8
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 3.570, 41.684%; route: 4.763, 55.608%; tC2Q: 0.232, 2.709%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path24

Path Summary:

Slack	1.200
Data Arrival Time	10.448
Data Required Time	11.648
From	Mdu/u_mdu/reg0_fast_Z[23]
To	Mdu/u_mdu/div_shift_number_Z[2]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.683	0.683	tINS	RR	498	IOT48[A]	clk_ibuf/O
1.883	1.201	tNET	RR	1	R44C35[2][A]	Mdu/u_mdu/reg0_fast_Z[23]/CLK
2.115	0.232	tC2Q	RF	5	R44C35[2][A]	Mdu/u_mdu/reg0_fast_Z[23]/Q
2.967	0.852	tNET	FF	1	R40C32[2][A]	Mdu/u_mdu/g0_5/I3
3.522	0.555	tINS	FF	4	R40C32[2][A]	Mdu/u_mdu/g0_5/F
4.191	0.669	tNET	FF	1	R37C33[1][B]	Mdu/u_mdu/g0_4_cZ/I1
4.746	0.555	tINS	FF	10	R37C33[1][B]	Mdu/u_mdu/g0_4_cZ/F
4.956	0.210	tNET	FF	1	R38C33[1][A]	Mdu/u_mdu/un2_div_shift_number_nx_i_cZ_cZ/I3
5.473	0.517	tINS	FF	10	R38C33[1][A]	Mdu/u_mdu/un2_div_shift_number_nx_i_cZ_cZ/F
5.918	0.444	tNET	FF	1	R38C32[0][B]	Mdu/u_mdu/op0_leading_zero_cZ[3]/I1
6.435	0.517	tINS	FF	2	R38C32[0][B]	Mdu/u_mdu/op0_leading_zero_cZ[3]/F
7.003	0.569	tNET	FF	1	R37C32[3][A]	Mdu/u_mdu/div_shift_number_nx_axb_3_i_lfx_cZ/S0
7.254	0.251	tINS	FF	1	R37C32[3][A]	Mdu/u_mdu/div_shift_number_nx_axb_3_i_lfx_cZ/O
8.159	0.904	tNET	FF	2	R37C32[2][B]	Mdu/u_mdu/div_shift_number_nx_cry_3_0/I0
8.729	0.570	tINS	FR	1	R37C32[2][B]	Mdu/u_mdu/div_shift_number_nx_cry_3_0/COUT
8.729	0.000	tNET	RR	2	R37C33[0][A]	Mdu/u_mdu/div_shift_number_nx_cry_4_0/CIN
8.764	0.035	tINS	RF	1	R37C33[0][A]	Mdu/u_mdu/div_shift_number_nx_cry_4_0/COUT
8.764	0.000	tNET	FF	1	R37C34[1][A]	Mdu/u_mdu/g0_0_cZ/I0
9.334	0.570	tINS	FR	6	R37C34[1][A]	Mdu/u_mdu/g0_0_cZ/F
10.448	1.114	tNET	RR	1	R51C37[2][A]	Mdu/u_mdu/div_shift_number_Z[2]/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	498	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R51C37[2][A]	Mdu/u_mdu/div_shift_number_Z[2]/CLK
11.683	-0.200	tUnc				Mdu/u_mdu/div_shift_number_Z[2]
11.648	-0.035	tSu		1	R51C37[2][A]	Mdu/u_mdu/div_shift_number_Z[2]

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	8
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 3.570, 41.684%; route: 4.763, 55.608%; tC2Q: 0.232, 2.709%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path25

Path Summary:

Slack	1.200
Data Arrival Time	10.448
Data Required Time	11.648
From	Mdu/u_mdu/reg0_fast_Z[23]
To	Mdu/u_mdu/div_shift_number_Z[3]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.683	0.683	tINS	RR	498	IOT48[A]	clk_ibuf/O
1.883	1.201	tNET	RR	1	R44C35[2][A]	Mdu/u_mdu/reg0_fast_Z[23]/CLK
2.115	0.232	tC2Q	RF	5	R44C35[2][A]	Mdu/u_mdu/reg0_fast_Z[23]/Q
2.967	0.852	tNET	FF	1	R40C32[2][A]	Mdu/u_mdu/g0_5/I3
3.522	0.555	tINS	FF	4	R40C32[2][A]	Mdu/u_mdu/g0_5/F
4.191	0.669	tNET	FF	1	R37C33[1][B]	Mdu/u_mdu/g0_4_cZ/I1
4.746	0.555	tINS	FF	10	R37C33[1][B]	Mdu/u_mdu/g0_4_cZ/F
4.956	0.210	tNET	FF	1	R38C33[1][A]	Mdu/u_mdu/un2_div_shift_number_nx_i_cZ_cZ/I3
5.473	0.517	tINS	FF	10	R38C33[1][A]	Mdu/u_mdu/un2_div_shift_number_nx_i_cZ_cZ/F
5.918	0.444	tNET	FF	1	R38C32[0][B]	Mdu/u_mdu/op0_leading_zero_cZ[3]/I1
6.435	0.517	tINS	FF	2	R38C32[0][B]	Mdu/u_mdu/op0_leading_zero_cZ[3]/F
7.003	0.569	tNET	FF	1	R37C32[3][A]	Mdu/u_mdu/div_shift_number_nx_axb_3_i_lfx_cZ/S0
7.254	0.251	tINS	FF	1	R37C32[3][A]	Mdu/u_mdu/div_shift_number_nx_axb_3_i_lfx_cZ/O
8.159	0.904	tNET	FF	2	R37C32[2][B]	Mdu/u_mdu/div_shift_number_nx_cry_3_0/I0
8.729	0.570	tINS	FR	1	R37C32[2][B]	Mdu/u_mdu/div_shift_number_nx_cry_3_0/COUT
8.729	0.000	tNET	RR	2	R37C33[0][A]	Mdu/u_mdu/div_shift_number_nx_cry_4_0/CIN
8.764	0.035	tINS	RF	1	R37C33[0][A]	Mdu/u_mdu/div_shift_number_nx_cry_4_0/COUT
8.764	0.000	tNET	FF	1	R37C34[1][A]	Mdu/u_mdu/g0_0_cZ/I0
9.334	0.570	tINS	FR	6	R37C34[1][A]	Mdu/u_mdu/g0_0_cZ/F
10.448	1.114	tNET	RR	1	R51C37[2][B]	Mdu/u_mdu/div_shift_number_Z[3]/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	498	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R51C37[2][B]	Mdu/u_mdu/div_shift_number_Z[3]/CLK
11.683	-0.200	tUnc				Mdu/u_mdu/div_shift_number_Z[3]
11.648	-0.035	tSu		1	R51C37[2][B]	Mdu/u_mdu/div_shift_number_Z[3]

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	8
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 3.570, 41.684%; route: 4.763, 55.608%; tC2Q: 0.232, 2.709%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Hold Analysis Report

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	0.213
Data Arrival Time	2.040
Data Required Time	1.826
From	u_la0_top/u_ao_mem_ctrl/data_reg_Z[65]
To	u_la0_top/u_ao_mem_ctrl/mem_mem_0_32
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	498	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R11C9[2][A]	u_la0_top/u_ao_mem_ctrl/data_reg_Z[65]/CLK
1.779	0.202	tC2Q	RR	1	R11C9[2][A]	u_la0_top/u_ao_mem_ctrl/data_reg_Z[65]/Q
2.040	0.260	tNET	RR	1	BSRAM_R10[2]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_32/DI1

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	498	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	BSRAM_R10[2]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_32/CLKA
1.577	0.000	tUnc				u_la0_top/u_ao_mem_ctrl/mem_mem_0_32
1.826	0.249	tHld		1	BSRAM_R10[2]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_32

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.260, 56.314%; tC2Q: 0.202, 43.686%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path2

Path Summary:

Slack	0.213
Data Arrival Time	2.040
Data Required Time	1.826
From	u_la0_top/u_ao_mem_ctrl/data_reg_Z[64]
To	u_la0_top/u_ao_mem_ctrl/mem_mem_0_32
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	498	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R9C10[2][A]	u_la0_top/u_ao_mem_ctrl/data_reg_Z[64]/CLK
1.779	0.202	tC2Q	RR	1	R9C10[2][A]	u_la0_top/u_ao_mem_ctrl/data_reg_Z[64]/Q
2.040	0.260	tNET	RR	1	BSRAM_R10[2]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_32/DI0

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	498	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	BSRAM_R10[2]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_32/CLKA
1.577	0.000	tUnc				u_la0_top/u_ao_mem_ctrl/mem_mem_0_32
1.826	0.249	tHld		1	BSRAM_R10[2]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_32

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.260, 56.314%; tC2Q: 0.202, 43.686%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path3

Path Summary:

Slack	0.225
Data Arrival Time	2.052
Data Required Time	1.826
From	u_la0_top/u_ao_mem_ctrl/data_reg_Z[85]
To	u_la0_top/u_ao_mem_ctrl/mem_mem_0_42
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	498	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R11C9[1][B]	u_la0_top/u_ao_mem_ctrl/data_reg_Z[85]/CLK
1.779	0.202	tC2Q	RR	1	R11C9[1][B]	u_la0_top/u_ao_mem_ctrl/data_reg_Z[85]/Q
2.052	0.272	tNET	RR	1	BSRAM_R10[4]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_42/DI1

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	498	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	BSRAM_R10[4]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_42/CLKA
1.577	0.000	tUnc				u_la0_top/u_ao_mem_ctrl/mem_mem_0_42
1.826	0.249	tHld		1	BSRAM_R10[4]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_42

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.272, 57.427%; tC2Q: 0.202, 42.573%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path4

Path Summary:

Slack	0.225
Data Arrival Time	2.052
Data Required Time	1.826
From	u_la0_top/u_ao_mem_ctrl/data_reg_Z[84]
To	u_la0_top/u_ao_mem_ctrl/mem_mem_0_42
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	498	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R11C9[1][A]	u_la0_top/u_ao_mem_ctrl/data_reg_Z[84]/CLK
1.779	0.202	tC2Q	RR	1	R11C9[1][A]	u_la0_top/u_ao_mem_ctrl/data_reg_Z[84]/Q
2.052	0.272	tNET	RR	1	BSRAM_R10[4]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_42/DI0

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	498	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	BSRAM_R10[4]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_42/CLKA
1.577	0.000	tUnc				u_la0_top/u_ao_mem_ctrl/mem_mem_0_42
1.826	0.249	tHld		1	BSRAM_R10[4]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_42

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.272, 57.427%; tC2Q: 0.202, 42.573%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path5

Path Summary:

Slack	0.231
Data Arrival Time	1.926
Data Required Time	1.695
From	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[2]
To	u_la0_top/u_ao_mem_ctrl/mem_mem_0_9
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	498	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R9C9[1][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[2]/CLK
1.779	0.202	tC2Q	RR	51	R9C9[1][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[2]/Q
1.926	0.147	tNET	RR	1	BSRAM_R10[1]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_9/ADA3

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	498	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	BSRAM_R10[1]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_9/CLKA
1.577	0.000	tUnc				u_la0_top/u_ao_mem_ctrl/mem_mem_0_9
1.695	0.118	tHld		1	BSRAM_R10[1]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_9

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.147, 42.083%; tC2Q: 0.202, 57.917%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path6

Path Summary:

Slack	0.233
Data Arrival Time	1.929
Data Required Time	1.695
From	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8]
To	u_la0_top/u_ao_mem_ctrl/mem_mem_0_9
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	498	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R11C8[0][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8]/CLK
1.779	0.202	tC2Q	RR	51	R11C8[0][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8]/Q
1.929	0.149	tNET	RR	1	BSRAM_R10[1]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_9/ADA9

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	498	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	BSRAM_R10[1]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_9/CLKA
1.577	0.000	tUnc				u_la0_top/u_ao_mem_ctrl/mem_mem_0_9
1.695	0.118	tHld		1	BSRAM_R10[1]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_9

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.149, 42.505%; tC2Q: 0.202, 57.495%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path7

Path Summary:

Slack	0.343
Data Arrival Time	2.038
Data Required Time	1.695
From	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[4]
To	u_la0_top/u_ao_mem_ctrl/mem_mem_0_9
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	498	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R12C9[0][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[4]/CLK
1.779	0.202	tC2Q	RR	51	R12C9[0][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[4]/Q
2.038	0.259	tNET	RR	1	BSRAM_R10[1]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_9/ADA5

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	498	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	BSRAM_R10[1]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_9/CLKA
1.577	0.000	tUnc				u_la0_top/u_ao_mem_ctrl/mem_mem_0_9
1.695	0.118	tHld		1	BSRAM_R10[1]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_9

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.259, 56.179%; tC2Q: 0.202, 43.821%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path8

Path Summary:

Slack	0.351
Data Arrival Time	2.178
Data Required Time	1.826
From	u_la0_top/u_ao_mem_ctrl/data_reg_Z[75]
To	u_la0_top/u_ao_mem_ctrl/mem_mem_0_37
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	498	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R12C10[2][A]	u_la0_top/u_ao_mem_ctrl/data_reg_Z[75]/CLK
1.779	0.202	tC2Q	RR	1	R12C10[2][A]	u_la0_top/u_ao_mem_ctrl/data_reg_Z[75]/Q
2.178	0.398	tNET	RR	1	BSRAM_R10[3]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_37/DI1

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	498	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	BSRAM_R10[3]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_37/CLKA
1.577	0.000	tUnc				u_la0_top/u_ao_mem_ctrl/mem_mem_0_37
1.826	0.249	tHld		1	BSRAM_R10[3]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_37

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.398, 66.358%; tC2Q: 0.202, 33.642%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path9

Path Summary:

Slack	0.353
Data Arrival Time	2.048
Data Required Time	1.695
From	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[9]
To	u_la0_top/u_ao_mem_ctrl/mem_mem_0_4
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	498	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R11C6[0][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[9]/CLK
1.779	0.202	tC2Q	RR	51	R11C6[0][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[9]/Q
2.048	0.269	tNET	RR	1	BSRAM_R10[0]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_4/ADA10

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	498	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	BSRAM_R10[0]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_4/CLKA
1.577	0.000	tUnc				u_la0_top/u_ao_mem_ctrl/mem_mem_0_4
1.695	0.118	tHld		1	BSRAM_R10[0]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_4

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.269, 57.097%; tC2Q: 0.202, 42.903%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path10

Path Summary:

Slack	0.354
Data Arrival Time	2.050
Data Required Time	1.695
From	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[5]
To	u_la0_top/u_ao_mem_ctrl/mem_mem_0_32
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	498	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R9C9[1][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[5]/CLK
1.779	0.202	tC2Q	RR	51	R9C9[1][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[5]/Q
2.050	0.270	tNET	RR	1	BSRAM_R10[2]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_32/ADA6

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	498	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	BSRAM_R10[2]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_32/CLKA
1.577	0.000	tUnc				u_la0_top/u_ao_mem_ctrl/mem_mem_0_32
1.695	0.118	tHld		1	BSRAM_R10[2]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_32

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.270, 57.213%; tC2Q: 0.202, 42.787%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path11

Path Summary:

Slack	0.354
Data Arrival Time	2.050
Data Required Time	1.695
From	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[5]
To	u_la0_top/u_ao_mem_ctrl/mem_mem_0_9
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	498	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R9C9[1][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[5]/CLK
1.779	0.202	tC2Q	RR	51	R9C9[1][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[5]/Q
2.050	0.270	tNET	RR	1	BSRAM_R10[1]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_9/ADA6

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	498	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	BSRAM_R10[1]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_9/CLKA
1.577	0.000	tUnc				u_la0_top/u_ao_mem_ctrl/mem_mem_0_9
1.695	0.118	tHld		1	BSRAM_R10[1]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_9

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.270, 57.213%; tC2Q: 0.202, 42.787%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path12

Path Summary:

Slack	0.355
Data Arrival Time	2.051
Data Required Time	1.695
From	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[10]
To	u_la0_top/u_ao_mem_ctrl/mem_mem_0_9
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	498	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R11C6[0][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[10]/CLK
1.779	0.202	tC2Q	RR	51	R11C6[0][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[10]/Q
2.051	0.271	tNET	RR	1	BSRAM_R10[1]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_9/ADA11

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	498	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	BSRAM_R10[1]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_9/CLKA
1.577	0.000	tUnc				u_la0_top/u_ao_mem_ctrl/mem_mem_0_9
1.695	0.118	tHld		1	BSRAM_R10[1]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_9

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.271, 57.319%; tC2Q: 0.202, 42.681%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path13

Path Summary:

Slack	0.355
Data Arrival Time	2.051
Data Required Time	1.695
From	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[10]
To	u_la0_top/u_ao_mem_ctrl/mem_mem_0_4
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	498	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R11C6[0][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[10]/CLK
1.779	0.202	tC2Q	RR	51	R11C6[0][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[10]/Q
2.051	0.271	tNET	RR	1	BSRAM_R10[0]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_4/ADA11

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	498	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	BSRAM_R10[0]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_4/CLKA
1.577	0.000	tUnc				u_la0_top/u_ao_mem_ctrl/mem_mem_0_4
1.695	0.118	tHld		1	BSRAM_R10[0]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_4

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.271, 57.319%; tC2Q: 0.202, 42.681%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path14

Path Summary:

Slack	0.363
Data Arrival Time	2.058
Data Required Time	1.695
From	cnt_Z[8]
To	memr_memr_0_10
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	498	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R46C46[2][A]	cnt_Z[8]/CLK
1.779	0.202	tC2Q	RR	18	R46C46[2][A]	cnt_Z[8]/Q
2.058	0.279	tNET	RR	1	BSRAM_R45[14]	memr_memr_0_10/ADA9

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	498	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	BSRAM_R45[14]	memr_memr_0_10/CLKA
1.577	0.000	tUnc				memr_memr_0_10
1.695	0.118	tHld		1	BSRAM_R45[14]	memr_memr_0_10

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.279, 57.968%; tC2Q: 0.202, 42.032%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path15

Path Summary:

Slack	0.364
Data Arrival Time	2.059
Data Required Time	1.695
From	cnt_Z[10]
To	memr_memr_0_9
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	498	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R46C47[0][A]	cnt_Z[10]/CLK
1.779	0.202	tC2Q	RR	18	R46C47[0][A]	cnt_Z[10]/Q
2.059	0.280	tNET	RR	1	BSRAM_R36[14]	memr_memr_0_9/ADA11

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	498	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	BSRAM_R36[14]	memr_memr_0_9/CLKA
1.577	0.000	tUnc				memr_memr_0_9
1.695	0.118	tHld		1	BSRAM_R36[14]	memr_memr_0_9

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.280, 58.058%; tC2Q: 0.202, 41.942%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path16

Path Summary:

Slack	0.364
Data Arrival Time	2.059
Data Required Time	1.695
From	cnt_Z[3]
To	memr_memr_0_7
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	498	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R46C45[2][B]	cnt_Z[3]/CLK
1.779	0.202	tC2Q	RR	18	R46C45[2][B]	cnt_Z[3]/Q
2.059	0.280	tNET	RR	1	BSRAM_R36[13]	memr_memr_0_7/ADA4

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	498	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	BSRAM_R36[13]	memr_memr_0_7/CLKA
1.577	0.000	tUnc				memr_memr_0_7
1.695	0.118	tHld		1	BSRAM_R36[13]	memr_memr_0_7

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.280, 58.075%; tC2Q: 0.202, 41.925%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path17

Path Summary:

Slack	0.364
Data Arrival Time	2.059
Data Required Time	1.695
From	cnt_Z[1]
To	memr_memr_0_7
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	498	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R46C45[1][B]	cnt_Z[1]/CLK
1.779	0.202	tC2Q	RR	18	R46C45[1][B]	cnt_Z[1]/Q
2.059	0.280	tNET	RR	1	BSRAM_R36[13]	memr_memr_0_7/ADA2

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	498	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	BSRAM_R36[13]	memr_memr_0_7/CLKA
1.577	0.000	tUnc				memr_memr_0_7
1.695	0.118	tHld		1	BSRAM_R36[13]	memr_memr_0_7

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.280, 58.075%; tC2Q: 0.202, 41.925%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path18

Path Summary:

Slack	0.364
Data Arrival Time	2.059
Data Required Time	1.695
From	cnt_Z[0]
To	memr_memr_0_7
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	498	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R46C45[1][A]	cnt_Z[0]/CLK
1.779	0.202	tC2Q	RR	18	R46C45[1][A]	cnt_Z[0]/Q
2.059	0.280	tNET	RR	1	BSRAM_R36[13]	memr_memr_0_7/ADA1

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	498	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	BSRAM_R36[13]	memr_memr_0_7/CLKA
1.577	0.000	tUnc				memr_memr_0_7
1.695	0.118	tHld		1	BSRAM_R36[13]	memr_memr_0_7

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.280, 58.075%; tC2Q: 0.202, 41.925%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path19

Path Summary:

Slack	0.367
Data Arrival Time	2.063
Data Required Time	1.695
From	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[9]
To	u_la0_top/u_ao_mem_ctrl/mem_mem_0_37
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	498	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R11C6[0][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[9]/CLK
1.779	0.202	tC2Q	RR	51	R11C6[0][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[9]/Q
2.063	0.283	tNET	RR	1	BSRAM_R10[3]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_37/ADA10

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	498	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	BSRAM_R10[3]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_37/CLKA
1.577	0.000	tUnc				u_la0_top/u_ao_mem_ctrl/mem_mem_0_37
1.695	0.118	tHld		1	BSRAM_R10[3]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_37

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.283, 58.359%; tC2Q: 0.202, 41.641%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path20

Path Summary:

Slack	0.367
Data Arrival Time	2.063
Data Required Time	1.695
From	cnt_1_Z[10]
To	memr_memr_0_8
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	498	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R48C47[0][A]	cnt_1_Z[10]/CLK
1.779	0.202	tC2Q	RR	17	R48C47[0][A]	cnt_1_Z[10]/Q
2.063	0.283	tNET	RR	1	BSRAM_R54[15]	memr_memr_0_8/ADB11

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	498	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	BSRAM_R54[15]	memr_memr_0_8/CLKB
1.577	0.000	tUnc				memr_memr_0_8
1.695	0.118	tHld		1	BSRAM_R54[15]	memr_memr_0_8

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.283, 58.359%; tC2Q: 0.202, 41.641%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path21

Path Summary:

Slack	0.367
Data Arrival Time	2.063
Data Required Time	1.695
From	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[10]
To	u_la0_top/u_ao_mem_ctrl/mem_mem_0_37
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	498	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R11C6[0][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[10]/CLK
1.779	0.202	tC2Q	RR	51	R11C6[0][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[10]/Q
2.063	0.283	tNET	RR	1	BSRAM_R10[3]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_37/ADA11

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	498	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	BSRAM_R10[3]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_37/CLKA
1.577	0.000	tUnc				u_la0_top/u_ao_mem_ctrl/mem_mem_0_37
1.695	0.118	tHld		1	BSRAM_R10[3]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_37

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.283, 58.375%; tC2Q: 0.202, 41.625%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path22

Path Summary:

Slack	0.369
Data Arrival Time	2.065
Data Required Time	1.695
From	cnt_Z[8]
To	memr_memr_0_8
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	498	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R46C46[2][A]	cnt_Z[8]/CLK
1.779	0.202	tC2Q	RR	18	R46C46[2][A]	cnt_Z[8]/Q
2.065	0.285	tNET	RR	1	BSRAM_R54[15]	memr_memr_0_8/ADA9

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	498	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	BSRAM_R54[15]	memr_memr_0_8/CLKA
1.577	0.000	tUnc				memr_memr_0_8
1.695	0.118	tHld		1	BSRAM_R54[15]	memr_memr_0_8

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.285, 58.551%; tC2Q: 0.202, 41.449%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path23

Path Summary:

Slack	0.369
Data Arrival Time	2.065
Data Required Time	1.695
From	cnt_Z[8]
To	memr_memr_0_6
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	498	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R46C46[2][A]	cnt_Z[8]/CLK
1.779	0.202	tC2Q	RR	18	R46C46[2][A]	cnt_Z[8]/Q
2.065	0.285	tNET	RR	1	BSRAM_R54[14]	memr_memr_0_6/ADA9

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	498	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	BSRAM_R54[14]	memr_memr_0_6/CLKA
1.577	0.000	tUnc				memr_memr_0_6
1.695	0.118	tHld		1	BSRAM_R54[14]	memr_memr_0_6

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.285, 58.551%; tC2Q: 0.202, 41.449%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path24

Path Summary:

Slack	0.378
Data Arrival Time	2.204
Data Required Time	1.826
From	u_la0_top/u_ao_mem_ctrl/data_reg_Z[40]
To	u_la0_top/u_ao_mem_ctrl/mem_mem_0_20
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	498	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R11C11[2][A]	u_la0_top/u_ao_mem_ctrl/data_reg_Z[40]/CLK
1.779	0.202	tC2Q	RR	1	R11C11[2][A]	u_la0_top/u_ao_mem_ctrl/data_reg_Z[40]/Q
2.204	0.425	tNET	RR	1	BSRAM_R10[5]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_20/DI0

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	498	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	BSRAM_R10[5]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_20/CLKA
1.577	0.000	tUnc				u_la0_top/u_ao_mem_ctrl/mem_mem_0_20
1.826	0.249	tHld		1	BSRAM_R10[5]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_20

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.425, 67.773%; tC2Q: 0.202, 32.227%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path25

Path Summary:

Slack	0.386
Data Arrival Time	2.081
Data Required Time	1.695
From	cnt_Z[0]
To	memr_memr_0_6
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	498	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R46C45[1][A]	cnt_Z[0]/CLK
1.779	0.202	tC2Q	RR	18	R46C45[1][A]	cnt_Z[0]/Q
2.081	0.302	tNET	RR	1	BSRAM_R54[14]	memr_memr_0_6/ADA1

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	498	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	BSRAM_R54[14]	memr_memr_0_6/CLKA
1.577	0.000	tUnc				memr_memr_0_6
1.695	0.118	tHld		1	BSRAM_R54[14]	memr_memr_0_6

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.302, 59.900%; tC2Q: 0.202, 40.100%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Recovery Analysis Report

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	1.748
Data Arrival Time	9.900
Data Required Time	11.648
From	u_la0_top/rst_ao_Z
To	u_la0_top/triger_level_cnt_Z[0]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.688	0.688	tINS	FF	498	IOT48[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R7C10[1][B]	u_la0_top/rst_ao_Z/CLK
7.148	0.232	tC2Q	FF	49	R7C10[1][B]	u_la0_top/rst_ao_Z/Q
9.900	2.752	tNET	FF	1	R12C8[0][B]	u_la0_top/triger_level_cnt_Z[0]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	498	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R12C8[0][B]	u_la0_top/triger_level_cnt_Z[0]/CLK
11.683	-0.200	tUnc				u_la0_top/triger_level_cnt_Z[0]
11.648	-0.035	tSu		1	R12C8[0][B]	u_la0_top/triger_level_cnt_Z[0]

Path Statistics:

Clock Skew	-0.033
Setup Relationship	5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.752, 92.227%; tC2Q: 0.232, 7.773%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path2

Path Summary:

Slack	1.748
Data Arrival Time	9.900
Data Required Time	11.648
From	u_la0_top/rst_ao_Z
To	u_la0_top/triger_level_cnt_Z[2]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.688	0.688	tINS	FF	498	IOT48[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R7C10[1][B]	u_la0_top/rst_ao_Z/CLK
7.148	0.232	tC2Q	FF	49	R7C10[1][B]	u_la0_top/rst_ao_Z/Q
9.900	2.752	tNET	FF	1	R12C8[1][B]	u_la0_top/triger_level_cnt_Z[2]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	498	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R12C8[1][B]	u_la0_top/triger_level_cnt_Z[2]/CLK
11.683	-0.200	tUnc				u_la0_top/triger_level_cnt_Z[2]
11.648	-0.035	tSu		1	R12C8[1][B]	u_la0_top/triger_level_cnt_Z[2]

Path Statistics:

Clock Skew	-0.033
Setup Relationship	5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.752, 92.227%; tC2Q: 0.232, 7.773%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path3

Path Summary:

Slack	1.748
Data Arrival Time	9.900
Data Required Time	11.648
From	u_la0_top/rst_ao_Z
To	u_la0_top/capture_window_sel[3]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.688	0.688	tINS	FF	498	IOT48[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R7C10[1][B]	u_la0_top/rst_ao_Z/CLK
7.148	0.232	tC2Q	FF	49	R7C10[1][B]	u_la0_top/rst_ao_Z/Q
9.900	2.752	tNET	FF	1	R12C8[0][A]	u_la0_top/capture_window_sel[3]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	498	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R12C8[0][A]	u_la0_top/capture_window_sel[3]/CLK
11.683	-0.200	tUnc				u_la0_top/capture_window_sel[3]
11.648	-0.035	tSu		1	R12C8[0][A]	u_la0_top/capture_window_sel[3]

Path Statistics:

Clock Skew	-0.033
Setup Relationship	5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.752, 92.227%; tC2Q: 0.232, 7.773%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path4

Path Summary:

Slack	1.748
Data Arrival Time	9.900
Data Required Time	11.648
From	u_la0_top/rst_ao_Z
To	u_la0_top/internal_reg_force_triger_syn_Z[0]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.688	0.688	tINS	FF	498	IOT48[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R7C10[1][B]	u_la0_top/rst_ao_Z/CLK
7.148	0.232	tC2Q	FF	49	R7C10[1][B]	u_la0_top/rst_ao_Z/Q
9.900	2.752	tNET	FF	1	R3C2[0][A]	u_la0_top/internal_reg_force_triger_syn_Z[0]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	498	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R3C2[0][A]	u_la0_top/internal_reg_force_triger_syn_Z[0]/CLK
11.683	-0.200	tUnc				u_la0_top/internal_reg_force_triger_syn_Z[0]
11.648	-0.035	tSu		1	R3C2[0][A]	u_la0_top/internal_reg_force_triger_syn_Z[0]

Path Statistics:

Clock Skew	-0.033
Setup Relationship	5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.752, 92.227%; tC2Q: 0.232, 7.773%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path5

Path Summary:

Slack	1.748
Data Arrival Time	9.900
Data Required Time	11.648
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_length_Z[12]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.688	0.688	tINS	FF	498	IOT48[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R7C10[1][B]	u_la0_top/rst_ao_Z/CLK
7.148	0.232	tC2Q	FF	49	R7C10[1][B]	u_la0_top/rst_ao_Z/Q
9.900	2.752	tNET	FF	1	R2C5[0][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[12]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	498	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R2C5[0][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[12]/CLK
11.683	-0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_length_Z[12]
11.648	-0.035	tSu		1	R2C5[0][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[12]

Path Statistics:

Clock Skew	-0.033
Setup Relationship	5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.752, 92.227%; tC2Q: 0.232, 7.773%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path6

Path Summary:

Slack	1.748
Data Arrival Time	9.900
Data Required Time	11.648
From	u_la0_top/rst_ao_Z
To	u_la0_top/internal_reg_start_syn_Z[0]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.688	0.688	tINS	FF	498	IOT48[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R7C10[1][B]	u_la0_top/rst_ao_Z/CLK
7.148	0.232	tC2Q	FF	49	R7C10[1][B]	u_la0_top/rst_ao_Z/Q
9.900	2.752	tNET	FF	1	R12C9[1][B]	u_la0_top/internal_reg_start_syn_Z[0]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	498	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R12C9[1][B]	u_la0_top/internal_reg_start_syn_Z[0]/CLK
11.683	-0.200	tUnc				u_la0_top/internal_reg_start_syn_Z[0]
11.648	-0.035	tSu		1	R12C9[1][B]	u_la0_top/internal_reg_start_syn_Z[0]

Path Statistics:

Clock Skew	-0.033
Setup Relationship	5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.752, 92.227%; tC2Q: 0.232, 7.773%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path7

Path Summary:

Slack	1.748
Data Arrival Time	9.900
Data Required Time	11.648
From	u_la0_top/rst_ao_Z
To	u_la0_top/internal_reg_start_dly_Z[0]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.688	0.688	tINS	FF	498	IOT48[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R7C10[1][B]	u_la0_top/rst_ao_Z/CLK
7.148	0.232	tC2Q	FF	49	R7C10[1][B]	u_la0_top/rst_ao_Z/Q
9.900	2.752	tNET	FF	1	R5C3[2][A]	u_la0_top/internal_reg_start_dly_Z[0]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	498	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R5C3[2][A]	u_la0_top/internal_reg_start_dly_Z[0]/CLK
11.683	-0.200	tUnc				u_la0_top/internal_reg_start_dly_Z[0]
11.648	-0.035	tSu		1	R5C3[2][A]	u_la0_top/internal_reg_start_dly_Z[0]

Path Statistics:

Clock Skew	-0.033
Setup Relationship	5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.752, 92.227%; tC2Q: 0.232, 7.773%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path8

Path Summary:

Slack	1.748
Data Arrival Time	9.900
Data Required Time	11.648
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.688	0.688	tINS	FF	498	IOT48[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R7C10[1][B]	u_la0_top/rst_ao_Z/CLK
7.148	0.232	tC2Q	FF	49	R7C10[1][B]	u_la0_top/rst_ao_Z/Q
9.900	2.752	tNET	FF	1	R12C3[1][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	498	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R12C3[1][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z/CLK
11.683	-0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z
11.648	-0.035	tSu		1	R12C3[1][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z

Path Statistics:

Clock Skew	-0.033
Setup Relationship	5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.752, 92.227%; tC2Q: 0.232, 7.773%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path9

Path Summary:

Slack	1.748
Data Arrival Time	9.900
Data Required Time	11.648
From	u_la0_top/rst_ao_Z
To	u_la0_top/capture_window_sel_Z[2]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.688	0.688	tINS	FF	498	IOT48[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R7C10[1][B]	u_la0_top/rst_ao_Z/CLK
7.148	0.232	tC2Q	FF	49	R7C10[1][B]	u_la0_top/rst_ao_Z/Q
9.900	2.752	tNET	FF	1	R8C2[2][B]	u_la0_top/capture_window_sel_Z[2]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	498	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R8C2[2][B]	u_la0_top/capture_window_sel_Z[2]/CLK
11.683	-0.200	tUnc				u_la0_top/capture_window_sel_Z[2]
11.648	-0.035	tSu		1	R8C2[2][B]	u_la0_top/capture_window_sel_Z[2]

Path Statistics:

Clock Skew	-0.033
Setup Relationship	5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.752, 92.227%; tC2Q: 0.232, 7.773%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path10

Path Summary:

Slack	1.748
Data Arrival Time	9.900
Data Required Time	11.648
From	u_la0_top/rst_ao_Z
To	u_la0_top/capture_end_dly_Z
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.688	0.688	tINS	FF	498	IOT48[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R7C10[1][B]	u_la0_top/rst_ao_Z/CLK
7.148	0.232	tC2Q	FF	49	R7C10[1][B]	u_la0_top/rst_ao_Z/Q
9.900	2.752	tNET	FF	1	R7C10[2][A]	u_la0_top/capture_end_dly_Z/PRESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	498	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R7C10[2][A]	u_la0_top/capture_end_dly_Z/CLK
11.683	-0.200	tUnc				u_la0_top/capture_end_dly_Z
11.648	-0.035	tSu		1	R7C10[2][A]	u_la0_top/capture_end_dly_Z

Path Statistics:

Clock Skew	-0.033
Setup Relationship	5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.752, 92.227%; tC2Q: 0.232, 7.773%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path11

Path Summary:

Slack	1.748
Data Arrival Time	9.900
Data Required Time	11.648
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.688	0.688	tINS	FF	498	IOT48[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R7C10[1][B]	u_la0_top/rst_ao_Z/CLK
7.148	0.232	tC2Q	FF	49	R7C10[1][B]	u_la0_top/rst_ao_Z/Q
9.900	2.752	tNET	FF	1	R9C2[2][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	498	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R9C2[2][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0]/CLK
11.683	-0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0]
11.648	-0.035	tSu		1	R9C2[2][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0]

Path Statistics:

Clock Skew	-0.033
Setup Relationship	5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.752, 92.227%; tC2Q: 0.232, 7.773%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path12

Path Summary:

Slack	1.748
Data Arrival Time	9.900
Data Required Time	11.648
From	u_la0_top/rst_ao_Z
To	u_la0_top/capture_window_sel_Z[1]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.688	0.688	tINS	FF	498	IOT48[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R7C10[1][B]	u_la0_top/rst_ao_Z/CLK
7.148	0.232	tC2Q	FF	49	R7C10[1][B]	u_la0_top/rst_ao_Z/Q
9.900	2.752	tNET	FF	1	R8C2[2][A]	u_la0_top/capture_window_sel_Z[1]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	498	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R8C2[2][A]	u_la0_top/capture_window_sel_Z[1]/CLK
11.683	-0.200	tUnc				u_la0_top/capture_window_sel_Z[1]
11.648	-0.035	tSu		1	R8C2[2][A]	u_la0_top/capture_window_sel_Z[1]

Path Statistics:

Clock Skew	-0.033
Setup Relationship	5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.752, 92.227%; tC2Q: 0.232, 7.773%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path13

Path Summary:

Slack	1.748
Data Arrival Time	9.900
Data Required Time	11.648
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_length_Z[4]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.688	0.688	tINS	FF	498	IOT48[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R7C10[1][B]	u_la0_top/rst_ao_Z/CLK
7.148	0.232	tC2Q	FF	49	R7C10[1][B]	u_la0_top/rst_ao_Z/Q
9.900	2.752	tNET	FF	1	R6C2[2][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[4]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	498	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R6C2[2][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[4]/CLK
11.683	-0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_length_Z[4]
11.648	-0.035	tSu		1	R6C2[2][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[4]

Path Statistics:

Clock Skew	-0.033
Setup Relationship	5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.752, 92.227%; tC2Q: 0.232, 7.773%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path14

Path Summary:

Slack	1.748
Data Arrival Time	9.900
Data Required Time	11.648
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_length_Z[3]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.688	0.688	tINS	FF	498	IOT48[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R7C10[1][B]	u_la0_top/rst_ao_Z/CLK
7.148	0.232	tC2Q	FF	49	R7C10[1][B]	u_la0_top/rst_ao_Z/Q
9.900	2.752	tNET	FF	1	R6C10[2][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[3]/PRESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	498	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R6C10[2][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[3]/CLK
11.683	-0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_length_Z[3]
11.648	-0.035	tSu		1	R6C10[2][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[3]

Path Statistics:

Clock Skew	-0.033
Setup Relationship	5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.752, 92.227%; tC2Q: 0.232, 7.773%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path15

Path Summary:

Slack	1.748
Data Arrival Time	9.900
Data Required Time	11.648
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_length_Z[9]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.688	0.688	tINS	FF	498	IOT48[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R7C10[1][B]	u_la0_top/rst_ao_Z/CLK
7.148	0.232	tC2Q	FF	49	R7C10[1][B]	u_la0_top/rst_ao_Z/Q
9.900	2.752	tNET	FF	1	R7C10[2][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[9]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	498	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R7C10[2][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[9]/CLK
11.683	-0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_length_Z[9]
11.648	-0.035	tSu		1	R7C10[2][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[9]

Path Statistics:

Clock Skew	-0.033
Setup Relationship	5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.752, 92.227%; tC2Q: 0.232, 7.773%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path16

Path Summary:

Slack	1.748
Data Arrival Time	9.900
Data Required Time	11.648
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[12]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.688	0.688	tINS	FF	498	IOT48[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R7C10[1][B]	u_la0_top/rst_ao_Z/CLK
7.148	0.232	tC2Q	FF	49	R7C10[1][B]	u_la0_top/rst_ao_Z/Q
9.900	2.752	tNET	FF	1	R9C2[1][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[12]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	498	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R9C2[1][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[12]/CLK
11.683	-0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[12]
11.648	-0.035	tSu		1	R9C2[1][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[12]

Path Statistics:

Clock Skew	-0.033
Setup Relationship	5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.752, 92.227%; tC2Q: 0.232, 7.773%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path17

Path Summary:

Slack	1.748
Data Arrival Time	9.900
Data Required Time	11.648
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[2]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.688	0.688	tINS	FF	498	IOT48[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R7C10[1][B]	u_la0_top/rst_ao_Z/CLK
7.148	0.232	tC2Q	FF	49	R7C10[1][B]	u_la0_top/rst_ao_Z/Q
9.900	2.752	tNET	FF	1	R9C9[1][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[2]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	498	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R9C9[1][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[2]/CLK
11.683	-0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[2]
11.648	-0.035	tSu		1	R9C9[1][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[2]

Path Statistics:

Clock Skew	-0.033
Setup Relationship	5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.752, 92.227%; tC2Q: 0.232, 7.773%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path18

Path Summary:

Slack	1.748
Data Arrival Time	9.900
Data Required Time	11.648
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[1]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.688	0.688	tINS	FF	498	IOT48[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R7C10[1][B]	u_la0_top/rst_ao_Z/CLK
7.148	0.232	tC2Q	FF	49	R7C10[1][B]	u_la0_top/rst_ao_Z/Q
9.900	2.752	tNET	FF	1	R9C2[2][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[1]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	498	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R9C2[2][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[1]/CLK
11.683	-0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[1]
11.648	-0.035	tSu		1	R9C2[2][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[1]

Path Statistics:

Clock Skew	-0.033
Setup Relationship	5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.752, 92.227%; tC2Q: 0.232, 7.773%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path19

Path Summary:

Slack	1.748
Data Arrival Time	9.900
Data Required Time	11.648
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_length_Z[7]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.688	0.688	tINS	FF	498	IOT48[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R7C10[1][B]	u_la0_top/rst_ao_Z/CLK
7.148	0.232	tC2Q	FF	49	R7C10[1][B]	u_la0_top/rst_ao_Z/Q
9.900	2.752	tNET	FF	1	R8C10[1][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[7]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	498	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R8C10[1][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[7]/CLK
11.683	-0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_length_Z[7]
11.648	-0.035	tSu		1	R8C10[1][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[7]

Path Statistics:

Clock Skew	-0.033
Setup Relationship	5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.752, 92.227%; tC2Q: 0.232, 7.773%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path20

Path Summary:

Slack	1.748
Data Arrival Time	9.900
Data Required Time	11.648
From	u_la0_top/rst_ao_Z
To	u_la0_top/trigger_seq_start_Z
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.688	0.688	tINS	FF	498	IOT48[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R7C10[1][B]	u_la0_top/rst_ao_Z/CLK
7.148	0.232	tC2Q	FF	49	R7C10[1][B]	u_la0_top/rst_ao_Z/Q
9.900	2.752	tNET	FF	1	R3C3[2][A]	u_la0_top/trigger_seq_start_Z/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	498	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R3C3[2][A]	u_la0_top/trigger_seq_start_Z/CLK
11.683	-0.200	tUnc				u_la0_top/trigger_seq_start_Z
11.648	-0.035	tSu		1	R3C3[2][A]	u_la0_top/trigger_seq_start_Z

Path Statistics:

Clock Skew	-0.033
Setup Relationship	5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.752, 92.227%; tC2Q: 0.232, 7.773%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path21

Path Summary:

Slack	1.748
Data Arrival Time	9.900
Data Required Time	11.648
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[9]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.688	0.688	tINS	FF	498	IOT48[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R7C10[1][B]	u_la0_top/rst_ao_Z/CLK
7.148	0.232	tC2Q	FF	49	R7C10[1][B]	u_la0_top/rst_ao_Z/Q
9.900	2.752	tNET	FF	1	R11C6[0][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[9]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	498	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R11C6[0][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[9]/CLK
11.683	-0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[9]
11.648	-0.035	tSu		1	R11C6[0][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[9]

Path Statistics:

Clock Skew	-0.033
Setup Relationship	5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.752, 92.227%; tC2Q: 0.232, 7.773%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path22

Path Summary:

Slack	1.748
Data Arrival Time	9.900
Data Required Time	11.648
From	u_la0_top/rst_ao_Z
To	u_la0_top/genblk1.u_ao_match_0/match_sep
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.688	0.688	tINS	FF	498	IOT48[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R7C10[1][B]	u_la0_top/rst_ao_Z/CLK
7.148	0.232	tC2Q	FF	49	R7C10[1][B]	u_la0_top/rst_ao_Z/Q
9.900	2.752	tNET	FF	1	R9C9[2][B]	u_la0_top/genblk1.u_ao_match_0/match_sep/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	498	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R9C9[2][B]	u_la0_top/genblk1.u_ao_match_0/match_sep/CLK
11.683	-0.200	tUnc				u_la0_top/genblk1.u_ao_match_0/match_sep
11.648	-0.035	tSu		1	R9C9[2][B]	u_la0_top/genblk1.u_ao_match_0/match_sep

Path Statistics:

Clock Skew	-0.033
Setup Relationship	5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.752, 92.227%; tC2Q: 0.232, 7.773%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path23

Path Summary:

Slack	1.748
Data Arrival Time	9.900
Data Required Time	11.648
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[3]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.688	0.688	tINS	FF	498	IOT48[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R7C10[1][B]	u_la0_top/rst_ao_Z/CLK
7.148	0.232	tC2Q	FF	49	R7C10[1][B]	u_la0_top/rst_ao_Z/Q
9.900	2.752	tNET	FF	1	R8C10[0][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[3]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	498	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R8C10[0][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[3]/CLK
11.683	-0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[3]
11.648	-0.035	tSu		1	R8C10[0][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[3]

Path Statistics:

Clock Skew	-0.033
Setup Relationship	5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.752, 92.227%; tC2Q: 0.232, 7.773%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path24

Path Summary:

Slack	1.748
Data Arrival Time	9.900
Data Required Time	11.648
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.688	0.688	tINS	FF	498	IOT48[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R7C10[1][B]	u_la0_top/rst_ao_Z/CLK
7.148	0.232	tC2Q	FF	49	R7C10[1][B]	u_la0_top/rst_ao_Z/Q
9.900	2.752	tNET	FF	1	R11C8[0][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	498	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R11C8[0][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8]/CLK
11.683	-0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8]
11.648	-0.035	tSu		1	R11C8[0][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8]

Path Statistics:

Clock Skew	-0.033
Setup Relationship	5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.752, 92.227%; tC2Q: 0.232, 7.773%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path25

Path Summary:

Slack	1.748
Data Arrival Time	9.900
Data Required Time	11.648
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_length_Z[2]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.688	0.688	tINS	FF	498	IOT48[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R7C10[1][B]	u_la0_top/rst_ao_Z/CLK
7.148	0.232	tC2Q	FF	49	R7C10[1][B]	u_la0_top/rst_ao_Z/Q
9.900	2.752	tNET	FF	1	R6C10[2][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[2]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	498	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R6C10[2][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[2]/CLK
11.683	-0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_length_Z[2]
11.648	-0.035	tSu		1	R6C10[2][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[2]

Path Statistics:

Clock Skew	-0.033
Setup Relationship	5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.752, 92.227%; tC2Q: 0.232, 7.773%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Removal Analysis Report

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	6.760
Data Arrival Time	8.548
Data Required Time	1.788
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.677	0.678	tINS	FF	498	IOT48[A]	clk_ibuf/O
6.590	0.913	tNET	FF	1	R7C10[1][B]	u_la0_top/rst_ao_Z/CLK
6.792	0.202	tC2Q	FR	49	R7C10[1][B]	u_la0_top/rst_ao_Z/Q
8.548	1.756	tNET	RR	1	R12C3[1][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	498	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R12C3[1][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z/CLK
1.777	0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z
1.788	0.011	tHld		1	R12C3[1][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.756, 89.683%; tC2Q: 0.202, 10.317%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path2

Path Summary:

Slack	6.760
Data Arrival Time	8.548
Data Required Time	1.788
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_Z
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.677	0.678	tINS	FF	498	IOT48[A]	clk_ibuf/O
6.590	0.913	tNET	FF	1	R7C10[1][B]	u_la0_top/rst_ao_Z/CLK
6.792	0.202	tC2Q	FR	49	R7C10[1][B]	u_la0_top/rst_ao_Z/Q
8.548	1.756	tNET	RR	1	R2C5[1][A]	u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_Z/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	498	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R2C5[1][A]	u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_Z/CLK
1.777	0.200	tUnc				u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_Z
1.788	0.011	tHld		1	R2C5[1][A]	u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_Z

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.756, 89.683%; tC2Q: 0.202, 10.317%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path3

Path Summary:

Slack	6.760
Data Arrival Time	8.548
Data Required Time	1.788
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_loop_Z
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.677	0.678	tINS	FF	498	IOT48[A]	clk_ibuf/O
6.590	0.913	tNET	FF	1	R7C10[1][B]	u_la0_top/rst_ao_Z/CLK
6.792	0.202	tC2Q	FR	49	R7C10[1][B]	u_la0_top/rst_ao_Z/Q
8.548	1.756	tNET	RR	1	R12C3[0][A]	u_la0_top/u_ao_mem_ctrl/capture_loop_Z/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	498	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R12C3[0][A]	u_la0_top/u_ao_mem_ctrl/capture_loop_Z/CLK
1.777	0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_loop_Z
1.788	0.011	tHld		1	R12C3[0][A]	u_la0_top/u_ao_mem_ctrl/capture_loop_Z

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.756, 89.683%; tC2Q: 0.202, 10.317%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path4

Path Summary:

Slack	6.760
Data Arrival Time	8.548
Data Required Time	1.788
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_length_Z[0]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.677	0.678	tINS	FF	498	IOT48[A]	clk_ibuf/O
6.590	0.913	tNET	FF	1	R7C10[1][B]	u_la0_top/rst_ao_Z/CLK
6.792	0.202	tC2Q	FR	49	R7C10[1][B]	u_la0_top/rst_ao_Z/Q
8.548	1.756	tNET	RR	1	R8C10[2][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[0]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	498	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R8C10[2][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[0]/CLK
1.777	0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_length_Z[0]
1.788	0.011	tHld		1	R8C10[2][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[0]

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.756, 89.683%; tC2Q: 0.202, 10.317%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path5

Path Summary:

Slack	6.760
Data Arrival Time	8.548
Data Required Time	1.788
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_length_Z[1]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.677	0.678	tINS	FF	498	IOT48[A]	clk_ibuf/O
6.590	0.913	tNET	FF	1	R7C10[1][B]	u_la0_top/rst_ao_Z/CLK
6.792	0.202	tC2Q	FR	49	R7C10[1][B]	u_la0_top/rst_ao_Z/Q
8.548	1.756	tNET	RR	1	R8C10[2][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[1]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	498	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R8C10[2][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[1]/CLK
1.777	0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_length_Z[1]
1.788	0.011	tHld		1	R8C10[2][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[1]

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.756, 89.683%; tC2Q: 0.202, 10.317%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path6

Path Summary:

Slack	6.760
Data Arrival Time	8.548
Data Required Time	1.788
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_length_Z[2]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.677	0.678	tINS	FF	498	IOT48[A]	clk_ibuf/O
6.590	0.913	tNET	FF	1	R7C10[1][B]	u_la0_top/rst_ao_Z/CLK
6.792	0.202	tC2Q	FR	49	R7C10[1][B]	u_la0_top/rst_ao_Z/Q
8.548	1.756	tNET	RR	1	R6C10[2][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[2]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	498	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R6C10[2][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[2]/CLK
1.777	0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_length_Z[2]
1.788	0.011	tHld		1	R6C10[2][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[2]

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.756, 89.683%; tC2Q: 0.202, 10.317%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path7

Path Summary:

Slack	6.760
Data Arrival Time	8.548
Data Required Time	1.788
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_length_Z[3]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.677	0.678	tINS	FF	498	IOT48[A]	clk_ibuf/O
6.590	0.913	tNET	FF	1	R7C10[1][B]	u_la0_top/rst_ao_Z/CLK
6.792	0.202	tC2Q	FR	49	R7C10[1][B]	u_la0_top/rst_ao_Z/Q
8.548	1.756	tNET	RR	1	R6C10[2][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[3]/PRESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	498	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R6C10[2][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[3]/CLK
1.777	0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_length_Z[3]
1.788	0.011	tHld		1	R6C10[2][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[3]

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.756, 89.683%; tC2Q: 0.202, 10.317%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path8

Path Summary:

Slack	6.760
Data Arrival Time	8.548
Data Required Time	1.788
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_length_Z[4]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.677	0.678	tINS	FF	498	IOT48[A]	clk_ibuf/O
6.590	0.913	tNET	FF	1	R7C10[1][B]	u_la0_top/rst_ao_Z/CLK
6.792	0.202	tC2Q	FR	49	R7C10[1][B]	u_la0_top/rst_ao_Z/Q
8.548	1.756	tNET	RR	1	R6C2[2][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[4]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	498	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R6C2[2][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[4]/CLK
1.777	0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_length_Z[4]
1.788	0.011	tHld		1	R6C2[2][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[4]

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.756, 89.683%; tC2Q: 0.202, 10.317%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path9

Path Summary:

Slack	6.760
Data Arrival Time	8.548
Data Required Time	1.788
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_length_Z[5]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.677	0.678	tINS	FF	498	IOT48[A]	clk_ibuf/O
6.590	0.913	tNET	FF	1	R7C10[1][B]	u_la0_top/rst_ao_Z/CLK
6.792	0.202	tC2Q	FR	49	R7C10[1][B]	u_la0_top/rst_ao_Z/Q
8.548	1.756	tNET	RR	1	R6C2[2][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[5]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	498	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R6C2[2][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[5]/CLK
1.777	0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_length_Z[5]
1.788	0.011	tHld		1	R6C2[2][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[5]

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.756, 89.683%; tC2Q: 0.202, 10.317%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path10

Path Summary:

Slack	6.760
Data Arrival Time	8.548
Data Required Time	1.788
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_length_Z[6]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.677	0.678	tINS	FF	498	IOT48[A]	clk_ibuf/O
6.590	0.913	tNET	FF	1	R7C10[1][B]	u_la0_top/rst_ao_Z/CLK
6.792	0.202	tC2Q	FR	49	R7C10[1][B]	u_la0_top/rst_ao_Z/Q
8.548	1.756	tNET	RR	1	R3C2[0][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[6]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	498	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R3C2[0][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[6]/CLK
1.777	0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_length_Z[6]
1.788	0.011	tHld		1	R3C2[0][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[6]

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.756, 89.683%; tC2Q: 0.202, 10.317%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path11

Path Summary:

Slack	6.760
Data Arrival Time	8.548
Data Required Time	1.788
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_length_Z[7]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.677	0.678	tINS	FF	498	IOT48[A]	clk_ibuf/O
6.590	0.913	tNET	FF	1	R7C10[1][B]	u_la0_top/rst_ao_Z/CLK
6.792	0.202	tC2Q	FR	49	R7C10[1][B]	u_la0_top/rst_ao_Z/Q
8.548	1.756	tNET	RR	1	R8C10[1][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[7]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	498	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R8C10[1][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[7]/CLK
1.777	0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_length_Z[7]
1.788	0.011	tHld		1	R8C10[1][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[7]

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.756, 89.683%; tC2Q: 0.202, 10.317%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path12

Path Summary:

Slack	6.760
Data Arrival Time	8.548
Data Required Time	1.788
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_length_Z[8]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.677	0.678	tINS	FF	498	IOT48[A]	clk_ibuf/O
6.590	0.913	tNET	FF	1	R7C10[1][B]	u_la0_top/rst_ao_Z/CLK
6.792	0.202	tC2Q	FR	49	R7C10[1][B]	u_la0_top/rst_ao_Z/Q
8.548	1.756	tNET	RR	1	R8C10[1][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[8]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	498	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R8C10[1][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[8]/CLK
1.777	0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_length_Z[8]
1.788	0.011	tHld		1	R8C10[1][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[8]

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.756, 89.683%; tC2Q: 0.202, 10.317%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path13

Path Summary:

Slack	6.760
Data Arrival Time	8.548
Data Required Time	1.788
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_length_Z[9]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.677	0.678	tINS	FF	498	IOT48[A]	clk_ibuf/O
6.590	0.913	tNET	FF	1	R7C10[1][B]	u_la0_top/rst_ao_Z/CLK
6.792	0.202	tC2Q	FR	49	R7C10[1][B]	u_la0_top/rst_ao_Z/Q
8.548	1.756	tNET	RR	1	R7C10[2][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[9]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	498	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R7C10[2][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[9]/CLK
1.777	0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_length_Z[9]
1.788	0.011	tHld		1	R7C10[2][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[9]

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.756, 89.683%; tC2Q: 0.202, 10.317%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path14

Path Summary:

Slack	6.760
Data Arrival Time	8.548
Data Required Time	1.788
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_length_Z[10]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.677	0.678	tINS	FF	498	IOT48[A]	clk_ibuf/O
6.590	0.913	tNET	FF	1	R7C10[1][B]	u_la0_top/rst_ao_Z/CLK
6.792	0.202	tC2Q	FR	49	R7C10[1][B]	u_la0_top/rst_ao_Z/Q
8.548	1.756	tNET	RR	1	R3C3[0][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[10]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	498	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R3C3[0][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[10]/CLK
1.777	0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_length_Z[10]
1.788	0.011	tHld		1	R3C3[0][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[10]

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.756, 89.683%; tC2Q: 0.202, 10.317%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path15

Path Summary:

Slack	6.760
Data Arrival Time	8.548
Data Required Time	1.788
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_length_Z[11]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.677	0.678	tINS	FF	498	IOT48[A]	clk_ibuf/O
6.590	0.913	tNET	FF	1	R7C10[1][B]	u_la0_top/rst_ao_Z/CLK
6.792	0.202	tC2Q	FR	49	R7C10[1][B]	u_la0_top/rst_ao_Z/Q
8.548	1.756	tNET	RR	1	R3C3[0][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[11]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	498	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R3C3[0][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[11]/CLK
1.777	0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_length_Z[11]
1.788	0.011	tHld		1	R3C3[0][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[11]

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.756, 89.683%; tC2Q: 0.202, 10.317%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path16

Path Summary:

Slack	6.760
Data Arrival Time	8.548
Data Required Time	1.788
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_length_Z[12]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.677	0.678	tINS	FF	498	IOT48[A]	clk_ibuf/O
6.590	0.913	tNET	FF	1	R7C10[1][B]	u_la0_top/rst_ao_Z/CLK
6.792	0.202	tC2Q	FR	49	R7C10[1][B]	u_la0_top/rst_ao_Z/Q
8.548	1.756	tNET	RR	1	R2C5[0][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[12]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	498	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R2C5[0][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[12]/CLK
1.777	0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_length_Z[12]
1.788	0.011	tHld		1	R2C5[0][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[12]

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.756, 89.683%; tC2Q: 0.202, 10.317%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path17

Path Summary:

Slack	6.760
Data Arrival Time	8.548
Data Required Time	1.788
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.677	0.678	tINS	FF	498	IOT48[A]	clk_ibuf/O
6.590	0.913	tNET	FF	1	R7C10[1][B]	u_la0_top/rst_ao_Z/CLK
6.792	0.202	tC2Q	FR	49	R7C10[1][B]	u_la0_top/rst_ao_Z/Q
8.548	1.756	tNET	RR	1	R9C2[2][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	498	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R9C2[2][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0]/CLK
1.777	0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0]
1.788	0.011	tHld		1	R9C2[2][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0]

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.756, 89.683%; tC2Q: 0.202, 10.317%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path18

Path Summary:

Slack	6.760
Data Arrival Time	8.548
Data Required Time	1.788
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[1]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.677	0.678	tINS	FF	498	IOT48[A]	clk_ibuf/O
6.590	0.913	tNET	FF	1	R7C10[1][B]	u_la0_top/rst_ao_Z/CLK
6.792	0.202	tC2Q	FR	49	R7C10[1][B]	u_la0_top/rst_ao_Z/Q
8.548	1.756	tNET	RR	1	R9C2[2][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[1]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	498	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R9C2[2][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[1]/CLK
1.777	0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[1]
1.788	0.011	tHld		1	R9C2[2][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[1]

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.756, 89.683%; tC2Q: 0.202, 10.317%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path19

Path Summary:

Slack	6.760
Data Arrival Time	8.548
Data Required Time	1.788
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[2]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.677	0.678	tINS	FF	498	IOT48[A]	clk_ibuf/O
6.590	0.913	tNET	FF	1	R7C10[1][B]	u_la0_top/rst_ao_Z/CLK
6.792	0.202	tC2Q	FR	49	R7C10[1][B]	u_la0_top/rst_ao_Z/Q
8.548	1.756	tNET	RR	1	R9C9[1][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[2]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	498	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R9C9[1][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[2]/CLK
1.777	0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[2]
1.788	0.011	tHld		1	R9C9[1][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[2]

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.756, 89.683%; tC2Q: 0.202, 10.317%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path20

Path Summary:

Slack	6.760
Data Arrival Time	8.548
Data Required Time	1.788
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[3]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.677	0.678	tINS	FF	498	IOT48[A]	clk_ibuf/O
6.590	0.913	tNET	FF	1	R7C10[1][B]	u_la0_top/rst_ao_Z/CLK
6.792	0.202	tC2Q	FR	49	R7C10[1][B]	u_la0_top/rst_ao_Z/Q
8.548	1.756	tNET	RR	1	R8C10[0][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[3]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	498	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R8C10[0][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[3]/CLK
1.777	0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[3]
1.788	0.011	tHld		1	R8C10[0][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[3]

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.756, 89.683%; tC2Q: 0.202, 10.317%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path21

Path Summary:

Slack	6.760
Data Arrival Time	8.548
Data Required Time	1.788
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[4]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.677	0.678	tINS	FF	498	IOT48[A]	clk_ibuf/O
6.590	0.913	tNET	FF	1	R7C10[1][B]	u_la0_top/rst_ao_Z/CLK
6.792	0.202	tC2Q	FR	49	R7C10[1][B]	u_la0_top/rst_ao_Z/Q
8.548	1.756	tNET	RR	1	R12C9[0][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[4]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	498	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R12C9[0][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[4]/CLK
1.777	0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[4]
1.788	0.011	tHld		1	R12C9[0][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[4]

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.756, 89.683%; tC2Q: 0.202, 10.317%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path22

Path Summary:

Slack	6.760
Data Arrival Time	8.548
Data Required Time	1.788
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[5]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.677	0.678	tINS	FF	498	IOT48[A]	clk_ibuf/O
6.590	0.913	tNET	FF	1	R7C10[1][B]	u_la0_top/rst_ao_Z/CLK
6.792	0.202	tC2Q	FR	49	R7C10[1][B]	u_la0_top/rst_ao_Z/Q
8.548	1.756	tNET	RR	1	R9C9[1][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[5]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	498	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R9C9[1][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[5]/CLK
1.777	0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[5]
1.788	0.011	tHld		1	R9C9[1][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[5]

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.756, 89.683%; tC2Q: 0.202, 10.317%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path23

Path Summary:

Slack	6.760
Data Arrival Time	8.548
Data Required Time	1.788
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[6]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.677	0.678	tINS	FF	498	IOT48[A]	clk_ibuf/O
6.590	0.913	tNET	FF	1	R7C10[1][B]	u_la0_top/rst_ao_Z/CLK
6.792	0.202	tC2Q	FR	49	R7C10[1][B]	u_la0_top/rst_ao_Z/Q
8.548	1.756	tNET	RR	1	R8C10[0][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[6]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	498	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R8C10[0][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[6]/CLK
1.777	0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[6]
1.788	0.011	tHld		1	R8C10[0][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[6]

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.756, 89.683%; tC2Q: 0.202, 10.317%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path24

Path Summary:

Slack	6.760
Data Arrival Time	8.548
Data Required Time	1.788
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[7]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.677	0.678	tINS	FF	498	IOT48[A]	clk_ibuf/O
6.590	0.913	tNET	FF	1	R7C10[1][B]	u_la0_top/rst_ao_Z/CLK
6.792	0.202	tC2Q	FR	49	R7C10[1][B]	u_la0_top/rst_ao_Z/Q
8.548	1.756	tNET	RR	1	R11C8[0][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[7]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	498	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R11C8[0][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[7]/CLK
1.777	0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[7]
1.788	0.011	tHld		1	R11C8[0][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[7]

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.756, 89.683%; tC2Q: 0.202, 10.317%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path25

Path Summary:

Slack	6.760
Data Arrival Time	8.548
Data Required Time	1.788
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.677	0.678	tINS	FF	498	IOT48[A]	clk_ibuf/O
6.590	0.913	tNET	FF	1	R7C10[1][B]	u_la0_top/rst_ao_Z/CLK
6.792	0.202	tC2Q	FR	49	R7C10[1][B]	u_la0_top/rst_ao_Z/Q
8.548	1.756	tNET	RR	1	R11C8[0][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	498	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R11C8[0][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8]/CLK
1.777	0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8]
1.788	0.011	tHld		1	R11C8[0][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8]

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.756, 89.683%; tC2Q: 0.202, 10.317%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Minimum Pulse Width Report:

Report Command:report_min_pulse_width -nworst 10 -detail

MPW1

MPW Summary:

Slack:	3.662
Actual Width:	4.662
Required Width:	1.000
Type:	Low Pulse Width
Clock:	DEFAULT_CLK
Objects:	cnt_1_Z[12]

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	clk_ibuf/I
5.688	0.688	tINS	FF	clk_ibuf/O
6.916	1.228	tNET	FF	cnt_1_Z[12]/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	clk_ibuf/I
10.675	0.675	tINS	RR	clk_ibuf/O
11.577	0.902	tNET	RR	cnt_1_Z[12]/CLK

MPW2

MPW Summary:

Slack:	3.662
Actual Width:	4.662
Required Width:	1.000
Type:	Low Pulse Width
Clock:	DEFAULT_CLK
Objects:	cnt_1_Z[10]

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	clk_ibuf/I
5.688	0.688	tINS	FF	clk_ibuf/O
6.916	1.228	tNET	FF	cnt_1_Z[10]/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	clk_ibuf/I
10.675	0.675	tINS	RR	clk_ibuf/O
11.577	0.902	tNET	RR	cnt_1_Z[10]/CLK

MPW3

MPW Summary:

Slack:	3.662
Actual Width:	4.662
Required Width:	1.000
Type:	Low Pulse Width
Clock:	DEFAULT_CLK
Objects:	cnt_1_Z[6]

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	clk_ibuf/I
5.688	0.688	tINS	FF	clk_ibuf/O
6.916	1.228	tNET	FF	cnt_1_Z[6]/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	clk_ibuf/I
10.675	0.675	tINS	RR	clk_ibuf/O
11.577	0.902	tNET	RR	cnt_1_Z[6]/CLK

MPW4

MPW Summary:

Slack:	3.662
Actual Width:	4.662
Required Width:	1.000
Type:	Low Pulse Width
Clock:	DEFAULT_CLK
Objects:	cnt_Z[11]

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	clk_ibuf/I
5.688	0.688	tINS	FF	clk_ibuf/O
6.916	1.228	tNET	FF	cnt_Z[11]/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	clk_ibuf/I
10.675	0.675	tINS	RR	clk_ibuf/O
11.577	0.902	tNET	RR	cnt_Z[11]/CLK

MPW5

MPW Summary:

Slack:	3.662
Actual Width:	4.662
Required Width:	1.000
Type:	Low Pulse Width
Clock:	DEFAULT_CLK
Objects:	divisor[29]

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	clk_ibuf/I
5.688	0.688	tINS	FF	clk_ibuf/O
6.916	1.228	tNET	FF	divisor[29]/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	clk_ibuf/I
10.675	0.675	tINS	RR	clk_ibuf/O
11.577	0.902	tNET	RR	divisor[29]/CLK

MPW6

MPW Summary:

Slack:	3.662
Actual Width:	4.662
Required Width:	1.000
Type:	Low Pulse Width
Clock:	DEFAULT_CLK
Objects:	m_Z[30]

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	clk_ibuf/I
5.688	0.688	tINS	FF	clk_ibuf/O
6.916	1.228	tNET	FF	m_Z[30]/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	clk_ibuf/I
10.675	0.675	tINS	RR	clk_ibuf/O
11.577	0.902	tNET	RR	m_Z[30]/CLK

MPW7

MPW Summary:

Slack:	3.662
Actual Width:	4.662
Required Width:	1.000
Type:	Low Pulse Width
Clock:	DEFAULT_CLK
Objects:	Mdu/u_mdu/reg0_Z[29]

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	clk_ibuf/I
5.688	0.688	tINS	FF	clk_ibuf/O
6.916	1.228	tNET	FF	Mdu/u_mdu/reg0_Z[29]/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	clk_ibuf/I
10.675	0.675	tINS	RR	clk_ibuf/O
11.577	0.902	tNET	RR	Mdu/u_mdu/reg0_Z[29]/CLK

MPW8

MPW Summary:

Slack:	3.662
Actual Width:	4.662
Required Width:	1.000
Type:	Low Pulse Width
Clock:	DEFAULT_CLK
Objects:	Mdu/u_mdu/reg0_fast_Z[1]

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	clk_ibuf/I
5.688	0.688	tINS	FF	clk_ibuf/O
6.916	1.228	tNET	FF	Mdu/u_mdu/reg0_fast_Z[1]/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	clk_ibuf/I
10.675	0.675	tINS	RR	clk_ibuf/O
11.577	0.902	tNET	RR	Mdu/u_mdu/reg0_fast_Z[1]/CLK

MPW9

MPW Summary:

Slack:	3.662
Actual Width:	4.662
Required Width:	1.000
Type:	Low Pulse Width
Clock:	DEFAULT_CLK
Objects:	Mdu/u_mdu/reg0_fast_Z[0]

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	clk_ibuf/I
5.688	0.688	tINS	FF	clk_ibuf/O
6.916	1.228	tNET	FF	Mdu/u_mdu/reg0_fast_Z[0]/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	clk_ibuf/I
10.675	0.675	tINS	RR	clk_ibuf/O
11.577	0.902	tNET	RR	Mdu/u_mdu/reg0_fast_Z[0]/CLK

MPW10

MPW Summary:

Slack:	3.662
Actual Width:	4.662
Required Width:	1.000
Type:	Low Pulse Width
Clock:	DEFAULT_CLK
Objects:	Mdu/u_mdu/reg0_Z[28]

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	clk_ibuf/I
5.688	0.688	tINS	FF	clk_ibuf/O
6.916	1.228	tNET	FF	Mdu/u_mdu/reg0_Z[28]/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	clk_ibuf/I
10.675	0.675	tINS	RR	clk_ibuf/O
11.577	0.902	tNET	RR	Mdu/u_mdu/reg0_Z[28]/CLK

High Fanout Nets Report:

Report Command:report_high_fanout_nets -max_nets 10

FANOUT	NET NAME	WORST SLACK	MAX DELAY
304	clk_c	-0.444	1.228
114	div_shift_number[1]	0.267	2.376
113	div_shift_number[0]	0.217	2.076
100	reg0_en	3.705	2.289
96	neg_result	4.648	2.394
92	state[1]	4.659	2.925
81	hi_result	2.936	1.729
74	reg0_exe_nx_sm0	1.063	1.647
71	state[3]	6.053	1.400
70	m0_2_03_1	2.160	1.538

Route Congestions Report:

Report Command:report_route_congestion -max_grids 10

GRID LOC	ROUTE CONGESTIONS
R33C36	0.806
R39C56	0.736
R39C33	0.722
R29C52	0.722
R33C37	0.708
R48C46	0.694
R29C51	0.681
R39C37	0.681
R48C38	0.681
R46C46	0.681

Timing Exceptions Report:

Setup Analysis Report

Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Hold Analysis Report

Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Recovery Analysis Report

Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Removal Analysis Report

Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Timing Constraints Report:

SDC Command Type	State	Detail Command