Project Settings
Project Name Integer_Multiply_Divider_pp Device Name rev_1: GOWIN-GW2A : GW2A_55
Implementation Name rev_1 Top Module [auto]
Pipelining 1 Retiming 0
Resource Sharing 1 Fanout Guide 10000
Disable I/O Insertion 0 Disable Sequential Optimizations 0
Clock Conversion 1 FSM Compiler 1

Run Status
Job Name Status CPU Time Real Time Memory Date/Time
(compiler)Complete 109 10 0 - 00m:02s - 2019/2/19
17:57:09
(premap)Complete 9 1 0 0m:01s 0m:02s 196MB 2019/2/19
17:57:13
(fpga_mapper)Complete 23 1 0 0m:10s 0m:11s 214MB 2019/2/19
17:57:25
Multi-srs Generator Complete2019/2/19
17:57:10

Area Summary
I/O ports (io_port) 281 Non I/O Register bits (non_io_reg) 275 (0%)
I/O Register bits (total_io_reg) 0 Block Rams (v_ram) 32 (140)
Block Multipliers (dsp_used) 0 (20) LUTs (total_luts) 1824 (3%)

Timing Summary
Clock NameReq FreqEst FreqSlack
top|clk129.6 MHz110.2 MHz-1.361
System12.0 MHz10.2 MHz-14.716

Optimizations Summary
Combined Clock Conversion 1 / 0