Timing Messages

Report Title	Gowin Timing Analysis Report
Design File	F:/user-bak/Users/FDELL/Desktop/IP/Integer_Multiply-Divider/ref_design/DIV/Integer_Multiply_Divider_pp/project/impl/synplify/rev_1/Integer_Multiply_Divider_pp.vm
Physical Constraints File	F:\user-bak\Users\FDELL\Desktop\IP\Integer_Multiply-Divider\ref_design\DIV\Integer_Multiply_Divider_pp\project\src\Integer_Multiply_Divider_pp.cst
Timing Constraints File	---
GOWIN version	v1.9.0Beta
Part Number	GW2A-LV55PG484C8/I7
Created Time	Tue Feb 19 17:58:45 2019
Legal Announcement	Copyright (C)2014-2019 Gowin Semiconductor Corporation. All rights reserved.

Timing Summaries

STA Tool Run Summary:

Setup Delay Model	Slow 0.95V 85C
Hold Delay Model	Fast 1.05V 0C
Numbers of Paths Analyzed	4117
Numbers of Endpoints Analyzed	9284
Numbers of Falling Endpoints	1
Numbers of Setup Violated Endpoints	0
Numbers of Hold Violated Endpoints	0

Clock Summary:

Clock Name	Type	Period	Frequency(MHz)	Rise	Fall	Source	Master	Objects
DEFAULT_CLK	Base	10.000	100.000	0.000	5.000

Max Frequency Summary:

NO.	Clock Name	Fmax	Entity
1	DEFAULT_CLK	100.613(MHz)	TOP

Total Negative Slack Summary:

Clock Name	Analysis Type	Endpoints TNS	Number of Endpoints
DEFAULT_CLK	Setup	0.000	0
DEFAULT_CLK	Hold	0.000	0

Timing Details

Path Slacks Table:

Setup Paths Table

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	0.061	Mdu/u_mdu/reg0_Z[6]/Q	Mdu/u_mdu/reg0_fast_Z[23]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	0.000	9.704
2	0.061	Mdu/u_mdu/reg0_Z[6]/Q	Mdu/u_mdu/reg0_Z[23]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	0.000	9.704
3	0.149	Mdu/u_mdu/reg0_Z[11]/Q	Mdu/u_mdu/reg0_fast_Z[30]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	0.000	9.616
4	0.149	Mdu/u_mdu/reg0_Z[11]/Q	Mdu/u_mdu/reg0_Z[30]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	0.000	9.616
5	0.223	Mdu/u_mdu/reg0_fast_Z[12]/Q	memq_memq_0_7/DI0	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	0.000	9.542
6	0.292	Mdu/u_mdu/reg0_fast_Z[12]/Q	memq_memq_0_3/DI1	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	0.000	9.473
7	0.397	Mdu/u_mdu/reg0_Z[26]/Q	Mdu/u_mdu/reg0_Z[43]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	0.000	9.368
8	0.419	Mdu/u_mdu/reg0_fast_Z[3]/Q	memq_memq_0_15/DI0	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	0.000	9.347
9	0.529	Mdu/u_mdu/func_reg_fast_Z[2]/Q	Mdu/u_mdu/reg0_Z[7]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	0.000	9.236
10	0.663	Mdu/u_mdu/reg0_fast_Z[3]/Q	memq_memq_0_0/DI0	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	0.000	9.103
11	0.663	Mdu/u_mdu/reg0_fast_Z[12]/Q	Mdu/u_mdu/reg0_Z[16]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	0.000	9.102
12	0.677	Mdu/u_mdu/div_shift_number_Z[1]/Q	Mdu/u_mdu/reg0_fast_Z[28]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	0.000	9.088
13	0.677	Mdu/u_mdu/div_shift_number_Z[1]/Q	Mdu/u_mdu/reg0_Z[28]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	0.000	9.088
14	0.710	Mdu/u_mdu/reg0_Z[49]/Q	memq_memq_0_14/DI1	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	0.000	9.055
15	0.754	Mdu/u_mdu/reg0_Z[8]/Q	Mdu/u_mdu/reg0_31_rep1_Z/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	0.000	9.011
16	0.754	Mdu/u_mdu/reg0_Z[8]/Q	Mdu/u_mdu/reg0_Z[31]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	0.000	9.011
17	0.801	Mdu/u_mdu/reg0_Z[7]/Q	Mdu/u_mdu/reg0_26_rep1_Z/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	0.000	8.964
18	0.801	Mdu/u_mdu/reg0_Z[7]/Q	Mdu/u_mdu/reg0_fast_Z[26]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	0.000	8.964
19	0.808	Mdu/u_mdu/reg0_Z[8]/Q	Mdu/u_mdu/reg0_fast_Z[31]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	0.000	8.957
20	0.820	Mdu/u_mdu/reg0_fast_Z[12]/Q	memq_memq_0_4/DI1	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	0.000	8.945
21	0.880	Mdu/u_mdu/reg0_fast_Z[12]/Q	memq_memq_0_4/DI0	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	0.000	8.886
22	0.888	Mdu/u_mdu/reg0_Z[7]/Q	Mdu/u_mdu/reg0_Z[26]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	0.000	8.877
23	0.949	Mdu/u_mdu/reg1_Z[26]/Q	Mdu/u_mdu/div_shift_number_Z[0]/RESET	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	0.000	8.816
24	0.949	Mdu/u_mdu/reg1_Z[26]/Q	Mdu/u_mdu/div_shift_number_Z[1]/RESET	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	0.000	8.816
25	0.949	Mdu/u_mdu/reg1_Z[26]/Q	Mdu/u_mdu/div_shift_number_Z[3]/RESET	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	0.000	8.816

Hold Paths Table

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	0.213	u_la0_top/u_ao_mem_ctrl/data_reg_Z[97]/Q	u_la0_top/u_ao_mem_ctrl/mem_mem_0_48/DI1	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.000	0.000	0.462
2	0.335	u_la0_top/u_ao_mem_ctrl/data_reg_Z[87]/Q	u_la0_top/u_ao_mem_ctrl/mem_mem_0_43/DI1	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.000	0.000	0.584
3	0.335	u_la0_top/u_ao_mem_ctrl/data_reg_Z[86]/Q	u_la0_top/u_ao_mem_ctrl/mem_mem_0_43/DI0	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.000	0.000	0.584
4	0.342	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[6]/Q	u_la0_top/u_ao_mem_ctrl/mem_mem_0_20/ADA7	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.000	0.000	0.460
5	0.342	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[3]/Q	u_la0_top/u_ao_mem_ctrl/mem_mem_0_20/ADA4	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.000	0.000	0.460
6	0.350	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0]/Q	u_la0_top/u_ao_mem_ctrl/mem_mem_0_20/ADA1	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.000	0.000	0.468
7	0.351	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8]/Q	u_la0_top/u_ao_mem_ctrl/mem_mem_0_20/ADA9	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.000	0.000	0.469
8	0.352	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[9]/Q	u_la0_top/u_ao_mem_ctrl/mem_mem_0_20/ADA10	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.000	0.000	0.470
9	0.352	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[9]/Q	u_la0_top/u_ao_mem_ctrl/mem_mem_0_15/ADA10	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.000	0.000	0.470
10	0.352	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[5]/Q	u_la0_top/u_ao_mem_ctrl/mem_mem_0_43/ADA6	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.000	0.000	0.470
11	0.354	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[12]/Q	u_la0_top/u_ao_mem_ctrl/mem_mem_0_20/ADA13	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.000	0.000	0.472
12	0.354	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[1]/Q	u_la0_top/u_ao_mem_ctrl/mem_mem_0_20/ADA2	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.000	0.000	0.472
13	0.354	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[12]/Q	u_la0_top/u_ao_mem_ctrl/mem_mem_0_15/ADA13	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.000	0.000	0.472
14	0.354	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[1]/Q	u_la0_top/u_ao_mem_ctrl/mem_mem_0_15/ADA2	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.000	0.000	0.472
15	0.354	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[7]/Q	u_la0_top/u_ao_mem_ctrl/mem_mem_0_20/ADA8	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.000	0.000	0.472
16	0.354	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[10]/Q	u_la0_top/u_ao_mem_ctrl/mem_mem_0_15/ADA11	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.000	0.000	0.472
17	0.354	cnt_Z[12]/Q	memq_memq_0_1/ADA13	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.000	0.000	0.472
18	0.355	cnt_Z[6]/Q	memq_memq_0_1/ADA7	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.000	0.000	0.473
19	0.355	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[7]/Q	u_la0_top/u_ao_mem_ctrl/mem_mem_0_43/ADA8	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.000	0.000	0.473
20	0.355	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[10]/Q	u_la0_top/u_ao_mem_ctrl/mem_mem_0_20/ADA11	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.000	0.000	0.473
21	0.361	cnt_Z[11]/Q	memq_memq_0_1/ADA12	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.000	0.000	0.479
22	0.361	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[9]/Q	u_la0_top/u_ao_mem_ctrl/mem_mem_0_43/ADA10	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.000	0.000	0.479
23	0.363	u_la0_top/u_ao_mem_ctrl/data_reg_Z[96]/Q	u_la0_top/u_ao_mem_ctrl/mem_mem_0_48/DI0	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.000	0.000	0.612
24	0.365	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[10]/Q	u_la0_top/u_ao_mem_ctrl/mem_mem_0_43/ADA11	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.000	0.000	0.483
25	0.421	Mdu/u_mdu/state[0]/Q	m_Z[24]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.000	0.000	0.432

Recovery Paths Table

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	1.914	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	5.000	0.033	2.818
2	1.914	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_Z/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	5.000	0.033	2.818
3	1.914	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_loop_Z/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	5.000	0.033	2.818
4	1.914	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_length_Z[0]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	5.000	0.033	2.818
5	1.914	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_length_Z[1]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	5.000	0.033	2.818
6	1.914	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_length_Z[2]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	5.000	0.033	2.818
7	1.914	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_length_Z[3]/PRESET	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	5.000	0.033	2.818
8	1.914	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_length_Z[4]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	5.000	0.033	2.818
9	1.914	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_length_Z[5]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	5.000	0.033	2.818
10	1.914	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_length_Z[6]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	5.000	0.033	2.818
11	1.914	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_length_Z[7]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	5.000	0.033	2.818
12	1.914	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_length_Z[8]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	5.000	0.033	2.818
13	1.914	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_length_Z[9]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	5.000	0.033	2.818
14	1.914	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_length_Z[10]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	5.000	0.033	2.818
15	1.914	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_length_Z[11]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	5.000	0.033	2.818
16	1.914	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_length_Z[12]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	5.000	0.033	2.818
17	1.914	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	5.000	0.033	2.818
18	1.914	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[1]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	5.000	0.033	2.818
19	1.914	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[2]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	5.000	0.033	2.818
20	1.914	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[3]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	5.000	0.033	2.818
21	1.914	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[4]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	5.000	0.033	2.818
22	1.914	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[5]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	5.000	0.033	2.818
23	1.914	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[6]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	5.000	0.033	2.818
24	1.914	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[7]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	5.000	0.033	2.818
25	1.914	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	5.000	0.033	2.818

Removal Paths Table

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	6.623	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	-5.000	0.013	1.821
2	6.623	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_loop_Z/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	-5.000	0.013	1.821
3	6.623	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_length_Z[0]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	-5.000	0.013	1.821
4	6.623	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_length_Z[1]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	-5.000	0.013	1.821
5	6.623	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_length_Z[2]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	-5.000	0.013	1.821
6	6.623	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_length_Z[4]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	-5.000	0.013	1.821
7	6.623	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_length_Z[5]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	-5.000	0.013	1.821
8	6.623	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_length_Z[7]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	-5.000	0.013	1.821
9	6.623	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_length_Z[8]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	-5.000	0.013	1.821
10	6.623	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_length_Z[9]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	-5.000	0.013	1.821
11	6.623	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_length_Z[10]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	-5.000	0.013	1.821
12	6.623	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_length_Z[11]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	-5.000	0.013	1.821
13	6.623	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_length_Z[12]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	-5.000	0.013	1.821
14	6.623	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	-5.000	0.013	1.821
15	6.623	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[1]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	-5.000	0.013	1.821
16	6.623	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[2]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	-5.000	0.013	1.821
17	6.623	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[3]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	-5.000	0.013	1.821
18	6.623	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[4]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	-5.000	0.013	1.821
19	6.623	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[5]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	-5.000	0.013	1.821
20	6.623	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[6]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	-5.000	0.013	1.821
21	6.623	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[7]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	-5.000	0.013	1.821
22	6.623	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	-5.000	0.013	1.821
23	6.623	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[9]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	-5.000	0.013	1.821
24	6.623	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[10]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	-5.000	0.013	1.821
25	6.623	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[11]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	-5.000	0.013	1.821

Minimum Pulse Width Table:

Report Command:report_min_pulse_width -nworst 10 -detail

Number	Slack	Actual Width	Required Width	Type	Clock	Objects
1	3.662	4.662	1.000	Low Pulse Width	DEFAULT_CLK	cnt_1_Z[12]
2	3.662	4.662	1.000	Low Pulse Width	DEFAULT_CLK	cnt_1_Z[10]
3	3.662	4.662	1.000	Low Pulse Width	DEFAULT_CLK	cnt_1_Z[6]
4	3.662	4.662	1.000	Low Pulse Width	DEFAULT_CLK	cnt_Z[11]
5	3.662	4.662	1.000	Low Pulse Width	DEFAULT_CLK	n_Z[25]
6	3.662	4.662	1.000	Low Pulse Width	DEFAULT_CLK	m_Z[27]
7	3.662	4.662	1.000	Low Pulse Width	DEFAULT_CLK	memq_memq_0_13
8	3.662	4.662	1.000	Low Pulse Width	DEFAULT_CLK	Mdu/u_mdu/reg0_fast_Z[31]
9	3.662	4.662	1.000	Low Pulse Width	DEFAULT_CLK	u_la0_top/u_ao_mem_ctrl/data_reg_Z[118]
10	3.662	4.662	1.000	Low Pulse Width	DEFAULT_CLK	u_la0_top/u_ao_mem_ctrl/data_reg_Z[119]

Timing Report By Analysis Type:

Setup Analysis Report

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	0.061
Data Arrival Time	11.587
Data Required Time	11.648
From	Mdu/u_mdu/reg0_Z[6]
To	Mdu/u_mdu/reg0_fast_Z[23]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.683	0.683	tINS	RR	581	IOT48[A]	clk_ibuf/O
1.883	1.201	tNET	RR	1	R39C38[0][A]	Mdu/u_mdu/reg0_Z[6]/CLK
2.115	0.232	tC2Q	RF	12	R39C38[0][A]	Mdu/u_mdu/reg0_Z[6]/Q
3.402	1.287	tNET	FF	1	R50C38[2][B]	Mdu/u_mdu/m7_0_03_1_0_cZ/I2
3.919	0.517	tINS	FF	2	R50C38[2][B]	Mdu/u_mdu/m7_0_03_1_0_cZ/F
4.172	0.253	tNET	FF	1	R52C38[0][A]	Mdu/u_mdu/m7_0_03_0_0_RNI79P/I1
4.689	0.517	tINS	FF	3	R52C38[0][A]	Mdu/u_mdu/m7_0_03_0_0_RNI79P/F
5.624	0.936	tNET	FF	1	R48C33[2][B]	Mdu/u_mdu/m7_2_03_cZ/I3
6.179	0.555	tINS	FF	4	R48C33[2][B]	Mdu/u_mdu/m7_2_03_cZ/F
7.237	1.057	tNET	FF	1	R51C35[2][B]	Mdu/u_mdu/m23_4_01_cZ/I1
7.754	0.517	tINS	FF	1	R51C35[2][B]	Mdu/u_mdu/m23_4_01_cZ/F
8.951	1.198	tNET	FF	1	R37C32[1][B]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[23]/I2
9.500	0.549	tINS	FR	1	R37C32[1][B]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[23]/F
9.502	0.001	tNET	RR	1	R37C32[0][A]	Mdu/u_mdu/reg0_exe_nx_cZ[23]/I3
10.057	0.555	tINS	RF	2	R37C32[0][A]	Mdu/u_mdu/reg0_exe_nx_cZ[23]/F
11.017	0.961	tNET	FF	1	R42C38[0][B]	Mdu/u_mdu/reg0_nx_fast_cZ[23]/I0
11.587	0.570	tINS	FR	1	R42C38[0][B]	Mdu/u_mdu/reg0_nx_fast_cZ[23]/F
11.587	0.000	tNET	RR	1	R42C38[0][B]	Mdu/u_mdu/reg0_fast_Z[23]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	581	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R42C38[0][B]	Mdu/u_mdu/reg0_fast_Z[23]/CLK
11.683	-0.200	tUnc				Mdu/u_mdu/reg0_fast_Z[23]
11.648	-0.035	tSu		1	R42C38[0][B]	Mdu/u_mdu/reg0_fast_Z[23]

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 3.780, 38.953%; route: 5.692, 58.656%; tC2Q: 0.232, 2.391%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path2

Path Summary:

Slack	0.061
Data Arrival Time	11.587
Data Required Time	11.648
From	Mdu/u_mdu/reg0_Z[6]
To	Mdu/u_mdu/reg0_Z[23]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.683	0.683	tINS	RR	581	IOT48[A]	clk_ibuf/O
1.883	1.201	tNET	RR	1	R39C38[0][A]	Mdu/u_mdu/reg0_Z[6]/CLK
2.115	0.232	tC2Q	RF	12	R39C38[0][A]	Mdu/u_mdu/reg0_Z[6]/Q
3.402	1.287	tNET	FF	1	R50C38[2][B]	Mdu/u_mdu/m7_0_03_1_0_cZ/I2
3.919	0.517	tINS	FF	2	R50C38[2][B]	Mdu/u_mdu/m7_0_03_1_0_cZ/F
4.172	0.253	tNET	FF	1	R52C38[0][A]	Mdu/u_mdu/m7_0_03_0_0_RNI79P/I1
4.689	0.517	tINS	FF	3	R52C38[0][A]	Mdu/u_mdu/m7_0_03_0_0_RNI79P/F
5.624	0.936	tNET	FF	1	R48C33[2][B]	Mdu/u_mdu/m7_2_03_cZ/I3
6.179	0.555	tINS	FF	4	R48C33[2][B]	Mdu/u_mdu/m7_2_03_cZ/F
7.237	1.057	tNET	FF	1	R51C35[2][B]	Mdu/u_mdu/m23_4_01_cZ/I1
7.754	0.517	tINS	FF	1	R51C35[2][B]	Mdu/u_mdu/m23_4_01_cZ/F
8.951	1.198	tNET	FF	1	R37C32[1][B]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[23]/I2
9.500	0.549	tINS	FR	1	R37C32[1][B]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[23]/F
9.502	0.001	tNET	RR	1	R37C32[0][A]	Mdu/u_mdu/reg0_exe_nx_cZ[23]/I3
10.057	0.555	tINS	RF	2	R37C32[0][A]	Mdu/u_mdu/reg0_exe_nx_cZ[23]/F
11.017	0.961	tNET	FF	1	R42C38[1][B]	Mdu/u_mdu/reg0_nx_cZ[23]/I0
11.587	0.570	tINS	FR	1	R42C38[1][B]	Mdu/u_mdu/reg0_nx_cZ[23]/F
11.587	0.000	tNET	RR	1	R42C38[1][B]	Mdu/u_mdu/reg0_Z[23]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	581	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R42C38[1][B]	Mdu/u_mdu/reg0_Z[23]/CLK
11.683	-0.200	tUnc				Mdu/u_mdu/reg0_Z[23]
11.648	-0.035	tSu		1	R42C38[1][B]	Mdu/u_mdu/reg0_Z[23]

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 3.780, 38.953%; route: 5.692, 58.656%; tC2Q: 0.232, 2.391%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path3

Path Summary:

Slack	0.149
Data Arrival Time	11.499
Data Required Time	11.648
From	Mdu/u_mdu/reg0_Z[11]
To	Mdu/u_mdu/reg0_fast_Z[30]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.683	0.683	tINS	RR	581	IOT48[A]	clk_ibuf/O
1.883	1.201	tNET	RR	1	R34C43[0][A]	Mdu/u_mdu/reg0_Z[11]/CLK
2.115	0.232	tC2Q	RF	10	R34C43[0][A]	Mdu/u_mdu/reg0_Z[11]/Q
3.577	1.462	tNET	FF	1	R49C39[3][B]	Mdu/u_mdu/m14_0_03_1_cZ/I2
4.094	0.517	tINS	FF	1	R49C39[3][B]	Mdu/u_mdu/m14_0_03_1_cZ/F
4.508	0.413	tNET	FF	1	R49C36[2][B]	Mdu/u_mdu/m14_0_03_cZ/I1
4.879	0.371	tINS	FF	4	R49C36[2][B]	Mdu/u_mdu/m14_0_03_cZ/F
5.543	0.665	tNET	FF	1	R47C33[2][B]	Mdu/u_mdu/m14_2_03_1_0_cZ/I3
6.113	0.570	tINS	FR	2	R47C33[2][B]	Mdu/u_mdu/m14_2_03_1_0_cZ/F
6.287	0.174	tNET	RR	1	R47C32[1][A]	Mdu/u_mdu/m14_2_03_0_0_RNI70O1/I1
6.857	0.570	tINS	RR	3	R47C32[1][A]	Mdu/u_mdu/m14_2_03_0_0_RNI70O1/F
7.036	0.179	tNET	RR	1	R46C32[2][A]	Mdu/u_mdu/m30_4_01_cZ/I1
7.553	0.517	tINS	RF	1	R46C32[2][A]	Mdu/u_mdu/m30_4_01_cZ/F
8.779	1.226	tNET	FF	1	R40C35[2][B]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[30]/I2
9.232	0.453	tINS	FF	1	R40C35[2][B]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[30]/F
9.629	0.397	tNET	FF	1	R40C36[3][B]	Mdu/u_mdu/reg0_exe_nx_cZ[30]/I3
10.184	0.555	tINS	FF	2	R40C36[3][B]	Mdu/u_mdu/reg0_exe_nx_cZ[30]/F
10.950	0.766	tNET	FF	1	R42C42[2][B]	Mdu/u_mdu/reg0_nx_fast_cZ[30]/I0
11.499	0.549	tINS	FR	1	R42C42[2][B]	Mdu/u_mdu/reg0_nx_fast_cZ[30]/F
11.499	0.000	tNET	RR	1	R42C42[2][B]	Mdu/u_mdu/reg0_fast_Z[30]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	581	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R42C42[2][B]	Mdu/u_mdu/reg0_fast_Z[30]/CLK
11.683	-0.200	tUnc				Mdu/u_mdu/reg0_fast_Z[30]
11.648	-0.035	tSu		1	R42C42[2][B]	Mdu/u_mdu/reg0_fast_Z[30]

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	8
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 4.102, 42.658%; route: 5.282, 54.929%; tC2Q: 0.232, 2.413%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path4

Path Summary:

Slack	0.149
Data Arrival Time	11.499
Data Required Time	11.648
From	Mdu/u_mdu/reg0_Z[11]
To	Mdu/u_mdu/reg0_Z[30]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.683	0.683	tINS	RR	581	IOT48[A]	clk_ibuf/O
1.883	1.201	tNET	RR	1	R34C43[0][A]	Mdu/u_mdu/reg0_Z[11]/CLK
2.115	0.232	tC2Q	RF	10	R34C43[0][A]	Mdu/u_mdu/reg0_Z[11]/Q
3.577	1.462	tNET	FF	1	R49C39[3][B]	Mdu/u_mdu/m14_0_03_1_cZ/I2
4.094	0.517	tINS	FF	1	R49C39[3][B]	Mdu/u_mdu/m14_0_03_1_cZ/F
4.508	0.413	tNET	FF	1	R49C36[2][B]	Mdu/u_mdu/m14_0_03_cZ/I1
4.879	0.371	tINS	FF	4	R49C36[2][B]	Mdu/u_mdu/m14_0_03_cZ/F
5.543	0.665	tNET	FF	1	R47C33[2][B]	Mdu/u_mdu/m14_2_03_1_0_cZ/I3
6.113	0.570	tINS	FR	2	R47C33[2][B]	Mdu/u_mdu/m14_2_03_1_0_cZ/F
6.287	0.174	tNET	RR	1	R47C32[1][A]	Mdu/u_mdu/m14_2_03_0_0_RNI70O1/I1
6.857	0.570	tINS	RR	3	R47C32[1][A]	Mdu/u_mdu/m14_2_03_0_0_RNI70O1/F
7.036	0.179	tNET	RR	1	R46C32[2][A]	Mdu/u_mdu/m30_4_01_cZ/I1
7.553	0.517	tINS	RF	1	R46C32[2][A]	Mdu/u_mdu/m30_4_01_cZ/F
8.779	1.226	tNET	FF	1	R40C35[2][B]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[30]/I2
9.232	0.453	tINS	FF	1	R40C35[2][B]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[30]/F
9.629	0.397	tNET	FF	1	R40C36[3][B]	Mdu/u_mdu/reg0_exe_nx_cZ[30]/I3
10.184	0.555	tINS	FF	2	R40C36[3][B]	Mdu/u_mdu/reg0_exe_nx_cZ[30]/F
10.950	0.766	tNET	FF	1	R42C42[1][B]	Mdu/u_mdu/reg0_nx_cZ[30]/I0
11.499	0.549	tINS	FR	1	R42C42[1][B]	Mdu/u_mdu/reg0_nx_cZ[30]/F
11.499	0.000	tNET	RR	1	R42C42[1][B]	Mdu/u_mdu/reg0_Z[30]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	581	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R42C42[1][B]	Mdu/u_mdu/reg0_Z[30]/CLK
11.683	-0.200	tUnc				Mdu/u_mdu/reg0_Z[30]
11.648	-0.035	tSu		1	R42C42[1][B]	Mdu/u_mdu/reg0_Z[30]

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	8
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 4.102, 42.658%; route: 5.282, 54.929%; tC2Q: 0.232, 2.413%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path5

Path Summary:

Slack	0.223
Data Arrival Time	11.426
Data Required Time	11.648
From	Mdu/u_mdu/reg0_fast_Z[12]
To	memq_memq_0_7
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.683	0.683	tINS	RR	581	IOT48[A]	clk_ibuf/O
1.883	1.201	tNET	RR	1	R48C43[0][B]	Mdu/u_mdu/reg0_fast_Z[12]/CLK
2.115	0.232	tC2Q	RF	8	R48C43[0][B]	Mdu/u_mdu/reg0_fast_Z[12]/Q
3.056	0.941	tNET	FF	1	R39C40[3][A]	Mdu/u_mdu/reg0_neg_axb_12_par_0_cp_cZ/I0
3.573	0.517	tINS	FF	1	R39C40[3][A]	Mdu/u_mdu/reg0_neg_axb_12_par_0_cp_cZ/F
4.771	1.198	tNET	FF	2	R33C29[2][B]	Mdu/u_mdu/reg0_neg_axb_12_par_cp_1/I0
5.341	0.570	tINS	FR	1	R33C29[2][B]	Mdu/u_mdu/reg0_neg_axb_12_par_cp_1/COUT
5.341	0.000	tNET	RR	2	R33C30[0][A]	Mdu/u_mdu/reg0_neg_axb_16_par_cp_1/CIN
5.376	0.035	tINS	RF	1	R33C30[0][A]	Mdu/u_mdu/reg0_neg_axb_16_par_cp_1/COUT
5.376	0.000	tNET	FF	2	R33C30[0][B]	Mdu/u_mdu/reg0_neg_axb_19_par_1/CIN
5.411	0.035	tINS	FF	1	R33C30[0][B]	Mdu/u_mdu/reg0_neg_axb_19_par_1/COUT
5.411	0.000	tNET	FF	2	R33C30[1][A]	Mdu/u_mdu/reg0_neg_axb_23_par_1/CIN
5.447	0.035	tINS	FF	1	R33C30[1][A]	Mdu/u_mdu/reg0_neg_axb_23_par_1/COUT
5.447	0.000	tNET	FF	2	R33C30[1][B]	Mdu/u_mdu/reg0_neg_axb_27_par_1/CIN
5.482	0.035	tINS	FF	1	R33C30[1][B]	Mdu/u_mdu/reg0_neg_axb_27_par_1/COUT
5.482	0.000	tNET	FF	2	R33C30[2][A]	Mdu/u_mdu/reg0_neg_axb_31_par_1/CIN
5.517	0.035	tINS	FF	1	R33C30[2][A]	Mdu/u_mdu/reg0_neg_axb_31_par_1/COUT
5.517	0.000	tNET	FF	2	R33C30[2][B]	Mdu/u_mdu/reg0_neg_cry_34_0/CIN
5.552	0.035	tINS	FF	1	R33C30[2][B]	Mdu/u_mdu/reg0_neg_cry_34_0/COUT
5.552	0.000	tNET	FF	2	R33C31[0][A]	Mdu/u_mdu/reg0_neg_cry_35_0/CIN
5.587	0.035	tINS	FF	1	R33C31[0][A]	Mdu/u_mdu/reg0_neg_cry_35_0/COUT
5.587	0.000	tNET	FF	2	R33C31[0][B]	Mdu/u_mdu/reg0_neg_cry_36_0/CIN
5.623	0.035	tINS	FF	1	R33C31[0][B]	Mdu/u_mdu/reg0_neg_cry_36_0/COUT
5.623	0.000	tNET	FF	2	R33C31[1][A]	Mdu/u_mdu/reg0_neg_cry_37_0/CIN
5.658	0.035	tINS	FF	1	R33C31[1][A]	Mdu/u_mdu/reg0_neg_cry_37_0/COUT
5.658	0.000	tNET	FF	2	R33C31[1][B]	Mdu/u_mdu/reg0_neg_cry_38_0/CIN
5.693	0.035	tINS	FF	1	R33C31[1][B]	Mdu/u_mdu/reg0_neg_cry_38_0/COUT
5.693	0.000	tNET	FF	2	R33C31[2][A]	Mdu/u_mdu/reg0_neg_cry_39_0/CIN
5.728	0.035	tINS	FF	1	R33C31[2][A]	Mdu/u_mdu/reg0_neg_cry_39_0/COUT
5.728	0.000	tNET	FF	2	R33C31[2][B]	Mdu/u_mdu/reg0_neg_cry_40_0/CIN
5.763	0.035	tINS	FF	1	R33C31[2][B]	Mdu/u_mdu/reg0_neg_cry_40_0/COUT
5.763	0.000	tNET	FF	2	R33C32[0][A]	Mdu/u_mdu/reg0_neg_cry_41_0/CIN
5.799	0.035	tINS	FF	1	R33C32[0][A]	Mdu/u_mdu/reg0_neg_cry_41_0/COUT
5.799	0.000	tNET	FF	2	R33C32[0][B]	Mdu/u_mdu/reg0_neg_cry_42_0/CIN
5.834	0.035	tINS	FF	1	R33C32[0][B]	Mdu/u_mdu/reg0_neg_cry_42_0/COUT
5.834	0.000	tNET	FF	2	R33C32[1][A]	Mdu/u_mdu/reg0_neg_cry_43_0/CIN
5.869	0.035	tINS	FF	1	R33C32[1][A]	Mdu/u_mdu/reg0_neg_cry_43_0/COUT
5.869	0.000	tNET	FF	2	R33C32[1][B]	Mdu/u_mdu/reg0_neg_cry_44_0/CIN
5.904	0.035	tINS	FF	1	R33C32[1][B]	Mdu/u_mdu/reg0_neg_cry_44_0/COUT
5.904	0.000	tNET	FF	2	R33C32[2][A]	Mdu/u_mdu/reg0_neg_cry_45_0/CIN
5.939	0.035	tINS	FF	1	R33C32[2][A]	Mdu/u_mdu/reg0_neg_cry_45_0/COUT
5.939	0.000	tNET	FF	2	R33C32[2][B]	Mdu/u_mdu/reg0_neg_cry_46_0/CIN
6.409	0.470	tINS	FF	1	R33C32[2][B]	Mdu/u_mdu/reg0_neg_cry_46_0/SUM
6.823	0.413	tNET	FF	1	R31C33[3][A]	Mdu/u_mdu/reg0_post_swap_2[14]/I2
7.276	0.453	tINS	FF	1	R31C33[3][A]	Mdu/u_mdu/reg0_post_swap_2[14]/F
7.276	0.000	tNET	FF	1	R31C33[3][A]	Mdu/u_mdu/reg0_post_swap_4[14]/I0
7.379	0.103	tINS	FF	2	R31C33[3][A]	Mdu/u_mdu/reg0_post_swap_4[14]/O
8.049	0.671	tNET	FF	1	R32C36[3][A]	Mdu/u_mdu/reg0_post_swap_5[14]/I1
8.604	0.555	tINS	FF	1	R32C36[3][A]	Mdu/u_mdu/reg0_post_swap_5[14]/F
9.018	0.413	tNET	FF	1	R32C39[2][A]	Mdu/u_mdu/res0_cZ[14]/I1
9.573	0.555	tINS	FF	3	R32C39[2][A]	Mdu/u_mdu/res0_cZ[14]/F
11.426	1.853	tNET	FF	1	BSRAM_R10[16]	memq_memq_0_7/DI0

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	581	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	BSRAM_R10[16]	memq_memq_0_7/CLKA
11.683	-0.200	tUnc				memq_memq_0_7
11.648	-0.035	tSu		1	BSRAM_R10[16]	memq_memq_0_7

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 3.821, 40.046%; route: 5.489, 57.522%; tC2Q: 0.232, 2.431%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path6

Path Summary:

Slack	0.292
Data Arrival Time	11.357
Data Required Time	11.648
From	Mdu/u_mdu/reg0_fast_Z[12]
To	memq_memq_0_3
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.683	0.683	tINS	RR	581	IOT48[A]	clk_ibuf/O
1.883	1.201	tNET	RR	1	R48C43[0][B]	Mdu/u_mdu/reg0_fast_Z[12]/CLK
2.115	0.232	tC2Q	RF	8	R48C43[0][B]	Mdu/u_mdu/reg0_fast_Z[12]/Q
3.056	0.941	tNET	FF	1	R39C40[3][A]	Mdu/u_mdu/reg0_neg_axb_12_par_0_cp_cZ/I0
3.573	0.517	tINS	FF	1	R39C40[3][A]	Mdu/u_mdu/reg0_neg_axb_12_par_0_cp_cZ/F
4.771	1.198	tNET	FF	2	R33C29[2][B]	Mdu/u_mdu/reg0_neg_axb_12_par_cp_1/I0
5.341	0.570	tINS	FR	1	R33C29[2][B]	Mdu/u_mdu/reg0_neg_axb_12_par_cp_1/COUT
5.341	0.000	tNET	RR	2	R33C30[0][A]	Mdu/u_mdu/reg0_neg_axb_16_par_cp_1/CIN
5.376	0.035	tINS	RF	1	R33C30[0][A]	Mdu/u_mdu/reg0_neg_axb_16_par_cp_1/COUT
5.376	0.000	tNET	FF	2	R33C30[0][B]	Mdu/u_mdu/reg0_neg_axb_19_par_1/CIN
5.411	0.035	tINS	FF	1	R33C30[0][B]	Mdu/u_mdu/reg0_neg_axb_19_par_1/COUT
5.411	0.000	tNET	FF	2	R33C30[1][A]	Mdu/u_mdu/reg0_neg_axb_23_par_1/CIN
5.447	0.035	tINS	FF	1	R33C30[1][A]	Mdu/u_mdu/reg0_neg_axb_23_par_1/COUT
5.447	0.000	tNET	FF	2	R33C30[1][B]	Mdu/u_mdu/reg0_neg_axb_27_par_1/CIN
5.482	0.035	tINS	FF	1	R33C30[1][B]	Mdu/u_mdu/reg0_neg_axb_27_par_1/COUT
5.482	0.000	tNET	FF	2	R33C30[2][A]	Mdu/u_mdu/reg0_neg_axb_31_par_1/CIN
5.517	0.035	tINS	FF	1	R33C30[2][A]	Mdu/u_mdu/reg0_neg_axb_31_par_1/COUT
5.517	0.000	tNET	FF	2	R33C30[2][B]	Mdu/u_mdu/reg0_neg_cry_34_0/CIN
5.552	0.035	tINS	FF	1	R33C30[2][B]	Mdu/u_mdu/reg0_neg_cry_34_0/COUT
5.552	0.000	tNET	FF	2	R33C31[0][A]	Mdu/u_mdu/reg0_neg_cry_35_0/CIN
5.587	0.035	tINS	FF	1	R33C31[0][A]	Mdu/u_mdu/reg0_neg_cry_35_0/COUT
5.587	0.000	tNET	FF	2	R33C31[0][B]	Mdu/u_mdu/reg0_neg_cry_36_0/CIN
5.623	0.035	tINS	FF	1	R33C31[0][B]	Mdu/u_mdu/reg0_neg_cry_36_0/COUT
5.623	0.000	tNET	FF	2	R33C31[1][A]	Mdu/u_mdu/reg0_neg_cry_37_0/CIN
5.658	0.035	tINS	FF	1	R33C31[1][A]	Mdu/u_mdu/reg0_neg_cry_37_0/COUT
5.658	0.000	tNET	FF	2	R33C31[1][B]	Mdu/u_mdu/reg0_neg_cry_38_0/CIN
5.693	0.035	tINS	FF	1	R33C31[1][B]	Mdu/u_mdu/reg0_neg_cry_38_0/COUT
5.693	0.000	tNET	FF	2	R33C31[2][A]	Mdu/u_mdu/reg0_neg_cry_39_0/CIN
6.163	0.470	tINS	FF	1	R33C31[2][A]	Mdu/u_mdu/reg0_neg_cry_39_0/SUM
6.770	0.607	tNET	FF	1	R32C40[3][A]	Mdu/u_mdu/reg0_post_swap_2[7]/I2
7.141	0.371	tINS	FF	1	R32C40[3][A]	Mdu/u_mdu/reg0_post_swap_2[7]/F
7.141	0.000	tNET	FF	1	R32C40[3][A]	Mdu/u_mdu/reg0_post_swap_4[7]/I0
7.244	0.103	tINS	FF	2	R32C40[3][A]	Mdu/u_mdu/reg0_post_swap_4[7]/O
8.159	0.915	tNET	FF	1	R32C40[2][A]	Mdu/u_mdu/reg0_post_swap_5[7]/I1
8.612	0.453	tINS	FF	1	R32C40[2][A]	Mdu/u_mdu/reg0_post_swap_5[7]/F
9.296	0.684	tNET	FF	1	R33C45[2][A]	Mdu/u_mdu/res0_cZ[7]/I1
9.851	0.555	tINS	FF	3	R33C45[2][A]	Mdu/u_mdu/res0_cZ[7]/F
11.357	1.505	tNET	FF	1	BSRAM_R10[15]	memq_memq_0_3/DI1

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	581	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	BSRAM_R10[15]	memq_memq_0_3/CLKA
11.683	-0.200	tUnc				memq_memq_0_3
11.648	-0.035	tSu		1	BSRAM_R10[15]	memq_memq_0_3

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 3.391, 35.795%; route: 5.850, 61.756%; tC2Q: 0.232, 2.449%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path7

Path Summary:

Slack	0.397
Data Arrival Time	11.251
Data Required Time	11.648
From	Mdu/u_mdu/reg0_Z[26]
To	Mdu/u_mdu/reg0_Z[43]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.683	0.683	tINS	RR	581	IOT48[A]	clk_ibuf/O
1.883	1.201	tNET	RR	1	R42C40[1][B]	Mdu/u_mdu/reg0_Z[26]/CLK
2.115	0.232	tC2Q	RF	13	R42C40[1][B]	Mdu/u_mdu/reg0_Z[26]/Q
3.342	1.227	tNET	FF	1	R52C44[1][B]	Mdu/u_mdu/m27_0_03_1_cZ/I3
3.804	0.462	tINS	FR	1	R52C44[1][B]	Mdu/u_mdu/m27_0_03_1_cZ/F
3.805	0.001	tNET	RR	1	R52C44[3][B]	Mdu/u_mdu/m27_0_03_cZ/I1
4.360	0.555	tINS	RF	4	R52C44[3][B]	Mdu/u_mdu/m27_0_03_cZ/F
5.026	0.666	tNET	FF	1	R53C41[0][A]	Mdu/u_mdu/m27_2_03_1_0_cZ/I3
5.581	0.555	tINS	FF	2	R53C41[0][A]	Mdu/u_mdu/m27_2_03_1_0_cZ/F
5.999	0.418	tNET	FF	1	R52C39[0][A]	Mdu/u_mdu/m27_2_03_0_0_RNIFACJ/I1
6.554	0.555	tINS	FF	2	R52C39[0][A]	Mdu/u_mdu/m27_2_03_0_0_RNIFACJ/F
7.392	0.838	tNET	FF	1	R47C39[2][A]	Mdu/u_mdu/m43_4_03_0_0_cZ/I0
7.845	0.453	tINS	FF	1	R47C39[2][A]	Mdu/u_mdu/m43_4_03_0_0_cZ/F
8.938	1.093	tNET	FF	1	R46C34[1][B]	Mdu/u_mdu/reg0_exe_nx_m1_cZ[43]/I1
9.455	0.517	tINS	FF	1	R46C34[1][B]	Mdu/u_mdu/reg0_exe_nx_m1_cZ[43]/F
9.455	0.000	tNET	FF	1	R46C34[1][A]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[43]/I1
9.558	0.103	tINS	FF	1	R46C34[1][A]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[43]/O
10.789	1.232	tNET	FF	1	R31C37[2][A]	Mdu/u_mdu/reg0_nx_cZ[43]/I0
11.251	0.462	tINS	FR	1	R31C37[2][A]	Mdu/u_mdu/reg0_nx_cZ[43]/F
11.251	0.000	tNET	RR	1	R31C37[2][A]	Mdu/u_mdu/reg0_Z[43]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	581	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R31C37[2][A]	Mdu/u_mdu/reg0_Z[43]/CLK
11.683	-0.200	tUnc				Mdu/u_mdu/reg0_Z[43]
11.648	-0.035	tSu		1	R31C37[2][A]	Mdu/u_mdu/reg0_Z[43]

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	8
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 3.662, 39.090%; route: 5.474, 58.434%; tC2Q: 0.232, 2.476%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path8

Path Summary:

Slack	0.419
Data Arrival Time	11.230
Data Required Time	11.648
From	Mdu/u_mdu/reg0_fast_Z[3]
To	memq_memq_0_15
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.683	0.683	tINS	RR	581	IOT48[A]	clk_ibuf/O
1.883	1.201	tNET	RR	1	R34C39[0][A]	Mdu/u_mdu/reg0_fast_Z[3]/CLK
2.115	0.232	tC2Q	RF	7	R34C39[0][A]	Mdu/u_mdu/reg0_fast_Z[3]/Q
3.064	0.949	tNET	FF	1	R39C36[1][B]	Mdu/u_mdu/reg0_neg_axb_0_par_0_cp_cZ/I3
3.517	0.453	tINS	FF	1	R39C36[1][B]	Mdu/u_mdu/reg0_neg_axb_0_par_0_cp_cZ/F
4.415	0.899	tNET	FF	2	R42C33[1][A]	Mdu/u_mdu/reg0_neg_axb_0_par_cp_2/I0
4.985	0.570	tINS	FR	1	R42C33[1][A]	Mdu/u_mdu/reg0_neg_axb_0_par_cp_2/COUT
4.985	0.000	tNET	RR	2	R42C33[1][B]	Mdu/u_mdu/reg0_neg_axb_4_par_cp_2/CIN
5.021	0.035	tINS	RF	1	R42C33[1][B]	Mdu/u_mdu/reg0_neg_axb_4_par_cp_2/COUT
5.021	0.000	tNET	FF	2	R42C33[2][A]	Mdu/u_mdu/reg0_neg_axb_8_par_1/CIN
5.056	0.035	tINS	FF	1	R42C33[2][A]	Mdu/u_mdu/reg0_neg_axb_8_par_1/COUT
5.056	0.000	tNET	FF	2	R42C33[2][B]	Mdu/u_mdu/reg0_neg_axb_12_par_1/CIN
5.091	0.035	tINS	FF	1	R42C33[2][B]	Mdu/u_mdu/reg0_neg_axb_12_par_1/COUT
5.091	0.000	tNET	FF	2	R42C34[0][A]	Mdu/u_mdu/reg0_neg_axb_16_par_1/CIN
5.126	0.035	tINS	FF	1	R42C34[0][A]	Mdu/u_mdu/reg0_neg_axb_16_par_1/COUT
5.126	0.000	tNET	FF	2	R42C34[0][B]	Mdu/u_mdu/reg0_neg_cry_19_0/CIN
5.161	0.035	tINS	FF	1	R42C34[0][B]	Mdu/u_mdu/reg0_neg_cry_19_0/COUT
5.161	0.000	tNET	FF	2	R42C34[1][A]	Mdu/u_mdu/reg0_neg_cry_20_0/CIN
5.197	0.035	tINS	FF	1	R42C34[1][A]	Mdu/u_mdu/reg0_neg_cry_20_0/COUT
5.197	0.000	tNET	FF	2	R42C34[1][B]	Mdu/u_mdu/reg0_neg_cry_21_0/CIN
5.232	0.035	tINS	FF	1	R42C34[1][B]	Mdu/u_mdu/reg0_neg_cry_21_0/COUT
5.232	0.000	tNET	FF	2	R42C34[2][A]	Mdu/u_mdu/reg0_neg_cry_22_0/CIN
5.267	0.035	tINS	FF	1	R42C34[2][A]	Mdu/u_mdu/reg0_neg_cry_22_0/COUT
5.267	0.000	tNET	FF	2	R42C34[2][B]	Mdu/u_mdu/reg0_neg_cry_23_0/CIN
5.302	0.035	tINS	FF	1	R42C34[2][B]	Mdu/u_mdu/reg0_neg_cry_23_0/COUT
5.302	0.000	tNET	FF	2	R42C35[0][A]	Mdu/u_mdu/reg0_neg_cry_24_0/CIN
5.337	0.035	tINS	FF	1	R42C35[0][A]	Mdu/u_mdu/reg0_neg_cry_24_0/COUT
5.337	0.000	tNET	FF	2	R42C35[0][B]	Mdu/u_mdu/reg0_neg_cry_25_0/CIN
5.373	0.035	tINS	FF	1	R42C35[0][B]	Mdu/u_mdu/reg0_neg_cry_25_0/COUT
5.373	0.000	tNET	FF	2	R42C35[1][A]	Mdu/u_mdu/reg0_neg_cry_26_0/CIN
5.408	0.035	tINS	FF	1	R42C35[1][A]	Mdu/u_mdu/reg0_neg_cry_26_0/COUT
5.408	0.000	tNET	FF	2	R42C35[1][B]	Mdu/u_mdu/reg0_neg_cry_27_0/CIN
5.443	0.035	tINS	FF	1	R42C35[1][B]	Mdu/u_mdu/reg0_neg_cry_27_0/COUT
5.443	0.000	tNET	FF	2	R42C35[2][A]	Mdu/u_mdu/reg0_neg_cry_28_0/CIN
5.478	0.035	tINS	FF	1	R42C35[2][A]	Mdu/u_mdu/reg0_neg_cry_28_0/COUT
5.478	0.000	tNET	FF	2	R42C35[2][B]	Mdu/u_mdu/reg0_neg_cry_29_0/CIN
5.513	0.035	tINS	FF	1	R42C35[2][B]	Mdu/u_mdu/reg0_neg_cry_29_0/COUT
5.513	0.000	tNET	FF	2	R42C36[0][A]	Mdu/u_mdu/reg0_neg_cry_30_0/CIN
5.983	0.470	tINS	FF	3	R42C36[0][A]	Mdu/u_mdu/reg0_neg_cry_30_0/SUM
6.891	0.907	tNET	FF	1	R38C34[3][B]	Mdu/u_mdu/reg0_post_swap_1[30]/I2
7.408	0.517	tINS	FF	2	R38C34[3][B]	Mdu/u_mdu/reg0_post_swap_1[30]/F
8.096	0.688	tNET	FF	1	R33C32[3][B]	Mdu/u_mdu/reg0_post_swap_5[30]/I0
8.651	0.555	tINS	FF	1	R33C32[3][B]	Mdu/u_mdu/reg0_post_swap_5[30]/F
8.898	0.247	tNET	FF	1	R35C32[2][B]	Mdu/u_mdu/res0_cZ[30]/I1
9.453	0.555	tINS	FF	3	R35C32[2][B]	Mdu/u_mdu/res0_cZ[30]/F
11.230	1.776	tNET	FF	1	BSRAM_R36[22]	memq_memq_0_15/DI0

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	581	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	BSRAM_R36[22]	memq_memq_0_15/CLKA
11.683	-0.200	tUnc				memq_memq_0_15
11.648	-0.035	tSu		1	BSRAM_R36[22]	memq_memq_0_15

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	6
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 3.648, 39.031%; route: 5.467, 58.487%; tC2Q: 0.232, 2.482%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path9

Path Summary:

Slack	0.529
Data Arrival Time	11.119
Data Required Time	11.648
From	Mdu/u_mdu/func_reg_fast_Z[2]
To	Mdu/u_mdu/reg0_Z[7]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.683	0.683	tINS	RR	581	IOT48[A]	clk_ibuf/O
1.883	1.201	tNET	RR	1	R38C35[2][A]	Mdu/u_mdu/func_reg_fast_Z[2]/CLK
2.115	0.232	tC2Q	RF	9	R38C35[2][A]	Mdu/u_mdu/func_reg_fast_Z[2]/Q
2.808	0.692	tNET	FF	1	R43C35[3][B]	Mdu/u_mdu/adder_sum_s_0_sf_lofx_cZ/I0
3.363	0.555	tINS	FF	1	R43C35[3][B]	Mdu/u_mdu/adder_sum_s_0_sf_lofx_cZ/F
4.018	0.656	tNET	FF	2	R44C32[1][A]	Mdu/u_mdu/adder_sum_cry_0_0/I0
4.588	0.570	tINS	FR	1	R44C32[1][A]	Mdu/u_mdu/adder_sum_cry_0_0/COUT
4.588	0.000	tNET	RR	2	R44C32[1][B]	Mdu/u_mdu/adder_sum_cry_1_0/CIN
4.624	0.035	tINS	RF	1	R44C32[1][B]	Mdu/u_mdu/adder_sum_cry_1_0/COUT
4.624	0.000	tNET	FF	2	R44C32[2][A]	Mdu/u_mdu/adder_sum_cry_2_0/CIN
4.659	0.035	tINS	FF	1	R44C32[2][A]	Mdu/u_mdu/adder_sum_cry_2_0/COUT
4.659	0.000	tNET	FF	2	R44C32[2][B]	Mdu/u_mdu/adder_sum_cry_3_0/CIN
4.694	0.035	tINS	FF	1	R44C32[2][B]	Mdu/u_mdu/adder_sum_cry_3_0/COUT
4.694	0.000	tNET	FF	2	R44C33[0][A]	Mdu/u_mdu/adder_sum_cry_4_0/CIN
4.729	0.035	tINS	FF	1	R44C33[0][A]	Mdu/u_mdu/adder_sum_cry_4_0/COUT
4.729	0.000	tNET	FF	2	R44C33[0][B]	Mdu/u_mdu/adder_sum_cry_5_0/CIN
4.764	0.035	tINS	FF	1	R44C33[0][B]	Mdu/u_mdu/adder_sum_cry_5_0/COUT
4.764	0.000	tNET	FF	2	R44C33[1][A]	Mdu/u_mdu/adder_sum_cry_6_0/CIN
4.800	0.035	tINS	FF	1	R44C33[1][A]	Mdu/u_mdu/adder_sum_cry_6_0/COUT
4.800	0.000	tNET	FF	2	R44C33[1][B]	Mdu/u_mdu/adder_sum_cry_7_0/CIN
4.835	0.035	tINS	FF	1	R44C33[1][B]	Mdu/u_mdu/adder_sum_cry_7_0/COUT
4.835	0.000	tNET	FF	2	R44C33[2][A]	Mdu/u_mdu/adder_sum_cry_8_0/CIN
4.870	0.035	tINS	FF	1	R44C33[2][A]	Mdu/u_mdu/adder_sum_cry_8_0/COUT
4.870	0.000	tNET	FF	2	R44C33[2][B]	Mdu/u_mdu/adder_sum_cry_9_0/CIN
4.905	0.035	tINS	FF	1	R44C33[2][B]	Mdu/u_mdu/adder_sum_cry_9_0/COUT
4.905	0.000	tNET	FF	2	R44C34[0][A]	Mdu/u_mdu/adder_sum_cry_10_0/CIN
4.940	0.035	tINS	FF	1	R44C34[0][A]	Mdu/u_mdu/adder_sum_cry_10_0/COUT
4.940	0.000	tNET	FF	2	R44C34[0][B]	Mdu/u_mdu/adder_sum_cry_11_0/CIN
4.976	0.035	tINS	FF	1	R44C34[0][B]	Mdu/u_mdu/adder_sum_cry_11_0/COUT
4.976	0.000	tNET	FF	2	R44C34[1][A]	Mdu/u_mdu/adder_sum_cry_12_0/CIN
5.011	0.035	tINS	FF	1	R44C34[1][A]	Mdu/u_mdu/adder_sum_cry_12_0/COUT
5.011	0.000	tNET	FF	2	R44C34[1][B]	Mdu/u_mdu/adder_sum_cry_13_0/CIN
5.046	0.035	tINS	FF	1	R44C34[1][B]	Mdu/u_mdu/adder_sum_cry_13_0/COUT
5.046	0.000	tNET	FF	2	R44C34[2][A]	Mdu/u_mdu/adder_sum_cry_14_0/CIN
5.081	0.035	tINS	FF	1	R44C34[2][A]	Mdu/u_mdu/adder_sum_cry_14_0/COUT
5.081	0.000	tNET	FF	2	R44C34[2][B]	Mdu/u_mdu/adder_sum_cry_15_0/CIN
5.116	0.035	tINS	FF	1	R44C34[2][B]	Mdu/u_mdu/adder_sum_cry_15_0/COUT
5.116	0.000	tNET	FF	2	R44C35[0][A]	Mdu/u_mdu/adder_sum_cry_16_0/CIN
5.152	0.035	tINS	FF	1	R44C35[0][A]	Mdu/u_mdu/adder_sum_cry_16_0/COUT
5.152	0.000	tNET	FF	2	R44C35[0][B]	Mdu/u_mdu/adder_sum_cry_17_0/CIN
5.187	0.035	tINS	FF	1	R44C35[0][B]	Mdu/u_mdu/adder_sum_cry_17_0/COUT
5.187	0.000	tNET	FF	2	R44C35[1][A]	Mdu/u_mdu/adder_sum_cry_18_0/CIN
5.222	0.035	tINS	FF	1	R44C35[1][A]	Mdu/u_mdu/adder_sum_cry_18_0/COUT
5.222	0.000	tNET	FF	2	R44C35[1][B]	Mdu/u_mdu/adder_sum_cry_19_0/CIN
5.257	0.035	tINS	FF	1	R44C35[1][B]	Mdu/u_mdu/adder_sum_cry_19_0/COUT
5.257	0.000	tNET	FF	2	R44C35[2][A]	Mdu/u_mdu/adder_sum_cry_20_0/CIN
5.292	0.035	tINS	FF	1	R44C35[2][A]	Mdu/u_mdu/adder_sum_cry_20_0/COUT
5.292	0.000	tNET	FF	2	R44C35[2][B]	Mdu/u_mdu/adder_sum_cry_21_0/CIN
5.328	0.035	tINS	FF	1	R44C35[2][B]	Mdu/u_mdu/adder_sum_cry_21_0/COUT
5.328	0.000	tNET	FF	2	R44C36[0][A]	Mdu/u_mdu/adder_sum_cry_22_0/CIN
5.363	0.035	tINS	FF	1	R44C36[0][A]	Mdu/u_mdu/adder_sum_cry_22_0/COUT
5.363	0.000	tNET	FF	2	R44C36[0][B]	Mdu/u_mdu/adder_sum_cry_23_0/CIN
5.398	0.035	tINS	FF	1	R44C36[0][B]	Mdu/u_mdu/adder_sum_cry_23_0/COUT
5.398	0.000	tNET	FF	2	R44C36[1][A]	Mdu/u_mdu/adder_sum_cry_24_0/CIN
5.433	0.035	tINS	FF	1	R44C36[1][A]	Mdu/u_mdu/adder_sum_cry_24_0/COUT
5.433	0.000	tNET	FF	2	R44C36[1][B]	Mdu/u_mdu/adder_sum_cry_25_0/CIN
5.468	0.035	tINS	FF	1	R44C36[1][B]	Mdu/u_mdu/adder_sum_cry_25_0/COUT
5.468	0.000	tNET	FF	2	R44C36[2][A]	Mdu/u_mdu/adder_sum_cry_26_0/CIN
5.504	0.035	tINS	FF	1	R44C36[2][A]	Mdu/u_mdu/adder_sum_cry_26_0/COUT
5.504	0.000	tNET	FF	2	R44C36[2][B]	Mdu/u_mdu/adder_sum_cry_27_0/CIN
5.539	0.035	tINS	FF	1	R44C36[2][B]	Mdu/u_mdu/adder_sum_cry_27_0/COUT
5.539	0.000	tNET	FF	2	R44C37[0][A]	Mdu/u_mdu/adder_sum_cry_28_0/CIN
5.574	0.035	tINS	FF	1	R44C37[0][A]	Mdu/u_mdu/adder_sum_cry_28_0/COUT
5.574	0.000	tNET	FF	2	R44C37[0][B]	Mdu/u_mdu/adder_sum_cry_29_0/CIN
5.609	0.035	tINS	FF	1	R44C37[0][B]	Mdu/u_mdu/adder_sum_cry_29_0/COUT
5.609	0.000	tNET	FF	2	R44C37[1][A]	Mdu/u_mdu/adder_sum_cry_30_0/CIN
5.644	0.035	tINS	FF	1	R44C37[1][A]	Mdu/u_mdu/adder_sum_cry_30_0/COUT
5.644	0.000	tNET	FF	2	R44C37[1][B]	Mdu/u_mdu/adder_sum_cry_31_0/CIN
5.680	0.035	tINS	FF	1	R44C37[1][B]	Mdu/u_mdu/adder_sum_cry_31_0/COUT
5.680	0.000	tNET	FF	2	R44C37[2][A]	Mdu/u_mdu/adder_sum_s_32_0/CIN
6.150	0.470	tINS	FF	6	R44C37[2][A]	Mdu/u_mdu/adder_sum_s_32_0/SUM
6.857	0.708	tNET	FF	1	R46C32[1][A]	Mdu/u_mdu/reg0_exe_nx_ss0_cZ/I0
7.310	0.453	tINS	FF	50	R46C32[1][A]	Mdu/u_mdu/reg0_exe_nx_ss0_cZ/F
8.143	0.833	tNET	FF	1	R41C36[3][A]	Mdu/u_mdu/reg0_exe_nx_m1_cZ[7]/I3
8.596	0.453	tINS	FF	1	R41C36[3][A]	Mdu/u_mdu/reg0_exe_nx_m1_cZ[7]/F
9.086	0.490	tNET	FF	1	R39C38[3][B]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[7]/I1
9.539	0.453	tINS	FF	1	R39C38[3][B]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[7]/F
10.195	0.656	tNET	FF	1	R34C38[2][B]	Mdu/u_mdu/reg0_exe_nx_cZ[7]/I3
10.566	0.371	tINS	FF	1	R34C38[2][B]	Mdu/u_mdu/reg0_exe_nx_cZ[7]/F
10.570	0.004	tNET	FF	1	R34C38[1][B]	Mdu/u_mdu/reg0_nx_cZ[7]/I0
11.119	0.549	tINS	FR	1	R34C38[1][B]	Mdu/u_mdu/reg0_nx_cZ[7]/F
11.119	0.000	tNET	RR	1	R34C38[1][B]	Mdu/u_mdu/reg0_Z[7]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	581	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R34C38[1][B]	Mdu/u_mdu/reg0_Z[7]/CLK
11.683	-0.200	tUnc				Mdu/u_mdu/reg0_Z[7]
11.648	-0.035	tSu		1	R34C38[1][B]	Mdu/u_mdu/reg0_Z[7]

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	8
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 4.965, 53.759%; route: 4.039, 43.729%; tC2Q: 0.232, 2.512%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path10

Path Summary:

Slack	0.663
Data Arrival Time	10.986
Data Required Time	11.648
From	Mdu/u_mdu/reg0_fast_Z[3]
To	memq_memq_0_0
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.683	0.683	tINS	RR	581	IOT48[A]	clk_ibuf/O
1.883	1.201	tNET	RR	1	R34C39[0][A]	Mdu/u_mdu/reg0_fast_Z[3]/CLK
2.115	0.232	tC2Q	RF	7	R34C39[0][A]	Mdu/u_mdu/reg0_fast_Z[3]/Q
3.064	0.949	tNET	FF	1	R39C36[1][B]	Mdu/u_mdu/reg0_neg_axb_0_par_0_cp_cZ/I3
3.517	0.453	tINS	FF	1	R39C36[1][B]	Mdu/u_mdu/reg0_neg_axb_0_par_0_cp_cZ/F
4.415	0.899	tNET	FF	2	R42C33[1][A]	Mdu/u_mdu/reg0_neg_axb_0_par_cp_2/I0
4.985	0.570	tINS	FR	1	R42C33[1][A]	Mdu/u_mdu/reg0_neg_axb_0_par_cp_2/COUT
4.985	0.000	tNET	RR	2	R42C33[1][B]	Mdu/u_mdu/reg0_neg_axb_4_par_cp_2/CIN
5.021	0.035	tINS	RF	1	R42C33[1][B]	Mdu/u_mdu/reg0_neg_axb_4_par_cp_2/COUT
5.021	0.000	tNET	FF	2	R42C33[2][A]	Mdu/u_mdu/reg0_neg_axb_8_par_1/CIN
5.056	0.035	tINS	FF	1	R42C33[2][A]	Mdu/u_mdu/reg0_neg_axb_8_par_1/COUT
5.056	0.000	tNET	FF	2	R42C33[2][B]	Mdu/u_mdu/reg0_neg_axb_12_par_1/CIN
5.091	0.035	tINS	FF	1	R42C33[2][B]	Mdu/u_mdu/reg0_neg_axb_12_par_1/COUT
5.091	0.000	tNET	FF	2	R42C34[0][A]	Mdu/u_mdu/reg0_neg_axb_16_par_1/CIN
5.126	0.035	tINS	FF	1	R42C34[0][A]	Mdu/u_mdu/reg0_neg_axb_16_par_1/COUT
5.126	0.000	tNET	FF	2	R42C34[0][B]	Mdu/u_mdu/reg0_neg_cry_19_0/CIN
5.161	0.035	tINS	FF	1	R42C34[0][B]	Mdu/u_mdu/reg0_neg_cry_19_0/COUT
5.161	0.000	tNET	FF	2	R42C34[1][A]	Mdu/u_mdu/reg0_neg_cry_20_0/CIN
5.197	0.035	tINS	FF	1	R42C34[1][A]	Mdu/u_mdu/reg0_neg_cry_20_0/COUT
5.197	0.000	tNET	FF	2	R42C34[1][B]	Mdu/u_mdu/reg0_neg_cry_21_0/CIN
5.232	0.035	tINS	FF	1	R42C34[1][B]	Mdu/u_mdu/reg0_neg_cry_21_0/COUT
5.232	0.000	tNET	FF	2	R42C34[2][A]	Mdu/u_mdu/reg0_neg_cry_22_0/CIN
5.267	0.035	tINS	FF	1	R42C34[2][A]	Mdu/u_mdu/reg0_neg_cry_22_0/COUT
5.267	0.000	tNET	FF	2	R42C34[2][B]	Mdu/u_mdu/reg0_neg_cry_23_0/CIN
5.302	0.035	tINS	FF	1	R42C34[2][B]	Mdu/u_mdu/reg0_neg_cry_23_0/COUT
5.302	0.000	tNET	FF	2	R42C35[0][A]	Mdu/u_mdu/reg0_neg_cry_24_0/CIN
5.337	0.035	tINS	FF	1	R42C35[0][A]	Mdu/u_mdu/reg0_neg_cry_24_0/COUT
5.337	0.000	tNET	FF	2	R42C35[0][B]	Mdu/u_mdu/reg0_neg_cry_25_0/CIN
5.373	0.035	tINS	FF	1	R42C35[0][B]	Mdu/u_mdu/reg0_neg_cry_25_0/COUT
5.373	0.000	tNET	FF	2	R42C35[1][A]	Mdu/u_mdu/reg0_neg_cry_26_0/CIN
5.408	0.035	tINS	FF	1	R42C35[1][A]	Mdu/u_mdu/reg0_neg_cry_26_0/COUT
5.408	0.000	tNET	FF	2	R42C35[1][B]	Mdu/u_mdu/reg0_neg_cry_27_0/CIN
5.443	0.035	tINS	FF	1	R42C35[1][B]	Mdu/u_mdu/reg0_neg_cry_27_0/COUT
5.443	0.000	tNET	FF	2	R42C35[2][A]	Mdu/u_mdu/reg0_neg_cry_28_0/CIN
5.478	0.035	tINS	FF	1	R42C35[2][A]	Mdu/u_mdu/reg0_neg_cry_28_0/COUT
5.478	0.000	tNET	FF	2	R42C35[2][B]	Mdu/u_mdu/reg0_neg_cry_29_0/CIN
5.513	0.035	tINS	FF	1	R42C35[2][B]	Mdu/u_mdu/reg0_neg_cry_29_0/COUT
5.513	0.000	tNET	FF	2	R42C36[0][A]	Mdu/u_mdu/reg0_neg_cry_30_0/CIN
5.549	0.035	tINS	FF	1	R42C36[0][A]	Mdu/u_mdu/reg0_neg_cry_30_0/COUT
5.549	0.000	tNET	FF	2	R42C36[0][B]	Mdu/u_mdu/reg0_neg_cry_31_0/CIN
5.584	0.035	tINS	FF	1	R42C36[0][B]	Mdu/u_mdu/reg0_neg_cry_31_0/COUT
5.584	0.000	tNET	FF	2	R42C36[1][A]	Mdu/u_mdu/reg0_neg_cry_32_0/CIN
6.054	0.470	tINS	FF	1	R42C36[1][A]	Mdu/u_mdu/reg0_neg_cry_32_0/SUM
6.738	0.684	tNET	FF	1	R34C39[3][A]	Mdu/u_mdu/reg0_post_swap_2[0]/I2
7.255	0.517	tINS	FF	1	R34C39[3][A]	Mdu/u_mdu/reg0_post_swap_2[0]/F
7.255	0.000	tNET	FF	1	R34C39[3][A]	Mdu/u_mdu/reg0_post_swap_4[0]/I0
7.358	0.103	tINS	FF	1	R34C39[3][A]	Mdu/u_mdu/reg0_post_swap_4[0]/O
7.611	0.253	tNET	FF	1	R34C39[2][B]	Mdu/u_mdu/reg0_post_swap_5[0]/I1
7.982	0.371	tINS	FF	3	R34C39[2][B]	Mdu/u_mdu/reg0_post_swap_5[0]/F
9.035	1.053	tNET	FF	1	R35C38[2][A]	Mdu/u_mdu/res0_cZ[0]/I1
9.590	0.555	tINS	FF	3	R35C38[2][A]	Mdu/u_mdu/res0_cZ[0]/F
10.986	1.396	tNET	FF	1	BSRAM_R54[15]	memq_memq_0_0/DI0

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	581	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	BSRAM_R54[15]	memq_memq_0_0/CLKA
11.683	-0.200	tUnc				memq_memq_0_0
11.648	-0.035	tSu		1	BSRAM_R54[15]	memq_memq_0_0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 3.637, 39.960%; route: 5.233, 57.492%; tC2Q: 0.232, 2.549%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path11

Path Summary:

Slack	0.663
Data Arrival Time	10.985
Data Required Time	11.648
From	Mdu/u_mdu/reg0_fast_Z[12]
To	Mdu/u_mdu/reg0_Z[16]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.683	0.683	tINS	RR	581	IOT48[A]	clk_ibuf/O
1.883	1.201	tNET	RR	1	R48C43[0][B]	Mdu/u_mdu/reg0_fast_Z[12]/CLK
2.115	0.232	tC2Q	RF	8	R48C43[0][B]	Mdu/u_mdu/reg0_fast_Z[12]/Q
3.056	0.941	tNET	FF	1	R39C40[3][A]	Mdu/u_mdu/reg0_neg_axb_12_par_0_cp_cZ/I0
3.573	0.517	tINS	FF	1	R39C40[3][A]	Mdu/u_mdu/reg0_neg_axb_12_par_0_cp_cZ/F
4.771	1.198	tNET	FF	2	R33C29[2][B]	Mdu/u_mdu/reg0_neg_axb_12_par_cp_1/I0
5.341	0.570	tINS	FR	1	R33C29[2][B]	Mdu/u_mdu/reg0_neg_axb_12_par_cp_1/COUT
5.341	0.000	tNET	RR	2	R33C30[0][A]	Mdu/u_mdu/reg0_neg_axb_16_par_cp_1/CIN
5.376	0.035	tINS	RF	1	R33C30[0][A]	Mdu/u_mdu/reg0_neg_axb_16_par_cp_1/COUT
5.376	0.000	tNET	FF	2	R33C30[0][B]	Mdu/u_mdu/reg0_neg_axb_19_par_1/CIN
5.411	0.035	tINS	FF	1	R33C30[0][B]	Mdu/u_mdu/reg0_neg_axb_19_par_1/COUT
5.411	0.000	tNET	FF	2	R33C30[1][A]	Mdu/u_mdu/reg0_neg_axb_23_par_1/CIN
5.447	0.035	tINS	FF	1	R33C30[1][A]	Mdu/u_mdu/reg0_neg_axb_23_par_1/COUT
5.447	0.000	tNET	FF	2	R33C30[1][B]	Mdu/u_mdu/reg0_neg_axb_27_par_1/CIN
5.482	0.035	tINS	FF	1	R33C30[1][B]	Mdu/u_mdu/reg0_neg_axb_27_par_1/COUT
5.482	0.000	tNET	FF	2	R33C30[2][A]	Mdu/u_mdu/reg0_neg_axb_31_par_1/CIN
5.517	0.035	tINS	FF	1	R33C30[2][A]	Mdu/u_mdu/reg0_neg_axb_31_par_1/COUT
5.517	0.000	tNET	FF	2	R33C30[2][B]	Mdu/u_mdu/reg0_neg_cry_34_0/CIN
5.552	0.035	tINS	FF	1	R33C30[2][B]	Mdu/u_mdu/reg0_neg_cry_34_0/COUT
5.552	0.000	tNET	FF	2	R33C31[0][A]	Mdu/u_mdu/reg0_neg_cry_35_0/CIN
5.587	0.035	tINS	FF	1	R33C31[0][A]	Mdu/u_mdu/reg0_neg_cry_35_0/COUT
5.587	0.000	tNET	FF	2	R33C31[0][B]	Mdu/u_mdu/reg0_neg_cry_36_0/CIN
5.623	0.035	tINS	FF	1	R33C31[0][B]	Mdu/u_mdu/reg0_neg_cry_36_0/COUT
5.623	0.000	tNET	FF	2	R33C31[1][A]	Mdu/u_mdu/reg0_neg_cry_37_0/CIN
5.658	0.035	tINS	FF	1	R33C31[1][A]	Mdu/u_mdu/reg0_neg_cry_37_0/COUT
5.658	0.000	tNET	FF	2	R33C31[1][B]	Mdu/u_mdu/reg0_neg_cry_38_0/CIN
5.693	0.035	tINS	FF	1	R33C31[1][B]	Mdu/u_mdu/reg0_neg_cry_38_0/COUT
5.693	0.000	tNET	FF	2	R33C31[2][A]	Mdu/u_mdu/reg0_neg_cry_39_0/CIN
5.728	0.035	tINS	FF	1	R33C31[2][A]	Mdu/u_mdu/reg0_neg_cry_39_0/COUT
5.728	0.000	tNET	FF	2	R33C31[2][B]	Mdu/u_mdu/reg0_neg_cry_40_0/CIN
5.763	0.035	tINS	FF	1	R33C31[2][B]	Mdu/u_mdu/reg0_neg_cry_40_0/COUT
5.763	0.000	tNET	FF	2	R33C32[0][A]	Mdu/u_mdu/reg0_neg_cry_41_0/CIN
5.799	0.035	tINS	FF	1	R33C32[0][A]	Mdu/u_mdu/reg0_neg_cry_41_0/COUT
5.799	0.000	tNET	FF	2	R33C32[0][B]	Mdu/u_mdu/reg0_neg_cry_42_0/CIN
5.834	0.035	tINS	FF	1	R33C32[0][B]	Mdu/u_mdu/reg0_neg_cry_42_0/COUT
5.834	0.000	tNET	FF	2	R33C32[1][A]	Mdu/u_mdu/reg0_neg_cry_43_0/CIN
5.869	0.035	tINS	FF	1	R33C32[1][A]	Mdu/u_mdu/reg0_neg_cry_43_0/COUT
5.869	0.000	tNET	FF	2	R33C32[1][B]	Mdu/u_mdu/reg0_neg_cry_44_0/CIN
5.904	0.035	tINS	FF	1	R33C32[1][B]	Mdu/u_mdu/reg0_neg_cry_44_0/COUT
5.904	0.000	tNET	FF	2	R33C32[2][A]	Mdu/u_mdu/reg0_neg_cry_45_0/CIN
5.939	0.035	tINS	FF	1	R33C32[2][A]	Mdu/u_mdu/reg0_neg_cry_45_0/COUT
5.939	0.000	tNET	FF	2	R33C32[2][B]	Mdu/u_mdu/reg0_neg_cry_46_0/CIN
5.975	0.035	tINS	FF	1	R33C32[2][B]	Mdu/u_mdu/reg0_neg_cry_46_0/COUT
5.975	0.000	tNET	FF	2	R33C33[0][A]	Mdu/u_mdu/reg0_neg_cry_47_0/CIN
6.010	0.035	tINS	FF	1	R33C33[0][A]	Mdu/u_mdu/reg0_neg_cry_47_0/COUT
6.010	0.000	tNET	FF	2	R33C33[0][B]	Mdu/u_mdu/reg0_neg_cry_48_0/CIN
6.480	0.470	tINS	FF	1	R33C33[0][B]	Mdu/u_mdu/reg0_neg_cry_48_0/SUM
7.136	0.656	tNET	FF	1	R33C37[2][A]	Mdu/u_mdu/reg0_post_swap_2[16]/I2
7.589	0.453	tINS	FF	1	R33C37[2][A]	Mdu/u_mdu/reg0_post_swap_2[16]/F
7.589	0.000	tNET	FF	1	R33C37[2][A]	Mdu/u_mdu/reg0_post_swap_4[16]/I0
7.692	0.103	tINS	FF	1	R33C37[2][A]	Mdu/u_mdu/reg0_post_swap_4[16]/O
8.305	0.613	tNET	FF	1	R33C43[1][B]	Mdu/u_mdu/reg0_post_swap_5[16]/I1
8.758	0.453	tINS	FF	2	R33C43[1][B]	Mdu/u_mdu/reg0_post_swap_5[16]/F
9.722	0.964	tNET	FF	1	R51C44[3][A]	Mdu/u_mdu/reg0_nx_1_cZ[16]/I0
10.292	0.570	tINS	FR	1	R51C44[3][A]	Mdu/u_mdu/reg0_nx_1_cZ[16]/F
10.436	0.144	tNET	RR	1	R51C44[2][B]	Mdu/u_mdu/reg0_nx_cZ[16]/I1
10.985	0.549	tINS	RR	1	R51C44[2][B]	Mdu/u_mdu/reg0_nx_cZ[16]/F
10.985	0.000	tNET	RR	1	R51C44[2][B]	Mdu/u_mdu/reg0_Z[16]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	581	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R51C44[2][B]	Mdu/u_mdu/reg0_Z[16]/CLK
11.683	-0.200	tUnc				Mdu/u_mdu/reg0_Z[16]
11.648	-0.035	tSu		1	R51C44[2][B]	Mdu/u_mdu/reg0_Z[16]

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	8
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 4.354, 47.834%; route: 4.516, 49.618%; tC2Q: 0.232, 2.549%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path12

Path Summary:

Slack	0.677
Data Arrival Time	10.971
Data Required Time	11.648
From	Mdu/u_mdu/div_shift_number_Z[1]
To	Mdu/u_mdu/reg0_fast_Z[28]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.683	0.683	tINS	RR	581	IOT48[A]	clk_ibuf/O
1.883	1.201	tNET	RR	1	R48C37[1][B]	Mdu/u_mdu/div_shift_number_Z[1]/CLK
2.115	0.232	tC2Q	RF	114	R48C37[1][B]	Mdu/u_mdu/div_shift_number_Z[1]/Q
3.289	1.173	tNET	FF	1	R41C40[2][A]	Mdu/u_mdu/m12_0_03_1_cZ/I1
3.838	0.549	tINS	FR	1	R41C40[2][A]	Mdu/u_mdu/m12_0_03_1_cZ/F
4.010	0.172	tNET	RR	1	R41C39[2][B]	Mdu/u_mdu/m12_0_03_cZ/I1
4.463	0.453	tINS	RF	4	R41C39[2][B]	Mdu/u_mdu/m12_0_03_cZ/F
5.403	0.940	tNET	FF	1	R47C36[1][B]	Mdu/u_mdu/m12_2_03_m1_e_1_cZ/I3
5.973	0.570	tINS	FR	2	R47C36[1][B]	Mdu/u_mdu/m12_2_03_m1_e_1_cZ/F
5.976	0.003	tNET	RR	1	R47C36[0][B]	Mdu/u_mdu/m12_2_03_m1_e_0_RNI7HT5/I1
6.531	0.555	tINS	RF	3	R47C36[0][B]	Mdu/u_mdu/m12_2_03_m1_e_0_RNI7HT5/F
7.029	0.499	tNET	FF	1	R47C40[0][A]	Mdu/u_mdu/m28_4_01_cZ/I1
7.584	0.555	tINS	FF	1	R47C40[0][A]	Mdu/u_mdu/m28_4_01_cZ/F
8.539	0.955	tNET	FF	1	R38C34[2][B]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[28]/I2
9.088	0.549	tINS	FR	1	R38C34[2][B]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[28]/F
9.090	0.001	tNET	RR	1	R38C34[1][B]	Mdu/u_mdu/reg0_exe_nx_cZ[28]/I3
9.607	0.517	tINS	RF	2	R38C34[1][B]	Mdu/u_mdu/reg0_exe_nx_cZ[28]/F
10.401	0.795	tNET	FF	1	R42C39[1][A]	Mdu/u_mdu/reg0_nx_fast_cZ[28]/I0
10.971	0.570	tINS	FR	1	R42C39[1][A]	Mdu/u_mdu/reg0_nx_fast_cZ[28]/F
10.971	0.000	tNET	RR	1	R42C39[1][A]	Mdu/u_mdu/reg0_fast_Z[28]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	581	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R42C39[1][A]	Mdu/u_mdu/reg0_fast_Z[28]/CLK
11.683	-0.200	tUnc				Mdu/u_mdu/reg0_fast_Z[28]
11.648	-0.035	tSu		1	R42C39[1][A]	Mdu/u_mdu/reg0_fast_Z[28]

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	8
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 4.318, 47.513%; route: 4.538, 49.935%; tC2Q: 0.232, 2.553%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path13

Path Summary:

Slack	0.677
Data Arrival Time	10.971
Data Required Time	11.648
From	Mdu/u_mdu/div_shift_number_Z[1]
To	Mdu/u_mdu/reg0_Z[28]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.683	0.683	tINS	RR	581	IOT48[A]	clk_ibuf/O
1.883	1.201	tNET	RR	1	R48C37[1][B]	Mdu/u_mdu/div_shift_number_Z[1]/CLK
2.115	0.232	tC2Q	RF	114	R48C37[1][B]	Mdu/u_mdu/div_shift_number_Z[1]/Q
3.289	1.173	tNET	FF	1	R41C40[2][A]	Mdu/u_mdu/m12_0_03_1_cZ/I1
3.838	0.549	tINS	FR	1	R41C40[2][A]	Mdu/u_mdu/m12_0_03_1_cZ/F
4.010	0.172	tNET	RR	1	R41C39[2][B]	Mdu/u_mdu/m12_0_03_cZ/I1
4.463	0.453	tINS	RF	4	R41C39[2][B]	Mdu/u_mdu/m12_0_03_cZ/F
5.403	0.940	tNET	FF	1	R47C36[1][B]	Mdu/u_mdu/m12_2_03_m1_e_1_cZ/I3
5.973	0.570	tINS	FR	2	R47C36[1][B]	Mdu/u_mdu/m12_2_03_m1_e_1_cZ/F
5.976	0.003	tNET	RR	1	R47C36[0][B]	Mdu/u_mdu/m12_2_03_m1_e_0_RNI7HT5/I1
6.531	0.555	tINS	RF	3	R47C36[0][B]	Mdu/u_mdu/m12_2_03_m1_e_0_RNI7HT5/F
7.029	0.499	tNET	FF	1	R47C40[0][A]	Mdu/u_mdu/m28_4_01_cZ/I1
7.584	0.555	tINS	FF	1	R47C40[0][A]	Mdu/u_mdu/m28_4_01_cZ/F
8.539	0.955	tNET	FF	1	R38C34[2][B]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[28]/I2
9.088	0.549	tINS	FR	1	R38C34[2][B]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[28]/F
9.090	0.001	tNET	RR	1	R38C34[1][B]	Mdu/u_mdu/reg0_exe_nx_cZ[28]/I3
9.607	0.517	tINS	RF	2	R38C34[1][B]	Mdu/u_mdu/reg0_exe_nx_cZ[28]/F
10.401	0.795	tNET	FF	1	R42C39[1][B]	Mdu/u_mdu/reg0_nx_cZ[28]/I0
10.971	0.570	tINS	FR	1	R42C39[1][B]	Mdu/u_mdu/reg0_nx_cZ[28]/F
10.971	0.000	tNET	RR	1	R42C39[1][B]	Mdu/u_mdu/reg0_Z[28]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	581	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R42C39[1][B]	Mdu/u_mdu/reg0_Z[28]/CLK
11.683	-0.200	tUnc				Mdu/u_mdu/reg0_Z[28]
11.648	-0.035	tSu		1	R42C39[1][B]	Mdu/u_mdu/reg0_Z[28]

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	8
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 4.318, 47.513%; route: 4.538, 49.935%; tC2Q: 0.232, 2.553%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path14

Path Summary:

Slack	0.710
Data Arrival Time	10.938
Data Required Time	11.648
From	Mdu/u_mdu/reg0_Z[49]
To	memq_memq_0_14
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.683	0.683	tINS	RR	581	IOT48[A]	clk_ibuf/O
1.883	1.201	tNET	RR	1	R43C40[0][A]	Mdu/u_mdu/reg0_Z[49]/CLK
2.115	0.232	tC2Q	RF	13	R43C40[0][A]	Mdu/u_mdu/reg0_Z[49]/Q
3.556	1.441	tNET	FF	1	R33C36[1][A]	Mdu/u_mdu/reg0_neg_axb_46_par_0_cZ/I3
4.073	0.517	tINS	FF	1	R33C36[1][A]	Mdu/u_mdu/reg0_neg_axb_46_par_0_cZ/F
4.879	0.806	tNET	FF	2	R34C36[1][A]	Mdu/u_mdu/reg0_neg_axb_46_par_1/I0
5.449	0.570	tINS	FR	1	R34C36[1][A]	Mdu/u_mdu/reg0_neg_axb_46_par_1/COUT
5.449	0.000	tNET	RR	2	R34C36[1][B]	Mdu/u_mdu/reg0_neg_axb_50_par_1/CIN
5.484	0.035	tINS	RF	1	R34C36[1][B]	Mdu/u_mdu/reg0_neg_axb_50_par_1/COUT
5.484	0.000	tNET	FF	2	R34C36[2][A]	Mdu/u_mdu/reg0_neg_cry_54_0/CIN
5.519	0.035	tINS	FF	1	R34C36[2][A]	Mdu/u_mdu/reg0_neg_cry_54_0/COUT
5.519	0.000	tNET	FF	2	R34C36[2][B]	Mdu/u_mdu/reg0_neg_cry_55_0/CIN
5.555	0.035	tINS	FF	1	R34C36[2][B]	Mdu/u_mdu/reg0_neg_cry_55_0/COUT
5.555	0.000	tNET	FF	2	R34C37[0][A]	Mdu/u_mdu/reg0_neg_cry_56_0/CIN
5.590	0.035	tINS	FF	1	R34C37[0][A]	Mdu/u_mdu/reg0_neg_cry_56_0/COUT
5.590	0.000	tNET	FF	2	R34C37[0][B]	Mdu/u_mdu/reg0_neg_cry_57_0/CIN
5.625	0.035	tINS	FF	1	R34C37[0][B]	Mdu/u_mdu/reg0_neg_cry_57_0/COUT
5.625	0.000	tNET	FF	2	R34C37[1][A]	Mdu/u_mdu/reg0_neg_cry_58_0/CIN
5.660	0.035	tINS	FF	1	R34C37[1][A]	Mdu/u_mdu/reg0_neg_cry_58_0/COUT
5.660	0.000	tNET	FF	2	R34C37[1][B]	Mdu/u_mdu/reg0_neg_cry_59_0/CIN
5.695	0.035	tINS	FF	1	R34C37[1][B]	Mdu/u_mdu/reg0_neg_cry_59_0/COUT
5.695	0.000	tNET	FF	2	R34C37[2][A]	Mdu/u_mdu/reg0_neg_cry_60_0/CIN
5.731	0.035	tINS	FF	1	R34C37[2][A]	Mdu/u_mdu/reg0_neg_cry_60_0/COUT
5.731	0.000	tNET	FF	2	R34C37[2][B]	Mdu/u_mdu/reg0_neg_cry_61_0/CIN
6.201	0.470	tINS	FF	1	R34C37[2][B]	Mdu/u_mdu/reg0_neg_cry_61_0/SUM
6.614	0.413	tNET	FF	1	R35C35[3][A]	Mdu/u_mdu/reg0_post_swap_2[29]/I2
7.067	0.453	tINS	FF	1	R35C35[3][A]	Mdu/u_mdu/reg0_post_swap_2[29]/F
7.067	0.000	tNET	FF	1	R35C35[3][A]	Mdu/u_mdu/reg0_post_swap_4[29]/I0
7.170	0.103	tINS	FF	1	R35C35[3][A]	Mdu/u_mdu/reg0_post_swap_4[29]/O
7.815	0.645	tNET	FF	1	R39C35[2][B]	Mdu/u_mdu/reg0_post_swap_5[29]/I1
8.332	0.517	tINS	FF	2	R39C35[2][B]	Mdu/u_mdu/reg0_post_swap_5[29]/F
8.750	0.418	tNET	FF	1	R38C36[3][B]	Mdu/u_mdu/res0_cZ[29]/I1
9.267	0.517	tINS	FF	3	R38C36[3][B]	Mdu/u_mdu/res0_cZ[29]/F
10.938	1.672	tNET	FF	1	BSRAM_R36[21]	memq_memq_0_14/DI1

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	581	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	BSRAM_R36[21]	memq_memq_0_14/CLKA
11.683	-0.200	tUnc				memq_memq_0_14
11.648	-0.035	tSu		1	BSRAM_R36[21]	memq_memq_0_14

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 3.429, 37.863%; route: 5.395, 59.575%; tC2Q: 0.232, 2.562%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path15

Path Summary:

Slack	0.754
Data Arrival Time	10.895
Data Required Time	11.648
From	Mdu/u_mdu/reg0_Z[8]
To	Mdu/u_mdu/reg0_31_rep1_Z
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.683	0.683	tINS	RR	581	IOT48[A]	clk_ibuf/O
1.883	1.201	tNET	RR	1	R34C41[1][A]	Mdu/u_mdu/reg0_Z[8]/CLK
2.115	0.232	tC2Q	RF	18	R34C41[1][A]	Mdu/u_mdu/reg0_Z[8]/Q
3.344	1.229	tNET	FF	1	R52C42[3][B]	Mdu/u_mdu/m11_0_03_1_cZ/I2
3.914	0.570	tINS	FR	1	R52C42[3][B]	Mdu/u_mdu/m11_0_03_1_cZ/F
3.915	0.001	tNET	RR	1	R52C42[3][A]	Mdu/u_mdu/m11_0_03_cZ/I1
4.432	0.517	tINS	RF	4	R52C42[3][A]	Mdu/u_mdu/m11_0_03_cZ/F
5.126	0.694	tNET	FF	1	R52C36[0][B]	Mdu/u_mdu/m15_2_03_1_0_cZ/I2
5.681	0.555	tINS	FF	2	R52C36[0][B]	Mdu/u_mdu/m15_2_03_1_0_cZ/F
6.612	0.931	tNET	FF	1	R47C32[3][B]	Mdu/u_mdu/m15_2_03_0_0_RNI9I0C/I1
7.167	0.555	tINS	FF	3	R47C32[3][B]	Mdu/u_mdu/m15_2_03_0_0_RNI9I0C/F
7.694	0.527	tNET	FF	1	R47C38[0][A]	Mdu/u_mdu/m31_4_01_cZ/I1
8.211	0.517	tINS	FF	1	R47C38[0][A]	Mdu/u_mdu/m31_4_01_cZ/F
8.729	0.518	tNET	FF	1	R41C38[3][B]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[31]/I2
9.278	0.549	tINS	FR	1	R41C38[3][B]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[31]/F
9.280	0.001	tNET	RR	1	R41C38[2][A]	Mdu/u_mdu/reg0_exe_nx_cZ[31]/I3
9.797	0.517	tINS	RF	3	R41C38[2][A]	Mdu/u_mdu/reg0_exe_nx_cZ[31]/F
10.325	0.528	tNET	FF	1	R40C42[2][A]	Mdu/u_mdu/reg0_nx_rep1_cZ[31]/I0
10.895	0.570	tINS	FR	1	R40C42[2][A]	Mdu/u_mdu/reg0_nx_rep1_cZ[31]/F
10.895	0.000	tNET	RR	1	R40C42[2][A]	Mdu/u_mdu/reg0_31_rep1_Z/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	581	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R40C42[2][A]	Mdu/u_mdu/reg0_31_rep1_Z/CLK
11.683	-0.200	tUnc				Mdu/u_mdu/reg0_31_rep1_Z
11.648	-0.035	tSu		1	R40C42[2][A]	Mdu/u_mdu/reg0_31_rep1_Z

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	8
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 4.350, 48.272%; route: 4.429, 49.154%; tC2Q: 0.232, 2.574%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path16

Path Summary:

Slack	0.754
Data Arrival Time	10.895
Data Required Time	11.648
From	Mdu/u_mdu/reg0_Z[8]
To	Mdu/u_mdu/reg0_Z[31]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.683	0.683	tINS	RR	581	IOT48[A]	clk_ibuf/O
1.883	1.201	tNET	RR	1	R34C41[1][A]	Mdu/u_mdu/reg0_Z[8]/CLK
2.115	0.232	tC2Q	RF	18	R34C41[1][A]	Mdu/u_mdu/reg0_Z[8]/Q
3.344	1.229	tNET	FF	1	R52C42[3][B]	Mdu/u_mdu/m11_0_03_1_cZ/I2
3.914	0.570	tINS	FR	1	R52C42[3][B]	Mdu/u_mdu/m11_0_03_1_cZ/F
3.915	0.001	tNET	RR	1	R52C42[3][A]	Mdu/u_mdu/m11_0_03_cZ/I1
4.432	0.517	tINS	RF	4	R52C42[3][A]	Mdu/u_mdu/m11_0_03_cZ/F
5.126	0.694	tNET	FF	1	R52C36[0][B]	Mdu/u_mdu/m15_2_03_1_0_cZ/I2
5.681	0.555	tINS	FF	2	R52C36[0][B]	Mdu/u_mdu/m15_2_03_1_0_cZ/F
6.612	0.931	tNET	FF	1	R47C32[3][B]	Mdu/u_mdu/m15_2_03_0_0_RNI9I0C/I1
7.167	0.555	tINS	FF	3	R47C32[3][B]	Mdu/u_mdu/m15_2_03_0_0_RNI9I0C/F
7.694	0.527	tNET	FF	1	R47C38[0][A]	Mdu/u_mdu/m31_4_01_cZ/I1
8.211	0.517	tINS	FF	1	R47C38[0][A]	Mdu/u_mdu/m31_4_01_cZ/F
8.729	0.518	tNET	FF	1	R41C38[3][B]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[31]/I2
9.278	0.549	tINS	FR	1	R41C38[3][B]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[31]/F
9.280	0.001	tNET	RR	1	R41C38[2][A]	Mdu/u_mdu/reg0_exe_nx_cZ[31]/I3
9.797	0.517	tINS	RF	3	R41C38[2][A]	Mdu/u_mdu/reg0_exe_nx_cZ[31]/F
10.325	0.528	tNET	FF	1	R40C42[2][B]	Mdu/u_mdu/reg0_nx_cZ[31]/I0
10.895	0.570	tINS	FR	1	R40C42[2][B]	Mdu/u_mdu/reg0_nx_cZ[31]/F
10.895	0.000	tNET	RR	1	R40C42[2][B]	Mdu/u_mdu/reg0_Z[31]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	581	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R40C42[2][B]	Mdu/u_mdu/reg0_Z[31]/CLK
11.683	-0.200	tUnc				Mdu/u_mdu/reg0_Z[31]
11.648	-0.035	tSu		1	R40C42[2][B]	Mdu/u_mdu/reg0_Z[31]

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	8
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 4.350, 48.272%; route: 4.429, 49.154%; tC2Q: 0.232, 2.574%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path17

Path Summary:

Slack	0.801
Data Arrival Time	10.847
Data Required Time	11.648
From	Mdu/u_mdu/reg0_Z[7]
To	Mdu/u_mdu/reg0_26_rep1_Z
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.683	0.683	tINS	RR	581	IOT48[A]	clk_ibuf/O
1.883	1.201	tNET	RR	1	R34C38[1][B]	Mdu/u_mdu/reg0_Z[7]/CLK
2.115	0.232	tC2Q	RF	20	R34C38[1][B]	Mdu/u_mdu/reg0_Z[7]/Q
3.469	1.354	tNET	FF	1	R48C42[0][A]	Mdu/u_mdu/m10_0_03_1_cZ/I2
4.039	0.570	tINS	FR	1	R48C42[0][A]	Mdu/u_mdu/m10_0_03_1_cZ/F
4.212	0.172	tNET	RR	1	R48C41[3][A]	Mdu/u_mdu/m10_0_03_cZ/I1
4.767	0.555	tINS	RF	4	R48C41[3][A]	Mdu/u_mdu/m10_0_03_cZ/F
5.431	0.665	tNET	FF	1	R47C38[2][B]	Mdu/u_mdu/m10_2_03_m1_e_1_cZ/I3
5.980	0.549	tINS	FR	1	R47C38[2][B]	Mdu/u_mdu/m10_2_03_m1_e_1_cZ/F
6.125	0.144	tNET	RR	1	R47C38[1][A]	Mdu/u_mdu/m10_2_03_m1_e/I3
6.496	0.371	tINS	RF	4	R47C38[1][A]	Mdu/u_mdu/m10_2_03_m1_e/F
7.166	0.670	tNET	FF	1	R47C33[2][A]	Mdu/u_mdu/m26_4_01_cZ/I1
7.715	0.549	tINS	FR	1	R47C33[2][A]	Mdu/u_mdu/m26_4_01_cZ/F
7.888	0.172	tNET	RR	1	R47C32[0][A]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[26]/I2
8.405	0.517	tINS	RF	1	R47C32[0][A]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[26]/F
9.089	0.684	tNET	FF	1	R42C32[0][A]	Mdu/u_mdu/reg0_exe_nx_cZ[26]/I3
9.606	0.517	tINS	FF	3	R42C32[0][A]	Mdu/u_mdu/reg0_exe_nx_cZ[26]/F
10.298	0.693	tNET	FF	1	R42C39[0][A]	Mdu/u_mdu/reg0_nx_rep1_cZ[26]/I0
10.847	0.549	tINS	FR	1	R42C39[0][A]	Mdu/u_mdu/reg0_nx_rep1_cZ[26]/F
10.847	0.000	tNET	RR	1	R42C39[0][A]	Mdu/u_mdu/reg0_26_rep1_Z/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	581	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R42C39[0][A]	Mdu/u_mdu/reg0_26_rep1_Z/CLK
11.683	-0.200	tUnc				Mdu/u_mdu/reg0_26_rep1_Z
11.648	-0.035	tSu		1	R42C39[0][A]	Mdu/u_mdu/reg0_26_rep1_Z

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	8
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 4.177, 46.596%; route: 4.555, 50.816%; tC2Q: 0.232, 2.588%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path18

Path Summary:

Slack	0.801
Data Arrival Time	10.847
Data Required Time	11.648
From	Mdu/u_mdu/reg0_Z[7]
To	Mdu/u_mdu/reg0_fast_Z[26]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.683	0.683	tINS	RR	581	IOT48[A]	clk_ibuf/O
1.883	1.201	tNET	RR	1	R34C38[1][B]	Mdu/u_mdu/reg0_Z[7]/CLK
2.115	0.232	tC2Q	RF	20	R34C38[1][B]	Mdu/u_mdu/reg0_Z[7]/Q
3.469	1.354	tNET	FF	1	R48C42[0][A]	Mdu/u_mdu/m10_0_03_1_cZ/I2
4.039	0.570	tINS	FR	1	R48C42[0][A]	Mdu/u_mdu/m10_0_03_1_cZ/F
4.212	0.172	tNET	RR	1	R48C41[3][A]	Mdu/u_mdu/m10_0_03_cZ/I1
4.767	0.555	tINS	RF	4	R48C41[3][A]	Mdu/u_mdu/m10_0_03_cZ/F
5.431	0.665	tNET	FF	1	R47C38[2][B]	Mdu/u_mdu/m10_2_03_m1_e_1_cZ/I3
5.980	0.549	tINS	FR	1	R47C38[2][B]	Mdu/u_mdu/m10_2_03_m1_e_1_cZ/F
6.125	0.144	tNET	RR	1	R47C38[1][A]	Mdu/u_mdu/m10_2_03_m1_e/I3
6.496	0.371	tINS	RF	4	R47C38[1][A]	Mdu/u_mdu/m10_2_03_m1_e/F
7.166	0.670	tNET	FF	1	R47C33[2][A]	Mdu/u_mdu/m26_4_01_cZ/I1
7.715	0.549	tINS	FR	1	R47C33[2][A]	Mdu/u_mdu/m26_4_01_cZ/F
7.888	0.172	tNET	RR	1	R47C32[0][A]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[26]/I2
8.405	0.517	tINS	RF	1	R47C32[0][A]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[26]/F
9.089	0.684	tNET	FF	1	R42C32[0][A]	Mdu/u_mdu/reg0_exe_nx_cZ[26]/I3
9.606	0.517	tINS	FF	3	R42C32[0][A]	Mdu/u_mdu/reg0_exe_nx_cZ[26]/F
10.298	0.693	tNET	FF	1	R42C40[2][A]	Mdu/u_mdu/reg0_nx_fast_cZ[26]/I0
10.847	0.549	tINS	FR	1	R42C40[2][A]	Mdu/u_mdu/reg0_nx_fast_cZ[26]/F
10.847	0.000	tNET	RR	1	R42C40[2][A]	Mdu/u_mdu/reg0_fast_Z[26]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	581	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R42C40[2][A]	Mdu/u_mdu/reg0_fast_Z[26]/CLK
11.683	-0.200	tUnc				Mdu/u_mdu/reg0_fast_Z[26]
11.648	-0.035	tSu		1	R42C40[2][A]	Mdu/u_mdu/reg0_fast_Z[26]

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	8
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 4.177, 46.596%; route: 4.555, 50.816%; tC2Q: 0.232, 2.588%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path19

Path Summary:

Slack	0.808
Data Arrival Time	10.840
Data Required Time	11.648
From	Mdu/u_mdu/reg0_Z[8]
To	Mdu/u_mdu/reg0_fast_Z[31]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.683	0.683	tINS	RR	581	IOT48[A]	clk_ibuf/O
1.883	1.201	tNET	RR	1	R34C41[1][A]	Mdu/u_mdu/reg0_Z[8]/CLK
2.115	0.232	tC2Q	RF	18	R34C41[1][A]	Mdu/u_mdu/reg0_Z[8]/Q
3.344	1.229	tNET	FF	1	R52C42[3][B]	Mdu/u_mdu/m11_0_03_1_cZ/I2
3.914	0.570	tINS	FR	1	R52C42[3][B]	Mdu/u_mdu/m11_0_03_1_cZ/F
3.915	0.001	tNET	RR	1	R52C42[3][A]	Mdu/u_mdu/m11_0_03_cZ/I1
4.432	0.517	tINS	RF	4	R52C42[3][A]	Mdu/u_mdu/m11_0_03_cZ/F
5.126	0.694	tNET	FF	1	R52C36[0][B]	Mdu/u_mdu/m15_2_03_1_0_cZ/I2
5.681	0.555	tINS	FF	2	R52C36[0][B]	Mdu/u_mdu/m15_2_03_1_0_cZ/F
6.612	0.931	tNET	FF	1	R47C32[3][B]	Mdu/u_mdu/m15_2_03_0_0_RNI9I0C/I1
7.167	0.555	tINS	FF	3	R47C32[3][B]	Mdu/u_mdu/m15_2_03_0_0_RNI9I0C/F
7.694	0.527	tNET	FF	1	R47C38[0][A]	Mdu/u_mdu/m31_4_01_cZ/I1
8.211	0.517	tINS	FF	1	R47C38[0][A]	Mdu/u_mdu/m31_4_01_cZ/F
8.729	0.518	tNET	FF	1	R41C38[3][B]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[31]/I2
9.278	0.549	tINS	FR	1	R41C38[3][B]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[31]/F
9.280	0.001	tNET	RR	1	R41C38[2][A]	Mdu/u_mdu/reg0_exe_nx_cZ[31]/I3
9.797	0.517	tINS	RF	3	R41C38[2][A]	Mdu/u_mdu/reg0_exe_nx_cZ[31]/F
10.291	0.494	tNET	FF	1	R41C42[2][B]	Mdu/u_mdu/reg0_nx_fast_cZ[31]/I0
10.840	0.549	tINS	FR	1	R41C42[2][B]	Mdu/u_mdu/reg0_nx_fast_cZ[31]/F
10.840	0.000	tNET	RR	1	R41C42[2][B]	Mdu/u_mdu/reg0_fast_Z[31]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	581	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R41C42[2][B]	Mdu/u_mdu/reg0_fast_Z[31]/CLK
11.683	-0.200	tUnc				Mdu/u_mdu/reg0_fast_Z[31]
11.648	-0.035	tSu		1	R41C42[2][B]	Mdu/u_mdu/reg0_fast_Z[31]

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	8
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 4.329, 48.333%; route: 4.396, 49.077%; tC2Q: 0.232, 2.590%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path20

Path Summary:

Slack	0.820
Data Arrival Time	10.829
Data Required Time	11.648
From	Mdu/u_mdu/reg0_fast_Z[12]
To	memq_memq_0_4
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.683	0.683	tINS	RR	581	IOT48[A]	clk_ibuf/O
1.883	1.201	tNET	RR	1	R48C43[0][B]	Mdu/u_mdu/reg0_fast_Z[12]/CLK
2.115	0.232	tC2Q	RF	8	R48C43[0][B]	Mdu/u_mdu/reg0_fast_Z[12]/Q
3.056	0.941	tNET	FF	1	R39C40[3][A]	Mdu/u_mdu/reg0_neg_axb_12_par_0_cp_cZ/I0
3.573	0.517	tINS	FF	1	R39C40[3][A]	Mdu/u_mdu/reg0_neg_axb_12_par_0_cp_cZ/F
4.771	1.198	tNET	FF	2	R33C29[2][B]	Mdu/u_mdu/reg0_neg_axb_12_par_cp_1/I0
5.341	0.570	tINS	FR	1	R33C29[2][B]	Mdu/u_mdu/reg0_neg_axb_12_par_cp_1/COUT
5.341	0.000	tNET	RR	2	R33C30[0][A]	Mdu/u_mdu/reg0_neg_axb_16_par_cp_1/CIN
5.376	0.035	tINS	RF	1	R33C30[0][A]	Mdu/u_mdu/reg0_neg_axb_16_par_cp_1/COUT
5.376	0.000	tNET	FF	2	R33C30[0][B]	Mdu/u_mdu/reg0_neg_axb_19_par_1/CIN
5.411	0.035	tINS	FF	1	R33C30[0][B]	Mdu/u_mdu/reg0_neg_axb_19_par_1/COUT
5.411	0.000	tNET	FF	2	R33C30[1][A]	Mdu/u_mdu/reg0_neg_axb_23_par_1/CIN
5.447	0.035	tINS	FF	1	R33C30[1][A]	Mdu/u_mdu/reg0_neg_axb_23_par_1/COUT
5.447	0.000	tNET	FF	2	R33C30[1][B]	Mdu/u_mdu/reg0_neg_axb_27_par_1/CIN
5.482	0.035	tINS	FF	1	R33C30[1][B]	Mdu/u_mdu/reg0_neg_axb_27_par_1/COUT
5.482	0.000	tNET	FF	2	R33C30[2][A]	Mdu/u_mdu/reg0_neg_axb_31_par_1/CIN
5.517	0.035	tINS	FF	1	R33C30[2][A]	Mdu/u_mdu/reg0_neg_axb_31_par_1/COUT
5.517	0.000	tNET	FF	2	R33C30[2][B]	Mdu/u_mdu/reg0_neg_cry_34_0/CIN
5.552	0.035	tINS	FF	1	R33C30[2][B]	Mdu/u_mdu/reg0_neg_cry_34_0/COUT
5.552	0.000	tNET	FF	2	R33C31[0][A]	Mdu/u_mdu/reg0_neg_cry_35_0/CIN
5.587	0.035	tINS	FF	1	R33C31[0][A]	Mdu/u_mdu/reg0_neg_cry_35_0/COUT
5.587	0.000	tNET	FF	2	R33C31[0][B]	Mdu/u_mdu/reg0_neg_cry_36_0/CIN
5.623	0.035	tINS	FF	1	R33C31[0][B]	Mdu/u_mdu/reg0_neg_cry_36_0/COUT
5.623	0.000	tNET	FF	2	R33C31[1][A]	Mdu/u_mdu/reg0_neg_cry_37_0/CIN
5.658	0.035	tINS	FF	1	R33C31[1][A]	Mdu/u_mdu/reg0_neg_cry_37_0/COUT
5.658	0.000	tNET	FF	2	R33C31[1][B]	Mdu/u_mdu/reg0_neg_cry_38_0/CIN
5.693	0.035	tINS	FF	1	R33C31[1][B]	Mdu/u_mdu/reg0_neg_cry_38_0/COUT
5.693	0.000	tNET	FF	2	R33C31[2][A]	Mdu/u_mdu/reg0_neg_cry_39_0/CIN
5.728	0.035	tINS	FF	1	R33C31[2][A]	Mdu/u_mdu/reg0_neg_cry_39_0/COUT
5.728	0.000	tNET	FF	2	R33C31[2][B]	Mdu/u_mdu/reg0_neg_cry_40_0/CIN
5.763	0.035	tINS	FF	1	R33C31[2][B]	Mdu/u_mdu/reg0_neg_cry_40_0/COUT
5.763	0.000	tNET	FF	2	R33C32[0][A]	Mdu/u_mdu/reg0_neg_cry_41_0/CIN
6.233	0.470	tINS	FF	1	R33C32[0][A]	Mdu/u_mdu/reg0_neg_cry_41_0/SUM
6.751	0.518	tNET	FF	1	R33C38[2][A]	Mdu/u_mdu/reg0_post_swap_2[9]/I2
7.306	0.555	tINS	FF	1	R33C38[2][A]	Mdu/u_mdu/reg0_post_swap_2[9]/F
7.306	0.000	tNET	FF	1	R33C38[2][A]	Mdu/u_mdu/reg0_post_swap_4[9]/I0
7.409	0.103	tINS	FF	1	R33C38[2][A]	Mdu/u_mdu/reg0_post_swap_4[9]/O
8.023	0.613	tNET	FF	1	R33C45[3][B]	Mdu/u_mdu/reg0_post_swap_5[9]/I1
8.540	0.517	tINS	FF	3	R33C45[3][B]	Mdu/u_mdu/reg0_post_swap_5[9]/F
8.791	0.252	tNET	FF	1	R35C45[3][B]	Mdu/u_mdu/res0_cZ[9]/I1
9.346	0.555	tINS	FF	3	R35C45[3][B]	Mdu/u_mdu/res0_cZ[9]/F
10.829	1.482	tNET	FF	1	BSRAM_R54[16]	memq_memq_0_4/DI1

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	581	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	BSRAM_R54[16]	memq_memq_0_4/CLKA
11.683	-0.200	tUnc				memq_memq_0_4
11.648	-0.035	tSu		1	BSRAM_R54[16]	memq_memq_0_4

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 3.709, 41.467%; route: 5.004, 55.940%; tC2Q: 0.232, 2.593%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path21

Path Summary:

Slack	0.880
Data Arrival Time	10.769
Data Required Time	11.648
From	Mdu/u_mdu/reg0_fast_Z[12]
To	memq_memq_0_4
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.683	0.683	tINS	RR	581	IOT48[A]	clk_ibuf/O
1.883	1.201	tNET	RR	1	R48C43[0][B]	Mdu/u_mdu/reg0_fast_Z[12]/CLK
2.115	0.232	tC2Q	RF	8	R48C43[0][B]	Mdu/u_mdu/reg0_fast_Z[12]/Q
3.056	0.941	tNET	FF	1	R39C40[3][A]	Mdu/u_mdu/reg0_neg_axb_12_par_0_cp_cZ/I0
3.573	0.517	tINS	FF	1	R39C40[3][A]	Mdu/u_mdu/reg0_neg_axb_12_par_0_cp_cZ/F
4.771	1.198	tNET	FF	2	R33C29[2][B]	Mdu/u_mdu/reg0_neg_axb_12_par_cp_1/I0
5.341	0.570	tINS	FR	1	R33C29[2][B]	Mdu/u_mdu/reg0_neg_axb_12_par_cp_1/COUT
5.341	0.000	tNET	RR	2	R33C30[0][A]	Mdu/u_mdu/reg0_neg_axb_16_par_cp_1/CIN
5.376	0.035	tINS	RF	1	R33C30[0][A]	Mdu/u_mdu/reg0_neg_axb_16_par_cp_1/COUT
5.376	0.000	tNET	FF	2	R33C30[0][B]	Mdu/u_mdu/reg0_neg_axb_19_par_1/CIN
5.411	0.035	tINS	FF	1	R33C30[0][B]	Mdu/u_mdu/reg0_neg_axb_19_par_1/COUT
5.411	0.000	tNET	FF	2	R33C30[1][A]	Mdu/u_mdu/reg0_neg_axb_23_par_1/CIN
5.447	0.035	tINS	FF	1	R33C30[1][A]	Mdu/u_mdu/reg0_neg_axb_23_par_1/COUT
5.447	0.000	tNET	FF	2	R33C30[1][B]	Mdu/u_mdu/reg0_neg_axb_27_par_1/CIN
5.482	0.035	tINS	FF	1	R33C30[1][B]	Mdu/u_mdu/reg0_neg_axb_27_par_1/COUT
5.482	0.000	tNET	FF	2	R33C30[2][A]	Mdu/u_mdu/reg0_neg_axb_31_par_1/CIN
5.517	0.035	tINS	FF	1	R33C30[2][A]	Mdu/u_mdu/reg0_neg_axb_31_par_1/COUT
5.517	0.000	tNET	FF	2	R33C30[2][B]	Mdu/u_mdu/reg0_neg_cry_34_0/CIN
5.552	0.035	tINS	FF	1	R33C30[2][B]	Mdu/u_mdu/reg0_neg_cry_34_0/COUT
5.552	0.000	tNET	FF	2	R33C31[0][A]	Mdu/u_mdu/reg0_neg_cry_35_0/CIN
5.587	0.035	tINS	FF	1	R33C31[0][A]	Mdu/u_mdu/reg0_neg_cry_35_0/COUT
5.587	0.000	tNET	FF	2	R33C31[0][B]	Mdu/u_mdu/reg0_neg_cry_36_0/CIN
5.623	0.035	tINS	FF	1	R33C31[0][B]	Mdu/u_mdu/reg0_neg_cry_36_0/COUT
5.623	0.000	tNET	FF	2	R33C31[1][A]	Mdu/u_mdu/reg0_neg_cry_37_0/CIN
5.658	0.035	tINS	FF	1	R33C31[1][A]	Mdu/u_mdu/reg0_neg_cry_37_0/COUT
5.658	0.000	tNET	FF	2	R33C31[1][B]	Mdu/u_mdu/reg0_neg_cry_38_0/CIN
5.693	0.035	tINS	FF	1	R33C31[1][B]	Mdu/u_mdu/reg0_neg_cry_38_0/COUT
5.693	0.000	tNET	FF	2	R33C31[2][A]	Mdu/u_mdu/reg0_neg_cry_39_0/CIN
5.728	0.035	tINS	FF	1	R33C31[2][A]	Mdu/u_mdu/reg0_neg_cry_39_0/COUT
5.728	0.000	tNET	FF	2	R33C31[2][B]	Mdu/u_mdu/reg0_neg_cry_40_0/CIN
6.198	0.470	tINS	FF	1	R33C31[2][B]	Mdu/u_mdu/reg0_neg_cry_40_0/SUM
6.640	0.441	tNET	FF	1	R33C38[3][A]	Mdu/u_mdu/reg0_post_swap_2[8]/I2
7.093	0.453	tINS	FF	1	R33C38[3][A]	Mdu/u_mdu/reg0_post_swap_2[8]/F
7.093	0.000	tNET	FF	1	R33C38[3][A]	Mdu/u_mdu/reg0_post_swap_4[8]/I0
7.196	0.103	tINS	FF	1	R33C38[3][A]	Mdu/u_mdu/reg0_post_swap_4[8]/O
7.764	0.569	tNET	FF	1	R33C41[0][A]	Mdu/u_mdu/reg0_post_swap_5[8]/I1
8.281	0.517	tINS	FF	2	R33C41[0][A]	Mdu/u_mdu/reg0_post_swap_5[8]/F
8.704	0.422	tNET	FF	1	R34C42[2][A]	Mdu/u_mdu/res0_cZ[8]/I1
9.259	0.555	tINS	FF	3	R34C42[2][A]	Mdu/u_mdu/res0_cZ[8]/F
10.769	1.510	tNET	FF	1	BSRAM_R54[16]	memq_memq_0_4/DI0

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	581	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	BSRAM_R54[16]	memq_memq_0_4/CLKA
11.683	-0.200	tUnc				memq_memq_0_4
11.648	-0.035	tSu		1	BSRAM_R54[16]	memq_memq_0_4

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 3.572, 40.202%; route: 5.081, 57.187%; tC2Q: 0.232, 2.611%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path22

Path Summary:

Slack	0.888
Data Arrival Time	10.760
Data Required Time	11.648
From	Mdu/u_mdu/reg0_Z[7]
To	Mdu/u_mdu/reg0_Z[26]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.683	0.683	tINS	RR	581	IOT48[A]	clk_ibuf/O
1.883	1.201	tNET	RR	1	R34C38[1][B]	Mdu/u_mdu/reg0_Z[7]/CLK
2.115	0.232	tC2Q	RF	20	R34C38[1][B]	Mdu/u_mdu/reg0_Z[7]/Q
3.469	1.354	tNET	FF	1	R48C42[0][A]	Mdu/u_mdu/m10_0_03_1_cZ/I2
4.039	0.570	tINS	FR	1	R48C42[0][A]	Mdu/u_mdu/m10_0_03_1_cZ/F
4.212	0.172	tNET	RR	1	R48C41[3][A]	Mdu/u_mdu/m10_0_03_cZ/I1
4.767	0.555	tINS	RF	4	R48C41[3][A]	Mdu/u_mdu/m10_0_03_cZ/F
5.431	0.665	tNET	FF	1	R47C38[2][B]	Mdu/u_mdu/m10_2_03_m1_e_1_cZ/I3
5.980	0.549	tINS	FR	1	R47C38[2][B]	Mdu/u_mdu/m10_2_03_m1_e_1_cZ/F
6.125	0.144	tNET	RR	1	R47C38[1][A]	Mdu/u_mdu/m10_2_03_m1_e/I3
6.496	0.371	tINS	RF	4	R47C38[1][A]	Mdu/u_mdu/m10_2_03_m1_e/F
7.166	0.670	tNET	FF	1	R47C33[2][A]	Mdu/u_mdu/m26_4_01_cZ/I1
7.715	0.549	tINS	FR	1	R47C33[2][A]	Mdu/u_mdu/m26_4_01_cZ/F
7.888	0.172	tNET	RR	1	R47C32[0][A]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[26]/I2
8.405	0.517	tINS	RF	1	R47C32[0][A]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[26]/F
9.089	0.684	tNET	FF	1	R42C32[0][A]	Mdu/u_mdu/reg0_exe_nx_cZ[26]/I3
9.606	0.517	tINS	FF	3	R42C32[0][A]	Mdu/u_mdu/reg0_exe_nx_cZ[26]/F
10.298	0.693	tNET	FF	1	R42C40[1][B]	Mdu/u_mdu/reg0_nx_cZ[26]/I0
10.760	0.462	tINS	FR	1	R42C40[1][B]	Mdu/u_mdu/reg0_nx_cZ[26]/F
10.760	0.000	tNET	RR	1	R42C40[1][B]	Mdu/u_mdu/reg0_Z[26]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	581	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R42C40[1][B]	Mdu/u_mdu/reg0_Z[26]/CLK
11.683	-0.200	tUnc				Mdu/u_mdu/reg0_Z[26]
11.648	-0.035	tSu		1	R42C40[1][B]	Mdu/u_mdu/reg0_Z[26]

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	8
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 4.090, 46.073%; route: 4.555, 51.314%; tC2Q: 0.232, 2.613%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path23

Path Summary:

Slack	0.949
Data Arrival Time	10.699
Data Required Time	11.648
From	Mdu/u_mdu/reg1_Z[26]
To	Mdu/u_mdu/div_shift_number_Z[0]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.683	0.683	tINS	RR	581	IOT48[A]	clk_ibuf/O
1.883	1.201	tNET	RR	1	R37C40[0][A]	Mdu/u_mdu/reg1_Z[26]/CLK
2.115	0.232	tC2Q	RF	9	R37C40[0][A]	Mdu/u_mdu/reg1_Z[26]/Q
2.540	0.425	tNET	FF	1	R37C40[3][B]	Mdu/u_mdu/un5_op1_eq_zero_nx_23_N_2L1_cZ_cZ/I0
3.095	0.555	tINS	FF	1	R37C40[3][B]	Mdu/u_mdu/un5_op1_eq_zero_nx_23_N_2L1_cZ_cZ/F
4.491	1.396	tNET	FF	1	R37C39[2][A]	Mdu/u_mdu/un5_op1_eq_zero_nx_23_cZ_cZ/S0
4.742	0.251	tINS	FF	2	R37C39[2][A]	Mdu/u_mdu/un5_op1_eq_zero_nx_23_cZ_cZ/O
5.151	0.408	tNET	FF	1	R37C38[0][A]	Mdu/u_mdu/un5_op1_eq_zero_nx_cZ_cZ/I2
5.706	0.555	tINS	FF	9	R37C38[0][A]	Mdu/u_mdu/un5_op1_eq_zero_nx_cZ_cZ/F
6.405	0.699	tNET	FF	1	R38C31[3][B]	Mdu/u_mdu/op1_lead_zero_detect_8_v[1]_i_m_cZ/I3
6.960	0.555	tINS	FF	3	R38C31[3][B]	Mdu/u_mdu/op1_lead_zero_detect_8_v[1]_i_m_cZ/F
7.370	0.411	tNET	FF	1	R40C31[3][A]	Mdu/u_mdu/div_shift_number_nx_axb_3_i_lfx_0_cZ/I1
7.887	0.517	tINS	FF	1	R40C31[3][A]	Mdu/u_mdu/div_shift_number_nx_axb_3_i_lfx_0_cZ/F
7.887	0.000	tNET	FF	1	R40C31[3][A]	Mdu/u_mdu/div_shift_number_nx_axb_3_i_lfx_cZ/I0
7.990	0.103	tINS	FF	1	R40C31[3][A]	Mdu/u_mdu/div_shift_number_nx_axb_3_i_lfx_cZ/O
8.409	0.419	tNET	FF	2	R39C32[2][B]	Mdu/u_mdu/div_shift_number_nx_cry_3_0/I0
8.979	0.570	tINS	FR	1	R39C32[2][B]	Mdu/u_mdu/div_shift_number_nx_cry_3_0/COUT
8.979	0.000	tNET	RR	2	R39C33[0][A]	Mdu/u_mdu/div_shift_number_nx_cry_4_0/CIN
9.015	0.035	tINS	RF	1	R39C33[0][A]	Mdu/u_mdu/div_shift_number_nx_cry_4_0/COUT
9.015	0.000	tNET	FF	1	R39C33[1][B]	Mdu/u_mdu/g0_0_cZ/I0
9.585	0.570	tINS	FR	6	R39C33[1][B]	Mdu/u_mdu/g0_0_cZ/F
10.699	1.114	tNET	RR	1	R48C37[1][A]	Mdu/u_mdu/div_shift_number_Z[0]/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	581	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R48C37[1][A]	Mdu/u_mdu/div_shift_number_Z[0]/CLK
11.683	-0.200	tUnc				Mdu/u_mdu/div_shift_number_Z[0]
11.648	-0.035	tSu		1	R48C37[1][A]	Mdu/u_mdu/div_shift_number_Z[0]

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	9
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 3.711, 42.097%; route: 4.873, 55.271%; tC2Q: 0.232, 2.632%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path24

Path Summary:

Slack	0.949
Data Arrival Time	10.699
Data Required Time	11.648
From	Mdu/u_mdu/reg1_Z[26]
To	Mdu/u_mdu/div_shift_number_Z[1]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.683	0.683	tINS	RR	581	IOT48[A]	clk_ibuf/O
1.883	1.201	tNET	RR	1	R37C40[0][A]	Mdu/u_mdu/reg1_Z[26]/CLK
2.115	0.232	tC2Q	RF	9	R37C40[0][A]	Mdu/u_mdu/reg1_Z[26]/Q
2.540	0.425	tNET	FF	1	R37C40[3][B]	Mdu/u_mdu/un5_op1_eq_zero_nx_23_N_2L1_cZ_cZ/I0
3.095	0.555	tINS	FF	1	R37C40[3][B]	Mdu/u_mdu/un5_op1_eq_zero_nx_23_N_2L1_cZ_cZ/F
4.491	1.396	tNET	FF	1	R37C39[2][A]	Mdu/u_mdu/un5_op1_eq_zero_nx_23_cZ_cZ/S0
4.742	0.251	tINS	FF	2	R37C39[2][A]	Mdu/u_mdu/un5_op1_eq_zero_nx_23_cZ_cZ/O
5.151	0.408	tNET	FF	1	R37C38[0][A]	Mdu/u_mdu/un5_op1_eq_zero_nx_cZ_cZ/I2
5.706	0.555	tINS	FF	9	R37C38[0][A]	Mdu/u_mdu/un5_op1_eq_zero_nx_cZ_cZ/F
6.405	0.699	tNET	FF	1	R38C31[3][B]	Mdu/u_mdu/op1_lead_zero_detect_8_v[1]_i_m_cZ/I3
6.960	0.555	tINS	FF	3	R38C31[3][B]	Mdu/u_mdu/op1_lead_zero_detect_8_v[1]_i_m_cZ/F
7.370	0.411	tNET	FF	1	R40C31[3][A]	Mdu/u_mdu/div_shift_number_nx_axb_3_i_lfx_0_cZ/I1
7.887	0.517	tINS	FF	1	R40C31[3][A]	Mdu/u_mdu/div_shift_number_nx_axb_3_i_lfx_0_cZ/F
7.887	0.000	tNET	FF	1	R40C31[3][A]	Mdu/u_mdu/div_shift_number_nx_axb_3_i_lfx_cZ/I0
7.990	0.103	tINS	FF	1	R40C31[3][A]	Mdu/u_mdu/div_shift_number_nx_axb_3_i_lfx_cZ/O
8.409	0.419	tNET	FF	2	R39C32[2][B]	Mdu/u_mdu/div_shift_number_nx_cry_3_0/I0
8.979	0.570	tINS	FR	1	R39C32[2][B]	Mdu/u_mdu/div_shift_number_nx_cry_3_0/COUT
8.979	0.000	tNET	RR	2	R39C33[0][A]	Mdu/u_mdu/div_shift_number_nx_cry_4_0/CIN
9.015	0.035	tINS	RF	1	R39C33[0][A]	Mdu/u_mdu/div_shift_number_nx_cry_4_0/COUT
9.015	0.000	tNET	FF	1	R39C33[1][B]	Mdu/u_mdu/g0_0_cZ/I0
9.585	0.570	tINS	FR	6	R39C33[1][B]	Mdu/u_mdu/g0_0_cZ/F
10.699	1.114	tNET	RR	1	R48C37[1][B]	Mdu/u_mdu/div_shift_number_Z[1]/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	581	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R48C37[1][B]	Mdu/u_mdu/div_shift_number_Z[1]/CLK
11.683	-0.200	tUnc				Mdu/u_mdu/div_shift_number_Z[1]
11.648	-0.035	tSu		1	R48C37[1][B]	Mdu/u_mdu/div_shift_number_Z[1]

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	9
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 3.711, 42.097%; route: 4.873, 55.271%; tC2Q: 0.232, 2.632%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path25

Path Summary:

Slack	0.949
Data Arrival Time	10.699
Data Required Time	11.648
From	Mdu/u_mdu/reg1_Z[26]
To	Mdu/u_mdu/div_shift_number_Z[3]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.683	0.683	tINS	RR	581	IOT48[A]	clk_ibuf/O
1.883	1.201	tNET	RR	1	R37C40[0][A]	Mdu/u_mdu/reg1_Z[26]/CLK
2.115	0.232	tC2Q	RF	9	R37C40[0][A]	Mdu/u_mdu/reg1_Z[26]/Q
2.540	0.425	tNET	FF	1	R37C40[3][B]	Mdu/u_mdu/un5_op1_eq_zero_nx_23_N_2L1_cZ_cZ/I0
3.095	0.555	tINS	FF	1	R37C40[3][B]	Mdu/u_mdu/un5_op1_eq_zero_nx_23_N_2L1_cZ_cZ/F
4.491	1.396	tNET	FF	1	R37C39[2][A]	Mdu/u_mdu/un5_op1_eq_zero_nx_23_cZ_cZ/S0
4.742	0.251	tINS	FF	2	R37C39[2][A]	Mdu/u_mdu/un5_op1_eq_zero_nx_23_cZ_cZ/O
5.151	0.408	tNET	FF	1	R37C38[0][A]	Mdu/u_mdu/un5_op1_eq_zero_nx_cZ_cZ/I2
5.706	0.555	tINS	FF	9	R37C38[0][A]	Mdu/u_mdu/un5_op1_eq_zero_nx_cZ_cZ/F
6.405	0.699	tNET	FF	1	R38C31[3][B]	Mdu/u_mdu/op1_lead_zero_detect_8_v[1]_i_m_cZ/I3
6.960	0.555	tINS	FF	3	R38C31[3][B]	Mdu/u_mdu/op1_lead_zero_detect_8_v[1]_i_m_cZ/F
7.370	0.411	tNET	FF	1	R40C31[3][A]	Mdu/u_mdu/div_shift_number_nx_axb_3_i_lfx_0_cZ/I1
7.887	0.517	tINS	FF	1	R40C31[3][A]	Mdu/u_mdu/div_shift_number_nx_axb_3_i_lfx_0_cZ/F
7.887	0.000	tNET	FF	1	R40C31[3][A]	Mdu/u_mdu/div_shift_number_nx_axb_3_i_lfx_cZ/I0
7.990	0.103	tINS	FF	1	R40C31[3][A]	Mdu/u_mdu/div_shift_number_nx_axb_3_i_lfx_cZ/O
8.409	0.419	tNET	FF	2	R39C32[2][B]	Mdu/u_mdu/div_shift_number_nx_cry_3_0/I0
8.979	0.570	tINS	FR	1	R39C32[2][B]	Mdu/u_mdu/div_shift_number_nx_cry_3_0/COUT
8.979	0.000	tNET	RR	2	R39C33[0][A]	Mdu/u_mdu/div_shift_number_nx_cry_4_0/CIN
9.015	0.035	tINS	RF	1	R39C33[0][A]	Mdu/u_mdu/div_shift_number_nx_cry_4_0/COUT
9.015	0.000	tNET	FF	1	R39C33[1][B]	Mdu/u_mdu/g0_0_cZ/I0
9.585	0.570	tINS	FR	6	R39C33[1][B]	Mdu/u_mdu/g0_0_cZ/F
10.699	1.114	tNET	RR	1	R48C37[2][B]	Mdu/u_mdu/div_shift_number_Z[3]/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	581	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R48C37[2][B]	Mdu/u_mdu/div_shift_number_Z[3]/CLK
11.683	-0.200	tUnc				Mdu/u_mdu/div_shift_number_Z[3]
11.648	-0.035	tSu		1	R48C37[2][B]	Mdu/u_mdu/div_shift_number_Z[3]

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	9
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 3.711, 42.097%; route: 4.873, 55.271%; tC2Q: 0.232, 2.632%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Hold Analysis Report

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	0.213
Data Arrival Time	2.040
Data Required Time	1.826
From	u_la0_top/u_ao_mem_ctrl/data_reg_Z[97]
To	u_la0_top/u_ao_mem_ctrl/mem_mem_0_48
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	581	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R12C13[0][A]	u_la0_top/u_ao_mem_ctrl/data_reg_Z[97]/CLK
1.779	0.202	tC2Q	RR	1	R12C13[0][A]	u_la0_top/u_ao_mem_ctrl/data_reg_Z[97]/Q
2.040	0.260	tNET	RR	1	BSRAM_R10[3]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_48/DI1

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	581	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	BSRAM_R10[3]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_48/CLKA
1.577	0.000	tUnc				u_la0_top/u_ao_mem_ctrl/mem_mem_0_48
1.826	0.249	tHld		1	BSRAM_R10[3]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_48

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.260, 56.314%; tC2Q: 0.202, 43.686%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path2

Path Summary:

Slack	0.335
Data Arrival Time	2.162
Data Required Time	1.826
From	u_la0_top/u_ao_mem_ctrl/data_reg_Z[87]
To	u_la0_top/u_ao_mem_ctrl/mem_mem_0_43
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	581	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R12C14[2][B]	u_la0_top/u_ao_mem_ctrl/data_reg_Z[87]/CLK
1.779	0.202	tC2Q	RR	1	R12C14[2][B]	u_la0_top/u_ao_mem_ctrl/data_reg_Z[87]/Q
2.162	0.382	tNET	RR	1	BSRAM_R10[2]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_43/DI1

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	581	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	BSRAM_R10[2]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_43/CLKA
1.577	0.000	tUnc				u_la0_top/u_ao_mem_ctrl/mem_mem_0_43
1.826	0.249	tHld		1	BSRAM_R10[2]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_43

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.382, 65.434%; tC2Q: 0.202, 34.566%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path3

Path Summary:

Slack	0.335
Data Arrival Time	2.162
Data Required Time	1.826
From	u_la0_top/u_ao_mem_ctrl/data_reg_Z[86]
To	u_la0_top/u_ao_mem_ctrl/mem_mem_0_43
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	581	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R12C14[2][A]	u_la0_top/u_ao_mem_ctrl/data_reg_Z[86]/CLK
1.779	0.202	tC2Q	RR	1	R12C14[2][A]	u_la0_top/u_ao_mem_ctrl/data_reg_Z[86]/Q
2.162	0.382	tNET	RR	1	BSRAM_R10[2]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_43/DI0

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	581	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	BSRAM_R10[2]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_43/CLKA
1.577	0.000	tUnc				u_la0_top/u_ao_mem_ctrl/mem_mem_0_43
1.826	0.249	tHld		1	BSRAM_R10[2]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_43

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.382, 65.434%; tC2Q: 0.202, 34.566%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path4

Path Summary:

Slack	0.342
Data Arrival Time	2.037
Data Required Time	1.695
From	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[6]
To	u_la0_top/u_ao_mem_ctrl/mem_mem_0_20
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	581	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R12C8[0][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[6]/CLK
1.779	0.202	tC2Q	RR	67	R12C8[0][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[6]/Q
2.037	0.258	tNET	RR	1	BSRAM_R10[1]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_20/ADA7

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	581	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	BSRAM_R10[1]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_20/CLKA
1.577	0.000	tUnc				u_la0_top/u_ao_mem_ctrl/mem_mem_0_20
1.695	0.118	tHld		1	BSRAM_R10[1]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_20

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.258, 56.063%; tC2Q: 0.202, 43.937%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path5

Path Summary:

Slack	0.342
Data Arrival Time	2.038
Data Required Time	1.695
From	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[3]
To	u_la0_top/u_ao_mem_ctrl/mem_mem_0_20
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	581	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R9C9[0][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[3]/CLK
1.779	0.202	tC2Q	RR	67	R9C9[0][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[3]/Q
2.038	0.258	tNET	RR	1	BSRAM_R10[1]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_20/ADA4

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	581	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	BSRAM_R10[1]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_20/CLKA
1.577	0.000	tUnc				u_la0_top/u_ao_mem_ctrl/mem_mem_0_20
1.695	0.118	tHld		1	BSRAM_R10[1]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_20

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.258, 56.116%; tC2Q: 0.202, 43.884%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path6

Path Summary:

Slack	0.350
Data Arrival Time	2.046
Data Required Time	1.695
From	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0]
To	u_la0_top/u_ao_mem_ctrl/mem_mem_0_20
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	581	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R9C8[2][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0]/CLK
1.779	0.202	tC2Q	RR	67	R9C8[2][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0]/Q
2.046	0.266	tNET	RR	1	BSRAM_R10[1]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_20/ADA1

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	581	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	BSRAM_R10[1]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_20/CLKA
1.577	0.000	tUnc				u_la0_top/u_ao_mem_ctrl/mem_mem_0_20
1.695	0.118	tHld		1	BSRAM_R10[1]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_20

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.266, 56.879%; tC2Q: 0.202, 43.121%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path7

Path Summary:

Slack	0.351
Data Arrival Time	2.046
Data Required Time	1.695
From	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8]
To	u_la0_top/u_ao_mem_ctrl/mem_mem_0_20
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	581	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R9C10[1][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8]/CLK
1.779	0.202	tC2Q	RR	67	R9C10[1][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8]/Q
2.046	0.266	tNET	RR	1	BSRAM_R10[1]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_20/ADA9

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	581	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	BSRAM_R10[1]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_20/CLKA
1.577	0.000	tUnc				u_la0_top/u_ao_mem_ctrl/mem_mem_0_20
1.695	0.118	tHld		1	BSRAM_R10[1]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_20

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.266, 56.884%; tC2Q: 0.202, 43.116%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path8

Path Summary:

Slack	0.352
Data Arrival Time	2.047
Data Required Time	1.695
From	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[9]
To	u_la0_top/u_ao_mem_ctrl/mem_mem_0_20
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	581	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R11C7[1][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[9]/CLK
1.779	0.202	tC2Q	RR	67	R11C7[1][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[9]/Q
2.047	0.268	tNET	RR	1	BSRAM_R10[1]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_20/ADA10

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	581	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	BSRAM_R10[1]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_20/CLKA
1.577	0.000	tUnc				u_la0_top/u_ao_mem_ctrl/mem_mem_0_20
1.695	0.118	tHld		1	BSRAM_R10[1]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_20

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.268, 56.986%; tC2Q: 0.202, 43.014%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path9

Path Summary:

Slack	0.352
Data Arrival Time	2.047
Data Required Time	1.695
From	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[9]
To	u_la0_top/u_ao_mem_ctrl/mem_mem_0_15
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	581	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R11C7[1][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[9]/CLK
1.779	0.202	tC2Q	RR	67	R11C7[1][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[9]/Q
2.047	0.268	tNET	RR	1	BSRAM_R10[0]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_15/ADA10

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	581	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	BSRAM_R10[0]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_15/CLKA
1.577	0.000	tUnc				u_la0_top/u_ao_mem_ctrl/mem_mem_0_15
1.695	0.118	tHld		1	BSRAM_R10[0]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_15

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.268, 56.986%; tC2Q: 0.202, 43.014%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path10

Path Summary:

Slack	0.352
Data Arrival Time	2.047
Data Required Time	1.695
From	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[5]
To	u_la0_top/u_ao_mem_ctrl/mem_mem_0_43
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	581	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R9C10[1][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[5]/CLK
1.779	0.202	tC2Q	RR	67	R9C10[1][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[5]/Q
2.047	0.268	tNET	RR	1	BSRAM_R10[2]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_43/ADA6

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	581	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	BSRAM_R10[2]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_43/CLKA
1.577	0.000	tUnc				u_la0_top/u_ao_mem_ctrl/mem_mem_0_43
1.695	0.118	tHld		1	BSRAM_R10[2]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_43

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.268, 56.996%; tC2Q: 0.202, 43.004%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path11

Path Summary:

Slack	0.354
Data Arrival Time	2.049
Data Required Time	1.695
From	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[12]
To	u_la0_top/u_ao_mem_ctrl/mem_mem_0_20
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	581	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R11C8[1][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[12]/CLK
1.779	0.202	tC2Q	RR	67	R11C8[1][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[12]/Q
2.049	0.270	tNET	RR	1	BSRAM_R10[1]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_20/ADA13

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	581	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	BSRAM_R10[1]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_20/CLKA
1.577	0.000	tUnc				u_la0_top/u_ao_mem_ctrl/mem_mem_0_20
1.695	0.118	tHld		1	BSRAM_R10[1]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_20

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.270, 57.208%; tC2Q: 0.202, 42.792%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path12

Path Summary:

Slack	0.354
Data Arrival Time	2.049
Data Required Time	1.695
From	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[1]
To	u_la0_top/u_ao_mem_ctrl/mem_mem_0_20
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	581	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R9C8[2][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[1]/CLK
1.779	0.202	tC2Q	RR	67	R9C8[2][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[1]/Q
2.049	0.270	tNET	RR	1	BSRAM_R10[1]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_20/ADA2

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	581	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	BSRAM_R10[1]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_20/CLKA
1.577	0.000	tUnc				u_la0_top/u_ao_mem_ctrl/mem_mem_0_20
1.695	0.118	tHld		1	BSRAM_R10[1]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_20

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.270, 57.208%; tC2Q: 0.202, 42.792%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path13

Path Summary:

Slack	0.354
Data Arrival Time	2.049
Data Required Time	1.695
From	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[12]
To	u_la0_top/u_ao_mem_ctrl/mem_mem_0_15
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	581	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R11C8[1][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[12]/CLK
1.779	0.202	tC2Q	RR	67	R11C8[1][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[12]/Q
2.049	0.270	tNET	RR	1	BSRAM_R10[0]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_15/ADA13

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	581	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	BSRAM_R10[0]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_15/CLKA
1.577	0.000	tUnc				u_la0_top/u_ao_mem_ctrl/mem_mem_0_15
1.695	0.118	tHld		1	BSRAM_R10[0]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_15

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.270, 57.208%; tC2Q: 0.202, 42.792%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path14

Path Summary:

Slack	0.354
Data Arrival Time	2.049
Data Required Time	1.695
From	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[1]
To	u_la0_top/u_ao_mem_ctrl/mem_mem_0_15
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	581	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R9C8[2][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[1]/CLK
1.779	0.202	tC2Q	RR	67	R9C8[2][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[1]/Q
2.049	0.270	tNET	RR	1	BSRAM_R10[0]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_15/ADA2

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	581	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	BSRAM_R10[0]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_15/CLKA
1.577	0.000	tUnc				u_la0_top/u_ao_mem_ctrl/mem_mem_0_15
1.695	0.118	tHld		1	BSRAM_R10[0]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_15

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.270, 57.208%; tC2Q: 0.202, 42.792%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path15

Path Summary:

Slack	0.354
Data Arrival Time	2.050
Data Required Time	1.695
From	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[7]
To	u_la0_top/u_ao_mem_ctrl/mem_mem_0_20
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	581	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R9C9[1][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[7]/CLK
1.779	0.202	tC2Q	RR	67	R9C9[1][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[7]/Q
2.050	0.270	tNET	RR	1	BSRAM_R10[1]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_20/ADA8

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	581	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	BSRAM_R10[1]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_20/CLKA
1.577	0.000	tUnc				u_la0_top/u_ao_mem_ctrl/mem_mem_0_20
1.695	0.118	tHld		1	BSRAM_R10[1]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_20

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.270, 57.213%; tC2Q: 0.202, 42.787%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path16

Path Summary:

Slack	0.354
Data Arrival Time	2.050
Data Required Time	1.695
From	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[10]
To	u_la0_top/u_ao_mem_ctrl/mem_mem_0_15
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	581	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R11C7[1][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[10]/CLK
1.779	0.202	tC2Q	RR	67	R11C7[1][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[10]/Q
2.050	0.270	tNET	RR	1	BSRAM_R10[0]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_15/ADA11

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	581	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	BSRAM_R10[0]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_15/CLKA
1.577	0.000	tUnc				u_la0_top/u_ao_mem_ctrl/mem_mem_0_15
1.695	0.118	tHld		1	BSRAM_R10[0]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_15

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.270, 57.213%; tC2Q: 0.202, 42.787%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path17

Path Summary:

Slack	0.354
Data Arrival Time	2.050
Data Required Time	1.695
From	cnt_Z[12]
To	memq_memq_0_1
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	581	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R33C51[2][B]	cnt_Z[12]/CLK
1.779	0.202	tC2Q	RR	34	R33C51[2][B]	cnt_Z[12]/Q
2.050	0.270	tNET	RR	1	BSRAM_R36[15]	memq_memq_0_1/ADA13

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	581	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	BSRAM_R36[15]	memq_memq_0_1/CLKA
1.577	0.000	tUnc				memq_memq_0_1
1.695	0.118	tHld		1	BSRAM_R36[15]	memq_memq_0_1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.270, 57.213%; tC2Q: 0.202, 42.787%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path18

Path Summary:

Slack	0.355
Data Arrival Time	2.051
Data Required Time	1.695
From	cnt_Z[6]
To	memq_memq_0_1
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	581	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R33C50[2][B]	cnt_Z[6]/CLK
1.779	0.202	tC2Q	RR	34	R33C50[2][B]	cnt_Z[6]/Q
2.051	0.271	tNET	RR	1	BSRAM_R36[15]	memq_memq_0_1/ADA7

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	581	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	BSRAM_R36[15]	memq_memq_0_1/CLKA
1.577	0.000	tUnc				memq_memq_0_1
1.695	0.118	tHld		1	BSRAM_R36[15]	memq_memq_0_1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.271, 57.309%; tC2Q: 0.202, 42.691%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path19

Path Summary:

Slack	0.355
Data Arrival Time	2.051
Data Required Time	1.695
From	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[7]
To	u_la0_top/u_ao_mem_ctrl/mem_mem_0_43
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	581	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R9C9[1][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[7]/CLK
1.779	0.202	tC2Q	RR	67	R9C9[1][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[7]/Q
2.051	0.271	tNET	RR	1	BSRAM_R10[2]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_43/ADA8

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	581	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	BSRAM_R10[2]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_43/CLKA
1.577	0.000	tUnc				u_la0_top/u_ao_mem_ctrl/mem_mem_0_43
1.695	0.118	tHld		1	BSRAM_R10[2]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_43

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.271, 57.319%; tC2Q: 0.202, 42.681%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path20

Path Summary:

Slack	0.355
Data Arrival Time	2.051
Data Required Time	1.695
From	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[10]
To	u_la0_top/u_ao_mem_ctrl/mem_mem_0_20
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	581	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R11C7[1][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[10]/CLK
1.779	0.202	tC2Q	RR	67	R11C7[1][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[10]/Q
2.051	0.271	tNET	RR	1	BSRAM_R10[1]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_20/ADA11

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	581	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	BSRAM_R10[1]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_20/CLKA
1.577	0.000	tUnc				u_la0_top/u_ao_mem_ctrl/mem_mem_0_20
1.695	0.118	tHld		1	BSRAM_R10[1]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_20

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.271, 57.319%; tC2Q: 0.202, 42.681%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path21

Path Summary:

Slack	0.361
Data Arrival Time	2.057
Data Required Time	1.695
From	cnt_Z[11]
To	memq_memq_0_1
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	581	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R33C51[2][A]	cnt_Z[11]/CLK
1.779	0.202	tC2Q	RR	34	R33C51[2][A]	cnt_Z[11]/Q
2.057	0.277	tNET	RR	1	BSRAM_R36[15]	memq_memq_0_1/ADA12

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	581	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	BSRAM_R36[15]	memq_memq_0_1/CLKA
1.577	0.000	tUnc				memq_memq_0_1
1.695	0.118	tHld		1	BSRAM_R36[15]	memq_memq_0_1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.277, 57.848%; tC2Q: 0.202, 42.152%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path22

Path Summary:

Slack	0.361
Data Arrival Time	2.057
Data Required Time	1.695
From	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[9]
To	u_la0_top/u_ao_mem_ctrl/mem_mem_0_43
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	581	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R11C7[1][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[9]/CLK
1.779	0.202	tC2Q	RR	67	R11C7[1][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[9]/Q
2.057	0.277	tNET	RR	1	BSRAM_R10[2]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_43/ADA10

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	581	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	BSRAM_R10[2]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_43/CLKA
1.577	0.000	tUnc				u_la0_top/u_ao_mem_ctrl/mem_mem_0_43
1.695	0.118	tHld		1	BSRAM_R10[2]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_43

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.277, 57.861%; tC2Q: 0.202, 42.139%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path23

Path Summary:

Slack	0.363
Data Arrival Time	2.189
Data Required Time	1.826
From	u_la0_top/u_ao_mem_ctrl/data_reg_Z[96]
To	u_la0_top/u_ao_mem_ctrl/mem_mem_0_48
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	581	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R12C9[0][A]	u_la0_top/u_ao_mem_ctrl/data_reg_Z[96]/CLK
1.779	0.202	tC2Q	RR	1	R12C9[0][A]	u_la0_top/u_ao_mem_ctrl/data_reg_Z[96]/Q
2.189	0.410	tNET	RR	1	BSRAM_R10[3]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_48/DI0

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	581	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	BSRAM_R10[3]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_48/CLKA
1.577	0.000	tUnc				u_la0_top/u_ao_mem_ctrl/mem_mem_0_48
1.826	0.249	tHld		1	BSRAM_R10[3]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_48

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.410, 66.974%; tC2Q: 0.202, 33.026%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path24

Path Summary:

Slack	0.365
Data Arrival Time	2.060
Data Required Time	1.695
From	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[10]
To	u_la0_top/u_ao_mem_ctrl/mem_mem_0_43
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	581	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R11C7[1][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[10]/CLK
1.779	0.202	tC2Q	RR	67	R11C7[1][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[10]/Q
2.060	0.281	tNET	RR	1	BSRAM_R10[2]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_43/ADA11

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	581	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	BSRAM_R10[2]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_43/CLKA
1.577	0.000	tUnc				u_la0_top/u_ao_mem_ctrl/mem_mem_0_43
1.695	0.118	tHld		1	BSRAM_R10[2]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_43

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.281, 58.181%; tC2Q: 0.202, 41.819%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path25

Path Summary:

Slack	0.421
Data Arrival Time	2.009
Data Required Time	1.588
From	Mdu/u_mdu/state[0]
To	m_Z[24]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	581	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R37C45[0][A]	Mdu/u_mdu/state[0]/CLK
1.778	0.201	tC2Q	RF	50	R37C45[0][A]	Mdu/u_mdu/state[0]/Q
1.778	0.000	tNET	FF	2	R37C47[1][A]	un1_m_cry_0_0/CIN
2.009	0.231	tINS	FF	1	R37C47[1][A]	un1_m_cry_0_0/SUM
2.009	0.000	tNET	FF	1	R37C47[1][A]	m_Z[24]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	581	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R37C47[1][A]	m_Z[24]/CLK
1.577	0.000	tUnc				m_Z[24]
1.588	0.011	tHld		1	R37C47[1][A]	m_Z[24]

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.231, 53.472%; route: 0.000, 0.000%; tC2Q: 0.201, 46.528%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Recovery Analysis Report

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	1.914
Data Arrival Time	9.734
Data Required Time	11.648
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.688	0.688	tINS	FF	581	IOT48[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R4C11[2][A]	u_la0_top/rst_ao_Z/CLK
7.148	0.232	tC2Q	FF	49	R4C11[2][A]	u_la0_top/rst_ao_Z/Q
9.734	2.586	tNET	FF	1	R8C10[1][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	581	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R8C10[1][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z/CLK
11.683	-0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z
11.648	-0.035	tSu		1	R8C10[1][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z

Path Statistics:

Clock Skew	-0.033
Setup Relationship	5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.586, 91.769%; tC2Q: 0.232, 8.231%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path2

Path Summary:

Slack	1.914
Data Arrival Time	9.734
Data Required Time	11.648
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_Z
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.688	0.688	tINS	FF	581	IOT48[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R4C11[2][A]	u_la0_top/rst_ao_Z/CLK
7.148	0.232	tC2Q	FF	49	R4C11[2][A]	u_la0_top/rst_ao_Z/Q
9.734	2.586	tNET	FF	1	R3C4[0][A]	u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_Z/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	581	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R3C4[0][A]	u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_Z/CLK
11.683	-0.200	tUnc				u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_Z
11.648	-0.035	tSu		1	R3C4[0][A]	u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_Z

Path Statistics:

Clock Skew	-0.033
Setup Relationship	5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.586, 91.769%; tC2Q: 0.232, 8.231%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path3

Path Summary:

Slack	1.914
Data Arrival Time	9.734
Data Required Time	11.648
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_loop_Z
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.688	0.688	tINS	FF	581	IOT48[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R4C11[2][A]	u_la0_top/rst_ao_Z/CLK
7.148	0.232	tC2Q	FF	49	R4C11[2][A]	u_la0_top/rst_ao_Z/Q
9.734	2.586	tNET	FF	1	R8C10[2][A]	u_la0_top/u_ao_mem_ctrl/capture_loop_Z/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	581	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R8C10[2][A]	u_la0_top/u_ao_mem_ctrl/capture_loop_Z/CLK
11.683	-0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_loop_Z
11.648	-0.035	tSu		1	R8C10[2][A]	u_la0_top/u_ao_mem_ctrl/capture_loop_Z

Path Statistics:

Clock Skew	-0.033
Setup Relationship	5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.586, 91.769%; tC2Q: 0.232, 8.231%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path4

Path Summary:

Slack	1.914
Data Arrival Time	9.734
Data Required Time	11.648
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_length_Z[0]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.688	0.688	tINS	FF	581	IOT48[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R4C11[2][A]	u_la0_top/rst_ao_Z/CLK
7.148	0.232	tC2Q	FF	49	R4C11[2][A]	u_la0_top/rst_ao_Z/Q
9.734	2.586	tNET	FF	1	R6C11[2][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[0]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	581	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R6C11[2][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[0]/CLK
11.683	-0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_length_Z[0]
11.648	-0.035	tSu		1	R6C11[2][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[0]

Path Statistics:

Clock Skew	-0.033
Setup Relationship	5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.586, 91.769%; tC2Q: 0.232, 8.231%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path5

Path Summary:

Slack	1.914
Data Arrival Time	9.734
Data Required Time	11.648
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_length_Z[1]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.688	0.688	tINS	FF	581	IOT48[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R4C11[2][A]	u_la0_top/rst_ao_Z/CLK
7.148	0.232	tC2Q	FF	49	R4C11[2][A]	u_la0_top/rst_ao_Z/Q
9.734	2.586	tNET	FF	1	R8C10[0][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[1]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	581	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R8C10[0][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[1]/CLK
11.683	-0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_length_Z[1]
11.648	-0.035	tSu		1	R8C10[0][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[1]

Path Statistics:

Clock Skew	-0.033
Setup Relationship	5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.586, 91.769%; tC2Q: 0.232, 8.231%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path6

Path Summary:

Slack	1.914
Data Arrival Time	9.734
Data Required Time	11.648
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_length_Z[2]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.688	0.688	tINS	FF	581	IOT48[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R4C11[2][A]	u_la0_top/rst_ao_Z/CLK
7.148	0.232	tC2Q	FF	49	R4C11[2][A]	u_la0_top/rst_ao_Z/Q
9.734	2.586	tNET	FF	1	R8C10[0][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[2]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	581	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R8C10[0][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[2]/CLK
11.683	-0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_length_Z[2]
11.648	-0.035	tSu		1	R8C10[0][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[2]

Path Statistics:

Clock Skew	-0.033
Setup Relationship	5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.586, 91.769%; tC2Q: 0.232, 8.231%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path7

Path Summary:

Slack	1.914
Data Arrival Time	9.734
Data Required Time	11.648
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_length_Z[3]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.688	0.688	tINS	FF	581	IOT48[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R4C11[2][A]	u_la0_top/rst_ao_Z/CLK
7.148	0.232	tC2Q	FF	49	R4C11[2][A]	u_la0_top/rst_ao_Z/Q
9.734	2.586	tNET	FF	1	R11C9[1][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[3]/PRESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	581	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R11C9[1][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[3]/CLK
11.683	-0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_length_Z[3]
11.648	-0.035	tSu		1	R11C9[1][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[3]

Path Statistics:

Clock Skew	-0.033
Setup Relationship	5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.586, 91.769%; tC2Q: 0.232, 8.231%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path8

Path Summary:

Slack	1.914
Data Arrival Time	9.734
Data Required Time	11.648
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_length_Z[4]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.688	0.688	tINS	FF	581	IOT48[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R4C11[2][A]	u_la0_top/rst_ao_Z/CLK
7.148	0.232	tC2Q	FF	49	R4C11[2][A]	u_la0_top/rst_ao_Z/Q
9.734	2.586	tNET	FF	1	R8C9[1][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[4]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	581	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R8C9[1][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[4]/CLK
11.683	-0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_length_Z[4]
11.648	-0.035	tSu		1	R8C9[1][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[4]

Path Statistics:

Clock Skew	-0.033
Setup Relationship	5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.586, 91.769%; tC2Q: 0.232, 8.231%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path9

Path Summary:

Slack	1.914
Data Arrival Time	9.734
Data Required Time	11.648
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_length_Z[5]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.688	0.688	tINS	FF	581	IOT48[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R4C11[2][A]	u_la0_top/rst_ao_Z/CLK
7.148	0.232	tC2Q	FF	49	R4C11[2][A]	u_la0_top/rst_ao_Z/Q
9.734	2.586	tNET	FF	1	R8C9[0][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[5]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	581	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R8C9[0][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[5]/CLK
11.683	-0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_length_Z[5]
11.648	-0.035	tSu		1	R8C9[0][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[5]

Path Statistics:

Clock Skew	-0.033
Setup Relationship	5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.586, 91.769%; tC2Q: 0.232, 8.231%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path10

Path Summary:

Slack	1.914
Data Arrival Time	9.734
Data Required Time	11.648
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_length_Z[6]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.688	0.688	tINS	FF	581	IOT48[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R4C11[2][A]	u_la0_top/rst_ao_Z/CLK
7.148	0.232	tC2Q	FF	49	R4C11[2][A]	u_la0_top/rst_ao_Z/Q
9.734	2.586	tNET	FF	1	R8C9[0][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[6]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	581	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R8C9[0][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[6]/CLK
11.683	-0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_length_Z[6]
11.648	-0.035	tSu		1	R8C9[0][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[6]

Path Statistics:

Clock Skew	-0.033
Setup Relationship	5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.586, 91.769%; tC2Q: 0.232, 8.231%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path11

Path Summary:

Slack	1.914
Data Arrival Time	9.734
Data Required Time	11.648
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_length_Z[7]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.688	0.688	tINS	FF	581	IOT48[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R4C11[2][A]	u_la0_top/rst_ao_Z/CLK
7.148	0.232	tC2Q	FF	49	R4C11[2][A]	u_la0_top/rst_ao_Z/Q
9.734	2.586	tNET	FF	1	R9C10[2][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[7]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	581	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R9C10[2][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[7]/CLK
11.683	-0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_length_Z[7]
11.648	-0.035	tSu		1	R9C10[2][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[7]

Path Statistics:

Clock Skew	-0.033
Setup Relationship	5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.586, 91.769%; tC2Q: 0.232, 8.231%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path12

Path Summary:

Slack	1.914
Data Arrival Time	9.734
Data Required Time	11.648
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_length_Z[8]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.688	0.688	tINS	FF	581	IOT48[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R4C11[2][A]	u_la0_top/rst_ao_Z/CLK
7.148	0.232	tC2Q	FF	49	R4C11[2][A]	u_la0_top/rst_ao_Z/Q
9.734	2.586	tNET	FF	1	R9C10[2][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[8]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	581	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R9C10[2][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[8]/CLK
11.683	-0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_length_Z[8]
11.648	-0.035	tSu		1	R9C10[2][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[8]

Path Statistics:

Clock Skew	-0.033
Setup Relationship	5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.586, 91.769%; tC2Q: 0.232, 8.231%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path13

Path Summary:

Slack	1.914
Data Arrival Time	9.734
Data Required Time	11.648
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_length_Z[9]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.688	0.688	tINS	FF	581	IOT48[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R4C11[2][A]	u_la0_top/rst_ao_Z/CLK
7.148	0.232	tC2Q	FF	49	R4C11[2][A]	u_la0_top/rst_ao_Z/Q
9.734	2.586	tNET	FF	1	R9C10[0][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[9]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	581	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R9C10[0][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[9]/CLK
11.683	-0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_length_Z[9]
11.648	-0.035	tSu		1	R9C10[0][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[9]

Path Statistics:

Clock Skew	-0.033
Setup Relationship	5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.586, 91.769%; tC2Q: 0.232, 8.231%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path14

Path Summary:

Slack	1.914
Data Arrival Time	9.734
Data Required Time	11.648
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_length_Z[10]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.688	0.688	tINS	FF	581	IOT48[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R4C11[2][A]	u_la0_top/rst_ao_Z/CLK
7.148	0.232	tC2Q	FF	49	R4C11[2][A]	u_la0_top/rst_ao_Z/Q
9.734	2.586	tNET	FF	1	R9C2[0][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[10]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	581	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R9C2[0][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[10]/CLK
11.683	-0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_length_Z[10]
11.648	-0.035	tSu		1	R9C2[0][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[10]

Path Statistics:

Clock Skew	-0.033
Setup Relationship	5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.586, 91.769%; tC2Q: 0.232, 8.231%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path15

Path Summary:

Slack	1.914
Data Arrival Time	9.734
Data Required Time	11.648
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_length_Z[11]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.688	0.688	tINS	FF	581	IOT48[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R4C11[2][A]	u_la0_top/rst_ao_Z/CLK
7.148	0.232	tC2Q	FF	49	R4C11[2][A]	u_la0_top/rst_ao_Z/Q
9.734	2.586	tNET	FF	1	R8C9[1][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[11]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	581	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R8C9[1][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[11]/CLK
11.683	-0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_length_Z[11]
11.648	-0.035	tSu		1	R8C9[1][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[11]

Path Statistics:

Clock Skew	-0.033
Setup Relationship	5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.586, 91.769%; tC2Q: 0.232, 8.231%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path16

Path Summary:

Slack	1.914
Data Arrival Time	9.734
Data Required Time	11.648
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_length_Z[12]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.688	0.688	tINS	FF	581	IOT48[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R4C11[2][A]	u_la0_top/rst_ao_Z/CLK
7.148	0.232	tC2Q	FF	49	R4C11[2][A]	u_la0_top/rst_ao_Z/Q
9.734	2.586	tNET	FF	1	R2C4[2][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[12]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	581	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R2C4[2][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[12]/CLK
11.683	-0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_length_Z[12]
11.648	-0.035	tSu		1	R2C4[2][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[12]

Path Statistics:

Clock Skew	-0.033
Setup Relationship	5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.586, 91.769%; tC2Q: 0.232, 8.231%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path17

Path Summary:

Slack	1.914
Data Arrival Time	9.734
Data Required Time	11.648
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.688	0.688	tINS	FF	581	IOT48[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R4C11[2][A]	u_la0_top/rst_ao_Z/CLK
7.148	0.232	tC2Q	FF	49	R4C11[2][A]	u_la0_top/rst_ao_Z/Q
9.734	2.586	tNET	FF	1	R9C8[2][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	581	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R9C8[2][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0]/CLK
11.683	-0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0]
11.648	-0.035	tSu		1	R9C8[2][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0]

Path Statistics:

Clock Skew	-0.033
Setup Relationship	5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.586, 91.769%; tC2Q: 0.232, 8.231%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path18

Path Summary:

Slack	1.914
Data Arrival Time	9.734
Data Required Time	11.648
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[1]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.688	0.688	tINS	FF	581	IOT48[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R4C11[2][A]	u_la0_top/rst_ao_Z/CLK
7.148	0.232	tC2Q	FF	49	R4C11[2][A]	u_la0_top/rst_ao_Z/Q
9.734	2.586	tNET	FF	1	R9C8[2][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[1]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	581	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R9C8[2][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[1]/CLK
11.683	-0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[1]
11.648	-0.035	tSu		1	R9C8[2][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[1]

Path Statistics:

Clock Skew	-0.033
Setup Relationship	5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.586, 91.769%; tC2Q: 0.232, 8.231%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path19

Path Summary:

Slack	1.914
Data Arrival Time	9.734
Data Required Time	11.648
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[2]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.688	0.688	tINS	FF	581	IOT48[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R4C11[2][A]	u_la0_top/rst_ao_Z/CLK
7.148	0.232	tC2Q	FF	49	R4C11[2][A]	u_la0_top/rst_ao_Z/Q
9.734	2.586	tNET	FF	1	R9C9[0][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[2]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	581	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R9C9[0][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[2]/CLK
11.683	-0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[2]
11.648	-0.035	tSu		1	R9C9[0][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[2]

Path Statistics:

Clock Skew	-0.033
Setup Relationship	5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.586, 91.769%; tC2Q: 0.232, 8.231%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path20

Path Summary:

Slack	1.914
Data Arrival Time	9.734
Data Required Time	11.648
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[3]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.688	0.688	tINS	FF	581	IOT48[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R4C11[2][A]	u_la0_top/rst_ao_Z/CLK
7.148	0.232	tC2Q	FF	49	R4C11[2][A]	u_la0_top/rst_ao_Z/Q
9.734	2.586	tNET	FF	1	R9C9[0][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[3]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	581	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R9C9[0][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[3]/CLK
11.683	-0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[3]
11.648	-0.035	tSu		1	R9C9[0][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[3]

Path Statistics:

Clock Skew	-0.033
Setup Relationship	5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.586, 91.769%; tC2Q: 0.232, 8.231%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path21

Path Summary:

Slack	1.914
Data Arrival Time	9.734
Data Required Time	11.648
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[4]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.688	0.688	tINS	FF	581	IOT48[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R4C11[2][A]	u_la0_top/rst_ao_Z/CLK
7.148	0.232	tC2Q	FF	49	R4C11[2][A]	u_la0_top/rst_ao_Z/Q
9.734	2.586	tNET	FF	1	R9C9[1][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[4]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	581	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R9C9[1][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[4]/CLK
11.683	-0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[4]
11.648	-0.035	tSu		1	R9C9[1][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[4]

Path Statistics:

Clock Skew	-0.033
Setup Relationship	5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.586, 91.769%; tC2Q: 0.232, 8.231%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path22

Path Summary:

Slack	1.914
Data Arrival Time	9.734
Data Required Time	11.648
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[5]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.688	0.688	tINS	FF	581	IOT48[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R4C11[2][A]	u_la0_top/rst_ao_Z/CLK
7.148	0.232	tC2Q	FF	49	R4C11[2][A]	u_la0_top/rst_ao_Z/Q
9.734	2.586	tNET	FF	1	R9C10[1][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[5]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	581	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R9C10[1][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[5]/CLK
11.683	-0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[5]
11.648	-0.035	tSu		1	R9C10[1][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[5]

Path Statistics:

Clock Skew	-0.033
Setup Relationship	5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.586, 91.769%; tC2Q: 0.232, 8.231%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path23

Path Summary:

Slack	1.914
Data Arrival Time	9.734
Data Required Time	11.648
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[6]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.688	0.688	tINS	FF	581	IOT48[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R4C11[2][A]	u_la0_top/rst_ao_Z/CLK
7.148	0.232	tC2Q	FF	49	R4C11[2][A]	u_la0_top/rst_ao_Z/Q
9.734	2.586	tNET	FF	1	R12C8[0][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[6]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	581	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R12C8[0][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[6]/CLK
11.683	-0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[6]
11.648	-0.035	tSu		1	R12C8[0][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[6]

Path Statistics:

Clock Skew	-0.033
Setup Relationship	5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.586, 91.769%; tC2Q: 0.232, 8.231%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path24

Path Summary:

Slack	1.914
Data Arrival Time	9.734
Data Required Time	11.648
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[7]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.688	0.688	tINS	FF	581	IOT48[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R4C11[2][A]	u_la0_top/rst_ao_Z/CLK
7.148	0.232	tC2Q	FF	49	R4C11[2][A]	u_la0_top/rst_ao_Z/Q
9.734	2.586	tNET	FF	1	R9C9[1][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[7]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	581	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R9C9[1][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[7]/CLK
11.683	-0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[7]
11.648	-0.035	tSu		1	R9C9[1][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[7]

Path Statistics:

Clock Skew	-0.033
Setup Relationship	5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.586, 91.769%; tC2Q: 0.232, 8.231%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path25

Path Summary:

Slack	1.914
Data Arrival Time	9.734
Data Required Time	11.648
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.688	0.688	tINS	FF	581	IOT48[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R4C11[2][A]	u_la0_top/rst_ao_Z/CLK
7.148	0.232	tC2Q	FF	49	R4C11[2][A]	u_la0_top/rst_ao_Z/Q
9.734	2.586	tNET	FF	1	R9C10[1][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	581	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R9C10[1][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8]/CLK
11.683	-0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8]
11.648	-0.035	tSu		1	R9C10[1][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8]

Path Statistics:

Clock Skew	-0.033
Setup Relationship	5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.586, 91.769%; tC2Q: 0.232, 8.231%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Removal Analysis Report

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	6.623
Data Arrival Time	8.411
Data Required Time	1.788
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.677	0.678	tINS	FF	581	IOT48[A]	clk_ibuf/O
6.590	0.913	tNET	FF	1	R4C11[2][A]	u_la0_top/rst_ao_Z/CLK
6.792	0.202	tC2Q	FR	49	R4C11[2][A]	u_la0_top/rst_ao_Z/Q
8.411	1.619	tNET	RR	1	R8C10[1][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	581	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R8C10[1][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z/CLK
1.777	0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z
1.788	0.011	tHld		1	R8C10[1][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.619, 88.906%; tC2Q: 0.202, 11.094%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path2

Path Summary:

Slack	6.623
Data Arrival Time	8.411
Data Required Time	1.788
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_loop_Z
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.677	0.678	tINS	FF	581	IOT48[A]	clk_ibuf/O
6.590	0.913	tNET	FF	1	R4C11[2][A]	u_la0_top/rst_ao_Z/CLK
6.792	0.202	tC2Q	FR	49	R4C11[2][A]	u_la0_top/rst_ao_Z/Q
8.411	1.619	tNET	RR	1	R8C10[2][A]	u_la0_top/u_ao_mem_ctrl/capture_loop_Z/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	581	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R8C10[2][A]	u_la0_top/u_ao_mem_ctrl/capture_loop_Z/CLK
1.777	0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_loop_Z
1.788	0.011	tHld		1	R8C10[2][A]	u_la0_top/u_ao_mem_ctrl/capture_loop_Z

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.619, 88.906%; tC2Q: 0.202, 11.094%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path3

Path Summary:

Slack	6.623
Data Arrival Time	8.411
Data Required Time	1.788
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_length_Z[0]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.677	0.678	tINS	FF	581	IOT48[A]	clk_ibuf/O
6.590	0.913	tNET	FF	1	R4C11[2][A]	u_la0_top/rst_ao_Z/CLK
6.792	0.202	tC2Q	FR	49	R4C11[2][A]	u_la0_top/rst_ao_Z/Q
8.411	1.619	tNET	RR	1	R6C11[2][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[0]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	581	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R6C11[2][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[0]/CLK
1.777	0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_length_Z[0]
1.788	0.011	tHld		1	R6C11[2][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[0]

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.619, 88.906%; tC2Q: 0.202, 11.094%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path4

Path Summary:

Slack	6.623
Data Arrival Time	8.411
Data Required Time	1.788
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_length_Z[1]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.677	0.678	tINS	FF	581	IOT48[A]	clk_ibuf/O
6.590	0.913	tNET	FF	1	R4C11[2][A]	u_la0_top/rst_ao_Z/CLK
6.792	0.202	tC2Q	FR	49	R4C11[2][A]	u_la0_top/rst_ao_Z/Q
8.411	1.619	tNET	RR	1	R8C10[0][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[1]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	581	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R8C10[0][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[1]/CLK
1.777	0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_length_Z[1]
1.788	0.011	tHld		1	R8C10[0][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[1]

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.619, 88.906%; tC2Q: 0.202, 11.094%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path5

Path Summary:

Slack	6.623
Data Arrival Time	8.411
Data Required Time	1.788
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_length_Z[2]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.677	0.678	tINS	FF	581	IOT48[A]	clk_ibuf/O
6.590	0.913	tNET	FF	1	R4C11[2][A]	u_la0_top/rst_ao_Z/CLK
6.792	0.202	tC2Q	FR	49	R4C11[2][A]	u_la0_top/rst_ao_Z/Q
8.411	1.619	tNET	RR	1	R8C10[0][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[2]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	581	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R8C10[0][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[2]/CLK
1.777	0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_length_Z[2]
1.788	0.011	tHld		1	R8C10[0][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[2]

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.619, 88.906%; tC2Q: 0.202, 11.094%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path6

Path Summary:

Slack	6.623
Data Arrival Time	8.411
Data Required Time	1.788
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_length_Z[4]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.677	0.678	tINS	FF	581	IOT48[A]	clk_ibuf/O
6.590	0.913	tNET	FF	1	R4C11[2][A]	u_la0_top/rst_ao_Z/CLK
6.792	0.202	tC2Q	FR	49	R4C11[2][A]	u_la0_top/rst_ao_Z/Q
8.411	1.619	tNET	RR	1	R8C9[1][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[4]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	581	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R8C9[1][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[4]/CLK
1.777	0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_length_Z[4]
1.788	0.011	tHld		1	R8C9[1][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[4]

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.619, 88.906%; tC2Q: 0.202, 11.094%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path7

Path Summary:

Slack	6.623
Data Arrival Time	8.411
Data Required Time	1.788
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_length_Z[5]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.677	0.678	tINS	FF	581	IOT48[A]	clk_ibuf/O
6.590	0.913	tNET	FF	1	R4C11[2][A]	u_la0_top/rst_ao_Z/CLK
6.792	0.202	tC2Q	FR	49	R4C11[2][A]	u_la0_top/rst_ao_Z/Q
8.411	1.619	tNET	RR	1	R8C9[0][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[5]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	581	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R8C9[0][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[5]/CLK
1.777	0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_length_Z[5]
1.788	0.011	tHld		1	R8C9[0][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[5]

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.619, 88.906%; tC2Q: 0.202, 11.094%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path8

Path Summary:

Slack	6.623
Data Arrival Time	8.411
Data Required Time	1.788
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_length_Z[7]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.677	0.678	tINS	FF	581	IOT48[A]	clk_ibuf/O
6.590	0.913	tNET	FF	1	R4C11[2][A]	u_la0_top/rst_ao_Z/CLK
6.792	0.202	tC2Q	FR	49	R4C11[2][A]	u_la0_top/rst_ao_Z/Q
8.411	1.619	tNET	RR	1	R9C10[2][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[7]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	581	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R9C10[2][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[7]/CLK
1.777	0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_length_Z[7]
1.788	0.011	tHld		1	R9C10[2][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[7]

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.619, 88.906%; tC2Q: 0.202, 11.094%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path9

Path Summary:

Slack	6.623
Data Arrival Time	8.411
Data Required Time	1.788
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_length_Z[8]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.677	0.678	tINS	FF	581	IOT48[A]	clk_ibuf/O
6.590	0.913	tNET	FF	1	R4C11[2][A]	u_la0_top/rst_ao_Z/CLK
6.792	0.202	tC2Q	FR	49	R4C11[2][A]	u_la0_top/rst_ao_Z/Q
8.411	1.619	tNET	RR	1	R9C10[2][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[8]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	581	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R9C10[2][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[8]/CLK
1.777	0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_length_Z[8]
1.788	0.011	tHld		1	R9C10[2][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[8]

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.619, 88.906%; tC2Q: 0.202, 11.094%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path10

Path Summary:

Slack	6.623
Data Arrival Time	8.411
Data Required Time	1.788
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_length_Z[9]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.677	0.678	tINS	FF	581	IOT48[A]	clk_ibuf/O
6.590	0.913	tNET	FF	1	R4C11[2][A]	u_la0_top/rst_ao_Z/CLK
6.792	0.202	tC2Q	FR	49	R4C11[2][A]	u_la0_top/rst_ao_Z/Q
8.411	1.619	tNET	RR	1	R9C10[0][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[9]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	581	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R9C10[0][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[9]/CLK
1.777	0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_length_Z[9]
1.788	0.011	tHld		1	R9C10[0][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[9]

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.619, 88.906%; tC2Q: 0.202, 11.094%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path11

Path Summary:

Slack	6.623
Data Arrival Time	8.411
Data Required Time	1.788
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_length_Z[10]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.677	0.678	tINS	FF	581	IOT48[A]	clk_ibuf/O
6.590	0.913	tNET	FF	1	R4C11[2][A]	u_la0_top/rst_ao_Z/CLK
6.792	0.202	tC2Q	FR	49	R4C11[2][A]	u_la0_top/rst_ao_Z/Q
8.411	1.619	tNET	RR	1	R9C2[0][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[10]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	581	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R9C2[0][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[10]/CLK
1.777	0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_length_Z[10]
1.788	0.011	tHld		1	R9C2[0][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[10]

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.619, 88.906%; tC2Q: 0.202, 11.094%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path12

Path Summary:

Slack	6.623
Data Arrival Time	8.411
Data Required Time	1.788
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_length_Z[11]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.677	0.678	tINS	FF	581	IOT48[A]	clk_ibuf/O
6.590	0.913	tNET	FF	1	R4C11[2][A]	u_la0_top/rst_ao_Z/CLK
6.792	0.202	tC2Q	FR	49	R4C11[2][A]	u_la0_top/rst_ao_Z/Q
8.411	1.619	tNET	RR	1	R8C9[1][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[11]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	581	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R8C9[1][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[11]/CLK
1.777	0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_length_Z[11]
1.788	0.011	tHld		1	R8C9[1][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[11]

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.619, 88.906%; tC2Q: 0.202, 11.094%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path13

Path Summary:

Slack	6.623
Data Arrival Time	8.411
Data Required Time	1.788
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_length_Z[12]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.677	0.678	tINS	FF	581	IOT48[A]	clk_ibuf/O
6.590	0.913	tNET	FF	1	R4C11[2][A]	u_la0_top/rst_ao_Z/CLK
6.792	0.202	tC2Q	FR	49	R4C11[2][A]	u_la0_top/rst_ao_Z/Q
8.411	1.619	tNET	RR	1	R2C4[2][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[12]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	581	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R2C4[2][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[12]/CLK
1.777	0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_length_Z[12]
1.788	0.011	tHld		1	R2C4[2][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[12]

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.619, 88.906%; tC2Q: 0.202, 11.094%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path14

Path Summary:

Slack	6.623
Data Arrival Time	8.411
Data Required Time	1.788
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.677	0.678	tINS	FF	581	IOT48[A]	clk_ibuf/O
6.590	0.913	tNET	FF	1	R4C11[2][A]	u_la0_top/rst_ao_Z/CLK
6.792	0.202	tC2Q	FR	49	R4C11[2][A]	u_la0_top/rst_ao_Z/Q
8.411	1.619	tNET	RR	1	R9C8[2][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	581	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R9C8[2][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0]/CLK
1.777	0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0]
1.788	0.011	tHld		1	R9C8[2][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0]

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.619, 88.906%; tC2Q: 0.202, 11.094%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path15

Path Summary:

Slack	6.623
Data Arrival Time	8.411
Data Required Time	1.788
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[1]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.677	0.678	tINS	FF	581	IOT48[A]	clk_ibuf/O
6.590	0.913	tNET	FF	1	R4C11[2][A]	u_la0_top/rst_ao_Z/CLK
6.792	0.202	tC2Q	FR	49	R4C11[2][A]	u_la0_top/rst_ao_Z/Q
8.411	1.619	tNET	RR	1	R9C8[2][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[1]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	581	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R9C8[2][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[1]/CLK
1.777	0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[1]
1.788	0.011	tHld		1	R9C8[2][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[1]

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.619, 88.906%; tC2Q: 0.202, 11.094%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path16

Path Summary:

Slack	6.623
Data Arrival Time	8.411
Data Required Time	1.788
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[2]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.677	0.678	tINS	FF	581	IOT48[A]	clk_ibuf/O
6.590	0.913	tNET	FF	1	R4C11[2][A]	u_la0_top/rst_ao_Z/CLK
6.792	0.202	tC2Q	FR	49	R4C11[2][A]	u_la0_top/rst_ao_Z/Q
8.411	1.619	tNET	RR	1	R9C9[0][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[2]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	581	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R9C9[0][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[2]/CLK
1.777	0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[2]
1.788	0.011	tHld		1	R9C9[0][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[2]

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.619, 88.906%; tC2Q: 0.202, 11.094%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path17

Path Summary:

Slack	6.623
Data Arrival Time	8.411
Data Required Time	1.788
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[3]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.677	0.678	tINS	FF	581	IOT48[A]	clk_ibuf/O
6.590	0.913	tNET	FF	1	R4C11[2][A]	u_la0_top/rst_ao_Z/CLK
6.792	0.202	tC2Q	FR	49	R4C11[2][A]	u_la0_top/rst_ao_Z/Q
8.411	1.619	tNET	RR	1	R9C9[0][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[3]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	581	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R9C9[0][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[3]/CLK
1.777	0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[3]
1.788	0.011	tHld		1	R9C9[0][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[3]

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.619, 88.906%; tC2Q: 0.202, 11.094%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path18

Path Summary:

Slack	6.623
Data Arrival Time	8.411
Data Required Time	1.788
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[4]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.677	0.678	tINS	FF	581	IOT48[A]	clk_ibuf/O
6.590	0.913	tNET	FF	1	R4C11[2][A]	u_la0_top/rst_ao_Z/CLK
6.792	0.202	tC2Q	FR	49	R4C11[2][A]	u_la0_top/rst_ao_Z/Q
8.411	1.619	tNET	RR	1	R9C9[1][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[4]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	581	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R9C9[1][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[4]/CLK
1.777	0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[4]
1.788	0.011	tHld		1	R9C9[1][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[4]

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.619, 88.906%; tC2Q: 0.202, 11.094%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path19

Path Summary:

Slack	6.623
Data Arrival Time	8.411
Data Required Time	1.788
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[5]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.677	0.678	tINS	FF	581	IOT48[A]	clk_ibuf/O
6.590	0.913	tNET	FF	1	R4C11[2][A]	u_la0_top/rst_ao_Z/CLK
6.792	0.202	tC2Q	FR	49	R4C11[2][A]	u_la0_top/rst_ao_Z/Q
8.411	1.619	tNET	RR	1	R9C10[1][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[5]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	581	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R9C10[1][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[5]/CLK
1.777	0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[5]
1.788	0.011	tHld		1	R9C10[1][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[5]

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.619, 88.906%; tC2Q: 0.202, 11.094%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path20

Path Summary:

Slack	6.623
Data Arrival Time	8.411
Data Required Time	1.788
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[6]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.677	0.678	tINS	FF	581	IOT48[A]	clk_ibuf/O
6.590	0.913	tNET	FF	1	R4C11[2][A]	u_la0_top/rst_ao_Z/CLK
6.792	0.202	tC2Q	FR	49	R4C11[2][A]	u_la0_top/rst_ao_Z/Q
8.411	1.619	tNET	RR	1	R12C8[0][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[6]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	581	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R12C8[0][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[6]/CLK
1.777	0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[6]
1.788	0.011	tHld		1	R12C8[0][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[6]

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.619, 88.906%; tC2Q: 0.202, 11.094%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path21

Path Summary:

Slack	6.623
Data Arrival Time	8.411
Data Required Time	1.788
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[7]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.677	0.678	tINS	FF	581	IOT48[A]	clk_ibuf/O
6.590	0.913	tNET	FF	1	R4C11[2][A]	u_la0_top/rst_ao_Z/CLK
6.792	0.202	tC2Q	FR	49	R4C11[2][A]	u_la0_top/rst_ao_Z/Q
8.411	1.619	tNET	RR	1	R9C9[1][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[7]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	581	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R9C9[1][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[7]/CLK
1.777	0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[7]
1.788	0.011	tHld		1	R9C9[1][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[7]

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.619, 88.906%; tC2Q: 0.202, 11.094%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path22

Path Summary:

Slack	6.623
Data Arrival Time	8.411
Data Required Time	1.788
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.677	0.678	tINS	FF	581	IOT48[A]	clk_ibuf/O
6.590	0.913	tNET	FF	1	R4C11[2][A]	u_la0_top/rst_ao_Z/CLK
6.792	0.202	tC2Q	FR	49	R4C11[2][A]	u_la0_top/rst_ao_Z/Q
8.411	1.619	tNET	RR	1	R9C10[1][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	581	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R9C10[1][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8]/CLK
1.777	0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8]
1.788	0.011	tHld		1	R9C10[1][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8]

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.619, 88.906%; tC2Q: 0.202, 11.094%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path23

Path Summary:

Slack	6.623
Data Arrival Time	8.411
Data Required Time	1.788
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[9]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.677	0.678	tINS	FF	581	IOT48[A]	clk_ibuf/O
6.590	0.913	tNET	FF	1	R4C11[2][A]	u_la0_top/rst_ao_Z/CLK
6.792	0.202	tC2Q	FR	49	R4C11[2][A]	u_la0_top/rst_ao_Z/Q
8.411	1.619	tNET	RR	1	R11C7[1][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[9]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	581	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R11C7[1][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[9]/CLK
1.777	0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[9]
1.788	0.011	tHld		1	R11C7[1][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[9]

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.619, 88.906%; tC2Q: 0.202, 11.094%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path24

Path Summary:

Slack	6.623
Data Arrival Time	8.411
Data Required Time	1.788
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[10]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.677	0.678	tINS	FF	581	IOT48[A]	clk_ibuf/O
6.590	0.913	tNET	FF	1	R4C11[2][A]	u_la0_top/rst_ao_Z/CLK
6.792	0.202	tC2Q	FR	49	R4C11[2][A]	u_la0_top/rst_ao_Z/Q
8.411	1.619	tNET	RR	1	R11C7[1][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[10]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	581	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R11C7[1][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[10]/CLK
1.777	0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[10]
1.788	0.011	tHld		1	R11C7[1][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[10]

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.619, 88.906%; tC2Q: 0.202, 11.094%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path25

Path Summary:

Slack	6.623
Data Arrival Time	8.411
Data Required Time	1.788
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[11]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.677	0.678	tINS	FF	581	IOT48[A]	clk_ibuf/O
6.590	0.913	tNET	FF	1	R4C11[2][A]	u_la0_top/rst_ao_Z/CLK
6.792	0.202	tC2Q	FR	49	R4C11[2][A]	u_la0_top/rst_ao_Z/Q
8.411	1.619	tNET	RR	1	R11C8[1][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[11]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	581	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R11C8[1][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[11]/CLK
1.777	0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[11]
1.788	0.011	tHld		1	R11C8[1][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[11]

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.619, 88.906%; tC2Q: 0.202, 11.094%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Minimum Pulse Width Report:

Report Command:report_min_pulse_width -nworst 10 -detail

MPW1

MPW Summary:

Slack:	3.662
Actual Width:	4.662
Required Width:	1.000
Type:	Low Pulse Width
Clock:	DEFAULT_CLK
Objects:	cnt_1_Z[12]

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	clk_ibuf/I
5.688	0.688	tINS	FF	clk_ibuf/O
6.916	1.228	tNET	FF	cnt_1_Z[12]/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	clk_ibuf/I
10.675	0.675	tINS	RR	clk_ibuf/O
11.577	0.902	tNET	RR	cnt_1_Z[12]/CLK

MPW2

MPW Summary:

Slack:	3.662
Actual Width:	4.662
Required Width:	1.000
Type:	Low Pulse Width
Clock:	DEFAULT_CLK
Objects:	cnt_1_Z[10]

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	clk_ibuf/I
5.688	0.688	tINS	FF	clk_ibuf/O
6.916	1.228	tNET	FF	cnt_1_Z[10]/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	clk_ibuf/I
10.675	0.675	tINS	RR	clk_ibuf/O
11.577	0.902	tNET	RR	cnt_1_Z[10]/CLK

MPW3

MPW Summary:

Slack:	3.662
Actual Width:	4.662
Required Width:	1.000
Type:	Low Pulse Width
Clock:	DEFAULT_CLK
Objects:	cnt_1_Z[6]

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	clk_ibuf/I
5.688	0.688	tINS	FF	clk_ibuf/O
6.916	1.228	tNET	FF	cnt_1_Z[6]/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	clk_ibuf/I
10.675	0.675	tINS	RR	clk_ibuf/O
11.577	0.902	tNET	RR	cnt_1_Z[6]/CLK

MPW4

MPW Summary:

Slack:	3.662
Actual Width:	4.662
Required Width:	1.000
Type:	Low Pulse Width
Clock:	DEFAULT_CLK
Objects:	cnt_Z[11]

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	clk_ibuf/I
5.688	0.688	tINS	FF	clk_ibuf/O
6.916	1.228	tNET	FF	cnt_Z[11]/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	clk_ibuf/I
10.675	0.675	tINS	RR	clk_ibuf/O
11.577	0.902	tNET	RR	cnt_Z[11]/CLK

MPW5

MPW Summary:

Slack:	3.662
Actual Width:	4.662
Required Width:	1.000
Type:	Low Pulse Width
Clock:	DEFAULT_CLK
Objects:	n_Z[25]

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	clk_ibuf/I
5.688	0.688	tINS	FF	clk_ibuf/O
6.916	1.228	tNET	FF	n_Z[25]/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	clk_ibuf/I
10.675	0.675	tINS	RR	clk_ibuf/O
11.577	0.902	tNET	RR	n_Z[25]/CLK

MPW6

MPW Summary:

Slack:	3.662
Actual Width:	4.662
Required Width:	1.000
Type:	Low Pulse Width
Clock:	DEFAULT_CLK
Objects:	m_Z[27]

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	clk_ibuf/I
5.688	0.688	tINS	FF	clk_ibuf/O
6.916	1.228	tNET	FF	m_Z[27]/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	clk_ibuf/I
10.675	0.675	tINS	RR	clk_ibuf/O
11.577	0.902	tNET	RR	m_Z[27]/CLK

MPW7

MPW Summary:

Slack:	3.662
Actual Width:	4.662
Required Width:	1.000
Type:	Low Pulse Width
Clock:	DEFAULT_CLK
Objects:	memq_memq_0_13

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	clk_ibuf/I
5.688	0.688	tINS	FF	clk_ibuf/O
6.916	1.228	tNET	FF	memq_memq_0_13/CLKB

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	clk_ibuf/I
10.675	0.675	tINS	RR	clk_ibuf/O
11.577	0.902	tNET	RR	memq_memq_0_13/CLKB

MPW8

MPW Summary:

Slack:	3.662
Actual Width:	4.662
Required Width:	1.000
Type:	Low Pulse Width
Clock:	DEFAULT_CLK
Objects:	Mdu/u_mdu/reg0_fast_Z[31]

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	clk_ibuf/I
5.688	0.688	tINS	FF	clk_ibuf/O
6.916	1.228	tNET	FF	Mdu/u_mdu/reg0_fast_Z[31]/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	clk_ibuf/I
10.675	0.675	tINS	RR	clk_ibuf/O
11.577	0.902	tNET	RR	Mdu/u_mdu/reg0_fast_Z[31]/CLK

MPW9

MPW Summary:

Slack:	3.662
Actual Width:	4.662
Required Width:	1.000
Type:	Low Pulse Width
Clock:	DEFAULT_CLK
Objects:	u_la0_top/u_ao_mem_ctrl/data_reg_Z[118]

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	clk_ibuf/I
5.688	0.688	tINS	FF	clk_ibuf/O
6.916	1.228	tNET	FF	u_la0_top/u_ao_mem_ctrl/data_reg_Z[118]/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	clk_ibuf/I
10.675	0.675	tINS	RR	clk_ibuf/O
11.577	0.902	tNET	RR	u_la0_top/u_ao_mem_ctrl/data_reg_Z[118]/CLK

MPW10

MPW Summary:

Slack:	3.662
Actual Width:	4.662
Required Width:	1.000
Type:	Low Pulse Width
Clock:	DEFAULT_CLK
Objects:	u_la0_top/u_ao_mem_ctrl/data_reg_Z[119]

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	clk_ibuf/I
5.688	0.688	tINS	FF	clk_ibuf/O
6.916	1.228	tNET	FF	u_la0_top/u_ao_mem_ctrl/data_reg_Z[119]/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	clk_ibuf/I
10.675	0.675	tINS	RR	clk_ibuf/O
11.577	0.902	tNET	RR	u_la0_top/u_ao_mem_ctrl/data_reg_Z[119]/CLK

High Fanout Nets Report:

Report Command:report_high_fanout_nets -max_nets 10

FANOUT	NET NAME	WORST SLACK	MAX DELAY
339	clk_c	0.061	1.228
114	div_shift_number[1]	0.552	1.218
113	div_shift_number[0]	0.639	1.042
100	reg0_en	5.654	1.670
96	neg_result	3.775	1.807
92	state[1]	5.113	2.439
81	hi_result	4.107	1.674
74	reg0_exe_nx_sm0	0.938	1.411
71	state[3]	5.060	2.425
70	m0_2_03_1	0.722	1.403

Route Congestions Report:

Report Command:report_route_congestion -max_grids 10

GRID LOC	ROUTE CONGESTIONS
R48C37	0.875
R33C51	0.792
R48C38	0.792
R34C39	0.764
R37C44	0.750
R43C40	0.750
R35C38	0.736
R33C48	0.736
R35C40	0.722
R33C49	0.722

Timing Exceptions Report:

Setup Analysis Report

Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Hold Analysis Report

Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Recovery Analysis Report

Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Removal Analysis Report

Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Timing Constraints Report:

SDC Command Type	State	Detail Command