Timing Messages

Report Title	Gowin Timing Analysis Report
Design File	F:/user-bak/Users/FDELL/Desktop/IP/Integer_Multiply-Divider/ref_design/DIV/Integer_Multiply_Divider_pn/project/impl/synplify/rev_1/Integer_Multiply_Divider_pn.vm
Physical Constraints File	F:\user-bak\Users\FDELL\Desktop\IP\Integer_Multiply-Divider\ref_design\DIV\Integer_Multiply_Divider_pn\project\src\Integer_Multiply_Divider_pn.cst
Timing Constraints File	---
GOWIN version	v1.9.0Beta
Part Number	GW2A-LV55PG484C8/I7
Created Time	Tue Feb 19 17:56:17 2019
Legal Announcement	Copyright (C)2014-2019 Gowin Semiconductor Corporation. All rights reserved.

Timing Summaries

STA Tool Run Summary:

Setup Delay Model	Slow 0.95V 85C
Hold Delay Model	Fast 1.05V 0C
Numbers of Paths Analyzed	4133
Numbers of Endpoints Analyzed	9289
Numbers of Falling Endpoints	1
Numbers of Setup Violated Endpoints	0
Numbers of Hold Violated Endpoints	0

Clock Summary:

Clock Name	Type	Period	Frequency(MHz)	Rise	Fall	Source	Master	Objects
DEFAULT_CLK	Base	10.000	100.000	0.000	5.000

Max Frequency Summary:

NO.	Clock Name	Fmax	Entity
1	DEFAULT_CLK	102.707(MHz)	TOP

Total Negative Slack Summary:

Clock Name	Analysis Type	Endpoints TNS	Number of Endpoints
DEFAULT_CLK	Setup	0.000	0
DEFAULT_CLK	Hold	0.000	0

Timing Details

Path Slacks Table:

Setup Paths Table

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	0.264	Mdu/u_mdu/reg1_Z[16]/Q	Mdu/u_mdu/reg0_Z[7]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	0.000	9.501
2	0.422	Mdu/u_mdu/reg0_fast_Z[4]/Q	Mdu/u_mdu/reg0_fast_Z[31]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	0.000	9.343
3	0.505	Mdu/u_mdu/reg0_Z[21]/Q	memq_memq_0_2/DI1	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	0.000	9.260
4	0.559	Mdu/u_mdu/reg1_Z[16]/Q	Mdu/u_mdu/reg0_Z[39]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	0.000	9.206
5	0.570	Mdu/u_mdu/reg0_Z[21]/Q	Mdu/u_mdu/reg0_Z[16]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	0.000	9.195
6	0.642	Mdu/u_mdu/reg0_Z[12]/Q	Mdu/u_mdu/reg0_22_rep1_Z/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	0.000	9.123
7	0.642	Mdu/u_mdu/reg0_Z[12]/Q	Mdu/u_mdu/reg0_Z[22]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	0.000	9.123
8	0.645	Mdu/u_mdu/reg0_fast_Z[4]/Q	Mdu/u_mdu/reg0_31_rep1_Z/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	0.000	9.120
9	0.704	Mdu/u_mdu/reg1_Z[16]/Q	Mdu/u_mdu/reg0_Z[53]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	0.000	9.061
10	0.720	Mdu/u_mdu/reg0_Z[12]/Q	Mdu/u_mdu/reg0_fast_Z[22]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	0.000	9.045
11	0.747	Mdu/u_mdu/reg0_Z[21]/Q	memq_memq_0_5/DI0	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	0.000	9.018
12	0.748	Mdu/u_mdu/reg1_Z[16]/Q	Mdu/u_mdu/reg0_Z[64]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	0.000	9.017
13	0.763	Mdu/u_mdu/reg1_Z[16]/Q	Mdu/u_mdu/reg0_Z[44]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	0.000	9.002
14	0.766	Mdu/u_mdu/reg0_Z[8]/Q	memq_memq_0_0/DI1	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	0.000	9.000
15	0.766	Mdu/u_mdu/reg1_Z[16]/Q	Mdu/u_mdu/reg0_Z[60]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	0.000	8.999
16	0.792	Mdu/u_mdu/div_shift_number_Z[0]/Q	Mdu/u_mdu/reg0_27_rep1_Z/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	0.000	8.973
17	0.792	Mdu/u_mdu/div_shift_number_Z[0]/Q	Mdu/u_mdu/reg0_fast_Z[27]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	0.000	8.973
18	0.792	Mdu/u_mdu/div_shift_number_Z[0]/Q	Mdu/u_mdu/reg0_Z[27]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	0.000	8.973
19	0.817	Mdu/u_mdu/reg0_Z[21]/Q	memq_memq_0_2/DI0	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	0.000	8.948
20	0.822	Mdu/u_mdu/reg1_Z[16]/Q	Mdu/u_mdu/reg0_Z[52]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	0.000	8.943
21	0.824	Mdu/u_mdu/div_shift_number_Z[0]/Q	Mdu/u_mdu/reg0_fast_Z[13]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	0.000	8.941
22	0.824	Mdu/u_mdu/div_shift_number_Z[0]/Q	Mdu/u_mdu/reg0_Z[13]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	0.000	8.941
23	0.829	Mdu/u_mdu/div_shift_number_Z[0]/Q	Mdu/u_mdu/reg0_Z[21]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	0.000	8.936
24	0.835	Mdu/u_mdu/reg1_Z[16]/Q	Mdu/u_mdu/reg0_Z[41]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	0.000	8.930
25	0.864	Mdu/u_mdu/reg0_fast_Z[4]/Q	memq_memq_0_15/DI1	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	0.000	8.901

Hold Paths Table

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	0.202	u_la0_top/u_ao_mem_ctrl/data_reg_Z[86]/Q	u_la0_top/u_ao_mem_ctrl/mem_mem_0_43/DI0	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.000	0.000	0.451
2	0.216	cnt_Z[10]/Q	memq_memq_0_1/ADA11	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.000	0.000	0.334
3	0.233	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[12]/Q	u_la0_top/u_ao_mem_ctrl/mem_mem_0_15/ADA13	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.000	0.000	0.351
4	0.334	Mdu/u_mdu/reg1_Z[31]/Q	Mdu/u_mdu/rs1_mul_Z[31]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.000	0.000	0.345
5	0.334	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0]/Q	u_la0_top/u_ao_mem_ctrl/mem_mem_0_15/ADA1	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.000	0.000	0.452
6	0.335	u_la0_top/u_ao_mem_ctrl/data_reg_Z[87]/Q	u_la0_top/u_ao_mem_ctrl/mem_mem_0_43/DI1	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.000	0.000	0.584
7	0.335	u_la0_top/u_ao_mem_ctrl/data_reg_Z[77]/Q	u_la0_top/u_ao_mem_ctrl/mem_mem_0_38/DI1	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.000	0.000	0.584
8	0.335	u_la0_top/u_ao_mem_ctrl/data_reg_Z[76]/Q	u_la0_top/u_ao_mem_ctrl/mem_mem_0_38/DI0	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.000	0.000	0.584
9	0.338	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[4]/Q	u_la0_top/u_ao_mem_ctrl/mem_mem_0_15/ADA5	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.000	0.000	0.456
10	0.339	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[5]/Q	u_la0_top/u_ao_mem_ctrl/mem_mem_0_15/ADA6	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.000	0.000	0.457
11	0.341	cnt_Z[8]/Q	memr_memr_0_14/ADA9	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.000	0.000	0.459
12	0.344	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[6]/Q	u_la0_top/u_ao_mem_ctrl/mem_mem_0_15/ADA7	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.000	0.000	0.462
13	0.345	cnt_Z[1]/Q	memr_memr_0_14/ADA2	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.000	0.000	0.463
14	0.350	cnt_Z[8]/Q	memq_memq_0_1/ADA9	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.000	0.000	0.468
15	0.352	cnt_Z[12]/Q	memq_memq_0_1/ADA13	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.000	0.000	0.470
16	0.352	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[2]/Q	u_la0_top/u_ao_mem_ctrl/mem_mem_0_15/ADA3	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.000	0.000	0.470
17	0.353	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[9]/Q	u_la0_top/u_ao_mem_ctrl/mem_mem_0_15/ADA10	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.000	0.000	0.471
18	0.354	cnt_1_Z[3]/Q	memr_memr_0_14/ADB4	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.000	0.000	0.472
19	0.354	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[7]/Q	u_la0_top/u_ao_mem_ctrl/mem_mem_0_15/ADA8	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.000	0.000	0.472
20	0.354	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[3]/Q	u_la0_top/u_ao_mem_ctrl/mem_mem_0_10/ADA4	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.000	0.000	0.472
21	0.354	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[10]/Q	u_la0_top/u_ao_mem_ctrl/mem_mem_0_10/ADA11	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.000	0.000	0.472
22	0.355	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[3]/Q	u_la0_top/u_ao_mem_ctrl/mem_mem_0_15/ADA4	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.000	0.000	0.473
23	0.357	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[10]/Q	u_la0_top/u_ao_mem_ctrl/mem_mem_0_15/ADA11	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.000	0.000	0.475
24	0.357	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8]/Q	u_la0_top/u_ao_mem_ctrl/mem_mem_0_38/ADA9	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.000	0.000	0.475
25	0.366	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[1]/Q	u_la0_top/u_ao_mem_ctrl/mem_mem_0_43/ADA2	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.000	0.000	0.484

Recovery Paths Table

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	1.643	u_la0_top/rst_ao_Z/Q	u_la0_top/triger_level_cnt_Z[0]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	5.000	0.033	3.089
2	1.643	u_la0_top/rst_ao_Z/Q	u_la0_top/triger_level_cnt_Z[2]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	5.000	0.033	3.089
3	1.643	u_la0_top/rst_ao_Z/Q	u_la0_top/capture_window_sel[3]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	5.000	0.033	3.089
4	1.643	u_la0_top/rst_ao_Z/Q	u_la0_top/internal_reg_force_triger_syn_Z[0]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	5.000	0.033	3.089
5	1.643	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_length_Z[12]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	5.000	0.033	3.089
6	1.643	u_la0_top/rst_ao_Z/Q	u_la0_top/internal_reg_start_syn_Z[0]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	5.000	0.033	3.089
7	1.643	u_la0_top/rst_ao_Z/Q	u_la0_top/internal_reg_start_dly_Z[0]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	5.000	0.033	3.089
8	1.643	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	5.000	0.033	3.089
9	1.643	u_la0_top/rst_ao_Z/Q	u_la0_top/capture_window_sel_Z[2]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	5.000	0.033	3.089
10	1.643	u_la0_top/rst_ao_Z/Q	u_la0_top/capture_end_dly_Z/PRESET	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	5.000	0.033	3.089
11	1.643	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	5.000	0.033	3.089
12	1.643	u_la0_top/rst_ao_Z/Q	u_la0_top/capture_window_sel_Z[1]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	5.000	0.033	3.089
13	1.643	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_length_Z[4]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	5.000	0.033	3.089
14	1.643	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_length_Z[3]/PRESET	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	5.000	0.033	3.089
15	1.643	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_length_Z[9]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	5.000	0.033	3.089
16	1.643	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[12]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	5.000	0.033	3.089
17	1.643	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[2]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	5.000	0.033	3.089
18	1.643	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[1]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	5.000	0.033	3.089
19	1.643	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_length_Z[7]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	5.000	0.033	3.089
20	1.643	u_la0_top/rst_ao_Z/Q	u_la0_top/trigger_seq_start_Z/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	5.000	0.033	3.089
21	1.643	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[9]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	5.000	0.033	3.089
22	1.643	u_la0_top/rst_ao_Z/Q	u_la0_top/genblk1.u_ao_match_0/match_sep/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	5.000	0.033	3.089
23	1.643	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[3]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	5.000	0.033	3.089
24	1.643	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	5.000	0.033	3.089
25	1.643	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_length_Z[2]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	5.000	0.033	3.089

Removal Paths Table

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	6.772	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	-5.000	0.013	1.970
2	6.772	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_loop_Z/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	-5.000	0.013	1.970
3	6.772	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_length_Z[0]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	-5.000	0.013	1.970
4	6.772	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_length_Z[1]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	-5.000	0.013	1.970
5	6.772	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_length_Z[2]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	-5.000	0.013	1.970
6	6.772	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_length_Z[4]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	-5.000	0.013	1.970
7	6.772	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_length_Z[5]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	-5.000	0.013	1.970
8	6.772	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_length_Z[7]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	-5.000	0.013	1.970
9	6.772	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_length_Z[8]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	-5.000	0.013	1.970
10	6.772	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_length_Z[9]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	-5.000	0.013	1.970
11	6.772	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_length_Z[10]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	-5.000	0.013	1.970
12	6.772	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_length_Z[11]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	-5.000	0.013	1.970
13	6.772	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_length_Z[12]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	-5.000	0.013	1.970
14	6.772	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	-5.000	0.013	1.970
15	6.772	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[1]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	-5.000	0.013	1.970
16	6.772	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[2]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	-5.000	0.013	1.970
17	6.772	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[3]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	-5.000	0.013	1.970
18	6.772	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[4]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	-5.000	0.013	1.970
19	6.772	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[5]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	-5.000	0.013	1.970
20	6.772	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[6]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	-5.000	0.013	1.970
21	6.772	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[7]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	-5.000	0.013	1.970
22	6.772	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	-5.000	0.013	1.970
23	6.772	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[9]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	-5.000	0.013	1.970
24	6.772	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[10]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	-5.000	0.013	1.970
25	6.772	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[11]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	-5.000	0.013	1.970

Minimum Pulse Width Table:

Report Command:report_min_pulse_width -nworst 10 -detail

Number	Slack	Actual Width	Required Width	Type	Clock	Objects
1	3.662	4.662	1.000	Low Pulse Width	DEFAULT_CLK	cnt_1_Z[12]
2	3.662	4.662	1.000	Low Pulse Width	DEFAULT_CLK	cnt_1_Z[10]
3	3.662	4.662	1.000	Low Pulse Width	DEFAULT_CLK	cnt_1_Z[6]
4	3.662	4.662	1.000	Low Pulse Width	DEFAULT_CLK	cnt_Z[11]
5	3.662	4.662	1.000	Low Pulse Width	DEFAULT_CLK	divisor[31]
6	3.662	4.662	1.000	Low Pulse Width	DEFAULT_CLK	n_Z[30]
7	3.662	4.662	1.000	Low Pulse Width	DEFAULT_CLK	memq_memq_0_15
8	3.662	4.662	1.000	Low Pulse Width	DEFAULT_CLK	Mdu/u_mdu/reg0_fast_Z[13]
9	3.662	4.662	1.000	Low Pulse Width	DEFAULT_CLK	u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_Z
10	3.662	4.662	1.000	Low Pulse Width	DEFAULT_CLK	u_la0_top/u_ao_mem_ctrl/capture_loop_Z

Timing Report By Analysis Type:

Setup Analysis Report

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	0.264
Data Arrival Time	11.385
Data Required Time	11.648
From	Mdu/u_mdu/reg1_Z[16]
To	Mdu/u_mdu/reg0_Z[7]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.683	0.683	tINS	RR	577	IOT48[A]	clk_ibuf/O
1.883	1.201	tNET	RR	1	R30C61[0][A]	Mdu/u_mdu/reg1_Z[16]/CLK
2.115	0.232	tC2Q	RF	8	R30C61[0][A]	Mdu/u_mdu/reg1_Z[16]/Q
3.560	1.445	tNET	FF	1	R43C62[0][A]	Mdu/u_mdu/adder_sum_axb_16_lofx_cZ/I1
4.077	0.517	tINS	FF	1	R43C62[0][A]	Mdu/u_mdu/adder_sum_axb_16_lofx_cZ/F
4.976	0.899	tNET	FF	2	R44C62[0][A]	Mdu/u_mdu/adder_sum_cry_16_0/I0
5.546	0.570	tINS	FR	1	R44C62[0][A]	Mdu/u_mdu/adder_sum_cry_16_0/COUT
5.546	0.000	tNET	RR	2	R44C62[0][B]	Mdu/u_mdu/adder_sum_cry_17_0/CIN
5.581	0.035	tINS	RF	1	R44C62[0][B]	Mdu/u_mdu/adder_sum_cry_17_0/COUT
5.581	0.000	tNET	FF	2	R44C62[1][A]	Mdu/u_mdu/adder_sum_cry_18_0/CIN
5.616	0.035	tINS	FF	1	R44C62[1][A]	Mdu/u_mdu/adder_sum_cry_18_0/COUT
5.616	0.000	tNET	FF	2	R44C62[1][B]	Mdu/u_mdu/adder_sum_cry_19_0/CIN
5.651	0.035	tINS	FF	1	R44C62[1][B]	Mdu/u_mdu/adder_sum_cry_19_0/COUT
5.651	0.000	tNET	FF	2	R44C62[2][A]	Mdu/u_mdu/adder_sum_cry_20_0/CIN
5.686	0.035	tINS	FF	1	R44C62[2][A]	Mdu/u_mdu/adder_sum_cry_20_0/COUT
5.686	0.000	tNET	FF	2	R44C62[2][B]	Mdu/u_mdu/adder_sum_cry_21_0/CIN
5.722	0.035	tINS	FF	1	R44C62[2][B]	Mdu/u_mdu/adder_sum_cry_21_0/COUT
5.722	0.000	tNET	FF	2	R44C63[0][A]	Mdu/u_mdu/adder_sum_cry_22_0/CIN
5.757	0.035	tINS	FF	1	R44C63[0][A]	Mdu/u_mdu/adder_sum_cry_22_0/COUT
5.757	0.000	tNET	FF	2	R44C63[0][B]	Mdu/u_mdu/adder_sum_cry_23_0/CIN
5.792	0.035	tINS	FF	1	R44C63[0][B]	Mdu/u_mdu/adder_sum_cry_23_0/COUT
5.792	0.000	tNET	FF	2	R44C63[1][A]	Mdu/u_mdu/adder_sum_cry_24_0/CIN
5.827	0.035	tINS	FF	1	R44C63[1][A]	Mdu/u_mdu/adder_sum_cry_24_0/COUT
5.827	0.000	tNET	FF	2	R44C63[1][B]	Mdu/u_mdu/adder_sum_cry_25_0/CIN
5.862	0.035	tINS	FF	1	R44C63[1][B]	Mdu/u_mdu/adder_sum_cry_25_0/COUT
5.862	0.000	tNET	FF	2	R44C63[2][A]	Mdu/u_mdu/adder_sum_cry_26_0/CIN
5.898	0.035	tINS	FF	1	R44C63[2][A]	Mdu/u_mdu/adder_sum_cry_26_0/COUT
5.898	0.000	tNET	FF	2	R44C63[2][B]	Mdu/u_mdu/adder_sum_cry_27_0/CIN
5.933	0.035	tINS	FF	1	R44C63[2][B]	Mdu/u_mdu/adder_sum_cry_27_0/COUT
5.933	0.000	tNET	FF	2	R44C64[0][A]	Mdu/u_mdu/adder_sum_cry_28_0/CIN
5.968	0.035	tINS	FF	1	R44C64[0][A]	Mdu/u_mdu/adder_sum_cry_28_0/COUT
5.968	0.000	tNET	FF	2	R44C64[0][B]	Mdu/u_mdu/adder_sum_cry_29_0/CIN
6.003	0.035	tINS	FF	1	R44C64[0][B]	Mdu/u_mdu/adder_sum_cry_29_0/COUT
6.003	0.000	tNET	FF	2	R44C64[1][A]	Mdu/u_mdu/adder_sum_cry_30_0/CIN
6.038	0.035	tINS	FF	1	R44C64[1][A]	Mdu/u_mdu/adder_sum_cry_30_0/COUT
6.038	0.000	tNET	FF	2	R44C64[1][B]	Mdu/u_mdu/adder_sum_cry_31_0/CIN
6.074	0.035	tINS	FF	1	R44C64[1][B]	Mdu/u_mdu/adder_sum_cry_31_0/COUT
6.074	0.000	tNET	FF	2	R44C64[2][A]	Mdu/u_mdu/adder_sum_s_32_0/CIN
6.544	0.470	tINS	FF	6	R44C64[2][A]	Mdu/u_mdu/adder_sum_s_32_0/SUM
7.245	0.702	tNET	FF	1	R41C60[3][A]	Mdu/u_mdu/reg0_exe_nx_ss0_cZ/I0
7.616	0.371	tINS	FF	50	R41C60[3][A]	Mdu/u_mdu/reg0_exe_nx_ss0_cZ/F
8.664	1.047	tNET	FF	1	R46C61[0][A]	Mdu/u_mdu/reg0_exe_nx_m1_cZ[7]/I3
9.117	0.453	tINS	FF	1	R46C61[0][A]	Mdu/u_mdu/reg0_exe_nx_m1_cZ[7]/F
9.801	0.684	tNET	FF	1	R50C62[2][B]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[7]/I1
10.371	0.570	tINS	FR	1	R50C62[2][B]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[7]/F
10.372	0.001	tNET	RR	1	R50C62[3][A]	Mdu/u_mdu/reg0_exe_nx_cZ[7]/I3
10.921	0.549	tINS	RR	1	R50C62[3][A]	Mdu/u_mdu/reg0_exe_nx_cZ[7]/F
10.923	0.001	tNET	RR	1	R50C62[2][A]	Mdu/u_mdu/reg0_nx_cZ[7]/I0
11.385	0.462	tINS	RR	1	R50C62[2][A]	Mdu/u_mdu/reg0_nx_cZ[7]/F
11.385	0.000	tNET	RR	1	R50C62[2][A]	Mdu/u_mdu/reg0_Z[7]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	577	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R50C62[2][A]	Mdu/u_mdu/reg0_Z[7]/CLK
11.683	-0.200	tUnc				Mdu/u_mdu/reg0_Z[7]
11.648	-0.035	tSu		1	R50C62[2][A]	Mdu/u_mdu/reg0_Z[7]

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	8
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 4.490, 47.256%; route: 4.779, 50.302%; tC2Q: 0.232, 2.442%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path2

Path Summary:

Slack	0.422
Data Arrival Time	11.226
Data Required Time	11.648
From	Mdu/u_mdu/reg0_fast_Z[4]
To	Mdu/u_mdu/reg0_fast_Z[31]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.683	0.683	tINS	RR	577	IOT48[A]	clk_ibuf/O
1.883	1.201	tNET	RR	1	R50C55[2][A]	Mdu/u_mdu/reg0_fast_Z[4]/CLK
2.115	0.232	tC2Q	RF	7	R50C55[2][A]	Mdu/u_mdu/reg0_fast_Z[4]/Q
3.349	1.234	tNET	FF	1	R35C61[0][B]	Mdu/u_mdu/reg0_neg_axb_4_par_0_cp_1_cZ/I2
3.866	0.517	tINS	FF	1	R35C61[0][B]	Mdu/u_mdu/reg0_neg_axb_4_par_0_cp_1_cZ/F
4.821	0.955	tNET	FF	2	R30C56[1][B]	Mdu/u_mdu/reg0_neg_axb_4_par_cp_1_0/I0
5.391	0.570	tINS	FR	1	R30C56[1][B]	Mdu/u_mdu/reg0_neg_axb_4_par_cp_1_0/COUT
5.391	0.000	tNET	RR	2	R30C56[2][A]	Mdu/u_mdu/reg0_neg_axb_8_par_cp_0_0/CIN
5.426	0.035	tINS	RF	1	R30C56[2][A]	Mdu/u_mdu/reg0_neg_axb_8_par_cp_0_0/COUT
5.426	0.000	tNET	FF	2	R30C56[2][B]	Mdu/u_mdu/reg0_neg_axb_12_par_cp_0_0/CIN
5.461	0.035	tINS	FF	1	R30C56[2][B]	Mdu/u_mdu/reg0_neg_axb_12_par_cp_0_0/COUT
5.461	0.000	tNET	FF	2	R30C57[0][A]	Mdu/u_mdu/reg0_neg_axb_16_par_cp_0_0/CIN
5.496	0.035	tINS	FF	1	R30C57[0][A]	Mdu/u_mdu/reg0_neg_axb_16_par_cp_0_0/COUT
5.496	0.000	tNET	FF	2	R30C57[0][B]	Mdu/u_mdu/reg0_neg_axb_19_par_cp_0/CIN
5.532	0.035	tINS	FF	1	R30C57[0][B]	Mdu/u_mdu/reg0_neg_axb_19_par_cp_0/COUT
5.532	0.000	tNET	FF	2	R30C57[1][A]	Mdu/u_mdu/reg0_neg_axb_23_par_cp_0/CIN
5.567	0.035	tINS	FF	1	R30C57[1][A]	Mdu/u_mdu/reg0_neg_axb_23_par_cp_0/COUT
5.567	0.000	tNET	FF	2	R30C57[1][B]	Mdu/u_mdu/reg0_neg_axb_27_par_cp_0/CIN
5.602	0.035	tINS	FF	1	R30C57[1][B]	Mdu/u_mdu/reg0_neg_axb_27_par_cp_0/COUT
5.602	0.000	tNET	FF	2	R30C57[2][A]	Mdu/u_mdu/reg0_neg_axb_31_par_cp_0/CIN
5.637	0.035	tINS	FF	1	R30C57[2][A]	Mdu/u_mdu/reg0_neg_axb_31_par_cp_0/COUT
5.637	0.000	tNET	FF	2	R30C57[2][B]	Mdu/u_mdu/reg0_neg_axb_34_par_1/CIN
5.672	0.035	tINS	FF	1	R30C57[2][B]	Mdu/u_mdu/reg0_neg_axb_34_par_1/COUT
5.672	0.000	tNET	FF	2	R30C58[0][A]	Mdu/u_mdu/reg0_neg_axb_38_par_1/CIN
5.708	0.035	tINS	FF	1	R30C58[0][A]	Mdu/u_mdu/reg0_neg_axb_38_par_1/COUT
5.708	0.000	tNET	FF	2	R30C58[0][B]	Mdu/u_mdu/reg0_neg_axb_42_par_1/CIN
5.743	0.035	tINS	FF	1	R30C58[0][B]	Mdu/u_mdu/reg0_neg_axb_42_par_1/COUT
5.743	0.000	tNET	FF	2	R30C58[1][A]	Mdu/u_mdu/reg0_neg_axb_46_par_1/CIN
5.778	0.035	tINS	FF	1	R30C58[1][A]	Mdu/u_mdu/reg0_neg_axb_46_par_1/COUT
5.778	0.000	tNET	FF	2	R30C58[1][B]	Mdu/u_mdu/reg0_neg_axb_50_par_1/CIN
5.813	0.035	tINS	FF	1	R30C58[1][B]	Mdu/u_mdu/reg0_neg_axb_50_par_1/COUT
5.813	0.000	tNET	FF	2	R30C58[2][A]	Mdu/u_mdu/reg0_neg_cry_54_0/CIN
5.848	0.035	tINS	FF	1	R30C58[2][A]	Mdu/u_mdu/reg0_neg_cry_54_0/COUT
5.848	0.000	tNET	FF	2	R30C58[2][B]	Mdu/u_mdu/reg0_neg_cry_55_0/CIN
5.884	0.035	tINS	FF	1	R30C58[2][B]	Mdu/u_mdu/reg0_neg_cry_55_0/COUT
5.884	0.000	tNET	FF	2	R30C59[0][A]	Mdu/u_mdu/reg0_neg_cry_56_0/CIN
5.919	0.035	tINS	FF	1	R30C59[0][A]	Mdu/u_mdu/reg0_neg_cry_56_0/COUT
5.919	0.000	tNET	FF	2	R30C59[0][B]	Mdu/u_mdu/reg0_neg_cry_57_0/CIN
5.954	0.035	tINS	FF	1	R30C59[0][B]	Mdu/u_mdu/reg0_neg_cry_57_0/COUT
5.954	0.000	tNET	FF	2	R30C59[1][A]	Mdu/u_mdu/reg0_neg_cry_58_0/CIN
5.989	0.035	tINS	FF	1	R30C59[1][A]	Mdu/u_mdu/reg0_neg_cry_58_0/COUT
5.989	0.000	tNET	FF	2	R30C59[1][B]	Mdu/u_mdu/reg0_neg_cry_59_0/CIN
6.024	0.035	tINS	FF	1	R30C59[1][B]	Mdu/u_mdu/reg0_neg_cry_59_0/COUT
6.024	0.000	tNET	FF	2	R30C59[2][A]	Mdu/u_mdu/reg0_neg_cry_60_0/CIN
6.060	0.035	tINS	FF	1	R30C59[2][A]	Mdu/u_mdu/reg0_neg_cry_60_0/COUT
6.060	0.000	tNET	FF	2	R30C59[2][B]	Mdu/u_mdu/reg0_neg_cry_61_0/CIN
6.095	0.035	tINS	FF	1	R30C59[2][B]	Mdu/u_mdu/reg0_neg_cry_61_0/COUT
6.095	0.000	tNET	FF	2	R30C60[0][A]	Mdu/u_mdu/reg0_neg_cry_62_0/CIN
6.130	0.035	tINS	FF	1	R30C60[0][A]	Mdu/u_mdu/reg0_neg_cry_62_0/COUT
6.130	0.000	tNET	FF	2	R30C60[0][B]	Mdu/u_mdu/reg0_neg_s_63_0/CIN
6.600	0.470	tINS	FF	1	R30C60[0][B]	Mdu/u_mdu/reg0_neg_s_63_0/SUM
7.478	0.878	tNET	FF	1	R38C56[3][A]	Mdu/u_mdu/reg0_post_swap_2[31]/I2
8.048	0.570	tINS	FR	1	R38C56[3][A]	Mdu/u_mdu/reg0_post_swap_2[31]/F
8.048	0.000	tNET	RR	1	R38C56[3][A]	Mdu/u_mdu/reg0_post_swap_4[31]/I0
8.153	0.105	tINS	RR	2	R38C56[3][A]	Mdu/u_mdu/reg0_post_swap_4[31]/O
8.332	0.178	tNET	RR	1	R38C56[1][A]	Mdu/u_mdu/un11_reg0_nx_cZ[31]_cZ/I1
8.785	0.453	tINS	RF	3	R38C56[1][A]	Mdu/u_mdu/un11_reg0_nx_cZ[31]_cZ/F
10.656	1.871	tNET	FF	1	R38C57[1][A]	Mdu/u_mdu/reg0_nx_fast_cZ[31]/I3
11.226	0.570	tINS	FR	1	R38C57[1][A]	Mdu/u_mdu/reg0_nx_fast_cZ[31]/F
11.226	0.000	tNET	RR	1	R38C57[1][A]	Mdu/u_mdu/reg0_fast_Z[31]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	577	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R38C57[1][A]	Mdu/u_mdu/reg0_fast_Z[31]/CLK
11.683	-0.200	tUnc				Mdu/u_mdu/reg0_fast_Z[31]
11.648	-0.035	tSu		1	R38C57[1][A]	Mdu/u_mdu/reg0_fast_Z[31]

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 3.994, 42.752%; route: 5.116, 54.765%; tC2Q: 0.232, 2.483%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path3

Path Summary:

Slack	0.505
Data Arrival Time	11.143
Data Required Time	11.648
From	Mdu/u_mdu/reg0_Z[21]
To	memq_memq_0_2
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.683	0.683	tINS	RR	577	IOT48[A]	clk_ibuf/O
1.883	1.201	tNET	RR	1	R56C53[0][A]	Mdu/u_mdu/reg0_Z[21]/CLK
2.115	0.232	tC2Q	RF	17	R56C53[0][A]	Mdu/u_mdu/reg0_Z[21]/Q
3.503	1.388	tNET	FF	1	R39C56[1][A]	Mdu/u_mdu/reg0_neg_axb_19_par_0_cZ/I0
4.020	0.517	tINS	FF	1	R39C56[1][A]	Mdu/u_mdu/reg0_neg_axb_19_par_0_cZ/F
5.125	1.105	tNET	FF	2	R34C49[0][B]	Mdu/u_mdu/reg0_neg_axb_19_par_1/I0
5.695	0.570	tINS	FR	1	R34C49[0][B]	Mdu/u_mdu/reg0_neg_axb_19_par_1/COUT
5.695	0.000	tNET	RR	2	R34C49[1][A]	Mdu/u_mdu/reg0_neg_axb_23_par_1/CIN
5.730	0.035	tINS	RF	1	R34C49[1][A]	Mdu/u_mdu/reg0_neg_axb_23_par_1/COUT
5.730	0.000	tNET	FF	2	R34C49[1][B]	Mdu/u_mdu/reg0_neg_axb_27_par_1/CIN
5.765	0.035	tINS	FF	1	R34C49[1][B]	Mdu/u_mdu/reg0_neg_axb_27_par_1/COUT
5.765	0.000	tNET	FF	2	R34C49[2][A]	Mdu/u_mdu/reg0_neg_axb_31_par_1/CIN
5.801	0.035	tINS	FF	1	R34C49[2][A]	Mdu/u_mdu/reg0_neg_axb_31_par_1/COUT
5.801	0.000	tNET	FF	2	R34C49[2][B]	Mdu/u_mdu/reg0_neg_cry_34_0/CIN
5.836	0.035	tINS	FF	1	R34C49[2][B]	Mdu/u_mdu/reg0_neg_cry_34_0/COUT
5.836	0.000	tNET	FF	2	R34C50[0][A]	Mdu/u_mdu/reg0_neg_cry_35_0/CIN
5.871	0.035	tINS	FF	1	R34C50[0][A]	Mdu/u_mdu/reg0_neg_cry_35_0/COUT
5.871	0.000	tNET	FF	2	R34C50[0][B]	Mdu/u_mdu/reg0_neg_cry_36_0/CIN
5.906	0.035	tINS	FF	1	R34C50[0][B]	Mdu/u_mdu/reg0_neg_cry_36_0/COUT
5.906	0.000	tNET	FF	2	R34C50[1][A]	Mdu/u_mdu/reg0_neg_cry_37_0/CIN
6.376	0.470	tINS	FF	1	R34C50[1][A]	Mdu/u_mdu/reg0_neg_cry_37_0/SUM
7.060	0.684	tNET	FF	1	R39C52[3][A]	Mdu/u_mdu/reg0_post_swap_2[5]/I2
7.615	0.555	tINS	FF	1	R39C52[3][A]	Mdu/u_mdu/reg0_post_swap_2[5]/F
7.615	0.000	tNET	FF	1	R39C52[3][A]	Mdu/u_mdu/reg0_post_swap_4[5]/I0
7.718	0.103	tINS	FF	1	R39C52[3][A]	Mdu/u_mdu/reg0_post_swap_4[5]/O
8.380	0.662	tNET	FF	1	R40C55[2][B]	Mdu/u_mdu/reg0_post_swap_5[5]/I1
8.897	0.517	tINS	FF	3	R40C55[2][B]	Mdu/u_mdu/reg0_post_swap_5[5]/F
9.562	0.665	tNET	FF	1	R41C52[3][A]	Mdu/u_mdu/res0_cZ[5]/I1
10.079	0.517	tINS	FF	3	R41C52[3][A]	Mdu/u_mdu/res0_cZ[5]/F
11.143	1.064	tNET	FF	1	BSRAM_R54[14]	memq_memq_0_2/DI1

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	577	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	BSRAM_R54[14]	memq_memq_0_2/CLKA
11.683	-0.200	tUnc				memq_memq_0_2
11.648	-0.035	tSu		1	BSRAM_R54[14]	memq_memq_0_2

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 3.460, 37.368%; route: 5.568, 60.127%; tC2Q: 0.232, 2.505%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path4

Path Summary:

Slack	0.559
Data Arrival Time	11.089
Data Required Time	11.648
From	Mdu/u_mdu/reg1_Z[16]
To	Mdu/u_mdu/reg0_Z[39]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.683	0.683	tINS	RR	577	IOT48[A]	clk_ibuf/O
1.883	1.201	tNET	RR	1	R30C61[0][A]	Mdu/u_mdu/reg1_Z[16]/CLK
2.115	0.232	tC2Q	RF	8	R30C61[0][A]	Mdu/u_mdu/reg1_Z[16]/Q
3.560	1.445	tNET	FF	1	R43C62[0][A]	Mdu/u_mdu/adder_sum_axb_16_lofx_cZ/I1
4.077	0.517	tINS	FF	1	R43C62[0][A]	Mdu/u_mdu/adder_sum_axb_16_lofx_cZ/F
4.976	0.899	tNET	FF	2	R44C62[0][A]	Mdu/u_mdu/adder_sum_cry_16_0/I0
5.546	0.570	tINS	FR	1	R44C62[0][A]	Mdu/u_mdu/adder_sum_cry_16_0/COUT
5.546	0.000	tNET	RR	2	R44C62[0][B]	Mdu/u_mdu/adder_sum_cry_17_0/CIN
5.581	0.035	tINS	RF	1	R44C62[0][B]	Mdu/u_mdu/adder_sum_cry_17_0/COUT
5.581	0.000	tNET	FF	2	R44C62[1][A]	Mdu/u_mdu/adder_sum_cry_18_0/CIN
5.616	0.035	tINS	FF	1	R44C62[1][A]	Mdu/u_mdu/adder_sum_cry_18_0/COUT
5.616	0.000	tNET	FF	2	R44C62[1][B]	Mdu/u_mdu/adder_sum_cry_19_0/CIN
5.651	0.035	tINS	FF	1	R44C62[1][B]	Mdu/u_mdu/adder_sum_cry_19_0/COUT
5.651	0.000	tNET	FF	2	R44C62[2][A]	Mdu/u_mdu/adder_sum_cry_20_0/CIN
5.686	0.035	tINS	FF	1	R44C62[2][A]	Mdu/u_mdu/adder_sum_cry_20_0/COUT
5.686	0.000	tNET	FF	2	R44C62[2][B]	Mdu/u_mdu/adder_sum_cry_21_0/CIN
5.722	0.035	tINS	FF	1	R44C62[2][B]	Mdu/u_mdu/adder_sum_cry_21_0/COUT
5.722	0.000	tNET	FF	2	R44C63[0][A]	Mdu/u_mdu/adder_sum_cry_22_0/CIN
5.757	0.035	tINS	FF	1	R44C63[0][A]	Mdu/u_mdu/adder_sum_cry_22_0/COUT
5.757	0.000	tNET	FF	2	R44C63[0][B]	Mdu/u_mdu/adder_sum_cry_23_0/CIN
5.792	0.035	tINS	FF	1	R44C63[0][B]	Mdu/u_mdu/adder_sum_cry_23_0/COUT
5.792	0.000	tNET	FF	2	R44C63[1][A]	Mdu/u_mdu/adder_sum_cry_24_0/CIN
5.827	0.035	tINS	FF	1	R44C63[1][A]	Mdu/u_mdu/adder_sum_cry_24_0/COUT
5.827	0.000	tNET	FF	2	R44C63[1][B]	Mdu/u_mdu/adder_sum_cry_25_0/CIN
5.862	0.035	tINS	FF	1	R44C63[1][B]	Mdu/u_mdu/adder_sum_cry_25_0/COUT
5.862	0.000	tNET	FF	2	R44C63[2][A]	Mdu/u_mdu/adder_sum_cry_26_0/CIN
5.898	0.035	tINS	FF	1	R44C63[2][A]	Mdu/u_mdu/adder_sum_cry_26_0/COUT
5.898	0.000	tNET	FF	2	R44C63[2][B]	Mdu/u_mdu/adder_sum_cry_27_0/CIN
5.933	0.035	tINS	FF	1	R44C63[2][B]	Mdu/u_mdu/adder_sum_cry_27_0/COUT
5.933	0.000	tNET	FF	2	R44C64[0][A]	Mdu/u_mdu/adder_sum_cry_28_0/CIN
5.968	0.035	tINS	FF	1	R44C64[0][A]	Mdu/u_mdu/adder_sum_cry_28_0/COUT
5.968	0.000	tNET	FF	2	R44C64[0][B]	Mdu/u_mdu/adder_sum_cry_29_0/CIN
6.003	0.035	tINS	FF	1	R44C64[0][B]	Mdu/u_mdu/adder_sum_cry_29_0/COUT
6.003	0.000	tNET	FF	2	R44C64[1][A]	Mdu/u_mdu/adder_sum_cry_30_0/CIN
6.038	0.035	tINS	FF	1	R44C64[1][A]	Mdu/u_mdu/adder_sum_cry_30_0/COUT
6.038	0.000	tNET	FF	2	R44C64[1][B]	Mdu/u_mdu/adder_sum_cry_31_0/CIN
6.074	0.035	tINS	FF	1	R44C64[1][B]	Mdu/u_mdu/adder_sum_cry_31_0/COUT
6.074	0.000	tNET	FF	2	R44C64[2][A]	Mdu/u_mdu/adder_sum_s_32_0/CIN
6.544	0.470	tINS	FF	6	R44C64[2][A]	Mdu/u_mdu/adder_sum_s_32_0/SUM
7.245	0.702	tNET	FF	1	R41C60[3][A]	Mdu/u_mdu/reg0_exe_nx_ss0_cZ/I0
7.616	0.371	tINS	FF	50	R41C60[3][A]	Mdu/u_mdu/reg0_exe_nx_ss0_cZ/F
8.595	0.978	tNET	FF	1	R46C60[3][A]	Mdu/u_mdu/reg0_exe_nx_m0_cZ[39]/I2
9.112	0.517	tINS	FF	1	R46C60[3][A]	Mdu/u_mdu/reg0_exe_nx_m0_cZ[39]/F
9.112	0.000	tNET	FF	1	R46C60[3][A]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[39]/I0
9.215	0.103	tINS	FF	1	R46C60[3][A]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[39]/O
10.540	1.325	tNET	FF	1	R37C57[0][B]	Mdu/u_mdu/reg0_nx_cZ[39]/I0
11.089	0.549	tINS	FR	1	R37C57[0][B]	Mdu/u_mdu/reg0_nx_cZ[39]/F
11.089	0.000	tNET	RR	1	R37C57[0][B]	Mdu/u_mdu/reg0_Z[39]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	577	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R37C57[0][B]	Mdu/u_mdu/reg0_Z[39]/CLK
11.683	-0.200	tUnc				Mdu/u_mdu/reg0_Z[39]
11.648	-0.035	tSu		1	R37C57[0][B]	Mdu/u_mdu/reg0_Z[39]

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 3.625, 39.378%; route: 5.349, 58.101%; tC2Q: 0.232, 2.520%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path5

Path Summary:

Slack	0.570
Data Arrival Time	11.078
Data Required Time	11.648
From	Mdu/u_mdu/reg0_Z[21]
To	Mdu/u_mdu/reg0_Z[16]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.683	0.683	tINS	RR	577	IOT48[A]	clk_ibuf/O
1.883	1.201	tNET	RR	1	R56C53[0][A]	Mdu/u_mdu/reg0_Z[21]/CLK
2.115	0.232	tC2Q	RF	17	R56C53[0][A]	Mdu/u_mdu/reg0_Z[21]/Q
3.503	1.388	tNET	FF	1	R39C56[1][A]	Mdu/u_mdu/reg0_neg_axb_19_par_0_cZ/I0
4.020	0.517	tINS	FF	1	R39C56[1][A]	Mdu/u_mdu/reg0_neg_axb_19_par_0_cZ/F
5.125	1.105	tNET	FF	2	R34C49[0][B]	Mdu/u_mdu/reg0_neg_axb_19_par_1/I0
5.695	0.570	tINS	FR	1	R34C49[0][B]	Mdu/u_mdu/reg0_neg_axb_19_par_1/COUT
5.695	0.000	tNET	RR	2	R34C49[1][A]	Mdu/u_mdu/reg0_neg_axb_23_par_1/CIN
5.730	0.035	tINS	RF	1	R34C49[1][A]	Mdu/u_mdu/reg0_neg_axb_23_par_1/COUT
5.730	0.000	tNET	FF	2	R34C49[1][B]	Mdu/u_mdu/reg0_neg_axb_27_par_1/CIN
5.765	0.035	tINS	FF	1	R34C49[1][B]	Mdu/u_mdu/reg0_neg_axb_27_par_1/COUT
5.765	0.000	tNET	FF	2	R34C49[2][A]	Mdu/u_mdu/reg0_neg_axb_31_par_1/CIN
5.801	0.035	tINS	FF	1	R34C49[2][A]	Mdu/u_mdu/reg0_neg_axb_31_par_1/COUT
5.801	0.000	tNET	FF	2	R34C49[2][B]	Mdu/u_mdu/reg0_neg_cry_34_0/CIN
5.836	0.035	tINS	FF	1	R34C49[2][B]	Mdu/u_mdu/reg0_neg_cry_34_0/COUT
5.836	0.000	tNET	FF	2	R34C50[0][A]	Mdu/u_mdu/reg0_neg_cry_35_0/CIN
5.871	0.035	tINS	FF	1	R34C50[0][A]	Mdu/u_mdu/reg0_neg_cry_35_0/COUT
5.871	0.000	tNET	FF	2	R34C50[0][B]	Mdu/u_mdu/reg0_neg_cry_36_0/CIN
5.906	0.035	tINS	FF	1	R34C50[0][B]	Mdu/u_mdu/reg0_neg_cry_36_0/COUT
5.906	0.000	tNET	FF	2	R34C50[1][A]	Mdu/u_mdu/reg0_neg_cry_37_0/CIN
5.941	0.035	tINS	FF	1	R34C50[1][A]	Mdu/u_mdu/reg0_neg_cry_37_0/COUT
5.941	0.000	tNET	FF	2	R34C50[1][B]	Mdu/u_mdu/reg0_neg_cry_38_0/CIN
5.977	0.035	tINS	FF	1	R34C50[1][B]	Mdu/u_mdu/reg0_neg_cry_38_0/COUT
5.977	0.000	tNET	FF	2	R34C50[2][A]	Mdu/u_mdu/reg0_neg_cry_39_0/CIN
6.012	0.035	tINS	FF	1	R34C50[2][A]	Mdu/u_mdu/reg0_neg_cry_39_0/COUT
6.012	0.000	tNET	FF	2	R34C50[2][B]	Mdu/u_mdu/reg0_neg_cry_40_0/CIN
6.047	0.035	tINS	FF	1	R34C50[2][B]	Mdu/u_mdu/reg0_neg_cry_40_0/COUT
6.047	0.000	tNET	FF	2	R34C51[0][A]	Mdu/u_mdu/reg0_neg_cry_41_0/CIN
6.082	0.035	tINS	FF	1	R34C51[0][A]	Mdu/u_mdu/reg0_neg_cry_41_0/COUT
6.082	0.000	tNET	FF	2	R34C51[0][B]	Mdu/u_mdu/reg0_neg_cry_42_0/CIN
6.117	0.035	tINS	FF	1	R34C51[0][B]	Mdu/u_mdu/reg0_neg_cry_42_0/COUT
6.117	0.000	tNET	FF	2	R34C51[1][A]	Mdu/u_mdu/reg0_neg_cry_43_0/CIN
6.153	0.035	tINS	FF	1	R34C51[1][A]	Mdu/u_mdu/reg0_neg_cry_43_0/COUT
6.153	0.000	tNET	FF	2	R34C51[1][B]	Mdu/u_mdu/reg0_neg_cry_44_0/CIN
6.188	0.035	tINS	FF	1	R34C51[1][B]	Mdu/u_mdu/reg0_neg_cry_44_0/COUT
6.188	0.000	tNET	FF	2	R34C51[2][A]	Mdu/u_mdu/reg0_neg_cry_45_0/CIN
6.223	0.035	tINS	FF	1	R34C51[2][A]	Mdu/u_mdu/reg0_neg_cry_45_0/COUT
6.223	0.000	tNET	FF	2	R34C51[2][B]	Mdu/u_mdu/reg0_neg_cry_46_0/CIN
6.258	0.035	tINS	FF	1	R34C51[2][B]	Mdu/u_mdu/reg0_neg_cry_46_0/COUT
6.258	0.000	tNET	FF	2	R34C52[0][A]	Mdu/u_mdu/reg0_neg_cry_47_0/CIN
6.293	0.035	tINS	FF	1	R34C52[0][A]	Mdu/u_mdu/reg0_neg_cry_47_0/COUT
6.293	0.000	tNET	FF	2	R34C52[0][B]	Mdu/u_mdu/reg0_neg_cry_48_0/CIN
6.763	0.470	tINS	FF	1	R34C52[0][B]	Mdu/u_mdu/reg0_neg_cry_48_0/SUM
7.281	0.518	tNET	FF	1	R38C53[3][A]	Mdu/u_mdu/reg0_post_swap_2[16]/I2
7.652	0.371	tINS	FF	1	R38C53[3][A]	Mdu/u_mdu/reg0_post_swap_2[16]/F
7.652	0.000	tNET	FF	1	R38C53[3][A]	Mdu/u_mdu/reg0_post_swap_4[16]/I0
7.755	0.103	tINS	FF	1	R38C53[3][A]	Mdu/u_mdu/reg0_post_swap_4[16]/O
7.932	0.176	tNET	FF	1	R39C53[3][B]	Mdu/u_mdu/reg0_post_swap_5[16]/I1
8.487	0.555	tINS	FF	2	R39C53[3][B]	Mdu/u_mdu/reg0_post_swap_5[16]/F
9.794	1.307	tNET	FF	1	R53C55[3][A]	Mdu/u_mdu/reg0_nx_1_cZ[16]/I0
10.364	0.570	tINS	FR	1	R53C55[3][A]	Mdu/u_mdu/reg0_nx_1_cZ[16]/F
10.508	0.144	tNET	RR	1	R53C55[2][B]	Mdu/u_mdu/reg0_nx_cZ[16]/I1
11.078	0.570	tINS	RR	1	R53C55[2][B]	Mdu/u_mdu/reg0_nx_cZ[16]/F
11.078	0.000	tNET	RR	1	R53C55[2][B]	Mdu/u_mdu/reg0_Z[16]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	577	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R53C55[2][B]	Mdu/u_mdu/reg0_Z[16]/CLK
11.683	-0.200	tUnc				Mdu/u_mdu/reg0_Z[16]
11.648	-0.035	tSu		1	R53C55[2][B]	Mdu/u_mdu/reg0_Z[16]

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	8
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 4.324, 47.032%; route: 4.638, 50.445%; tC2Q: 0.232, 2.523%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path6

Path Summary:

Slack	0.642
Data Arrival Time	11.006
Data Required Time	11.648
From	Mdu/u_mdu/reg0_Z[12]
To	Mdu/u_mdu/reg0_22_rep1_Z
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.683	0.683	tINS	RR	577	IOT48[A]	clk_ibuf/O
1.883	1.201	tNET	RR	1	R40C54[2][B]	Mdu/u_mdu/reg0_Z[12]/CLK
2.115	0.232	tC2Q	RF	11	R40C54[2][B]	Mdu/u_mdu/reg0_Z[12]/Q
3.478	1.363	tNET	FF	1	R52C51[0][A]	Mdu/u_mdu/m14_0_03_1_cZ/I3
3.940	0.462	tINS	FR	1	R52C51[0][A]	Mdu/u_mdu/m14_0_03_1_cZ/F
3.941	0.001	tNET	RR	1	R52C51[1][A]	Mdu/u_mdu/m14_0_03_cZ/I1
4.312	0.371	tINS	RF	4	R52C51[1][A]	Mdu/u_mdu/m14_0_03_cZ/F
5.650	1.337	tNET	FF	1	R47C56[2][A]	Mdu/u_mdu/m22_2_03_0_0_cZ/I3
6.167	0.517	tINS	FF	2	R47C56[2][A]	Mdu/u_mdu/m22_2_03_0_0_cZ/F
6.978	0.811	tNET	FF	1	R48C59[3][A]	Mdu/u_mdu/m22_4_01_cZ/I2
7.349	0.371	tINS	FF	1	R48C59[3][A]	Mdu/u_mdu/m22_4_01_cZ/F
8.138	0.789	tNET	FF	1	R52C53[1][B]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[22]/I2
8.600	0.462	tINS	FR	1	R52C53[1][B]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[22]/F
8.601	0.001	tNET	RR	1	R52C53[3][B]	Mdu/u_mdu/reg0_exe_nx_cZ[22]/I3
9.156	0.555	tINS	RF	3	R52C53[3][B]	Mdu/u_mdu/reg0_exe_nx_cZ[22]/F
10.544	1.388	tNET	FF	1	R40C58[2][B]	Mdu/u_mdu/reg0_nx_rep1_cZ[22]/I0
11.006	0.462	tINS	FR	1	R40C58[2][B]	Mdu/u_mdu/reg0_nx_rep1_cZ[22]/F
11.006	0.000	tNET	RR	1	R40C58[2][B]	Mdu/u_mdu/reg0_22_rep1_Z/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	577	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R40C58[2][B]	Mdu/u_mdu/reg0_22_rep1_Z/CLK
11.683	-0.200	tUnc				Mdu/u_mdu/reg0_22_rep1_Z
11.648	-0.035	tSu		1	R40C58[2][B]	Mdu/u_mdu/reg0_22_rep1_Z

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 3.200, 35.076%; route: 5.691, 62.381%; tC2Q: 0.232, 2.543%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path7

Path Summary:

Slack	0.642
Data Arrival Time	11.006
Data Required Time	11.648
From	Mdu/u_mdu/reg0_Z[12]
To	Mdu/u_mdu/reg0_Z[22]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.683	0.683	tINS	RR	577	IOT48[A]	clk_ibuf/O
1.883	1.201	tNET	RR	1	R40C54[2][B]	Mdu/u_mdu/reg0_Z[12]/CLK
2.115	0.232	tC2Q	RF	11	R40C54[2][B]	Mdu/u_mdu/reg0_Z[12]/Q
3.478	1.363	tNET	FF	1	R52C51[0][A]	Mdu/u_mdu/m14_0_03_1_cZ/I3
3.940	0.462	tINS	FR	1	R52C51[0][A]	Mdu/u_mdu/m14_0_03_1_cZ/F
3.941	0.001	tNET	RR	1	R52C51[1][A]	Mdu/u_mdu/m14_0_03_cZ/I1
4.312	0.371	tINS	RF	4	R52C51[1][A]	Mdu/u_mdu/m14_0_03_cZ/F
5.650	1.337	tNET	FF	1	R47C56[2][A]	Mdu/u_mdu/m22_2_03_0_0_cZ/I3
6.167	0.517	tINS	FF	2	R47C56[2][A]	Mdu/u_mdu/m22_2_03_0_0_cZ/F
6.978	0.811	tNET	FF	1	R48C59[3][A]	Mdu/u_mdu/m22_4_01_cZ/I2
7.349	0.371	tINS	FF	1	R48C59[3][A]	Mdu/u_mdu/m22_4_01_cZ/F
8.138	0.789	tNET	FF	1	R52C53[1][B]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[22]/I2
8.600	0.462	tINS	FR	1	R52C53[1][B]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[22]/F
8.601	0.001	tNET	RR	1	R52C53[3][B]	Mdu/u_mdu/reg0_exe_nx_cZ[22]/I3
9.156	0.555	tINS	RF	3	R52C53[3][B]	Mdu/u_mdu/reg0_exe_nx_cZ[22]/F
10.544	1.388	tNET	FF	1	R40C58[2][A]	Mdu/u_mdu/reg0_nx_cZ[22]/I0
11.006	0.462	tINS	FR	1	R40C58[2][A]	Mdu/u_mdu/reg0_nx_cZ[22]/F
11.006	0.000	tNET	RR	1	R40C58[2][A]	Mdu/u_mdu/reg0_Z[22]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	577	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R40C58[2][A]	Mdu/u_mdu/reg0_Z[22]/CLK
11.683	-0.200	tUnc				Mdu/u_mdu/reg0_Z[22]
11.648	-0.035	tSu		1	R40C58[2][A]	Mdu/u_mdu/reg0_Z[22]

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 3.200, 35.076%; route: 5.691, 62.381%; tC2Q: 0.232, 2.543%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path8

Path Summary:

Slack	0.645
Data Arrival Time	11.003
Data Required Time	11.648
From	Mdu/u_mdu/reg0_fast_Z[4]
To	Mdu/u_mdu/reg0_31_rep1_Z
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.683	0.683	tINS	RR	577	IOT48[A]	clk_ibuf/O
1.883	1.201	tNET	RR	1	R50C55[2][A]	Mdu/u_mdu/reg0_fast_Z[4]/CLK
2.115	0.232	tC2Q	RF	7	R50C55[2][A]	Mdu/u_mdu/reg0_fast_Z[4]/Q
3.349	1.234	tNET	FF	1	R35C61[0][B]	Mdu/u_mdu/reg0_neg_axb_4_par_0_cp_1_cZ/I2
3.866	0.517	tINS	FF	1	R35C61[0][B]	Mdu/u_mdu/reg0_neg_axb_4_par_0_cp_1_cZ/F
4.821	0.955	tNET	FF	2	R30C56[1][B]	Mdu/u_mdu/reg0_neg_axb_4_par_cp_1_0/I0
5.391	0.570	tINS	FR	1	R30C56[1][B]	Mdu/u_mdu/reg0_neg_axb_4_par_cp_1_0/COUT
5.391	0.000	tNET	RR	2	R30C56[2][A]	Mdu/u_mdu/reg0_neg_axb_8_par_cp_0_0/CIN
5.426	0.035	tINS	RF	1	R30C56[2][A]	Mdu/u_mdu/reg0_neg_axb_8_par_cp_0_0/COUT
5.426	0.000	tNET	FF	2	R30C56[2][B]	Mdu/u_mdu/reg0_neg_axb_12_par_cp_0_0/CIN
5.461	0.035	tINS	FF	1	R30C56[2][B]	Mdu/u_mdu/reg0_neg_axb_12_par_cp_0_0/COUT
5.461	0.000	tNET	FF	2	R30C57[0][A]	Mdu/u_mdu/reg0_neg_axb_16_par_cp_0_0/CIN
5.496	0.035	tINS	FF	1	R30C57[0][A]	Mdu/u_mdu/reg0_neg_axb_16_par_cp_0_0/COUT
5.496	0.000	tNET	FF	2	R30C57[0][B]	Mdu/u_mdu/reg0_neg_axb_19_par_cp_0/CIN
5.532	0.035	tINS	FF	1	R30C57[0][B]	Mdu/u_mdu/reg0_neg_axb_19_par_cp_0/COUT
5.532	0.000	tNET	FF	2	R30C57[1][A]	Mdu/u_mdu/reg0_neg_axb_23_par_cp_0/CIN
5.567	0.035	tINS	FF	1	R30C57[1][A]	Mdu/u_mdu/reg0_neg_axb_23_par_cp_0/COUT
5.567	0.000	tNET	FF	2	R30C57[1][B]	Mdu/u_mdu/reg0_neg_axb_27_par_cp_0/CIN
5.602	0.035	tINS	FF	1	R30C57[1][B]	Mdu/u_mdu/reg0_neg_axb_27_par_cp_0/COUT
5.602	0.000	tNET	FF	2	R30C57[2][A]	Mdu/u_mdu/reg0_neg_axb_31_par_cp_0/CIN
5.637	0.035	tINS	FF	1	R30C57[2][A]	Mdu/u_mdu/reg0_neg_axb_31_par_cp_0/COUT
5.637	0.000	tNET	FF	2	R30C57[2][B]	Mdu/u_mdu/reg0_neg_axb_34_par_1/CIN
5.672	0.035	tINS	FF	1	R30C57[2][B]	Mdu/u_mdu/reg0_neg_axb_34_par_1/COUT
5.672	0.000	tNET	FF	2	R30C58[0][A]	Mdu/u_mdu/reg0_neg_axb_38_par_1/CIN
5.708	0.035	tINS	FF	1	R30C58[0][A]	Mdu/u_mdu/reg0_neg_axb_38_par_1/COUT
5.708	0.000	tNET	FF	2	R30C58[0][B]	Mdu/u_mdu/reg0_neg_axb_42_par_1/CIN
5.743	0.035	tINS	FF	1	R30C58[0][B]	Mdu/u_mdu/reg0_neg_axb_42_par_1/COUT
5.743	0.000	tNET	FF	2	R30C58[1][A]	Mdu/u_mdu/reg0_neg_axb_46_par_1/CIN
5.778	0.035	tINS	FF	1	R30C58[1][A]	Mdu/u_mdu/reg0_neg_axb_46_par_1/COUT
5.778	0.000	tNET	FF	2	R30C58[1][B]	Mdu/u_mdu/reg0_neg_axb_50_par_1/CIN
5.813	0.035	tINS	FF	1	R30C58[1][B]	Mdu/u_mdu/reg0_neg_axb_50_par_1/COUT
5.813	0.000	tNET	FF	2	R30C58[2][A]	Mdu/u_mdu/reg0_neg_cry_54_0/CIN
5.848	0.035	tINS	FF	1	R30C58[2][A]	Mdu/u_mdu/reg0_neg_cry_54_0/COUT
5.848	0.000	tNET	FF	2	R30C58[2][B]	Mdu/u_mdu/reg0_neg_cry_55_0/CIN
5.884	0.035	tINS	FF	1	R30C58[2][B]	Mdu/u_mdu/reg0_neg_cry_55_0/COUT
5.884	0.000	tNET	FF	2	R30C59[0][A]	Mdu/u_mdu/reg0_neg_cry_56_0/CIN
5.919	0.035	tINS	FF	1	R30C59[0][A]	Mdu/u_mdu/reg0_neg_cry_56_0/COUT
5.919	0.000	tNET	FF	2	R30C59[0][B]	Mdu/u_mdu/reg0_neg_cry_57_0/CIN
5.954	0.035	tINS	FF	1	R30C59[0][B]	Mdu/u_mdu/reg0_neg_cry_57_0/COUT
5.954	0.000	tNET	FF	2	R30C59[1][A]	Mdu/u_mdu/reg0_neg_cry_58_0/CIN
5.989	0.035	tINS	FF	1	R30C59[1][A]	Mdu/u_mdu/reg0_neg_cry_58_0/COUT
5.989	0.000	tNET	FF	2	R30C59[1][B]	Mdu/u_mdu/reg0_neg_cry_59_0/CIN
6.024	0.035	tINS	FF	1	R30C59[1][B]	Mdu/u_mdu/reg0_neg_cry_59_0/COUT
6.024	0.000	tNET	FF	2	R30C59[2][A]	Mdu/u_mdu/reg0_neg_cry_60_0/CIN
6.060	0.035	tINS	FF	1	R30C59[2][A]	Mdu/u_mdu/reg0_neg_cry_60_0/COUT
6.060	0.000	tNET	FF	2	R30C59[2][B]	Mdu/u_mdu/reg0_neg_cry_61_0/CIN
6.095	0.035	tINS	FF	1	R30C59[2][B]	Mdu/u_mdu/reg0_neg_cry_61_0/COUT
6.095	0.000	tNET	FF	2	R30C60[0][A]	Mdu/u_mdu/reg0_neg_cry_62_0/CIN
6.130	0.035	tINS	FF	1	R30C60[0][A]	Mdu/u_mdu/reg0_neg_cry_62_0/COUT
6.130	0.000	tNET	FF	2	R30C60[0][B]	Mdu/u_mdu/reg0_neg_s_63_0/CIN
6.600	0.470	tINS	FF	1	R30C60[0][B]	Mdu/u_mdu/reg0_neg_s_63_0/SUM
7.478	0.878	tNET	FF	1	R38C56[3][A]	Mdu/u_mdu/reg0_post_swap_2[31]/I2
8.048	0.570	tINS	FR	1	R38C56[3][A]	Mdu/u_mdu/reg0_post_swap_2[31]/F
8.048	0.000	tNET	RR	1	R38C56[3][A]	Mdu/u_mdu/reg0_post_swap_4[31]/I0
8.153	0.105	tINS	RR	2	R38C56[3][A]	Mdu/u_mdu/reg0_post_swap_4[31]/O
8.332	0.178	tNET	RR	1	R38C56[1][A]	Mdu/u_mdu/un11_reg0_nx_cZ[31]_cZ/I1
8.785	0.453	tINS	RF	3	R38C56[1][A]	Mdu/u_mdu/un11_reg0_nx_cZ[31]_cZ/F
10.433	1.649	tNET	FF	1	R38C57[0][B]	Mdu/u_mdu/reg0_nx_rep1_cZ[31]/I3
11.003	0.570	tINS	FR	1	R38C57[0][B]	Mdu/u_mdu/reg0_nx_rep1_cZ[31]/F
11.003	0.000	tNET	RR	1	R38C57[0][B]	Mdu/u_mdu/reg0_31_rep1_Z/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	577	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R38C57[0][B]	Mdu/u_mdu/reg0_31_rep1_Z/CLK
11.683	-0.200	tUnc				Mdu/u_mdu/reg0_31_rep1_Z
11.648	-0.035	tSu		1	R38C57[0][B]	Mdu/u_mdu/reg0_31_rep1_Z

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 3.994, 43.794%; route: 4.894, 53.662%; tC2Q: 0.232, 2.544%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path9

Path Summary:

Slack	0.704
Data Arrival Time	10.944
Data Required Time	11.648
From	Mdu/u_mdu/reg1_Z[16]
To	Mdu/u_mdu/reg0_Z[53]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.683	0.683	tINS	RR	577	IOT48[A]	clk_ibuf/O
1.883	1.201	tNET	RR	1	R30C61[0][A]	Mdu/u_mdu/reg1_Z[16]/CLK
2.115	0.232	tC2Q	RF	8	R30C61[0][A]	Mdu/u_mdu/reg1_Z[16]/Q
3.560	1.445	tNET	FF	1	R43C62[0][A]	Mdu/u_mdu/adder_sum_axb_16_lofx_cZ/I1
4.077	0.517	tINS	FF	1	R43C62[0][A]	Mdu/u_mdu/adder_sum_axb_16_lofx_cZ/F
4.976	0.899	tNET	FF	2	R44C62[0][A]	Mdu/u_mdu/adder_sum_cry_16_0/I0
5.546	0.570	tINS	FR	1	R44C62[0][A]	Mdu/u_mdu/adder_sum_cry_16_0/COUT
5.546	0.000	tNET	RR	2	R44C62[0][B]	Mdu/u_mdu/adder_sum_cry_17_0/CIN
5.581	0.035	tINS	RF	1	R44C62[0][B]	Mdu/u_mdu/adder_sum_cry_17_0/COUT
5.581	0.000	tNET	FF	2	R44C62[1][A]	Mdu/u_mdu/adder_sum_cry_18_0/CIN
5.616	0.035	tINS	FF	1	R44C62[1][A]	Mdu/u_mdu/adder_sum_cry_18_0/COUT
5.616	0.000	tNET	FF	2	R44C62[1][B]	Mdu/u_mdu/adder_sum_cry_19_0/CIN
5.651	0.035	tINS	FF	1	R44C62[1][B]	Mdu/u_mdu/adder_sum_cry_19_0/COUT
5.651	0.000	tNET	FF	2	R44C62[2][A]	Mdu/u_mdu/adder_sum_cry_20_0/CIN
5.686	0.035	tINS	FF	1	R44C62[2][A]	Mdu/u_mdu/adder_sum_cry_20_0/COUT
5.686	0.000	tNET	FF	2	R44C62[2][B]	Mdu/u_mdu/adder_sum_cry_21_0/CIN
5.722	0.035	tINS	FF	1	R44C62[2][B]	Mdu/u_mdu/adder_sum_cry_21_0/COUT
5.722	0.000	tNET	FF	2	R44C63[0][A]	Mdu/u_mdu/adder_sum_cry_22_0/CIN
5.757	0.035	tINS	FF	1	R44C63[0][A]	Mdu/u_mdu/adder_sum_cry_22_0/COUT
5.757	0.000	tNET	FF	2	R44C63[0][B]	Mdu/u_mdu/adder_sum_cry_23_0/CIN
5.792	0.035	tINS	FF	1	R44C63[0][B]	Mdu/u_mdu/adder_sum_cry_23_0/COUT
5.792	0.000	tNET	FF	2	R44C63[1][A]	Mdu/u_mdu/adder_sum_cry_24_0/CIN
5.827	0.035	tINS	FF	1	R44C63[1][A]	Mdu/u_mdu/adder_sum_cry_24_0/COUT
5.827	0.000	tNET	FF	2	R44C63[1][B]	Mdu/u_mdu/adder_sum_cry_25_0/CIN
5.862	0.035	tINS	FF	1	R44C63[1][B]	Mdu/u_mdu/adder_sum_cry_25_0/COUT
5.862	0.000	tNET	FF	2	R44C63[2][A]	Mdu/u_mdu/adder_sum_cry_26_0/CIN
5.898	0.035	tINS	FF	1	R44C63[2][A]	Mdu/u_mdu/adder_sum_cry_26_0/COUT
5.898	0.000	tNET	FF	2	R44C63[2][B]	Mdu/u_mdu/adder_sum_cry_27_0/CIN
5.933	0.035	tINS	FF	1	R44C63[2][B]	Mdu/u_mdu/adder_sum_cry_27_0/COUT
5.933	0.000	tNET	FF	2	R44C64[0][A]	Mdu/u_mdu/adder_sum_cry_28_0/CIN
5.968	0.035	tINS	FF	1	R44C64[0][A]	Mdu/u_mdu/adder_sum_cry_28_0/COUT
5.968	0.000	tNET	FF	2	R44C64[0][B]	Mdu/u_mdu/adder_sum_cry_29_0/CIN
6.003	0.035	tINS	FF	1	R44C64[0][B]	Mdu/u_mdu/adder_sum_cry_29_0/COUT
6.003	0.000	tNET	FF	2	R44C64[1][A]	Mdu/u_mdu/adder_sum_cry_30_0/CIN
6.038	0.035	tINS	FF	1	R44C64[1][A]	Mdu/u_mdu/adder_sum_cry_30_0/COUT
6.038	0.000	tNET	FF	2	R44C64[1][B]	Mdu/u_mdu/adder_sum_cry_31_0/CIN
6.074	0.035	tINS	FF	1	R44C64[1][B]	Mdu/u_mdu/adder_sum_cry_31_0/COUT
6.074	0.000	tNET	FF	2	R44C64[2][A]	Mdu/u_mdu/adder_sum_s_32_0/CIN
6.544	0.470	tINS	FF	6	R44C64[2][A]	Mdu/u_mdu/adder_sum_s_32_0/SUM
7.245	0.702	tNET	FF	1	R41C60[3][A]	Mdu/u_mdu/reg0_exe_nx_ss0_cZ/I0
7.616	0.371	tINS	FF	50	R41C60[3][A]	Mdu/u_mdu/reg0_exe_nx_ss0_cZ/F
8.579	0.962	tNET	FF	1	R43C57[1][A]	Mdu/u_mdu/reg0_exe_nx_m0_cZ[53]/I2
9.096	0.517	tINS	FF	1	R43C57[1][A]	Mdu/u_mdu/reg0_exe_nx_m0_cZ[53]/F
9.096	0.000	tNET	FF	1	R43C57[1][A]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[53]/I0
9.199	0.103	tINS	FF	1	R43C57[1][A]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[53]/O
10.374	1.175	tNET	FF	1	R56C55[0][A]	Mdu/u_mdu/reg0_nx_0[53]/I2
10.944	0.570	tINS	FR	1	R56C55[0][A]	Mdu/u_mdu/reg0_nx_0[53]/F
10.944	0.000	tNET	RR	1	R56C55[0][A]	Mdu/u_mdu/reg0_Z[53]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	577	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R56C55[0][A]	Mdu/u_mdu/reg0_Z[53]/CLK
11.683	-0.200	tUnc				Mdu/u_mdu/reg0_Z[53]
11.648	-0.035	tSu		1	R56C55[0][A]	Mdu/u_mdu/reg0_Z[53]

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 3.646, 40.238%; route: 5.183, 57.201%; tC2Q: 0.232, 2.560%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path10

Path Summary:

Slack	0.720
Data Arrival Time	10.928
Data Required Time	11.648
From	Mdu/u_mdu/reg0_Z[12]
To	Mdu/u_mdu/reg0_fast_Z[22]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.683	0.683	tINS	RR	577	IOT48[A]	clk_ibuf/O
1.883	1.201	tNET	RR	1	R40C54[2][B]	Mdu/u_mdu/reg0_Z[12]/CLK
2.115	0.232	tC2Q	RF	11	R40C54[2][B]	Mdu/u_mdu/reg0_Z[12]/Q
3.478	1.363	tNET	FF	1	R52C51[0][A]	Mdu/u_mdu/m14_0_03_1_cZ/I3
3.940	0.462	tINS	FR	1	R52C51[0][A]	Mdu/u_mdu/m14_0_03_1_cZ/F
3.941	0.001	tNET	RR	1	R52C51[1][A]	Mdu/u_mdu/m14_0_03_cZ/I1
4.312	0.371	tINS	RF	4	R52C51[1][A]	Mdu/u_mdu/m14_0_03_cZ/F
5.650	1.337	tNET	FF	1	R47C56[2][A]	Mdu/u_mdu/m22_2_03_0_0_cZ/I3
6.167	0.517	tINS	FF	2	R47C56[2][A]	Mdu/u_mdu/m22_2_03_0_0_cZ/F
6.978	0.811	tNET	FF	1	R48C59[3][A]	Mdu/u_mdu/m22_4_01_cZ/I2
7.349	0.371	tINS	FF	1	R48C59[3][A]	Mdu/u_mdu/m22_4_01_cZ/F
8.138	0.789	tNET	FF	1	R52C53[1][B]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[22]/I2
8.600	0.462	tINS	FR	1	R52C53[1][B]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[22]/F
8.601	0.001	tNET	RR	1	R52C53[3][B]	Mdu/u_mdu/reg0_exe_nx_cZ[22]/I3
9.156	0.555	tINS	RF	3	R52C53[3][B]	Mdu/u_mdu/reg0_exe_nx_cZ[22]/F
10.358	1.202	tNET	FF	1	R39C57[1][A]	Mdu/u_mdu/reg0_nx_fast_cZ[22]/I0
10.928	0.570	tINS	FR	1	R39C57[1][A]	Mdu/u_mdu/reg0_nx_fast_cZ[22]/F
10.928	0.000	tNET	RR	1	R39C57[1][A]	Mdu/u_mdu/reg0_fast_Z[22]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	577	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R39C57[1][A]	Mdu/u_mdu/reg0_fast_Z[22]/CLK
11.683	-0.200	tUnc				Mdu/u_mdu/reg0_fast_Z[22]
11.648	-0.035	tSu		1	R39C57[1][A]	Mdu/u_mdu/reg0_fast_Z[22]

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 3.308, 36.572%; route: 5.505, 60.863%; tC2Q: 0.232, 2.565%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path11

Path Summary:

Slack	0.747
Data Arrival Time	10.901
Data Required Time	11.648
From	Mdu/u_mdu/reg0_Z[21]
To	memq_memq_0_5
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.683	0.683	tINS	RR	577	IOT48[A]	clk_ibuf/O
1.883	1.201	tNET	RR	1	R56C53[0][A]	Mdu/u_mdu/reg0_Z[21]/CLK
2.115	0.232	tC2Q	RF	17	R56C53[0][A]	Mdu/u_mdu/reg0_Z[21]/Q
3.503	1.388	tNET	FF	1	R39C56[1][A]	Mdu/u_mdu/reg0_neg_axb_19_par_0_cZ/I0
4.020	0.517	tINS	FF	1	R39C56[1][A]	Mdu/u_mdu/reg0_neg_axb_19_par_0_cZ/F
5.125	1.105	tNET	FF	2	R34C49[0][B]	Mdu/u_mdu/reg0_neg_axb_19_par_1/I0
5.695	0.570	tINS	FR	1	R34C49[0][B]	Mdu/u_mdu/reg0_neg_axb_19_par_1/COUT
5.695	0.000	tNET	RR	2	R34C49[1][A]	Mdu/u_mdu/reg0_neg_axb_23_par_1/CIN
5.730	0.035	tINS	RF	1	R34C49[1][A]	Mdu/u_mdu/reg0_neg_axb_23_par_1/COUT
5.730	0.000	tNET	FF	2	R34C49[1][B]	Mdu/u_mdu/reg0_neg_axb_27_par_1/CIN
5.765	0.035	tINS	FF	1	R34C49[1][B]	Mdu/u_mdu/reg0_neg_axb_27_par_1/COUT
5.765	0.000	tNET	FF	2	R34C49[2][A]	Mdu/u_mdu/reg0_neg_axb_31_par_1/CIN
5.801	0.035	tINS	FF	1	R34C49[2][A]	Mdu/u_mdu/reg0_neg_axb_31_par_1/COUT
5.801	0.000	tNET	FF	2	R34C49[2][B]	Mdu/u_mdu/reg0_neg_cry_34_0/CIN
5.836	0.035	tINS	FF	1	R34C49[2][B]	Mdu/u_mdu/reg0_neg_cry_34_0/COUT
5.836	0.000	tNET	FF	2	R34C50[0][A]	Mdu/u_mdu/reg0_neg_cry_35_0/CIN
5.871	0.035	tINS	FF	1	R34C50[0][A]	Mdu/u_mdu/reg0_neg_cry_35_0/COUT
5.871	0.000	tNET	FF	2	R34C50[0][B]	Mdu/u_mdu/reg0_neg_cry_36_0/CIN
5.906	0.035	tINS	FF	1	R34C50[0][B]	Mdu/u_mdu/reg0_neg_cry_36_0/COUT
5.906	0.000	tNET	FF	2	R34C50[1][A]	Mdu/u_mdu/reg0_neg_cry_37_0/CIN
5.941	0.035	tINS	FF	1	R34C50[1][A]	Mdu/u_mdu/reg0_neg_cry_37_0/COUT
5.941	0.000	tNET	FF	2	R34C50[1][B]	Mdu/u_mdu/reg0_neg_cry_38_0/CIN
5.977	0.035	tINS	FF	1	R34C50[1][B]	Mdu/u_mdu/reg0_neg_cry_38_0/COUT
5.977	0.000	tNET	FF	2	R34C50[2][A]	Mdu/u_mdu/reg0_neg_cry_39_0/CIN
6.012	0.035	tINS	FF	1	R34C50[2][A]	Mdu/u_mdu/reg0_neg_cry_39_0/COUT
6.012	0.000	tNET	FF	2	R34C50[2][B]	Mdu/u_mdu/reg0_neg_cry_40_0/CIN
6.047	0.035	tINS	FF	1	R34C50[2][B]	Mdu/u_mdu/reg0_neg_cry_40_0/COUT
6.047	0.000	tNET	FF	2	R34C51[0][A]	Mdu/u_mdu/reg0_neg_cry_41_0/CIN
6.082	0.035	tINS	FF	1	R34C51[0][A]	Mdu/u_mdu/reg0_neg_cry_41_0/COUT
6.082	0.000	tNET	FF	2	R34C51[0][B]	Mdu/u_mdu/reg0_neg_cry_42_0/CIN
6.552	0.470	tINS	FF	1	R34C51[0][B]	Mdu/u_mdu/reg0_neg_cry_42_0/SUM
7.236	0.684	tNET	FF	1	R39C53[0][A]	Mdu/u_mdu/reg0_post_swap_2[10]/I2
7.791	0.555	tINS	FF	1	R39C53[0][A]	Mdu/u_mdu/reg0_post_swap_2[10]/F
7.791	0.000	tNET	FF	1	R39C53[0][A]	Mdu/u_mdu/reg0_post_swap_4[10]/I0
7.894	0.103	tINS	FF	1	R39C53[0][A]	Mdu/u_mdu/reg0_post_swap_4[10]/O
8.507	0.613	tNET	FF	1	R39C61[3][B]	Mdu/u_mdu/reg0_post_swap_5[10]/I1
9.062	0.555	tINS	FF	3	R39C61[3][B]	Mdu/u_mdu/reg0_post_swap_5[10]/F
9.508	0.446	tNET	FF	1	R39C54[2][A]	Mdu/u_mdu/res0_cZ[10]/I1
10.063	0.555	tINS	FF	3	R39C54[2][A]	Mdu/u_mdu/res0_cZ[10]/F
10.901	0.838	tNET	FF	1	BSRAM_R36[15]	memq_memq_0_5/DI0

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	577	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	BSRAM_R36[15]	memq_memq_0_5/CLKA
11.683	-0.200	tUnc				memq_memq_0_5
11.648	-0.035	tSu		1	BSRAM_R36[15]	memq_memq_0_5

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 3.712, 41.163%; route: 5.074, 56.264%; tC2Q: 0.232, 2.573%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path12

Path Summary:

Slack	0.748
Data Arrival Time	10.900
Data Required Time	11.648
From	Mdu/u_mdu/reg1_Z[16]
To	Mdu/u_mdu/reg0_Z[64]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.683	0.683	tINS	RR	577	IOT48[A]	clk_ibuf/O
1.883	1.201	tNET	RR	1	R30C61[0][A]	Mdu/u_mdu/reg1_Z[16]/CLK
2.115	0.232	tC2Q	RF	8	R30C61[0][A]	Mdu/u_mdu/reg1_Z[16]/Q
3.560	1.445	tNET	FF	1	R43C62[0][A]	Mdu/u_mdu/adder_sum_axb_16_lofx_cZ/I1
4.077	0.517	tINS	FF	1	R43C62[0][A]	Mdu/u_mdu/adder_sum_axb_16_lofx_cZ/F
4.976	0.899	tNET	FF	2	R44C62[0][A]	Mdu/u_mdu/adder_sum_cry_16_0/I0
5.546	0.570	tINS	FR	1	R44C62[0][A]	Mdu/u_mdu/adder_sum_cry_16_0/COUT
5.546	0.000	tNET	RR	2	R44C62[0][B]	Mdu/u_mdu/adder_sum_cry_17_0/CIN
5.581	0.035	tINS	RF	1	R44C62[0][B]	Mdu/u_mdu/adder_sum_cry_17_0/COUT
5.581	0.000	tNET	FF	2	R44C62[1][A]	Mdu/u_mdu/adder_sum_cry_18_0/CIN
5.616	0.035	tINS	FF	1	R44C62[1][A]	Mdu/u_mdu/adder_sum_cry_18_0/COUT
5.616	0.000	tNET	FF	2	R44C62[1][B]	Mdu/u_mdu/adder_sum_cry_19_0/CIN
5.651	0.035	tINS	FF	1	R44C62[1][B]	Mdu/u_mdu/adder_sum_cry_19_0/COUT
5.651	0.000	tNET	FF	2	R44C62[2][A]	Mdu/u_mdu/adder_sum_cry_20_0/CIN
5.686	0.035	tINS	FF	1	R44C62[2][A]	Mdu/u_mdu/adder_sum_cry_20_0/COUT
5.686	0.000	tNET	FF	2	R44C62[2][B]	Mdu/u_mdu/adder_sum_cry_21_0/CIN
5.722	0.035	tINS	FF	1	R44C62[2][B]	Mdu/u_mdu/adder_sum_cry_21_0/COUT
5.722	0.000	tNET	FF	2	R44C63[0][A]	Mdu/u_mdu/adder_sum_cry_22_0/CIN
5.757	0.035	tINS	FF	1	R44C63[0][A]	Mdu/u_mdu/adder_sum_cry_22_0/COUT
5.757	0.000	tNET	FF	2	R44C63[0][B]	Mdu/u_mdu/adder_sum_cry_23_0/CIN
5.792	0.035	tINS	FF	1	R44C63[0][B]	Mdu/u_mdu/adder_sum_cry_23_0/COUT
5.792	0.000	tNET	FF	2	R44C63[1][A]	Mdu/u_mdu/adder_sum_cry_24_0/CIN
5.827	0.035	tINS	FF	1	R44C63[1][A]	Mdu/u_mdu/adder_sum_cry_24_0/COUT
5.827	0.000	tNET	FF	2	R44C63[1][B]	Mdu/u_mdu/adder_sum_cry_25_0/CIN
5.862	0.035	tINS	FF	1	R44C63[1][B]	Mdu/u_mdu/adder_sum_cry_25_0/COUT
5.862	0.000	tNET	FF	2	R44C63[2][A]	Mdu/u_mdu/adder_sum_cry_26_0/CIN
5.898	0.035	tINS	FF	1	R44C63[2][A]	Mdu/u_mdu/adder_sum_cry_26_0/COUT
5.898	0.000	tNET	FF	2	R44C63[2][B]	Mdu/u_mdu/adder_sum_cry_27_0/CIN
5.933	0.035	tINS	FF	1	R44C63[2][B]	Mdu/u_mdu/adder_sum_cry_27_0/COUT
5.933	0.000	tNET	FF	2	R44C64[0][A]	Mdu/u_mdu/adder_sum_cry_28_0/CIN
5.968	0.035	tINS	FF	1	R44C64[0][A]	Mdu/u_mdu/adder_sum_cry_28_0/COUT
5.968	0.000	tNET	FF	2	R44C64[0][B]	Mdu/u_mdu/adder_sum_cry_29_0/CIN
6.003	0.035	tINS	FF	1	R44C64[0][B]	Mdu/u_mdu/adder_sum_cry_29_0/COUT
6.003	0.000	tNET	FF	2	R44C64[1][A]	Mdu/u_mdu/adder_sum_cry_30_0/CIN
6.038	0.035	tINS	FF	1	R44C64[1][A]	Mdu/u_mdu/adder_sum_cry_30_0/COUT
6.038	0.000	tNET	FF	2	R44C64[1][B]	Mdu/u_mdu/adder_sum_cry_31_0/CIN
6.074	0.035	tINS	FF	1	R44C64[1][B]	Mdu/u_mdu/adder_sum_cry_31_0/COUT
6.074	0.000	tNET	FF	2	R44C64[2][A]	Mdu/u_mdu/adder_sum_s_32_0/CIN
6.544	0.470	tINS	FF	6	R44C64[2][A]	Mdu/u_mdu/adder_sum_s_32_0/SUM
7.245	0.702	tNET	FF	1	R41C60[3][A]	Mdu/u_mdu/reg0_exe_nx_ss0_cZ/I0
7.616	0.371	tINS	FF	50	R41C60[3][A]	Mdu/u_mdu/reg0_exe_nx_ss0_cZ/F
8.571	0.955	tNET	FF	1	R42C58[3][B]	Mdu/u_mdu/reg0_exe_nx_m0_cZ[64]/I2
9.088	0.517	tINS	FF	1	R42C58[3][B]	Mdu/u_mdu/reg0_exe_nx_m0_cZ[64]/F
9.485	0.397	tNET	FF	1	R40C58[3][A]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[64]/I0
9.938	0.453	tINS	FF	1	R40C58[3][A]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[64]/F
10.351	0.413	tNET	FF	1	R38C57[2][A]	Mdu/u_mdu/reg0_nx_cZ[64]/I0
10.900	0.549	tINS	FR	1	R38C57[2][A]	Mdu/u_mdu/reg0_nx_cZ[64]/F
10.900	0.000	tNET	RR	1	R38C57[2][A]	Mdu/u_mdu/reg0_Z[64]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	577	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R38C57[2][A]	Mdu/u_mdu/reg0_Z[64]/CLK
11.683	-0.200	tUnc				Mdu/u_mdu/reg0_Z[64]
11.648	-0.035	tSu		1	R38C57[2][A]	Mdu/u_mdu/reg0_Z[64]

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 3.975, 44.083%; route: 4.810, 53.344%; tC2Q: 0.232, 2.573%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path13

Path Summary:

Slack	0.763
Data Arrival Time	10.885
Data Required Time	11.648
From	Mdu/u_mdu/reg1_Z[16]
To	Mdu/u_mdu/reg0_Z[44]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.683	0.683	tINS	RR	577	IOT48[A]	clk_ibuf/O
1.883	1.201	tNET	RR	1	R30C61[0][A]	Mdu/u_mdu/reg1_Z[16]/CLK
2.115	0.232	tC2Q	RF	8	R30C61[0][A]	Mdu/u_mdu/reg1_Z[16]/Q
3.560	1.445	tNET	FF	1	R43C62[0][A]	Mdu/u_mdu/adder_sum_axb_16_lofx_cZ/I1
4.077	0.517	tINS	FF	1	R43C62[0][A]	Mdu/u_mdu/adder_sum_axb_16_lofx_cZ/F
4.976	0.899	tNET	FF	2	R44C62[0][A]	Mdu/u_mdu/adder_sum_cry_16_0/I0
5.546	0.570	tINS	FR	1	R44C62[0][A]	Mdu/u_mdu/adder_sum_cry_16_0/COUT
5.546	0.000	tNET	RR	2	R44C62[0][B]	Mdu/u_mdu/adder_sum_cry_17_0/CIN
5.581	0.035	tINS	RF	1	R44C62[0][B]	Mdu/u_mdu/adder_sum_cry_17_0/COUT
5.581	0.000	tNET	FF	2	R44C62[1][A]	Mdu/u_mdu/adder_sum_cry_18_0/CIN
5.616	0.035	tINS	FF	1	R44C62[1][A]	Mdu/u_mdu/adder_sum_cry_18_0/COUT
5.616	0.000	tNET	FF	2	R44C62[1][B]	Mdu/u_mdu/adder_sum_cry_19_0/CIN
5.651	0.035	tINS	FF	1	R44C62[1][B]	Mdu/u_mdu/adder_sum_cry_19_0/COUT
5.651	0.000	tNET	FF	2	R44C62[2][A]	Mdu/u_mdu/adder_sum_cry_20_0/CIN
5.686	0.035	tINS	FF	1	R44C62[2][A]	Mdu/u_mdu/adder_sum_cry_20_0/COUT
5.686	0.000	tNET	FF	2	R44C62[2][B]	Mdu/u_mdu/adder_sum_cry_21_0/CIN
5.722	0.035	tINS	FF	1	R44C62[2][B]	Mdu/u_mdu/adder_sum_cry_21_0/COUT
5.722	0.000	tNET	FF	2	R44C63[0][A]	Mdu/u_mdu/adder_sum_cry_22_0/CIN
5.757	0.035	tINS	FF	1	R44C63[0][A]	Mdu/u_mdu/adder_sum_cry_22_0/COUT
5.757	0.000	tNET	FF	2	R44C63[0][B]	Mdu/u_mdu/adder_sum_cry_23_0/CIN
5.792	0.035	tINS	FF	1	R44C63[0][B]	Mdu/u_mdu/adder_sum_cry_23_0/COUT
5.792	0.000	tNET	FF	2	R44C63[1][A]	Mdu/u_mdu/adder_sum_cry_24_0/CIN
5.827	0.035	tINS	FF	1	R44C63[1][A]	Mdu/u_mdu/adder_sum_cry_24_0/COUT
5.827	0.000	tNET	FF	2	R44C63[1][B]	Mdu/u_mdu/adder_sum_cry_25_0/CIN
5.862	0.035	tINS	FF	1	R44C63[1][B]	Mdu/u_mdu/adder_sum_cry_25_0/COUT
5.862	0.000	tNET	FF	2	R44C63[2][A]	Mdu/u_mdu/adder_sum_cry_26_0/CIN
5.898	0.035	tINS	FF	1	R44C63[2][A]	Mdu/u_mdu/adder_sum_cry_26_0/COUT
5.898	0.000	tNET	FF	2	R44C63[2][B]	Mdu/u_mdu/adder_sum_cry_27_0/CIN
5.933	0.035	tINS	FF	1	R44C63[2][B]	Mdu/u_mdu/adder_sum_cry_27_0/COUT
5.933	0.000	tNET	FF	2	R44C64[0][A]	Mdu/u_mdu/adder_sum_cry_28_0/CIN
5.968	0.035	tINS	FF	1	R44C64[0][A]	Mdu/u_mdu/adder_sum_cry_28_0/COUT
5.968	0.000	tNET	FF	2	R44C64[0][B]	Mdu/u_mdu/adder_sum_cry_29_0/CIN
6.003	0.035	tINS	FF	1	R44C64[0][B]	Mdu/u_mdu/adder_sum_cry_29_0/COUT
6.003	0.000	tNET	FF	2	R44C64[1][A]	Mdu/u_mdu/adder_sum_cry_30_0/CIN
6.038	0.035	tINS	FF	1	R44C64[1][A]	Mdu/u_mdu/adder_sum_cry_30_0/COUT
6.038	0.000	tNET	FF	2	R44C64[1][B]	Mdu/u_mdu/adder_sum_cry_31_0/CIN
6.074	0.035	tINS	FF	1	R44C64[1][B]	Mdu/u_mdu/adder_sum_cry_31_0/COUT
6.074	0.000	tNET	FF	2	R44C64[2][A]	Mdu/u_mdu/adder_sum_s_32_0/CIN
6.544	0.470	tINS	FF	6	R44C64[2][A]	Mdu/u_mdu/adder_sum_s_32_0/SUM
7.245	0.702	tNET	FF	1	R41C60[3][A]	Mdu/u_mdu/reg0_exe_nx_ss0_cZ/I0
7.616	0.371	tINS	FF	50	R41C60[3][A]	Mdu/u_mdu/reg0_exe_nx_ss0_cZ/F
8.930	1.313	tNET	FF	1	R46C56[2][A]	Mdu/u_mdu/reg0_exe_nx_m0_cZ[44]/I2
9.301	0.371	tINS	FF	1	R46C56[2][A]	Mdu/u_mdu/reg0_exe_nx_m0_cZ[44]/F
9.301	0.000	tNET	FF	1	R46C56[2][A]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[44]/I0
9.404	0.103	tINS	FF	1	R46C56[2][A]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[44]/O
10.336	0.933	tNET	FF	1	R39C55[0][A]	Mdu/u_mdu/reg0_nx_cZ[44]/I0
10.885	0.549	tINS	FR	1	R39C55[0][A]	Mdu/u_mdu/reg0_nx_cZ[44]/F
10.885	0.000	tNET	RR	1	R39C55[0][A]	Mdu/u_mdu/reg0_Z[44]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	577	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R39C55[0][A]	Mdu/u_mdu/reg0_Z[44]/CLK
11.683	-0.200	tUnc				Mdu/u_mdu/reg0_Z[44]
11.648	-0.035	tSu		1	R39C55[0][A]	Mdu/u_mdu/reg0_Z[44]

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 3.479, 38.647%; route: 5.291, 58.776%; tC2Q: 0.232, 2.577%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path14

Path Summary:

Slack	0.766
Data Arrival Time	10.883
Data Required Time	11.648
From	Mdu/u_mdu/reg0_Z[8]
To	memq_memq_0_0
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.683	0.683	tINS	RR	577	IOT48[A]	clk_ibuf/O
1.883	1.201	tNET	RR	1	R51C62[2][A]	Mdu/u_mdu/reg0_Z[8]/CLK
2.115	0.232	tC2Q	RF	18	R51C62[2][A]	Mdu/u_mdu/reg0_Z[8]/Q
3.384	1.269	tNET	FF	1	R40C59[3][B]	Mdu/u_mdu/reg0_neg_axb_8_par_0_cZ/I0
3.939	0.555	tINS	FF	1	R40C59[3][B]	Mdu/u_mdu/reg0_neg_axb_8_par_0_cZ/F
4.352	0.413	tNET	FF	2	R42C58[2][A]	Mdu/u_mdu/reg0_neg_axb_8_par_1/I0
4.922	0.570	tINS	FR	1	R42C58[2][A]	Mdu/u_mdu/reg0_neg_axb_8_par_1/COUT
4.922	0.000	tNET	RR	2	R42C58[2][B]	Mdu/u_mdu/reg0_neg_axb_12_par_1/CIN
4.957	0.035	tINS	RF	1	R42C58[2][B]	Mdu/u_mdu/reg0_neg_axb_12_par_1/COUT
4.957	0.000	tNET	FF	2	R42C59[0][A]	Mdu/u_mdu/reg0_neg_axb_16_par_1/CIN
4.992	0.035	tINS	FF	1	R42C59[0][A]	Mdu/u_mdu/reg0_neg_axb_16_par_1/COUT
4.992	0.000	tNET	FF	2	R42C59[0][B]	Mdu/u_mdu/reg0_neg_cry_19_0/CIN
5.028	0.035	tINS	FF	1	R42C59[0][B]	Mdu/u_mdu/reg0_neg_cry_19_0/COUT
5.028	0.000	tNET	FF	2	R42C59[1][A]	Mdu/u_mdu/reg0_neg_cry_20_0/CIN
5.063	0.035	tINS	FF	1	R42C59[1][A]	Mdu/u_mdu/reg0_neg_cry_20_0/COUT
5.063	0.000	tNET	FF	2	R42C59[1][B]	Mdu/u_mdu/reg0_neg_cry_21_0/CIN
5.098	0.035	tINS	FF	1	R42C59[1][B]	Mdu/u_mdu/reg0_neg_cry_21_0/COUT
5.098	0.000	tNET	FF	2	R42C59[2][A]	Mdu/u_mdu/reg0_neg_cry_22_0/CIN
5.133	0.035	tINS	FF	1	R42C59[2][A]	Mdu/u_mdu/reg0_neg_cry_22_0/COUT
5.133	0.000	tNET	FF	2	R42C59[2][B]	Mdu/u_mdu/reg0_neg_cry_23_0/CIN
5.168	0.035	tINS	FF	1	R42C59[2][B]	Mdu/u_mdu/reg0_neg_cry_23_0/COUT
5.168	0.000	tNET	FF	2	R42C60[0][A]	Mdu/u_mdu/reg0_neg_cry_24_0/CIN
5.204	0.035	tINS	FF	1	R42C60[0][A]	Mdu/u_mdu/reg0_neg_cry_24_0/COUT
5.204	0.000	tNET	FF	2	R42C60[0][B]	Mdu/u_mdu/reg0_neg_cry_25_0/CIN
5.239	0.035	tINS	FF	1	R42C60[0][B]	Mdu/u_mdu/reg0_neg_cry_25_0/COUT
5.239	0.000	tNET	FF	2	R42C60[1][A]	Mdu/u_mdu/reg0_neg_cry_26_0/CIN
5.274	0.035	tINS	FF	1	R42C60[1][A]	Mdu/u_mdu/reg0_neg_cry_26_0/COUT
5.274	0.000	tNET	FF	2	R42C60[1][B]	Mdu/u_mdu/reg0_neg_cry_27_0/CIN
5.309	0.035	tINS	FF	1	R42C60[1][B]	Mdu/u_mdu/reg0_neg_cry_27_0/COUT
5.309	0.000	tNET	FF	2	R42C60[2][A]	Mdu/u_mdu/reg0_neg_cry_28_0/CIN
5.344	0.035	tINS	FF	1	R42C60[2][A]	Mdu/u_mdu/reg0_neg_cry_28_0/COUT
5.344	0.000	tNET	FF	2	R42C60[2][B]	Mdu/u_mdu/reg0_neg_cry_29_0/CIN
5.380	0.035	tINS	FF	1	R42C60[2][B]	Mdu/u_mdu/reg0_neg_cry_29_0/COUT
5.380	0.000	tNET	FF	2	R42C61[0][A]	Mdu/u_mdu/reg0_neg_cry_30_0/CIN
5.415	0.035	tINS	FF	1	R42C61[0][A]	Mdu/u_mdu/reg0_neg_cry_30_0/COUT
5.415	0.000	tNET	FF	2	R42C61[0][B]	Mdu/u_mdu/reg0_neg_cry_31_0/CIN
5.450	0.035	tINS	FF	1	R42C61[0][B]	Mdu/u_mdu/reg0_neg_cry_31_0/COUT
5.450	0.000	tNET	FF	2	R42C61[1][A]	Mdu/u_mdu/reg0_neg_cry_32_0/CIN
5.485	0.035	tINS	FF	1	R42C61[1][A]	Mdu/u_mdu/reg0_neg_cry_32_0/COUT
5.485	0.000	tNET	FF	2	R42C61[1][B]	Mdu/u_mdu/reg0_neg_s_33_0/CIN
5.955	0.470	tINS	FF	1	R42C61[1][B]	Mdu/u_mdu/reg0_neg_s_33_0/SUM
6.639	0.684	tNET	FF	1	R41C55[3][A]	Mdu/u_mdu/reg0_post_swap_2[1]/I1
7.156	0.517	tINS	FF	1	R41C55[3][A]	Mdu/u_mdu/reg0_post_swap_2[1]/F
7.156	0.000	tNET	FF	1	R41C55[3][A]	Mdu/u_mdu/reg0_post_swap_4[1]/I0
7.259	0.103	tINS	FF	1	R41C55[3][A]	Mdu/u_mdu/reg0_post_swap_4[1]/O
7.512	0.253	tNET	FF	1	R41C54[3][A]	Mdu/u_mdu/reg0_post_swap_5[1]/I1
7.965	0.453	tINS	FF	4	R41C54[3][A]	Mdu/u_mdu/reg0_post_swap_5[1]/F
8.658	0.693	tNET	FF	1	R34C56[3][B]	Mdu/u_mdu/res0_cZ[1]/I1
9.111	0.453	tINS	FF	3	R34C56[3][B]	Mdu/u_mdu/res0_cZ[1]/F
10.883	1.772	tNET	FF	1	BSRAM_R54[13]	memq_memq_0_0/DI1

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	577	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	BSRAM_R54[13]	memq_memq_0_0/CLKA
11.683	-0.200	tUnc				memq_memq_0_0
11.648	-0.035	tSu		1	BSRAM_R54[13]	memq_memq_0_0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 3.684, 40.937%; route: 5.084, 56.485%; tC2Q: 0.232, 2.578%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path15

Path Summary:

Slack	0.766
Data Arrival Time	10.883
Data Required Time	11.648
From	Mdu/u_mdu/reg1_Z[16]
To	Mdu/u_mdu/reg0_Z[60]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.683	0.683	tINS	RR	577	IOT48[A]	clk_ibuf/O
1.883	1.201	tNET	RR	1	R30C61[0][A]	Mdu/u_mdu/reg1_Z[16]/CLK
2.115	0.232	tC2Q	RF	8	R30C61[0][A]	Mdu/u_mdu/reg1_Z[16]/Q
3.560	1.445	tNET	FF	1	R43C62[0][A]	Mdu/u_mdu/adder_sum_axb_16_lofx_cZ/I1
4.077	0.517	tINS	FF	1	R43C62[0][A]	Mdu/u_mdu/adder_sum_axb_16_lofx_cZ/F
4.976	0.899	tNET	FF	2	R44C62[0][A]	Mdu/u_mdu/adder_sum_cry_16_0/I0
5.546	0.570	tINS	FR	1	R44C62[0][A]	Mdu/u_mdu/adder_sum_cry_16_0/COUT
5.546	0.000	tNET	RR	2	R44C62[0][B]	Mdu/u_mdu/adder_sum_cry_17_0/CIN
5.581	0.035	tINS	RF	1	R44C62[0][B]	Mdu/u_mdu/adder_sum_cry_17_0/COUT
5.581	0.000	tNET	FF	2	R44C62[1][A]	Mdu/u_mdu/adder_sum_cry_18_0/CIN
5.616	0.035	tINS	FF	1	R44C62[1][A]	Mdu/u_mdu/adder_sum_cry_18_0/COUT
5.616	0.000	tNET	FF	2	R44C62[1][B]	Mdu/u_mdu/adder_sum_cry_19_0/CIN
5.651	0.035	tINS	FF	1	R44C62[1][B]	Mdu/u_mdu/adder_sum_cry_19_0/COUT
5.651	0.000	tNET	FF	2	R44C62[2][A]	Mdu/u_mdu/adder_sum_cry_20_0/CIN
5.686	0.035	tINS	FF	1	R44C62[2][A]	Mdu/u_mdu/adder_sum_cry_20_0/COUT
5.686	0.000	tNET	FF	2	R44C62[2][B]	Mdu/u_mdu/adder_sum_cry_21_0/CIN
5.722	0.035	tINS	FF	1	R44C62[2][B]	Mdu/u_mdu/adder_sum_cry_21_0/COUT
5.722	0.000	tNET	FF	2	R44C63[0][A]	Mdu/u_mdu/adder_sum_cry_22_0/CIN
5.757	0.035	tINS	FF	1	R44C63[0][A]	Mdu/u_mdu/adder_sum_cry_22_0/COUT
5.757	0.000	tNET	FF	2	R44C63[0][B]	Mdu/u_mdu/adder_sum_cry_23_0/CIN
5.792	0.035	tINS	FF	1	R44C63[0][B]	Mdu/u_mdu/adder_sum_cry_23_0/COUT
5.792	0.000	tNET	FF	2	R44C63[1][A]	Mdu/u_mdu/adder_sum_cry_24_0/CIN
5.827	0.035	tINS	FF	1	R44C63[1][A]	Mdu/u_mdu/adder_sum_cry_24_0/COUT
5.827	0.000	tNET	FF	2	R44C63[1][B]	Mdu/u_mdu/adder_sum_cry_25_0/CIN
5.862	0.035	tINS	FF	1	R44C63[1][B]	Mdu/u_mdu/adder_sum_cry_25_0/COUT
5.862	0.000	tNET	FF	2	R44C63[2][A]	Mdu/u_mdu/adder_sum_cry_26_0/CIN
5.898	0.035	tINS	FF	1	R44C63[2][A]	Mdu/u_mdu/adder_sum_cry_26_0/COUT
5.898	0.000	tNET	FF	2	R44C63[2][B]	Mdu/u_mdu/adder_sum_cry_27_0/CIN
5.933	0.035	tINS	FF	1	R44C63[2][B]	Mdu/u_mdu/adder_sum_cry_27_0/COUT
5.933	0.000	tNET	FF	2	R44C64[0][A]	Mdu/u_mdu/adder_sum_cry_28_0/CIN
5.968	0.035	tINS	FF	1	R44C64[0][A]	Mdu/u_mdu/adder_sum_cry_28_0/COUT
5.968	0.000	tNET	FF	2	R44C64[0][B]	Mdu/u_mdu/adder_sum_cry_29_0/CIN
6.003	0.035	tINS	FF	1	R44C64[0][B]	Mdu/u_mdu/adder_sum_cry_29_0/COUT
6.003	0.000	tNET	FF	2	R44C64[1][A]	Mdu/u_mdu/adder_sum_cry_30_0/CIN
6.038	0.035	tINS	FF	1	R44C64[1][A]	Mdu/u_mdu/adder_sum_cry_30_0/COUT
6.038	0.000	tNET	FF	2	R44C64[1][B]	Mdu/u_mdu/adder_sum_cry_31_0/CIN
6.074	0.035	tINS	FF	1	R44C64[1][B]	Mdu/u_mdu/adder_sum_cry_31_0/COUT
6.074	0.000	tNET	FF	2	R44C64[2][A]	Mdu/u_mdu/adder_sum_s_32_0/CIN
6.544	0.470	tINS	FF	6	R44C64[2][A]	Mdu/u_mdu/adder_sum_s_32_0/SUM
7.245	0.702	tNET	FF	1	R41C60[3][A]	Mdu/u_mdu/reg0_exe_nx_ss0_cZ/I0
7.616	0.371	tINS	FF	50	R41C60[3][A]	Mdu/u_mdu/reg0_exe_nx_ss0_cZ/F
8.675	1.059	tNET	FF	1	R44C55[3][A]	Mdu/u_mdu/reg0_exe_nx_m0_cZ[60]/I2
9.128	0.453	tINS	FF	1	R44C55[3][A]	Mdu/u_mdu/reg0_exe_nx_m0_cZ[60]/F
9.128	0.000	tNET	FF	1	R44C55[3][A]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[60]/I0
9.231	0.103	tINS	FF	1	R44C55[3][A]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[60]/O
10.512	1.280	tNET	FF	1	R56C54[2][B]	Mdu/u_mdu/reg0_nx_0[60]/I2
10.883	0.371	tINS	FF	1	R56C54[2][B]	Mdu/u_mdu/reg0_nx_0[60]/F
10.883	0.000	tNET	FF	1	R56C54[2][B]	Mdu/u_mdu/reg0_Z[60]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	577	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R56C54[2][B]	Mdu/u_mdu/reg0_Z[60]/CLK
11.683	-0.200	tUnc				Mdu/u_mdu/reg0_Z[60]
11.648	-0.035	tSu		1	R56C54[2][B]	Mdu/u_mdu/reg0_Z[60]

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 3.383, 37.592%; route: 5.384, 59.830%; tC2Q: 0.232, 2.578%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path16

Path Summary:

Slack	0.792
Data Arrival Time	10.856
Data Required Time	11.648
From	Mdu/u_mdu/div_shift_number_Z[0]
To	Mdu/u_mdu/reg0_27_rep1_Z
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.683	0.683	tINS	RR	577	IOT48[A]	clk_ibuf/O
1.883	1.201	tNET	RR	1	R44C53[0][B]	Mdu/u_mdu/div_shift_number_Z[0]/CLK
2.115	0.232	tC2Q	RF	113	R44C53[0][B]	Mdu/u_mdu/div_shift_number_Z[0]/Q
3.569	1.454	tNET	FF	1	R43C62[2][A]	Mdu/u_mdu/m3_0_03_1_0_cZ/I0
4.124	0.555	tINS	FF	5	R43C62[2][A]	Mdu/u_mdu/m3_0_03_1_0_cZ/F
4.629	0.504	tNET	FF	1	R47C62[0][A]	Mdu/u_mdu/m11_2_03_2_cZ/I1
5.082	0.453	tINS	FF	1	R47C62[0][A]	Mdu/u_mdu/m11_2_03_2_cZ/F
5.964	0.882	tNET	FF	1	R47C61[2][B]	Mdu/u_mdu/m11_2_03_m1_e/I2
6.481	0.517	tINS	FF	4	R47C61[2][B]	Mdu/u_mdu/m11_2_03_m1_e/F
7.156	0.675	tNET	FF	1	R46C58[2][B]	Mdu/u_mdu/m27_4_01_cZ/I1
7.609	0.453	tINS	FF	1	R46C58[2][B]	Mdu/u_mdu/m27_4_01_cZ/F
8.398	0.789	tNET	FF	1	R34C57[3][B]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[27]/I2
8.860	0.462	tINS	FR	1	R34C57[3][B]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[27]/F
9.033	0.172	tNET	RR	1	R34C56[1][B]	Mdu/u_mdu/reg0_exe_nx_cZ[27]/I3
9.486	0.453	tINS	RF	3	R34C56[1][B]	Mdu/u_mdu/reg0_exe_nx_cZ[27]/F
10.286	0.800	tNET	FF	1	R42C53[1][A]	Mdu/u_mdu/reg0_nx_rep1_cZ[27]/I0
10.856	0.570	tINS	FR	1	R42C53[1][A]	Mdu/u_mdu/reg0_nx_rep1_cZ[27]/F
10.856	0.000	tNET	RR	1	R42C53[1][A]	Mdu/u_mdu/reg0_27_rep1_Z/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	577	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R42C53[1][A]	Mdu/u_mdu/reg0_27_rep1_Z/CLK
11.683	-0.200	tUnc				Mdu/u_mdu/reg0_27_rep1_Z
11.648	-0.035	tSu		1	R42C53[1][A]	Mdu/u_mdu/reg0_27_rep1_Z

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 3.463, 38.595%; route: 5.278, 58.820%; tC2Q: 0.232, 2.586%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path17

Path Summary:

Slack	0.792
Data Arrival Time	10.856
Data Required Time	11.648
From	Mdu/u_mdu/div_shift_number_Z[0]
To	Mdu/u_mdu/reg0_fast_Z[27]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.683	0.683	tINS	RR	577	IOT48[A]	clk_ibuf/O
1.883	1.201	tNET	RR	1	R44C53[0][B]	Mdu/u_mdu/div_shift_number_Z[0]/CLK
2.115	0.232	tC2Q	RF	113	R44C53[0][B]	Mdu/u_mdu/div_shift_number_Z[0]/Q
3.569	1.454	tNET	FF	1	R43C62[2][A]	Mdu/u_mdu/m3_0_03_1_0_cZ/I0
4.124	0.555	tINS	FF	5	R43C62[2][A]	Mdu/u_mdu/m3_0_03_1_0_cZ/F
4.629	0.504	tNET	FF	1	R47C62[0][A]	Mdu/u_mdu/m11_2_03_2_cZ/I1
5.082	0.453	tINS	FF	1	R47C62[0][A]	Mdu/u_mdu/m11_2_03_2_cZ/F
5.964	0.882	tNET	FF	1	R47C61[2][B]	Mdu/u_mdu/m11_2_03_m1_e/I2
6.481	0.517	tINS	FF	4	R47C61[2][B]	Mdu/u_mdu/m11_2_03_m1_e/F
7.156	0.675	tNET	FF	1	R46C58[2][B]	Mdu/u_mdu/m27_4_01_cZ/I1
7.609	0.453	tINS	FF	1	R46C58[2][B]	Mdu/u_mdu/m27_4_01_cZ/F
8.398	0.789	tNET	FF	1	R34C57[3][B]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[27]/I2
8.860	0.462	tINS	FR	1	R34C57[3][B]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[27]/F
9.033	0.172	tNET	RR	1	R34C56[1][B]	Mdu/u_mdu/reg0_exe_nx_cZ[27]/I3
9.486	0.453	tINS	RF	3	R34C56[1][B]	Mdu/u_mdu/reg0_exe_nx_cZ[27]/F
10.286	0.800	tNET	FF	1	R42C53[2][B]	Mdu/u_mdu/reg0_nx_fast_cZ[27]/I0
10.856	0.570	tINS	FR	1	R42C53[2][B]	Mdu/u_mdu/reg0_nx_fast_cZ[27]/F
10.856	0.000	tNET	RR	1	R42C53[2][B]	Mdu/u_mdu/reg0_fast_Z[27]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	577	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R42C53[2][B]	Mdu/u_mdu/reg0_fast_Z[27]/CLK
11.683	-0.200	tUnc				Mdu/u_mdu/reg0_fast_Z[27]
11.648	-0.035	tSu		1	R42C53[2][B]	Mdu/u_mdu/reg0_fast_Z[27]

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 3.463, 38.595%; route: 5.278, 58.820%; tC2Q: 0.232, 2.586%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path18

Path Summary:

Slack	0.792
Data Arrival Time	10.856
Data Required Time	11.648
From	Mdu/u_mdu/div_shift_number_Z[0]
To	Mdu/u_mdu/reg0_Z[27]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.683	0.683	tINS	RR	577	IOT48[A]	clk_ibuf/O
1.883	1.201	tNET	RR	1	R44C53[0][B]	Mdu/u_mdu/div_shift_number_Z[0]/CLK
2.115	0.232	tC2Q	RF	113	R44C53[0][B]	Mdu/u_mdu/div_shift_number_Z[0]/Q
3.569	1.454	tNET	FF	1	R43C62[2][A]	Mdu/u_mdu/m3_0_03_1_0_cZ/I0
4.124	0.555	tINS	FF	5	R43C62[2][A]	Mdu/u_mdu/m3_0_03_1_0_cZ/F
4.629	0.504	tNET	FF	1	R47C62[0][A]	Mdu/u_mdu/m11_2_03_2_cZ/I1
5.082	0.453	tINS	FF	1	R47C62[0][A]	Mdu/u_mdu/m11_2_03_2_cZ/F
5.964	0.882	tNET	FF	1	R47C61[2][B]	Mdu/u_mdu/m11_2_03_m1_e/I2
6.481	0.517	tINS	FF	4	R47C61[2][B]	Mdu/u_mdu/m11_2_03_m1_e/F
7.156	0.675	tNET	FF	1	R46C58[2][B]	Mdu/u_mdu/m27_4_01_cZ/I1
7.609	0.453	tINS	FF	1	R46C58[2][B]	Mdu/u_mdu/m27_4_01_cZ/F
8.398	0.789	tNET	FF	1	R34C57[3][B]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[27]/I2
8.860	0.462	tINS	FR	1	R34C57[3][B]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[27]/F
9.033	0.172	tNET	RR	1	R34C56[1][B]	Mdu/u_mdu/reg0_exe_nx_cZ[27]/I3
9.486	0.453	tINS	RF	3	R34C56[1][B]	Mdu/u_mdu/reg0_exe_nx_cZ[27]/F
10.286	0.800	tNET	FF	1	R42C53[1][B]	Mdu/u_mdu/reg0_nx_cZ[27]/I0
10.856	0.570	tINS	FR	1	R42C53[1][B]	Mdu/u_mdu/reg0_nx_cZ[27]/F
10.856	0.000	tNET	RR	1	R42C53[1][B]	Mdu/u_mdu/reg0_Z[27]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	577	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R42C53[1][B]	Mdu/u_mdu/reg0_Z[27]/CLK
11.683	-0.200	tUnc				Mdu/u_mdu/reg0_Z[27]
11.648	-0.035	tSu		1	R42C53[1][B]	Mdu/u_mdu/reg0_Z[27]

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 3.463, 38.595%; route: 5.278, 58.820%; tC2Q: 0.232, 2.586%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path19

Path Summary:

Slack	0.817
Data Arrival Time	10.831
Data Required Time	11.648
From	Mdu/u_mdu/reg0_Z[21]
To	memq_memq_0_2
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.683	0.683	tINS	RR	577	IOT48[A]	clk_ibuf/O
1.883	1.201	tNET	RR	1	R56C53[0][A]	Mdu/u_mdu/reg0_Z[21]/CLK
2.115	0.232	tC2Q	RF	17	R56C53[0][A]	Mdu/u_mdu/reg0_Z[21]/Q
3.503	1.388	tNET	FF	1	R39C56[1][A]	Mdu/u_mdu/reg0_neg_axb_19_par_0_cZ/I0
4.020	0.517	tINS	FF	1	R39C56[1][A]	Mdu/u_mdu/reg0_neg_axb_19_par_0_cZ/F
5.125	1.105	tNET	FF	2	R34C49[0][B]	Mdu/u_mdu/reg0_neg_axb_19_par_1/I0
5.695	0.570	tINS	FR	1	R34C49[0][B]	Mdu/u_mdu/reg0_neg_axb_19_par_1/COUT
5.695	0.000	tNET	RR	2	R34C49[1][A]	Mdu/u_mdu/reg0_neg_axb_23_par_1/CIN
5.730	0.035	tINS	RF	1	R34C49[1][A]	Mdu/u_mdu/reg0_neg_axb_23_par_1/COUT
5.730	0.000	tNET	FF	2	R34C49[1][B]	Mdu/u_mdu/reg0_neg_axb_27_par_1/CIN
5.765	0.035	tINS	FF	1	R34C49[1][B]	Mdu/u_mdu/reg0_neg_axb_27_par_1/COUT
5.765	0.000	tNET	FF	2	R34C49[2][A]	Mdu/u_mdu/reg0_neg_axb_31_par_1/CIN
5.801	0.035	tINS	FF	1	R34C49[2][A]	Mdu/u_mdu/reg0_neg_axb_31_par_1/COUT
5.801	0.000	tNET	FF	2	R34C49[2][B]	Mdu/u_mdu/reg0_neg_cry_34_0/CIN
5.836	0.035	tINS	FF	1	R34C49[2][B]	Mdu/u_mdu/reg0_neg_cry_34_0/COUT
5.836	0.000	tNET	FF	2	R34C50[0][A]	Mdu/u_mdu/reg0_neg_cry_35_0/CIN
5.871	0.035	tINS	FF	1	R34C50[0][A]	Mdu/u_mdu/reg0_neg_cry_35_0/COUT
5.871	0.000	tNET	FF	2	R34C50[0][B]	Mdu/u_mdu/reg0_neg_cry_36_0/CIN
6.341	0.470	tINS	FF	1	R34C50[0][B]	Mdu/u_mdu/reg0_neg_cry_36_0/SUM
6.754	0.413	tNET	FF	1	R35C52[2][A]	Mdu/u_mdu/reg0_post_swap_2[4]/I2
7.125	0.371	tINS	FF	1	R35C52[2][A]	Mdu/u_mdu/reg0_post_swap_2[4]/F
7.125	0.000	tNET	FF	1	R35C52[2][A]	Mdu/u_mdu/reg0_post_swap_4[4]/I0
7.228	0.103	tINS	FF	1	R35C52[2][A]	Mdu/u_mdu/reg0_post_swap_4[4]/O
8.133	0.904	tNET	FF	1	R38C55[0][B]	Mdu/u_mdu/reg0_post_swap_5[4]/I1
8.650	0.517	tINS	FF	3	R38C55[0][B]	Mdu/u_mdu/reg0_post_swap_5[4]/F
9.338	0.688	tNET	FF	1	R42C52[0][B]	Mdu/u_mdu/res0_cZ[4]/I1
9.791	0.453	tINS	FF	3	R42C52[0][B]	Mdu/u_mdu/res0_cZ[4]/F
10.831	1.040	tNET	FF	1	BSRAM_R54[14]	memq_memq_0_2/DI0

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	577	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	BSRAM_R54[14]	memq_memq_0_2/CLKA
11.683	-0.200	tUnc				memq_memq_0_2
11.648	-0.035	tSu		1	BSRAM_R54[14]	memq_memq_0_2

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 3.177, 35.504%; route: 5.539, 61.903%; tC2Q: 0.232, 2.593%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path20

Path Summary:

Slack	0.822
Data Arrival Time	10.827
Data Required Time	11.648
From	Mdu/u_mdu/reg1_Z[16]
To	Mdu/u_mdu/reg0_Z[52]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.683	0.683	tINS	RR	577	IOT48[A]	clk_ibuf/O
1.883	1.201	tNET	RR	1	R30C61[0][A]	Mdu/u_mdu/reg1_Z[16]/CLK
2.115	0.232	tC2Q	RF	8	R30C61[0][A]	Mdu/u_mdu/reg1_Z[16]/Q
3.560	1.445	tNET	FF	1	R43C62[0][A]	Mdu/u_mdu/adder_sum_axb_16_lofx_cZ/I1
4.077	0.517	tINS	FF	1	R43C62[0][A]	Mdu/u_mdu/adder_sum_axb_16_lofx_cZ/F
4.976	0.899	tNET	FF	2	R44C62[0][A]	Mdu/u_mdu/adder_sum_cry_16_0/I0
5.546	0.570	tINS	FR	1	R44C62[0][A]	Mdu/u_mdu/adder_sum_cry_16_0/COUT
5.546	0.000	tNET	RR	2	R44C62[0][B]	Mdu/u_mdu/adder_sum_cry_17_0/CIN
5.581	0.035	tINS	RF	1	R44C62[0][B]	Mdu/u_mdu/adder_sum_cry_17_0/COUT
5.581	0.000	tNET	FF	2	R44C62[1][A]	Mdu/u_mdu/adder_sum_cry_18_0/CIN
5.616	0.035	tINS	FF	1	R44C62[1][A]	Mdu/u_mdu/adder_sum_cry_18_0/COUT
5.616	0.000	tNET	FF	2	R44C62[1][B]	Mdu/u_mdu/adder_sum_cry_19_0/CIN
5.651	0.035	tINS	FF	1	R44C62[1][B]	Mdu/u_mdu/adder_sum_cry_19_0/COUT
5.651	0.000	tNET	FF	2	R44C62[2][A]	Mdu/u_mdu/adder_sum_cry_20_0/CIN
5.686	0.035	tINS	FF	1	R44C62[2][A]	Mdu/u_mdu/adder_sum_cry_20_0/COUT
5.686	0.000	tNET	FF	2	R44C62[2][B]	Mdu/u_mdu/adder_sum_cry_21_0/CIN
5.722	0.035	tINS	FF	1	R44C62[2][B]	Mdu/u_mdu/adder_sum_cry_21_0/COUT
5.722	0.000	tNET	FF	2	R44C63[0][A]	Mdu/u_mdu/adder_sum_cry_22_0/CIN
5.757	0.035	tINS	FF	1	R44C63[0][A]	Mdu/u_mdu/adder_sum_cry_22_0/COUT
5.757	0.000	tNET	FF	2	R44C63[0][B]	Mdu/u_mdu/adder_sum_cry_23_0/CIN
5.792	0.035	tINS	FF	1	R44C63[0][B]	Mdu/u_mdu/adder_sum_cry_23_0/COUT
5.792	0.000	tNET	FF	2	R44C63[1][A]	Mdu/u_mdu/adder_sum_cry_24_0/CIN
5.827	0.035	tINS	FF	1	R44C63[1][A]	Mdu/u_mdu/adder_sum_cry_24_0/COUT
5.827	0.000	tNET	FF	2	R44C63[1][B]	Mdu/u_mdu/adder_sum_cry_25_0/CIN
5.862	0.035	tINS	FF	1	R44C63[1][B]	Mdu/u_mdu/adder_sum_cry_25_0/COUT
5.862	0.000	tNET	FF	2	R44C63[2][A]	Mdu/u_mdu/adder_sum_cry_26_0/CIN
5.898	0.035	tINS	FF	1	R44C63[2][A]	Mdu/u_mdu/adder_sum_cry_26_0/COUT
5.898	0.000	tNET	FF	2	R44C63[2][B]	Mdu/u_mdu/adder_sum_cry_27_0/CIN
5.933	0.035	tINS	FF	1	R44C63[2][B]	Mdu/u_mdu/adder_sum_cry_27_0/COUT
5.933	0.000	tNET	FF	2	R44C64[0][A]	Mdu/u_mdu/adder_sum_cry_28_0/CIN
5.968	0.035	tINS	FF	1	R44C64[0][A]	Mdu/u_mdu/adder_sum_cry_28_0/COUT
5.968	0.000	tNET	FF	2	R44C64[0][B]	Mdu/u_mdu/adder_sum_cry_29_0/CIN
6.003	0.035	tINS	FF	1	R44C64[0][B]	Mdu/u_mdu/adder_sum_cry_29_0/COUT
6.003	0.000	tNET	FF	2	R44C64[1][A]	Mdu/u_mdu/adder_sum_cry_30_0/CIN
6.038	0.035	tINS	FF	1	R44C64[1][A]	Mdu/u_mdu/adder_sum_cry_30_0/COUT
6.038	0.000	tNET	FF	2	R44C64[1][B]	Mdu/u_mdu/adder_sum_cry_31_0/CIN
6.074	0.035	tINS	FF	1	R44C64[1][B]	Mdu/u_mdu/adder_sum_cry_31_0/COUT
6.074	0.000	tNET	FF	2	R44C64[2][A]	Mdu/u_mdu/adder_sum_s_32_0/CIN
6.544	0.470	tINS	FF	6	R44C64[2][A]	Mdu/u_mdu/adder_sum_s_32_0/SUM
7.245	0.702	tNET	FF	1	R41C60[3][A]	Mdu/u_mdu/reg0_exe_nx_ss0_cZ/I0
7.616	0.371	tINS	FF	50	R41C60[3][A]	Mdu/u_mdu/reg0_exe_nx_ss0_cZ/F
8.831	1.214	tNET	FF	1	R44C56[3][A]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[52]/S0
9.082	0.251	tINS	FF	1	R44C56[3][A]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[52]/O
10.456	1.374	tNET	FF	1	R44C55[2][B]	Mdu/u_mdu/reg0_nx_0[52]/I2
10.827	0.371	tINS	FF	1	R44C55[2][B]	Mdu/u_mdu/reg0_nx_0[52]/F
10.827	0.000	tNET	FF	1	R44C55[2][B]	Mdu/u_mdu/reg0_Z[52]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	577	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R44C55[2][B]	Mdu/u_mdu/reg0_Z[52]/CLK
11.683	-0.200	tUnc				Mdu/u_mdu/reg0_Z[52]
11.648	-0.035	tSu		1	R44C55[2][B]	Mdu/u_mdu/reg0_Z[52]

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	6
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 3.078, 34.416%; route: 5.633, 62.990%; tC2Q: 0.232, 2.594%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path21

Path Summary:

Slack	0.824
Data Arrival Time	10.825
Data Required Time	11.648
From	Mdu/u_mdu/div_shift_number_Z[0]
To	Mdu/u_mdu/reg0_fast_Z[13]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.683	0.683	tINS	RR	577	IOT48[A]	clk_ibuf/O
1.883	1.201	tNET	RR	1	R44C53[0][B]	Mdu/u_mdu/div_shift_number_Z[0]/CLK
2.115	0.232	tC2Q	RF	113	R44C53[0][B]	Mdu/u_mdu/div_shift_number_Z[0]/Q
4.165	2.050	tNET	FF	1	R48C56[3][B]	Mdu/u_mdu/m5_0_03_1_cZ/I0
4.735	0.570	tINS	FR	1	R48C56[3][B]	Mdu/u_mdu/m5_0_03_1_cZ/F
4.736	0.001	tNET	RR	1	R48C56[3][A]	Mdu/u_mdu/m5_0_03_cZ/I1
5.253	0.517	tINS	RF	5	R48C56[3][A]	Mdu/u_mdu/m5_0_03_cZ/F
5.786	0.533	tNET	FF	1	R52C57[2][A]	Mdu/u_mdu/m13_2_03_m1_e_sx_cZ/I1
6.303	0.517	tINS	FF	1	R52C57[2][A]	Mdu/u_mdu/m13_2_03_m1_e_sx_cZ/F
6.700	0.397	tNET	FF	1	R50C57[3][A]	Mdu/u_mdu/m13_2_03_m1_e_sx_RNI3693/I1
7.255	0.555	tINS	FF	2	R50C57[3][A]	Mdu/u_mdu/m13_2_03_m1_e_sx_RNI3693/F
7.927	0.672	tNET	FF	1	R48C53[3][B]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[13]/I2
8.444	0.517	tINS	FF	1	R48C53[3][B]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[13]/F
9.278	0.834	tNET	FF	1	R42C53[3][B]	Mdu/u_mdu/reg0_exe_nx_cZ[13]/I3
9.731	0.453	tINS	FF	2	R42C53[3][B]	Mdu/u_mdu/reg0_exe_nx_cZ[13]/F
10.255	0.524	tNET	FF	1	R40C57[2][B]	Mdu/u_mdu/reg0_nx_fast_cZ[13]/I0
10.825	0.570	tINS	FR	1	R40C57[2][B]	Mdu/u_mdu/reg0_nx_fast_cZ[13]/F
10.825	0.000	tNET	RR	1	R40C57[2][B]	Mdu/u_mdu/reg0_fast_Z[13]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	577	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R40C57[2][B]	Mdu/u_mdu/reg0_fast_Z[13]/CLK
11.683	-0.200	tUnc				Mdu/u_mdu/reg0_fast_Z[13]
11.648	-0.035	tSu		1	R40C57[2][B]	Mdu/u_mdu/reg0_fast_Z[13]

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 3.699, 41.370%; route: 5.010, 56.036%; tC2Q: 0.232, 2.595%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path22

Path Summary:

Slack	0.824
Data Arrival Time	10.825
Data Required Time	11.648
From	Mdu/u_mdu/div_shift_number_Z[0]
To	Mdu/u_mdu/reg0_Z[13]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.683	0.683	tINS	RR	577	IOT48[A]	clk_ibuf/O
1.883	1.201	tNET	RR	1	R44C53[0][B]	Mdu/u_mdu/div_shift_number_Z[0]/CLK
2.115	0.232	tC2Q	RF	113	R44C53[0][B]	Mdu/u_mdu/div_shift_number_Z[0]/Q
4.165	2.050	tNET	FF	1	R48C56[3][B]	Mdu/u_mdu/m5_0_03_1_cZ/I0
4.735	0.570	tINS	FR	1	R48C56[3][B]	Mdu/u_mdu/m5_0_03_1_cZ/F
4.736	0.001	tNET	RR	1	R48C56[3][A]	Mdu/u_mdu/m5_0_03_cZ/I1
5.253	0.517	tINS	RF	5	R48C56[3][A]	Mdu/u_mdu/m5_0_03_cZ/F
5.786	0.533	tNET	FF	1	R52C57[2][A]	Mdu/u_mdu/m13_2_03_m1_e_sx_cZ/I1
6.303	0.517	tINS	FF	1	R52C57[2][A]	Mdu/u_mdu/m13_2_03_m1_e_sx_cZ/F
6.700	0.397	tNET	FF	1	R50C57[3][A]	Mdu/u_mdu/m13_2_03_m1_e_sx_RNI3693/I1
7.255	0.555	tINS	FF	2	R50C57[3][A]	Mdu/u_mdu/m13_2_03_m1_e_sx_RNI3693/F
7.927	0.672	tNET	FF	1	R48C53[3][B]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[13]/I2
8.444	0.517	tINS	FF	1	R48C53[3][B]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[13]/F
9.278	0.834	tNET	FF	1	R42C53[3][B]	Mdu/u_mdu/reg0_exe_nx_cZ[13]/I3
9.731	0.453	tINS	FF	2	R42C53[3][B]	Mdu/u_mdu/reg0_exe_nx_cZ[13]/F
10.255	0.524	tNET	FF	1	R40C57[2][A]	Mdu/u_mdu/reg0_nx_cZ[13]/I0
10.825	0.570	tINS	FR	1	R40C57[2][A]	Mdu/u_mdu/reg0_nx_cZ[13]/F
10.825	0.000	tNET	RR	1	R40C57[2][A]	Mdu/u_mdu/reg0_Z[13]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	577	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R40C57[2][A]	Mdu/u_mdu/reg0_Z[13]/CLK
11.683	-0.200	tUnc				Mdu/u_mdu/reg0_Z[13]
11.648	-0.035	tSu		1	R40C57[2][A]	Mdu/u_mdu/reg0_Z[13]

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 3.699, 41.370%; route: 5.010, 56.036%; tC2Q: 0.232, 2.595%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path23

Path Summary:

Slack	0.829
Data Arrival Time	10.819
Data Required Time	11.648
From	Mdu/u_mdu/div_shift_number_Z[0]
To	Mdu/u_mdu/reg0_Z[21]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.683	0.683	tINS	RR	577	IOT48[A]	clk_ibuf/O
1.883	1.201	tNET	RR	1	R44C53[0][B]	Mdu/u_mdu/div_shift_number_Z[0]/CLK
2.115	0.232	tC2Q	RF	113	R44C53[0][B]	Mdu/u_mdu/div_shift_number_Z[0]/Q
4.165	2.050	tNET	FF	1	R48C56[3][B]	Mdu/u_mdu/m5_0_03_1_cZ/I0
4.735	0.570	tINS	FR	1	R48C56[3][B]	Mdu/u_mdu/m5_0_03_1_cZ/F
4.736	0.001	tNET	RR	1	R48C56[3][A]	Mdu/u_mdu/m5_0_03_cZ/I1
5.253	0.517	tINS	RF	5	R48C56[3][A]	Mdu/u_mdu/m5_0_03_cZ/F
5.924	0.670	tNET	FF	1	R48C61[0][B]	Mdu/u_mdu/m5_2_03_cZ/I3
6.441	0.517	tINS	FF	4	R48C61[0][B]	Mdu/u_mdu/m5_2_03_cZ/F
7.166	0.725	tNET	FF	1	R52C54[1][A]	Mdu/u_mdu/m21_4_01_cZ/I1
7.537	0.371	tINS	FF	1	R52C54[1][A]	Mdu/u_mdu/m21_4_01_cZ/F
7.950	0.413	tNET	FF	1	R55C54[1][B]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[21]/I2
8.321	0.371	tINS	FF	1	R55C54[1][B]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[21]/F
8.977	0.656	tNET	FF	1	R55C53[1][A]	Mdu/u_mdu/reg0_exe_nx_cZ[21]/I3
9.547	0.570	tINS	FR	1	R55C53[1][A]	Mdu/u_mdu/reg0_exe_nx_cZ[21]/F
9.720	0.172	tNET	RR	1	R56C53[2][B]	Mdu/u_mdu/reg0_nx_sx_cZ[21]/I0
10.269	0.549	tINS	RR	1	R56C53[2][B]	Mdu/u_mdu/reg0_nx_sx_cZ[21]/F
10.270	0.001	tNET	RR	1	R56C53[0][A]	Mdu/u_mdu/reg0_nx_cZ[21]/I0
10.819	0.549	tINS	RR	1	R56C53[0][A]	Mdu/u_mdu/reg0_nx_cZ[21]/F
10.819	0.000	tNET	RR	1	R56C53[0][A]	Mdu/u_mdu/reg0_Z[21]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	577	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R56C53[0][A]	Mdu/u_mdu/reg0_Z[21]/CLK
11.683	-0.200	tUnc				Mdu/u_mdu/reg0_Z[21]
11.648	-0.035	tSu		1	R56C53[0][A]	Mdu/u_mdu/reg0_Z[21]

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	8
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 4.014, 44.921%; route: 4.690, 52.483%; tC2Q: 0.232, 2.596%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path24

Path Summary:

Slack	0.835
Data Arrival Time	10.813
Data Required Time	11.648
From	Mdu/u_mdu/reg1_Z[16]
To	Mdu/u_mdu/reg0_Z[41]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.683	0.683	tINS	RR	577	IOT48[A]	clk_ibuf/O
1.883	1.201	tNET	RR	1	R30C61[0][A]	Mdu/u_mdu/reg1_Z[16]/CLK
2.115	0.232	tC2Q	RF	8	R30C61[0][A]	Mdu/u_mdu/reg1_Z[16]/Q
3.560	1.445	tNET	FF	1	R43C62[0][A]	Mdu/u_mdu/adder_sum_axb_16_lofx_cZ/I1
4.077	0.517	tINS	FF	1	R43C62[0][A]	Mdu/u_mdu/adder_sum_axb_16_lofx_cZ/F
4.976	0.899	tNET	FF	2	R44C62[0][A]	Mdu/u_mdu/adder_sum_cry_16_0/I0
5.546	0.570	tINS	FR	1	R44C62[0][A]	Mdu/u_mdu/adder_sum_cry_16_0/COUT
5.546	0.000	tNET	RR	2	R44C62[0][B]	Mdu/u_mdu/adder_sum_cry_17_0/CIN
5.581	0.035	tINS	RF	1	R44C62[0][B]	Mdu/u_mdu/adder_sum_cry_17_0/COUT
5.581	0.000	tNET	FF	2	R44C62[1][A]	Mdu/u_mdu/adder_sum_cry_18_0/CIN
5.616	0.035	tINS	FF	1	R44C62[1][A]	Mdu/u_mdu/adder_sum_cry_18_0/COUT
5.616	0.000	tNET	FF	2	R44C62[1][B]	Mdu/u_mdu/adder_sum_cry_19_0/CIN
5.651	0.035	tINS	FF	1	R44C62[1][B]	Mdu/u_mdu/adder_sum_cry_19_0/COUT
5.651	0.000	tNET	FF	2	R44C62[2][A]	Mdu/u_mdu/adder_sum_cry_20_0/CIN
5.686	0.035	tINS	FF	1	R44C62[2][A]	Mdu/u_mdu/adder_sum_cry_20_0/COUT
5.686	0.000	tNET	FF	2	R44C62[2][B]	Mdu/u_mdu/adder_sum_cry_21_0/CIN
5.722	0.035	tINS	FF	1	R44C62[2][B]	Mdu/u_mdu/adder_sum_cry_21_0/COUT
5.722	0.000	tNET	FF	2	R44C63[0][A]	Mdu/u_mdu/adder_sum_cry_22_0/CIN
5.757	0.035	tINS	FF	1	R44C63[0][A]	Mdu/u_mdu/adder_sum_cry_22_0/COUT
5.757	0.000	tNET	FF	2	R44C63[0][B]	Mdu/u_mdu/adder_sum_cry_23_0/CIN
5.792	0.035	tINS	FF	1	R44C63[0][B]	Mdu/u_mdu/adder_sum_cry_23_0/COUT
5.792	0.000	tNET	FF	2	R44C63[1][A]	Mdu/u_mdu/adder_sum_cry_24_0/CIN
5.827	0.035	tINS	FF	1	R44C63[1][A]	Mdu/u_mdu/adder_sum_cry_24_0/COUT
5.827	0.000	tNET	FF	2	R44C63[1][B]	Mdu/u_mdu/adder_sum_cry_25_0/CIN
5.862	0.035	tINS	FF	1	R44C63[1][B]	Mdu/u_mdu/adder_sum_cry_25_0/COUT
5.862	0.000	tNET	FF	2	R44C63[2][A]	Mdu/u_mdu/adder_sum_cry_26_0/CIN
5.898	0.035	tINS	FF	1	R44C63[2][A]	Mdu/u_mdu/adder_sum_cry_26_0/COUT
5.898	0.000	tNET	FF	2	R44C63[2][B]	Mdu/u_mdu/adder_sum_cry_27_0/CIN
5.933	0.035	tINS	FF	1	R44C63[2][B]	Mdu/u_mdu/adder_sum_cry_27_0/COUT
5.933	0.000	tNET	FF	2	R44C64[0][A]	Mdu/u_mdu/adder_sum_cry_28_0/CIN
5.968	0.035	tINS	FF	1	R44C64[0][A]	Mdu/u_mdu/adder_sum_cry_28_0/COUT
5.968	0.000	tNET	FF	2	R44C64[0][B]	Mdu/u_mdu/adder_sum_cry_29_0/CIN
6.003	0.035	tINS	FF	1	R44C64[0][B]	Mdu/u_mdu/adder_sum_cry_29_0/COUT
6.003	0.000	tNET	FF	2	R44C64[1][A]	Mdu/u_mdu/adder_sum_cry_30_0/CIN
6.038	0.035	tINS	FF	1	R44C64[1][A]	Mdu/u_mdu/adder_sum_cry_30_0/COUT
6.038	0.000	tNET	FF	2	R44C64[1][B]	Mdu/u_mdu/adder_sum_cry_31_0/CIN
6.074	0.035	tINS	FF	1	R44C64[1][B]	Mdu/u_mdu/adder_sum_cry_31_0/COUT
6.074	0.000	tNET	FF	2	R44C64[2][A]	Mdu/u_mdu/adder_sum_s_32_0/CIN
6.544	0.470	tINS	FF	6	R44C64[2][A]	Mdu/u_mdu/adder_sum_s_32_0/SUM
7.245	0.702	tNET	FF	1	R41C60[3][A]	Mdu/u_mdu/reg0_exe_nx_ss0_cZ/I0
7.616	0.371	tINS	FF	50	R41C60[3][A]	Mdu/u_mdu/reg0_exe_nx_ss0_cZ/F
8.595	0.978	tNET	FF	1	R46C60[1][A]	Mdu/u_mdu/reg0_exe_nx_m0_cZ[41]/I2
9.150	0.555	tINS	FF	1	R46C60[1][A]	Mdu/u_mdu/reg0_exe_nx_m0_cZ[41]/F
9.150	0.000	tNET	FF	1	R46C60[1][A]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[41]/I0
9.253	0.103	tINS	FF	1	R46C60[1][A]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[41]/O
10.351	1.099	tNET	FF	1	R35C57[0][B]	Mdu/u_mdu/reg0_nx_cZ[41]/I0
10.813	0.462	tINS	FR	1	R35C57[0][B]	Mdu/u_mdu/reg0_nx_cZ[41]/F
10.813	0.000	tNET	RR	1	R35C57[0][B]	Mdu/u_mdu/reg0_Z[41]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	577	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R35C57[0][B]	Mdu/u_mdu/reg0_Z[41]/CLK
11.683	-0.200	tUnc				Mdu/u_mdu/reg0_Z[41]
11.648	-0.035	tSu		1	R35C57[0][B]	Mdu/u_mdu/reg0_Z[41]

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 3.576, 40.045%; route: 5.122, 57.357%; tC2Q: 0.232, 2.598%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path25

Path Summary:

Slack	0.864
Data Arrival Time	10.784
Data Required Time	11.648
From	Mdu/u_mdu/reg0_fast_Z[4]
To	memq_memq_0_15
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.683	0.683	tINS	RR	577	IOT48[A]	clk_ibuf/O
1.883	1.201	tNET	RR	1	R50C55[2][A]	Mdu/u_mdu/reg0_fast_Z[4]/CLK
2.115	0.232	tC2Q	RF	7	R50C55[2][A]	Mdu/u_mdu/reg0_fast_Z[4]/Q
3.349	1.234	tNET	FF	1	R35C61[0][B]	Mdu/u_mdu/reg0_neg_axb_4_par_0_cp_1_cZ/I2
3.866	0.517	tINS	FF	1	R35C61[0][B]	Mdu/u_mdu/reg0_neg_axb_4_par_0_cp_1_cZ/F
4.821	0.955	tNET	FF	2	R30C56[1][B]	Mdu/u_mdu/reg0_neg_axb_4_par_cp_1_0/I0
5.391	0.570	tINS	FR	1	R30C56[1][B]	Mdu/u_mdu/reg0_neg_axb_4_par_cp_1_0/COUT
5.391	0.000	tNET	RR	2	R30C56[2][A]	Mdu/u_mdu/reg0_neg_axb_8_par_cp_0_0/CIN
5.426	0.035	tINS	RF	1	R30C56[2][A]	Mdu/u_mdu/reg0_neg_axb_8_par_cp_0_0/COUT
5.426	0.000	tNET	FF	2	R30C56[2][B]	Mdu/u_mdu/reg0_neg_axb_12_par_cp_0_0/CIN
5.461	0.035	tINS	FF	1	R30C56[2][B]	Mdu/u_mdu/reg0_neg_axb_12_par_cp_0_0/COUT
5.461	0.000	tNET	FF	2	R30C57[0][A]	Mdu/u_mdu/reg0_neg_axb_16_par_cp_0_0/CIN
5.496	0.035	tINS	FF	1	R30C57[0][A]	Mdu/u_mdu/reg0_neg_axb_16_par_cp_0_0/COUT
5.496	0.000	tNET	FF	2	R30C57[0][B]	Mdu/u_mdu/reg0_neg_axb_19_par_cp_0/CIN
5.532	0.035	tINS	FF	1	R30C57[0][B]	Mdu/u_mdu/reg0_neg_axb_19_par_cp_0/COUT
5.532	0.000	tNET	FF	2	R30C57[1][A]	Mdu/u_mdu/reg0_neg_axb_23_par_cp_0/CIN
5.567	0.035	tINS	FF	1	R30C57[1][A]	Mdu/u_mdu/reg0_neg_axb_23_par_cp_0/COUT
5.567	0.000	tNET	FF	2	R30C57[1][B]	Mdu/u_mdu/reg0_neg_axb_27_par_cp_0/CIN
5.602	0.035	tINS	FF	1	R30C57[1][B]	Mdu/u_mdu/reg0_neg_axb_27_par_cp_0/COUT
5.602	0.000	tNET	FF	2	R30C57[2][A]	Mdu/u_mdu/reg0_neg_axb_31_par_cp_0/CIN
5.637	0.035	tINS	FF	1	R30C57[2][A]	Mdu/u_mdu/reg0_neg_axb_31_par_cp_0/COUT
5.637	0.000	tNET	FF	2	R30C57[2][B]	Mdu/u_mdu/reg0_neg_axb_34_par_1/CIN
5.672	0.035	tINS	FF	1	R30C57[2][B]	Mdu/u_mdu/reg0_neg_axb_34_par_1/COUT
5.672	0.000	tNET	FF	2	R30C58[0][A]	Mdu/u_mdu/reg0_neg_axb_38_par_1/CIN
5.708	0.035	tINS	FF	1	R30C58[0][A]	Mdu/u_mdu/reg0_neg_axb_38_par_1/COUT
5.708	0.000	tNET	FF	2	R30C58[0][B]	Mdu/u_mdu/reg0_neg_axb_42_par_1/CIN
5.743	0.035	tINS	FF	1	R30C58[0][B]	Mdu/u_mdu/reg0_neg_axb_42_par_1/COUT
5.743	0.000	tNET	FF	2	R30C58[1][A]	Mdu/u_mdu/reg0_neg_axb_46_par_1/CIN
5.778	0.035	tINS	FF	1	R30C58[1][A]	Mdu/u_mdu/reg0_neg_axb_46_par_1/COUT
5.778	0.000	tNET	FF	2	R30C58[1][B]	Mdu/u_mdu/reg0_neg_axb_50_par_1/CIN
5.813	0.035	tINS	FF	1	R30C58[1][B]	Mdu/u_mdu/reg0_neg_axb_50_par_1/COUT
5.813	0.000	tNET	FF	2	R30C58[2][A]	Mdu/u_mdu/reg0_neg_cry_54_0/CIN
5.848	0.035	tINS	FF	1	R30C58[2][A]	Mdu/u_mdu/reg0_neg_cry_54_0/COUT
5.848	0.000	tNET	FF	2	R30C58[2][B]	Mdu/u_mdu/reg0_neg_cry_55_0/CIN
5.884	0.035	tINS	FF	1	R30C58[2][B]	Mdu/u_mdu/reg0_neg_cry_55_0/COUT
5.884	0.000	tNET	FF	2	R30C59[0][A]	Mdu/u_mdu/reg0_neg_cry_56_0/CIN
5.919	0.035	tINS	FF	1	R30C59[0][A]	Mdu/u_mdu/reg0_neg_cry_56_0/COUT
5.919	0.000	tNET	FF	2	R30C59[0][B]	Mdu/u_mdu/reg0_neg_cry_57_0/CIN
5.954	0.035	tINS	FF	1	R30C59[0][B]	Mdu/u_mdu/reg0_neg_cry_57_0/COUT
5.954	0.000	tNET	FF	2	R30C59[1][A]	Mdu/u_mdu/reg0_neg_cry_58_0/CIN
5.989	0.035	tINS	FF	1	R30C59[1][A]	Mdu/u_mdu/reg0_neg_cry_58_0/COUT
5.989	0.000	tNET	FF	2	R30C59[1][B]	Mdu/u_mdu/reg0_neg_cry_59_0/CIN
6.024	0.035	tINS	FF	1	R30C59[1][B]	Mdu/u_mdu/reg0_neg_cry_59_0/COUT
6.024	0.000	tNET	FF	2	R30C59[2][A]	Mdu/u_mdu/reg0_neg_cry_60_0/CIN
6.060	0.035	tINS	FF	1	R30C59[2][A]	Mdu/u_mdu/reg0_neg_cry_60_0/COUT
6.060	0.000	tNET	FF	2	R30C59[2][B]	Mdu/u_mdu/reg0_neg_cry_61_0/CIN
6.095	0.035	tINS	FF	1	R30C59[2][B]	Mdu/u_mdu/reg0_neg_cry_61_0/COUT
6.095	0.000	tNET	FF	2	R30C60[0][A]	Mdu/u_mdu/reg0_neg_cry_62_0/CIN
6.130	0.035	tINS	FF	1	R30C60[0][A]	Mdu/u_mdu/reg0_neg_cry_62_0/COUT
6.130	0.000	tNET	FF	2	R30C60[0][B]	Mdu/u_mdu/reg0_neg_s_63_0/CIN
6.600	0.470	tINS	FF	1	R30C60[0][B]	Mdu/u_mdu/reg0_neg_s_63_0/SUM
7.478	0.878	tNET	FF	1	R38C56[3][A]	Mdu/u_mdu/reg0_post_swap_2[31]/I2
8.033	0.555	tINS	FF	1	R38C56[3][A]	Mdu/u_mdu/reg0_post_swap_2[31]/F
8.033	0.000	tNET	FF	1	R38C56[3][A]	Mdu/u_mdu/reg0_post_swap_4[31]/I0
8.136	0.103	tINS	FF	2	R38C56[3][A]	Mdu/u_mdu/reg0_post_swap_4[31]/O
9.050	0.913	tNET	FF	1	R38C56[2][A]	Mdu/u_mdu/reg0_post_swap_5[31]/I1
9.620	0.570	tINS	FR	1	R38C56[2][A]	Mdu/u_mdu/reg0_post_swap_5[31]/F
9.792	0.172	tNET	RR	1	R37C56[1][B]	Mdu/u_mdu/res0_cZ[31]/I1
10.163	0.371	tINS	RF	3	R37C56[1][B]	Mdu/u_mdu/res0_cZ[31]/F
10.784	0.621	tNET	FF	1	BSRAM_R36[20]	memq_memq_0_15/DI1

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	577	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	BSRAM_R36[20]	memq_memq_0_15/CLKA
11.683	-0.200	tUnc				memq_memq_0_15
11.648	-0.035	tSu		1	BSRAM_R36[20]	memq_memq_0_15

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 3.895, 43.762%; route: 4.774, 53.632%; tC2Q: 0.232, 2.606%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Hold Analysis Report

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	0.202
Data Arrival Time	2.029
Data Required Time	1.826
From	u_la0_top/u_ao_mem_ctrl/data_reg_Z[86]
To	u_la0_top/u_ao_mem_ctrl/mem_mem_0_43
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	577	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R12C14[2][B]	u_la0_top/u_ao_mem_ctrl/data_reg_Z[86]/CLK
1.779	0.202	tC2Q	RR	1	R12C14[2][B]	u_la0_top/u_ao_mem_ctrl/data_reg_Z[86]/Q
2.029	0.249	tNET	RR	1	BSRAM_R10[3]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_43/DI0

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	577	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	BSRAM_R10[3]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_43/CLKA
1.577	0.000	tUnc				u_la0_top/u_ao_mem_ctrl/mem_mem_0_43
1.826	0.249	tHld		1	BSRAM_R10[3]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_43

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.249, 55.230%; tC2Q: 0.202, 44.770%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path2

Path Summary:

Slack	0.216
Data Arrival Time	1.912
Data Required Time	1.695
From	cnt_Z[10]
To	memq_memq_0_1
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	577	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R38C44[0][A]	cnt_Z[10]/CLK
1.779	0.202	tC2Q	RR	34	R38C44[0][A]	cnt_Z[10]/Q
1.912	0.132	tNET	RR	1	BSRAM_R36[13]	memq_memq_0_1/ADA11

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	577	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	BSRAM_R36[13]	memq_memq_0_1/CLKA
1.577	0.000	tUnc				memq_memq_0_1
1.695	0.118	tHld		1	BSRAM_R36[13]	memq_memq_0_1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.132, 39.581%; tC2Q: 0.202, 60.419%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path3

Path Summary:

Slack	0.233
Data Arrival Time	1.929
Data Required Time	1.695
From	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[12]
To	u_la0_top/u_ao_mem_ctrl/mem_mem_0_15
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	577	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R11C9[0][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[12]/CLK
1.779	0.202	tC2Q	RR	67	R11C9[0][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[12]/Q
1.929	0.149	tNET	RR	1	BSRAM_R10[1]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_15/ADA13

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	577	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	BSRAM_R10[1]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_15/CLKA
1.577	0.000	tUnc				u_la0_top/u_ao_mem_ctrl/mem_mem_0_15
1.695	0.118	tHld		1	BSRAM_R10[1]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_15

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.149, 42.505%; tC2Q: 0.202, 57.495%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path4

Path Summary:

Slack	0.334
Data Arrival Time	1.923
Data Required Time	1.588
From	Mdu/u_mdu/reg1_Z[31]
To	Mdu/u_mdu/rs1_mul_Z[31]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	577	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R31C59[2][B]	Mdu/u_mdu/reg1_Z[31]/CLK
1.779	0.202	tC2Q	RR	36	R31C59[2][B]	Mdu/u_mdu/reg1_Z[31]/Q
1.923	0.143	tNET	RR	1	R31C59[0][A]	Mdu/u_mdu/rs1_mul_Z[31]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	577	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R31C59[0][A]	Mdu/u_mdu/rs1_mul_Z[31]/CLK
1.577	0.000	tUnc				Mdu/u_mdu/rs1_mul_Z[31]
1.588	0.011	tHld		1	R31C59[0][A]	Mdu/u_mdu/rs1_mul_Z[31]

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.143, 41.463%; tC2Q: 0.202, 58.537%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path5

Path Summary:

Slack	0.334
Data Arrival Time	2.030
Data Required Time	1.695
From	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0]
To	u_la0_top/u_ao_mem_ctrl/mem_mem_0_15
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	577	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R9C7[1][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0]/CLK
1.779	0.202	tC2Q	RR	67	R9C7[1][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0]/Q
2.030	0.250	tNET	RR	1	BSRAM_R10[1]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_15/ADA1

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	577	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	BSRAM_R10[1]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_15/CLKA
1.577	0.000	tUnc				u_la0_top/u_ao_mem_ctrl/mem_mem_0_15
1.695	0.118	tHld		1	BSRAM_R10[1]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_15

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.250, 55.321%; tC2Q: 0.202, 44.679%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path6

Path Summary:

Slack	0.335
Data Arrival Time	2.162
Data Required Time	1.826
From	u_la0_top/u_ao_mem_ctrl/data_reg_Z[87]
To	u_la0_top/u_ao_mem_ctrl/mem_mem_0_43
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	577	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R11C11[0][B]	u_la0_top/u_ao_mem_ctrl/data_reg_Z[87]/CLK
1.779	0.202	tC2Q	RR	1	R11C11[0][B]	u_la0_top/u_ao_mem_ctrl/data_reg_Z[87]/Q
2.162	0.382	tNET	RR	1	BSRAM_R10[3]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_43/DI1

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	577	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	BSRAM_R10[3]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_43/CLKA
1.577	0.000	tUnc				u_la0_top/u_ao_mem_ctrl/mem_mem_0_43
1.826	0.249	tHld		1	BSRAM_R10[3]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_43

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.382, 65.434%; tC2Q: 0.202, 34.566%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path7

Path Summary:

Slack	0.335
Data Arrival Time	2.162
Data Required Time	1.826
From	u_la0_top/u_ao_mem_ctrl/data_reg_Z[77]
To	u_la0_top/u_ao_mem_ctrl/mem_mem_0_38
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	577	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R13C12[1][B]	u_la0_top/u_ao_mem_ctrl/data_reg_Z[77]/CLK
1.779	0.202	tC2Q	RR	1	R13C12[1][B]	u_la0_top/u_ao_mem_ctrl/data_reg_Z[77]/Q
2.162	0.382	tNET	RR	1	BSRAM_R10[2]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_38/DI1

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	577	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	BSRAM_R10[2]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_38/CLKA
1.577	0.000	tUnc				u_la0_top/u_ao_mem_ctrl/mem_mem_0_38
1.826	0.249	tHld		1	BSRAM_R10[2]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_38

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.382, 65.434%; tC2Q: 0.202, 34.566%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path8

Path Summary:

Slack	0.335
Data Arrival Time	2.162
Data Required Time	1.826
From	u_la0_top/u_ao_mem_ctrl/data_reg_Z[76]
To	u_la0_top/u_ao_mem_ctrl/mem_mem_0_38
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	577	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R13C12[1][A]	u_la0_top/u_ao_mem_ctrl/data_reg_Z[76]/CLK
1.779	0.202	tC2Q	RR	1	R13C12[1][A]	u_la0_top/u_ao_mem_ctrl/data_reg_Z[76]/Q
2.162	0.382	tNET	RR	1	BSRAM_R10[2]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_38/DI0

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	577	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	BSRAM_R10[2]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_38/CLKA
1.577	0.000	tUnc				u_la0_top/u_ao_mem_ctrl/mem_mem_0_38
1.826	0.249	tHld		1	BSRAM_R10[2]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_38

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.382, 65.434%; tC2Q: 0.202, 34.566%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path9

Path Summary:

Slack	0.338
Data Arrival Time	2.034
Data Required Time	1.695
From	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[4]
To	u_la0_top/u_ao_mem_ctrl/mem_mem_0_15
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	577	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R9C9[0][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[4]/CLK
1.779	0.202	tC2Q	RR	67	R9C9[0][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[4]/Q
2.034	0.254	tNET	RR	1	BSRAM_R10[1]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_15/ADA5

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	577	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	BSRAM_R10[1]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_15/CLKA
1.577	0.000	tUnc				u_la0_top/u_ao_mem_ctrl/mem_mem_0_15
1.695	0.118	tHld		1	BSRAM_R10[1]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_15

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.254, 55.710%; tC2Q: 0.202, 44.290%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path10

Path Summary:

Slack	0.339
Data Arrival Time	2.035
Data Required Time	1.695
From	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[5]
To	u_la0_top/u_ao_mem_ctrl/mem_mem_0_15
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	577	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R12C8[1][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[5]/CLK
1.779	0.202	tC2Q	RR	67	R12C8[1][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[5]/Q
2.035	0.255	tNET	RR	1	BSRAM_R10[1]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_15/ADA6

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	577	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	BSRAM_R10[1]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_15/CLKA
1.577	0.000	tUnc				u_la0_top/u_ao_mem_ctrl/mem_mem_0_15
1.695	0.118	tHld		1	BSRAM_R10[1]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_15

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.255, 55.828%; tC2Q: 0.202, 44.172%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path11

Path Summary:

Slack	0.341
Data Arrival Time	2.036
Data Required Time	1.695
From	cnt_Z[8]
To	memr_memr_0_14
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	577	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R38C43[2][A]	cnt_Z[8]/CLK
1.779	0.202	tC2Q	RR	34	R38C43[2][A]	cnt_Z[8]/Q
2.036	0.257	tNET	RR	1	BSRAM_R36[12]	memr_memr_0_14/ADA9

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	577	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	BSRAM_R36[12]	memr_memr_0_14/CLKA
1.577	0.000	tUnc				memr_memr_0_14
1.695	0.118	tHld		1	BSRAM_R36[12]	memr_memr_0_14

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.257, 55.959%; tC2Q: 0.202, 44.041%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path12

Path Summary:

Slack	0.344
Data Arrival Time	2.040
Data Required Time	1.695
From	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[6]
To	u_la0_top/u_ao_mem_ctrl/mem_mem_0_15
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	577	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R12C8[1][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[6]/CLK
1.779	0.202	tC2Q	RR	67	R12C8[1][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[6]/Q
2.040	0.260	tNET	RR	1	BSRAM_R10[1]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_15/ADA7

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	577	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	BSRAM_R10[1]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_15/CLKA
1.577	0.000	tUnc				u_la0_top/u_ao_mem_ctrl/mem_mem_0_15
1.695	0.118	tHld		1	BSRAM_R10[1]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_15

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.260, 56.295%; tC2Q: 0.202, 43.705%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path13

Path Summary:

Slack	0.345
Data Arrival Time	2.040
Data Required Time	1.695
From	cnt_Z[1]
To	memr_memr_0_14
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	577	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R38C42[1][B]	cnt_Z[1]/CLK
1.779	0.202	tC2Q	RR	34	R38C42[1][B]	cnt_Z[1]/Q
2.040	0.261	tNET	RR	1	BSRAM_R36[12]	memr_memr_0_14/ADA2

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	577	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	BSRAM_R36[12]	memr_memr_0_14/CLKA
1.577	0.000	tUnc				memr_memr_0_14
1.695	0.118	tHld		1	BSRAM_R36[12]	memr_memr_0_14

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.261, 56.337%; tC2Q: 0.202, 43.663%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path14

Path Summary:

Slack	0.350
Data Arrival Time	2.045
Data Required Time	1.695
From	cnt_Z[8]
To	memq_memq_0_1
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	577	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R38C43[2][A]	cnt_Z[8]/CLK
1.779	0.202	tC2Q	RR	34	R38C43[2][A]	cnt_Z[8]/Q
2.045	0.266	tNET	RR	1	BSRAM_R36[13]	memq_memq_0_1/ADA9

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	577	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	BSRAM_R36[13]	memq_memq_0_1/CLKA
1.577	0.000	tUnc				memq_memq_0_1
1.695	0.118	tHld		1	BSRAM_R36[13]	memq_memq_0_1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.266, 56.822%; tC2Q: 0.202, 43.178%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path15

Path Summary:

Slack	0.352
Data Arrival Time	2.047
Data Required Time	1.695
From	cnt_Z[12]
To	memq_memq_0_1
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	577	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R38C44[1][A]	cnt_Z[12]/CLK
1.779	0.202	tC2Q	RR	34	R38C44[1][A]	cnt_Z[12]/Q
2.047	0.268	tNET	RR	1	BSRAM_R36[13]	memq_memq_0_1/ADA13

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	577	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	BSRAM_R36[13]	memq_memq_0_1/CLKA
1.577	0.000	tUnc				memq_memq_0_1
1.695	0.118	tHld		1	BSRAM_R36[13]	memq_memq_0_1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.268, 56.986%; tC2Q: 0.202, 43.014%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path16

Path Summary:

Slack	0.352
Data Arrival Time	2.047
Data Required Time	1.695
From	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[2]
To	u_la0_top/u_ao_mem_ctrl/mem_mem_0_15
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	577	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R9C7[2][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[2]/CLK
1.779	0.202	tC2Q	RR	67	R9C7[2][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[2]/Q
2.047	0.268	tNET	RR	1	BSRAM_R10[1]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_15/ADA3

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	577	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	BSRAM_R10[1]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_15/CLKA
1.577	0.000	tUnc				u_la0_top/u_ao_mem_ctrl/mem_mem_0_15
1.695	0.118	tHld		1	BSRAM_R10[1]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_15

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.268, 56.991%; tC2Q: 0.202, 43.009%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path17

Path Summary:

Slack	0.353
Data Arrival Time	2.048
Data Required Time	1.695
From	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[9]
To	u_la0_top/u_ao_mem_ctrl/mem_mem_0_15
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	577	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R11C7[2][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[9]/CLK
1.779	0.202	tC2Q	RR	67	R11C7[2][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[9]/Q
2.048	0.269	tNET	RR	1	BSRAM_R10[1]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_15/ADA10

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	577	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	BSRAM_R10[1]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_15/CLKA
1.577	0.000	tUnc				u_la0_top/u_ao_mem_ctrl/mem_mem_0_15
1.695	0.118	tHld		1	BSRAM_R10[1]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_15

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.269, 57.102%; tC2Q: 0.202, 42.898%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path18

Path Summary:

Slack	0.354
Data Arrival Time	2.049
Data Required Time	1.695
From	cnt_1_Z[3]
To	memr_memr_0_14
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	577	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R39C42[2][B]	cnt_1_Z[3]/CLK
1.779	0.202	tC2Q	RR	33	R39C42[2][B]	cnt_1_Z[3]/Q
2.049	0.270	tNET	RR	1	BSRAM_R36[12]	memr_memr_0_14/ADB4

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	577	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	BSRAM_R36[12]	memr_memr_0_14/CLKB
1.577	0.000	tUnc				memr_memr_0_14
1.695	0.118	tHld		1	BSRAM_R36[12]	memr_memr_0_14

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.270, 57.208%; tC2Q: 0.202, 42.792%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path19

Path Summary:

Slack	0.354
Data Arrival Time	2.050
Data Required Time	1.695
From	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[7]
To	u_la0_top/u_ao_mem_ctrl/mem_mem_0_15
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	577	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R9C9[0][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[7]/CLK
1.779	0.202	tC2Q	RR	67	R9C9[0][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[7]/Q
2.050	0.270	tNET	RR	1	BSRAM_R10[1]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_15/ADA8

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	577	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	BSRAM_R10[1]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_15/CLKA
1.577	0.000	tUnc				u_la0_top/u_ao_mem_ctrl/mem_mem_0_15
1.695	0.118	tHld		1	BSRAM_R10[1]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_15

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.270, 57.213%; tC2Q: 0.202, 42.787%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path20

Path Summary:

Slack	0.354
Data Arrival Time	2.050
Data Required Time	1.695
From	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[3]
To	u_la0_top/u_ao_mem_ctrl/mem_mem_0_10
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	577	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R9C7[2][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[3]/CLK
1.779	0.202	tC2Q	RR	67	R9C7[2][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[3]/Q
2.050	0.270	tNET	RR	1	BSRAM_R10[0]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_10/ADA4

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	577	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	BSRAM_R10[0]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_10/CLKA
1.577	0.000	tUnc				u_la0_top/u_ao_mem_ctrl/mem_mem_0_10
1.695	0.118	tHld		1	BSRAM_R10[0]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_10

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.270, 57.213%; tC2Q: 0.202, 42.787%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path21

Path Summary:

Slack	0.354
Data Arrival Time	2.050
Data Required Time	1.695
From	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[10]
To	u_la0_top/u_ao_mem_ctrl/mem_mem_0_10
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	577	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R11C7[2][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[10]/CLK
1.779	0.202	tC2Q	RR	67	R11C7[2][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[10]/Q
2.050	0.270	tNET	RR	1	BSRAM_R10[0]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_10/ADA11

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	577	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	BSRAM_R10[0]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_10/CLKA
1.577	0.000	tUnc				u_la0_top/u_ao_mem_ctrl/mem_mem_0_10
1.695	0.118	tHld		1	BSRAM_R10[0]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_10

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.270, 57.218%; tC2Q: 0.202, 42.782%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path22

Path Summary:

Slack	0.355
Data Arrival Time	2.051
Data Required Time	1.695
From	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[3]
To	u_la0_top/u_ao_mem_ctrl/mem_mem_0_15
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	577	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R9C7[2][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[3]/CLK
1.779	0.202	tC2Q	RR	67	R9C7[2][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[3]/Q
2.051	0.271	tNET	RR	1	BSRAM_R10[1]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_15/ADA4

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	577	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	BSRAM_R10[1]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_15/CLKA
1.577	0.000	tUnc				u_la0_top/u_ao_mem_ctrl/mem_mem_0_15
1.695	0.118	tHld		1	BSRAM_R10[1]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_15

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.271, 57.319%; tC2Q: 0.202, 42.681%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path23

Path Summary:

Slack	0.357
Data Arrival Time	2.052
Data Required Time	1.695
From	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[10]
To	u_la0_top/u_ao_mem_ctrl/mem_mem_0_15
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	577	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R11C7[2][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[10]/CLK
1.779	0.202	tC2Q	RR	67	R11C7[2][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[10]/Q
2.052	0.273	tNET	RR	1	BSRAM_R10[1]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_15/ADA11

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	577	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	BSRAM_R10[1]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_15/CLKA
1.577	0.000	tUnc				u_la0_top/u_ao_mem_ctrl/mem_mem_0_15
1.695	0.118	tHld		1	BSRAM_R10[1]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_15

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.273, 57.429%; tC2Q: 0.202, 42.571%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path24

Path Summary:

Slack	0.357
Data Arrival Time	2.052
Data Required Time	1.695
From	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8]
To	u_la0_top/u_ao_mem_ctrl/mem_mem_0_38
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	577	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R7C11[0][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8]/CLK
1.779	0.202	tC2Q	RR	67	R7C11[0][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8]/Q
2.052	0.273	tNET	RR	1	BSRAM_R10[2]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_38/ADA9

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	577	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	BSRAM_R10[2]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_38/CLKA
1.577	0.000	tUnc				u_la0_top/u_ao_mem_ctrl/mem_mem_0_38
1.695	0.118	tHld		1	BSRAM_R10[2]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_38

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.273, 57.434%; tC2Q: 0.202, 42.566%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path25

Path Summary:

Slack	0.366
Data Arrival Time	2.061
Data Required Time	1.695
From	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[1]
To	u_la0_top/u_ao_mem_ctrl/mem_mem_0_43
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	577	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R9C7[1][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[1]/CLK
1.779	0.202	tC2Q	RR	67	R9C7[1][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[1]/Q
2.061	0.282	tNET	RR	1	BSRAM_R10[3]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_43/ADA2

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	577	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	BSRAM_R10[3]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_43/CLKA
1.577	0.000	tUnc				u_la0_top/u_ao_mem_ctrl/mem_mem_0_43
1.695	0.118	tHld		1	BSRAM_R10[3]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_43

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.282, 58.254%; tC2Q: 0.202, 41.746%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Recovery Analysis Report

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	1.643
Data Arrival Time	10.005
Data Required Time	11.648
From	u_la0_top/rst_ao_Z
To	u_la0_top/triger_level_cnt_Z[0]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.688	0.688	tINS	FF	577	IOT48[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R9C2[2][B]	u_la0_top/rst_ao_Z/CLK
7.148	0.232	tC2Q	FF	49	R9C2[2][B]	u_la0_top/rst_ao_Z/Q
10.005	2.857	tNET	FF	1	R9C9[2][A]	u_la0_top/triger_level_cnt_Z[0]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	577	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R9C9[2][A]	u_la0_top/triger_level_cnt_Z[0]/CLK
11.683	-0.200	tUnc				u_la0_top/triger_level_cnt_Z[0]
11.648	-0.035	tSu		1	R9C9[2][A]	u_la0_top/triger_level_cnt_Z[0]

Path Statistics:

Clock Skew	-0.033
Setup Relationship	5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.857, 92.490%; tC2Q: 0.232, 7.510%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path2

Path Summary:

Slack	1.643
Data Arrival Time	10.005
Data Required Time	11.648
From	u_la0_top/rst_ao_Z
To	u_la0_top/triger_level_cnt_Z[2]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.688	0.688	tINS	FF	577	IOT48[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R9C2[2][B]	u_la0_top/rst_ao_Z/CLK
7.148	0.232	tC2Q	FF	49	R9C2[2][B]	u_la0_top/rst_ao_Z/Q
10.005	2.857	tNET	FF	1	R12C9[2][B]	u_la0_top/triger_level_cnt_Z[2]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	577	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R12C9[2][B]	u_la0_top/triger_level_cnt_Z[2]/CLK
11.683	-0.200	tUnc				u_la0_top/triger_level_cnt_Z[2]
11.648	-0.035	tSu		1	R12C9[2][B]	u_la0_top/triger_level_cnt_Z[2]

Path Statistics:

Clock Skew	-0.033
Setup Relationship	5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.857, 92.490%; tC2Q: 0.232, 7.510%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path3

Path Summary:

Slack	1.643
Data Arrival Time	10.005
Data Required Time	11.648
From	u_la0_top/rst_ao_Z
To	u_la0_top/capture_window_sel[3]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.688	0.688	tINS	FF	577	IOT48[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R9C2[2][B]	u_la0_top/rst_ao_Z/CLK
7.148	0.232	tC2Q	FF	49	R9C2[2][B]	u_la0_top/rst_ao_Z/Q
10.005	2.857	tNET	FF	1	R9C2[1][B]	u_la0_top/capture_window_sel[3]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	577	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R9C2[1][B]	u_la0_top/capture_window_sel[3]/CLK
11.683	-0.200	tUnc				u_la0_top/capture_window_sel[3]
11.648	-0.035	tSu		1	R9C2[1][B]	u_la0_top/capture_window_sel[3]

Path Statistics:

Clock Skew	-0.033
Setup Relationship	5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.857, 92.490%; tC2Q: 0.232, 7.510%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path4

Path Summary:

Slack	1.643
Data Arrival Time	10.005
Data Required Time	11.648
From	u_la0_top/rst_ao_Z
To	u_la0_top/internal_reg_force_triger_syn_Z[0]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.688	0.688	tINS	FF	577	IOT48[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R9C2[2][B]	u_la0_top/rst_ao_Z/CLK
7.148	0.232	tC2Q	FF	49	R9C2[2][B]	u_la0_top/rst_ao_Z/Q
10.005	2.857	tNET	FF	1	R12C3[0][A]	u_la0_top/internal_reg_force_triger_syn_Z[0]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	577	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R12C3[0][A]	u_la0_top/internal_reg_force_triger_syn_Z[0]/CLK
11.683	-0.200	tUnc				u_la0_top/internal_reg_force_triger_syn_Z[0]
11.648	-0.035	tSu		1	R12C3[0][A]	u_la0_top/internal_reg_force_triger_syn_Z[0]

Path Statistics:

Clock Skew	-0.033
Setup Relationship	5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.857, 92.490%; tC2Q: 0.232, 7.510%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path5

Path Summary:

Slack	1.643
Data Arrival Time	10.005
Data Required Time	11.648
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_length_Z[12]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.688	0.688	tINS	FF	577	IOT48[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R9C2[2][B]	u_la0_top/rst_ao_Z/CLK
7.148	0.232	tC2Q	FF	49	R9C2[2][B]	u_la0_top/rst_ao_Z/Q
10.005	2.857	tNET	FF	1	R2C4[2][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[12]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	577	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R2C4[2][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[12]/CLK
11.683	-0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_length_Z[12]
11.648	-0.035	tSu		1	R2C4[2][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[12]

Path Statistics:

Clock Skew	-0.033
Setup Relationship	5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.857, 92.490%; tC2Q: 0.232, 7.510%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path6

Path Summary:

Slack	1.643
Data Arrival Time	10.005
Data Required Time	11.648
From	u_la0_top/rst_ao_Z
To	u_la0_top/internal_reg_start_syn_Z[0]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.688	0.688	tINS	FF	577	IOT48[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R9C2[2][B]	u_la0_top/rst_ao_Z/CLK
7.148	0.232	tC2Q	FF	49	R9C2[2][B]	u_la0_top/rst_ao_Z/Q
10.005	2.857	tNET	FF	1	R6C11[2][A]	u_la0_top/internal_reg_start_syn_Z[0]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	577	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R6C11[2][A]	u_la0_top/internal_reg_start_syn_Z[0]/CLK
11.683	-0.200	tUnc				u_la0_top/internal_reg_start_syn_Z[0]
11.648	-0.035	tSu		1	R6C11[2][A]	u_la0_top/internal_reg_start_syn_Z[0]

Path Statistics:

Clock Skew	-0.033
Setup Relationship	5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.857, 92.490%; tC2Q: 0.232, 7.510%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path7

Path Summary:

Slack	1.643
Data Arrival Time	10.005
Data Required Time	11.648
From	u_la0_top/rst_ao_Z
To	u_la0_top/internal_reg_start_dly_Z[0]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.688	0.688	tINS	FF	577	IOT48[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R9C2[2][B]	u_la0_top/rst_ao_Z/CLK
7.148	0.232	tC2Q	FF	49	R9C2[2][B]	u_la0_top/rst_ao_Z/Q
10.005	2.857	tNET	FF	1	R3C7[0][B]	u_la0_top/internal_reg_start_dly_Z[0]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	577	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R3C7[0][B]	u_la0_top/internal_reg_start_dly_Z[0]/CLK
11.683	-0.200	tUnc				u_la0_top/internal_reg_start_dly_Z[0]
11.648	-0.035	tSu		1	R3C7[0][B]	u_la0_top/internal_reg_start_dly_Z[0]

Path Statistics:

Clock Skew	-0.033
Setup Relationship	5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.857, 92.490%; tC2Q: 0.232, 7.510%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path8

Path Summary:

Slack	1.643
Data Arrival Time	10.005
Data Required Time	11.648
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.688	0.688	tINS	FF	577	IOT48[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R9C2[2][B]	u_la0_top/rst_ao_Z/CLK
7.148	0.232	tC2Q	FF	49	R9C2[2][B]	u_la0_top/rst_ao_Z/Q
10.005	2.857	tNET	FF	1	R9C10[1][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	577	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R9C10[1][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z/CLK
11.683	-0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z
11.648	-0.035	tSu		1	R9C10[1][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z

Path Statistics:

Clock Skew	-0.033
Setup Relationship	5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.857, 92.490%; tC2Q: 0.232, 7.510%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path9

Path Summary:

Slack	1.643
Data Arrival Time	10.005
Data Required Time	11.648
From	u_la0_top/rst_ao_Z
To	u_la0_top/capture_window_sel_Z[2]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.688	0.688	tINS	FF	577	IOT48[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R9C2[2][B]	u_la0_top/rst_ao_Z/CLK
7.148	0.232	tC2Q	FF	49	R9C2[2][B]	u_la0_top/rst_ao_Z/Q
10.005	2.857	tNET	FF	1	R3C7[2][A]	u_la0_top/capture_window_sel_Z[2]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	577	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R3C7[2][A]	u_la0_top/capture_window_sel_Z[2]/CLK
11.683	-0.200	tUnc				u_la0_top/capture_window_sel_Z[2]
11.648	-0.035	tSu		1	R3C7[2][A]	u_la0_top/capture_window_sel_Z[2]

Path Statistics:

Clock Skew	-0.033
Setup Relationship	5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.857, 92.490%; tC2Q: 0.232, 7.510%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path10

Path Summary:

Slack	1.643
Data Arrival Time	10.005
Data Required Time	11.648
From	u_la0_top/rst_ao_Z
To	u_la0_top/capture_end_dly_Z
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.688	0.688	tINS	FF	577	IOT48[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R9C2[2][B]	u_la0_top/rst_ao_Z/CLK
7.148	0.232	tC2Q	FF	49	R9C2[2][B]	u_la0_top/rst_ao_Z/Q
10.005	2.857	tNET	FF	1	R11C9[2][A]	u_la0_top/capture_end_dly_Z/PRESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	577	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R11C9[2][A]	u_la0_top/capture_end_dly_Z/CLK
11.683	-0.200	tUnc				u_la0_top/capture_end_dly_Z
11.648	-0.035	tSu		1	R11C9[2][A]	u_la0_top/capture_end_dly_Z

Path Statistics:

Clock Skew	-0.033
Setup Relationship	5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.857, 92.490%; tC2Q: 0.232, 7.510%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path11

Path Summary:

Slack	1.643
Data Arrival Time	10.005
Data Required Time	11.648
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.688	0.688	tINS	FF	577	IOT48[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R9C2[2][B]	u_la0_top/rst_ao_Z/CLK
7.148	0.232	tC2Q	FF	49	R9C2[2][B]	u_la0_top/rst_ao_Z/Q
10.005	2.857	tNET	FF	1	R9C7[1][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	577	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R9C7[1][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0]/CLK
11.683	-0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0]
11.648	-0.035	tSu		1	R9C7[1][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0]

Path Statistics:

Clock Skew	-0.033
Setup Relationship	5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.857, 92.490%; tC2Q: 0.232, 7.510%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path12

Path Summary:

Slack	1.643
Data Arrival Time	10.005
Data Required Time	11.648
From	u_la0_top/rst_ao_Z
To	u_la0_top/capture_window_sel_Z[1]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.688	0.688	tINS	FF	577	IOT48[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R9C2[2][B]	u_la0_top/rst_ao_Z/CLK
7.148	0.232	tC2Q	FF	49	R9C2[2][B]	u_la0_top/rst_ao_Z/Q
10.005	2.857	tNET	FF	1	R3C7[1][B]	u_la0_top/capture_window_sel_Z[1]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	577	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R3C7[1][B]	u_la0_top/capture_window_sel_Z[1]/CLK
11.683	-0.200	tUnc				u_la0_top/capture_window_sel_Z[1]
11.648	-0.035	tSu		1	R3C7[1][B]	u_la0_top/capture_window_sel_Z[1]

Path Statistics:

Clock Skew	-0.033
Setup Relationship	5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.857, 92.490%; tC2Q: 0.232, 7.510%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path13

Path Summary:

Slack	1.643
Data Arrival Time	10.005
Data Required Time	11.648
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_length_Z[4]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.688	0.688	tINS	FF	577	IOT48[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R9C2[2][B]	u_la0_top/rst_ao_Z/CLK
7.148	0.232	tC2Q	FF	49	R9C2[2][B]	u_la0_top/rst_ao_Z/Q
10.005	2.857	tNET	FF	1	R8C9[1][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[4]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	577	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R8C9[1][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[4]/CLK
11.683	-0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_length_Z[4]
11.648	-0.035	tSu		1	R8C9[1][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[4]

Path Statistics:

Clock Skew	-0.033
Setup Relationship	5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.857, 92.490%; tC2Q: 0.232, 7.510%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path14

Path Summary:

Slack	1.643
Data Arrival Time	10.005
Data Required Time	11.648
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_length_Z[3]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.688	0.688	tINS	FF	577	IOT48[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R9C2[2][B]	u_la0_top/rst_ao_Z/CLK
7.148	0.232	tC2Q	FF	49	R9C2[2][B]	u_la0_top/rst_ao_Z/Q
10.005	2.857	tNET	FF	1	R12C3[0][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[3]/PRESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	577	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R12C3[0][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[3]/CLK
11.683	-0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_length_Z[3]
11.648	-0.035	tSu		1	R12C3[0][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[3]

Path Statistics:

Clock Skew	-0.033
Setup Relationship	5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.857, 92.490%; tC2Q: 0.232, 7.510%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path15

Path Summary:

Slack	1.643
Data Arrival Time	10.005
Data Required Time	11.648
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_length_Z[9]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.688	0.688	tINS	FF	577	IOT48[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R9C2[2][B]	u_la0_top/rst_ao_Z/CLK
7.148	0.232	tC2Q	FF	49	R9C2[2][B]	u_la0_top/rst_ao_Z/Q
10.005	2.857	tNET	FF	1	R6C11[2][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[9]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	577	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R6C11[2][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[9]/CLK
11.683	-0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_length_Z[9]
11.648	-0.035	tSu		1	R6C11[2][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[9]

Path Statistics:

Clock Skew	-0.033
Setup Relationship	5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.857, 92.490%; tC2Q: 0.232, 7.510%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path16

Path Summary:

Slack	1.643
Data Arrival Time	10.005
Data Required Time	11.648
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[12]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.688	0.688	tINS	FF	577	IOT48[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R9C2[2][B]	u_la0_top/rst_ao_Z/CLK
7.148	0.232	tC2Q	FF	49	R9C2[2][B]	u_la0_top/rst_ao_Z/Q
10.005	2.857	tNET	FF	1	R11C9[0][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[12]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	577	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R11C9[0][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[12]/CLK
11.683	-0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[12]
11.648	-0.035	tSu		1	R11C9[0][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[12]

Path Statistics:

Clock Skew	-0.033
Setup Relationship	5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.857, 92.490%; tC2Q: 0.232, 7.510%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path17

Path Summary:

Slack	1.643
Data Arrival Time	10.005
Data Required Time	11.648
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[2]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.688	0.688	tINS	FF	577	IOT48[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R9C2[2][B]	u_la0_top/rst_ao_Z/CLK
7.148	0.232	tC2Q	FF	49	R9C2[2][B]	u_la0_top/rst_ao_Z/Q
10.005	2.857	tNET	FF	1	R9C7[2][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[2]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	577	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R9C7[2][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[2]/CLK
11.683	-0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[2]
11.648	-0.035	tSu		1	R9C7[2][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[2]

Path Statistics:

Clock Skew	-0.033
Setup Relationship	5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.857, 92.490%; tC2Q: 0.232, 7.510%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path18

Path Summary:

Slack	1.643
Data Arrival Time	10.005
Data Required Time	11.648
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[1]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.688	0.688	tINS	FF	577	IOT48[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R9C2[2][B]	u_la0_top/rst_ao_Z/CLK
7.148	0.232	tC2Q	FF	49	R9C2[2][B]	u_la0_top/rst_ao_Z/Q
10.005	2.857	tNET	FF	1	R9C7[1][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[1]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	577	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R9C7[1][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[1]/CLK
11.683	-0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[1]
11.648	-0.035	tSu		1	R9C7[1][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[1]

Path Statistics:

Clock Skew	-0.033
Setup Relationship	5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.857, 92.490%; tC2Q: 0.232, 7.510%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path19

Path Summary:

Slack	1.643
Data Arrival Time	10.005
Data Required Time	11.648
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_length_Z[7]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.688	0.688	tINS	FF	577	IOT48[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R9C2[2][B]	u_la0_top/rst_ao_Z/CLK
7.148	0.232	tC2Q	FF	49	R9C2[2][B]	u_la0_top/rst_ao_Z/Q
10.005	2.857	tNET	FF	1	R7C11[1][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[7]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	577	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R7C11[1][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[7]/CLK
11.683	-0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_length_Z[7]
11.648	-0.035	tSu		1	R7C11[1][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[7]

Path Statistics:

Clock Skew	-0.033
Setup Relationship	5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.857, 92.490%; tC2Q: 0.232, 7.510%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path20

Path Summary:

Slack	1.643
Data Arrival Time	10.005
Data Required Time	11.648
From	u_la0_top/rst_ao_Z
To	u_la0_top/trigger_seq_start_Z
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.688	0.688	tINS	FF	577	IOT48[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R9C2[2][B]	u_la0_top/rst_ao_Z/CLK
7.148	0.232	tC2Q	FF	49	R9C2[2][B]	u_la0_top/rst_ao_Z/Q
10.005	2.857	tNET	FF	1	R11C9[1][A]	u_la0_top/trigger_seq_start_Z/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	577	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R11C9[1][A]	u_la0_top/trigger_seq_start_Z/CLK
11.683	-0.200	tUnc				u_la0_top/trigger_seq_start_Z
11.648	-0.035	tSu		1	R11C9[1][A]	u_la0_top/trigger_seq_start_Z

Path Statistics:

Clock Skew	-0.033
Setup Relationship	5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.857, 92.490%; tC2Q: 0.232, 7.510%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path21

Path Summary:

Slack	1.643
Data Arrival Time	10.005
Data Required Time	11.648
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[9]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.688	0.688	tINS	FF	577	IOT48[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R9C2[2][B]	u_la0_top/rst_ao_Z/CLK
7.148	0.232	tC2Q	FF	49	R9C2[2][B]	u_la0_top/rst_ao_Z/Q
10.005	2.857	tNET	FF	1	R11C7[2][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[9]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	577	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R11C7[2][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[9]/CLK
11.683	-0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[9]
11.648	-0.035	tSu		1	R11C7[2][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[9]

Path Statistics:

Clock Skew	-0.033
Setup Relationship	5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.857, 92.490%; tC2Q: 0.232, 7.510%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path22

Path Summary:

Slack	1.643
Data Arrival Time	10.005
Data Required Time	11.648
From	u_la0_top/rst_ao_Z
To	u_la0_top/genblk1.u_ao_match_0/match_sep
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.688	0.688	tINS	FF	577	IOT48[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R9C2[2][B]	u_la0_top/rst_ao_Z/CLK
7.148	0.232	tC2Q	FF	49	R9C2[2][B]	u_la0_top/rst_ao_Z/Q
10.005	2.857	tNET	FF	1	R3C7[0][A]	u_la0_top/genblk1.u_ao_match_0/match_sep/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	577	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R3C7[0][A]	u_la0_top/genblk1.u_ao_match_0/match_sep/CLK
11.683	-0.200	tUnc				u_la0_top/genblk1.u_ao_match_0/match_sep
11.648	-0.035	tSu		1	R3C7[0][A]	u_la0_top/genblk1.u_ao_match_0/match_sep

Path Statistics:

Clock Skew	-0.033
Setup Relationship	5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.857, 92.490%; tC2Q: 0.232, 7.510%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path23

Path Summary:

Slack	1.643
Data Arrival Time	10.005
Data Required Time	11.648
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[3]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.688	0.688	tINS	FF	577	IOT48[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R9C2[2][B]	u_la0_top/rst_ao_Z/CLK
7.148	0.232	tC2Q	FF	49	R9C2[2][B]	u_la0_top/rst_ao_Z/Q
10.005	2.857	tNET	FF	1	R9C7[2][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[3]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	577	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R9C7[2][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[3]/CLK
11.683	-0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[3]
11.648	-0.035	tSu		1	R9C7[2][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[3]

Path Statistics:

Clock Skew	-0.033
Setup Relationship	5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.857, 92.490%; tC2Q: 0.232, 7.510%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path24

Path Summary:

Slack	1.643
Data Arrival Time	10.005
Data Required Time	11.648
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.688	0.688	tINS	FF	577	IOT48[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R9C2[2][B]	u_la0_top/rst_ao_Z/CLK
7.148	0.232	tC2Q	FF	49	R9C2[2][B]	u_la0_top/rst_ao_Z/Q
10.005	2.857	tNET	FF	1	R7C11[0][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	577	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R7C11[0][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8]/CLK
11.683	-0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8]
11.648	-0.035	tSu		1	R7C11[0][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8]

Path Statistics:

Clock Skew	-0.033
Setup Relationship	5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.857, 92.490%; tC2Q: 0.232, 7.510%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path25

Path Summary:

Slack	1.643
Data Arrival Time	10.005
Data Required Time	11.648
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_length_Z[2]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.688	0.688	tINS	FF	577	IOT48[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R9C2[2][B]	u_la0_top/rst_ao_Z/CLK
7.148	0.232	tC2Q	FF	49	R9C2[2][B]	u_la0_top/rst_ao_Z/Q
10.005	2.857	tNET	FF	1	R9C9[2][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[2]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	577	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R9C9[2][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[2]/CLK
11.683	-0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_length_Z[2]
11.648	-0.035	tSu		1	R9C9[2][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[2]

Path Statistics:

Clock Skew	-0.033
Setup Relationship	5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.857, 92.490%; tC2Q: 0.232, 7.510%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Removal Analysis Report

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	6.772
Data Arrival Time	8.560
Data Required Time	1.788
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.677	0.678	tINS	FF	577	IOT48[A]	clk_ibuf/O
6.590	0.913	tNET	FF	1	R9C2[2][B]	u_la0_top/rst_ao_Z/CLK
6.792	0.202	tC2Q	FR	49	R9C2[2][B]	u_la0_top/rst_ao_Z/Q
8.560	1.768	tNET	RR	1	R9C10[1][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	577	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R9C10[1][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z/CLK
1.777	0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z
1.788	0.011	tHld		1	R9C10[1][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.768, 89.747%; tC2Q: 0.202, 10.253%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path2

Path Summary:

Slack	6.772
Data Arrival Time	8.560
Data Required Time	1.788
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_loop_Z
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.677	0.678	tINS	FF	577	IOT48[A]	clk_ibuf/O
6.590	0.913	tNET	FF	1	R9C2[2][B]	u_la0_top/rst_ao_Z/CLK
6.792	0.202	tC2Q	FR	49	R9C2[2][B]	u_la0_top/rst_ao_Z/Q
8.560	1.768	tNET	RR	1	R9C10[2][A]	u_la0_top/u_ao_mem_ctrl/capture_loop_Z/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	577	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R9C10[2][A]	u_la0_top/u_ao_mem_ctrl/capture_loop_Z/CLK
1.777	0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_loop_Z
1.788	0.011	tHld		1	R9C10[2][A]	u_la0_top/u_ao_mem_ctrl/capture_loop_Z

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.768, 89.747%; tC2Q: 0.202, 10.253%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path3

Path Summary:

Slack	6.772
Data Arrival Time	8.560
Data Required Time	1.788
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_length_Z[0]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.677	0.678	tINS	FF	577	IOT48[A]	clk_ibuf/O
6.590	0.913	tNET	FF	1	R9C2[2][B]	u_la0_top/rst_ao_Z/CLK
6.792	0.202	tC2Q	FR	49	R9C2[2][B]	u_la0_top/rst_ao_Z/Q
8.560	1.768	tNET	RR	1	R7C11[2][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[0]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	577	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R7C11[2][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[0]/CLK
1.777	0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_length_Z[0]
1.788	0.011	tHld		1	R7C11[2][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[0]

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.768, 89.747%; tC2Q: 0.202, 10.253%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path4

Path Summary:

Slack	6.772
Data Arrival Time	8.560
Data Required Time	1.788
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_length_Z[1]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.677	0.678	tINS	FF	577	IOT48[A]	clk_ibuf/O
6.590	0.913	tNET	FF	1	R9C2[2][B]	u_la0_top/rst_ao_Z/CLK
6.792	0.202	tC2Q	FR	49	R9C2[2][B]	u_la0_top/rst_ao_Z/Q
8.560	1.768	tNET	RR	1	R9C10[0][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[1]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	577	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R9C10[0][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[1]/CLK
1.777	0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_length_Z[1]
1.788	0.011	tHld		1	R9C10[0][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[1]

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.768, 89.747%; tC2Q: 0.202, 10.253%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path5

Path Summary:

Slack	6.772
Data Arrival Time	8.560
Data Required Time	1.788
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_length_Z[2]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.677	0.678	tINS	FF	577	IOT48[A]	clk_ibuf/O
6.590	0.913	tNET	FF	1	R9C2[2][B]	u_la0_top/rst_ao_Z/CLK
6.792	0.202	tC2Q	FR	49	R9C2[2][B]	u_la0_top/rst_ao_Z/Q
8.560	1.768	tNET	RR	1	R9C9[2][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[2]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	577	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R9C9[2][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[2]/CLK
1.777	0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_length_Z[2]
1.788	0.011	tHld		1	R9C9[2][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[2]

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.768, 89.747%; tC2Q: 0.202, 10.253%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path6

Path Summary:

Slack	6.772
Data Arrival Time	8.560
Data Required Time	1.788
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_length_Z[4]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.677	0.678	tINS	FF	577	IOT48[A]	clk_ibuf/O
6.590	0.913	tNET	FF	1	R9C2[2][B]	u_la0_top/rst_ao_Z/CLK
6.792	0.202	tC2Q	FR	49	R9C2[2][B]	u_la0_top/rst_ao_Z/Q
8.560	1.768	tNET	RR	1	R8C9[1][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[4]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	577	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R8C9[1][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[4]/CLK
1.777	0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_length_Z[4]
1.788	0.011	tHld		1	R8C9[1][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[4]

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.768, 89.747%; tC2Q: 0.202, 10.253%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path7

Path Summary:

Slack	6.772
Data Arrival Time	8.560
Data Required Time	1.788
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_length_Z[5]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.677	0.678	tINS	FF	577	IOT48[A]	clk_ibuf/O
6.590	0.913	tNET	FF	1	R9C2[2][B]	u_la0_top/rst_ao_Z/CLK
6.792	0.202	tC2Q	FR	49	R9C2[2][B]	u_la0_top/rst_ao_Z/Q
8.560	1.768	tNET	RR	1	R8C2[2][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[5]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	577	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R8C2[2][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[5]/CLK
1.777	0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_length_Z[5]
1.788	0.011	tHld		1	R8C2[2][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[5]

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.768, 89.747%; tC2Q: 0.202, 10.253%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path8

Path Summary:

Slack	6.772
Data Arrival Time	8.560
Data Required Time	1.788
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_length_Z[7]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.677	0.678	tINS	FF	577	IOT48[A]	clk_ibuf/O
6.590	0.913	tNET	FF	1	R9C2[2][B]	u_la0_top/rst_ao_Z/CLK
6.792	0.202	tC2Q	FR	49	R9C2[2][B]	u_la0_top/rst_ao_Z/Q
8.560	1.768	tNET	RR	1	R7C11[1][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[7]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	577	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R7C11[1][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[7]/CLK
1.777	0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_length_Z[7]
1.788	0.011	tHld		1	R7C11[1][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[7]

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.768, 89.747%; tC2Q: 0.202, 10.253%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path9

Path Summary:

Slack	6.772
Data Arrival Time	8.560
Data Required Time	1.788
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_length_Z[8]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.677	0.678	tINS	FF	577	IOT48[A]	clk_ibuf/O
6.590	0.913	tNET	FF	1	R9C2[2][B]	u_la0_top/rst_ao_Z/CLK
6.792	0.202	tC2Q	FR	49	R9C2[2][B]	u_la0_top/rst_ao_Z/Q
8.560	1.768	tNET	RR	1	R7C11[1][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[8]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	577	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R7C11[1][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[8]/CLK
1.777	0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_length_Z[8]
1.788	0.011	tHld		1	R7C11[1][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[8]

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.768, 89.747%; tC2Q: 0.202, 10.253%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path10

Path Summary:

Slack	6.772
Data Arrival Time	8.560
Data Required Time	1.788
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_length_Z[9]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.677	0.678	tINS	FF	577	IOT48[A]	clk_ibuf/O
6.590	0.913	tNET	FF	1	R9C2[2][B]	u_la0_top/rst_ao_Z/CLK
6.792	0.202	tC2Q	FR	49	R9C2[2][B]	u_la0_top/rst_ao_Z/Q
8.560	1.768	tNET	RR	1	R6C11[2][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[9]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	577	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R6C11[2][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[9]/CLK
1.777	0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_length_Z[9]
1.788	0.011	tHld		1	R6C11[2][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[9]

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.768, 89.747%; tC2Q: 0.202, 10.253%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path11

Path Summary:

Slack	6.772
Data Arrival Time	8.560
Data Required Time	1.788
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_length_Z[10]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.677	0.678	tINS	FF	577	IOT48[A]	clk_ibuf/O
6.590	0.913	tNET	FF	1	R9C2[2][B]	u_la0_top/rst_ao_Z/CLK
6.792	0.202	tC2Q	FR	49	R9C2[2][B]	u_la0_top/rst_ao_Z/Q
8.560	1.768	tNET	RR	1	R9C2[1][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[10]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	577	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R9C2[1][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[10]/CLK
1.777	0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_length_Z[10]
1.788	0.011	tHld		1	R9C2[1][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[10]

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.768, 89.747%; tC2Q: 0.202, 10.253%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path12

Path Summary:

Slack	6.772
Data Arrival Time	8.560
Data Required Time	1.788
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_length_Z[11]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.677	0.678	tINS	FF	577	IOT48[A]	clk_ibuf/O
6.590	0.913	tNET	FF	1	R9C2[2][B]	u_la0_top/rst_ao_Z/CLK
6.792	0.202	tC2Q	FR	49	R9C2[2][B]	u_la0_top/rst_ao_Z/Q
8.560	1.768	tNET	RR	1	R8C9[1][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[11]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	577	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R8C9[1][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[11]/CLK
1.777	0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_length_Z[11]
1.788	0.011	tHld		1	R8C9[1][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[11]

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.768, 89.747%; tC2Q: 0.202, 10.253%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path13

Path Summary:

Slack	6.772
Data Arrival Time	8.560
Data Required Time	1.788
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_length_Z[12]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.677	0.678	tINS	FF	577	IOT48[A]	clk_ibuf/O
6.590	0.913	tNET	FF	1	R9C2[2][B]	u_la0_top/rst_ao_Z/CLK
6.792	0.202	tC2Q	FR	49	R9C2[2][B]	u_la0_top/rst_ao_Z/Q
8.560	1.768	tNET	RR	1	R2C4[2][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[12]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	577	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R2C4[2][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[12]/CLK
1.777	0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_length_Z[12]
1.788	0.011	tHld		1	R2C4[2][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[12]

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.768, 89.747%; tC2Q: 0.202, 10.253%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path14

Path Summary:

Slack	6.772
Data Arrival Time	8.560
Data Required Time	1.788
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.677	0.678	tINS	FF	577	IOT48[A]	clk_ibuf/O
6.590	0.913	tNET	FF	1	R9C2[2][B]	u_la0_top/rst_ao_Z/CLK
6.792	0.202	tC2Q	FR	49	R9C2[2][B]	u_la0_top/rst_ao_Z/Q
8.560	1.768	tNET	RR	1	R9C7[1][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	577	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R9C7[1][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0]/CLK
1.777	0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0]
1.788	0.011	tHld		1	R9C7[1][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0]

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.768, 89.747%; tC2Q: 0.202, 10.253%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path15

Path Summary:

Slack	6.772
Data Arrival Time	8.560
Data Required Time	1.788
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[1]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.677	0.678	tINS	FF	577	IOT48[A]	clk_ibuf/O
6.590	0.913	tNET	FF	1	R9C2[2][B]	u_la0_top/rst_ao_Z/CLK
6.792	0.202	tC2Q	FR	49	R9C2[2][B]	u_la0_top/rst_ao_Z/Q
8.560	1.768	tNET	RR	1	R9C7[1][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[1]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	577	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R9C7[1][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[1]/CLK
1.777	0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[1]
1.788	0.011	tHld		1	R9C7[1][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[1]

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.768, 89.747%; tC2Q: 0.202, 10.253%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path16

Path Summary:

Slack	6.772
Data Arrival Time	8.560
Data Required Time	1.788
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[2]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.677	0.678	tINS	FF	577	IOT48[A]	clk_ibuf/O
6.590	0.913	tNET	FF	1	R9C2[2][B]	u_la0_top/rst_ao_Z/CLK
6.792	0.202	tC2Q	FR	49	R9C2[2][B]	u_la0_top/rst_ao_Z/Q
8.560	1.768	tNET	RR	1	R9C7[2][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[2]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	577	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R9C7[2][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[2]/CLK
1.777	0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[2]
1.788	0.011	tHld		1	R9C7[2][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[2]

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.768, 89.747%; tC2Q: 0.202, 10.253%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path17

Path Summary:

Slack	6.772
Data Arrival Time	8.560
Data Required Time	1.788
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[3]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.677	0.678	tINS	FF	577	IOT48[A]	clk_ibuf/O
6.590	0.913	tNET	FF	1	R9C2[2][B]	u_la0_top/rst_ao_Z/CLK
6.792	0.202	tC2Q	FR	49	R9C2[2][B]	u_la0_top/rst_ao_Z/Q
8.560	1.768	tNET	RR	1	R9C7[2][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[3]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	577	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R9C7[2][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[3]/CLK
1.777	0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[3]
1.788	0.011	tHld		1	R9C7[2][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[3]

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.768, 89.747%; tC2Q: 0.202, 10.253%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path18

Path Summary:

Slack	6.772
Data Arrival Time	8.560
Data Required Time	1.788
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[4]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.677	0.678	tINS	FF	577	IOT48[A]	clk_ibuf/O
6.590	0.913	tNET	FF	1	R9C2[2][B]	u_la0_top/rst_ao_Z/CLK
6.792	0.202	tC2Q	FR	49	R9C2[2][B]	u_la0_top/rst_ao_Z/Q
8.560	1.768	tNET	RR	1	R9C9[0][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[4]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	577	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R9C9[0][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[4]/CLK
1.777	0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[4]
1.788	0.011	tHld		1	R9C9[0][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[4]

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.768, 89.747%; tC2Q: 0.202, 10.253%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path19

Path Summary:

Slack	6.772
Data Arrival Time	8.560
Data Required Time	1.788
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[5]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.677	0.678	tINS	FF	577	IOT48[A]	clk_ibuf/O
6.590	0.913	tNET	FF	1	R9C2[2][B]	u_la0_top/rst_ao_Z/CLK
6.792	0.202	tC2Q	FR	49	R9C2[2][B]	u_la0_top/rst_ao_Z/Q
8.560	1.768	tNET	RR	1	R12C8[1][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[5]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	577	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R12C8[1][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[5]/CLK
1.777	0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[5]
1.788	0.011	tHld		1	R12C8[1][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[5]

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.768, 89.747%; tC2Q: 0.202, 10.253%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path20

Path Summary:

Slack	6.772
Data Arrival Time	8.560
Data Required Time	1.788
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[6]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.677	0.678	tINS	FF	577	IOT48[A]	clk_ibuf/O
6.590	0.913	tNET	FF	1	R9C2[2][B]	u_la0_top/rst_ao_Z/CLK
6.792	0.202	tC2Q	FR	49	R9C2[2][B]	u_la0_top/rst_ao_Z/Q
8.560	1.768	tNET	RR	1	R12C8[1][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[6]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	577	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R12C8[1][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[6]/CLK
1.777	0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[6]
1.788	0.011	tHld		1	R12C8[1][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[6]

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.768, 89.747%; tC2Q: 0.202, 10.253%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path21

Path Summary:

Slack	6.772
Data Arrival Time	8.560
Data Required Time	1.788
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[7]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.677	0.678	tINS	FF	577	IOT48[A]	clk_ibuf/O
6.590	0.913	tNET	FF	1	R9C2[2][B]	u_la0_top/rst_ao_Z/CLK
6.792	0.202	tC2Q	FR	49	R9C2[2][B]	u_la0_top/rst_ao_Z/Q
8.560	1.768	tNET	RR	1	R9C9[0][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[7]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	577	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R9C9[0][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[7]/CLK
1.777	0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[7]
1.788	0.011	tHld		1	R9C9[0][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[7]

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.768, 89.747%; tC2Q: 0.202, 10.253%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path22

Path Summary:

Slack	6.772
Data Arrival Time	8.560
Data Required Time	1.788
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.677	0.678	tINS	FF	577	IOT48[A]	clk_ibuf/O
6.590	0.913	tNET	FF	1	R9C2[2][B]	u_la0_top/rst_ao_Z/CLK
6.792	0.202	tC2Q	FR	49	R9C2[2][B]	u_la0_top/rst_ao_Z/Q
8.560	1.768	tNET	RR	1	R7C11[0][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	577	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R7C11[0][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8]/CLK
1.777	0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8]
1.788	0.011	tHld		1	R7C11[0][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8]

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.768, 89.747%; tC2Q: 0.202, 10.253%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path23

Path Summary:

Slack	6.772
Data Arrival Time	8.560
Data Required Time	1.788
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[9]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.677	0.678	tINS	FF	577	IOT48[A]	clk_ibuf/O
6.590	0.913	tNET	FF	1	R9C2[2][B]	u_la0_top/rst_ao_Z/CLK
6.792	0.202	tC2Q	FR	49	R9C2[2][B]	u_la0_top/rst_ao_Z/Q
8.560	1.768	tNET	RR	1	R11C7[2][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[9]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	577	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R11C7[2][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[9]/CLK
1.777	0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[9]
1.788	0.011	tHld		1	R11C7[2][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[9]

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.768, 89.747%; tC2Q: 0.202, 10.253%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path24

Path Summary:

Slack	6.772
Data Arrival Time	8.560
Data Required Time	1.788
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[10]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.677	0.678	tINS	FF	577	IOT48[A]	clk_ibuf/O
6.590	0.913	tNET	FF	1	R9C2[2][B]	u_la0_top/rst_ao_Z/CLK
6.792	0.202	tC2Q	FR	49	R9C2[2][B]	u_la0_top/rst_ao_Z/Q
8.560	1.768	tNET	RR	1	R11C7[2][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[10]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	577	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R11C7[2][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[10]/CLK
1.777	0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[10]
1.788	0.011	tHld		1	R11C7[2][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[10]

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.768, 89.747%; tC2Q: 0.202, 10.253%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path25

Path Summary:

Slack	6.772
Data Arrival Time	8.560
Data Required Time	1.788
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[11]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.677	0.678	tINS	FF	577	IOT48[A]	clk_ibuf/O
6.590	0.913	tNET	FF	1	R9C2[2][B]	u_la0_top/rst_ao_Z/CLK
6.792	0.202	tC2Q	FR	49	R9C2[2][B]	u_la0_top/rst_ao_Z/Q
8.560	1.768	tNET	RR	1	R11C9[0][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[11]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	577	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R11C9[0][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[11]/CLK
1.777	0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[11]
1.788	0.011	tHld		1	R11C9[0][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[11]

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.768, 89.747%; tC2Q: 0.202, 10.253%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Minimum Pulse Width Report:

Report Command:report_min_pulse_width -nworst 10 -detail

MPW1

MPW Summary:

Slack:	3.662
Actual Width:	4.662
Required Width:	1.000
Type:	Low Pulse Width
Clock:	DEFAULT_CLK
Objects:	cnt_1_Z[12]

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	clk_ibuf/I
5.688	0.688	tINS	FF	clk_ibuf/O
6.916	1.228	tNET	FF	cnt_1_Z[12]/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	clk_ibuf/I
10.675	0.675	tINS	RR	clk_ibuf/O
11.577	0.902	tNET	RR	cnt_1_Z[12]/CLK

MPW2

MPW Summary:

Slack:	3.662
Actual Width:	4.662
Required Width:	1.000
Type:	Low Pulse Width
Clock:	DEFAULT_CLK
Objects:	cnt_1_Z[10]

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	clk_ibuf/I
5.688	0.688	tINS	FF	clk_ibuf/O
6.916	1.228	tNET	FF	cnt_1_Z[10]/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	clk_ibuf/I
10.675	0.675	tINS	RR	clk_ibuf/O
11.577	0.902	tNET	RR	cnt_1_Z[10]/CLK

MPW3

MPW Summary:

Slack:	3.662
Actual Width:	4.662
Required Width:	1.000
Type:	Low Pulse Width
Clock:	DEFAULT_CLK
Objects:	cnt_1_Z[6]

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	clk_ibuf/I
5.688	0.688	tINS	FF	clk_ibuf/O
6.916	1.228	tNET	FF	cnt_1_Z[6]/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	clk_ibuf/I
10.675	0.675	tINS	RR	clk_ibuf/O
11.577	0.902	tNET	RR	cnt_1_Z[6]/CLK

MPW4

MPW Summary:

Slack:	3.662
Actual Width:	4.662
Required Width:	1.000
Type:	Low Pulse Width
Clock:	DEFAULT_CLK
Objects:	cnt_Z[11]

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	clk_ibuf/I
5.688	0.688	tINS	FF	clk_ibuf/O
6.916	1.228	tNET	FF	cnt_Z[11]/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	clk_ibuf/I
10.675	0.675	tINS	RR	clk_ibuf/O
11.577	0.902	tNET	RR	cnt_Z[11]/CLK

MPW5

MPW Summary:

Slack:	3.662
Actual Width:	4.662
Required Width:	1.000
Type:	Low Pulse Width
Clock:	DEFAULT_CLK
Objects:	divisor[31]

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	clk_ibuf/I
5.688	0.688	tINS	FF	clk_ibuf/O
6.916	1.228	tNET	FF	divisor[31]/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	clk_ibuf/I
10.675	0.675	tINS	RR	clk_ibuf/O
11.577	0.902	tNET	RR	divisor[31]/CLK

MPW6

MPW Summary:

Slack:	3.662
Actual Width:	4.662
Required Width:	1.000
Type:	Low Pulse Width
Clock:	DEFAULT_CLK
Objects:	n_Z[30]

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	clk_ibuf/I
5.688	0.688	tINS	FF	clk_ibuf/O
6.916	1.228	tNET	FF	n_Z[30]/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	clk_ibuf/I
10.675	0.675	tINS	RR	clk_ibuf/O
11.577	0.902	tNET	RR	n_Z[30]/CLK

MPW7

MPW Summary:

Slack:	3.662
Actual Width:	4.662
Required Width:	1.000
Type:	Low Pulse Width
Clock:	DEFAULT_CLK
Objects:	memq_memq_0_15

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	clk_ibuf/I
5.688	0.688	tINS	FF	clk_ibuf/O
6.916	1.228	tNET	FF	memq_memq_0_15/CLKB

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	clk_ibuf/I
10.675	0.675	tINS	RR	clk_ibuf/O
11.577	0.902	tNET	RR	memq_memq_0_15/CLKB

MPW8

MPW Summary:

Slack:	3.662
Actual Width:	4.662
Required Width:	1.000
Type:	Low Pulse Width
Clock:	DEFAULT_CLK
Objects:	Mdu/u_mdu/reg0_fast_Z[13]

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	clk_ibuf/I
5.688	0.688	tINS	FF	clk_ibuf/O
6.916	1.228	tNET	FF	Mdu/u_mdu/reg0_fast_Z[13]/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	clk_ibuf/I
10.675	0.675	tINS	RR	clk_ibuf/O
11.577	0.902	tNET	RR	Mdu/u_mdu/reg0_fast_Z[13]/CLK

MPW9

MPW Summary:

Slack:	3.662
Actual Width:	4.662
Required Width:	1.000
Type:	Low Pulse Width
Clock:	DEFAULT_CLK
Objects:	u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_Z

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	clk_ibuf/I
5.688	0.688	tINS	FF	clk_ibuf/O
6.916	1.228	tNET	FF	u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_Z/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	clk_ibuf/I
10.675	0.675	tINS	RR	clk_ibuf/O
11.577	0.902	tNET	RR	u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_Z/CLK

MPW10

MPW Summary:

Slack:	3.662
Actual Width:	4.662
Required Width:	1.000
Type:	Low Pulse Width
Clock:	DEFAULT_CLK
Objects:	u_la0_top/u_ao_mem_ctrl/capture_loop_Z

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	clk_ibuf/I
5.688	0.688	tINS	FF	clk_ibuf/O
6.916	1.228	tNET	FF	u_la0_top/u_ao_mem_ctrl/capture_loop_Z/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	clk_ibuf/I
10.675	0.675	tINS	RR	clk_ibuf/O
11.577	0.902	tNET	RR	u_la0_top/u_ao_mem_ctrl/capture_loop_Z/CLK

High Fanout Nets Report:

Report Command:report_high_fanout_nets -max_nets 10

FANOUT	NET NAME	WORST SLACK	MAX DELAY
335	clk_c	0.264	1.228
114	div_shift_number[1]	0.959	2.122
113	div_shift_number[0]	0.792	2.050
100	reg0_en	5.194	2.212
96	neg_result	3.672	2.100
92	state[1]	5.518	1.824
81	hi_result	3.818	1.785
74	reg0_exe_nx_sm0	1.895	1.654
71	state[3]	5.567	1.579
70	m0_2_03_1	1.402	1.594

Route Congestions Report:

Report Command:report_route_congestion -max_grids 10

GRID LOC	ROUTE CONGESTIONS
R38C43	0.819
R47C54	0.792
R39C43	0.778
R55C45	0.778
R38C46	0.750
R38C42	0.736
R39C42	0.736
R55C42	0.736
R53C45	0.722
R42C55	0.722

Timing Exceptions Report:

Setup Analysis Report

Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Hold Analysis Report

Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Recovery Analysis Report

Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Removal Analysis Report

Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Timing Constraints Report:

SDC Command Type	State	Detail Command