#Build: Synplify Pro (R) O-2018.09G-SP1, Build 099R, Feb 12 2019 #install: C:\Gowin\1.8\SynplifyPro #OS: Windows 7 6.1 #Hostname: GW-SW-048 # Tue Feb 19 17:52:28 2019 #Implementation: rev_1 Copyright (C) 1994-2019 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: O-2018.09G-SP1 Install: C:\Gowin\1.8\SynplifyPro OS: Windows 6.1 Hostname: GW-SW-048 Implementation : rev_1 Synopsys HDL Compiler, Version comp2018q4p1, Build 115R, Built Feb 12 2019 09:25:38 @N: : | Running in 64-bit mode ###########################################################[ Copyright (C) 1994-2019 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: O-2018.09G-SP1 Install: C:\Gowin\1.8\SynplifyPro OS: Windows 6.1 Hostname: GW-SW-048 Implementation : rev_1 Synopsys Verilog Compiler, Version comp2018q4p1, Build 115R, Built Feb 12 2019 09:25:38 @N: : | Running in 64-bit mode @N:CG1349 : | Running Verilog Compiler in System Verilog mode @N:CG1350 : | Running Verilog Compiler in Multiple File Compilation Unit mode @I::"C:\Gowin\1.8\SynplifyPro\lib\generic\gw2a.v" (library work) @I::"C:\Gowin\1.8\SynplifyPro\lib\vlog\hypermods.v" (library __hyper__lib__) @I::"C:\Gowin\1.8\SynplifyPro\lib\vlog\umr_capim.v" (library snps_haps) @I::"C:\Gowin\1.8\SynplifyPro\lib\vlog\scemi_objects.v" (library snps_haps) @I::"C:\Gowin\1.8\SynplifyPro\lib\vlog\scemi_pipes.svh" (library snps_haps) @I::"F:\user-bak\Users\FDELL\Desktop\IP\Integer_Multiply-Divider\ref_design\DIV\Integer_Multiply_Divider_np\project\src\integer_multiply_divider\integer_multiply_divider.v" (library work) @I::"F:\user-bak\Users\FDELL\Desktop\IP\Integer_Multiply-Divider\ref_design\DIV\Integer_Multiply_Divider_np\project\src\top.v" (library work) Verilog syntax check successful! Options changed - recompiling Selecting top level module top @N:CG364 : gw2a.v(1597) | Synthesizing module GSR in library work. Running optimization stage 1 on GSR ....... Running optimization stage 1 on MUX2_LUT5 ....... Running optimization stage 1 on INV ....... Running optimization stage 1 on LUT4 ....... Running optimization stage 1 on LUT3 ....... Running optimization stage 1 on LUT2 ....... Running optimization stage 1 on DFFRE ....... Running optimization stage 1 on DFFE ....... Running optimization stage 1 on DFFC ....... Running optimization stage 1 on DFFP ....... Running optimization stage 1 on DFFCE ....... Running optimization stage 1 on DFFSE ....... Running optimization stage 1 on ALU ....... Running optimization stage 1 on GND ....... Running optimization stage 1 on VCC ....... Running optimization stage 1 on \(integerMultiplyDivider)/(Integer_Multiply_Divider_Top)_Z1 ....... @N:CG364 : integer_multiply_divider.v(17140) | Synthesizing module Integer_Multiply_Divider_Top in library work. Running optimization stage 1 on Integer_Multiply_Divider_Top ....... @W:CL168 : integer_multiply_divider.v(17206) | Removing instance GND_cZ because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @N:CG364 : top.v(4) | Synthesizing module top in library work. @W:CS142 : top.v(4) | Range of port tagI in port declaration and body are different. @W:CS142 : top.v(4) | Range of port tagO in port declaration and body are different. @W:CS142 : top.v(4) | Range of port quotient in port declaration and body are different. @W:CS142 : top.v(4) | Range of port remainder in port declaration and body are different. Running optimization stage 1 on top ....... @N:CL134 : top.v(124) | Found RAM memr, depth=8192, width=32 @N:CL134 : top.v(124) | Found RAM memq, depth=8192, width=32 Running optimization stage 2 on top ....... @N:CL189 : top.v(151) | Register bit ad[1] is always 0. @N:CL189 : top.v(57) | Register bit m[0] is always 1. @N:CL189 : top.v(57) | Register bit m[1] is always 0. @N:CL189 : top.v(57) | Register bit m[2] is always 0. @N:CL189 : top.v(57) | Register bit m[3] is always 0. @N:CL189 : top.v(57) | Register bit m[4] is always 0. @N:CL189 : top.v(57) | Register bit m[5] is always 0. @N:CL189 : top.v(57) | Register bit m[6] is always 0. @N:CL189 : top.v(57) | Register bit m[7] is always 0. @N:CL189 : top.v(57) | Register bit m[8] is always 0. @N:CL189 : top.v(57) | Register bit m[9] is always 0. @N:CL189 : top.v(57) | Register bit m[10] is always 0. @N:CL189 : top.v(57) | Register bit m[11] is always 0. @N:CL189 : top.v(57) | Register bit m[12] is always 0. @N:CL189 : top.v(57) | Register bit m[13] is always 0. @N:CL189 : top.v(57) | Register bit m[14] is always 0. @N:CL189 : top.v(57) | Register bit m[15] is always 0. @N:CL189 : top.v(57) | Register bit m[16] is always 0. @N:CL189 : top.v(57) | Register bit m[17] is always 0. @N:CL189 : top.v(57) | Register bit m[18] is always 0. @N:CL189 : top.v(57) | Register bit m[19] is always 0. @N:CL189 : top.v(57) | Register bit m[20] is always 0. @N:CL189 : top.v(57) | Register bit m[21] is always 0. @N:CL189 : top.v(57) | Register bit m[22] is always 0. @N:CL189 : top.v(73) | Register bit n[0] is always 0. @N:CL189 : top.v(73) | Register bit n[1] is always 0. @N:CL189 : top.v(73) | Register bit n[2] is always 0. @N:CL189 : top.v(73) | Register bit n[3] is always 0. @N:CL189 : top.v(73) | Register bit n[4] is always 0. @N:CL189 : top.v(73) | Register bit n[5] is always 0. @N:CL189 : top.v(73) | Register bit n[6] is always 0. @N:CL189 : top.v(73) | Register bit n[7] is always 0. @N:CL189 : top.v(73) | Register bit n[8] is always 0. @N:CL189 : top.v(73) | Register bit n[9] is always 0. @N:CL189 : top.v(73) | Register bit n[10] is always 0. @N:CL189 : top.v(73) | Register bit n[11] is always 0. @N:CL189 : top.v(73) | Register bit n[12] is always 0. @N:CL189 : top.v(73) | Register bit n[13] is always 0. @N:CL189 : top.v(73) | Register bit n[14] is always 0. @N:CL189 : top.v(73) | Register bit n[15] is always 0. @N:CL189 : top.v(73) | Register bit n[16] is always 0. @N:CL189 : top.v(73) | Register bit n[17] is always 0. @N:CL189 : top.v(73) | Register bit n[18] is always 0. @N:CL189 : top.v(73) | Register bit n[19] is always 0. @N:CL189 : top.v(73) | Register bit n[20] is always 0. @N:CL189 : top.v(73) | Register bit n[21] is always 0. @N:CL189 : top.v(73) | Register bit n[22] is always 0. @W:CL279 : top.v(73) | Pruning register bits 22 to 0 of n[31:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. @W:CL279 : top.v(57) | Pruning register bits 22 to 0 of m[31:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. @W:CL260 : top.v(151) | Pruning register bit 1 of ad[1:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. @N:CL189 : top.v(88) | Register bit dividend[1] is always 0. @N:CL189 : top.v(88) | Register bit dividend[2] is always 0. @N:CL189 : top.v(88) | Register bit dividend[3] is always 0. @N:CL189 : top.v(88) | Register bit dividend[4] is always 0. @N:CL189 : top.v(88) | Register bit dividend[5] is always 0. @N:CL189 : top.v(88) | Register bit dividend[6] is always 0. @N:CL189 : top.v(88) | Register bit dividend[7] is always 0. @N:CL189 : top.v(88) | Register bit dividend[8] is always 0. @N:CL189 : top.v(88) | Register bit dividend[9] is always 0. @N:CL189 : top.v(88) | Register bit dividend[10] is always 0. @N:CL189 : top.v(88) | Register bit dividend[11] is always 0. @N:CL189 : top.v(88) | Register bit dividend[12] is always 0. @N:CL189 : top.v(88) | Register bit dividend[13] is always 0. @N:CL189 : top.v(88) | Register bit dividend[14] is always 0. @N:CL189 : top.v(88) | Register bit dividend[15] is always 0. @N:CL189 : top.v(88) | Register bit dividend[16] is always 0. @N:CL189 : top.v(88) | Register bit dividend[17] is always 0. @N:CL189 : top.v(88) | Register bit dividend[18] is always 0. @N:CL189 : top.v(88) | Register bit dividend[19] is always 0. @N:CL189 : top.v(88) | Register bit dividend[20] is always 0. @N:CL189 : top.v(88) | Register bit dividend[21] is always 0. @N:CL189 : top.v(88) | Register bit dividend[22] is always 0. @N:CL189 : top.v(88) | Register bit divisor[0] is always 0. @N:CL189 : top.v(88) | Register bit divisor[1] is always 0. @N:CL189 : top.v(88) | Register bit divisor[2] is always 0. @N:CL189 : top.v(88) | Register bit divisor[3] is always 0. @N:CL189 : top.v(88) | Register bit divisor[4] is always 0. @N:CL189 : top.v(88) | Register bit divisor[5] is always 0. @N:CL189 : top.v(88) | Register bit divisor[6] is always 0. @N:CL189 : top.v(88) | Register bit divisor[7] is always 0. @N:CL189 : top.v(88) | Register bit divisor[8] is always 0. @N:CL189 : top.v(88) | Register bit divisor[9] is always 0. @N:CL189 : top.v(88) | Register bit divisor[10] is always 0. @N:CL189 : top.v(88) | Register bit divisor[11] is always 0. @N:CL189 : top.v(88) | Register bit divisor[12] is always 0. @N:CL189 : top.v(88) | Register bit divisor[13] is always 0. @N:CL189 : top.v(88) | Register bit divisor[14] is always 0. @N:CL189 : top.v(88) | Register bit divisor[15] is always 0. @N:CL189 : top.v(88) | Register bit divisor[16] is always 0. @N:CL189 : top.v(88) | Register bit divisor[17] is always 0. @N:CL189 : top.v(88) | Register bit divisor[18] is always 0. @N:CL189 : top.v(88) | Register bit divisor[19] is always 0. @N:CL189 : top.v(88) | Register bit divisor[20] is always 0. @N:CL189 : top.v(88) | Register bit divisor[21] is always 0. @N:CL189 : top.v(88) | Register bit divisor[22] is always 0. @N:CL189 : top.v(73) | Register bit n[31] is always 0. @W:CL260 : top.v(73) | Pruning register bit 31 of n[31:23]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. @W:CL279 : top.v(88) | Pruning register bits 22 to 0 of divisor[31:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. @W:CL279 : top.v(88) | Pruning register bits 22 to 1 of dividend[31:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. @N:CL189 : top.v(88) | Register bit divisor[31] is always 0. @W:CL260 : top.v(88) | Pruning register bit 31 of divisor[31:23]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. Running optimization stage 2 on Integer_Multiply_Divider_Top ....... Running optimization stage 2 on \(integerMultiplyDivider)/(Integer_Multiply_Divider_Top)_Z1 ....... Running optimization stage 2 on VCC ....... Running optimization stage 2 on GND ....... Running optimization stage 2 on ALU ....... Running optimization stage 2 on DFFSE ....... Running optimization stage 2 on DFFCE ....... Running optimization stage 2 on DFFP ....... Running optimization stage 2 on DFFC ....... Running optimization stage 2 on DFFE ....... Running optimization stage 2 on DFFRE ....... Running optimization stage 2 on LUT2 ....... Running optimization stage 2 on LUT3 ....... Running optimization stage 2 on LUT4 ....... Running optimization stage 2 on INV ....... Running optimization stage 2 on MUX2_LUT5 ....... Running optimization stage 2 on GSR ....... For a summary of runtime and memory usage per design unit, please see file: ========================================================== Linked File: layer0.rt.csv At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 93MB peak: 106MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. # Tue Feb 19 17:52:29 2019 ###########################################################] ###########################################################[ Copyright (C) 1994-2019 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: O-2018.09G-SP1 Install: C:\Gowin\1.8\SynplifyPro OS: Windows 6.1 Hostname: GW-SW-048 Implementation : rev_1 Synopsys Synopsys Netlist Linker, Version comp2018q4p1, Build 115R, Built Feb 12 2019 09:25:38 @N: : | Running in 64-bit mode File /share/gwsw/gowin_new/Gowin/Gowin_YunYuan_V1.9.xBeta/SynplifyPro/linux_a_64/syn_nfilter changed - recompiling File /home/wenbo/Desktop/Integer_Multiply_Divider_np/impl/synplify/rev_1/synwork/layer0.srs changed - recompiling @N:NF107 : top.v(4) | Selected library: work cell: top view verilog as top level @N:NF107 : top.v(4) | Selected library: work cell: top view verilog as top level At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 70MB peak: 72MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. # Tue Feb 19 17:52:29 2019 ###########################################################] @END At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. # Tue Feb 19 17:52:30 2019 ###########################################################]