Timing Messages

Report Title	Gowin Timing Analysis Report
Design File	F:/user-bak/Users/FDELL/Desktop/IP/Integer_Multiply-Divider/ref_design/DIV/Integer_Multiply_Divider_np/project/impl/synplify/rev_1/Integer_Multiply_Divider_np.vm
Physical Constraints File	F:\user-bak\Users\FDELL\Desktop\IP\Integer_Multiply-Divider\ref_design\DIV\Integer_Multiply_Divider_np\project\src\Integer_Multiply_Divider_np.cst
Timing Constraints File	---
GOWIN version	v1.9.0Beta
Part Number	GW2A-LV55PG484C8/I7
Created Time	Tue Feb 19 17:54:03 2019
Legal Announcement	Copyright (C)2014-2019 Gowin Semiconductor Corporation. All rights reserved.

Timing Summaries

STA Tool Run Summary:

Setup Delay Model	Slow 0.95V 85C
Hold Delay Model	Fast 1.05V 0C
Numbers of Paths Analyzed	4128
Numbers of Endpoints Analyzed	9288
Numbers of Falling Endpoints	1
Numbers of Setup Violated Endpoints	0
Numbers of Hold Violated Endpoints	0

Clock Summary:

Clock Name	Type	Period	Frequency(MHz)	Rise	Fall	Source	Master	Objects
DEFAULT_CLK	Base	10.000	100.000	0.000	5.000

Max Frequency Summary:

NO.	Clock Name	Fmax	Entity
1	DEFAULT_CLK	104.397(MHz)	TOP

Total Negative Slack Summary:

Clock Name	Analysis Type	Endpoints TNS	Number of Endpoints
DEFAULT_CLK	Setup	0.000	0
DEFAULT_CLK	Hold	0.000	0

Timing Details

Path Slacks Table:

Setup Paths Table

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	0.421	Mdu/u_mdu/reg0_Z[3]/Q	Mdu/u_mdu/reg0_fast_Z[20]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	0.000	9.344
2	0.421	Mdu/u_mdu/reg0_Z[3]/Q	Mdu/u_mdu/reg0_Z[20]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	0.000	9.344
3	0.497	Mdu/u_mdu/reg1_Z[1]/Q	Mdu/u_mdu/reg0_Z[7]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	0.000	9.268
4	0.576	Mdu/u_mdu/reg1_Z[1]/Q	Mdu/u_mdu/reg0_Z[32]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	0.000	9.189
5	0.688	Mdu/u_mdu/reg0_Z[10]/Q	Mdu/u_mdu/reg0_Z[31]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	0.000	9.077
6	0.688	Mdu/u_mdu/reg0_Z[3]/Q	Mdu/u_mdu/reg0_fast_Z[28]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	0.000	9.077
7	0.688	Mdu/u_mdu/reg0_Z[3]/Q	Mdu/u_mdu/reg0_Z[28]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	0.000	9.077
8	0.744	Mdu/u_mdu/reg0_fast_Z[4]/Q	memq_memq_0_9/DI0	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	0.000	9.021
9	0.853	Mdu/u_mdu/reg1_Z[1]/Q	Mdu/u_mdu/reg0_Z[37]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	0.000	8.912
10	0.860	Mdu/u_mdu/reg0_fast_Z[20]/Q	memq_memq_0_15/DI1	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	0.000	8.905
11	0.870	Mdu/u_mdu/reg0_fast_Z[4]/Q	Mdu/u_mdu/reg0_fast_Z[13]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	0.000	8.895
12	0.870	Mdu/u_mdu/reg0_fast_Z[4]/Q	Mdu/u_mdu/reg0_Z[13]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	0.000	8.895
13	0.912	Mdu/u_mdu/reg0_Z[3]/Q	Mdu/u_mdu/reg0_Z[64]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	0.000	8.853
14	0.932	Mdu/u_mdu/reg0_fast_Z[4]/Q	memq_memq_0_6/DI0	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	0.000	8.833
15	0.935	Mdu/u_mdu/reg0_Z[10]/Q	Mdu/u_mdu/reg0_31_rep1_Z/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	0.000	8.830
16	0.935	Mdu/u_mdu/reg0_Z[10]/Q	Mdu/u_mdu/reg0_fast_Z[31]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	0.000	8.830
17	0.968	Mdu/u_mdu/reg0_fast_Z[4]/Q	Mdu/u_mdu/reg0_Z[16]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	0.000	8.797
18	1.079	Mdu/u_mdu/reg0_fast_Z[4]/Q	memq_memq_0_8/DI0	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	0.000	8.687
19	1.169	Mdu/u_mdu/reg0_fast_Z[4]/Q	Mdu/u_mdu/reg0_Z[18]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	0.000	8.596
20	1.190	Mdu/u_mdu/reg0_fast_Z[4]/Q	Mdu/u_mdu/reg0_fast_Z[18]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	0.000	8.575
21	1.292	Mdu/u_mdu/reg0_fast_Z[4]/Q	Mdu/u_mdu/reg0_Z[21]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	0.000	8.473
22	1.341	Mdu/u_mdu/reg0_fast_Z[4]/Q	memq_memq_0_10/DI0	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	0.000	8.424
23	1.388	Mdu/u_mdu/reg0_fast_Z[4]/Q	memq_memq_0_4/DI1	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	0.000	8.378
24	1.399	Mdu/u_mdu/reg1_Z[1]/Q	Mdu/u_mdu/reg0_Z[38]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	0.000	8.366
25	1.400	Mdu/u_mdu/reg1_Z[1]/Q	Mdu/u_mdu/reg0_Z[35]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	0.000	8.365

Hold Paths Table

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	0.213	u_la0_top/u_ao_mem_ctrl/data_reg_Z[97]/Q	u_la0_top/u_ao_mem_ctrl/mem_mem_0_48/DI1	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.000	0.000	0.462
2	0.213	u_la0_top/u_ao_mem_ctrl/data_reg_Z[87]/Q	u_la0_top/u_ao_mem_ctrl/mem_mem_0_43/DI1	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.000	0.000	0.462
3	0.213	u_la0_top/u_ao_mem_ctrl/data_reg_Z[86]/Q	u_la0_top/u_ao_mem_ctrl/mem_mem_0_43/DI0	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.000	0.000	0.462
4	0.230	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[9]/Q	u_la0_top/u_ao_mem_ctrl/mem_mem_0_11/ADA10	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.000	0.000	0.348
5	0.232	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8]/Q	u_la0_top/u_ao_mem_ctrl/mem_mem_0_11/ADA9	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.000	0.000	0.350
6	0.235	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[11]/Q	u_la0_top/u_ao_mem_ctrl/mem_mem_0_11/ADA12	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.000	0.000	0.353
7	0.324	Mdu/u_mdu/reg1_Z[29]/Q	Mdu/u_mdu/rs1_mul_Z[29]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.000	0.000	0.335
8	0.335	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[10]/Q	u_la0_top/u_ao_mem_ctrl/mem_mem_0_11/ADA11	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.000	0.000	0.453
9	0.335	u_la0_top/u_ao_mem_ctrl/data_reg_Z[106]/Q	u_la0_top/u_ao_mem_ctrl/mem_mem_0_53/DI0	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.000	0.000	0.584
10	0.335	u_la0_top/u_ao_mem_ctrl/data_reg_Z[96]/Q	u_la0_top/u_ao_mem_ctrl/mem_mem_0_48/DI0	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.000	0.000	0.584
11	0.337	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0]/Q	u_la0_top/u_ao_mem_ctrl/mem_mem_0_43/ADA1	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.000	0.000	0.455
12	0.353	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[6]/Q	u_la0_top/u_ao_mem_ctrl/mem_mem_0_11/ADA7	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.000	0.000	0.471
13	0.353	cnt_1_Z[5]/Q	memq_memq_0_2/ADB6	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.000	0.000	0.471
14	0.354	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[2]/Q	u_la0_top/u_ao_mem_ctrl/mem_mem_0_43/ADA3	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.000	0.000	0.472
15	0.354	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[2]/Q	u_la0_top/u_ao_mem_ctrl/mem_mem_0_11/ADA3	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.000	0.000	0.472
16	0.354	cnt_1_Z[12]/Q	memq_memq_0_2/ADB13	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.000	0.000	0.472
17	0.355	cnt_1_Z[6]/Q	memq_memq_0_2/ADB7	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.000	0.000	0.473
18	0.357	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[3]/Q	u_la0_top/u_ao_mem_ctrl/mem_mem_0_43/ADA4	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.000	0.000	0.475
19	0.357	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[3]/Q	u_la0_top/u_ao_mem_ctrl/mem_mem_0_11/ADA4	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.000	0.000	0.475
20	0.358	cnt_1_Z[0]/Q	memr_memr_0_15/ADB1	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.000	0.000	0.476
21	0.361	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0]/Q	u_la0_top/u_ao_mem_ctrl/mem_mem_0_6/ADA1	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.000	0.000	0.479
22	0.363	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[10]/Q	u_la0_top/u_ao_mem_ctrl/mem_mem_0_6/ADA11	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.000	0.000	0.481
23	0.364	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[1]/Q	u_la0_top/u_ao_mem_ctrl/mem_mem_0_6/ADA2	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.000	0.000	0.482
24	0.367	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[3]/Q	u_la0_top/u_ao_mem_ctrl/mem_mem_0_6/ADA4	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.000	0.000	0.485
25	0.373	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[1]/Q	u_la0_top/u_ao_mem_ctrl/mem_mem_0_53/ADA2	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.000	0.000	0.491

Recovery Paths Table

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	1.914	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	5.000	0.033	2.818
2	1.914	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_Z/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	5.000	0.033	2.818
3	1.914	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_loop_Z/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	5.000	0.033	2.818
4	1.914	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_length_Z[0]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	5.000	0.033	2.818
5	1.914	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_length_Z[1]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	5.000	0.033	2.818
6	1.914	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_length_Z[2]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	5.000	0.033	2.818
7	1.914	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_length_Z[3]/PRESET	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	5.000	0.033	2.818
8	1.914	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_length_Z[4]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	5.000	0.033	2.818
9	1.914	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_length_Z[5]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	5.000	0.033	2.818
10	1.914	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_length_Z[6]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	5.000	0.033	2.818
11	1.914	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_length_Z[7]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	5.000	0.033	2.818
12	1.914	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_length_Z[8]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	5.000	0.033	2.818
13	1.914	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_length_Z[9]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	5.000	0.033	2.818
14	1.914	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_length_Z[10]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	5.000	0.033	2.818
15	1.914	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_length_Z[11]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	5.000	0.033	2.818
16	1.914	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_length_Z[12]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	5.000	0.033	2.818
17	1.914	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	5.000	0.033	2.818
18	1.914	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[1]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	5.000	0.033	2.818
19	1.914	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[2]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	5.000	0.033	2.818
20	1.914	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[3]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	5.000	0.033	2.818
21	1.914	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[4]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	5.000	0.033	2.818
22	1.914	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[5]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	5.000	0.033	2.818
23	1.914	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[6]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	5.000	0.033	2.818
24	1.914	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[7]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	5.000	0.033	2.818
25	1.914	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	5.000	0.033	2.818

Removal Paths Table

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	6.623	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	-5.000	0.013	1.821
2	6.623	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_loop_Z/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	-5.000	0.013	1.821
3	6.623	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_length_Z[0]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	-5.000	0.013	1.821
4	6.623	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_length_Z[1]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	-5.000	0.013	1.821
5	6.623	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_length_Z[2]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	-5.000	0.013	1.821
6	6.623	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_length_Z[4]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	-5.000	0.013	1.821
7	6.623	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_length_Z[5]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	-5.000	0.013	1.821
8	6.623	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_length_Z[7]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	-5.000	0.013	1.821
9	6.623	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_length_Z[8]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	-5.000	0.013	1.821
10	6.623	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_length_Z[9]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	-5.000	0.013	1.821
11	6.623	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_length_Z[10]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	-5.000	0.013	1.821
12	6.623	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_length_Z[11]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	-5.000	0.013	1.821
13	6.623	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_length_Z[12]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	-5.000	0.013	1.821
14	6.623	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	-5.000	0.013	1.821
15	6.623	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[1]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	-5.000	0.013	1.821
16	6.623	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[2]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	-5.000	0.013	1.821
17	6.623	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[3]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	-5.000	0.013	1.821
18	6.623	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[4]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	-5.000	0.013	1.821
19	6.623	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[5]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	-5.000	0.013	1.821
20	6.623	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[6]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	-5.000	0.013	1.821
21	6.623	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[7]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	-5.000	0.013	1.821
22	6.623	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	-5.000	0.013	1.821
23	6.623	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[9]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	-5.000	0.013	1.821
24	6.623	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[10]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	-5.000	0.013	1.821
25	6.623	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[11]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	-5.000	0.013	1.821

Minimum Pulse Width Table:

Report Command:report_min_pulse_width -nworst 10 -detail

Number	Slack	Actual Width	Required Width	Type	Clock	Objects
1	3.662	4.662	1.000	Low Pulse Width	DEFAULT_CLK	cnt_1_Z[12]
2	3.662	4.662	1.000	Low Pulse Width	DEFAULT_CLK	cnt_1_Z[10]
3	3.662	4.662	1.000	Low Pulse Width	DEFAULT_CLK	cnt_1_Z[6]
4	3.662	4.662	1.000	Low Pulse Width	DEFAULT_CLK	cnt_Z[11]
5	3.662	4.662	1.000	Low Pulse Width	DEFAULT_CLK	dividend[24]
6	3.662	4.662	1.000	Low Pulse Width	DEFAULT_CLK	memr_memr_0_0
7	3.662	4.662	1.000	Low Pulse Width	DEFAULT_CLK	Mdu/u_mdu/div_shift_number_Z[5]
8	3.662	4.662	1.000	Low Pulse Width	DEFAULT_CLK	Mdu/u_mdu/reg0_fast_Z[12]
9	3.662	4.662	1.000	Low Pulse Width	DEFAULT_CLK	u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z
10	3.662	4.662	1.000	Low Pulse Width	DEFAULT_CLK	u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_Z

Timing Report By Analysis Type:

Setup Analysis Report

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	0.421
Data Arrival Time	11.227
Data Required Time	11.648
From	Mdu/u_mdu/reg0_Z[3]
To	Mdu/u_mdu/reg0_fast_Z[20]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.683	0.683	tINS	RR	576	IOT48[A]	clk_ibuf/O
1.883	1.201	tNET	RR	1	R39C48[0][A]	Mdu/u_mdu/reg0_Z[3]/CLK
2.115	0.232	tC2Q	RF	12	R39C48[0][A]	Mdu/u_mdu/reg0_Z[3]/Q
3.182	1.067	tNET	FF	1	R46C55[0][A]	Mdu/u_mdu/m4_0_03_1_0_cZ/I2
3.553	0.371	tINS	FF	2	R46C55[0][A]	Mdu/u_mdu/m4_0_03_1_0_cZ/F
4.049	0.496	tNET	FF	1	R46C59[1][B]	Mdu/u_mdu/m4_0_03_0_0_RNI1JV1/I1
4.604	0.555	tINS	FF	3	R46C59[1][B]	Mdu/u_mdu/m4_0_03_0_0_RNI1JV1/F
5.297	0.693	tNET	FF	1	R47C55[1][A]	Mdu/u_mdu/m4_2_03_cZ/I3
5.852	0.555	tINS	FF	4	R47C55[1][A]	Mdu/u_mdu/m4_2_03_cZ/F
6.379	0.527	tNET	FF	1	R43C55[2][A]	Mdu/u_mdu/m20_4_01_cZ/I1
6.896	0.517	tINS	FF	1	R43C55[2][A]	Mdu/u_mdu/m20_4_01_cZ/F
7.822	0.927	tNET	FF	1	R38C52[3][A]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[20]/I2
8.275	0.453	tINS	FF	1	R38C52[3][A]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[20]/F
9.174	0.899	tNET	FF	1	R38C49[0][A]	Mdu/u_mdu/reg0_exe_nx_cZ[20]/I3
9.545	0.371	tINS	FF	2	R38C49[0][A]	Mdu/u_mdu/reg0_exe_nx_cZ[20]/F
10.678	1.133	tNET	FF	1	R43C48[0][B]	Mdu/u_mdu/reg0_nx_fast_cZ[20]/I0
11.227	0.549	tINS	FR	1	R43C48[0][B]	Mdu/u_mdu/reg0_nx_fast_cZ[20]/F
11.227	0.000	tNET	RR	1	R43C48[0][B]	Mdu/u_mdu/reg0_fast_Z[20]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	576	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R43C48[0][B]	Mdu/u_mdu/reg0_fast_Z[20]/CLK
11.683	-0.200	tUnc				Mdu/u_mdu/reg0_fast_Z[20]
11.648	-0.035	tSu		1	R43C48[0][B]	Mdu/u_mdu/reg0_fast_Z[20]

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 3.371, 36.077%; route: 5.741, 61.440%; tC2Q: 0.232, 2.483%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path2

Path Summary:

Slack	0.421
Data Arrival Time	11.227
Data Required Time	11.648
From	Mdu/u_mdu/reg0_Z[3]
To	Mdu/u_mdu/reg0_Z[20]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.683	0.683	tINS	RR	576	IOT48[A]	clk_ibuf/O
1.883	1.201	tNET	RR	1	R39C48[0][A]	Mdu/u_mdu/reg0_Z[3]/CLK
2.115	0.232	tC2Q	RF	12	R39C48[0][A]	Mdu/u_mdu/reg0_Z[3]/Q
3.182	1.067	tNET	FF	1	R46C55[0][A]	Mdu/u_mdu/m4_0_03_1_0_cZ/I2
3.553	0.371	tINS	FF	2	R46C55[0][A]	Mdu/u_mdu/m4_0_03_1_0_cZ/F
4.049	0.496	tNET	FF	1	R46C59[1][B]	Mdu/u_mdu/m4_0_03_0_0_RNI1JV1/I1
4.604	0.555	tINS	FF	3	R46C59[1][B]	Mdu/u_mdu/m4_0_03_0_0_RNI1JV1/F
5.297	0.693	tNET	FF	1	R47C55[1][A]	Mdu/u_mdu/m4_2_03_cZ/I3
5.852	0.555	tINS	FF	4	R47C55[1][A]	Mdu/u_mdu/m4_2_03_cZ/F
6.379	0.527	tNET	FF	1	R43C55[2][A]	Mdu/u_mdu/m20_4_01_cZ/I1
6.896	0.517	tINS	FF	1	R43C55[2][A]	Mdu/u_mdu/m20_4_01_cZ/F
7.822	0.927	tNET	FF	1	R38C52[3][A]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[20]/I2
8.275	0.453	tINS	FF	1	R38C52[3][A]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[20]/F
9.174	0.899	tNET	FF	1	R38C49[0][A]	Mdu/u_mdu/reg0_exe_nx_cZ[20]/I3
9.545	0.371	tINS	FF	2	R38C49[0][A]	Mdu/u_mdu/reg0_exe_nx_cZ[20]/F
10.678	1.133	tNET	FF	1	R43C48[1][A]	Mdu/u_mdu/reg0_nx_cZ[20]/I0
11.227	0.549	tINS	FR	1	R43C48[1][A]	Mdu/u_mdu/reg0_nx_cZ[20]/F
11.227	0.000	tNET	RR	1	R43C48[1][A]	Mdu/u_mdu/reg0_Z[20]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	576	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R43C48[1][A]	Mdu/u_mdu/reg0_Z[20]/CLK
11.683	-0.200	tUnc				Mdu/u_mdu/reg0_Z[20]
11.648	-0.035	tSu		1	R43C48[1][A]	Mdu/u_mdu/reg0_Z[20]

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 3.371, 36.077%; route: 5.741, 61.440%; tC2Q: 0.232, 2.483%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path3

Path Summary:

Slack	0.497
Data Arrival Time	11.151
Data Required Time	11.648
From	Mdu/u_mdu/reg1_Z[1]
To	Mdu/u_mdu/reg0_Z[7]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.683	0.683	tINS	RR	576	IOT48[A]	clk_ibuf/O
1.883	1.201	tNET	RR	1	R34C60[0][B]	Mdu/u_mdu/reg1_Z[1]/CLK
2.115	0.232	tC2Q	RF	8	R34C60[0][B]	Mdu/u_mdu/reg1_Z[1]/Q
3.060	0.945	tNET	FF	1	R35C53[3][A]	Mdu/u_mdu/adder_sum_s_1_sf_lofx_cZ/I1
3.513	0.453	tINS	FF	1	R35C53[3][A]	Mdu/u_mdu/adder_sum_s_1_sf_lofx_cZ/F
4.411	0.899	tNET	FF	2	R38C50[1][B]	Mdu/u_mdu/adder_sum_cry_1_0/I0
4.981	0.570	tINS	FR	1	R38C50[1][B]	Mdu/u_mdu/adder_sum_cry_1_0/COUT
4.981	0.000	tNET	RR	2	R38C50[2][A]	Mdu/u_mdu/adder_sum_cry_2_0/CIN
5.017	0.035	tINS	RF	1	R38C50[2][A]	Mdu/u_mdu/adder_sum_cry_2_0/COUT
5.017	0.000	tNET	FF	2	R38C50[2][B]	Mdu/u_mdu/adder_sum_cry_3_0/CIN
5.052	0.035	tINS	FF	1	R38C50[2][B]	Mdu/u_mdu/adder_sum_cry_3_0/COUT
5.052	0.000	tNET	FF	2	R38C51[0][A]	Mdu/u_mdu/adder_sum_cry_4_0/CIN
5.087	0.035	tINS	FF	1	R38C51[0][A]	Mdu/u_mdu/adder_sum_cry_4_0/COUT
5.087	0.000	tNET	FF	2	R38C51[0][B]	Mdu/u_mdu/adder_sum_cry_5_0/CIN
5.122	0.035	tINS	FF	1	R38C51[0][B]	Mdu/u_mdu/adder_sum_cry_5_0/COUT
5.122	0.000	tNET	FF	2	R38C51[1][A]	Mdu/u_mdu/adder_sum_cry_6_0/CIN
5.157	0.035	tINS	FF	1	R38C51[1][A]	Mdu/u_mdu/adder_sum_cry_6_0/COUT
5.157	0.000	tNET	FF	2	R38C51[1][B]	Mdu/u_mdu/adder_sum_cry_7_0/CIN
5.193	0.035	tINS	FF	1	R38C51[1][B]	Mdu/u_mdu/adder_sum_cry_7_0/COUT
5.193	0.000	tNET	FF	2	R38C51[2][A]	Mdu/u_mdu/adder_sum_cry_8_0/CIN
5.228	0.035	tINS	FF	1	R38C51[2][A]	Mdu/u_mdu/adder_sum_cry_8_0/COUT
5.228	0.000	tNET	FF	2	R38C51[2][B]	Mdu/u_mdu/adder_sum_cry_9_0/CIN
5.263	0.035	tINS	FF	1	R38C51[2][B]	Mdu/u_mdu/adder_sum_cry_9_0/COUT
5.263	0.000	tNET	FF	2	R38C52[0][A]	Mdu/u_mdu/adder_sum_cry_10_0/CIN
5.298	0.035	tINS	FF	1	R38C52[0][A]	Mdu/u_mdu/adder_sum_cry_10_0/COUT
5.298	0.000	tNET	FF	2	R38C52[0][B]	Mdu/u_mdu/adder_sum_cry_11_0/CIN
5.333	0.035	tINS	FF	1	R38C52[0][B]	Mdu/u_mdu/adder_sum_cry_11_0/COUT
5.333	0.000	tNET	FF	2	R38C52[1][A]	Mdu/u_mdu/adder_sum_cry_12_0/CIN
5.369	0.035	tINS	FF	1	R38C52[1][A]	Mdu/u_mdu/adder_sum_cry_12_0/COUT
5.369	0.000	tNET	FF	2	R38C52[1][B]	Mdu/u_mdu/adder_sum_cry_13_0/CIN
5.404	0.035	tINS	FF	1	R38C52[1][B]	Mdu/u_mdu/adder_sum_cry_13_0/COUT
5.404	0.000	tNET	FF	2	R38C52[2][A]	Mdu/u_mdu/adder_sum_cry_14_0/CIN
5.439	0.035	tINS	FF	1	R38C52[2][A]	Mdu/u_mdu/adder_sum_cry_14_0/COUT
5.439	0.000	tNET	FF	2	R38C52[2][B]	Mdu/u_mdu/adder_sum_cry_15_0/CIN
5.474	0.035	tINS	FF	1	R38C52[2][B]	Mdu/u_mdu/adder_sum_cry_15_0/COUT
5.474	0.000	tNET	FF	2	R38C53[0][A]	Mdu/u_mdu/adder_sum_cry_16_0/CIN
5.509	0.035	tINS	FF	1	R38C53[0][A]	Mdu/u_mdu/adder_sum_cry_16_0/COUT
5.509	0.000	tNET	FF	2	R38C53[0][B]	Mdu/u_mdu/adder_sum_cry_17_0/CIN
5.545	0.035	tINS	FF	1	R38C53[0][B]	Mdu/u_mdu/adder_sum_cry_17_0/COUT
5.545	0.000	tNET	FF	2	R38C53[1][A]	Mdu/u_mdu/adder_sum_cry_18_0/CIN
5.580	0.035	tINS	FF	1	R38C53[1][A]	Mdu/u_mdu/adder_sum_cry_18_0/COUT
5.580	0.000	tNET	FF	2	R38C53[1][B]	Mdu/u_mdu/adder_sum_cry_19_0/CIN
5.615	0.035	tINS	FF	1	R38C53[1][B]	Mdu/u_mdu/adder_sum_cry_19_0/COUT
5.615	0.000	tNET	FF	2	R38C53[2][A]	Mdu/u_mdu/adder_sum_cry_20_0/CIN
5.650	0.035	tINS	FF	1	R38C53[2][A]	Mdu/u_mdu/adder_sum_cry_20_0/COUT
5.650	0.000	tNET	FF	2	R38C53[2][B]	Mdu/u_mdu/adder_sum_cry_21_0/CIN
5.685	0.035	tINS	FF	1	R38C53[2][B]	Mdu/u_mdu/adder_sum_cry_21_0/COUT
5.685	0.000	tNET	FF	2	R38C54[0][A]	Mdu/u_mdu/adder_sum_cry_22_0/CIN
5.721	0.035	tINS	FF	1	R38C54[0][A]	Mdu/u_mdu/adder_sum_cry_22_0/COUT
5.721	0.000	tNET	FF	2	R38C54[0][B]	Mdu/u_mdu/adder_sum_cry_23_0/CIN
5.756	0.035	tINS	FF	1	R38C54[0][B]	Mdu/u_mdu/adder_sum_cry_23_0/COUT
5.756	0.000	tNET	FF	2	R38C54[1][A]	Mdu/u_mdu/adder_sum_cry_24_0/CIN
5.791	0.035	tINS	FF	1	R38C54[1][A]	Mdu/u_mdu/adder_sum_cry_24_0/COUT
5.791	0.000	tNET	FF	2	R38C54[1][B]	Mdu/u_mdu/adder_sum_cry_25_0/CIN
5.826	0.035	tINS	FF	1	R38C54[1][B]	Mdu/u_mdu/adder_sum_cry_25_0/COUT
5.826	0.000	tNET	FF	2	R38C54[2][A]	Mdu/u_mdu/adder_sum_cry_26_0/CIN
5.861	0.035	tINS	FF	1	R38C54[2][A]	Mdu/u_mdu/adder_sum_cry_26_0/COUT
5.861	0.000	tNET	FF	2	R38C54[2][B]	Mdu/u_mdu/adder_sum_cry_27_0/CIN
5.897	0.035	tINS	FF	1	R38C54[2][B]	Mdu/u_mdu/adder_sum_cry_27_0/COUT
5.897	0.000	tNET	FF	2	R38C55[0][A]	Mdu/u_mdu/adder_sum_cry_28_0/CIN
5.932	0.035	tINS	FF	1	R38C55[0][A]	Mdu/u_mdu/adder_sum_cry_28_0/COUT
5.932	0.000	tNET	FF	2	R38C55[0][B]	Mdu/u_mdu/adder_sum_cry_29_0/CIN
5.967	0.035	tINS	FF	1	R38C55[0][B]	Mdu/u_mdu/adder_sum_cry_29_0/COUT
5.967	0.000	tNET	FF	2	R38C55[1][A]	Mdu/u_mdu/adder_sum_cry_30_0/CIN
6.002	0.035	tINS	FF	1	R38C55[1][A]	Mdu/u_mdu/adder_sum_cry_30_0/COUT
6.002	0.000	tNET	FF	2	R38C55[1][B]	Mdu/u_mdu/adder_sum_cry_31_0/CIN
6.037	0.035	tINS	FF	1	R38C55[1][B]	Mdu/u_mdu/adder_sum_cry_31_0/COUT
6.037	0.000	tNET	FF	2	R38C55[2][A]	Mdu/u_mdu/adder_sum_s_32_0/CIN
6.507	0.470	tINS	FF	6	R38C55[2][A]	Mdu/u_mdu/adder_sum_s_32_0/SUM
7.185	0.678	tNET	FF	1	R37C52[3][B]	Mdu/u_mdu/reg0_exe_nx_ss0_cZ/I0
7.702	0.517	tINS	FF	50	R37C52[3][B]	Mdu/u_mdu/reg0_exe_nx_ss0_cZ/F
8.493	0.791	tNET	FF	1	R44C50[2][A]	Mdu/u_mdu/reg0_exe_nx_m1_cZ[7]/I3
8.864	0.371	tINS	FF	1	R44C50[2][A]	Mdu/u_mdu/reg0_exe_nx_m1_cZ[7]/F
9.112	0.247	tNET	FF	1	R46C50[2][A]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[7]/I1
9.483	0.371	tINS	FF	1	R46C50[2][A]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[7]/F
10.138	0.656	tNET	FF	1	R46C49[3][B]	Mdu/u_mdu/reg0_exe_nx_cZ[7]/I3
10.600	0.462	tINS	FR	1	R46C49[3][B]	Mdu/u_mdu/reg0_exe_nx_cZ[7]/F
10.602	0.001	tNET	RR	1	R46C49[1][B]	Mdu/u_mdu/reg0_nx_cZ[7]/I0
11.151	0.549	tINS	RR	1	R46C49[1][B]	Mdu/u_mdu/reg0_nx_cZ[7]/F
11.151	0.000	tNET	RR	1	R46C49[1][B]	Mdu/u_mdu/reg0_Z[7]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	576	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R46C49[1][B]	Mdu/u_mdu/reg0_Z[7]/CLK
11.683	-0.200	tUnc				Mdu/u_mdu/reg0_Z[7]
11.648	-0.035	tSu		1	R46C49[1][B]	Mdu/u_mdu/reg0_Z[7]

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	8
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 4.819, 51.998%; route: 4.217, 45.499%; tC2Q: 0.232, 2.503%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path4

Path Summary:

Slack	0.576
Data Arrival Time	11.073
Data Required Time	11.648
From	Mdu/u_mdu/reg1_Z[1]
To	Mdu/u_mdu/reg0_Z[32]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.683	0.683	tINS	RR	576	IOT48[A]	clk_ibuf/O
1.883	1.201	tNET	RR	1	R34C60[0][B]	Mdu/u_mdu/reg1_Z[1]/CLK
2.115	0.232	tC2Q	RF	8	R34C60[0][B]	Mdu/u_mdu/reg1_Z[1]/Q
3.060	0.945	tNET	FF	1	R35C53[3][A]	Mdu/u_mdu/adder_sum_s_1_sf_lofx_cZ/I1
3.513	0.453	tINS	FF	1	R35C53[3][A]	Mdu/u_mdu/adder_sum_s_1_sf_lofx_cZ/F
4.411	0.899	tNET	FF	2	R38C50[1][B]	Mdu/u_mdu/adder_sum_cry_1_0/I0
4.981	0.570	tINS	FR	1	R38C50[1][B]	Mdu/u_mdu/adder_sum_cry_1_0/COUT
4.981	0.000	tNET	RR	2	R38C50[2][A]	Mdu/u_mdu/adder_sum_cry_2_0/CIN
5.017	0.035	tINS	RF	1	R38C50[2][A]	Mdu/u_mdu/adder_sum_cry_2_0/COUT
5.017	0.000	tNET	FF	2	R38C50[2][B]	Mdu/u_mdu/adder_sum_cry_3_0/CIN
5.052	0.035	tINS	FF	1	R38C50[2][B]	Mdu/u_mdu/adder_sum_cry_3_0/COUT
5.052	0.000	tNET	FF	2	R38C51[0][A]	Mdu/u_mdu/adder_sum_cry_4_0/CIN
5.087	0.035	tINS	FF	1	R38C51[0][A]	Mdu/u_mdu/adder_sum_cry_4_0/COUT
5.087	0.000	tNET	FF	2	R38C51[0][B]	Mdu/u_mdu/adder_sum_cry_5_0/CIN
5.122	0.035	tINS	FF	1	R38C51[0][B]	Mdu/u_mdu/adder_sum_cry_5_0/COUT
5.122	0.000	tNET	FF	2	R38C51[1][A]	Mdu/u_mdu/adder_sum_cry_6_0/CIN
5.157	0.035	tINS	FF	1	R38C51[1][A]	Mdu/u_mdu/adder_sum_cry_6_0/COUT
5.157	0.000	tNET	FF	2	R38C51[1][B]	Mdu/u_mdu/adder_sum_cry_7_0/CIN
5.193	0.035	tINS	FF	1	R38C51[1][B]	Mdu/u_mdu/adder_sum_cry_7_0/COUT
5.193	0.000	tNET	FF	2	R38C51[2][A]	Mdu/u_mdu/adder_sum_cry_8_0/CIN
5.228	0.035	tINS	FF	1	R38C51[2][A]	Mdu/u_mdu/adder_sum_cry_8_0/COUT
5.228	0.000	tNET	FF	2	R38C51[2][B]	Mdu/u_mdu/adder_sum_cry_9_0/CIN
5.263	0.035	tINS	FF	1	R38C51[2][B]	Mdu/u_mdu/adder_sum_cry_9_0/COUT
5.263	0.000	tNET	FF	2	R38C52[0][A]	Mdu/u_mdu/adder_sum_cry_10_0/CIN
5.298	0.035	tINS	FF	1	R38C52[0][A]	Mdu/u_mdu/adder_sum_cry_10_0/COUT
5.298	0.000	tNET	FF	2	R38C52[0][B]	Mdu/u_mdu/adder_sum_cry_11_0/CIN
5.333	0.035	tINS	FF	1	R38C52[0][B]	Mdu/u_mdu/adder_sum_cry_11_0/COUT
5.333	0.000	tNET	FF	2	R38C52[1][A]	Mdu/u_mdu/adder_sum_cry_12_0/CIN
5.369	0.035	tINS	FF	1	R38C52[1][A]	Mdu/u_mdu/adder_sum_cry_12_0/COUT
5.369	0.000	tNET	FF	2	R38C52[1][B]	Mdu/u_mdu/adder_sum_cry_13_0/CIN
5.404	0.035	tINS	FF	1	R38C52[1][B]	Mdu/u_mdu/adder_sum_cry_13_0/COUT
5.404	0.000	tNET	FF	2	R38C52[2][A]	Mdu/u_mdu/adder_sum_cry_14_0/CIN
5.439	0.035	tINS	FF	1	R38C52[2][A]	Mdu/u_mdu/adder_sum_cry_14_0/COUT
5.439	0.000	tNET	FF	2	R38C52[2][B]	Mdu/u_mdu/adder_sum_cry_15_0/CIN
5.474	0.035	tINS	FF	1	R38C52[2][B]	Mdu/u_mdu/adder_sum_cry_15_0/COUT
5.474	0.000	tNET	FF	2	R38C53[0][A]	Mdu/u_mdu/adder_sum_cry_16_0/CIN
5.509	0.035	tINS	FF	1	R38C53[0][A]	Mdu/u_mdu/adder_sum_cry_16_0/COUT
5.509	0.000	tNET	FF	2	R38C53[0][B]	Mdu/u_mdu/adder_sum_cry_17_0/CIN
5.545	0.035	tINS	FF	1	R38C53[0][B]	Mdu/u_mdu/adder_sum_cry_17_0/COUT
5.545	0.000	tNET	FF	2	R38C53[1][A]	Mdu/u_mdu/adder_sum_cry_18_0/CIN
5.580	0.035	tINS	FF	1	R38C53[1][A]	Mdu/u_mdu/adder_sum_cry_18_0/COUT
5.580	0.000	tNET	FF	2	R38C53[1][B]	Mdu/u_mdu/adder_sum_cry_19_0/CIN
5.615	0.035	tINS	FF	1	R38C53[1][B]	Mdu/u_mdu/adder_sum_cry_19_0/COUT
5.615	0.000	tNET	FF	2	R38C53[2][A]	Mdu/u_mdu/adder_sum_cry_20_0/CIN
5.650	0.035	tINS	FF	1	R38C53[2][A]	Mdu/u_mdu/adder_sum_cry_20_0/COUT
5.650	0.000	tNET	FF	2	R38C53[2][B]	Mdu/u_mdu/adder_sum_cry_21_0/CIN
5.685	0.035	tINS	FF	1	R38C53[2][B]	Mdu/u_mdu/adder_sum_cry_21_0/COUT
5.685	0.000	tNET	FF	2	R38C54[0][A]	Mdu/u_mdu/adder_sum_cry_22_0/CIN
5.721	0.035	tINS	FF	1	R38C54[0][A]	Mdu/u_mdu/adder_sum_cry_22_0/COUT
5.721	0.000	tNET	FF	2	R38C54[0][B]	Mdu/u_mdu/adder_sum_cry_23_0/CIN
5.756	0.035	tINS	FF	1	R38C54[0][B]	Mdu/u_mdu/adder_sum_cry_23_0/COUT
5.756	0.000	tNET	FF	2	R38C54[1][A]	Mdu/u_mdu/adder_sum_cry_24_0/CIN
5.791	0.035	tINS	FF	1	R38C54[1][A]	Mdu/u_mdu/adder_sum_cry_24_0/COUT
5.791	0.000	tNET	FF	2	R38C54[1][B]	Mdu/u_mdu/adder_sum_cry_25_0/CIN
5.826	0.035	tINS	FF	1	R38C54[1][B]	Mdu/u_mdu/adder_sum_cry_25_0/COUT
5.826	0.000	tNET	FF	2	R38C54[2][A]	Mdu/u_mdu/adder_sum_cry_26_0/CIN
5.861	0.035	tINS	FF	1	R38C54[2][A]	Mdu/u_mdu/adder_sum_cry_26_0/COUT
5.861	0.000	tNET	FF	2	R38C54[2][B]	Mdu/u_mdu/adder_sum_cry_27_0/CIN
5.897	0.035	tINS	FF	1	R38C54[2][B]	Mdu/u_mdu/adder_sum_cry_27_0/COUT
5.897	0.000	tNET	FF	2	R38C55[0][A]	Mdu/u_mdu/adder_sum_cry_28_0/CIN
5.932	0.035	tINS	FF	1	R38C55[0][A]	Mdu/u_mdu/adder_sum_cry_28_0/COUT
5.932	0.000	tNET	FF	2	R38C55[0][B]	Mdu/u_mdu/adder_sum_cry_29_0/CIN
5.967	0.035	tINS	FF	1	R38C55[0][B]	Mdu/u_mdu/adder_sum_cry_29_0/COUT
5.967	0.000	tNET	FF	2	R38C55[1][A]	Mdu/u_mdu/adder_sum_cry_30_0/CIN
6.002	0.035	tINS	FF	1	R38C55[1][A]	Mdu/u_mdu/adder_sum_cry_30_0/COUT
6.002	0.000	tNET	FF	2	R38C55[1][B]	Mdu/u_mdu/adder_sum_cry_31_0/CIN
6.037	0.035	tINS	FF	1	R38C55[1][B]	Mdu/u_mdu/adder_sum_cry_31_0/COUT
6.037	0.000	tNET	FF	2	R38C55[2][A]	Mdu/u_mdu/adder_sum_s_32_0/CIN
6.507	0.470	tINS	FF	6	R38C55[2][A]	Mdu/u_mdu/adder_sum_s_32_0/SUM
7.185	0.678	tNET	FF	1	R37C52[3][B]	Mdu/u_mdu/reg0_exe_nx_ss0_cZ/I0
7.702	0.517	tINS	FF	50	R37C52[3][B]	Mdu/u_mdu/reg0_exe_nx_ss0_cZ/F
8.251	0.548	tNET	FF	1	R46C50[0][A]	Mdu/u_mdu/reg0_exe_nx_m1_cZ[32]/I3
8.704	0.453	tINS	FF	1	R46C50[0][A]	Mdu/u_mdu/reg0_exe_nx_m1_cZ[32]/F
9.809	1.105	tNET	FF	1	R47C47[3][A]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[32]/I1
10.364	0.555	tINS	FF	1	R47C47[3][A]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[32]/F
10.611	0.247	tNET	FF	1	R47C45[1][B]	Mdu/u_mdu/reg0_nx_cZ[32]/I0
11.073	0.462	tINS	FR	1	R47C45[1][B]	Mdu/u_mdu/reg0_nx_cZ[32]/F
11.073	0.000	tNET	RR	1	R47C45[1][B]	Mdu/u_mdu/reg0_Z[32]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	576	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R47C45[1][B]	Mdu/u_mdu/reg0_Z[32]/CLK
11.683	-0.200	tUnc				Mdu/u_mdu/reg0_Z[32]
11.648	-0.035	tSu		1	R47C45[1][B]	Mdu/u_mdu/reg0_Z[32]

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 4.536, 49.361%; route: 4.421, 48.115%; tC2Q: 0.232, 2.525%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path5

Path Summary:

Slack	0.688
Data Arrival Time	10.960
Data Required Time	11.648
From	Mdu/u_mdu/reg0_Z[10]
To	Mdu/u_mdu/reg0_Z[31]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.683	0.683	tINS	RR	576	IOT48[A]	clk_ibuf/O
1.883	1.201	tNET	RR	1	R41C44[2][B]	Mdu/u_mdu/reg0_Z[10]/CLK
2.115	0.232	tC2Q	RF	11	R41C44[2][B]	Mdu/u_mdu/reg0_Z[10]/Q
3.431	1.316	tNET	FF	1	R46C58[2][B]	Mdu/u_mdu/m11_0_03_1_cZ/I3
3.980	0.549	tINS	FR	1	R46C58[2][B]	Mdu/u_mdu/m11_0_03_1_cZ/F
3.982	0.001	tNET	RR	1	R46C58[2][A]	Mdu/u_mdu/m11_0_03_cZ/I1
4.499	0.517	tINS	RF	4	R46C58[2][A]	Mdu/u_mdu/m11_0_03_cZ/F
5.318	0.819	tNET	FF	1	R44C59[0][B]	Mdu/u_mdu/m15_2_03_1_0_cZ/I2
5.689	0.371	tINS	FF	2	R44C59[0][B]	Mdu/u_mdu/m15_2_03_1_0_cZ/F
5.698	0.009	tNET	FF	1	R44C59[3][A]	Mdu/u_mdu/m15_2_03_0_0_RNI9I0C/I1
6.253	0.555	tINS	FF	3	R44C59[3][A]	Mdu/u_mdu/m15_2_03_0_0_RNI9I0C/F
7.188	0.936	tNET	FF	1	R47C53[2][A]	Mdu/u_mdu/m31_4_01_cZ/I1
7.641	0.453	tINS	FF	1	R47C53[2][A]	Mdu/u_mdu/m31_4_01_cZ/F
8.491	0.850	tNET	FF	1	R35C53[1][B]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[31]/I2
9.061	0.570	tINS	FR	1	R35C53[1][B]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[31]/F
9.234	0.172	tNET	RR	1	R35C52[3][A]	Mdu/u_mdu/reg0_exe_nx_cZ[31]/I3
9.751	0.517	tINS	RF	3	R35C52[3][A]	Mdu/u_mdu/reg0_exe_nx_cZ[31]/F
10.411	0.660	tNET	FF	1	R33C49[0][B]	Mdu/u_mdu/reg0_nx_cZ[31]/I0
10.960	0.549	tINS	FR	1	R33C49[0][B]	Mdu/u_mdu/reg0_nx_cZ[31]/F
10.960	0.000	tNET	RR	1	R33C49[0][B]	Mdu/u_mdu/reg0_Z[31]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	576	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R33C49[0][B]	Mdu/u_mdu/reg0_Z[31]/CLK
11.683	-0.200	tUnc				Mdu/u_mdu/reg0_Z[31]
11.648	-0.035	tSu		1	R33C49[0][B]	Mdu/u_mdu/reg0_Z[31]

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	8
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 4.081, 44.961%; route: 4.764, 52.483%; tC2Q: 0.232, 2.556%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path6

Path Summary:

Slack	0.688
Data Arrival Time	10.960
Data Required Time	11.648
From	Mdu/u_mdu/reg0_Z[3]
To	Mdu/u_mdu/reg0_fast_Z[28]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.683	0.683	tINS	RR	576	IOT48[A]	clk_ibuf/O
1.883	1.201	tNET	RR	1	R39C48[0][A]	Mdu/u_mdu/reg0_Z[3]/CLK
2.115	0.232	tC2Q	RF	12	R39C48[0][A]	Mdu/u_mdu/reg0_Z[3]/Q
3.182	1.067	tNET	FF	1	R46C55[0][A]	Mdu/u_mdu/m4_0_03_1_0_cZ/I2
3.553	0.371	tINS	FF	2	R46C55[0][A]	Mdu/u_mdu/m4_0_03_1_0_cZ/F
4.049	0.496	tNET	FF	1	R46C59[1][B]	Mdu/u_mdu/m4_0_03_0_0_RNI1JV1/I1
4.604	0.555	tINS	FF	3	R46C59[1][B]	Mdu/u_mdu/m4_0_03_0_0_RNI1JV1/F
5.511	0.908	tNET	FF	1	R47C54[1][B]	Mdu/u_mdu/m12_2_03_m1_e_1_cZ/I1
6.060	0.549	tINS	FR	2	R47C54[1][B]	Mdu/u_mdu/m12_2_03_m1_e_1_cZ/F
6.063	0.003	tNET	RR	1	R47C54[2][B]	Mdu/u_mdu/m12_2_03_m1_e_0_RNI7HT5/I1
6.618	0.555	tINS	RF	3	R47C54[2][B]	Mdu/u_mdu/m12_2_03_m1_e_0_RNI7HT5/F
7.041	0.423	tNET	FF	1	R44C54[1][A]	Mdu/u_mdu/m28_4_01_cZ/I1
7.596	0.555	tINS	FF	1	R44C54[1][A]	Mdu/u_mdu/m28_4_01_cZ/F
8.159	0.563	tNET	FF	1	R41C54[3][B]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[28]/I2
8.714	0.555	tINS	FF	1	R41C54[3][B]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[28]/F
9.204	0.490	tNET	FF	1	R41C50[2][A]	Mdu/u_mdu/reg0_exe_nx_cZ[28]/I3
9.721	0.517	tINS	FF	2	R41C50[2][A]	Mdu/u_mdu/reg0_exe_nx_cZ[28]/F
10.411	0.690	tNET	FF	1	R46C49[0][A]	Mdu/u_mdu/reg0_nx_fast_cZ[28]/I0
10.960	0.549	tINS	FR	1	R46C49[0][A]	Mdu/u_mdu/reg0_nx_fast_cZ[28]/F
10.960	0.000	tNET	RR	1	R46C49[0][A]	Mdu/u_mdu/reg0_fast_Z[28]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	576	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R46C49[0][A]	Mdu/u_mdu/reg0_fast_Z[28]/CLK
11.683	-0.200	tUnc				Mdu/u_mdu/reg0_fast_Z[28]
11.648	-0.035	tSu		1	R46C49[0][A]	Mdu/u_mdu/reg0_fast_Z[28]

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	8
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 4.206, 46.338%; route: 4.639, 51.106%; tC2Q: 0.232, 2.556%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path7

Path Summary:

Slack	0.688
Data Arrival Time	10.960
Data Required Time	11.648
From	Mdu/u_mdu/reg0_Z[3]
To	Mdu/u_mdu/reg0_Z[28]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.683	0.683	tINS	RR	576	IOT48[A]	clk_ibuf/O
1.883	1.201	tNET	RR	1	R39C48[0][A]	Mdu/u_mdu/reg0_Z[3]/CLK
2.115	0.232	tC2Q	RF	12	R39C48[0][A]	Mdu/u_mdu/reg0_Z[3]/Q
3.182	1.067	tNET	FF	1	R46C55[0][A]	Mdu/u_mdu/m4_0_03_1_0_cZ/I2
3.553	0.371	tINS	FF	2	R46C55[0][A]	Mdu/u_mdu/m4_0_03_1_0_cZ/F
4.049	0.496	tNET	FF	1	R46C59[1][B]	Mdu/u_mdu/m4_0_03_0_0_RNI1JV1/I1
4.604	0.555	tINS	FF	3	R46C59[1][B]	Mdu/u_mdu/m4_0_03_0_0_RNI1JV1/F
5.511	0.908	tNET	FF	1	R47C54[1][B]	Mdu/u_mdu/m12_2_03_m1_e_1_cZ/I1
6.060	0.549	tINS	FR	2	R47C54[1][B]	Mdu/u_mdu/m12_2_03_m1_e_1_cZ/F
6.063	0.003	tNET	RR	1	R47C54[2][B]	Mdu/u_mdu/m12_2_03_m1_e_0_RNI7HT5/I1
6.618	0.555	tINS	RF	3	R47C54[2][B]	Mdu/u_mdu/m12_2_03_m1_e_0_RNI7HT5/F
7.041	0.423	tNET	FF	1	R44C54[1][A]	Mdu/u_mdu/m28_4_01_cZ/I1
7.596	0.555	tINS	FF	1	R44C54[1][A]	Mdu/u_mdu/m28_4_01_cZ/F
8.159	0.563	tNET	FF	1	R41C54[3][B]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[28]/I2
8.714	0.555	tINS	FF	1	R41C54[3][B]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[28]/F
9.204	0.490	tNET	FF	1	R41C50[2][A]	Mdu/u_mdu/reg0_exe_nx_cZ[28]/I3
9.721	0.517	tINS	FF	2	R41C50[2][A]	Mdu/u_mdu/reg0_exe_nx_cZ[28]/F
10.411	0.690	tNET	FF	1	R46C49[1][A]	Mdu/u_mdu/reg0_nx_cZ[28]/I0
10.960	0.549	tINS	FR	1	R46C49[1][A]	Mdu/u_mdu/reg0_nx_cZ[28]/F
10.960	0.000	tNET	RR	1	R46C49[1][A]	Mdu/u_mdu/reg0_Z[28]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	576	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R46C49[1][A]	Mdu/u_mdu/reg0_Z[28]/CLK
11.683	-0.200	tUnc				Mdu/u_mdu/reg0_Z[28]
11.648	-0.035	tSu		1	R46C49[1][A]	Mdu/u_mdu/reg0_Z[28]

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	8
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 4.206, 46.338%; route: 4.639, 51.106%; tC2Q: 0.232, 2.556%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path8

Path Summary:

Slack	0.744
Data Arrival Time	10.904
Data Required Time	11.648
From	Mdu/u_mdu/reg0_fast_Z[4]
To	memq_memq_0_9
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.683	0.683	tINS	RR	576	IOT48[A]	clk_ibuf/O
1.883	1.201	tNET	RR	1	R48C45[1][B]	Mdu/u_mdu/reg0_fast_Z[4]/CLK
2.115	0.232	tC2Q	RF	7	R48C45[1][B]	Mdu/u_mdu/reg0_fast_Z[4]/Q
3.081	0.966	tNET	FF	1	R42C50[3][A]	Mdu/u_mdu/reg0_neg_axb_4_par_0_cp_0_cZ/I2
3.598	0.517	tINS	FF	1	R42C50[3][A]	Mdu/u_mdu/reg0_neg_axb_4_par_0_cp_0_cZ/F
4.497	0.899	tNET	FF	2	R42C53[1][B]	Mdu/u_mdu/reg0_neg_axb_4_par_cp_0_0/I0
5.067	0.570	tINS	FR	1	R42C53[1][B]	Mdu/u_mdu/reg0_neg_axb_4_par_cp_0_0/COUT
5.067	0.000	tNET	RR	2	R42C53[2][A]	Mdu/u_mdu/reg0_neg_axb_8_par_cp_1/CIN
5.102	0.035	tINS	RF	1	R42C53[2][A]	Mdu/u_mdu/reg0_neg_axb_8_par_cp_1/COUT
5.102	0.000	tNET	FF	2	R42C53[2][B]	Mdu/u_mdu/reg0_neg_axb_12_par_cp_1/CIN
5.137	0.035	tINS	FF	1	R42C53[2][B]	Mdu/u_mdu/reg0_neg_axb_12_par_cp_1/COUT
5.137	0.000	tNET	FF	2	R42C54[0][A]	Mdu/u_mdu/reg0_neg_axb_16_par_cp_1/CIN
5.173	0.035	tINS	FF	1	R42C54[0][A]	Mdu/u_mdu/reg0_neg_axb_16_par_cp_1/COUT
5.173	0.000	tNET	FF	2	R42C54[0][B]	Mdu/u_mdu/reg0_neg_axb_19_par_1/CIN
5.208	0.035	tINS	FF	1	R42C54[0][B]	Mdu/u_mdu/reg0_neg_axb_19_par_1/COUT
5.208	0.000	tNET	FF	2	R42C54[1][A]	Mdu/u_mdu/reg0_neg_axb_23_par_1/CIN
5.243	0.035	tINS	FF	1	R42C54[1][A]	Mdu/u_mdu/reg0_neg_axb_23_par_1/COUT
5.243	0.000	tNET	FF	2	R42C54[1][B]	Mdu/u_mdu/reg0_neg_axb_27_par_1/CIN
5.278	0.035	tINS	FF	1	R42C54[1][B]	Mdu/u_mdu/reg0_neg_axb_27_par_1/COUT
5.278	0.000	tNET	FF	2	R42C54[2][A]	Mdu/u_mdu/reg0_neg_axb_31_par_1/CIN
5.313	0.035	tINS	FF	1	R42C54[2][A]	Mdu/u_mdu/reg0_neg_axb_31_par_1/COUT
5.313	0.000	tNET	FF	2	R42C54[2][B]	Mdu/u_mdu/reg0_neg_cry_34_0/CIN
5.349	0.035	tINS	FF	1	R42C54[2][B]	Mdu/u_mdu/reg0_neg_cry_34_0/COUT
5.349	0.000	tNET	FF	2	R42C55[0][A]	Mdu/u_mdu/reg0_neg_cry_35_0/CIN
5.384	0.035	tINS	FF	1	R42C55[0][A]	Mdu/u_mdu/reg0_neg_cry_35_0/COUT
5.384	0.000	tNET	FF	2	R42C55[0][B]	Mdu/u_mdu/reg0_neg_cry_36_0/CIN
5.419	0.035	tINS	FF	1	R42C55[0][B]	Mdu/u_mdu/reg0_neg_cry_36_0/COUT
5.419	0.000	tNET	FF	2	R42C55[1][A]	Mdu/u_mdu/reg0_neg_cry_37_0/CIN
5.454	0.035	tINS	FF	1	R42C55[1][A]	Mdu/u_mdu/reg0_neg_cry_37_0/COUT
5.454	0.000	tNET	FF	2	R42C55[1][B]	Mdu/u_mdu/reg0_neg_cry_38_0/CIN
5.489	0.035	tINS	FF	1	R42C55[1][B]	Mdu/u_mdu/reg0_neg_cry_38_0/COUT
5.489	0.000	tNET	FF	2	R42C55[2][A]	Mdu/u_mdu/reg0_neg_cry_39_0/CIN
5.525	0.035	tINS	FF	1	R42C55[2][A]	Mdu/u_mdu/reg0_neg_cry_39_0/COUT
5.525	0.000	tNET	FF	2	R42C55[2][B]	Mdu/u_mdu/reg0_neg_cry_40_0/CIN
5.560	0.035	tINS	FF	1	R42C55[2][B]	Mdu/u_mdu/reg0_neg_cry_40_0/COUT
5.560	0.000	tNET	FF	2	R42C56[0][A]	Mdu/u_mdu/reg0_neg_cry_41_0/CIN
5.595	0.035	tINS	FF	1	R42C56[0][A]	Mdu/u_mdu/reg0_neg_cry_41_0/COUT
5.595	0.000	tNET	FF	2	R42C56[0][B]	Mdu/u_mdu/reg0_neg_cry_42_0/CIN
5.630	0.035	tINS	FF	1	R42C56[0][B]	Mdu/u_mdu/reg0_neg_cry_42_0/COUT
5.630	0.000	tNET	FF	2	R42C56[1][A]	Mdu/u_mdu/reg0_neg_cry_43_0/CIN
5.665	0.035	tINS	FF	1	R42C56[1][A]	Mdu/u_mdu/reg0_neg_cry_43_0/COUT
5.665	0.000	tNET	FF	2	R42C56[1][B]	Mdu/u_mdu/reg0_neg_cry_44_0/CIN
5.701	0.035	tINS	FF	1	R42C56[1][B]	Mdu/u_mdu/reg0_neg_cry_44_0/COUT
5.701	0.000	tNET	FF	2	R42C56[2][A]	Mdu/u_mdu/reg0_neg_cry_45_0/CIN
5.736	0.035	tINS	FF	1	R42C56[2][A]	Mdu/u_mdu/reg0_neg_cry_45_0/COUT
5.736	0.000	tNET	FF	2	R42C56[2][B]	Mdu/u_mdu/reg0_neg_cry_46_0/CIN
5.771	0.035	tINS	FF	1	R42C56[2][B]	Mdu/u_mdu/reg0_neg_cry_46_0/COUT
5.771	0.000	tNET	FF	2	R42C57[0][A]	Mdu/u_mdu/reg0_neg_cry_47_0/CIN
5.806	0.035	tINS	FF	1	R42C57[0][A]	Mdu/u_mdu/reg0_neg_cry_47_0/COUT
5.806	0.000	tNET	FF	2	R42C57[0][B]	Mdu/u_mdu/reg0_neg_cry_48_0/CIN
5.841	0.035	tINS	FF	1	R42C57[0][B]	Mdu/u_mdu/reg0_neg_cry_48_0/COUT
5.841	0.000	tNET	FF	2	R42C57[1][A]	Mdu/u_mdu/reg0_neg_cry_49_0/CIN
5.877	0.035	tINS	FF	1	R42C57[1][A]	Mdu/u_mdu/reg0_neg_cry_49_0/COUT
5.877	0.000	tNET	FF	2	R42C57[1][B]	Mdu/u_mdu/reg0_neg_cry_50_0/CIN
6.347	0.470	tINS	FF	1	R42C57[1][B]	Mdu/u_mdu/reg0_neg_cry_50_0/SUM
7.135	0.789	tNET	FF	1	R34C48[3][A]	Mdu/u_mdu/reg0_post_swap_2[18]/I2
7.506	0.371	tINS	FF	1	R34C48[3][A]	Mdu/u_mdu/reg0_post_swap_2[18]/F
7.506	0.000	tNET	FF	1	R34C48[3][A]	Mdu/u_mdu/reg0_post_swap_4[18]/I0
7.609	0.103	tINS	FF	2	R34C48[3][A]	Mdu/u_mdu/reg0_post_swap_4[18]/O
8.520	0.910	tNET	FF	1	R34C48[0][A]	Mdu/u_mdu/reg0_post_swap_5[18]/I1
8.973	0.453	tINS	FF	1	R34C48[0][A]	Mdu/u_mdu/reg0_post_swap_5[18]/F
9.386	0.413	tNET	FF	1	R33C47[3][A]	Mdu/u_mdu/res0_cZ[18]/I1
9.941	0.555	tINS	FF	3	R33C47[3][A]	Mdu/u_mdu/res0_cZ[18]/F
10.904	0.964	tNET	FF	1	BSRAM_R45[14]	memq_memq_0_9/DI0

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	576	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	BSRAM_R45[14]	memq_memq_0_9/CLKA
11.683	-0.200	tUnc				memq_memq_0_9
11.648	-0.035	tSu		1	BSRAM_R45[14]	memq_memq_0_9

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 3.849, 42.661%; route: 4.941, 54.767%; tC2Q: 0.232, 2.572%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path9

Path Summary:

Slack	0.853
Data Arrival Time	10.795
Data Required Time	11.648
From	Mdu/u_mdu/reg1_Z[1]
To	Mdu/u_mdu/reg0_Z[37]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.683	0.683	tINS	RR	576	IOT48[A]	clk_ibuf/O
1.883	1.201	tNET	RR	1	R34C60[0][B]	Mdu/u_mdu/reg1_Z[1]/CLK
2.115	0.232	tC2Q	RF	8	R34C60[0][B]	Mdu/u_mdu/reg1_Z[1]/Q
3.060	0.945	tNET	FF	1	R35C53[3][A]	Mdu/u_mdu/adder_sum_s_1_sf_lofx_cZ/I1
3.513	0.453	tINS	FF	1	R35C53[3][A]	Mdu/u_mdu/adder_sum_s_1_sf_lofx_cZ/F
4.411	0.899	tNET	FF	2	R38C50[1][B]	Mdu/u_mdu/adder_sum_cry_1_0/I0
4.981	0.570	tINS	FR	1	R38C50[1][B]	Mdu/u_mdu/adder_sum_cry_1_0/COUT
4.981	0.000	tNET	RR	2	R38C50[2][A]	Mdu/u_mdu/adder_sum_cry_2_0/CIN
5.017	0.035	tINS	RF	1	R38C50[2][A]	Mdu/u_mdu/adder_sum_cry_2_0/COUT
5.017	0.000	tNET	FF	2	R38C50[2][B]	Mdu/u_mdu/adder_sum_cry_3_0/CIN
5.052	0.035	tINS	FF	1	R38C50[2][B]	Mdu/u_mdu/adder_sum_cry_3_0/COUT
5.052	0.000	tNET	FF	2	R38C51[0][A]	Mdu/u_mdu/adder_sum_cry_4_0/CIN
5.087	0.035	tINS	FF	1	R38C51[0][A]	Mdu/u_mdu/adder_sum_cry_4_0/COUT
5.087	0.000	tNET	FF	2	R38C51[0][B]	Mdu/u_mdu/adder_sum_cry_5_0/CIN
5.122	0.035	tINS	FF	1	R38C51[0][B]	Mdu/u_mdu/adder_sum_cry_5_0/COUT
5.122	0.000	tNET	FF	2	R38C51[1][A]	Mdu/u_mdu/adder_sum_cry_6_0/CIN
5.157	0.035	tINS	FF	1	R38C51[1][A]	Mdu/u_mdu/adder_sum_cry_6_0/COUT
5.157	0.000	tNET	FF	2	R38C51[1][B]	Mdu/u_mdu/adder_sum_cry_7_0/CIN
5.193	0.035	tINS	FF	1	R38C51[1][B]	Mdu/u_mdu/adder_sum_cry_7_0/COUT
5.193	0.000	tNET	FF	2	R38C51[2][A]	Mdu/u_mdu/adder_sum_cry_8_0/CIN
5.228	0.035	tINS	FF	1	R38C51[2][A]	Mdu/u_mdu/adder_sum_cry_8_0/COUT
5.228	0.000	tNET	FF	2	R38C51[2][B]	Mdu/u_mdu/adder_sum_cry_9_0/CIN
5.263	0.035	tINS	FF	1	R38C51[2][B]	Mdu/u_mdu/adder_sum_cry_9_0/COUT
5.263	0.000	tNET	FF	2	R38C52[0][A]	Mdu/u_mdu/adder_sum_cry_10_0/CIN
5.298	0.035	tINS	FF	1	R38C52[0][A]	Mdu/u_mdu/adder_sum_cry_10_0/COUT
5.298	0.000	tNET	FF	2	R38C52[0][B]	Mdu/u_mdu/adder_sum_cry_11_0/CIN
5.333	0.035	tINS	FF	1	R38C52[0][B]	Mdu/u_mdu/adder_sum_cry_11_0/COUT
5.333	0.000	tNET	FF	2	R38C52[1][A]	Mdu/u_mdu/adder_sum_cry_12_0/CIN
5.369	0.035	tINS	FF	1	R38C52[1][A]	Mdu/u_mdu/adder_sum_cry_12_0/COUT
5.369	0.000	tNET	FF	2	R38C52[1][B]	Mdu/u_mdu/adder_sum_cry_13_0/CIN
5.404	0.035	tINS	FF	1	R38C52[1][B]	Mdu/u_mdu/adder_sum_cry_13_0/COUT
5.404	0.000	tNET	FF	2	R38C52[2][A]	Mdu/u_mdu/adder_sum_cry_14_0/CIN
5.439	0.035	tINS	FF	1	R38C52[2][A]	Mdu/u_mdu/adder_sum_cry_14_0/COUT
5.439	0.000	tNET	FF	2	R38C52[2][B]	Mdu/u_mdu/adder_sum_cry_15_0/CIN
5.474	0.035	tINS	FF	1	R38C52[2][B]	Mdu/u_mdu/adder_sum_cry_15_0/COUT
5.474	0.000	tNET	FF	2	R38C53[0][A]	Mdu/u_mdu/adder_sum_cry_16_0/CIN
5.509	0.035	tINS	FF	1	R38C53[0][A]	Mdu/u_mdu/adder_sum_cry_16_0/COUT
5.509	0.000	tNET	FF	2	R38C53[0][B]	Mdu/u_mdu/adder_sum_cry_17_0/CIN
5.545	0.035	tINS	FF	1	R38C53[0][B]	Mdu/u_mdu/adder_sum_cry_17_0/COUT
5.545	0.000	tNET	FF	2	R38C53[1][A]	Mdu/u_mdu/adder_sum_cry_18_0/CIN
5.580	0.035	tINS	FF	1	R38C53[1][A]	Mdu/u_mdu/adder_sum_cry_18_0/COUT
5.580	0.000	tNET	FF	2	R38C53[1][B]	Mdu/u_mdu/adder_sum_cry_19_0/CIN
5.615	0.035	tINS	FF	1	R38C53[1][B]	Mdu/u_mdu/adder_sum_cry_19_0/COUT
5.615	0.000	tNET	FF	2	R38C53[2][A]	Mdu/u_mdu/adder_sum_cry_20_0/CIN
5.650	0.035	tINS	FF	1	R38C53[2][A]	Mdu/u_mdu/adder_sum_cry_20_0/COUT
5.650	0.000	tNET	FF	2	R38C53[2][B]	Mdu/u_mdu/adder_sum_cry_21_0/CIN
5.685	0.035	tINS	FF	1	R38C53[2][B]	Mdu/u_mdu/adder_sum_cry_21_0/COUT
5.685	0.000	tNET	FF	2	R38C54[0][A]	Mdu/u_mdu/adder_sum_cry_22_0/CIN
5.721	0.035	tINS	FF	1	R38C54[0][A]	Mdu/u_mdu/adder_sum_cry_22_0/COUT
5.721	0.000	tNET	FF	2	R38C54[0][B]	Mdu/u_mdu/adder_sum_cry_23_0/CIN
5.756	0.035	tINS	FF	1	R38C54[0][B]	Mdu/u_mdu/adder_sum_cry_23_0/COUT
5.756	0.000	tNET	FF	2	R38C54[1][A]	Mdu/u_mdu/adder_sum_cry_24_0/CIN
5.791	0.035	tINS	FF	1	R38C54[1][A]	Mdu/u_mdu/adder_sum_cry_24_0/COUT
5.791	0.000	tNET	FF	2	R38C54[1][B]	Mdu/u_mdu/adder_sum_cry_25_0/CIN
5.826	0.035	tINS	FF	1	R38C54[1][B]	Mdu/u_mdu/adder_sum_cry_25_0/COUT
5.826	0.000	tNET	FF	2	R38C54[2][A]	Mdu/u_mdu/adder_sum_cry_26_0/CIN
5.861	0.035	tINS	FF	1	R38C54[2][A]	Mdu/u_mdu/adder_sum_cry_26_0/COUT
5.861	0.000	tNET	FF	2	R38C54[2][B]	Mdu/u_mdu/adder_sum_cry_27_0/CIN
5.897	0.035	tINS	FF	1	R38C54[2][B]	Mdu/u_mdu/adder_sum_cry_27_0/COUT
5.897	0.000	tNET	FF	2	R38C55[0][A]	Mdu/u_mdu/adder_sum_cry_28_0/CIN
5.932	0.035	tINS	FF	1	R38C55[0][A]	Mdu/u_mdu/adder_sum_cry_28_0/COUT
5.932	0.000	tNET	FF	2	R38C55[0][B]	Mdu/u_mdu/adder_sum_cry_29_0/CIN
5.967	0.035	tINS	FF	1	R38C55[0][B]	Mdu/u_mdu/adder_sum_cry_29_0/COUT
5.967	0.000	tNET	FF	2	R38C55[1][A]	Mdu/u_mdu/adder_sum_cry_30_0/CIN
6.002	0.035	tINS	FF	1	R38C55[1][A]	Mdu/u_mdu/adder_sum_cry_30_0/COUT
6.002	0.000	tNET	FF	2	R38C55[1][B]	Mdu/u_mdu/adder_sum_cry_31_0/CIN
6.037	0.035	tINS	FF	1	R38C55[1][B]	Mdu/u_mdu/adder_sum_cry_31_0/COUT
6.037	0.000	tNET	FF	2	R38C55[2][A]	Mdu/u_mdu/adder_sum_s_32_0/CIN
6.507	0.470	tINS	FF	6	R38C55[2][A]	Mdu/u_mdu/adder_sum_s_32_0/SUM
7.185	0.678	tNET	FF	1	R37C52[3][B]	Mdu/u_mdu/reg0_exe_nx_ss0_cZ/I0
7.734	0.549	tINS	FR	50	R37C52[3][B]	Mdu/u_mdu/reg0_exe_nx_ss0_cZ/F
8.186	0.452	tNET	RR	1	R43C53[2][A]	Mdu/u_mdu/reg0_exe_nx_m0_cZ[37]/I2
8.741	0.555	tINS	RF	1	R43C53[2][A]	Mdu/u_mdu/reg0_exe_nx_m0_cZ[37]/F
8.741	0.000	tNET	FF	1	R43C53[2][A]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[37]/I0
8.844	0.103	tINS	FF	1	R43C53[2][A]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[37]/O
10.246	1.402	tNET	FF	1	R43C53[0][B]	Mdu/u_mdu/reg0_nx_cZ[37]/I0
10.795	0.549	tINS	FR	1	R43C53[0][B]	Mdu/u_mdu/reg0_nx_cZ[37]/F
10.795	0.000	tNET	RR	1	R43C53[0][B]	Mdu/u_mdu/reg0_Z[37]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	576	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R43C53[0][B]	Mdu/u_mdu/reg0_Z[37]/CLK
11.683	-0.200	tUnc				Mdu/u_mdu/reg0_Z[37]
11.648	-0.035	tSu		1	R43C53[0][B]	Mdu/u_mdu/reg0_Z[37]

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 4.305, 48.307%; route: 4.375, 49.090%; tC2Q: 0.232, 2.603%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path10

Path Summary:

Slack	0.860
Data Arrival Time	10.789
Data Required Time	11.648
From	Mdu/u_mdu/reg0_fast_Z[20]
To	memq_memq_0_15
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.683	0.683	tINS	RR	576	IOT48[A]	clk_ibuf/O
1.883	1.201	tNET	RR	1	R43C48[0][B]	Mdu/u_mdu/reg0_fast_Z[20]/CLK
2.115	0.232	tC2Q	RF	5	R43C48[0][B]	Mdu/u_mdu/reg0_fast_Z[20]/Q
3.488	1.373	tNET	FF	1	R41C49[2][B]	Mdu/u_mdu/reg0_neg_axb_19_par_0_cp_cZ/I3
4.005	0.517	tINS	FF	1	R41C49[2][B]	Mdu/u_mdu/reg0_neg_axb_19_par_0_cp_cZ/F
4.689	0.684	tNET	FF	2	R34C50[0][B]	Mdu/u_mdu/reg0_neg_axb_19_par_cp_0/I0
5.259	0.570	tINS	FR	1	R34C50[0][B]	Mdu/u_mdu/reg0_neg_axb_19_par_cp_0/COUT
5.259	0.000	tNET	RR	2	R34C50[1][A]	Mdu/u_mdu/reg0_neg_axb_23_par_cp_0/CIN
5.294	0.035	tINS	RF	1	R34C50[1][A]	Mdu/u_mdu/reg0_neg_axb_23_par_cp_0/COUT
5.294	0.000	tNET	FF	2	R34C50[1][B]	Mdu/u_mdu/reg0_neg_axb_27_par_cp_0/CIN
5.329	0.035	tINS	FF	1	R34C50[1][B]	Mdu/u_mdu/reg0_neg_axb_27_par_cp_0/COUT
5.329	0.000	tNET	FF	2	R34C50[2][A]	Mdu/u_mdu/reg0_neg_axb_31_par_cp_0/CIN
5.364	0.035	tINS	FF	1	R34C50[2][A]	Mdu/u_mdu/reg0_neg_axb_31_par_cp_0/COUT
5.364	0.000	tNET	FF	2	R34C50[2][B]	Mdu/u_mdu/reg0_neg_axb_34_par_1/CIN
5.400	0.035	tINS	FF	1	R34C50[2][B]	Mdu/u_mdu/reg0_neg_axb_34_par_1/COUT
5.400	0.000	tNET	FF	2	R34C51[0][A]	Mdu/u_mdu/reg0_neg_axb_38_par_1/CIN
5.435	0.035	tINS	FF	1	R34C51[0][A]	Mdu/u_mdu/reg0_neg_axb_38_par_1/COUT
5.435	0.000	tNET	FF	2	R34C51[0][B]	Mdu/u_mdu/reg0_neg_axb_42_par_1/CIN
5.470	0.035	tINS	FF	1	R34C51[0][B]	Mdu/u_mdu/reg0_neg_axb_42_par_1/COUT
5.470	0.000	tNET	FF	2	R34C51[1][A]	Mdu/u_mdu/reg0_neg_axb_46_par_1/CIN
5.505	0.035	tINS	FF	1	R34C51[1][A]	Mdu/u_mdu/reg0_neg_axb_46_par_1/COUT
5.505	0.000	tNET	FF	2	R34C51[1][B]	Mdu/u_mdu/reg0_neg_axb_50_par_1/CIN
5.540	0.035	tINS	FF	1	R34C51[1][B]	Mdu/u_mdu/reg0_neg_axb_50_par_1/COUT
5.540	0.000	tNET	FF	2	R34C51[2][A]	Mdu/u_mdu/reg0_neg_cry_54_0/CIN
5.576	0.035	tINS	FF	1	R34C51[2][A]	Mdu/u_mdu/reg0_neg_cry_54_0/COUT
5.576	0.000	tNET	FF	2	R34C51[2][B]	Mdu/u_mdu/reg0_neg_cry_55_0/CIN
5.611	0.035	tINS	FF	1	R34C51[2][B]	Mdu/u_mdu/reg0_neg_cry_55_0/COUT
5.611	0.000	tNET	FF	2	R34C52[0][A]	Mdu/u_mdu/reg0_neg_cry_56_0/CIN
5.646	0.035	tINS	FF	1	R34C52[0][A]	Mdu/u_mdu/reg0_neg_cry_56_0/COUT
5.646	0.000	tNET	FF	2	R34C52[0][B]	Mdu/u_mdu/reg0_neg_cry_57_0/CIN
5.681	0.035	tINS	FF	1	R34C52[0][B]	Mdu/u_mdu/reg0_neg_cry_57_0/COUT
5.681	0.000	tNET	FF	2	R34C52[1][A]	Mdu/u_mdu/reg0_neg_cry_58_0/CIN
5.716	0.035	tINS	FF	1	R34C52[1][A]	Mdu/u_mdu/reg0_neg_cry_58_0/COUT
5.716	0.000	tNET	FF	2	R34C52[1][B]	Mdu/u_mdu/reg0_neg_cry_59_0/CIN
5.752	0.035	tINS	FF	1	R34C52[1][B]	Mdu/u_mdu/reg0_neg_cry_59_0/COUT
5.752	0.000	tNET	FF	2	R34C52[2][A]	Mdu/u_mdu/reg0_neg_cry_60_0/CIN
5.787	0.035	tINS	FF	1	R34C52[2][A]	Mdu/u_mdu/reg0_neg_cry_60_0/COUT
5.787	0.000	tNET	FF	2	R34C52[2][B]	Mdu/u_mdu/reg0_neg_cry_61_0/CIN
5.822	0.035	tINS	FF	1	R34C52[2][B]	Mdu/u_mdu/reg0_neg_cry_61_0/COUT
5.822	0.000	tNET	FF	2	R34C53[0][A]	Mdu/u_mdu/reg0_neg_cry_62_0/CIN
5.857	0.035	tINS	FF	1	R34C53[0][A]	Mdu/u_mdu/reg0_neg_cry_62_0/COUT
5.857	0.000	tNET	FF	2	R34C53[0][B]	Mdu/u_mdu/reg0_neg_s_63_0/CIN
6.327	0.470	tINS	FF	1	R34C53[0][B]	Mdu/u_mdu/reg0_neg_s_63_0/SUM
7.011	0.684	tNET	FF	1	R33C48[3][A]	Mdu/u_mdu/reg0_post_swap_2[31]/I2
7.464	0.453	tINS	FF	1	R33C48[3][A]	Mdu/u_mdu/reg0_post_swap_2[31]/F
7.464	0.000	tNET	FF	1	R33C48[3][A]	Mdu/u_mdu/reg0_post_swap_4[31]/I0
7.567	0.103	tINS	FF	2	R33C48[3][A]	Mdu/u_mdu/reg0_post_swap_4[31]/O
8.472	0.904	tNET	FF	1	R32C48[3][A]	Mdu/u_mdu/reg0_post_swap_5[31]/I1
8.934	0.462	tINS	FR	1	R32C48[3][A]	Mdu/u_mdu/reg0_post_swap_5[31]/F
8.935	0.001	tNET	RR	1	R32C48[2][A]	Mdu/u_mdu/res0_cZ[31]/I1
9.388	0.453	tINS	RF	3	R32C48[2][A]	Mdu/u_mdu/res0_cZ[31]/F
10.789	1.401	tNET	FF	1	BSRAM_R45[17]	memq_memq_0_15/DI1

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	576	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	BSRAM_R45[17]	memq_memq_0_15/CLKA
11.683	-0.200	tUnc				memq_memq_0_15
11.648	-0.035	tSu		1	BSRAM_R45[17]	memq_memq_0_15

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 3.626, 40.721%; route: 5.047, 56.674%; tC2Q: 0.232, 2.605%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path11

Path Summary:

Slack	0.870
Data Arrival Time	10.778
Data Required Time	11.648
From	Mdu/u_mdu/reg0_fast_Z[4]
To	Mdu/u_mdu/reg0_fast_Z[13]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.683	0.683	tINS	RR	576	IOT48[A]	clk_ibuf/O
1.883	1.201	tNET	RR	1	R48C45[1][B]	Mdu/u_mdu/reg0_fast_Z[4]/CLK
2.115	0.232	tC2Q	RF	7	R48C45[1][B]	Mdu/u_mdu/reg0_fast_Z[4]/Q
3.081	0.966	tNET	FF	1	R42C50[3][A]	Mdu/u_mdu/reg0_neg_axb_4_par_0_cp_0_cZ/I2
3.598	0.517	tINS	FF	1	R42C50[3][A]	Mdu/u_mdu/reg0_neg_axb_4_par_0_cp_0_cZ/F
4.497	0.899	tNET	FF	2	R42C53[1][B]	Mdu/u_mdu/reg0_neg_axb_4_par_cp_0_0/I0
5.067	0.570	tINS	FR	1	R42C53[1][B]	Mdu/u_mdu/reg0_neg_axb_4_par_cp_0_0/COUT
5.067	0.000	tNET	RR	2	R42C53[2][A]	Mdu/u_mdu/reg0_neg_axb_8_par_cp_1/CIN
5.102	0.035	tINS	RF	1	R42C53[2][A]	Mdu/u_mdu/reg0_neg_axb_8_par_cp_1/COUT
5.102	0.000	tNET	FF	2	R42C53[2][B]	Mdu/u_mdu/reg0_neg_axb_12_par_cp_1/CIN
5.137	0.035	tINS	FF	1	R42C53[2][B]	Mdu/u_mdu/reg0_neg_axb_12_par_cp_1/COUT
5.137	0.000	tNET	FF	2	R42C54[0][A]	Mdu/u_mdu/reg0_neg_axb_16_par_cp_1/CIN
5.173	0.035	tINS	FF	1	R42C54[0][A]	Mdu/u_mdu/reg0_neg_axb_16_par_cp_1/COUT
5.173	0.000	tNET	FF	2	R42C54[0][B]	Mdu/u_mdu/reg0_neg_axb_19_par_1/CIN
5.208	0.035	tINS	FF	1	R42C54[0][B]	Mdu/u_mdu/reg0_neg_axb_19_par_1/COUT
5.208	0.000	tNET	FF	2	R42C54[1][A]	Mdu/u_mdu/reg0_neg_axb_23_par_1/CIN
5.243	0.035	tINS	FF	1	R42C54[1][A]	Mdu/u_mdu/reg0_neg_axb_23_par_1/COUT
5.243	0.000	tNET	FF	2	R42C54[1][B]	Mdu/u_mdu/reg0_neg_axb_27_par_1/CIN
5.278	0.035	tINS	FF	1	R42C54[1][B]	Mdu/u_mdu/reg0_neg_axb_27_par_1/COUT
5.278	0.000	tNET	FF	2	R42C54[2][A]	Mdu/u_mdu/reg0_neg_axb_31_par_1/CIN
5.313	0.035	tINS	FF	1	R42C54[2][A]	Mdu/u_mdu/reg0_neg_axb_31_par_1/COUT
5.313	0.000	tNET	FF	2	R42C54[2][B]	Mdu/u_mdu/reg0_neg_cry_34_0/CIN
5.349	0.035	tINS	FF	1	R42C54[2][B]	Mdu/u_mdu/reg0_neg_cry_34_0/COUT
5.349	0.000	tNET	FF	2	R42C55[0][A]	Mdu/u_mdu/reg0_neg_cry_35_0/CIN
5.384	0.035	tINS	FF	1	R42C55[0][A]	Mdu/u_mdu/reg0_neg_cry_35_0/COUT
5.384	0.000	tNET	FF	2	R42C55[0][B]	Mdu/u_mdu/reg0_neg_cry_36_0/CIN
5.419	0.035	tINS	FF	1	R42C55[0][B]	Mdu/u_mdu/reg0_neg_cry_36_0/COUT
5.419	0.000	tNET	FF	2	R42C55[1][A]	Mdu/u_mdu/reg0_neg_cry_37_0/CIN
5.454	0.035	tINS	FF	1	R42C55[1][A]	Mdu/u_mdu/reg0_neg_cry_37_0/COUT
5.454	0.000	tNET	FF	2	R42C55[1][B]	Mdu/u_mdu/reg0_neg_cry_38_0/CIN
5.489	0.035	tINS	FF	1	R42C55[1][B]	Mdu/u_mdu/reg0_neg_cry_38_0/COUT
5.489	0.000	tNET	FF	2	R42C55[2][A]	Mdu/u_mdu/reg0_neg_cry_39_0/CIN
5.525	0.035	tINS	FF	1	R42C55[2][A]	Mdu/u_mdu/reg0_neg_cry_39_0/COUT
5.525	0.000	tNET	FF	2	R42C55[2][B]	Mdu/u_mdu/reg0_neg_cry_40_0/CIN
5.560	0.035	tINS	FF	1	R42C55[2][B]	Mdu/u_mdu/reg0_neg_cry_40_0/COUT
5.560	0.000	tNET	FF	2	R42C56[0][A]	Mdu/u_mdu/reg0_neg_cry_41_0/CIN
5.595	0.035	tINS	FF	1	R42C56[0][A]	Mdu/u_mdu/reg0_neg_cry_41_0/COUT
5.595	0.000	tNET	FF	2	R42C56[0][B]	Mdu/u_mdu/reg0_neg_cry_42_0/CIN
5.630	0.035	tINS	FF	1	R42C56[0][B]	Mdu/u_mdu/reg0_neg_cry_42_0/COUT
5.630	0.000	tNET	FF	2	R42C56[1][A]	Mdu/u_mdu/reg0_neg_cry_43_0/CIN
5.665	0.035	tINS	FF	1	R42C56[1][A]	Mdu/u_mdu/reg0_neg_cry_43_0/COUT
5.665	0.000	tNET	FF	2	R42C56[1][B]	Mdu/u_mdu/reg0_neg_cry_44_0/CIN
5.701	0.035	tINS	FF	1	R42C56[1][B]	Mdu/u_mdu/reg0_neg_cry_44_0/COUT
5.701	0.000	tNET	FF	2	R42C56[2][A]	Mdu/u_mdu/reg0_neg_cry_45_0/CIN
6.171	0.470	tINS	FF	1	R42C56[2][A]	Mdu/u_mdu/reg0_neg_cry_45_0/SUM
7.368	1.198	tNET	FF	1	R38C47[3][A]	Mdu/u_mdu/reg0_post_swap_2[13]/I2
7.923	0.555	tINS	FF	1	R38C47[3][A]	Mdu/u_mdu/reg0_post_swap_2[13]/F
7.923	0.000	tNET	FF	1	R38C47[3][A]	Mdu/u_mdu/reg0_post_swap_4[13]/I0
8.026	0.103	tINS	FF	2	R38C47[3][A]	Mdu/u_mdu/reg0_post_swap_4[13]/O
8.940	0.913	tNET	FF	1	R38C47[1][B]	Mdu/u_mdu/un11_reg0_nx_cZ[13]_cZ/I1
9.457	0.517	tINS	FF	2	R38C47[1][B]	Mdu/u_mdu/un11_reg0_nx_cZ[13]_cZ/F
10.316	0.859	tNET	FF	1	R49C48[2][A]	Mdu/u_mdu/reg0_nx_fast_cZ[13]/I3
10.778	0.462	tINS	FR	1	R49C48[2][A]	Mdu/u_mdu/reg0_nx_fast_cZ[13]/F
10.778	0.000	tNET	RR	1	R49C48[2][A]	Mdu/u_mdu/reg0_fast_Z[13]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	576	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R49C48[2][A]	Mdu/u_mdu/reg0_fast_Z[13]/CLK
11.683	-0.200	tUnc				Mdu/u_mdu/reg0_fast_Z[13]
11.648	-0.035	tSu		1	R49C48[2][A]	Mdu/u_mdu/reg0_fast_Z[13]

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 3.828, 43.033%; route: 4.835, 54.359%; tC2Q: 0.232, 2.608%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path12

Path Summary:

Slack	0.870
Data Arrival Time	10.778
Data Required Time	11.648
From	Mdu/u_mdu/reg0_fast_Z[4]
To	Mdu/u_mdu/reg0_Z[13]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.683	0.683	tINS	RR	576	IOT48[A]	clk_ibuf/O
1.883	1.201	tNET	RR	1	R48C45[1][B]	Mdu/u_mdu/reg0_fast_Z[4]/CLK
2.115	0.232	tC2Q	RF	7	R48C45[1][B]	Mdu/u_mdu/reg0_fast_Z[4]/Q
3.081	0.966	tNET	FF	1	R42C50[3][A]	Mdu/u_mdu/reg0_neg_axb_4_par_0_cp_0_cZ/I2
3.598	0.517	tINS	FF	1	R42C50[3][A]	Mdu/u_mdu/reg0_neg_axb_4_par_0_cp_0_cZ/F
4.497	0.899	tNET	FF	2	R42C53[1][B]	Mdu/u_mdu/reg0_neg_axb_4_par_cp_0_0/I0
5.067	0.570	tINS	FR	1	R42C53[1][B]	Mdu/u_mdu/reg0_neg_axb_4_par_cp_0_0/COUT
5.067	0.000	tNET	RR	2	R42C53[2][A]	Mdu/u_mdu/reg0_neg_axb_8_par_cp_1/CIN
5.102	0.035	tINS	RF	1	R42C53[2][A]	Mdu/u_mdu/reg0_neg_axb_8_par_cp_1/COUT
5.102	0.000	tNET	FF	2	R42C53[2][B]	Mdu/u_mdu/reg0_neg_axb_12_par_cp_1/CIN
5.137	0.035	tINS	FF	1	R42C53[2][B]	Mdu/u_mdu/reg0_neg_axb_12_par_cp_1/COUT
5.137	0.000	tNET	FF	2	R42C54[0][A]	Mdu/u_mdu/reg0_neg_axb_16_par_cp_1/CIN
5.173	0.035	tINS	FF	1	R42C54[0][A]	Mdu/u_mdu/reg0_neg_axb_16_par_cp_1/COUT
5.173	0.000	tNET	FF	2	R42C54[0][B]	Mdu/u_mdu/reg0_neg_axb_19_par_1/CIN
5.208	0.035	tINS	FF	1	R42C54[0][B]	Mdu/u_mdu/reg0_neg_axb_19_par_1/COUT
5.208	0.000	tNET	FF	2	R42C54[1][A]	Mdu/u_mdu/reg0_neg_axb_23_par_1/CIN
5.243	0.035	tINS	FF	1	R42C54[1][A]	Mdu/u_mdu/reg0_neg_axb_23_par_1/COUT
5.243	0.000	tNET	FF	2	R42C54[1][B]	Mdu/u_mdu/reg0_neg_axb_27_par_1/CIN
5.278	0.035	tINS	FF	1	R42C54[1][B]	Mdu/u_mdu/reg0_neg_axb_27_par_1/COUT
5.278	0.000	tNET	FF	2	R42C54[2][A]	Mdu/u_mdu/reg0_neg_axb_31_par_1/CIN
5.313	0.035	tINS	FF	1	R42C54[2][A]	Mdu/u_mdu/reg0_neg_axb_31_par_1/COUT
5.313	0.000	tNET	FF	2	R42C54[2][B]	Mdu/u_mdu/reg0_neg_cry_34_0/CIN
5.349	0.035	tINS	FF	1	R42C54[2][B]	Mdu/u_mdu/reg0_neg_cry_34_0/COUT
5.349	0.000	tNET	FF	2	R42C55[0][A]	Mdu/u_mdu/reg0_neg_cry_35_0/CIN
5.384	0.035	tINS	FF	1	R42C55[0][A]	Mdu/u_mdu/reg0_neg_cry_35_0/COUT
5.384	0.000	tNET	FF	2	R42C55[0][B]	Mdu/u_mdu/reg0_neg_cry_36_0/CIN
5.419	0.035	tINS	FF	1	R42C55[0][B]	Mdu/u_mdu/reg0_neg_cry_36_0/COUT
5.419	0.000	tNET	FF	2	R42C55[1][A]	Mdu/u_mdu/reg0_neg_cry_37_0/CIN
5.454	0.035	tINS	FF	1	R42C55[1][A]	Mdu/u_mdu/reg0_neg_cry_37_0/COUT
5.454	0.000	tNET	FF	2	R42C55[1][B]	Mdu/u_mdu/reg0_neg_cry_38_0/CIN
5.489	0.035	tINS	FF	1	R42C55[1][B]	Mdu/u_mdu/reg0_neg_cry_38_0/COUT
5.489	0.000	tNET	FF	2	R42C55[2][A]	Mdu/u_mdu/reg0_neg_cry_39_0/CIN
5.525	0.035	tINS	FF	1	R42C55[2][A]	Mdu/u_mdu/reg0_neg_cry_39_0/COUT
5.525	0.000	tNET	FF	2	R42C55[2][B]	Mdu/u_mdu/reg0_neg_cry_40_0/CIN
5.560	0.035	tINS	FF	1	R42C55[2][B]	Mdu/u_mdu/reg0_neg_cry_40_0/COUT
5.560	0.000	tNET	FF	2	R42C56[0][A]	Mdu/u_mdu/reg0_neg_cry_41_0/CIN
5.595	0.035	tINS	FF	1	R42C56[0][A]	Mdu/u_mdu/reg0_neg_cry_41_0/COUT
5.595	0.000	tNET	FF	2	R42C56[0][B]	Mdu/u_mdu/reg0_neg_cry_42_0/CIN
5.630	0.035	tINS	FF	1	R42C56[0][B]	Mdu/u_mdu/reg0_neg_cry_42_0/COUT
5.630	0.000	tNET	FF	2	R42C56[1][A]	Mdu/u_mdu/reg0_neg_cry_43_0/CIN
5.665	0.035	tINS	FF	1	R42C56[1][A]	Mdu/u_mdu/reg0_neg_cry_43_0/COUT
5.665	0.000	tNET	FF	2	R42C56[1][B]	Mdu/u_mdu/reg0_neg_cry_44_0/CIN
5.701	0.035	tINS	FF	1	R42C56[1][B]	Mdu/u_mdu/reg0_neg_cry_44_0/COUT
5.701	0.000	tNET	FF	2	R42C56[2][A]	Mdu/u_mdu/reg0_neg_cry_45_0/CIN
6.171	0.470	tINS	FF	1	R42C56[2][A]	Mdu/u_mdu/reg0_neg_cry_45_0/SUM
7.368	1.198	tNET	FF	1	R38C47[3][A]	Mdu/u_mdu/reg0_post_swap_2[13]/I2
7.923	0.555	tINS	FF	1	R38C47[3][A]	Mdu/u_mdu/reg0_post_swap_2[13]/F
7.923	0.000	tNET	FF	1	R38C47[3][A]	Mdu/u_mdu/reg0_post_swap_4[13]/I0
8.026	0.103	tINS	FF	2	R38C47[3][A]	Mdu/u_mdu/reg0_post_swap_4[13]/O
8.940	0.913	tNET	FF	1	R38C47[1][B]	Mdu/u_mdu/un11_reg0_nx_cZ[13]_cZ/I1
9.457	0.517	tINS	FF	2	R38C47[1][B]	Mdu/u_mdu/un11_reg0_nx_cZ[13]_cZ/F
10.316	0.859	tNET	FF	1	R49C48[2][B]	Mdu/u_mdu/reg0_nx_cZ[13]/I3
10.778	0.462	tINS	FR	1	R49C48[2][B]	Mdu/u_mdu/reg0_nx_cZ[13]/F
10.778	0.000	tNET	RR	1	R49C48[2][B]	Mdu/u_mdu/reg0_Z[13]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	576	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R49C48[2][B]	Mdu/u_mdu/reg0_Z[13]/CLK
11.683	-0.200	tUnc				Mdu/u_mdu/reg0_Z[13]
11.648	-0.035	tSu		1	R49C48[2][B]	Mdu/u_mdu/reg0_Z[13]

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 3.828, 43.033%; route: 4.835, 54.359%; tC2Q: 0.232, 2.608%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path13

Path Summary:

Slack	0.912
Data Arrival Time	10.736
Data Required Time	11.648
From	Mdu/u_mdu/reg0_Z[3]
To	Mdu/u_mdu/reg0_Z[64]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.683	0.683	tINS	RR	576	IOT48[A]	clk_ibuf/O
1.883	1.201	tNET	RR	1	R39C48[0][A]	Mdu/u_mdu/reg0_Z[3]/CLK
2.115	0.232	tC2Q	RF	12	R39C48[0][A]	Mdu/u_mdu/reg0_Z[3]/Q
3.182	1.067	tNET	FF	1	R46C55[0][A]	Mdu/u_mdu/m4_0_03_1_0_cZ/I2
3.553	0.371	tINS	FF	2	R46C55[0][A]	Mdu/u_mdu/m4_0_03_1_0_cZ/F
4.049	0.496	tNET	FF	1	R46C59[1][B]	Mdu/u_mdu/m4_0_03_0_0_RNI1JV1/I1
4.604	0.555	tINS	FF	3	R46C59[1][B]	Mdu/u_mdu/m4_0_03_0_0_RNI1JV1/F
5.463	0.859	tNET	FF	1	R47C54[3][B]	Mdu/u_mdu/m16_2_03_0_0_cZ/I0
6.018	0.555	tINS	FF	4	R47C54[3][B]	Mdu/u_mdu/m16_2_03_0_0_cZ/F
6.877	0.859	tNET	FF	1	R40C52[3][B]	Mdu/u_mdu/m64_4_03_0_0_RNO/I0
7.330	0.453	tINS	FF	1	R40C52[3][B]	Mdu/u_mdu/m64_4_03_0_0_RNO/F
7.743	0.413	tNET	FF	1	R39C54[3][B]	Mdu/u_mdu/m64_4_03_0_0_cZ/I0
8.114	0.371	tINS	FF	1	R39C54[3][B]	Mdu/u_mdu/m64_4_03_0_0_cZ/F
8.119	0.004	tNET	FF	1	R39C54[2][B]	Mdu/u_mdu/m64_4_03_cZ/I2
8.636	0.517	tINS	FF	1	R39C54[2][B]	Mdu/u_mdu/m64_4_03_cZ/F
9.397	0.761	tNET	FF	1	R33C53[3][A]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[64]/I3
9.952	0.555	tINS	FF	1	R33C53[3][A]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[64]/F
10.365	0.413	tNET	FF	1	R32C52[2][A]	Mdu/u_mdu/reg0_nx_cZ[64]/I0
10.736	0.371	tINS	FF	1	R32C52[2][A]	Mdu/u_mdu/reg0_nx_cZ[64]/F
10.736	0.000	tNET	FF	1	R32C52[2][A]	Mdu/u_mdu/reg0_Z[64]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	576	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R32C52[2][A]	Mdu/u_mdu/reg0_Z[64]/CLK
11.683	-0.200	tUnc				Mdu/u_mdu/reg0_Z[64]
11.648	-0.035	tSu		1	R32C52[2][A]	Mdu/u_mdu/reg0_Z[64]

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	8
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 3.748, 42.338%; route: 4.873, 55.041%; tC2Q: 0.232, 2.621%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path14

Path Summary:

Slack	0.932
Data Arrival Time	10.716
Data Required Time	11.648
From	Mdu/u_mdu/reg0_fast_Z[4]
To	memq_memq_0_6
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.683	0.683	tINS	RR	576	IOT48[A]	clk_ibuf/O
1.883	1.201	tNET	RR	1	R48C45[1][B]	Mdu/u_mdu/reg0_fast_Z[4]/CLK
2.115	0.232	tC2Q	RF	7	R48C45[1][B]	Mdu/u_mdu/reg0_fast_Z[4]/Q
3.081	0.966	tNET	FF	1	R42C50[3][A]	Mdu/u_mdu/reg0_neg_axb_4_par_0_cp_0_cZ/I2
3.598	0.517	tINS	FF	1	R42C50[3][A]	Mdu/u_mdu/reg0_neg_axb_4_par_0_cp_0_cZ/F
4.497	0.899	tNET	FF	2	R42C53[1][B]	Mdu/u_mdu/reg0_neg_axb_4_par_cp_0_0/I0
5.067	0.570	tINS	FR	1	R42C53[1][B]	Mdu/u_mdu/reg0_neg_axb_4_par_cp_0_0/COUT
5.067	0.000	tNET	RR	2	R42C53[2][A]	Mdu/u_mdu/reg0_neg_axb_8_par_cp_1/CIN
5.102	0.035	tINS	RF	1	R42C53[2][A]	Mdu/u_mdu/reg0_neg_axb_8_par_cp_1/COUT
5.102	0.000	tNET	FF	2	R42C53[2][B]	Mdu/u_mdu/reg0_neg_axb_12_par_cp_1/CIN
5.137	0.035	tINS	FF	1	R42C53[2][B]	Mdu/u_mdu/reg0_neg_axb_12_par_cp_1/COUT
5.137	0.000	tNET	FF	2	R42C54[0][A]	Mdu/u_mdu/reg0_neg_axb_16_par_cp_1/CIN
5.173	0.035	tINS	FF	1	R42C54[0][A]	Mdu/u_mdu/reg0_neg_axb_16_par_cp_1/COUT
5.173	0.000	tNET	FF	2	R42C54[0][B]	Mdu/u_mdu/reg0_neg_axb_19_par_1/CIN
5.208	0.035	tINS	FF	1	R42C54[0][B]	Mdu/u_mdu/reg0_neg_axb_19_par_1/COUT
5.208	0.000	tNET	FF	2	R42C54[1][A]	Mdu/u_mdu/reg0_neg_axb_23_par_1/CIN
5.243	0.035	tINS	FF	1	R42C54[1][A]	Mdu/u_mdu/reg0_neg_axb_23_par_1/COUT
5.243	0.000	tNET	FF	2	R42C54[1][B]	Mdu/u_mdu/reg0_neg_axb_27_par_1/CIN
5.278	0.035	tINS	FF	1	R42C54[1][B]	Mdu/u_mdu/reg0_neg_axb_27_par_1/COUT
5.278	0.000	tNET	FF	2	R42C54[2][A]	Mdu/u_mdu/reg0_neg_axb_31_par_1/CIN
5.313	0.035	tINS	FF	1	R42C54[2][A]	Mdu/u_mdu/reg0_neg_axb_31_par_1/COUT
5.313	0.000	tNET	FF	2	R42C54[2][B]	Mdu/u_mdu/reg0_neg_cry_34_0/CIN
5.349	0.035	tINS	FF	1	R42C54[2][B]	Mdu/u_mdu/reg0_neg_cry_34_0/COUT
5.349	0.000	tNET	FF	2	R42C55[0][A]	Mdu/u_mdu/reg0_neg_cry_35_0/CIN
5.384	0.035	tINS	FF	1	R42C55[0][A]	Mdu/u_mdu/reg0_neg_cry_35_0/COUT
5.384	0.000	tNET	FF	2	R42C55[0][B]	Mdu/u_mdu/reg0_neg_cry_36_0/CIN
5.419	0.035	tINS	FF	1	R42C55[0][B]	Mdu/u_mdu/reg0_neg_cry_36_0/COUT
5.419	0.000	tNET	FF	2	R42C55[1][A]	Mdu/u_mdu/reg0_neg_cry_37_0/CIN
5.454	0.035	tINS	FF	1	R42C55[1][A]	Mdu/u_mdu/reg0_neg_cry_37_0/COUT
5.454	0.000	tNET	FF	2	R42C55[1][B]	Mdu/u_mdu/reg0_neg_cry_38_0/CIN
5.489	0.035	tINS	FF	1	R42C55[1][B]	Mdu/u_mdu/reg0_neg_cry_38_0/COUT
5.489	0.000	tNET	FF	2	R42C55[2][A]	Mdu/u_mdu/reg0_neg_cry_39_0/CIN
5.525	0.035	tINS	FF	1	R42C55[2][A]	Mdu/u_mdu/reg0_neg_cry_39_0/COUT
5.525	0.000	tNET	FF	2	R42C55[2][B]	Mdu/u_mdu/reg0_neg_cry_40_0/CIN
5.560	0.035	tINS	FF	1	R42C55[2][B]	Mdu/u_mdu/reg0_neg_cry_40_0/COUT
5.560	0.000	tNET	FF	2	R42C56[0][A]	Mdu/u_mdu/reg0_neg_cry_41_0/CIN
5.595	0.035	tINS	FF	1	R42C56[0][A]	Mdu/u_mdu/reg0_neg_cry_41_0/COUT
5.595	0.000	tNET	FF	2	R42C56[0][B]	Mdu/u_mdu/reg0_neg_cry_42_0/CIN
5.630	0.035	tINS	FF	1	R42C56[0][B]	Mdu/u_mdu/reg0_neg_cry_42_0/COUT
5.630	0.000	tNET	FF	2	R42C56[1][A]	Mdu/u_mdu/reg0_neg_cry_43_0/CIN
5.665	0.035	tINS	FF	1	R42C56[1][A]	Mdu/u_mdu/reg0_neg_cry_43_0/COUT
5.665	0.000	tNET	FF	2	R42C56[1][B]	Mdu/u_mdu/reg0_neg_cry_44_0/CIN
6.135	0.470	tINS	FF	1	R42C56[1][B]	Mdu/u_mdu/reg0_neg_cry_44_0/SUM
7.305	1.170	tNET	FF	1	R38C47[2][A]	Mdu/u_mdu/reg0_post_swap_2[12]/I2
7.854	0.549	tINS	FR	1	R38C47[2][A]	Mdu/u_mdu/reg0_post_swap_2[12]/F
7.854	0.000	tNET	RR	1	R38C47[2][A]	Mdu/u_mdu/reg0_post_swap_4[12]/I0
7.959	0.105	tINS	RR	1	R38C47[2][A]	Mdu/u_mdu/reg0_post_swap_4[12]/O
8.137	0.178	tNET	RR	1	R39C47[2][B]	Mdu/u_mdu/reg0_post_swap_5[12]/I1
8.590	0.453	tINS	RF	3	R39C47[2][B]	Mdu/u_mdu/reg0_post_swap_5[12]/F
9.008	0.418	tNET	FF	1	R39C49[0][B]	Mdu/u_mdu/res0_cZ[12]/I1
9.563	0.555	tINS	FF	3	R39C49[0][B]	Mdu/u_mdu/res0_cZ[12]/F
10.716	1.154	tNET	FF	1	BSRAM_R54[14]	memq_memq_0_6/DI0

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	576	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	BSRAM_R54[14]	memq_memq_0_6/CLKA
11.683	-0.200	tUnc				memq_memq_0_6
11.648	-0.035	tSu		1	BSRAM_R54[14]	memq_memq_0_6

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 3.817, 43.217%; route: 4.784, 54.156%; tC2Q: 0.232, 2.627%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path15

Path Summary:

Slack	0.935
Data Arrival Time	10.713
Data Required Time	11.648
From	Mdu/u_mdu/reg0_Z[10]
To	Mdu/u_mdu/reg0_31_rep1_Z
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.683	0.683	tINS	RR	576	IOT48[A]	clk_ibuf/O
1.883	1.201	tNET	RR	1	R41C44[2][B]	Mdu/u_mdu/reg0_Z[10]/CLK
2.115	0.232	tC2Q	RF	11	R41C44[2][B]	Mdu/u_mdu/reg0_Z[10]/Q
3.431	1.316	tNET	FF	1	R46C58[2][B]	Mdu/u_mdu/m11_0_03_1_cZ/I3
3.980	0.549	tINS	FR	1	R46C58[2][B]	Mdu/u_mdu/m11_0_03_1_cZ/F
3.982	0.001	tNET	RR	1	R46C58[2][A]	Mdu/u_mdu/m11_0_03_cZ/I1
4.499	0.517	tINS	RF	4	R46C58[2][A]	Mdu/u_mdu/m11_0_03_cZ/F
5.318	0.819	tNET	FF	1	R44C59[0][B]	Mdu/u_mdu/m15_2_03_1_0_cZ/I2
5.689	0.371	tINS	FF	2	R44C59[0][B]	Mdu/u_mdu/m15_2_03_1_0_cZ/F
5.698	0.009	tNET	FF	1	R44C59[3][A]	Mdu/u_mdu/m15_2_03_0_0_RNI9I0C/I1
6.253	0.555	tINS	FF	3	R44C59[3][A]	Mdu/u_mdu/m15_2_03_0_0_RNI9I0C/F
7.188	0.936	tNET	FF	1	R47C53[2][A]	Mdu/u_mdu/m31_4_01_cZ/I1
7.641	0.453	tINS	FF	1	R47C53[2][A]	Mdu/u_mdu/m31_4_01_cZ/F
8.491	0.850	tNET	FF	1	R35C53[1][B]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[31]/I2
9.061	0.570	tINS	FR	1	R35C53[1][B]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[31]/F
9.234	0.172	tNET	RR	1	R35C52[3][A]	Mdu/u_mdu/reg0_exe_nx_cZ[31]/I3
9.751	0.517	tINS	RF	3	R35C52[3][A]	Mdu/u_mdu/reg0_exe_nx_cZ[31]/F
10.251	0.500	tNET	FF	1	R33C50[0][A]	Mdu/u_mdu/reg0_nx_rep1_cZ[31]/I0
10.713	0.462	tINS	FR	1	R33C50[0][A]	Mdu/u_mdu/reg0_nx_rep1_cZ[31]/F
10.713	0.000	tNET	RR	1	R33C50[0][A]	Mdu/u_mdu/reg0_31_rep1_Z/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	576	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R33C50[0][A]	Mdu/u_mdu/reg0_31_rep1_Z/CLK
11.683	-0.200	tUnc				Mdu/u_mdu/reg0_31_rep1_Z
11.648	-0.035	tSu		1	R33C50[0][A]	Mdu/u_mdu/reg0_31_rep1_Z

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	8
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 3.994, 45.235%; route: 4.604, 52.138%; tC2Q: 0.232, 2.628%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path16

Path Summary:

Slack	0.935
Data Arrival Time	10.713
Data Required Time	11.648
From	Mdu/u_mdu/reg0_Z[10]
To	Mdu/u_mdu/reg0_fast_Z[31]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.683	0.683	tINS	RR	576	IOT48[A]	clk_ibuf/O
1.883	1.201	tNET	RR	1	R41C44[2][B]	Mdu/u_mdu/reg0_Z[10]/CLK
2.115	0.232	tC2Q	RF	11	R41C44[2][B]	Mdu/u_mdu/reg0_Z[10]/Q
3.431	1.316	tNET	FF	1	R46C58[2][B]	Mdu/u_mdu/m11_0_03_1_cZ/I3
3.980	0.549	tINS	FR	1	R46C58[2][B]	Mdu/u_mdu/m11_0_03_1_cZ/F
3.982	0.001	tNET	RR	1	R46C58[2][A]	Mdu/u_mdu/m11_0_03_cZ/I1
4.499	0.517	tINS	RF	4	R46C58[2][A]	Mdu/u_mdu/m11_0_03_cZ/F
5.318	0.819	tNET	FF	1	R44C59[0][B]	Mdu/u_mdu/m15_2_03_1_0_cZ/I2
5.689	0.371	tINS	FF	2	R44C59[0][B]	Mdu/u_mdu/m15_2_03_1_0_cZ/F
5.698	0.009	tNET	FF	1	R44C59[3][A]	Mdu/u_mdu/m15_2_03_0_0_RNI9I0C/I1
6.253	0.555	tINS	FF	3	R44C59[3][A]	Mdu/u_mdu/m15_2_03_0_0_RNI9I0C/F
7.188	0.936	tNET	FF	1	R47C53[2][A]	Mdu/u_mdu/m31_4_01_cZ/I1
7.641	0.453	tINS	FF	1	R47C53[2][A]	Mdu/u_mdu/m31_4_01_cZ/F
8.491	0.850	tNET	FF	1	R35C53[1][B]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[31]/I2
9.061	0.570	tINS	FR	1	R35C53[1][B]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[31]/F
9.234	0.172	tNET	RR	1	R35C52[3][A]	Mdu/u_mdu/reg0_exe_nx_cZ[31]/I3
9.751	0.517	tINS	RF	3	R35C52[3][A]	Mdu/u_mdu/reg0_exe_nx_cZ[31]/F
10.251	0.500	tNET	FF	1	R33C50[1][A]	Mdu/u_mdu/reg0_nx_fast_cZ[31]/I0
10.713	0.462	tINS	FR	1	R33C50[1][A]	Mdu/u_mdu/reg0_nx_fast_cZ[31]/F
10.713	0.000	tNET	RR	1	R33C50[1][A]	Mdu/u_mdu/reg0_fast_Z[31]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	576	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R33C50[1][A]	Mdu/u_mdu/reg0_fast_Z[31]/CLK
11.683	-0.200	tUnc				Mdu/u_mdu/reg0_fast_Z[31]
11.648	-0.035	tSu		1	R33C50[1][A]	Mdu/u_mdu/reg0_fast_Z[31]

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	8
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 3.994, 45.235%; route: 4.604, 52.138%; tC2Q: 0.232, 2.628%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path17

Path Summary:

Slack	0.968
Data Arrival Time	10.681
Data Required Time	11.648
From	Mdu/u_mdu/reg0_fast_Z[4]
To	Mdu/u_mdu/reg0_Z[16]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.683	0.683	tINS	RR	576	IOT48[A]	clk_ibuf/O
1.883	1.201	tNET	RR	1	R48C45[1][B]	Mdu/u_mdu/reg0_fast_Z[4]/CLK
2.115	0.232	tC2Q	RF	7	R48C45[1][B]	Mdu/u_mdu/reg0_fast_Z[4]/Q
3.081	0.966	tNET	FF	1	R42C50[3][A]	Mdu/u_mdu/reg0_neg_axb_4_par_0_cp_0_cZ/I2
3.598	0.517	tINS	FF	1	R42C50[3][A]	Mdu/u_mdu/reg0_neg_axb_4_par_0_cp_0_cZ/F
4.497	0.899	tNET	FF	2	R42C53[1][B]	Mdu/u_mdu/reg0_neg_axb_4_par_cp_0_0/I0
5.067	0.570	tINS	FR	1	R42C53[1][B]	Mdu/u_mdu/reg0_neg_axb_4_par_cp_0_0/COUT
5.067	0.000	tNET	RR	2	R42C53[2][A]	Mdu/u_mdu/reg0_neg_axb_8_par_cp_1/CIN
5.102	0.035	tINS	RF	1	R42C53[2][A]	Mdu/u_mdu/reg0_neg_axb_8_par_cp_1/COUT
5.102	0.000	tNET	FF	2	R42C53[2][B]	Mdu/u_mdu/reg0_neg_axb_12_par_cp_1/CIN
5.137	0.035	tINS	FF	1	R42C53[2][B]	Mdu/u_mdu/reg0_neg_axb_12_par_cp_1/COUT
5.137	0.000	tNET	FF	2	R42C54[0][A]	Mdu/u_mdu/reg0_neg_axb_16_par_cp_1/CIN
5.173	0.035	tINS	FF	1	R42C54[0][A]	Mdu/u_mdu/reg0_neg_axb_16_par_cp_1/COUT
5.173	0.000	tNET	FF	2	R42C54[0][B]	Mdu/u_mdu/reg0_neg_axb_19_par_1/CIN
5.208	0.035	tINS	FF	1	R42C54[0][B]	Mdu/u_mdu/reg0_neg_axb_19_par_1/COUT
5.208	0.000	tNET	FF	2	R42C54[1][A]	Mdu/u_mdu/reg0_neg_axb_23_par_1/CIN
5.243	0.035	tINS	FF	1	R42C54[1][A]	Mdu/u_mdu/reg0_neg_axb_23_par_1/COUT
5.243	0.000	tNET	FF	2	R42C54[1][B]	Mdu/u_mdu/reg0_neg_axb_27_par_1/CIN
5.278	0.035	tINS	FF	1	R42C54[1][B]	Mdu/u_mdu/reg0_neg_axb_27_par_1/COUT
5.278	0.000	tNET	FF	2	R42C54[2][A]	Mdu/u_mdu/reg0_neg_axb_31_par_1/CIN
5.313	0.035	tINS	FF	1	R42C54[2][A]	Mdu/u_mdu/reg0_neg_axb_31_par_1/COUT
5.313	0.000	tNET	FF	2	R42C54[2][B]	Mdu/u_mdu/reg0_neg_cry_34_0/CIN
5.349	0.035	tINS	FF	1	R42C54[2][B]	Mdu/u_mdu/reg0_neg_cry_34_0/COUT
5.349	0.000	tNET	FF	2	R42C55[0][A]	Mdu/u_mdu/reg0_neg_cry_35_0/CIN
5.384	0.035	tINS	FF	1	R42C55[0][A]	Mdu/u_mdu/reg0_neg_cry_35_0/COUT
5.384	0.000	tNET	FF	2	R42C55[0][B]	Mdu/u_mdu/reg0_neg_cry_36_0/CIN
5.419	0.035	tINS	FF	1	R42C55[0][B]	Mdu/u_mdu/reg0_neg_cry_36_0/COUT
5.419	0.000	tNET	FF	2	R42C55[1][A]	Mdu/u_mdu/reg0_neg_cry_37_0/CIN
5.454	0.035	tINS	FF	1	R42C55[1][A]	Mdu/u_mdu/reg0_neg_cry_37_0/COUT
5.454	0.000	tNET	FF	2	R42C55[1][B]	Mdu/u_mdu/reg0_neg_cry_38_0/CIN
5.489	0.035	tINS	FF	1	R42C55[1][B]	Mdu/u_mdu/reg0_neg_cry_38_0/COUT
5.489	0.000	tNET	FF	2	R42C55[2][A]	Mdu/u_mdu/reg0_neg_cry_39_0/CIN
5.525	0.035	tINS	FF	1	R42C55[2][A]	Mdu/u_mdu/reg0_neg_cry_39_0/COUT
5.525	0.000	tNET	FF	2	R42C55[2][B]	Mdu/u_mdu/reg0_neg_cry_40_0/CIN
5.560	0.035	tINS	FF	1	R42C55[2][B]	Mdu/u_mdu/reg0_neg_cry_40_0/COUT
5.560	0.000	tNET	FF	2	R42C56[0][A]	Mdu/u_mdu/reg0_neg_cry_41_0/CIN
5.595	0.035	tINS	FF	1	R42C56[0][A]	Mdu/u_mdu/reg0_neg_cry_41_0/COUT
5.595	0.000	tNET	FF	2	R42C56[0][B]	Mdu/u_mdu/reg0_neg_cry_42_0/CIN
5.630	0.035	tINS	FF	1	R42C56[0][B]	Mdu/u_mdu/reg0_neg_cry_42_0/COUT
5.630	0.000	tNET	FF	2	R42C56[1][A]	Mdu/u_mdu/reg0_neg_cry_43_0/CIN
5.665	0.035	tINS	FF	1	R42C56[1][A]	Mdu/u_mdu/reg0_neg_cry_43_0/COUT
5.665	0.000	tNET	FF	2	R42C56[1][B]	Mdu/u_mdu/reg0_neg_cry_44_0/CIN
5.701	0.035	tINS	FF	1	R42C56[1][B]	Mdu/u_mdu/reg0_neg_cry_44_0/COUT
5.701	0.000	tNET	FF	2	R42C56[2][A]	Mdu/u_mdu/reg0_neg_cry_45_0/CIN
5.736	0.035	tINS	FF	1	R42C56[2][A]	Mdu/u_mdu/reg0_neg_cry_45_0/COUT
5.736	0.000	tNET	FF	2	R42C56[2][B]	Mdu/u_mdu/reg0_neg_cry_46_0/CIN
5.771	0.035	tINS	FF	1	R42C56[2][B]	Mdu/u_mdu/reg0_neg_cry_46_0/COUT
5.771	0.000	tNET	FF	2	R42C57[0][A]	Mdu/u_mdu/reg0_neg_cry_47_0/CIN
5.806	0.035	tINS	FF	1	R42C57[0][A]	Mdu/u_mdu/reg0_neg_cry_47_0/COUT
5.806	0.000	tNET	FF	2	R42C57[0][B]	Mdu/u_mdu/reg0_neg_cry_48_0/CIN
6.276	0.470	tINS	FF	1	R42C57[0][B]	Mdu/u_mdu/reg0_neg_cry_48_0/SUM
7.231	0.955	tNET	FF	1	R35C48[3][A]	Mdu/u_mdu/reg0_post_swap_2[16]/I2
7.684	0.453	tINS	FF	1	R35C48[3][A]	Mdu/u_mdu/reg0_post_swap_2[16]/F
7.684	0.000	tNET	FF	1	R35C48[3][A]	Mdu/u_mdu/reg0_post_swap_4[16]/I0
7.787	0.103	tINS	FF	1	R35C48[3][A]	Mdu/u_mdu/reg0_post_swap_4[16]/O
8.449	0.662	tNET	FF	1	R40C48[2][A]	Mdu/u_mdu/reg0_post_swap_5[16]/I1
8.902	0.453	tINS	FF	2	R40C48[2][A]	Mdu/u_mdu/reg0_post_swap_5[16]/F
9.514	0.612	tNET	FF	1	R48C48[3][B]	Mdu/u_mdu/reg0_nx_1_cZ[16]/I0
9.885	0.371	tINS	FF	1	R48C48[3][B]	Mdu/u_mdu/reg0_nx_1_cZ[16]/F
10.132	0.247	tNET	FF	1	R48C49[0][B]	Mdu/u_mdu/reg0_nx_cZ[16]/I1
10.681	0.549	tINS	FR	1	R48C49[0][B]	Mdu/u_mdu/reg0_nx_cZ[16]/F
10.681	0.000	tNET	RR	1	R48C49[0][B]	Mdu/u_mdu/reg0_Z[16]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	576	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R48C49[0][B]	Mdu/u_mdu/reg0_Z[16]/CLK
11.683	-0.200	tUnc				Mdu/u_mdu/reg0_Z[16]
11.648	-0.035	tSu		1	R48C49[0][B]	Mdu/u_mdu/reg0_Z[16]

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	8
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 4.225, 48.028%; route: 4.340, 49.335%; tC2Q: 0.232, 2.637%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path18

Path Summary:

Slack	1.079
Data Arrival Time	10.570
Data Required Time	11.648
From	Mdu/u_mdu/reg0_fast_Z[4]
To	memq_memq_0_8
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.683	0.683	tINS	RR	576	IOT48[A]	clk_ibuf/O
1.883	1.201	tNET	RR	1	R48C45[1][B]	Mdu/u_mdu/reg0_fast_Z[4]/CLK
2.115	0.232	tC2Q	RF	7	R48C45[1][B]	Mdu/u_mdu/reg0_fast_Z[4]/Q
3.081	0.966	tNET	FF	1	R42C50[3][A]	Mdu/u_mdu/reg0_neg_axb_4_par_0_cp_0_cZ/I2
3.598	0.517	tINS	FF	1	R42C50[3][A]	Mdu/u_mdu/reg0_neg_axb_4_par_0_cp_0_cZ/F
4.497	0.899	tNET	FF	2	R42C53[1][B]	Mdu/u_mdu/reg0_neg_axb_4_par_cp_0_0/I0
5.067	0.570	tINS	FR	1	R42C53[1][B]	Mdu/u_mdu/reg0_neg_axb_4_par_cp_0_0/COUT
5.067	0.000	tNET	RR	2	R42C53[2][A]	Mdu/u_mdu/reg0_neg_axb_8_par_cp_1/CIN
5.102	0.035	tINS	RF	1	R42C53[2][A]	Mdu/u_mdu/reg0_neg_axb_8_par_cp_1/COUT
5.102	0.000	tNET	FF	2	R42C53[2][B]	Mdu/u_mdu/reg0_neg_axb_12_par_cp_1/CIN
5.137	0.035	tINS	FF	1	R42C53[2][B]	Mdu/u_mdu/reg0_neg_axb_12_par_cp_1/COUT
5.137	0.000	tNET	FF	2	R42C54[0][A]	Mdu/u_mdu/reg0_neg_axb_16_par_cp_1/CIN
5.173	0.035	tINS	FF	1	R42C54[0][A]	Mdu/u_mdu/reg0_neg_axb_16_par_cp_1/COUT
5.173	0.000	tNET	FF	2	R42C54[0][B]	Mdu/u_mdu/reg0_neg_axb_19_par_1/CIN
5.208	0.035	tINS	FF	1	R42C54[0][B]	Mdu/u_mdu/reg0_neg_axb_19_par_1/COUT
5.208	0.000	tNET	FF	2	R42C54[1][A]	Mdu/u_mdu/reg0_neg_axb_23_par_1/CIN
5.243	0.035	tINS	FF	1	R42C54[1][A]	Mdu/u_mdu/reg0_neg_axb_23_par_1/COUT
5.243	0.000	tNET	FF	2	R42C54[1][B]	Mdu/u_mdu/reg0_neg_axb_27_par_1/CIN
5.278	0.035	tINS	FF	1	R42C54[1][B]	Mdu/u_mdu/reg0_neg_axb_27_par_1/COUT
5.278	0.000	tNET	FF	2	R42C54[2][A]	Mdu/u_mdu/reg0_neg_axb_31_par_1/CIN
5.313	0.035	tINS	FF	1	R42C54[2][A]	Mdu/u_mdu/reg0_neg_axb_31_par_1/COUT
5.313	0.000	tNET	FF	2	R42C54[2][B]	Mdu/u_mdu/reg0_neg_cry_34_0/CIN
5.349	0.035	tINS	FF	1	R42C54[2][B]	Mdu/u_mdu/reg0_neg_cry_34_0/COUT
5.349	0.000	tNET	FF	2	R42C55[0][A]	Mdu/u_mdu/reg0_neg_cry_35_0/CIN
5.384	0.035	tINS	FF	1	R42C55[0][A]	Mdu/u_mdu/reg0_neg_cry_35_0/COUT
5.384	0.000	tNET	FF	2	R42C55[0][B]	Mdu/u_mdu/reg0_neg_cry_36_0/CIN
5.419	0.035	tINS	FF	1	R42C55[0][B]	Mdu/u_mdu/reg0_neg_cry_36_0/COUT
5.419	0.000	tNET	FF	2	R42C55[1][A]	Mdu/u_mdu/reg0_neg_cry_37_0/CIN
5.454	0.035	tINS	FF	1	R42C55[1][A]	Mdu/u_mdu/reg0_neg_cry_37_0/COUT
5.454	0.000	tNET	FF	2	R42C55[1][B]	Mdu/u_mdu/reg0_neg_cry_38_0/CIN
5.489	0.035	tINS	FF	1	R42C55[1][B]	Mdu/u_mdu/reg0_neg_cry_38_0/COUT
5.489	0.000	tNET	FF	2	R42C55[2][A]	Mdu/u_mdu/reg0_neg_cry_39_0/CIN
5.525	0.035	tINS	FF	1	R42C55[2][A]	Mdu/u_mdu/reg0_neg_cry_39_0/COUT
5.525	0.000	tNET	FF	2	R42C55[2][B]	Mdu/u_mdu/reg0_neg_cry_40_0/CIN
5.560	0.035	tINS	FF	1	R42C55[2][B]	Mdu/u_mdu/reg0_neg_cry_40_0/COUT
5.560	0.000	tNET	FF	2	R42C56[0][A]	Mdu/u_mdu/reg0_neg_cry_41_0/CIN
5.595	0.035	tINS	FF	1	R42C56[0][A]	Mdu/u_mdu/reg0_neg_cry_41_0/COUT
5.595	0.000	tNET	FF	2	R42C56[0][B]	Mdu/u_mdu/reg0_neg_cry_42_0/CIN
5.630	0.035	tINS	FF	1	R42C56[0][B]	Mdu/u_mdu/reg0_neg_cry_42_0/COUT
5.630	0.000	tNET	FF	2	R42C56[1][A]	Mdu/u_mdu/reg0_neg_cry_43_0/CIN
5.665	0.035	tINS	FF	1	R42C56[1][A]	Mdu/u_mdu/reg0_neg_cry_43_0/COUT
5.665	0.000	tNET	FF	2	R42C56[1][B]	Mdu/u_mdu/reg0_neg_cry_44_0/CIN
5.701	0.035	tINS	FF	1	R42C56[1][B]	Mdu/u_mdu/reg0_neg_cry_44_0/COUT
5.701	0.000	tNET	FF	2	R42C56[2][A]	Mdu/u_mdu/reg0_neg_cry_45_0/CIN
5.736	0.035	tINS	FF	1	R42C56[2][A]	Mdu/u_mdu/reg0_neg_cry_45_0/COUT
5.736	0.000	tNET	FF	2	R42C56[2][B]	Mdu/u_mdu/reg0_neg_cry_46_0/CIN
5.771	0.035	tINS	FF	1	R42C56[2][B]	Mdu/u_mdu/reg0_neg_cry_46_0/COUT
5.771	0.000	tNET	FF	2	R42C57[0][A]	Mdu/u_mdu/reg0_neg_cry_47_0/CIN
5.806	0.035	tINS	FF	1	R42C57[0][A]	Mdu/u_mdu/reg0_neg_cry_47_0/COUT
5.806	0.000	tNET	FF	2	R42C57[0][B]	Mdu/u_mdu/reg0_neg_cry_48_0/CIN
6.276	0.470	tINS	FF	1	R42C57[0][B]	Mdu/u_mdu/reg0_neg_cry_48_0/SUM
7.231	0.955	tNET	FF	1	R35C48[3][A]	Mdu/u_mdu/reg0_post_swap_2[16]/I2
7.684	0.453	tINS	FF	1	R35C48[3][A]	Mdu/u_mdu/reg0_post_swap_2[16]/F
7.684	0.000	tNET	FF	1	R35C48[3][A]	Mdu/u_mdu/reg0_post_swap_4[16]/I0
7.787	0.103	tINS	FF	1	R35C48[3][A]	Mdu/u_mdu/reg0_post_swap_4[16]/O
8.449	0.662	tNET	FF	1	R40C48[2][A]	Mdu/u_mdu/reg0_post_swap_5[16]/I1
8.902	0.453	tINS	FF	2	R40C48[2][A]	Mdu/u_mdu/reg0_post_swap_5[16]/F
9.153	0.252	tNET	FF	1	R40C46[3][A]	Mdu/u_mdu/res0_cZ[16]/I1
9.606	0.453	tINS	FF	3	R40C46[3][A]	Mdu/u_mdu/res0_cZ[16]/F
10.570	0.964	tNET	FF	1	BSRAM_R54[15]	memq_memq_0_8/DI0

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	576	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	BSRAM_R54[15]	memq_memq_0_8/CLKA
11.683	-0.200	tUnc				memq_memq_0_8
11.648	-0.035	tSu		1	BSRAM_R54[15]	memq_memq_0_8

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 3.758, 43.263%; route: 4.697, 54.066%; tC2Q: 0.232, 2.671%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path19

Path Summary:

Slack	1.169
Data Arrival Time	10.479
Data Required Time	11.648
From	Mdu/u_mdu/reg0_fast_Z[4]
To	Mdu/u_mdu/reg0_Z[18]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.683	0.683	tINS	RR	576	IOT48[A]	clk_ibuf/O
1.883	1.201	tNET	RR	1	R48C45[1][B]	Mdu/u_mdu/reg0_fast_Z[4]/CLK
2.115	0.232	tC2Q	RF	7	R48C45[1][B]	Mdu/u_mdu/reg0_fast_Z[4]/Q
3.081	0.966	tNET	FF	1	R42C50[3][A]	Mdu/u_mdu/reg0_neg_axb_4_par_0_cp_0_cZ/I2
3.598	0.517	tINS	FF	1	R42C50[3][A]	Mdu/u_mdu/reg0_neg_axb_4_par_0_cp_0_cZ/F
4.497	0.899	tNET	FF	2	R42C53[1][B]	Mdu/u_mdu/reg0_neg_axb_4_par_cp_0_0/I0
5.067	0.570	tINS	FR	1	R42C53[1][B]	Mdu/u_mdu/reg0_neg_axb_4_par_cp_0_0/COUT
5.067	0.000	tNET	RR	2	R42C53[2][A]	Mdu/u_mdu/reg0_neg_axb_8_par_cp_1/CIN
5.102	0.035	tINS	RF	1	R42C53[2][A]	Mdu/u_mdu/reg0_neg_axb_8_par_cp_1/COUT
5.102	0.000	tNET	FF	2	R42C53[2][B]	Mdu/u_mdu/reg0_neg_axb_12_par_cp_1/CIN
5.137	0.035	tINS	FF	1	R42C53[2][B]	Mdu/u_mdu/reg0_neg_axb_12_par_cp_1/COUT
5.137	0.000	tNET	FF	2	R42C54[0][A]	Mdu/u_mdu/reg0_neg_axb_16_par_cp_1/CIN
5.173	0.035	tINS	FF	1	R42C54[0][A]	Mdu/u_mdu/reg0_neg_axb_16_par_cp_1/COUT
5.173	0.000	tNET	FF	2	R42C54[0][B]	Mdu/u_mdu/reg0_neg_axb_19_par_1/CIN
5.208	0.035	tINS	FF	1	R42C54[0][B]	Mdu/u_mdu/reg0_neg_axb_19_par_1/COUT
5.208	0.000	tNET	FF	2	R42C54[1][A]	Mdu/u_mdu/reg0_neg_axb_23_par_1/CIN
5.243	0.035	tINS	FF	1	R42C54[1][A]	Mdu/u_mdu/reg0_neg_axb_23_par_1/COUT
5.243	0.000	tNET	FF	2	R42C54[1][B]	Mdu/u_mdu/reg0_neg_axb_27_par_1/CIN
5.278	0.035	tINS	FF	1	R42C54[1][B]	Mdu/u_mdu/reg0_neg_axb_27_par_1/COUT
5.278	0.000	tNET	FF	2	R42C54[2][A]	Mdu/u_mdu/reg0_neg_axb_31_par_1/CIN
5.313	0.035	tINS	FF	1	R42C54[2][A]	Mdu/u_mdu/reg0_neg_axb_31_par_1/COUT
5.313	0.000	tNET	FF	2	R42C54[2][B]	Mdu/u_mdu/reg0_neg_cry_34_0/CIN
5.349	0.035	tINS	FF	1	R42C54[2][B]	Mdu/u_mdu/reg0_neg_cry_34_0/COUT
5.349	0.000	tNET	FF	2	R42C55[0][A]	Mdu/u_mdu/reg0_neg_cry_35_0/CIN
5.384	0.035	tINS	FF	1	R42C55[0][A]	Mdu/u_mdu/reg0_neg_cry_35_0/COUT
5.384	0.000	tNET	FF	2	R42C55[0][B]	Mdu/u_mdu/reg0_neg_cry_36_0/CIN
5.419	0.035	tINS	FF	1	R42C55[0][B]	Mdu/u_mdu/reg0_neg_cry_36_0/COUT
5.419	0.000	tNET	FF	2	R42C55[1][A]	Mdu/u_mdu/reg0_neg_cry_37_0/CIN
5.454	0.035	tINS	FF	1	R42C55[1][A]	Mdu/u_mdu/reg0_neg_cry_37_0/COUT
5.454	0.000	tNET	FF	2	R42C55[1][B]	Mdu/u_mdu/reg0_neg_cry_38_0/CIN
5.489	0.035	tINS	FF	1	R42C55[1][B]	Mdu/u_mdu/reg0_neg_cry_38_0/COUT
5.489	0.000	tNET	FF	2	R42C55[2][A]	Mdu/u_mdu/reg0_neg_cry_39_0/CIN
5.525	0.035	tINS	FF	1	R42C55[2][A]	Mdu/u_mdu/reg0_neg_cry_39_0/COUT
5.525	0.000	tNET	FF	2	R42C55[2][B]	Mdu/u_mdu/reg0_neg_cry_40_0/CIN
5.560	0.035	tINS	FF	1	R42C55[2][B]	Mdu/u_mdu/reg0_neg_cry_40_0/COUT
5.560	0.000	tNET	FF	2	R42C56[0][A]	Mdu/u_mdu/reg0_neg_cry_41_0/CIN
5.595	0.035	tINS	FF	1	R42C56[0][A]	Mdu/u_mdu/reg0_neg_cry_41_0/COUT
5.595	0.000	tNET	FF	2	R42C56[0][B]	Mdu/u_mdu/reg0_neg_cry_42_0/CIN
5.630	0.035	tINS	FF	1	R42C56[0][B]	Mdu/u_mdu/reg0_neg_cry_42_0/COUT
5.630	0.000	tNET	FF	2	R42C56[1][A]	Mdu/u_mdu/reg0_neg_cry_43_0/CIN
5.665	0.035	tINS	FF	1	R42C56[1][A]	Mdu/u_mdu/reg0_neg_cry_43_0/COUT
5.665	0.000	tNET	FF	2	R42C56[1][B]	Mdu/u_mdu/reg0_neg_cry_44_0/CIN
5.701	0.035	tINS	FF	1	R42C56[1][B]	Mdu/u_mdu/reg0_neg_cry_44_0/COUT
5.701	0.000	tNET	FF	2	R42C56[2][A]	Mdu/u_mdu/reg0_neg_cry_45_0/CIN
5.736	0.035	tINS	FF	1	R42C56[2][A]	Mdu/u_mdu/reg0_neg_cry_45_0/COUT
5.736	0.000	tNET	FF	2	R42C56[2][B]	Mdu/u_mdu/reg0_neg_cry_46_0/CIN
5.771	0.035	tINS	FF	1	R42C56[2][B]	Mdu/u_mdu/reg0_neg_cry_46_0/COUT
5.771	0.000	tNET	FF	2	R42C57[0][A]	Mdu/u_mdu/reg0_neg_cry_47_0/CIN
5.806	0.035	tINS	FF	1	R42C57[0][A]	Mdu/u_mdu/reg0_neg_cry_47_0/COUT
5.806	0.000	tNET	FF	2	R42C57[0][B]	Mdu/u_mdu/reg0_neg_cry_48_0/CIN
5.841	0.035	tINS	FF	1	R42C57[0][B]	Mdu/u_mdu/reg0_neg_cry_48_0/COUT
5.841	0.000	tNET	FF	2	R42C57[1][A]	Mdu/u_mdu/reg0_neg_cry_49_0/CIN
5.877	0.035	tINS	FF	1	R42C57[1][A]	Mdu/u_mdu/reg0_neg_cry_49_0/COUT
5.877	0.000	tNET	FF	2	R42C57[1][B]	Mdu/u_mdu/reg0_neg_cry_50_0/CIN
6.347	0.470	tINS	FF	1	R42C57[1][B]	Mdu/u_mdu/reg0_neg_cry_50_0/SUM
7.135	0.789	tNET	FF	1	R34C48[3][A]	Mdu/u_mdu/reg0_post_swap_2[18]/I2
7.506	0.371	tINS	FF	1	R34C48[3][A]	Mdu/u_mdu/reg0_post_swap_2[18]/F
7.506	0.000	tNET	FF	1	R34C48[3][A]	Mdu/u_mdu/reg0_post_swap_4[18]/I0
7.609	0.103	tINS	FF	2	R34C48[3][A]	Mdu/u_mdu/reg0_post_swap_4[18]/O
8.520	0.910	tNET	FF	1	R34C48[1][B]	Mdu/u_mdu/un11_reg0_nx_cZ[18]_cZ/I1
8.973	0.453	tINS	FF	3	R34C48[1][B]	Mdu/u_mdu/un11_reg0_nx_cZ[18]_cZ/F
9.909	0.937	tNET	FF	1	R46C47[2][A]	Mdu/u_mdu/reg0_nx_cZ[18]/I3
10.479	0.570	tINS	FR	1	R46C47[2][A]	Mdu/u_mdu/reg0_nx_cZ[18]/F
10.479	0.000	tNET	RR	1	R46C47[2][A]	Mdu/u_mdu/reg0_Z[18]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	576	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R46C47[2][A]	Mdu/u_mdu/reg0_Z[18]/CLK
11.683	-0.200	tUnc				Mdu/u_mdu/reg0_Z[18]
11.648	-0.035	tSu		1	R46C47[2][A]	Mdu/u_mdu/reg0_Z[18]

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 3.864, 44.945%; route: 4.501, 52.356%; tC2Q: 0.232, 2.699%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path20

Path Summary:

Slack	1.190
Data Arrival Time	10.458
Data Required Time	11.648
From	Mdu/u_mdu/reg0_fast_Z[4]
To	Mdu/u_mdu/reg0_fast_Z[18]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.683	0.683	tINS	RR	576	IOT48[A]	clk_ibuf/O
1.883	1.201	tNET	RR	1	R48C45[1][B]	Mdu/u_mdu/reg0_fast_Z[4]/CLK
2.115	0.232	tC2Q	RF	7	R48C45[1][B]	Mdu/u_mdu/reg0_fast_Z[4]/Q
3.081	0.966	tNET	FF	1	R42C50[3][A]	Mdu/u_mdu/reg0_neg_axb_4_par_0_cp_0_cZ/I2
3.598	0.517	tINS	FF	1	R42C50[3][A]	Mdu/u_mdu/reg0_neg_axb_4_par_0_cp_0_cZ/F
4.497	0.899	tNET	FF	2	R42C53[1][B]	Mdu/u_mdu/reg0_neg_axb_4_par_cp_0_0/I0
5.067	0.570	tINS	FR	1	R42C53[1][B]	Mdu/u_mdu/reg0_neg_axb_4_par_cp_0_0/COUT
5.067	0.000	tNET	RR	2	R42C53[2][A]	Mdu/u_mdu/reg0_neg_axb_8_par_cp_1/CIN
5.102	0.035	tINS	RF	1	R42C53[2][A]	Mdu/u_mdu/reg0_neg_axb_8_par_cp_1/COUT
5.102	0.000	tNET	FF	2	R42C53[2][B]	Mdu/u_mdu/reg0_neg_axb_12_par_cp_1/CIN
5.137	0.035	tINS	FF	1	R42C53[2][B]	Mdu/u_mdu/reg0_neg_axb_12_par_cp_1/COUT
5.137	0.000	tNET	FF	2	R42C54[0][A]	Mdu/u_mdu/reg0_neg_axb_16_par_cp_1/CIN
5.173	0.035	tINS	FF	1	R42C54[0][A]	Mdu/u_mdu/reg0_neg_axb_16_par_cp_1/COUT
5.173	0.000	tNET	FF	2	R42C54[0][B]	Mdu/u_mdu/reg0_neg_axb_19_par_1/CIN
5.208	0.035	tINS	FF	1	R42C54[0][B]	Mdu/u_mdu/reg0_neg_axb_19_par_1/COUT
5.208	0.000	tNET	FF	2	R42C54[1][A]	Mdu/u_mdu/reg0_neg_axb_23_par_1/CIN
5.243	0.035	tINS	FF	1	R42C54[1][A]	Mdu/u_mdu/reg0_neg_axb_23_par_1/COUT
5.243	0.000	tNET	FF	2	R42C54[1][B]	Mdu/u_mdu/reg0_neg_axb_27_par_1/CIN
5.278	0.035	tINS	FF	1	R42C54[1][B]	Mdu/u_mdu/reg0_neg_axb_27_par_1/COUT
5.278	0.000	tNET	FF	2	R42C54[2][A]	Mdu/u_mdu/reg0_neg_axb_31_par_1/CIN
5.313	0.035	tINS	FF	1	R42C54[2][A]	Mdu/u_mdu/reg0_neg_axb_31_par_1/COUT
5.313	0.000	tNET	FF	2	R42C54[2][B]	Mdu/u_mdu/reg0_neg_cry_34_0/CIN
5.349	0.035	tINS	FF	1	R42C54[2][B]	Mdu/u_mdu/reg0_neg_cry_34_0/COUT
5.349	0.000	tNET	FF	2	R42C55[0][A]	Mdu/u_mdu/reg0_neg_cry_35_0/CIN
5.384	0.035	tINS	FF	1	R42C55[0][A]	Mdu/u_mdu/reg0_neg_cry_35_0/COUT
5.384	0.000	tNET	FF	2	R42C55[0][B]	Mdu/u_mdu/reg0_neg_cry_36_0/CIN
5.419	0.035	tINS	FF	1	R42C55[0][B]	Mdu/u_mdu/reg0_neg_cry_36_0/COUT
5.419	0.000	tNET	FF	2	R42C55[1][A]	Mdu/u_mdu/reg0_neg_cry_37_0/CIN
5.454	0.035	tINS	FF	1	R42C55[1][A]	Mdu/u_mdu/reg0_neg_cry_37_0/COUT
5.454	0.000	tNET	FF	2	R42C55[1][B]	Mdu/u_mdu/reg0_neg_cry_38_0/CIN
5.489	0.035	tINS	FF	1	R42C55[1][B]	Mdu/u_mdu/reg0_neg_cry_38_0/COUT
5.489	0.000	tNET	FF	2	R42C55[2][A]	Mdu/u_mdu/reg0_neg_cry_39_0/CIN
5.525	0.035	tINS	FF	1	R42C55[2][A]	Mdu/u_mdu/reg0_neg_cry_39_0/COUT
5.525	0.000	tNET	FF	2	R42C55[2][B]	Mdu/u_mdu/reg0_neg_cry_40_0/CIN
5.560	0.035	tINS	FF	1	R42C55[2][B]	Mdu/u_mdu/reg0_neg_cry_40_0/COUT
5.560	0.000	tNET	FF	2	R42C56[0][A]	Mdu/u_mdu/reg0_neg_cry_41_0/CIN
5.595	0.035	tINS	FF	1	R42C56[0][A]	Mdu/u_mdu/reg0_neg_cry_41_0/COUT
5.595	0.000	tNET	FF	2	R42C56[0][B]	Mdu/u_mdu/reg0_neg_cry_42_0/CIN
5.630	0.035	tINS	FF	1	R42C56[0][B]	Mdu/u_mdu/reg0_neg_cry_42_0/COUT
5.630	0.000	tNET	FF	2	R42C56[1][A]	Mdu/u_mdu/reg0_neg_cry_43_0/CIN
5.665	0.035	tINS	FF	1	R42C56[1][A]	Mdu/u_mdu/reg0_neg_cry_43_0/COUT
5.665	0.000	tNET	FF	2	R42C56[1][B]	Mdu/u_mdu/reg0_neg_cry_44_0/CIN
5.701	0.035	tINS	FF	1	R42C56[1][B]	Mdu/u_mdu/reg0_neg_cry_44_0/COUT
5.701	0.000	tNET	FF	2	R42C56[2][A]	Mdu/u_mdu/reg0_neg_cry_45_0/CIN
5.736	0.035	tINS	FF	1	R42C56[2][A]	Mdu/u_mdu/reg0_neg_cry_45_0/COUT
5.736	0.000	tNET	FF	2	R42C56[2][B]	Mdu/u_mdu/reg0_neg_cry_46_0/CIN
5.771	0.035	tINS	FF	1	R42C56[2][B]	Mdu/u_mdu/reg0_neg_cry_46_0/COUT
5.771	0.000	tNET	FF	2	R42C57[0][A]	Mdu/u_mdu/reg0_neg_cry_47_0/CIN
5.806	0.035	tINS	FF	1	R42C57[0][A]	Mdu/u_mdu/reg0_neg_cry_47_0/COUT
5.806	0.000	tNET	FF	2	R42C57[0][B]	Mdu/u_mdu/reg0_neg_cry_48_0/CIN
5.841	0.035	tINS	FF	1	R42C57[0][B]	Mdu/u_mdu/reg0_neg_cry_48_0/COUT
5.841	0.000	tNET	FF	2	R42C57[1][A]	Mdu/u_mdu/reg0_neg_cry_49_0/CIN
5.877	0.035	tINS	FF	1	R42C57[1][A]	Mdu/u_mdu/reg0_neg_cry_49_0/COUT
5.877	0.000	tNET	FF	2	R42C57[1][B]	Mdu/u_mdu/reg0_neg_cry_50_0/CIN
6.347	0.470	tINS	FF	1	R42C57[1][B]	Mdu/u_mdu/reg0_neg_cry_50_0/SUM
7.135	0.789	tNET	FF	1	R34C48[3][A]	Mdu/u_mdu/reg0_post_swap_2[18]/I2
7.506	0.371	tINS	FF	1	R34C48[3][A]	Mdu/u_mdu/reg0_post_swap_2[18]/F
7.506	0.000	tNET	FF	1	R34C48[3][A]	Mdu/u_mdu/reg0_post_swap_4[18]/I0
7.609	0.103	tINS	FF	2	R34C48[3][A]	Mdu/u_mdu/reg0_post_swap_4[18]/O
8.520	0.910	tNET	FF	1	R34C48[1][B]	Mdu/u_mdu/un11_reg0_nx_cZ[18]_cZ/I1
8.973	0.453	tINS	FF	3	R34C48[1][B]	Mdu/u_mdu/un11_reg0_nx_cZ[18]_cZ/F
9.909	0.937	tNET	FF	1	R46C47[0][B]	Mdu/u_mdu/reg0_nx_fast_cZ[18]/I3
10.458	0.549	tINS	FR	1	R46C47[0][B]	Mdu/u_mdu/reg0_nx_fast_cZ[18]/F
10.458	0.000	tNET	RR	1	R46C47[0][B]	Mdu/u_mdu/reg0_fast_Z[18]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	576	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R46C47[0][B]	Mdu/u_mdu/reg0_fast_Z[18]/CLK
11.683	-0.200	tUnc				Mdu/u_mdu/reg0_fast_Z[18]
11.648	-0.035	tSu		1	R46C47[0][B]	Mdu/u_mdu/reg0_fast_Z[18]

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 3.843, 44.810%; route: 4.501, 52.484%; tC2Q: 0.232, 2.705%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path21

Path Summary:

Slack	1.292
Data Arrival Time	10.356
Data Required Time	11.648
From	Mdu/u_mdu/reg0_fast_Z[4]
To	Mdu/u_mdu/reg0_Z[21]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.683	0.683	tINS	RR	576	IOT48[A]	clk_ibuf/O
1.883	1.201	tNET	RR	1	R48C45[1][B]	Mdu/u_mdu/reg0_fast_Z[4]/CLK
2.115	0.232	tC2Q	RF	7	R48C45[1][B]	Mdu/u_mdu/reg0_fast_Z[4]/Q
3.081	0.966	tNET	FF	1	R42C50[3][A]	Mdu/u_mdu/reg0_neg_axb_4_par_0_cp_0_cZ/I2
3.598	0.517	tINS	FF	1	R42C50[3][A]	Mdu/u_mdu/reg0_neg_axb_4_par_0_cp_0_cZ/F
4.497	0.899	tNET	FF	2	R42C53[1][B]	Mdu/u_mdu/reg0_neg_axb_4_par_cp_0_0/I0
5.067	0.570	tINS	FR	1	R42C53[1][B]	Mdu/u_mdu/reg0_neg_axb_4_par_cp_0_0/COUT
5.067	0.000	tNET	RR	2	R42C53[2][A]	Mdu/u_mdu/reg0_neg_axb_8_par_cp_1/CIN
5.102	0.035	tINS	RF	1	R42C53[2][A]	Mdu/u_mdu/reg0_neg_axb_8_par_cp_1/COUT
5.102	0.000	tNET	FF	2	R42C53[2][B]	Mdu/u_mdu/reg0_neg_axb_12_par_cp_1/CIN
5.137	0.035	tINS	FF	1	R42C53[2][B]	Mdu/u_mdu/reg0_neg_axb_12_par_cp_1/COUT
5.137	0.000	tNET	FF	2	R42C54[0][A]	Mdu/u_mdu/reg0_neg_axb_16_par_cp_1/CIN
5.173	0.035	tINS	FF	1	R42C54[0][A]	Mdu/u_mdu/reg0_neg_axb_16_par_cp_1/COUT
5.173	0.000	tNET	FF	2	R42C54[0][B]	Mdu/u_mdu/reg0_neg_axb_19_par_1/CIN
5.208	0.035	tINS	FF	1	R42C54[0][B]	Mdu/u_mdu/reg0_neg_axb_19_par_1/COUT
5.208	0.000	tNET	FF	2	R42C54[1][A]	Mdu/u_mdu/reg0_neg_axb_23_par_1/CIN
5.243	0.035	tINS	FF	1	R42C54[1][A]	Mdu/u_mdu/reg0_neg_axb_23_par_1/COUT
5.243	0.000	tNET	FF	2	R42C54[1][B]	Mdu/u_mdu/reg0_neg_axb_27_par_1/CIN
5.278	0.035	tINS	FF	1	R42C54[1][B]	Mdu/u_mdu/reg0_neg_axb_27_par_1/COUT
5.278	0.000	tNET	FF	2	R42C54[2][A]	Mdu/u_mdu/reg0_neg_axb_31_par_1/CIN
5.313	0.035	tINS	FF	1	R42C54[2][A]	Mdu/u_mdu/reg0_neg_axb_31_par_1/COUT
5.313	0.000	tNET	FF	2	R42C54[2][B]	Mdu/u_mdu/reg0_neg_cry_34_0/CIN
5.349	0.035	tINS	FF	1	R42C54[2][B]	Mdu/u_mdu/reg0_neg_cry_34_0/COUT
5.349	0.000	tNET	FF	2	R42C55[0][A]	Mdu/u_mdu/reg0_neg_cry_35_0/CIN
5.384	0.035	tINS	FF	1	R42C55[0][A]	Mdu/u_mdu/reg0_neg_cry_35_0/COUT
5.384	0.000	tNET	FF	2	R42C55[0][B]	Mdu/u_mdu/reg0_neg_cry_36_0/CIN
5.419	0.035	tINS	FF	1	R42C55[0][B]	Mdu/u_mdu/reg0_neg_cry_36_0/COUT
5.419	0.000	tNET	FF	2	R42C55[1][A]	Mdu/u_mdu/reg0_neg_cry_37_0/CIN
5.454	0.035	tINS	FF	1	R42C55[1][A]	Mdu/u_mdu/reg0_neg_cry_37_0/COUT
5.454	0.000	tNET	FF	2	R42C55[1][B]	Mdu/u_mdu/reg0_neg_cry_38_0/CIN
5.489	0.035	tINS	FF	1	R42C55[1][B]	Mdu/u_mdu/reg0_neg_cry_38_0/COUT
5.489	0.000	tNET	FF	2	R42C55[2][A]	Mdu/u_mdu/reg0_neg_cry_39_0/CIN
5.525	0.035	tINS	FF	1	R42C55[2][A]	Mdu/u_mdu/reg0_neg_cry_39_0/COUT
5.525	0.000	tNET	FF	2	R42C55[2][B]	Mdu/u_mdu/reg0_neg_cry_40_0/CIN
5.560	0.035	tINS	FF	1	R42C55[2][B]	Mdu/u_mdu/reg0_neg_cry_40_0/COUT
5.560	0.000	tNET	FF	2	R42C56[0][A]	Mdu/u_mdu/reg0_neg_cry_41_0/CIN
5.595	0.035	tINS	FF	1	R42C56[0][A]	Mdu/u_mdu/reg0_neg_cry_41_0/COUT
5.595	0.000	tNET	FF	2	R42C56[0][B]	Mdu/u_mdu/reg0_neg_cry_42_0/CIN
5.630	0.035	tINS	FF	1	R42C56[0][B]	Mdu/u_mdu/reg0_neg_cry_42_0/COUT
5.630	0.000	tNET	FF	2	R42C56[1][A]	Mdu/u_mdu/reg0_neg_cry_43_0/CIN
5.665	0.035	tINS	FF	1	R42C56[1][A]	Mdu/u_mdu/reg0_neg_cry_43_0/COUT
5.665	0.000	tNET	FF	2	R42C56[1][B]	Mdu/u_mdu/reg0_neg_cry_44_0/CIN
5.701	0.035	tINS	FF	1	R42C56[1][B]	Mdu/u_mdu/reg0_neg_cry_44_0/COUT
5.701	0.000	tNET	FF	2	R42C56[2][A]	Mdu/u_mdu/reg0_neg_cry_45_0/CIN
5.736	0.035	tINS	FF	1	R42C56[2][A]	Mdu/u_mdu/reg0_neg_cry_45_0/COUT
5.736	0.000	tNET	FF	2	R42C56[2][B]	Mdu/u_mdu/reg0_neg_cry_46_0/CIN
5.771	0.035	tINS	FF	1	R42C56[2][B]	Mdu/u_mdu/reg0_neg_cry_46_0/COUT
5.771	0.000	tNET	FF	2	R42C57[0][A]	Mdu/u_mdu/reg0_neg_cry_47_0/CIN
5.806	0.035	tINS	FF	1	R42C57[0][A]	Mdu/u_mdu/reg0_neg_cry_47_0/COUT
5.806	0.000	tNET	FF	2	R42C57[0][B]	Mdu/u_mdu/reg0_neg_cry_48_0/CIN
5.841	0.035	tINS	FF	1	R42C57[0][B]	Mdu/u_mdu/reg0_neg_cry_48_0/COUT
5.841	0.000	tNET	FF	2	R42C57[1][A]	Mdu/u_mdu/reg0_neg_cry_49_0/CIN
5.877	0.035	tINS	FF	1	R42C57[1][A]	Mdu/u_mdu/reg0_neg_cry_49_0/COUT
5.877	0.000	tNET	FF	2	R42C57[1][B]	Mdu/u_mdu/reg0_neg_cry_50_0/CIN
5.912	0.035	tINS	FF	1	R42C57[1][B]	Mdu/u_mdu/reg0_neg_cry_50_0/COUT
5.912	0.000	tNET	FF	2	R42C57[2][A]	Mdu/u_mdu/reg0_neg_cry_51_0/CIN
5.947	0.035	tINS	FF	1	R42C57[2][A]	Mdu/u_mdu/reg0_neg_cry_51_0/COUT
5.947	0.000	tNET	FF	2	R42C57[2][B]	Mdu/u_mdu/reg0_neg_cry_52_0/CIN
5.982	0.035	tINS	FF	1	R42C57[2][B]	Mdu/u_mdu/reg0_neg_cry_52_0/COUT
5.982	0.000	tNET	FF	2	R42C58[0][A]	Mdu/u_mdu/reg0_neg_s_53_0/CIN
6.452	0.470	tINS	FF	1	R42C58[0][A]	Mdu/u_mdu/reg0_neg_s_53_0/SUM
7.573	1.121	tNET	FF	1	R35C48[2][A]	Mdu/u_mdu/reg0_post_swap_2[21]/I2
7.944	0.371	tINS	FF	1	R35C48[2][A]	Mdu/u_mdu/reg0_post_swap_2[21]/F
7.944	0.000	tNET	FF	1	R35C48[2][A]	Mdu/u_mdu/reg0_post_swap_4[21]/I0
8.047	0.103	tINS	FF	1	R35C48[2][A]	Mdu/u_mdu/reg0_post_swap_4[21]/O
8.300	0.253	tNET	FF	1	R35C48[0][B]	Mdu/u_mdu/reg0_post_swap_5[21]/I1
8.855	0.555	tINS	FF	2	R35C48[0][B]	Mdu/u_mdu/reg0_post_swap_5[21]/F
9.786	0.931	tNET	FF	1	R48C48[0][A]	Mdu/u_mdu/reg0_nx_cZ[21]/I1
10.356	0.570	tINS	FR	1	R48C48[0][A]	Mdu/u_mdu/reg0_nx_cZ[21]/F
10.356	0.000	tNET	RR	1	R48C48[0][A]	Mdu/u_mdu/reg0_Z[21]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	576	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R48C48[0][A]	Mdu/u_mdu/reg0_Z[21]/CLK
11.683	-0.200	tUnc				Mdu/u_mdu/reg0_Z[21]
11.648	-0.035	tSu		1	R48C48[0][A]	Mdu/u_mdu/reg0_Z[21]

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 4.071, 48.049%; route: 4.170, 49.213%; tC2Q: 0.232, 2.738%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path22

Path Summary:

Slack	1.341
Data Arrival Time	10.307
Data Required Time	11.648
From	Mdu/u_mdu/reg0_fast_Z[4]
To	memq_memq_0_10
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.683	0.683	tINS	RR	576	IOT48[A]	clk_ibuf/O
1.883	1.201	tNET	RR	1	R48C45[1][B]	Mdu/u_mdu/reg0_fast_Z[4]/CLK
2.115	0.232	tC2Q	RF	7	R48C45[1][B]	Mdu/u_mdu/reg0_fast_Z[4]/Q
3.081	0.966	tNET	FF	1	R42C50[3][A]	Mdu/u_mdu/reg0_neg_axb_4_par_0_cp_0_cZ/I2
3.598	0.517	tINS	FF	1	R42C50[3][A]	Mdu/u_mdu/reg0_neg_axb_4_par_0_cp_0_cZ/F
4.497	0.899	tNET	FF	2	R42C53[1][B]	Mdu/u_mdu/reg0_neg_axb_4_par_cp_0_0/I0
5.067	0.570	tINS	FR	1	R42C53[1][B]	Mdu/u_mdu/reg0_neg_axb_4_par_cp_0_0/COUT
5.067	0.000	tNET	RR	2	R42C53[2][A]	Mdu/u_mdu/reg0_neg_axb_8_par_cp_1/CIN
5.102	0.035	tINS	RF	1	R42C53[2][A]	Mdu/u_mdu/reg0_neg_axb_8_par_cp_1/COUT
5.102	0.000	tNET	FF	2	R42C53[2][B]	Mdu/u_mdu/reg0_neg_axb_12_par_cp_1/CIN
5.137	0.035	tINS	FF	1	R42C53[2][B]	Mdu/u_mdu/reg0_neg_axb_12_par_cp_1/COUT
5.137	0.000	tNET	FF	2	R42C54[0][A]	Mdu/u_mdu/reg0_neg_axb_16_par_cp_1/CIN
5.173	0.035	tINS	FF	1	R42C54[0][A]	Mdu/u_mdu/reg0_neg_axb_16_par_cp_1/COUT
5.173	0.000	tNET	FF	2	R42C54[0][B]	Mdu/u_mdu/reg0_neg_axb_19_par_1/CIN
5.208	0.035	tINS	FF	1	R42C54[0][B]	Mdu/u_mdu/reg0_neg_axb_19_par_1/COUT
5.208	0.000	tNET	FF	2	R42C54[1][A]	Mdu/u_mdu/reg0_neg_axb_23_par_1/CIN
5.243	0.035	tINS	FF	1	R42C54[1][A]	Mdu/u_mdu/reg0_neg_axb_23_par_1/COUT
5.243	0.000	tNET	FF	2	R42C54[1][B]	Mdu/u_mdu/reg0_neg_axb_27_par_1/CIN
5.278	0.035	tINS	FF	1	R42C54[1][B]	Mdu/u_mdu/reg0_neg_axb_27_par_1/COUT
5.278	0.000	tNET	FF	2	R42C54[2][A]	Mdu/u_mdu/reg0_neg_axb_31_par_1/CIN
5.313	0.035	tINS	FF	1	R42C54[2][A]	Mdu/u_mdu/reg0_neg_axb_31_par_1/COUT
5.313	0.000	tNET	FF	2	R42C54[2][B]	Mdu/u_mdu/reg0_neg_cry_34_0/CIN
5.349	0.035	tINS	FF	1	R42C54[2][B]	Mdu/u_mdu/reg0_neg_cry_34_0/COUT
5.349	0.000	tNET	FF	2	R42C55[0][A]	Mdu/u_mdu/reg0_neg_cry_35_0/CIN
5.384	0.035	tINS	FF	1	R42C55[0][A]	Mdu/u_mdu/reg0_neg_cry_35_0/COUT
5.384	0.000	tNET	FF	2	R42C55[0][B]	Mdu/u_mdu/reg0_neg_cry_36_0/CIN
5.419	0.035	tINS	FF	1	R42C55[0][B]	Mdu/u_mdu/reg0_neg_cry_36_0/COUT
5.419	0.000	tNET	FF	2	R42C55[1][A]	Mdu/u_mdu/reg0_neg_cry_37_0/CIN
5.454	0.035	tINS	FF	1	R42C55[1][A]	Mdu/u_mdu/reg0_neg_cry_37_0/COUT
5.454	0.000	tNET	FF	2	R42C55[1][B]	Mdu/u_mdu/reg0_neg_cry_38_0/CIN
5.489	0.035	tINS	FF	1	R42C55[1][B]	Mdu/u_mdu/reg0_neg_cry_38_0/COUT
5.489	0.000	tNET	FF	2	R42C55[2][A]	Mdu/u_mdu/reg0_neg_cry_39_0/CIN
5.525	0.035	tINS	FF	1	R42C55[2][A]	Mdu/u_mdu/reg0_neg_cry_39_0/COUT
5.525	0.000	tNET	FF	2	R42C55[2][B]	Mdu/u_mdu/reg0_neg_cry_40_0/CIN
5.560	0.035	tINS	FF	1	R42C55[2][B]	Mdu/u_mdu/reg0_neg_cry_40_0/COUT
5.560	0.000	tNET	FF	2	R42C56[0][A]	Mdu/u_mdu/reg0_neg_cry_41_0/CIN
5.595	0.035	tINS	FF	1	R42C56[0][A]	Mdu/u_mdu/reg0_neg_cry_41_0/COUT
5.595	0.000	tNET	FF	2	R42C56[0][B]	Mdu/u_mdu/reg0_neg_cry_42_0/CIN
5.630	0.035	tINS	FF	1	R42C56[0][B]	Mdu/u_mdu/reg0_neg_cry_42_0/COUT
5.630	0.000	tNET	FF	2	R42C56[1][A]	Mdu/u_mdu/reg0_neg_cry_43_0/CIN
5.665	0.035	tINS	FF	1	R42C56[1][A]	Mdu/u_mdu/reg0_neg_cry_43_0/COUT
5.665	0.000	tNET	FF	2	R42C56[1][B]	Mdu/u_mdu/reg0_neg_cry_44_0/CIN
5.701	0.035	tINS	FF	1	R42C56[1][B]	Mdu/u_mdu/reg0_neg_cry_44_0/COUT
5.701	0.000	tNET	FF	2	R42C56[2][A]	Mdu/u_mdu/reg0_neg_cry_45_0/CIN
5.736	0.035	tINS	FF	1	R42C56[2][A]	Mdu/u_mdu/reg0_neg_cry_45_0/COUT
5.736	0.000	tNET	FF	2	R42C56[2][B]	Mdu/u_mdu/reg0_neg_cry_46_0/CIN
5.771	0.035	tINS	FF	1	R42C56[2][B]	Mdu/u_mdu/reg0_neg_cry_46_0/COUT
5.771	0.000	tNET	FF	2	R42C57[0][A]	Mdu/u_mdu/reg0_neg_cry_47_0/CIN
5.806	0.035	tINS	FF	1	R42C57[0][A]	Mdu/u_mdu/reg0_neg_cry_47_0/COUT
5.806	0.000	tNET	FF	2	R42C57[0][B]	Mdu/u_mdu/reg0_neg_cry_48_0/CIN
5.841	0.035	tINS	FF	1	R42C57[0][B]	Mdu/u_mdu/reg0_neg_cry_48_0/COUT
5.841	0.000	tNET	FF	2	R42C57[1][A]	Mdu/u_mdu/reg0_neg_cry_49_0/CIN
5.877	0.035	tINS	FF	1	R42C57[1][A]	Mdu/u_mdu/reg0_neg_cry_49_0/COUT
5.877	0.000	tNET	FF	2	R42C57[1][B]	Mdu/u_mdu/reg0_neg_cry_50_0/CIN
5.912	0.035	tINS	FF	1	R42C57[1][B]	Mdu/u_mdu/reg0_neg_cry_50_0/COUT
5.912	0.000	tNET	FF	2	R42C57[2][A]	Mdu/u_mdu/reg0_neg_cry_51_0/CIN
5.947	0.035	tINS	FF	1	R42C57[2][A]	Mdu/u_mdu/reg0_neg_cry_51_0/COUT
5.947	0.000	tNET	FF	2	R42C57[2][B]	Mdu/u_mdu/reg0_neg_cry_52_0/CIN
6.417	0.470	tINS	FF	1	R42C57[2][B]	Mdu/u_mdu/reg0_neg_cry_52_0/SUM
7.372	0.955	tNET	FF	1	R35C47[3][A]	Mdu/u_mdu/reg0_post_swap_2[20]/I2
7.825	0.453	tINS	FF	1	R35C47[3][A]	Mdu/u_mdu/reg0_post_swap_2[20]/F
7.825	0.000	tNET	FF	1	R35C47[3][A]	Mdu/u_mdu/reg0_post_swap_4[20]/I0
7.928	0.103	tINS	FF	2	R35C47[3][A]	Mdu/u_mdu/reg0_post_swap_4[20]/O
8.338	0.411	tNET	FF	1	R34C47[0][B]	Mdu/u_mdu/reg0_post_swap_5[20]/I1
8.908	0.570	tINS	FR	1	R34C47[0][B]	Mdu/u_mdu/reg0_post_swap_5[20]/F
8.910	0.001	tNET	RR	1	R34C47[3][A]	Mdu/u_mdu/res0_cZ[20]/I1
9.465	0.555	tINS	RF	3	R34C47[3][A]	Mdu/u_mdu/res0_cZ[20]/F
10.307	0.843	tNET	FF	1	BSRAM_R36[15]	memq_memq_0_10/DI0

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	576	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	BSRAM_R36[15]	memq_memq_0_10/CLKA
11.683	-0.200	tUnc				memq_memq_0_10
11.648	-0.035	tSu		1	BSRAM_R36[15]	memq_memq_0_10

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 4.118, 48.882%; route: 4.074, 48.364%; tC2Q: 0.232, 2.754%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path23

Path Summary:

Slack	1.388
Data Arrival Time	10.261
Data Required Time	11.648
From	Mdu/u_mdu/reg0_fast_Z[4]
To	memq_memq_0_4
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.683	0.683	tINS	RR	576	IOT48[A]	clk_ibuf/O
1.883	1.201	tNET	RR	1	R48C45[1][B]	Mdu/u_mdu/reg0_fast_Z[4]/CLK
2.115	0.232	tC2Q	RF	7	R48C45[1][B]	Mdu/u_mdu/reg0_fast_Z[4]/Q
3.081	0.966	tNET	FF	1	R42C50[3][A]	Mdu/u_mdu/reg0_neg_axb_4_par_0_cp_0_cZ/I2
3.598	0.517	tINS	FF	1	R42C50[3][A]	Mdu/u_mdu/reg0_neg_axb_4_par_0_cp_0_cZ/F
4.497	0.899	tNET	FF	2	R42C53[1][B]	Mdu/u_mdu/reg0_neg_axb_4_par_cp_0_0/I0
5.067	0.570	tINS	FR	1	R42C53[1][B]	Mdu/u_mdu/reg0_neg_axb_4_par_cp_0_0/COUT
5.067	0.000	tNET	RR	2	R42C53[2][A]	Mdu/u_mdu/reg0_neg_axb_8_par_cp_1/CIN
5.102	0.035	tINS	RF	1	R42C53[2][A]	Mdu/u_mdu/reg0_neg_axb_8_par_cp_1/COUT
5.102	0.000	tNET	FF	2	R42C53[2][B]	Mdu/u_mdu/reg0_neg_axb_12_par_cp_1/CIN
5.137	0.035	tINS	FF	1	R42C53[2][B]	Mdu/u_mdu/reg0_neg_axb_12_par_cp_1/COUT
5.137	0.000	tNET	FF	2	R42C54[0][A]	Mdu/u_mdu/reg0_neg_axb_16_par_cp_1/CIN
5.173	0.035	tINS	FF	1	R42C54[0][A]	Mdu/u_mdu/reg0_neg_axb_16_par_cp_1/COUT
5.173	0.000	tNET	FF	2	R42C54[0][B]	Mdu/u_mdu/reg0_neg_axb_19_par_1/CIN
5.208	0.035	tINS	FF	1	R42C54[0][B]	Mdu/u_mdu/reg0_neg_axb_19_par_1/COUT
5.208	0.000	tNET	FF	2	R42C54[1][A]	Mdu/u_mdu/reg0_neg_axb_23_par_1/CIN
5.243	0.035	tINS	FF	1	R42C54[1][A]	Mdu/u_mdu/reg0_neg_axb_23_par_1/COUT
5.243	0.000	tNET	FF	2	R42C54[1][B]	Mdu/u_mdu/reg0_neg_axb_27_par_1/CIN
5.278	0.035	tINS	FF	1	R42C54[1][B]	Mdu/u_mdu/reg0_neg_axb_27_par_1/COUT
5.278	0.000	tNET	FF	2	R42C54[2][A]	Mdu/u_mdu/reg0_neg_axb_31_par_1/CIN
5.313	0.035	tINS	FF	1	R42C54[2][A]	Mdu/u_mdu/reg0_neg_axb_31_par_1/COUT
5.313	0.000	tNET	FF	2	R42C54[2][B]	Mdu/u_mdu/reg0_neg_cry_34_0/CIN
5.349	0.035	tINS	FF	1	R42C54[2][B]	Mdu/u_mdu/reg0_neg_cry_34_0/COUT
5.349	0.000	tNET	FF	2	R42C55[0][A]	Mdu/u_mdu/reg0_neg_cry_35_0/CIN
5.384	0.035	tINS	FF	1	R42C55[0][A]	Mdu/u_mdu/reg0_neg_cry_35_0/COUT
5.384	0.000	tNET	FF	2	R42C55[0][B]	Mdu/u_mdu/reg0_neg_cry_36_0/CIN
5.419	0.035	tINS	FF	1	R42C55[0][B]	Mdu/u_mdu/reg0_neg_cry_36_0/COUT
5.419	0.000	tNET	FF	2	R42C55[1][A]	Mdu/u_mdu/reg0_neg_cry_37_0/CIN
5.454	0.035	tINS	FF	1	R42C55[1][A]	Mdu/u_mdu/reg0_neg_cry_37_0/COUT
5.454	0.000	tNET	FF	2	R42C55[1][B]	Mdu/u_mdu/reg0_neg_cry_38_0/CIN
5.489	0.035	tINS	FF	1	R42C55[1][B]	Mdu/u_mdu/reg0_neg_cry_38_0/COUT
5.489	0.000	tNET	FF	2	R42C55[2][A]	Mdu/u_mdu/reg0_neg_cry_39_0/CIN
5.525	0.035	tINS	FF	1	R42C55[2][A]	Mdu/u_mdu/reg0_neg_cry_39_0/COUT
5.525	0.000	tNET	FF	2	R42C55[2][B]	Mdu/u_mdu/reg0_neg_cry_40_0/CIN
5.560	0.035	tINS	FF	1	R42C55[2][B]	Mdu/u_mdu/reg0_neg_cry_40_0/COUT
5.560	0.000	tNET	FF	2	R42C56[0][A]	Mdu/u_mdu/reg0_neg_cry_41_0/CIN
6.030	0.470	tINS	FF	1	R42C56[0][A]	Mdu/u_mdu/reg0_neg_cry_41_0/SUM
6.985	0.955	tNET	FF	1	R38C45[2][A]	Mdu/u_mdu/reg0_post_swap_2[9]/I2
7.356	0.371	tINS	FF	1	R38C45[2][A]	Mdu/u_mdu/reg0_post_swap_2[9]/F
7.356	0.000	tNET	FF	1	R38C45[2][A]	Mdu/u_mdu/reg0_post_swap_4[9]/I0
7.459	0.103	tINS	FF	1	R38C45[2][A]	Mdu/u_mdu/reg0_post_swap_4[9]/O
7.878	0.419	tNET	FF	1	R39C46[1][B]	Mdu/u_mdu/reg0_post_swap_5[9]/I1
8.340	0.462	tINS	FR	3	R39C46[1][B]	Mdu/u_mdu/reg0_post_swap_5[9]/F
8.513	0.174	tNET	RR	1	R40C46[2][B]	Mdu/u_mdu/res0_cZ[9]/I1
9.030	0.517	tINS	RF	3	R40C46[2][B]	Mdu/u_mdu/res0_cZ[9]/F
10.261	1.230	tNET	FF	1	BSRAM_R54[13]	memq_memq_0_4/DI1

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	576	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	BSRAM_R54[13]	memq_memq_0_4/CLKA
11.683	-0.200	tUnc				memq_memq_0_4
11.648	-0.035	tSu		1	BSRAM_R54[13]	memq_memq_0_4

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 3.503, 41.812%; route: 4.643, 55.419%; tC2Q: 0.232, 2.769%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path24

Path Summary:

Slack	1.399
Data Arrival Time	10.249
Data Required Time	11.648
From	Mdu/u_mdu/reg1_Z[1]
To	Mdu/u_mdu/reg0_Z[38]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.683	0.683	tINS	RR	576	IOT48[A]	clk_ibuf/O
1.883	1.201	tNET	RR	1	R34C60[0][B]	Mdu/u_mdu/reg1_Z[1]/CLK
2.115	0.232	tC2Q	RF	8	R34C60[0][B]	Mdu/u_mdu/reg1_Z[1]/Q
3.060	0.945	tNET	FF	1	R35C53[3][A]	Mdu/u_mdu/adder_sum_s_1_sf_lofx_cZ/I1
3.513	0.453	tINS	FF	1	R35C53[3][A]	Mdu/u_mdu/adder_sum_s_1_sf_lofx_cZ/F
4.411	0.899	tNET	FF	2	R38C50[1][B]	Mdu/u_mdu/adder_sum_cry_1_0/I0
4.981	0.570	tINS	FR	1	R38C50[1][B]	Mdu/u_mdu/adder_sum_cry_1_0/COUT
4.981	0.000	tNET	RR	2	R38C50[2][A]	Mdu/u_mdu/adder_sum_cry_2_0/CIN
5.017	0.035	tINS	RF	1	R38C50[2][A]	Mdu/u_mdu/adder_sum_cry_2_0/COUT
5.017	0.000	tNET	FF	2	R38C50[2][B]	Mdu/u_mdu/adder_sum_cry_3_0/CIN
5.052	0.035	tINS	FF	1	R38C50[2][B]	Mdu/u_mdu/adder_sum_cry_3_0/COUT
5.052	0.000	tNET	FF	2	R38C51[0][A]	Mdu/u_mdu/adder_sum_cry_4_0/CIN
5.087	0.035	tINS	FF	1	R38C51[0][A]	Mdu/u_mdu/adder_sum_cry_4_0/COUT
5.087	0.000	tNET	FF	2	R38C51[0][B]	Mdu/u_mdu/adder_sum_cry_5_0/CIN
5.122	0.035	tINS	FF	1	R38C51[0][B]	Mdu/u_mdu/adder_sum_cry_5_0/COUT
5.122	0.000	tNET	FF	2	R38C51[1][A]	Mdu/u_mdu/adder_sum_cry_6_0/CIN
5.157	0.035	tINS	FF	1	R38C51[1][A]	Mdu/u_mdu/adder_sum_cry_6_0/COUT
5.157	0.000	tNET	FF	2	R38C51[1][B]	Mdu/u_mdu/adder_sum_cry_7_0/CIN
5.193	0.035	tINS	FF	1	R38C51[1][B]	Mdu/u_mdu/adder_sum_cry_7_0/COUT
5.193	0.000	tNET	FF	2	R38C51[2][A]	Mdu/u_mdu/adder_sum_cry_8_0/CIN
5.228	0.035	tINS	FF	1	R38C51[2][A]	Mdu/u_mdu/adder_sum_cry_8_0/COUT
5.228	0.000	tNET	FF	2	R38C51[2][B]	Mdu/u_mdu/adder_sum_cry_9_0/CIN
5.263	0.035	tINS	FF	1	R38C51[2][B]	Mdu/u_mdu/adder_sum_cry_9_0/COUT
5.263	0.000	tNET	FF	2	R38C52[0][A]	Mdu/u_mdu/adder_sum_cry_10_0/CIN
5.298	0.035	tINS	FF	1	R38C52[0][A]	Mdu/u_mdu/adder_sum_cry_10_0/COUT
5.298	0.000	tNET	FF	2	R38C52[0][B]	Mdu/u_mdu/adder_sum_cry_11_0/CIN
5.333	0.035	tINS	FF	1	R38C52[0][B]	Mdu/u_mdu/adder_sum_cry_11_0/COUT
5.333	0.000	tNET	FF	2	R38C52[1][A]	Mdu/u_mdu/adder_sum_cry_12_0/CIN
5.369	0.035	tINS	FF	1	R38C52[1][A]	Mdu/u_mdu/adder_sum_cry_12_0/COUT
5.369	0.000	tNET	FF	2	R38C52[1][B]	Mdu/u_mdu/adder_sum_cry_13_0/CIN
5.404	0.035	tINS	FF	1	R38C52[1][B]	Mdu/u_mdu/adder_sum_cry_13_0/COUT
5.404	0.000	tNET	FF	2	R38C52[2][A]	Mdu/u_mdu/adder_sum_cry_14_0/CIN
5.439	0.035	tINS	FF	1	R38C52[2][A]	Mdu/u_mdu/adder_sum_cry_14_0/COUT
5.439	0.000	tNET	FF	2	R38C52[2][B]	Mdu/u_mdu/adder_sum_cry_15_0/CIN
5.474	0.035	tINS	FF	1	R38C52[2][B]	Mdu/u_mdu/adder_sum_cry_15_0/COUT
5.474	0.000	tNET	FF	2	R38C53[0][A]	Mdu/u_mdu/adder_sum_cry_16_0/CIN
5.509	0.035	tINS	FF	1	R38C53[0][A]	Mdu/u_mdu/adder_sum_cry_16_0/COUT
5.509	0.000	tNET	FF	2	R38C53[0][B]	Mdu/u_mdu/adder_sum_cry_17_0/CIN
5.545	0.035	tINS	FF	1	R38C53[0][B]	Mdu/u_mdu/adder_sum_cry_17_0/COUT
5.545	0.000	tNET	FF	2	R38C53[1][A]	Mdu/u_mdu/adder_sum_cry_18_0/CIN
5.580	0.035	tINS	FF	1	R38C53[1][A]	Mdu/u_mdu/adder_sum_cry_18_0/COUT
5.580	0.000	tNET	FF	2	R38C53[1][B]	Mdu/u_mdu/adder_sum_cry_19_0/CIN
5.615	0.035	tINS	FF	1	R38C53[1][B]	Mdu/u_mdu/adder_sum_cry_19_0/COUT
5.615	0.000	tNET	FF	2	R38C53[2][A]	Mdu/u_mdu/adder_sum_cry_20_0/CIN
5.650	0.035	tINS	FF	1	R38C53[2][A]	Mdu/u_mdu/adder_sum_cry_20_0/COUT
5.650	0.000	tNET	FF	2	R38C53[2][B]	Mdu/u_mdu/adder_sum_cry_21_0/CIN
5.685	0.035	tINS	FF	1	R38C53[2][B]	Mdu/u_mdu/adder_sum_cry_21_0/COUT
5.685	0.000	tNET	FF	2	R38C54[0][A]	Mdu/u_mdu/adder_sum_cry_22_0/CIN
5.721	0.035	tINS	FF	1	R38C54[0][A]	Mdu/u_mdu/adder_sum_cry_22_0/COUT
5.721	0.000	tNET	FF	2	R38C54[0][B]	Mdu/u_mdu/adder_sum_cry_23_0/CIN
5.756	0.035	tINS	FF	1	R38C54[0][B]	Mdu/u_mdu/adder_sum_cry_23_0/COUT
5.756	0.000	tNET	FF	2	R38C54[1][A]	Mdu/u_mdu/adder_sum_cry_24_0/CIN
5.791	0.035	tINS	FF	1	R38C54[1][A]	Mdu/u_mdu/adder_sum_cry_24_0/COUT
5.791	0.000	tNET	FF	2	R38C54[1][B]	Mdu/u_mdu/adder_sum_cry_25_0/CIN
5.826	0.035	tINS	FF	1	R38C54[1][B]	Mdu/u_mdu/adder_sum_cry_25_0/COUT
5.826	0.000	tNET	FF	2	R38C54[2][A]	Mdu/u_mdu/adder_sum_cry_26_0/CIN
5.861	0.035	tINS	FF	1	R38C54[2][A]	Mdu/u_mdu/adder_sum_cry_26_0/COUT
5.861	0.000	tNET	FF	2	R38C54[2][B]	Mdu/u_mdu/adder_sum_cry_27_0/CIN
5.897	0.035	tINS	FF	1	R38C54[2][B]	Mdu/u_mdu/adder_sum_cry_27_0/COUT
5.897	0.000	tNET	FF	2	R38C55[0][A]	Mdu/u_mdu/adder_sum_cry_28_0/CIN
5.932	0.035	tINS	FF	1	R38C55[0][A]	Mdu/u_mdu/adder_sum_cry_28_0/COUT
5.932	0.000	tNET	FF	2	R38C55[0][B]	Mdu/u_mdu/adder_sum_cry_29_0/CIN
5.967	0.035	tINS	FF	1	R38C55[0][B]	Mdu/u_mdu/adder_sum_cry_29_0/COUT
5.967	0.000	tNET	FF	2	R38C55[1][A]	Mdu/u_mdu/adder_sum_cry_30_0/CIN
6.002	0.035	tINS	FF	1	R38C55[1][A]	Mdu/u_mdu/adder_sum_cry_30_0/COUT
6.002	0.000	tNET	FF	2	R38C55[1][B]	Mdu/u_mdu/adder_sum_cry_31_0/CIN
6.037	0.035	tINS	FF	1	R38C55[1][B]	Mdu/u_mdu/adder_sum_cry_31_0/COUT
6.037	0.000	tNET	FF	2	R38C55[2][A]	Mdu/u_mdu/adder_sum_s_32_0/CIN
6.507	0.470	tINS	FF	6	R38C55[2][A]	Mdu/u_mdu/adder_sum_s_32_0/SUM
7.185	0.678	tNET	FF	1	R37C52[3][B]	Mdu/u_mdu/reg0_exe_nx_ss0_cZ/I0
7.734	0.549	tINS	FR	50	R37C52[3][B]	Mdu/u_mdu/reg0_exe_nx_ss0_cZ/F
8.186	0.452	tNET	RR	1	R43C53[3][A]	Mdu/u_mdu/reg0_exe_nx_m0_cZ[38]/I2
8.703	0.517	tINS	RF	1	R43C53[3][A]	Mdu/u_mdu/reg0_exe_nx_m0_cZ[38]/F
8.703	0.000	tNET	FF	1	R43C53[3][A]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[38]/I0
8.806	0.103	tINS	FF	1	R43C53[3][A]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[38]/O
9.787	0.981	tNET	FF	1	R43C53[0][A]	Mdu/u_mdu/reg0_nx_0[38]/I2
10.249	0.462	tINS	FR	1	R43C53[0][A]	Mdu/u_mdu/reg0_nx_0[38]/F
10.249	0.000	tNET	RR	1	R43C53[0][A]	Mdu/u_mdu/reg0_Z[38]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	576	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R43C53[0][A]	Mdu/u_mdu/reg0_Z[38]/CLK
11.683	-0.200	tUnc				Mdu/u_mdu/reg0_Z[38]
11.648	-0.035	tSu		1	R43C53[0][A]	Mdu/u_mdu/reg0_Z[38]

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 4.180, 49.964%; route: 3.954, 47.263%; tC2Q: 0.232, 2.773%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path25

Path Summary:

Slack	1.400
Data Arrival Time	10.248
Data Required Time	11.648
From	Mdu/u_mdu/reg1_Z[1]
To	Mdu/u_mdu/reg0_Z[35]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.683	0.683	tINS	RR	576	IOT48[A]	clk_ibuf/O
1.883	1.201	tNET	RR	1	R34C60[0][B]	Mdu/u_mdu/reg1_Z[1]/CLK
2.115	0.232	tC2Q	RF	8	R34C60[0][B]	Mdu/u_mdu/reg1_Z[1]/Q
3.060	0.945	tNET	FF	1	R35C53[3][A]	Mdu/u_mdu/adder_sum_s_1_sf_lofx_cZ/I1
3.513	0.453	tINS	FF	1	R35C53[3][A]	Mdu/u_mdu/adder_sum_s_1_sf_lofx_cZ/F
4.411	0.899	tNET	FF	2	R38C50[1][B]	Mdu/u_mdu/adder_sum_cry_1_0/I0
4.981	0.570	tINS	FR	1	R38C50[1][B]	Mdu/u_mdu/adder_sum_cry_1_0/COUT
4.981	0.000	tNET	RR	2	R38C50[2][A]	Mdu/u_mdu/adder_sum_cry_2_0/CIN
5.017	0.035	tINS	RF	1	R38C50[2][A]	Mdu/u_mdu/adder_sum_cry_2_0/COUT
5.017	0.000	tNET	FF	2	R38C50[2][B]	Mdu/u_mdu/adder_sum_cry_3_0/CIN
5.052	0.035	tINS	FF	1	R38C50[2][B]	Mdu/u_mdu/adder_sum_cry_3_0/COUT
5.052	0.000	tNET	FF	2	R38C51[0][A]	Mdu/u_mdu/adder_sum_cry_4_0/CIN
5.087	0.035	tINS	FF	1	R38C51[0][A]	Mdu/u_mdu/adder_sum_cry_4_0/COUT
5.087	0.000	tNET	FF	2	R38C51[0][B]	Mdu/u_mdu/adder_sum_cry_5_0/CIN
5.122	0.035	tINS	FF	1	R38C51[0][B]	Mdu/u_mdu/adder_sum_cry_5_0/COUT
5.122	0.000	tNET	FF	2	R38C51[1][A]	Mdu/u_mdu/adder_sum_cry_6_0/CIN
5.157	0.035	tINS	FF	1	R38C51[1][A]	Mdu/u_mdu/adder_sum_cry_6_0/COUT
5.157	0.000	tNET	FF	2	R38C51[1][B]	Mdu/u_mdu/adder_sum_cry_7_0/CIN
5.193	0.035	tINS	FF	1	R38C51[1][B]	Mdu/u_mdu/adder_sum_cry_7_0/COUT
5.193	0.000	tNET	FF	2	R38C51[2][A]	Mdu/u_mdu/adder_sum_cry_8_0/CIN
5.228	0.035	tINS	FF	1	R38C51[2][A]	Mdu/u_mdu/adder_sum_cry_8_0/COUT
5.228	0.000	tNET	FF	2	R38C51[2][B]	Mdu/u_mdu/adder_sum_cry_9_0/CIN
5.263	0.035	tINS	FF	1	R38C51[2][B]	Mdu/u_mdu/adder_sum_cry_9_0/COUT
5.263	0.000	tNET	FF	2	R38C52[0][A]	Mdu/u_mdu/adder_sum_cry_10_0/CIN
5.298	0.035	tINS	FF	1	R38C52[0][A]	Mdu/u_mdu/adder_sum_cry_10_0/COUT
5.298	0.000	tNET	FF	2	R38C52[0][B]	Mdu/u_mdu/adder_sum_cry_11_0/CIN
5.333	0.035	tINS	FF	1	R38C52[0][B]	Mdu/u_mdu/adder_sum_cry_11_0/COUT
5.333	0.000	tNET	FF	2	R38C52[1][A]	Mdu/u_mdu/adder_sum_cry_12_0/CIN
5.369	0.035	tINS	FF	1	R38C52[1][A]	Mdu/u_mdu/adder_sum_cry_12_0/COUT
5.369	0.000	tNET	FF	2	R38C52[1][B]	Mdu/u_mdu/adder_sum_cry_13_0/CIN
5.404	0.035	tINS	FF	1	R38C52[1][B]	Mdu/u_mdu/adder_sum_cry_13_0/COUT
5.404	0.000	tNET	FF	2	R38C52[2][A]	Mdu/u_mdu/adder_sum_cry_14_0/CIN
5.439	0.035	tINS	FF	1	R38C52[2][A]	Mdu/u_mdu/adder_sum_cry_14_0/COUT
5.439	0.000	tNET	FF	2	R38C52[2][B]	Mdu/u_mdu/adder_sum_cry_15_0/CIN
5.474	0.035	tINS	FF	1	R38C52[2][B]	Mdu/u_mdu/adder_sum_cry_15_0/COUT
5.474	0.000	tNET	FF	2	R38C53[0][A]	Mdu/u_mdu/adder_sum_cry_16_0/CIN
5.509	0.035	tINS	FF	1	R38C53[0][A]	Mdu/u_mdu/adder_sum_cry_16_0/COUT
5.509	0.000	tNET	FF	2	R38C53[0][B]	Mdu/u_mdu/adder_sum_cry_17_0/CIN
5.545	0.035	tINS	FF	1	R38C53[0][B]	Mdu/u_mdu/adder_sum_cry_17_0/COUT
5.545	0.000	tNET	FF	2	R38C53[1][A]	Mdu/u_mdu/adder_sum_cry_18_0/CIN
5.580	0.035	tINS	FF	1	R38C53[1][A]	Mdu/u_mdu/adder_sum_cry_18_0/COUT
5.580	0.000	tNET	FF	2	R38C53[1][B]	Mdu/u_mdu/adder_sum_cry_19_0/CIN
5.615	0.035	tINS	FF	1	R38C53[1][B]	Mdu/u_mdu/adder_sum_cry_19_0/COUT
5.615	0.000	tNET	FF	2	R38C53[2][A]	Mdu/u_mdu/adder_sum_cry_20_0/CIN
5.650	0.035	tINS	FF	1	R38C53[2][A]	Mdu/u_mdu/adder_sum_cry_20_0/COUT
5.650	0.000	tNET	FF	2	R38C53[2][B]	Mdu/u_mdu/adder_sum_cry_21_0/CIN
5.685	0.035	tINS	FF	1	R38C53[2][B]	Mdu/u_mdu/adder_sum_cry_21_0/COUT
5.685	0.000	tNET	FF	2	R38C54[0][A]	Mdu/u_mdu/adder_sum_cry_22_0/CIN
5.721	0.035	tINS	FF	1	R38C54[0][A]	Mdu/u_mdu/adder_sum_cry_22_0/COUT
5.721	0.000	tNET	FF	2	R38C54[0][B]	Mdu/u_mdu/adder_sum_cry_23_0/CIN
5.756	0.035	tINS	FF	1	R38C54[0][B]	Mdu/u_mdu/adder_sum_cry_23_0/COUT
5.756	0.000	tNET	FF	2	R38C54[1][A]	Mdu/u_mdu/adder_sum_cry_24_0/CIN
5.791	0.035	tINS	FF	1	R38C54[1][A]	Mdu/u_mdu/adder_sum_cry_24_0/COUT
5.791	0.000	tNET	FF	2	R38C54[1][B]	Mdu/u_mdu/adder_sum_cry_25_0/CIN
5.826	0.035	tINS	FF	1	R38C54[1][B]	Mdu/u_mdu/adder_sum_cry_25_0/COUT
5.826	0.000	tNET	FF	2	R38C54[2][A]	Mdu/u_mdu/adder_sum_cry_26_0/CIN
5.861	0.035	tINS	FF	1	R38C54[2][A]	Mdu/u_mdu/adder_sum_cry_26_0/COUT
5.861	0.000	tNET	FF	2	R38C54[2][B]	Mdu/u_mdu/adder_sum_cry_27_0/CIN
5.897	0.035	tINS	FF	1	R38C54[2][B]	Mdu/u_mdu/adder_sum_cry_27_0/COUT
5.897	0.000	tNET	FF	2	R38C55[0][A]	Mdu/u_mdu/adder_sum_cry_28_0/CIN
5.932	0.035	tINS	FF	1	R38C55[0][A]	Mdu/u_mdu/adder_sum_cry_28_0/COUT
5.932	0.000	tNET	FF	2	R38C55[0][B]	Mdu/u_mdu/adder_sum_cry_29_0/CIN
5.967	0.035	tINS	FF	1	R38C55[0][B]	Mdu/u_mdu/adder_sum_cry_29_0/COUT
5.967	0.000	tNET	FF	2	R38C55[1][A]	Mdu/u_mdu/adder_sum_cry_30_0/CIN
6.002	0.035	tINS	FF	1	R38C55[1][A]	Mdu/u_mdu/adder_sum_cry_30_0/COUT
6.002	0.000	tNET	FF	2	R38C55[1][B]	Mdu/u_mdu/adder_sum_cry_31_0/CIN
6.037	0.035	tINS	FF	1	R38C55[1][B]	Mdu/u_mdu/adder_sum_cry_31_0/COUT
6.037	0.000	tNET	FF	2	R38C55[2][A]	Mdu/u_mdu/adder_sum_s_32_0/CIN
6.507	0.470	tINS	FF	6	R38C55[2][A]	Mdu/u_mdu/adder_sum_s_32_0/SUM
7.185	0.678	tNET	FF	1	R37C52[3][B]	Mdu/u_mdu/reg0_exe_nx_ss0_cZ/I0
7.734	0.549	tINS	FR	50	R37C52[3][B]	Mdu/u_mdu/reg0_exe_nx_ss0_cZ/F
8.174	0.440	tNET	RR	1	R43C51[3][A]	Mdu/u_mdu/reg0_exe_nx_m0_cZ[35]/I2
8.691	0.517	tINS	RF	1	R43C51[3][A]	Mdu/u_mdu/reg0_exe_nx_m0_cZ[35]/F
8.691	0.000	tNET	FF	1	R43C51[3][A]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[35]/I0
8.794	0.103	tINS	FF	1	R43C51[3][A]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[35]/O
9.699	0.904	tNET	FF	1	R43C51[1][A]	Mdu/u_mdu/reg0_nx_cZ[35]/I0
10.248	0.549	tINS	FR	1	R43C51[1][A]	Mdu/u_mdu/reg0_nx_cZ[35]/F
10.248	0.000	tNET	RR	1	R43C51[1][A]	Mdu/u_mdu/reg0_Z[35]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	576	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R43C51[1][A]	Mdu/u_mdu/reg0_Z[35]/CLK
11.683	-0.200	tUnc				Mdu/u_mdu/reg0_Z[35]
11.648	-0.035	tSu		1	R43C51[1][A]	Mdu/u_mdu/reg0_Z[35]

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 4.267, 51.013%; route: 3.866, 46.214%; tC2Q: 0.232, 2.774%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Hold Analysis Report

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	0.213
Data Arrival Time	2.040
Data Required Time	1.826
From	u_la0_top/u_ao_mem_ctrl/data_reg_Z[97]
To	u_la0_top/u_ao_mem_ctrl/mem_mem_0_48
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	576	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R12C13[0][A]	u_la0_top/u_ao_mem_ctrl/data_reg_Z[97]/CLK
1.779	0.202	tC2Q	RR	1	R12C13[0][A]	u_la0_top/u_ao_mem_ctrl/data_reg_Z[97]/Q
2.040	0.260	tNET	RR	1	BSRAM_R10[3]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_48/DI1

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	576	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	BSRAM_R10[3]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_48/CLKA
1.577	0.000	tUnc				u_la0_top/u_ao_mem_ctrl/mem_mem_0_48
1.826	0.249	tHld		1	BSRAM_R10[3]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_48

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.260, 56.314%; tC2Q: 0.202, 43.686%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path2

Path Summary:

Slack	0.213
Data Arrival Time	2.040
Data Required Time	1.826
From	u_la0_top/u_ao_mem_ctrl/data_reg_Z[87]
To	u_la0_top/u_ao_mem_ctrl/mem_mem_0_43
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	576	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R11C10[1][B]	u_la0_top/u_ao_mem_ctrl/data_reg_Z[87]/CLK
1.779	0.202	tC2Q	RR	1	R11C10[1][B]	u_la0_top/u_ao_mem_ctrl/data_reg_Z[87]/Q
2.040	0.260	tNET	RR	1	BSRAM_R10[2]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_43/DI1

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	576	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	BSRAM_R10[2]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_43/CLKA
1.577	0.000	tUnc				u_la0_top/u_ao_mem_ctrl/mem_mem_0_43
1.826	0.249	tHld		1	BSRAM_R10[2]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_43

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.260, 56.314%; tC2Q: 0.202, 43.686%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path3

Path Summary:

Slack	0.213
Data Arrival Time	2.040
Data Required Time	1.826
From	u_la0_top/u_ao_mem_ctrl/data_reg_Z[86]
To	u_la0_top/u_ao_mem_ctrl/mem_mem_0_43
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	576	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R12C10[2][A]	u_la0_top/u_ao_mem_ctrl/data_reg_Z[86]/CLK
1.779	0.202	tC2Q	RR	1	R12C10[2][A]	u_la0_top/u_ao_mem_ctrl/data_reg_Z[86]/Q
2.040	0.260	tNET	RR	1	BSRAM_R10[2]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_43/DI0

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	576	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	BSRAM_R10[2]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_43/CLKA
1.577	0.000	tUnc				u_la0_top/u_ao_mem_ctrl/mem_mem_0_43
1.826	0.249	tHld		1	BSRAM_R10[2]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_43

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.260, 56.314%; tC2Q: 0.202, 43.686%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path4

Path Summary:

Slack	0.230
Data Arrival Time	1.926
Data Required Time	1.695
From	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[9]
To	u_la0_top/u_ao_mem_ctrl/mem_mem_0_11
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	576	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R11C8[2][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[9]/CLK
1.778	0.201	tC2Q	RF	67	R11C8[2][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[9]/Q
1.926	0.147	tNET	FF	1	BSRAM_R10[1]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_11/ADA10

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	576	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	BSRAM_R10[1]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_11/CLKA
1.577	0.000	tUnc				u_la0_top/u_ao_mem_ctrl/mem_mem_0_11
1.695	0.118	tHld		1	BSRAM_R10[1]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_11

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.147, 42.272%; tC2Q: 0.201, 57.728%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path5

Path Summary:

Slack	0.232
Data Arrival Time	1.927
Data Required Time	1.695
From	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8]
To	u_la0_top/u_ao_mem_ctrl/mem_mem_0_11
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	576	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R11C8[2][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8]/CLK
1.779	0.202	tC2Q	RR	67	R11C8[2][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8]/Q
1.927	0.148	tNET	RR	1	BSRAM_R10[1]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_11/ADA9

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	576	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	BSRAM_R10[1]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_11/CLKA
1.577	0.000	tUnc				u_la0_top/u_ao_mem_ctrl/mem_mem_0_11
1.695	0.118	tHld		1	BSRAM_R10[1]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_11

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.148, 42.267%; tC2Q: 0.202, 57.733%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path6

Path Summary:

Slack	0.235
Data Arrival Time	1.930
Data Required Time	1.695
From	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[11]
To	u_la0_top/u_ao_mem_ctrl/mem_mem_0_11
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	576	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R11C9[1][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[11]/CLK
1.779	0.202	tC2Q	RR	67	R11C9[1][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[11]/Q
1.930	0.151	tNET	RR	1	BSRAM_R10[1]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_11/ADA12

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	576	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	BSRAM_R10[1]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_11/CLKA
1.577	0.000	tUnc				u_la0_top/u_ao_mem_ctrl/mem_mem_0_11
1.695	0.118	tHld		1	BSRAM_R10[1]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_11

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.151, 42.704%; tC2Q: 0.202, 57.296%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path7

Path Summary:

Slack	0.324
Data Arrival Time	1.912
Data Required Time	1.588
From	Mdu/u_mdu/reg1_Z[29]
To	Mdu/u_mdu/rs1_mul_Z[29]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	576	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R39C57[1][A]	Mdu/u_mdu/reg1_Z[29]/CLK
1.778	0.201	tC2Q	RF	8	R39C57[1][A]	Mdu/u_mdu/reg1_Z[29]/Q
1.912	0.134	tNET	FF	1	R39C57[2][B]	Mdu/u_mdu/rs1_mul_Z[29]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	576	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R39C57[2][B]	Mdu/u_mdu/rs1_mul_Z[29]/CLK
1.577	0.000	tUnc				Mdu/u_mdu/rs1_mul_Z[29]
1.588	0.011	tHld		1	R39C57[2][B]	Mdu/u_mdu/rs1_mul_Z[29]

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.134, 39.911%; tC2Q: 0.201, 60.089%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path8

Path Summary:

Slack	0.335
Data Arrival Time	2.031
Data Required Time	1.695
From	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[10]
To	u_la0_top/u_ao_mem_ctrl/mem_mem_0_11
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	576	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R11C9[1][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[10]/CLK
1.779	0.202	tC2Q	RR	67	R11C9[1][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[10]/Q
2.031	0.251	tNET	RR	1	BSRAM_R10[1]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_11/ADA11

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	576	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	BSRAM_R10[1]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_11/CLKA
1.577	0.000	tUnc				u_la0_top/u_ao_mem_ctrl/mem_mem_0_11
1.695	0.118	tHld		1	BSRAM_R10[1]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_11

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.251, 55.441%; tC2Q: 0.202, 44.559%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path9

Path Summary:

Slack	0.335
Data Arrival Time	2.162
Data Required Time	1.826
From	u_la0_top/u_ao_mem_ctrl/data_reg_Z[106]
To	u_la0_top/u_ao_mem_ctrl/mem_mem_0_53
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	576	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R12C14[0][A]	u_la0_top/u_ao_mem_ctrl/data_reg_Z[106]/CLK
1.779	0.202	tC2Q	RR	1	R12C14[0][A]	u_la0_top/u_ao_mem_ctrl/data_reg_Z[106]/Q
2.162	0.382	tNET	RR	1	BSRAM_R10[4]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_53/DI0

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	576	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	BSRAM_R10[4]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_53/CLKA
1.577	0.000	tUnc				u_la0_top/u_ao_mem_ctrl/mem_mem_0_53
1.826	0.249	tHld		1	BSRAM_R10[4]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_53

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.382, 65.434%; tC2Q: 0.202, 34.566%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path10

Path Summary:

Slack	0.335
Data Arrival Time	2.162
Data Required Time	1.826
From	u_la0_top/u_ao_mem_ctrl/data_reg_Z[96]
To	u_la0_top/u_ao_mem_ctrl/mem_mem_0_48
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	576	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R11C11[2][B]	u_la0_top/u_ao_mem_ctrl/data_reg_Z[96]/CLK
1.779	0.202	tC2Q	RR	1	R11C11[2][B]	u_la0_top/u_ao_mem_ctrl/data_reg_Z[96]/Q
2.162	0.382	tNET	RR	1	BSRAM_R10[3]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_48/DI0

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	576	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	BSRAM_R10[3]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_48/CLKA
1.577	0.000	tUnc				u_la0_top/u_ao_mem_ctrl/mem_mem_0_48
1.826	0.249	tHld		1	BSRAM_R10[3]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_48

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.382, 65.434%; tC2Q: 0.202, 34.566%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path11

Path Summary:

Slack	0.337
Data Arrival Time	2.033
Data Required Time	1.695
From	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0]
To	u_la0_top/u_ao_mem_ctrl/mem_mem_0_43
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	576	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R9C10[1][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0]/CLK
1.779	0.202	tC2Q	RR	67	R9C10[1][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0]/Q
2.033	0.253	tNET	RR	1	BSRAM_R10[2]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_43/ADA1

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	576	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	BSRAM_R10[2]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_43/CLKA
1.577	0.000	tUnc				u_la0_top/u_ao_mem_ctrl/mem_mem_0_43
1.695	0.118	tHld		1	BSRAM_R10[2]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_43

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.253, 55.615%; tC2Q: 0.202, 44.385%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path12

Path Summary:

Slack	0.353
Data Arrival Time	2.048
Data Required Time	1.695
From	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[6]
To	u_la0_top/u_ao_mem_ctrl/mem_mem_0_11
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	576	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R12C9[1][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[6]/CLK
1.779	0.202	tC2Q	RR	67	R12C9[1][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[6]/Q
2.048	0.269	tNET	RR	1	BSRAM_R10[1]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_11/ADA7

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	576	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	BSRAM_R10[1]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_11/CLKA
1.577	0.000	tUnc				u_la0_top/u_ao_mem_ctrl/mem_mem_0_11
1.695	0.118	tHld		1	BSRAM_R10[1]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_11

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.269, 57.097%; tC2Q: 0.202, 42.903%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path13

Path Summary:

Slack	0.353
Data Arrival Time	2.049
Data Required Time	1.695
From	cnt_1_Z[5]
To	memq_memq_0_2
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	576	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R42C41[2][A]	cnt_1_Z[5]/CLK
1.779	0.202	tC2Q	RR	33	R42C41[2][A]	cnt_1_Z[5]/Q
2.049	0.269	tNET	RR	1	BSRAM_R45[13]	memq_memq_0_2/ADB6

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	576	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	BSRAM_R45[13]	memq_memq_0_2/CLKB
1.577	0.000	tUnc				memq_memq_0_2
1.695	0.118	tHld		1	BSRAM_R45[13]	memq_memq_0_2

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.269, 57.143%; tC2Q: 0.202, 42.857%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path14

Path Summary:

Slack	0.354
Data Arrival Time	2.049
Data Required Time	1.695
From	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[2]
To	u_la0_top/u_ao_mem_ctrl/mem_mem_0_43
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	576	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R9C10[2][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[2]/CLK
1.779	0.202	tC2Q	RR	67	R9C10[2][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[2]/Q
2.049	0.270	tNET	RR	1	BSRAM_R10[2]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_43/ADA3

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	576	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	BSRAM_R10[2]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_43/CLKA
1.577	0.000	tUnc				u_la0_top/u_ao_mem_ctrl/mem_mem_0_43
1.695	0.118	tHld		1	BSRAM_R10[2]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_43

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.270, 57.208%; tC2Q: 0.202, 42.792%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path15

Path Summary:

Slack	0.354
Data Arrival Time	2.049
Data Required Time	1.695
From	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[2]
To	u_la0_top/u_ao_mem_ctrl/mem_mem_0_11
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	576	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R9C10[2][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[2]/CLK
1.779	0.202	tC2Q	RR	67	R9C10[2][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[2]/Q
2.049	0.270	tNET	RR	1	BSRAM_R10[1]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_11/ADA3

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	576	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	BSRAM_R10[1]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_11/CLKA
1.577	0.000	tUnc				u_la0_top/u_ao_mem_ctrl/mem_mem_0_11
1.695	0.118	tHld		1	BSRAM_R10[1]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_11

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.270, 57.208%; tC2Q: 0.202, 42.792%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path16

Path Summary:

Slack	0.354
Data Arrival Time	2.050
Data Required Time	1.695
From	cnt_1_Z[12]
To	memq_memq_0_2
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	576	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R42C42[2][B]	cnt_1_Z[12]/CLK
1.779	0.202	tC2Q	RR	33	R42C42[2][B]	cnt_1_Z[12]/Q
2.050	0.270	tNET	RR	1	BSRAM_R45[13]	memq_memq_0_2/ADB13

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	576	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	BSRAM_R45[13]	memq_memq_0_2/CLKB
1.577	0.000	tUnc				memq_memq_0_2
1.695	0.118	tHld		1	BSRAM_R45[13]	memq_memq_0_2

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.270, 57.213%; tC2Q: 0.202, 42.787%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path17

Path Summary:

Slack	0.355
Data Arrival Time	2.051
Data Required Time	1.695
From	cnt_1_Z[6]
To	memq_memq_0_2
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	576	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R42C41[2][B]	cnt_1_Z[6]/CLK
1.779	0.202	tC2Q	RR	33	R42C41[2][B]	cnt_1_Z[6]/Q
2.051	0.271	tNET	RR	1	BSRAM_R45[13]	memq_memq_0_2/ADB7

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	576	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	BSRAM_R45[13]	memq_memq_0_2/CLKB
1.577	0.000	tUnc				memq_memq_0_2
1.695	0.118	tHld		1	BSRAM_R45[13]	memq_memq_0_2

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.271, 57.304%; tC2Q: 0.202, 42.696%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path18

Path Summary:

Slack	0.357
Data Arrival Time	2.052
Data Required Time	1.695
From	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[3]
To	u_la0_top/u_ao_mem_ctrl/mem_mem_0_43
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	576	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R9C10[2][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[3]/CLK
1.779	0.202	tC2Q	RR	67	R9C10[2][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[3]/Q
2.052	0.273	tNET	RR	1	BSRAM_R10[2]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_43/ADA4

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	576	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	BSRAM_R10[2]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_43/CLKA
1.577	0.000	tUnc				u_la0_top/u_ao_mem_ctrl/mem_mem_0_43
1.695	0.118	tHld		1	BSRAM_R10[2]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_43

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.273, 57.434%; tC2Q: 0.202, 42.566%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path19

Path Summary:

Slack	0.357
Data Arrival Time	2.052
Data Required Time	1.695
From	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[3]
To	u_la0_top/u_ao_mem_ctrl/mem_mem_0_11
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	576	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R9C10[2][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[3]/CLK
1.779	0.202	tC2Q	RR	67	R9C10[2][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[3]/Q
2.052	0.273	tNET	RR	1	BSRAM_R10[1]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_11/ADA4

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	576	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	BSRAM_R10[1]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_11/CLKA
1.577	0.000	tUnc				u_la0_top/u_ao_mem_ctrl/mem_mem_0_11
1.695	0.118	tHld		1	BSRAM_R10[1]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_11

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.273, 57.434%; tC2Q: 0.202, 42.566%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path20

Path Summary:

Slack	0.358
Data Arrival Time	2.053
Data Required Time	1.695
From	cnt_1_Z[0]
To	memr_memr_0_15
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	576	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R42C40[2][B]	cnt_1_Z[0]/CLK
1.779	0.202	tC2Q	RR	33	R42C40[2][B]	cnt_1_Z[0]/Q
2.053	0.274	tNET	RR	1	BSRAM_R45[12]	memr_memr_0_15/ADB1

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	576	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	BSRAM_R45[12]	memr_memr_0_15/CLKB
1.577	0.000	tUnc				memr_memr_0_15
1.695	0.118	tHld		1	BSRAM_R45[12]	memr_memr_0_15

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.274, 57.528%; tC2Q: 0.202, 42.472%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path21

Path Summary:

Slack	0.361
Data Arrival Time	2.057
Data Required Time	1.695
From	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0]
To	u_la0_top/u_ao_mem_ctrl/mem_mem_0_6
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	576	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R9C10[1][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0]/CLK
1.779	0.202	tC2Q	RR	67	R9C10[1][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0]/Q
2.057	0.277	tNET	RR	1	BSRAM_R10[0]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_6/ADA1

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	576	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	BSRAM_R10[0]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_6/CLKA
1.577	0.000	tUnc				u_la0_top/u_ao_mem_ctrl/mem_mem_0_6
1.695	0.118	tHld		1	BSRAM_R10[0]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_6

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.277, 57.861%; tC2Q: 0.202, 42.139%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path22

Path Summary:

Slack	0.363
Data Arrival Time	2.058
Data Required Time	1.695
From	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[10]
To	u_la0_top/u_ao_mem_ctrl/mem_mem_0_6
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	576	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R11C9[1][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[10]/CLK
1.779	0.202	tC2Q	RR	67	R11C9[1][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[10]/Q
2.058	0.279	tNET	RR	1	BSRAM_R10[0]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_6/ADA11

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	576	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	BSRAM_R10[0]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_6/CLKA
1.577	0.000	tUnc				u_la0_top/u_ao_mem_ctrl/mem_mem_0_6
1.695	0.118	tHld		1	BSRAM_R10[0]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_6

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.279, 57.968%; tC2Q: 0.202, 42.032%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path23

Path Summary:

Slack	0.364
Data Arrival Time	2.059
Data Required Time	1.695
From	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[1]
To	u_la0_top/u_ao_mem_ctrl/mem_mem_0_6
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	576	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R9C10[1][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[1]/CLK
1.779	0.202	tC2Q	RR	67	R9C10[1][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[1]/Q
2.059	0.280	tNET	RR	1	BSRAM_R10[0]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_6/ADA2

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	576	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	BSRAM_R10[0]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_6/CLKA
1.577	0.000	tUnc				u_la0_top/u_ao_mem_ctrl/mem_mem_0_6
1.695	0.118	tHld		1	BSRAM_R10[0]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_6

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.280, 58.075%; tC2Q: 0.202, 41.925%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path24

Path Summary:

Slack	0.367
Data Arrival Time	2.063
Data Required Time	1.695
From	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[3]
To	u_la0_top/u_ao_mem_ctrl/mem_mem_0_6
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	576	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R9C10[2][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[3]/CLK
1.779	0.202	tC2Q	RR	67	R9C10[2][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[3]/Q
2.063	0.283	tNET	RR	1	BSRAM_R10[0]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_6/ADA4

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	576	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	BSRAM_R10[0]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_6/CLKA
1.577	0.000	tUnc				u_la0_top/u_ao_mem_ctrl/mem_mem_0_6
1.695	0.118	tHld		1	BSRAM_R10[0]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_6

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.283, 58.391%; tC2Q: 0.202, 41.609%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path25

Path Summary:

Slack	0.373
Data Arrival Time	2.068
Data Required Time	1.695
From	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[1]
To	u_la0_top/u_ao_mem_ctrl/mem_mem_0_53
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	576	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R9C10[1][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[1]/CLK
1.779	0.202	tC2Q	RR	67	R9C10[1][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[1]/Q
2.068	0.289	tNET	RR	1	BSRAM_R10[4]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_53/ADA2

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	576	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	BSRAM_R10[4]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_53/CLKA
1.577	0.000	tUnc				u_la0_top/u_ao_mem_ctrl/mem_mem_0_53
1.695	0.118	tHld		1	BSRAM_R10[4]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_53

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.289, 58.845%; tC2Q: 0.202, 41.155%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Recovery Analysis Report

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	1.914
Data Arrival Time	9.734
Data Required Time	11.648
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.688	0.688	tINS	FF	576	IOT48[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R9C10[0][B]	u_la0_top/rst_ao_Z/CLK
7.148	0.232	tC2Q	FF	49	R9C10[0][B]	u_la0_top/rst_ao_Z/Q
9.734	2.586	tNET	FF	1	R5C12[2][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	576	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R5C12[2][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z/CLK
11.683	-0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z
11.648	-0.035	tSu		1	R5C12[2][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z

Path Statistics:

Clock Skew	-0.033
Setup Relationship	5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.586, 91.769%; tC2Q: 0.232, 8.231%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path2

Path Summary:

Slack	1.914
Data Arrival Time	9.734
Data Required Time	11.648
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_Z
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.688	0.688	tINS	FF	576	IOT48[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R9C10[0][B]	u_la0_top/rst_ao_Z/CLK
7.148	0.232	tC2Q	FF	49	R9C10[0][B]	u_la0_top/rst_ao_Z/Q
9.734	2.586	tNET	FF	1	R3C4[0][A]	u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_Z/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	576	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R3C4[0][A]	u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_Z/CLK
11.683	-0.200	tUnc				u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_Z
11.648	-0.035	tSu		1	R3C4[0][A]	u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_Z

Path Statistics:

Clock Skew	-0.033
Setup Relationship	5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.586, 91.769%; tC2Q: 0.232, 8.231%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path3

Path Summary:

Slack	1.914
Data Arrival Time	9.734
Data Required Time	11.648
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_loop_Z
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.688	0.688	tINS	FF	576	IOT48[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R9C10[0][B]	u_la0_top/rst_ao_Z/CLK
7.148	0.232	tC2Q	FF	49	R9C10[0][B]	u_la0_top/rst_ao_Z/Q
9.734	2.586	tNET	FF	1	R11C8[0][A]	u_la0_top/u_ao_mem_ctrl/capture_loop_Z/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	576	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R11C8[0][A]	u_la0_top/u_ao_mem_ctrl/capture_loop_Z/CLK
11.683	-0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_loop_Z
11.648	-0.035	tSu		1	R11C8[0][A]	u_la0_top/u_ao_mem_ctrl/capture_loop_Z

Path Statistics:

Clock Skew	-0.033
Setup Relationship	5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.586, 91.769%; tC2Q: 0.232, 8.231%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path4

Path Summary:

Slack	1.914
Data Arrival Time	9.734
Data Required Time	11.648
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_length_Z[0]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.688	0.688	tINS	FF	576	IOT48[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R9C10[0][B]	u_la0_top/rst_ao_Z/CLK
7.148	0.232	tC2Q	FF	49	R9C10[0][B]	u_la0_top/rst_ao_Z/Q
9.734	2.586	tNET	FF	1	R12C5[1][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[0]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	576	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R12C5[1][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[0]/CLK
11.683	-0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_length_Z[0]
11.648	-0.035	tSu		1	R12C5[1][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[0]

Path Statistics:

Clock Skew	-0.033
Setup Relationship	5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.586, 91.769%; tC2Q: 0.232, 8.231%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path5

Path Summary:

Slack	1.914
Data Arrival Time	9.734
Data Required Time	11.648
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_length_Z[1]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.688	0.688	tINS	FF	576	IOT48[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R9C10[0][B]	u_la0_top/rst_ao_Z/CLK
7.148	0.232	tC2Q	FF	49	R9C10[0][B]	u_la0_top/rst_ao_Z/Q
9.734	2.586	tNET	FF	1	R6C11[2][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[1]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	576	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R6C11[2][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[1]/CLK
11.683	-0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_length_Z[1]
11.648	-0.035	tSu		1	R6C11[2][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[1]

Path Statistics:

Clock Skew	-0.033
Setup Relationship	5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.586, 91.769%; tC2Q: 0.232, 8.231%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path6

Path Summary:

Slack	1.914
Data Arrival Time	9.734
Data Required Time	11.648
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_length_Z[2]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.688	0.688	tINS	FF	576	IOT48[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R9C10[0][B]	u_la0_top/rst_ao_Z/CLK
7.148	0.232	tC2Q	FF	49	R9C10[0][B]	u_la0_top/rst_ao_Z/Q
9.734	2.586	tNET	FF	1	R8C10[0][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[2]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	576	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R8C10[0][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[2]/CLK
11.683	-0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_length_Z[2]
11.648	-0.035	tSu		1	R8C10[0][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[2]

Path Statistics:

Clock Skew	-0.033
Setup Relationship	5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.586, 91.769%; tC2Q: 0.232, 8.231%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path7

Path Summary:

Slack	1.914
Data Arrival Time	9.734
Data Required Time	11.648
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_length_Z[3]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.688	0.688	tINS	FF	576	IOT48[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R9C10[0][B]	u_la0_top/rst_ao_Z/CLK
7.148	0.232	tC2Q	FF	49	R9C10[0][B]	u_la0_top/rst_ao_Z/Q
9.734	2.586	tNET	FF	1	R12C8[1][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[3]/PRESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	576	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R12C8[1][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[3]/CLK
11.683	-0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_length_Z[3]
11.648	-0.035	tSu		1	R12C8[1][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[3]

Path Statistics:

Clock Skew	-0.033
Setup Relationship	5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.586, 91.769%; tC2Q: 0.232, 8.231%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path8

Path Summary:

Slack	1.914
Data Arrival Time	9.734
Data Required Time	11.648
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_length_Z[4]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.688	0.688	tINS	FF	576	IOT48[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R9C10[0][B]	u_la0_top/rst_ao_Z/CLK
7.148	0.232	tC2Q	FF	49	R9C10[0][B]	u_la0_top/rst_ao_Z/Q
9.734	2.586	tNET	FF	1	R8C10[0][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[4]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	576	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R8C10[0][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[4]/CLK
11.683	-0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_length_Z[4]
11.648	-0.035	tSu		1	R8C10[0][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[4]

Path Statistics:

Clock Skew	-0.033
Setup Relationship	5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.586, 91.769%; tC2Q: 0.232, 8.231%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path9

Path Summary:

Slack	1.914
Data Arrival Time	9.734
Data Required Time	11.648
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_length_Z[5]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.688	0.688	tINS	FF	576	IOT48[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R9C10[0][B]	u_la0_top/rst_ao_Z/CLK
7.148	0.232	tC2Q	FF	49	R9C10[0][B]	u_la0_top/rst_ao_Z/Q
9.734	2.586	tNET	FF	1	R7C10[2][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[5]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	576	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R7C10[2][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[5]/CLK
11.683	-0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_length_Z[5]
11.648	-0.035	tSu		1	R7C10[2][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[5]

Path Statistics:

Clock Skew	-0.033
Setup Relationship	5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.586, 91.769%; tC2Q: 0.232, 8.231%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path10

Path Summary:

Slack	1.914
Data Arrival Time	9.734
Data Required Time	11.648
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_length_Z[6]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.688	0.688	tINS	FF	576	IOT48[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R9C10[0][B]	u_la0_top/rst_ao_Z/CLK
7.148	0.232	tC2Q	FF	49	R9C10[0][B]	u_la0_top/rst_ao_Z/Q
9.734	2.586	tNET	FF	1	R7C10[2][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[6]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	576	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R7C10[2][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[6]/CLK
11.683	-0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_length_Z[6]
11.648	-0.035	tSu		1	R7C10[2][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[6]

Path Statistics:

Clock Skew	-0.033
Setup Relationship	5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.586, 91.769%; tC2Q: 0.232, 8.231%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path11

Path Summary:

Slack	1.914
Data Arrival Time	9.734
Data Required Time	11.648
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_length_Z[7]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.688	0.688	tINS	FF	576	IOT48[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R9C10[0][B]	u_la0_top/rst_ao_Z/CLK
7.148	0.232	tC2Q	FF	49	R9C10[0][B]	u_la0_top/rst_ao_Z/Q
9.734	2.586	tNET	FF	1	R11C9[0][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[7]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	576	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R11C9[0][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[7]/CLK
11.683	-0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_length_Z[7]
11.648	-0.035	tSu		1	R11C9[0][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[7]

Path Statistics:

Clock Skew	-0.033
Setup Relationship	5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.586, 91.769%; tC2Q: 0.232, 8.231%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path12

Path Summary:

Slack	1.914
Data Arrival Time	9.734
Data Required Time	11.648
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_length_Z[8]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.688	0.688	tINS	FF	576	IOT48[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R9C10[0][B]	u_la0_top/rst_ao_Z/CLK
7.148	0.232	tC2Q	FF	49	R9C10[0][B]	u_la0_top/rst_ao_Z/Q
9.734	2.586	tNET	FF	1	R11C9[0][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[8]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	576	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R11C9[0][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[8]/CLK
11.683	-0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_length_Z[8]
11.648	-0.035	tSu		1	R11C9[0][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[8]

Path Statistics:

Clock Skew	-0.033
Setup Relationship	5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.586, 91.769%; tC2Q: 0.232, 8.231%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path13

Path Summary:

Slack	1.914
Data Arrival Time	9.734
Data Required Time	11.648
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_length_Z[9]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.688	0.688	tINS	FF	576	IOT48[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R9C10[0][B]	u_la0_top/rst_ao_Z/CLK
7.148	0.232	tC2Q	FF	49	R9C10[0][B]	u_la0_top/rst_ao_Z/Q
9.734	2.586	tNET	FF	1	R11C8[1][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[9]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	576	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R11C8[1][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[9]/CLK
11.683	-0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_length_Z[9]
11.648	-0.035	tSu		1	R11C8[1][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[9]

Path Statistics:

Clock Skew	-0.033
Setup Relationship	5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.586, 91.769%; tC2Q: 0.232, 8.231%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path14

Path Summary:

Slack	1.914
Data Arrival Time	9.734
Data Required Time	11.648
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_length_Z[10]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.688	0.688	tINS	FF	576	IOT48[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R9C10[0][B]	u_la0_top/rst_ao_Z/CLK
7.148	0.232	tC2Q	FF	49	R9C10[0][B]	u_la0_top/rst_ao_Z/Q
9.734	2.586	tNET	FF	1	R9C8[2][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[10]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	576	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R9C8[2][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[10]/CLK
11.683	-0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_length_Z[10]
11.648	-0.035	tSu		1	R9C8[2][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[10]

Path Statistics:

Clock Skew	-0.033
Setup Relationship	5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.586, 91.769%; tC2Q: 0.232, 8.231%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path15

Path Summary:

Slack	1.914
Data Arrival Time	9.734
Data Required Time	11.648
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_length_Z[11]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.688	0.688	tINS	FF	576	IOT48[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R9C10[0][B]	u_la0_top/rst_ao_Z/CLK
7.148	0.232	tC2Q	FF	49	R9C10[0][B]	u_la0_top/rst_ao_Z/Q
9.734	2.586	tNET	FF	1	R9C8[2][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[11]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	576	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R9C8[2][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[11]/CLK
11.683	-0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_length_Z[11]
11.648	-0.035	tSu		1	R9C8[2][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[11]

Path Statistics:

Clock Skew	-0.033
Setup Relationship	5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.586, 91.769%; tC2Q: 0.232, 8.231%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path16

Path Summary:

Slack	1.914
Data Arrival Time	9.734
Data Required Time	11.648
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_length_Z[12]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.688	0.688	tINS	FF	576	IOT48[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R9C10[0][B]	u_la0_top/rst_ao_Z/CLK
7.148	0.232	tC2Q	FF	49	R9C10[0][B]	u_la0_top/rst_ao_Z/Q
9.734	2.586	tNET	FF	1	R4C4[0][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[12]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	576	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R4C4[0][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[12]/CLK
11.683	-0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_length_Z[12]
11.648	-0.035	tSu		1	R4C4[0][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[12]

Path Statistics:

Clock Skew	-0.033
Setup Relationship	5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.586, 91.769%; tC2Q: 0.232, 8.231%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path17

Path Summary:

Slack	1.914
Data Arrival Time	9.734
Data Required Time	11.648
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.688	0.688	tINS	FF	576	IOT48[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R9C10[0][B]	u_la0_top/rst_ao_Z/CLK
7.148	0.232	tC2Q	FF	49	R9C10[0][B]	u_la0_top/rst_ao_Z/Q
9.734	2.586	tNET	FF	1	R9C10[1][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	576	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R9C10[1][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0]/CLK
11.683	-0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0]
11.648	-0.035	tSu		1	R9C10[1][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0]

Path Statistics:

Clock Skew	-0.033
Setup Relationship	5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.586, 91.769%; tC2Q: 0.232, 8.231%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path18

Path Summary:

Slack	1.914
Data Arrival Time	9.734
Data Required Time	11.648
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[1]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.688	0.688	tINS	FF	576	IOT48[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R9C10[0][B]	u_la0_top/rst_ao_Z/CLK
7.148	0.232	tC2Q	FF	49	R9C10[0][B]	u_la0_top/rst_ao_Z/Q
9.734	2.586	tNET	FF	1	R9C10[1][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[1]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	576	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R9C10[1][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[1]/CLK
11.683	-0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[1]
11.648	-0.035	tSu		1	R9C10[1][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[1]

Path Statistics:

Clock Skew	-0.033
Setup Relationship	5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.586, 91.769%; tC2Q: 0.232, 8.231%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path19

Path Summary:

Slack	1.914
Data Arrival Time	9.734
Data Required Time	11.648
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[2]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.688	0.688	tINS	FF	576	IOT48[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R9C10[0][B]	u_la0_top/rst_ao_Z/CLK
7.148	0.232	tC2Q	FF	49	R9C10[0][B]	u_la0_top/rst_ao_Z/Q
9.734	2.586	tNET	FF	1	R9C10[2][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[2]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	576	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R9C10[2][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[2]/CLK
11.683	-0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[2]
11.648	-0.035	tSu		1	R9C10[2][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[2]

Path Statistics:

Clock Skew	-0.033
Setup Relationship	5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.586, 91.769%; tC2Q: 0.232, 8.231%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path20

Path Summary:

Slack	1.914
Data Arrival Time	9.734
Data Required Time	11.648
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[3]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.688	0.688	tINS	FF	576	IOT48[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R9C10[0][B]	u_la0_top/rst_ao_Z/CLK
7.148	0.232	tC2Q	FF	49	R9C10[0][B]	u_la0_top/rst_ao_Z/Q
9.734	2.586	tNET	FF	1	R9C10[2][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[3]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	576	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R9C10[2][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[3]/CLK
11.683	-0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[3]
11.648	-0.035	tSu		1	R9C10[2][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[3]

Path Statistics:

Clock Skew	-0.033
Setup Relationship	5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.586, 91.769%; tC2Q: 0.232, 8.231%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path21

Path Summary:

Slack	1.914
Data Arrival Time	9.734
Data Required Time	11.648
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[4]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.688	0.688	tINS	FF	576	IOT48[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R9C10[0][B]	u_la0_top/rst_ao_Z/CLK
7.148	0.232	tC2Q	FF	49	R9C10[0][B]	u_la0_top/rst_ao_Z/Q
9.734	2.586	tNET	FF	1	R5C11[2][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[4]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	576	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R5C11[2][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[4]/CLK
11.683	-0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[4]
11.648	-0.035	tSu		1	R5C11[2][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[4]

Path Statistics:

Clock Skew	-0.033
Setup Relationship	5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.586, 91.769%; tC2Q: 0.232, 8.231%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path22

Path Summary:

Slack	1.914
Data Arrival Time	9.734
Data Required Time	11.648
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[5]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.688	0.688	tINS	FF	576	IOT48[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R9C10[0][B]	u_la0_top/rst_ao_Z/CLK
7.148	0.232	tC2Q	FF	49	R9C10[0][B]	u_la0_top/rst_ao_Z/Q
9.734	2.586	tNET	FF	1	R12C9[1][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[5]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	576	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R12C9[1][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[5]/CLK
11.683	-0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[5]
11.648	-0.035	tSu		1	R12C9[1][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[5]

Path Statistics:

Clock Skew	-0.033
Setup Relationship	5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.586, 91.769%; tC2Q: 0.232, 8.231%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path23

Path Summary:

Slack	1.914
Data Arrival Time	9.734
Data Required Time	11.648
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[6]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.688	0.688	tINS	FF	576	IOT48[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R9C10[0][B]	u_la0_top/rst_ao_Z/CLK
7.148	0.232	tC2Q	FF	49	R9C10[0][B]	u_la0_top/rst_ao_Z/Q
9.734	2.586	tNET	FF	1	R12C9[1][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[6]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	576	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R12C9[1][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[6]/CLK
11.683	-0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[6]
11.648	-0.035	tSu		1	R12C9[1][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[6]

Path Statistics:

Clock Skew	-0.033
Setup Relationship	5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.586, 91.769%; tC2Q: 0.232, 8.231%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path24

Path Summary:

Slack	1.914
Data Arrival Time	9.734
Data Required Time	11.648
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[7]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.688	0.688	tINS	FF	576	IOT48[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R9C10[0][B]	u_la0_top/rst_ao_Z/CLK
7.148	0.232	tC2Q	FF	49	R9C10[0][B]	u_la0_top/rst_ao_Z/Q
9.734	2.586	tNET	FF	1	R5C11[2][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[7]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	576	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R5C11[2][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[7]/CLK
11.683	-0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[7]
11.648	-0.035	tSu		1	R5C11[2][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[7]

Path Statistics:

Clock Skew	-0.033
Setup Relationship	5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.586, 91.769%; tC2Q: 0.232, 8.231%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path25

Path Summary:

Slack	1.914
Data Arrival Time	9.734
Data Required Time	11.648
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.688	0.688	tINS	FF	576	IOT48[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R9C10[0][B]	u_la0_top/rst_ao_Z/CLK
7.148	0.232	tC2Q	FF	49	R9C10[0][B]	u_la0_top/rst_ao_Z/Q
9.734	2.586	tNET	FF	1	R11C8[2][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	576	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R11C8[2][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8]/CLK
11.683	-0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8]
11.648	-0.035	tSu		1	R11C8[2][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8]

Path Statistics:

Clock Skew	-0.033
Setup Relationship	5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.586, 91.769%; tC2Q: 0.232, 8.231%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Removal Analysis Report

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	6.623
Data Arrival Time	8.411
Data Required Time	1.788
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.677	0.678	tINS	FF	576	IOT48[A]	clk_ibuf/O
6.590	0.913	tNET	FF	1	R9C10[0][B]	u_la0_top/rst_ao_Z/CLK
6.792	0.202	tC2Q	FR	49	R9C10[0][B]	u_la0_top/rst_ao_Z/Q
8.411	1.619	tNET	RR	1	R5C12[2][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	576	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R5C12[2][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z/CLK
1.777	0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z
1.788	0.011	tHld		1	R5C12[2][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.619, 88.906%; tC2Q: 0.202, 11.094%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path2

Path Summary:

Slack	6.623
Data Arrival Time	8.411
Data Required Time	1.788
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_loop_Z
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.677	0.678	tINS	FF	576	IOT48[A]	clk_ibuf/O
6.590	0.913	tNET	FF	1	R9C10[0][B]	u_la0_top/rst_ao_Z/CLK
6.792	0.202	tC2Q	FR	49	R9C10[0][B]	u_la0_top/rst_ao_Z/Q
8.411	1.619	tNET	RR	1	R11C8[0][A]	u_la0_top/u_ao_mem_ctrl/capture_loop_Z/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	576	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R11C8[0][A]	u_la0_top/u_ao_mem_ctrl/capture_loop_Z/CLK
1.777	0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_loop_Z
1.788	0.011	tHld		1	R11C8[0][A]	u_la0_top/u_ao_mem_ctrl/capture_loop_Z

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.619, 88.906%; tC2Q: 0.202, 11.094%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path3

Path Summary:

Slack	6.623
Data Arrival Time	8.411
Data Required Time	1.788
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_length_Z[0]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.677	0.678	tINS	FF	576	IOT48[A]	clk_ibuf/O
6.590	0.913	tNET	FF	1	R9C10[0][B]	u_la0_top/rst_ao_Z/CLK
6.792	0.202	tC2Q	FR	49	R9C10[0][B]	u_la0_top/rst_ao_Z/Q
8.411	1.619	tNET	RR	1	R12C5[1][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[0]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	576	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R12C5[1][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[0]/CLK
1.777	0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_length_Z[0]
1.788	0.011	tHld		1	R12C5[1][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[0]

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.619, 88.906%; tC2Q: 0.202, 11.094%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path4

Path Summary:

Slack	6.623
Data Arrival Time	8.411
Data Required Time	1.788
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_length_Z[1]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.677	0.678	tINS	FF	576	IOT48[A]	clk_ibuf/O
6.590	0.913	tNET	FF	1	R9C10[0][B]	u_la0_top/rst_ao_Z/CLK
6.792	0.202	tC2Q	FR	49	R9C10[0][B]	u_la0_top/rst_ao_Z/Q
8.411	1.619	tNET	RR	1	R6C11[2][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[1]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	576	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R6C11[2][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[1]/CLK
1.777	0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_length_Z[1]
1.788	0.011	tHld		1	R6C11[2][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[1]

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.619, 88.906%; tC2Q: 0.202, 11.094%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path5

Path Summary:

Slack	6.623
Data Arrival Time	8.411
Data Required Time	1.788
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_length_Z[2]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.677	0.678	tINS	FF	576	IOT48[A]	clk_ibuf/O
6.590	0.913	tNET	FF	1	R9C10[0][B]	u_la0_top/rst_ao_Z/CLK
6.792	0.202	tC2Q	FR	49	R9C10[0][B]	u_la0_top/rst_ao_Z/Q
8.411	1.619	tNET	RR	1	R8C10[0][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[2]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	576	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R8C10[0][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[2]/CLK
1.777	0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_length_Z[2]
1.788	0.011	tHld		1	R8C10[0][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[2]

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.619, 88.906%; tC2Q: 0.202, 11.094%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path6

Path Summary:

Slack	6.623
Data Arrival Time	8.411
Data Required Time	1.788
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_length_Z[4]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.677	0.678	tINS	FF	576	IOT48[A]	clk_ibuf/O
6.590	0.913	tNET	FF	1	R9C10[0][B]	u_la0_top/rst_ao_Z/CLK
6.792	0.202	tC2Q	FR	49	R9C10[0][B]	u_la0_top/rst_ao_Z/Q
8.411	1.619	tNET	RR	1	R8C10[0][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[4]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	576	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R8C10[0][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[4]/CLK
1.777	0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_length_Z[4]
1.788	0.011	tHld		1	R8C10[0][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[4]

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.619, 88.906%; tC2Q: 0.202, 11.094%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path7

Path Summary:

Slack	6.623
Data Arrival Time	8.411
Data Required Time	1.788
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_length_Z[5]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.677	0.678	tINS	FF	576	IOT48[A]	clk_ibuf/O
6.590	0.913	tNET	FF	1	R9C10[0][B]	u_la0_top/rst_ao_Z/CLK
6.792	0.202	tC2Q	FR	49	R9C10[0][B]	u_la0_top/rst_ao_Z/Q
8.411	1.619	tNET	RR	1	R7C10[2][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[5]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	576	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R7C10[2][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[5]/CLK
1.777	0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_length_Z[5]
1.788	0.011	tHld		1	R7C10[2][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[5]

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.619, 88.906%; tC2Q: 0.202, 11.094%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path8

Path Summary:

Slack	6.623
Data Arrival Time	8.411
Data Required Time	1.788
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_length_Z[7]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.677	0.678	tINS	FF	576	IOT48[A]	clk_ibuf/O
6.590	0.913	tNET	FF	1	R9C10[0][B]	u_la0_top/rst_ao_Z/CLK
6.792	0.202	tC2Q	FR	49	R9C10[0][B]	u_la0_top/rst_ao_Z/Q
8.411	1.619	tNET	RR	1	R11C9[0][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[7]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	576	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R11C9[0][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[7]/CLK
1.777	0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_length_Z[7]
1.788	0.011	tHld		1	R11C9[0][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[7]

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.619, 88.906%; tC2Q: 0.202, 11.094%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path9

Path Summary:

Slack	6.623
Data Arrival Time	8.411
Data Required Time	1.788
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_length_Z[8]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.677	0.678	tINS	FF	576	IOT48[A]	clk_ibuf/O
6.590	0.913	tNET	FF	1	R9C10[0][B]	u_la0_top/rst_ao_Z/CLK
6.792	0.202	tC2Q	FR	49	R9C10[0][B]	u_la0_top/rst_ao_Z/Q
8.411	1.619	tNET	RR	1	R11C9[0][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[8]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	576	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R11C9[0][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[8]/CLK
1.777	0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_length_Z[8]
1.788	0.011	tHld		1	R11C9[0][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[8]

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.619, 88.906%; tC2Q: 0.202, 11.094%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path10

Path Summary:

Slack	6.623
Data Arrival Time	8.411
Data Required Time	1.788
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_length_Z[9]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.677	0.678	tINS	FF	576	IOT48[A]	clk_ibuf/O
6.590	0.913	tNET	FF	1	R9C10[0][B]	u_la0_top/rst_ao_Z/CLK
6.792	0.202	tC2Q	FR	49	R9C10[0][B]	u_la0_top/rst_ao_Z/Q
8.411	1.619	tNET	RR	1	R11C8[1][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[9]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	576	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R11C8[1][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[9]/CLK
1.777	0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_length_Z[9]
1.788	0.011	tHld		1	R11C8[1][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[9]

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.619, 88.906%; tC2Q: 0.202, 11.094%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path11

Path Summary:

Slack	6.623
Data Arrival Time	8.411
Data Required Time	1.788
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_length_Z[10]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.677	0.678	tINS	FF	576	IOT48[A]	clk_ibuf/O
6.590	0.913	tNET	FF	1	R9C10[0][B]	u_la0_top/rst_ao_Z/CLK
6.792	0.202	tC2Q	FR	49	R9C10[0][B]	u_la0_top/rst_ao_Z/Q
8.411	1.619	tNET	RR	1	R9C8[2][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[10]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	576	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R9C8[2][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[10]/CLK
1.777	0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_length_Z[10]
1.788	0.011	tHld		1	R9C8[2][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[10]

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.619, 88.906%; tC2Q: 0.202, 11.094%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path12

Path Summary:

Slack	6.623
Data Arrival Time	8.411
Data Required Time	1.788
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_length_Z[11]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.677	0.678	tINS	FF	576	IOT48[A]	clk_ibuf/O
6.590	0.913	tNET	FF	1	R9C10[0][B]	u_la0_top/rst_ao_Z/CLK
6.792	0.202	tC2Q	FR	49	R9C10[0][B]	u_la0_top/rst_ao_Z/Q
8.411	1.619	tNET	RR	1	R9C8[2][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[11]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	576	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R9C8[2][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[11]/CLK
1.777	0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_length_Z[11]
1.788	0.011	tHld		1	R9C8[2][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[11]

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.619, 88.906%; tC2Q: 0.202, 11.094%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path13

Path Summary:

Slack	6.623
Data Arrival Time	8.411
Data Required Time	1.788
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_length_Z[12]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.677	0.678	tINS	FF	576	IOT48[A]	clk_ibuf/O
6.590	0.913	tNET	FF	1	R9C10[0][B]	u_la0_top/rst_ao_Z/CLK
6.792	0.202	tC2Q	FR	49	R9C10[0][B]	u_la0_top/rst_ao_Z/Q
8.411	1.619	tNET	RR	1	R4C4[0][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[12]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	576	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R4C4[0][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[12]/CLK
1.777	0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_length_Z[12]
1.788	0.011	tHld		1	R4C4[0][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[12]

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.619, 88.906%; tC2Q: 0.202, 11.094%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path14

Path Summary:

Slack	6.623
Data Arrival Time	8.411
Data Required Time	1.788
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.677	0.678	tINS	FF	576	IOT48[A]	clk_ibuf/O
6.590	0.913	tNET	FF	1	R9C10[0][B]	u_la0_top/rst_ao_Z/CLK
6.792	0.202	tC2Q	FR	49	R9C10[0][B]	u_la0_top/rst_ao_Z/Q
8.411	1.619	tNET	RR	1	R9C10[1][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	576	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R9C10[1][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0]/CLK
1.777	0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0]
1.788	0.011	tHld		1	R9C10[1][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0]

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.619, 88.906%; tC2Q: 0.202, 11.094%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path15

Path Summary:

Slack	6.623
Data Arrival Time	8.411
Data Required Time	1.788
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[1]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.677	0.678	tINS	FF	576	IOT48[A]	clk_ibuf/O
6.590	0.913	tNET	FF	1	R9C10[0][B]	u_la0_top/rst_ao_Z/CLK
6.792	0.202	tC2Q	FR	49	R9C10[0][B]	u_la0_top/rst_ao_Z/Q
8.411	1.619	tNET	RR	1	R9C10[1][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[1]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	576	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R9C10[1][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[1]/CLK
1.777	0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[1]
1.788	0.011	tHld		1	R9C10[1][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[1]

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.619, 88.906%; tC2Q: 0.202, 11.094%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path16

Path Summary:

Slack	6.623
Data Arrival Time	8.411
Data Required Time	1.788
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[2]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.677	0.678	tINS	FF	576	IOT48[A]	clk_ibuf/O
6.590	0.913	tNET	FF	1	R9C10[0][B]	u_la0_top/rst_ao_Z/CLK
6.792	0.202	tC2Q	FR	49	R9C10[0][B]	u_la0_top/rst_ao_Z/Q
8.411	1.619	tNET	RR	1	R9C10[2][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[2]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	576	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R9C10[2][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[2]/CLK
1.777	0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[2]
1.788	0.011	tHld		1	R9C10[2][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[2]

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.619, 88.906%; tC2Q: 0.202, 11.094%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path17

Path Summary:

Slack	6.623
Data Arrival Time	8.411
Data Required Time	1.788
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[3]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.677	0.678	tINS	FF	576	IOT48[A]	clk_ibuf/O
6.590	0.913	tNET	FF	1	R9C10[0][B]	u_la0_top/rst_ao_Z/CLK
6.792	0.202	tC2Q	FR	49	R9C10[0][B]	u_la0_top/rst_ao_Z/Q
8.411	1.619	tNET	RR	1	R9C10[2][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[3]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	576	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R9C10[2][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[3]/CLK
1.777	0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[3]
1.788	0.011	tHld		1	R9C10[2][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[3]

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.619, 88.906%; tC2Q: 0.202, 11.094%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path18

Path Summary:

Slack	6.623
Data Arrival Time	8.411
Data Required Time	1.788
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[4]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.677	0.678	tINS	FF	576	IOT48[A]	clk_ibuf/O
6.590	0.913	tNET	FF	1	R9C10[0][B]	u_la0_top/rst_ao_Z/CLK
6.792	0.202	tC2Q	FR	49	R9C10[0][B]	u_la0_top/rst_ao_Z/Q
8.411	1.619	tNET	RR	1	R5C11[2][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[4]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	576	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R5C11[2][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[4]/CLK
1.777	0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[4]
1.788	0.011	tHld		1	R5C11[2][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[4]

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.619, 88.906%; tC2Q: 0.202, 11.094%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path19

Path Summary:

Slack	6.623
Data Arrival Time	8.411
Data Required Time	1.788
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[5]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.677	0.678	tINS	FF	576	IOT48[A]	clk_ibuf/O
6.590	0.913	tNET	FF	1	R9C10[0][B]	u_la0_top/rst_ao_Z/CLK
6.792	0.202	tC2Q	FR	49	R9C10[0][B]	u_la0_top/rst_ao_Z/Q
8.411	1.619	tNET	RR	1	R12C9[1][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[5]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	576	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R12C9[1][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[5]/CLK
1.777	0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[5]
1.788	0.011	tHld		1	R12C9[1][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[5]

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.619, 88.906%; tC2Q: 0.202, 11.094%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path20

Path Summary:

Slack	6.623
Data Arrival Time	8.411
Data Required Time	1.788
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[6]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.677	0.678	tINS	FF	576	IOT48[A]	clk_ibuf/O
6.590	0.913	tNET	FF	1	R9C10[0][B]	u_la0_top/rst_ao_Z/CLK
6.792	0.202	tC2Q	FR	49	R9C10[0][B]	u_la0_top/rst_ao_Z/Q
8.411	1.619	tNET	RR	1	R12C9[1][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[6]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	576	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R12C9[1][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[6]/CLK
1.777	0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[6]
1.788	0.011	tHld		1	R12C9[1][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[6]

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.619, 88.906%; tC2Q: 0.202, 11.094%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path21

Path Summary:

Slack	6.623
Data Arrival Time	8.411
Data Required Time	1.788
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[7]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.677	0.678	tINS	FF	576	IOT48[A]	clk_ibuf/O
6.590	0.913	tNET	FF	1	R9C10[0][B]	u_la0_top/rst_ao_Z/CLK
6.792	0.202	tC2Q	FR	49	R9C10[0][B]	u_la0_top/rst_ao_Z/Q
8.411	1.619	tNET	RR	1	R5C11[2][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[7]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	576	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R5C11[2][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[7]/CLK
1.777	0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[7]
1.788	0.011	tHld		1	R5C11[2][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[7]

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.619, 88.906%; tC2Q: 0.202, 11.094%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path22

Path Summary:

Slack	6.623
Data Arrival Time	8.411
Data Required Time	1.788
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.677	0.678	tINS	FF	576	IOT48[A]	clk_ibuf/O
6.590	0.913	tNET	FF	1	R9C10[0][B]	u_la0_top/rst_ao_Z/CLK
6.792	0.202	tC2Q	FR	49	R9C10[0][B]	u_la0_top/rst_ao_Z/Q
8.411	1.619	tNET	RR	1	R11C8[2][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	576	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R11C8[2][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8]/CLK
1.777	0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8]
1.788	0.011	tHld		1	R11C8[2][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8]

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.619, 88.906%; tC2Q: 0.202, 11.094%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path23

Path Summary:

Slack	6.623
Data Arrival Time	8.411
Data Required Time	1.788
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[9]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.677	0.678	tINS	FF	576	IOT48[A]	clk_ibuf/O
6.590	0.913	tNET	FF	1	R9C10[0][B]	u_la0_top/rst_ao_Z/CLK
6.792	0.202	tC2Q	FR	49	R9C10[0][B]	u_la0_top/rst_ao_Z/Q
8.411	1.619	tNET	RR	1	R11C8[2][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[9]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	576	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R11C8[2][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[9]/CLK
1.777	0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[9]
1.788	0.011	tHld		1	R11C8[2][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[9]

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.619, 88.906%; tC2Q: 0.202, 11.094%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path24

Path Summary:

Slack	6.623
Data Arrival Time	8.411
Data Required Time	1.788
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[10]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.677	0.678	tINS	FF	576	IOT48[A]	clk_ibuf/O
6.590	0.913	tNET	FF	1	R9C10[0][B]	u_la0_top/rst_ao_Z/CLK
6.792	0.202	tC2Q	FR	49	R9C10[0][B]	u_la0_top/rst_ao_Z/Q
8.411	1.619	tNET	RR	1	R11C9[1][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[10]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	576	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R11C9[1][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[10]/CLK
1.777	0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[10]
1.788	0.011	tHld		1	R11C9[1][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[10]

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.619, 88.906%; tC2Q: 0.202, 11.094%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path25

Path Summary:

Slack	6.623
Data Arrival Time	8.411
Data Required Time	1.788
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[11]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.677	0.678	tINS	FF	576	IOT48[A]	clk_ibuf/O
6.590	0.913	tNET	FF	1	R9C10[0][B]	u_la0_top/rst_ao_Z/CLK
6.792	0.202	tC2Q	FR	49	R9C10[0][B]	u_la0_top/rst_ao_Z/Q
8.411	1.619	tNET	RR	1	R11C9[1][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[11]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	576	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R11C9[1][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[11]/CLK
1.777	0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[11]
1.788	0.011	tHld		1	R11C9[1][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[11]

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.619, 88.906%; tC2Q: 0.202, 11.094%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Minimum Pulse Width Report:

Report Command:report_min_pulse_width -nworst 10 -detail

MPW1

MPW Summary:

Slack:	3.662
Actual Width:	4.662
Required Width:	1.000
Type:	Low Pulse Width
Clock:	DEFAULT_CLK
Objects:	cnt_1_Z[12]

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	clk_ibuf/I
5.688	0.688	tINS	FF	clk_ibuf/O
6.916	1.228	tNET	FF	cnt_1_Z[12]/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	clk_ibuf/I
10.675	0.675	tINS	RR	clk_ibuf/O
11.577	0.902	tNET	RR	cnt_1_Z[12]/CLK

MPW2

MPW Summary:

Slack:	3.662
Actual Width:	4.662
Required Width:	1.000
Type:	Low Pulse Width
Clock:	DEFAULT_CLK
Objects:	cnt_1_Z[10]

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	clk_ibuf/I
5.688	0.688	tINS	FF	clk_ibuf/O
6.916	1.228	tNET	FF	cnt_1_Z[10]/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	clk_ibuf/I
10.675	0.675	tINS	RR	clk_ibuf/O
11.577	0.902	tNET	RR	cnt_1_Z[10]/CLK

MPW3

MPW Summary:

Slack:	3.662
Actual Width:	4.662
Required Width:	1.000
Type:	Low Pulse Width
Clock:	DEFAULT_CLK
Objects:	cnt_1_Z[6]

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	clk_ibuf/I
5.688	0.688	tINS	FF	clk_ibuf/O
6.916	1.228	tNET	FF	cnt_1_Z[6]/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	clk_ibuf/I
10.675	0.675	tINS	RR	clk_ibuf/O
11.577	0.902	tNET	RR	cnt_1_Z[6]/CLK

MPW4

MPW Summary:

Slack:	3.662
Actual Width:	4.662
Required Width:	1.000
Type:	Low Pulse Width
Clock:	DEFAULT_CLK
Objects:	cnt_Z[11]

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	clk_ibuf/I
5.688	0.688	tINS	FF	clk_ibuf/O
6.916	1.228	tNET	FF	cnt_Z[11]/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	clk_ibuf/I
10.675	0.675	tINS	RR	clk_ibuf/O
11.577	0.902	tNET	RR	cnt_Z[11]/CLK

MPW5

MPW Summary:

Slack:	3.662
Actual Width:	4.662
Required Width:	1.000
Type:	Low Pulse Width
Clock:	DEFAULT_CLK
Objects:	dividend[24]

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	clk_ibuf/I
5.688	0.688	tINS	FF	clk_ibuf/O
6.916	1.228	tNET	FF	dividend[24]/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	clk_ibuf/I
10.675	0.675	tINS	RR	clk_ibuf/O
11.577	0.902	tNET	RR	dividend[24]/CLK

MPW6

MPW Summary:

Slack:	3.662
Actual Width:	4.662
Required Width:	1.000
Type:	Low Pulse Width
Clock:	DEFAULT_CLK
Objects:	memr_memr_0_0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	clk_ibuf/I
5.688	0.688	tINS	FF	clk_ibuf/O
6.916	1.228	tNET	FF	memr_memr_0_0/CLKA

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	clk_ibuf/I
10.675	0.675	tINS	RR	clk_ibuf/O
11.577	0.902	tNET	RR	memr_memr_0_0/CLKA

MPW7

MPW Summary:

Slack:	3.662
Actual Width:	4.662
Required Width:	1.000
Type:	Low Pulse Width
Clock:	DEFAULT_CLK
Objects:	Mdu/u_mdu/div_shift_number_Z[5]

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	clk_ibuf/I
5.688	0.688	tINS	FF	clk_ibuf/O
6.916	1.228	tNET	FF	Mdu/u_mdu/div_shift_number_Z[5]/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	clk_ibuf/I
10.675	0.675	tINS	RR	clk_ibuf/O
11.577	0.902	tNET	RR	Mdu/u_mdu/div_shift_number_Z[5]/CLK

MPW8

MPW Summary:

Slack:	3.662
Actual Width:	4.662
Required Width:	1.000
Type:	Low Pulse Width
Clock:	DEFAULT_CLK
Objects:	Mdu/u_mdu/reg0_fast_Z[12]

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	clk_ibuf/I
5.688	0.688	tINS	FF	clk_ibuf/O
6.916	1.228	tNET	FF	Mdu/u_mdu/reg0_fast_Z[12]/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	clk_ibuf/I
10.675	0.675	tINS	RR	clk_ibuf/O
11.577	0.902	tNET	RR	Mdu/u_mdu/reg0_fast_Z[12]/CLK

MPW9

MPW Summary:

Slack:	3.662
Actual Width:	4.662
Required Width:	1.000
Type:	Low Pulse Width
Clock:	DEFAULT_CLK
Objects:	u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	clk_ibuf/I
5.688	0.688	tINS	FF	clk_ibuf/O
6.916	1.228	tNET	FF	u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	clk_ibuf/I
10.675	0.675	tINS	RR	clk_ibuf/O
11.577	0.902	tNET	RR	u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z/CLK

MPW10

MPW Summary:

Slack:	3.662
Actual Width:	4.662
Required Width:	1.000
Type:	Low Pulse Width
Clock:	DEFAULT_CLK
Objects:	u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_Z

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	clk_ibuf/I
5.688	0.688	tINS	FF	clk_ibuf/O
6.916	1.228	tNET	FF	u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_Z/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	clk_ibuf/I
10.675	0.675	tINS	RR	clk_ibuf/O
11.577	0.902	tNET	RR	u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_Z/CLK

High Fanout Nets Report:

Report Command:report_high_fanout_nets -max_nets 10

FANOUT	NET NAME	WORST SLACK	MAX DELAY
334	clk_c	0.421	1.228
114	div_shift_number[1]	0.974	1.198
113	div_shift_number[0]	0.889	1.473
100	reg0_en	5.438	1.885
96	neg_result	4.351	1.889
92	state[1]	3.098	3.243
81	hi_result	2.299	1.824
74	reg0_exe_nx_sm0	1.445	1.819
71	a_c[31]	6.042	3.226
71	state[3]	5.628	1.850

Route Congestions Report:

Report Command:report_route_congestion -max_grids 10

GRID LOC	ROUTE CONGESTIONS
R43C48	0.875
R42C51	0.778
R46C49	0.764
R52C35	0.750
R42C42	0.750
R43C52	0.750
R46C57	0.736
R42C40	0.736
R42C41	0.736
R43C49	0.736

Timing Exceptions Report:

Setup Analysis Report

Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Hold Analysis Report

Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Recovery Analysis Report

Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Removal Analysis Report

Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Timing Constraints Report:

SDC Command Type	State	Detail Command