@N|Running in 64-bit mode
@N|Running in 64-bit mode
@N: CG1349 :	| Running Verilog Compiler in System Verilog mode
@N: CG1350 :	| Running Verilog Compiler in Multiple File Compilation Unit mode
@N: CG364 :"/share/gwsw/gowin_new/Gowin/Gowin_YunYuan_V1.9.xBeta/IDE/ipcore/INT_MULT_DIV/data/mdu_wrap.v":3:19:3:19|Synthesizing module Integer_Multiply_Divider_Top in library work.
@N|Running in 64-bit mode
@N: NF107 :"/share/gwsw/gowin_new/Gowin/Gowin_YunYuan_V1.9.xBeta/IDE/ipcore/INT_MULT_DIV/data/mdu_wrap.v":3:19:3:19|Selected library: work cell: Integer_Multiply_Divider_Top view verilog as top level
@N: NF107 :"/share/gwsw/gowin_new/Gowin/Gowin_YunYuan_V1.9.xBeta/IDE/ipcore/INT_MULT_DIV/data/mdu_wrap.v":3:19:3:19|Selected library: work cell: Integer_Multiply_Divider_Top view verilog as top level

