Timing Messages

Report Title	Gowin Timing Analysis Report
Design File	F:/user-bak/Users/FDELL/Desktop/IP/Integer_Multiply-Divider/ref_design/DIV/Integer_Multiply_Divider_nn/project/impl/synplify/rev_1/Integer_Multiply_Divider_nn.vm
Physical Constraints File	F:\user-bak\Users\FDELL\Desktop\IP\Integer_Multiply-Divider\ref_design\DIV\Integer_Multiply_Divider_nn\project\src\Integer_Multiply_Divider_nn.cst
Timing Constraints File	---
GOWIN version	v1.9.0Beta
Part Number	GW2A-LV55PG484C8/I7
Created Time	Tue Feb 19 17:48:24 2019
Legal Announcement	Copyright (C)2014-2019 Gowin Semiconductor Corporation. All rights reserved.

Timing Summaries

STA Tool Run Summary:

Setup Delay Model	Slow 0.95V 85C
Hold Delay Model	Fast 1.05V 0C
Numbers of Paths Analyzed	4129
Numbers of Endpoints Analyzed	9282
Numbers of Falling Endpoints	1
Numbers of Setup Violated Endpoints	0
Numbers of Hold Violated Endpoints	0

Clock Summary:

Clock Name	Type	Period	Frequency(MHz)	Rise	Fall	Source	Master	Objects
DEFAULT_CLK	Base	10.000	100.000	0.000	5.000

Max Frequency Summary:

NO.	Clock Name	Fmax	Entity
1	DEFAULT_CLK	100.566(MHz)	TOP

Total Negative Slack Summary:

Clock Name	Analysis Type	Endpoints TNS	Number of Endpoints
DEFAULT_CLK	Setup	0.000	0
DEFAULT_CLK	Hold	0.000	0

Timing Details

Path Slacks Table:

Setup Paths Table

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Data Delay
1	0.056	Mdu/u_mdu/rs1_mul_Z[5]/Q	Mdu/u_mdu/reg0_Z[7]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	9.709
2	0.180	Mdu/u_mdu/reg0_fast_Z[13]/Q	memq_memq_0_10/DI1	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	9.585
3	0.320	Mdu/u_mdu/reg0_fast_Z[13]/Q	memq_memq_0_15/DI1	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	9.445
4	0.348	Mdu/u_mdu/rs1_mul_Z[5]/Q	Mdu/u_mdu/reg0_Z[37]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	9.417
5	0.371	Mdu/u_mdu/reg0_fast_Z[13]/Q	memq_memq_0_14/DI1	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	9.394
6	0.522	Mdu/u_mdu/rs1_mul_Z[5]/Q	Mdu/u_mdu/reg0_Z[39]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	9.243
7	0.530	Mdu/u_mdu/div_shift_number_Z[1]/Q	Mdu/u_mdu/reg0_Z[54]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	9.235
8	0.605	Mdu/u_mdu/reg0_fast_Z[13]/Q	memq_memq_0_13/DI1	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	9.161
9	0.629	Mdu/u_mdu/reg0_fast_Z[13]/Q	memq_memq_0_9/DI1	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	9.136
10	0.679	Mdu/u_mdu/reg0_fast_Z[13]/Q	memq_memq_0_14/DI0	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	9.087
11	0.713	Mdu/u_mdu/reg0_fast_Z[13]/Q	Mdu/u_mdu/reg0_Z[19]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	9.052
12	0.733	Mdu/u_mdu/div_shift_number_Z[0]/Q	Mdu/u_mdu/reg0_Z[47]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	9.032
13	0.761	Mdu/u_mdu/reg0_fast_Z[13]/Q	memq_memq_0_15/DI0	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	9.004
14	0.782	Mdu/u_mdu/reg0_fast_Z[13]/Q	memq_memq_0_6/DI0	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	8.984
15	0.786	Mdu/u_mdu/reg0_fast_Z[13]/Q	Mdu/u_mdu/reg0_19_rep1_Z/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	8.979
16	0.804	Mdu/u_mdu/rs1_mul_Z[5]/Q	Mdu/u_mdu/reg0_Z[36]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	8.961
17	0.834	Mdu/u_mdu/div_shift_number_Z[0]/Q	Mdu/u_mdu/reg0_Z[43]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	8.931
18	0.856	Mdu/u_mdu/reg0_fast_Z[13]/Q	memq_memq_0_7/DI1	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	8.910
19	0.861	Mdu/u_mdu/rs1_mul_Z[5]/Q	Mdu/u_mdu/reg0_Z[45]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	8.904
20	0.863	Mdu/u_mdu/reg0_fast_Z[13]/Q	Mdu/u_mdu/reg0_fast_Z[19]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	8.902
21	0.881	Mdu/u_mdu/reg0_fast_Z[9]/Q	memq_memq_0_11/DI1	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	8.884
22	0.882	Mdu/u_mdu/reg0_fast_Z[13]/Q	Mdu/u_mdu/reg0_fast_Z[26]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	8.883
23	0.887	Mdu/u_mdu/rs1_mul_Z[5]/Q	Mdu/u_mdu/reg0_Z[38]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	8.878
24	0.887	Mdu/u_mdu/reg0_fast_Z[13]/Q	memq_memq_0_5/DI1	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	8.878
25	1.003	Mdu/u_mdu/rs1_mul_Z[5]/Q	Mdu/u_mdu/reg0_Z[40]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	8.762

Hold Paths Table

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Data Delay
1	0.213	u_la0_top/u_ao_mem_ctrl/data_reg_Z[85]/Q	u_la0_top/u_ao_mem_ctrl/mem_mem_0_42/DI1	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.462
2	0.213	u_la0_top/u_ao_mem_ctrl/data_reg_Z[84]/Q	u_la0_top/u_ao_mem_ctrl/mem_mem_0_42/DI0	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.462
3	0.225	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[10]/Q	u_la0_top/u_ao_mem_ctrl/mem_mem_0_14/ADA11	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.343
4	0.233	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[12]/Q	u_la0_top/u_ao_mem_ctrl/mem_mem_0_14/ADA13	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.351
5	0.342	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[6]/Q	u_la0_top/u_ao_mem_ctrl/mem_mem_0_14/ADA7	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.460
6	0.352	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[11]/Q	u_la0_top/u_ao_mem_ctrl/mem_mem_0_14/ADA12	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.470
7	0.354	cnt_1_Z[8]/Q	memr_memr_0_15/ADB9	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.472
8	0.354	cnt_1_Z[9]/Q	memr_memr_0_15/ADB10	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.472
9	0.359	cnt_1_Z[2]/Q	memr_memr_0_13/ADB3	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.477
10	0.361	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[1]/Q	u_la0_top/u_ao_mem_ctrl/mem_mem_0_14/ADA2	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.479
11	0.366	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0]/Q	u_la0_top/u_ao_mem_ctrl/mem_mem_0_14/ADA1	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.484
12	0.367	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[3]/Q	u_la0_top/u_ao_mem_ctrl/mem_mem_0_14/ADA4	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.485
13	0.375	u_la0_top/u_ao_mem_ctrl/data_reg_Z[55]/Q	u_la0_top/u_ao_mem_ctrl/mem_mem_0_27/DI1	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.624
14	0.421	Mdu/u_mdu/state[0]/Q	m_Z[23]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.432
15	0.427	u_la0_top/capture_window_sel_Z[0]/Q	u_la0_top/capture_window_sel_Z[0]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.438
16	0.428	divisor_1[0]/Q	divisor_1[0]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.439
17	0.428	divisor[24]/Q	divisor[24]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.439
18	0.428	dividend[30]/Q	dividend[30]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.439
19	0.428	divisor[31]/Q	divisor[31]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.439
20	0.428	divisor[30]/Q	divisor[30]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.439
21	0.429	dividend[28]/Q	dividend[28]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.440
22	0.429	divisor[27]/Q	divisor[27]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.440
23	0.429	Mdu/u_mdu/reg0_Z[54]/Q	Mdu/u_mdu/reg0_Z[54]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.440
24	0.429	divisor[26]/Q	divisor[26]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.440
25	0.432	Mdu/u_mdu/reg0_Z[50]/Q	Mdu/u_mdu/reg0_Z[50]/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.443

Recovery Paths Table

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	1.643	u_la0_top/rst_ao_Z/Q	u_la0_top/triger_level_cnt_Z[0]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	5.000	0.033	3.089
2	1.643	u_la0_top/rst_ao_Z/Q	u_la0_top/triger_level_cnt_Z[2]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	5.000	0.033	3.089
3	1.643	u_la0_top/rst_ao_Z/Q	u_la0_top/capture_window_sel[3]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	5.000	0.033	3.089
4	1.643	u_la0_top/rst_ao_Z/Q	u_la0_top/internal_reg_force_triger_syn_Z[0]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	5.000	0.033	3.089
5	1.643	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_length_Z[12]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	5.000	0.033	3.089
6	1.643	u_la0_top/rst_ao_Z/Q	u_la0_top/internal_reg_start_syn_Z[0]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	5.000	0.033	3.089
7	1.643	u_la0_top/rst_ao_Z/Q	u_la0_top/internal_reg_start_dly_Z[0]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	5.000	0.033	3.089
8	1.643	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	5.000	0.033	3.089
9	1.643	u_la0_top/rst_ao_Z/Q	u_la0_top/capture_window_sel_Z[2]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	5.000	0.033	3.089
10	1.643	u_la0_top/rst_ao_Z/Q	u_la0_top/capture_end_dly_Z/PRESET	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	5.000	0.033	3.089
11	1.643	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	5.000	0.033	3.089
12	1.643	u_la0_top/rst_ao_Z/Q	u_la0_top/capture_window_sel_Z[1]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	5.000	0.033	3.089
13	1.643	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_length_Z[4]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	5.000	0.033	3.089
14	1.643	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_length_Z[3]/PRESET	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	5.000	0.033	3.089
15	1.643	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_length_Z[9]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	5.000	0.033	3.089
16	1.643	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[12]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	5.000	0.033	3.089
17	1.643	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[2]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	5.000	0.033	3.089
18	1.643	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[1]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	5.000	0.033	3.089
19	1.643	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_length_Z[7]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	5.000	0.033	3.089
20	1.643	u_la0_top/rst_ao_Z/Q	u_la0_top/trigger_seq_start_Z/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	5.000	0.033	3.089
21	1.643	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[9]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	5.000	0.033	3.089
22	1.643	u_la0_top/rst_ao_Z/Q	u_la0_top/genblk1.u_ao_match_0/match_sep/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	5.000	0.033	3.089
23	1.643	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[3]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	5.000	0.033	3.089
24	1.643	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	5.000	0.033	3.089
25	1.643	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_length_Z[2]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	5.000	0.033	3.089

Removal Paths Table

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	6.772	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	-5.000	0.013	1.970
2	6.772	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_loop_Z/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	-5.000	0.013	1.970
3	6.772	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_length_Z[0]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	-5.000	0.013	1.970
4	6.772	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_length_Z[1]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	-5.000	0.013	1.970
5	6.772	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_length_Z[2]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	-5.000	0.013	1.970
6	6.772	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_length_Z[4]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	-5.000	0.013	1.970
7	6.772	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_length_Z[5]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	-5.000	0.013	1.970
8	6.772	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_length_Z[7]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	-5.000	0.013	1.970
9	6.772	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_length_Z[8]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	-5.000	0.013	1.970
10	6.772	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_length_Z[9]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	-5.000	0.013	1.970
11	6.772	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_length_Z[10]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	-5.000	0.013	1.970
12	6.772	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_length_Z[11]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	-5.000	0.013	1.970
13	6.772	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_length_Z[12]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	-5.000	0.013	1.970
14	6.772	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	-5.000	0.013	1.970
15	6.772	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[1]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	-5.000	0.013	1.970
16	6.772	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[2]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	-5.000	0.013	1.970
17	6.772	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[3]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	-5.000	0.013	1.970
18	6.772	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[4]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	-5.000	0.013	1.970
19	6.772	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[5]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	-5.000	0.013	1.970
20	6.772	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[6]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	-5.000	0.013	1.970
21	6.772	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[7]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	-5.000	0.013	1.970
22	6.772	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	-5.000	0.013	1.970
23	6.772	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[9]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	-5.000	0.013	1.970
24	6.772	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[10]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	-5.000	0.013	1.970
25	6.772	u_la0_top/rst_ao_Z/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[11]/CLEAR	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	-5.000	0.013	1.970

Minimum Pulse Width Table:

Report Command:report_min_pulse_width -nworst 10 -detail

Number	Slack	Actual Width	Required Width	Type	Clock	Objects
1	3.662	4.662	1.000	Low Pulse Width	DEFAULT_CLK	cnt_1_Z[12]
2	3.662	4.662	1.000	Low Pulse Width	DEFAULT_CLK	cnt_1_Z[10]
3	3.662	4.662	1.000	Low Pulse Width	DEFAULT_CLK	cnt_1_Z[6]
4	3.662	4.662	1.000	Low Pulse Width	DEFAULT_CLK	cnt_Z[11]
5	3.662	4.662	1.000	Low Pulse Width	DEFAULT_CLK	divisor[29]
6	3.662	4.662	1.000	Low Pulse Width	DEFAULT_CLK	m_Z[30]
7	3.662	4.662	1.000	Low Pulse Width	DEFAULT_CLK	memq_memq_0_15
8	3.662	4.662	1.000	Low Pulse Width	DEFAULT_CLK	Mdu/u_mdu/reg0_fast_Z[15]
9	3.662	4.662	1.000	Low Pulse Width	DEFAULT_CLK	u_la0_top/u_ao_mem_ctrl/capture_loop_Z
10	3.662	4.662	1.000	Low Pulse Width	DEFAULT_CLK	u_la0_top/u_ao_mem_ctrl/data_reg_Z[116]

Timing Report By Analysis Type:

Setup Analysis Report

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	0.056
Data Arrival Time	11.592
Data Required Time	11.648
From	Mdu/u_mdu/rs1_mul_Z[5]
To	Mdu/u_mdu/reg0_Z[7]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.683	0.683	tINS	RR	578	IOT48[A]	clk_ibuf/O
1.883	1.201	tNET	RR	1	R46C62[1][A]	Mdu/u_mdu/rs1_mul_Z[5]/CLK
2.115	0.232	tC2Q	RF	1	R46C62[1][A]	Mdu/u_mdu/rs1_mul_Z[5]/Q
3.013	0.898	tNET	FF	1	R46C62[3][B]	Mdu/u_mdu/adder_sum_s_5_sf_lofx_cZ/I2
3.568	0.555	tINS	FF	1	R46C62[3][B]	Mdu/u_mdu/adder_sum_s_5_sf_lofx_cZ/F
4.252	0.684	tNET	FF	2	R47C58[0][B]	Mdu/u_mdu/adder_sum_cry_5_0/I0
4.822	0.570	tINS	FR	1	R47C58[0][B]	Mdu/u_mdu/adder_sum_cry_5_0/COUT
4.822	0.000	tNET	RR	2	R47C58[1][A]	Mdu/u_mdu/adder_sum_cry_6_0/CIN
4.857	0.035	tINS	RF	1	R47C58[1][A]	Mdu/u_mdu/adder_sum_cry_6_0/COUT
4.857	0.000	tNET	FF	2	R47C58[1][B]	Mdu/u_mdu/adder_sum_cry_7_0/CIN
4.892	0.035	tINS	FF	1	R47C58[1][B]	Mdu/u_mdu/adder_sum_cry_7_0/COUT
4.892	0.000	tNET	FF	2	R47C58[2][A]	Mdu/u_mdu/adder_sum_cry_8_0/CIN
4.927	0.035	tINS	FF	1	R47C58[2][A]	Mdu/u_mdu/adder_sum_cry_8_0/COUT
4.927	0.000	tNET	FF	2	R47C58[2][B]	Mdu/u_mdu/adder_sum_cry_9_0/CIN
4.963	0.035	tINS	FF	1	R47C58[2][B]	Mdu/u_mdu/adder_sum_cry_9_0/COUT
4.963	0.000	tNET	FF	2	R47C59[0][A]	Mdu/u_mdu/adder_sum_cry_10_0/CIN
4.998	0.035	tINS	FF	1	R47C59[0][A]	Mdu/u_mdu/adder_sum_cry_10_0/COUT
4.998	0.000	tNET	FF	2	R47C59[0][B]	Mdu/u_mdu/adder_sum_cry_11_0/CIN
5.033	0.035	tINS	FF	1	R47C59[0][B]	Mdu/u_mdu/adder_sum_cry_11_0/COUT
5.033	0.000	tNET	FF	2	R47C59[1][A]	Mdu/u_mdu/adder_sum_cry_12_0/CIN
5.068	0.035	tINS	FF	1	R47C59[1][A]	Mdu/u_mdu/adder_sum_cry_12_0/COUT
5.068	0.000	tNET	FF	2	R47C59[1][B]	Mdu/u_mdu/adder_sum_cry_13_0/CIN
5.103	0.035	tINS	FF	1	R47C59[1][B]	Mdu/u_mdu/adder_sum_cry_13_0/COUT
5.103	0.000	tNET	FF	2	R47C59[2][A]	Mdu/u_mdu/adder_sum_cry_14_0/CIN
5.139	0.035	tINS	FF	1	R47C59[2][A]	Mdu/u_mdu/adder_sum_cry_14_0/COUT
5.139	0.000	tNET	FF	2	R47C59[2][B]	Mdu/u_mdu/adder_sum_cry_15_0/CIN
5.174	0.035	tINS	FF	1	R47C59[2][B]	Mdu/u_mdu/adder_sum_cry_15_0/COUT
5.174	0.000	tNET	FF	2	R47C60[0][A]	Mdu/u_mdu/adder_sum_cry_16_0/CIN
5.209	0.035	tINS	FF	1	R47C60[0][A]	Mdu/u_mdu/adder_sum_cry_16_0/COUT
5.209	0.000	tNET	FF	2	R47C60[0][B]	Mdu/u_mdu/adder_sum_cry_17_0/CIN
5.244	0.035	tINS	FF	1	R47C60[0][B]	Mdu/u_mdu/adder_sum_cry_17_0/COUT
5.244	0.000	tNET	FF	2	R47C60[1][A]	Mdu/u_mdu/adder_sum_cry_18_0/CIN
5.279	0.035	tINS	FF	1	R47C60[1][A]	Mdu/u_mdu/adder_sum_cry_18_0/COUT
5.279	0.000	tNET	FF	2	R47C60[1][B]	Mdu/u_mdu/adder_sum_cry_19_0/CIN
5.315	0.035	tINS	FF	1	R47C60[1][B]	Mdu/u_mdu/adder_sum_cry_19_0/COUT
5.315	0.000	tNET	FF	2	R47C60[2][A]	Mdu/u_mdu/adder_sum_cry_20_0/CIN
5.350	0.035	tINS	FF	1	R47C60[2][A]	Mdu/u_mdu/adder_sum_cry_20_0/COUT
5.350	0.000	tNET	FF	2	R47C60[2][B]	Mdu/u_mdu/adder_sum_cry_21_0/CIN
5.385	0.035	tINS	FF	1	R47C60[2][B]	Mdu/u_mdu/adder_sum_cry_21_0/COUT
5.385	0.000	tNET	FF	2	R47C61[0][A]	Mdu/u_mdu/adder_sum_cry_22_0/CIN
5.420	0.035	tINS	FF	1	R47C61[0][A]	Mdu/u_mdu/adder_sum_cry_22_0/COUT
5.420	0.000	tNET	FF	2	R47C61[0][B]	Mdu/u_mdu/adder_sum_cry_23_0/CIN
5.455	0.035	tINS	FF	1	R47C61[0][B]	Mdu/u_mdu/adder_sum_cry_23_0/COUT
5.455	0.000	tNET	FF	2	R47C61[1][A]	Mdu/u_mdu/adder_sum_cry_24_0/CIN
5.491	0.035	tINS	FF	1	R47C61[1][A]	Mdu/u_mdu/adder_sum_cry_24_0/COUT
5.491	0.000	tNET	FF	2	R47C61[1][B]	Mdu/u_mdu/adder_sum_cry_25_0/CIN
5.526	0.035	tINS	FF	1	R47C61[1][B]	Mdu/u_mdu/adder_sum_cry_25_0/COUT
5.526	0.000	tNET	FF	2	R47C61[2][A]	Mdu/u_mdu/adder_sum_cry_26_0/CIN
5.561	0.035	tINS	FF	1	R47C61[2][A]	Mdu/u_mdu/adder_sum_cry_26_0/COUT
5.561	0.000	tNET	FF	2	R47C61[2][B]	Mdu/u_mdu/adder_sum_cry_27_0/CIN
5.596	0.035	tINS	FF	1	R47C61[2][B]	Mdu/u_mdu/adder_sum_cry_27_0/COUT
5.596	0.000	tNET	FF	2	R47C62[0][A]	Mdu/u_mdu/adder_sum_cry_28_0/CIN
5.631	0.035	tINS	FF	1	R47C62[0][A]	Mdu/u_mdu/adder_sum_cry_28_0/COUT
5.631	0.000	tNET	FF	2	R47C62[0][B]	Mdu/u_mdu/adder_sum_cry_29_0/CIN
5.667	0.035	tINS	FF	1	R47C62[0][B]	Mdu/u_mdu/adder_sum_cry_29_0/COUT
5.667	0.000	tNET	FF	2	R47C62[1][A]	Mdu/u_mdu/adder_sum_cry_30_0/CIN
5.702	0.035	tINS	FF	1	R47C62[1][A]	Mdu/u_mdu/adder_sum_cry_30_0/COUT
5.702	0.000	tNET	FF	2	R47C62[1][B]	Mdu/u_mdu/adder_sum_cry_31_0/CIN
5.737	0.035	tINS	FF	1	R47C62[1][B]	Mdu/u_mdu/adder_sum_cry_31_0/COUT
5.737	0.000	tNET	FF	2	R47C62[2][A]	Mdu/u_mdu/adder_sum_s_32_0/CIN
6.207	0.470	tINS	FF	6	R47C62[2][A]	Mdu/u_mdu/adder_sum_s_32_0/SUM
7.175	0.968	tNET	FF	1	R37C55[1][B]	Mdu/u_mdu/reg0_exe_nx_ss0_cZ/I0
7.692	0.517	tINS	FF	50	R37C55[1][B]	Mdu/u_mdu/reg0_exe_nx_ss0_cZ/F
8.658	0.966	tNET	FF	1	R32C58[3][A]	Mdu/u_mdu/reg0_exe_nx_m1_cZ[7]/I3
9.029	0.371	tINS	FF	1	R32C58[3][A]	Mdu/u_mdu/reg0_exe_nx_m1_cZ[7]/F
9.519	0.490	tNET	FF	1	R32C54[3][A]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[7]/I1
9.972	0.453	tINS	FF	1	R32C54[3][A]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[7]/F
10.580	0.607	tNET	FF	1	R39C54[3][B]	Mdu/u_mdu/reg0_exe_nx_cZ[7]/I3
11.042	0.462	tINS	FR	1	R39C54[3][B]	Mdu/u_mdu/reg0_exe_nx_cZ[7]/F
11.043	0.001	tNET	RR	1	R39C54[0][A]	Mdu/u_mdu/reg0_nx_cZ[7]/I0
11.592	0.549	tINS	RR	1	R39C54[0][A]	Mdu/u_mdu/reg0_nx_cZ[7]/F
11.592	0.000	tNET	RR	1	R39C54[0][A]	Mdu/u_mdu/reg0_Z[7]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	578	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R39C54[0][A]	Mdu/u_mdu/reg0_Z[7]/CLK
11.683	-0.200	tUnc				Mdu/u_mdu/reg0_Z[7]
11.648	-0.035	tSu		1	R39C54[0][A]	Mdu/u_mdu/reg0_Z[7]

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	8
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 4.862, 50.081%; route: 4.614, 47.529%; tC2Q: 0.232, 2.390%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path2

Path Summary:

Slack	0.180
Data Arrival Time	11.468
Data Required Time	11.648
From	Mdu/u_mdu/reg0_fast_Z[13]
To	memq_memq_0_10
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.683	0.683	tINS	RR	578	IOT48[A]	clk_ibuf/O
1.883	1.201	tNET	RR	1	R38C59[1][A]	Mdu/u_mdu/reg0_fast_Z[13]/CLK
2.115	0.232	tC2Q	RF	8	R38C59[1][A]	Mdu/u_mdu/reg0_fast_Z[13]/Q
3.360	1.245	tNET	FF	1	R51C56[1][B]	Mdu/u_mdu/reg0_neg_axb_12_par_0_cp_cZ/I1
3.915	0.555	tINS	FF	1	R51C56[1][B]	Mdu/u_mdu/reg0_neg_axb_12_par_0_cp_cZ/F
4.814	0.899	tNET	FF	2	R52C56[2][B]	Mdu/u_mdu/reg0_neg_axb_12_par_cp_1/I0
5.384	0.570	tINS	FR	1	R52C56[2][B]	Mdu/u_mdu/reg0_neg_axb_12_par_cp_1/COUT
5.384	0.000	tNET	RR	2	R52C57[0][A]	Mdu/u_mdu/reg0_neg_axb_16_par_cp_1/CIN
5.419	0.035	tINS	RF	1	R52C57[0][A]	Mdu/u_mdu/reg0_neg_axb_16_par_cp_1/COUT
5.419	0.000	tNET	FF	2	R52C57[0][B]	Mdu/u_mdu/reg0_neg_axb_19_par_1/CIN
5.454	0.035	tINS	FF	1	R52C57[0][B]	Mdu/u_mdu/reg0_neg_axb_19_par_1/COUT
5.454	0.000	tNET	FF	2	R52C57[1][A]	Mdu/u_mdu/reg0_neg_axb_23_par_1/CIN
5.490	0.035	tINS	FF	1	R52C57[1][A]	Mdu/u_mdu/reg0_neg_axb_23_par_1/COUT
5.490	0.000	tNET	FF	2	R52C57[1][B]	Mdu/u_mdu/reg0_neg_axb_27_par_1/CIN
5.525	0.035	tINS	FF	1	R52C57[1][B]	Mdu/u_mdu/reg0_neg_axb_27_par_1/COUT
5.525	0.000	tNET	FF	2	R52C57[2][A]	Mdu/u_mdu/reg0_neg_axb_31_par_1/CIN
5.560	0.035	tINS	FF	1	R52C57[2][A]	Mdu/u_mdu/reg0_neg_axb_31_par_1/COUT
5.560	0.000	tNET	FF	2	R52C57[2][B]	Mdu/u_mdu/reg0_neg_cry_34_0/CIN
5.595	0.035	tINS	FF	1	R52C57[2][B]	Mdu/u_mdu/reg0_neg_cry_34_0/COUT
5.595	0.000	tNET	FF	2	R52C58[0][A]	Mdu/u_mdu/reg0_neg_cry_35_0/CIN
5.630	0.035	tINS	FF	1	R52C58[0][A]	Mdu/u_mdu/reg0_neg_cry_35_0/COUT
5.630	0.000	tNET	FF	2	R52C58[0][B]	Mdu/u_mdu/reg0_neg_cry_36_0/CIN
5.666	0.035	tINS	FF	1	R52C58[0][B]	Mdu/u_mdu/reg0_neg_cry_36_0/COUT
5.666	0.000	tNET	FF	2	R52C58[1][A]	Mdu/u_mdu/reg0_neg_cry_37_0/CIN
5.701	0.035	tINS	FF	1	R52C58[1][A]	Mdu/u_mdu/reg0_neg_cry_37_0/COUT
5.701	0.000	tNET	FF	2	R52C58[1][B]	Mdu/u_mdu/reg0_neg_cry_38_0/CIN
5.736	0.035	tINS	FF	1	R52C58[1][B]	Mdu/u_mdu/reg0_neg_cry_38_0/COUT
5.736	0.000	tNET	FF	2	R52C58[2][A]	Mdu/u_mdu/reg0_neg_cry_39_0/CIN
5.771	0.035	tINS	FF	1	R52C58[2][A]	Mdu/u_mdu/reg0_neg_cry_39_0/COUT
5.771	0.000	tNET	FF	2	R52C58[2][B]	Mdu/u_mdu/reg0_neg_cry_40_0/CIN
5.806	0.035	tINS	FF	1	R52C58[2][B]	Mdu/u_mdu/reg0_neg_cry_40_0/COUT
5.806	0.000	tNET	FF	2	R52C59[0][A]	Mdu/u_mdu/reg0_neg_cry_41_0/CIN
5.842	0.035	tINS	FF	1	R52C59[0][A]	Mdu/u_mdu/reg0_neg_cry_41_0/COUT
5.842	0.000	tNET	FF	2	R52C59[0][B]	Mdu/u_mdu/reg0_neg_cry_42_0/CIN
5.877	0.035	tINS	FF	1	R52C59[0][B]	Mdu/u_mdu/reg0_neg_cry_42_0/COUT
5.877	0.000	tNET	FF	2	R52C59[1][A]	Mdu/u_mdu/reg0_neg_cry_43_0/CIN
5.912	0.035	tINS	FF	1	R52C59[1][A]	Mdu/u_mdu/reg0_neg_cry_43_0/COUT
5.912	0.000	tNET	FF	2	R52C59[1][B]	Mdu/u_mdu/reg0_neg_cry_44_0/CIN
5.947	0.035	tINS	FF	1	R52C59[1][B]	Mdu/u_mdu/reg0_neg_cry_44_0/COUT
5.947	0.000	tNET	FF	2	R52C59[2][A]	Mdu/u_mdu/reg0_neg_cry_45_0/CIN
5.982	0.035	tINS	FF	1	R52C59[2][A]	Mdu/u_mdu/reg0_neg_cry_45_0/COUT
5.982	0.000	tNET	FF	2	R52C59[2][B]	Mdu/u_mdu/reg0_neg_cry_46_0/CIN
6.018	0.035	tINS	FF	1	R52C59[2][B]	Mdu/u_mdu/reg0_neg_cry_46_0/COUT
6.018	0.000	tNET	FF	2	R52C60[0][A]	Mdu/u_mdu/reg0_neg_cry_47_0/CIN
6.053	0.035	tINS	FF	1	R52C60[0][A]	Mdu/u_mdu/reg0_neg_cry_47_0/COUT
6.053	0.000	tNET	FF	2	R52C60[0][B]	Mdu/u_mdu/reg0_neg_cry_48_0/CIN
6.088	0.035	tINS	FF	1	R52C60[0][B]	Mdu/u_mdu/reg0_neg_cry_48_0/COUT
6.088	0.000	tNET	FF	2	R52C60[1][A]	Mdu/u_mdu/reg0_neg_cry_49_0/CIN
6.123	0.035	tINS	FF	1	R52C60[1][A]	Mdu/u_mdu/reg0_neg_cry_49_0/COUT
6.123	0.000	tNET	FF	2	R52C60[1][B]	Mdu/u_mdu/reg0_neg_cry_50_0/CIN
6.158	0.035	tINS	FF	1	R52C60[1][B]	Mdu/u_mdu/reg0_neg_cry_50_0/COUT
6.158	0.000	tNET	FF	2	R52C60[2][A]	Mdu/u_mdu/reg0_neg_cry_51_0/CIN
6.194	0.035	tINS	FF	1	R52C60[2][A]	Mdu/u_mdu/reg0_neg_cry_51_0/COUT
6.194	0.000	tNET	FF	2	R52C60[2][B]	Mdu/u_mdu/reg0_neg_cry_52_0/CIN
6.229	0.035	tINS	FF	1	R52C60[2][B]	Mdu/u_mdu/reg0_neg_cry_52_0/COUT
6.229	0.000	tNET	FF	2	R52C61[0][A]	Mdu/u_mdu/reg0_neg_s_53_0/CIN
6.699	0.470	tINS	FF	1	R52C61[0][A]	Mdu/u_mdu/reg0_neg_s_53_0/SUM
7.367	0.668	tNET	FF	1	R52C55[3][A]	Mdu/u_mdu/reg0_post_swap_2[21]/I2
7.884	0.517	tINS	FF	1	R52C55[3][A]	Mdu/u_mdu/reg0_post_swap_2[21]/F
7.884	0.000	tNET	FF	1	R52C55[3][A]	Mdu/u_mdu/reg0_post_swap_4[21]/I0
7.987	0.103	tINS	FF	1	R52C55[3][A]	Mdu/u_mdu/reg0_post_swap_4[21]/O
8.632	0.645	tNET	FF	1	R48C55[2][A]	Mdu/u_mdu/reg0_post_swap_5[21]/I1
9.149	0.517	tINS	FF	2	R48C55[2][A]	Mdu/u_mdu/reg0_post_swap_5[21]/F
9.672	0.522	tNET	FF	1	R38C55[2][B]	Mdu/u_mdu/res0_cZ[21]/I1
10.043	0.371	tINS	FF	3	R38C55[2][B]	Mdu/u_mdu/res0_cZ[21]/F
11.468	1.426	tNET	FF	1	BSRAM_R45[17]	memq_memq_0_10/DI1

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	578	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	BSRAM_R45[17]	memq_memq_0_10/CLKA
11.683	-0.200	tUnc				memq_memq_0_10
11.648	-0.035	tSu		1	BSRAM_R45[17]	memq_memq_0_10

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 3.948, 41.187%; route: 5.405, 56.393%; tC2Q: 0.232, 2.420%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path3

Path Summary:

Slack	0.320
Data Arrival Time	11.328
Data Required Time	11.648
From	Mdu/u_mdu/reg0_fast_Z[13]
To	memq_memq_0_15
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.683	0.683	tINS	RR	578	IOT48[A]	clk_ibuf/O
1.883	1.201	tNET	RR	1	R38C59[1][A]	Mdu/u_mdu/reg0_fast_Z[13]/CLK
2.115	0.232	tC2Q	RF	8	R38C59[1][A]	Mdu/u_mdu/reg0_fast_Z[13]/Q
3.516	1.401	tNET	FF	1	R51C54[3][B]	Mdu/u_mdu/reg0_neg_axb_12_par_0_cp_0_cZ/I1
4.033	0.517	tINS	FF	1	R51C54[3][B]	Mdu/u_mdu/reg0_neg_axb_12_par_0_cp_0_cZ/F
4.960	0.927	tNET	FF	2	R56C51[2][B]	Mdu/u_mdu/reg0_neg_axb_12_par_cp_0_0/I0
5.530	0.570	tINS	FR	1	R56C51[2][B]	Mdu/u_mdu/reg0_neg_axb_12_par_cp_0_0/COUT
5.530	0.000	tNET	RR	2	R56C52[0][A]	Mdu/u_mdu/reg0_neg_axb_16_par_cp_0_0/CIN
5.565	0.035	tINS	RF	1	R56C52[0][A]	Mdu/u_mdu/reg0_neg_axb_16_par_cp_0_0/COUT
5.565	0.000	tNET	FF	2	R56C52[0][B]	Mdu/u_mdu/reg0_neg_axb_19_par_cp_0/CIN
5.600	0.035	tINS	FF	1	R56C52[0][B]	Mdu/u_mdu/reg0_neg_axb_19_par_cp_0/COUT
5.600	0.000	tNET	FF	2	R56C52[1][A]	Mdu/u_mdu/reg0_neg_axb_23_par_cp_0/CIN
5.635	0.035	tINS	FF	1	R56C52[1][A]	Mdu/u_mdu/reg0_neg_axb_23_par_cp_0/COUT
5.635	0.000	tNET	FF	2	R56C52[1][B]	Mdu/u_mdu/reg0_neg_axb_27_par_cp_0/CIN
5.671	0.035	tINS	FF	1	R56C52[1][B]	Mdu/u_mdu/reg0_neg_axb_27_par_cp_0/COUT
5.671	0.000	tNET	FF	2	R56C52[2][A]	Mdu/u_mdu/reg0_neg_axb_31_par_cp_0/CIN
5.706	0.035	tINS	FF	1	R56C52[2][A]	Mdu/u_mdu/reg0_neg_axb_31_par_cp_0/COUT
5.706	0.000	tNET	FF	2	R56C52[2][B]	Mdu/u_mdu/reg0_neg_axb_34_par_1/CIN
5.741	0.035	tINS	FF	1	R56C52[2][B]	Mdu/u_mdu/reg0_neg_axb_34_par_1/COUT
5.741	0.000	tNET	FF	2	R56C53[0][A]	Mdu/u_mdu/reg0_neg_axb_38_par_1/CIN
5.776	0.035	tINS	FF	1	R56C53[0][A]	Mdu/u_mdu/reg0_neg_axb_38_par_1/COUT
5.776	0.000	tNET	FF	2	R56C53[0][B]	Mdu/u_mdu/reg0_neg_axb_42_par_1/CIN
5.811	0.035	tINS	FF	1	R56C53[0][B]	Mdu/u_mdu/reg0_neg_axb_42_par_1/COUT
5.811	0.000	tNET	FF	2	R56C53[1][A]	Mdu/u_mdu/reg0_neg_axb_46_par_1/CIN
5.847	0.035	tINS	FF	1	R56C53[1][A]	Mdu/u_mdu/reg0_neg_axb_46_par_1/COUT
5.847	0.000	tNET	FF	2	R56C53[1][B]	Mdu/u_mdu/reg0_neg_axb_50_par_1/CIN
5.882	0.035	tINS	FF	1	R56C53[1][B]	Mdu/u_mdu/reg0_neg_axb_50_par_1/COUT
5.882	0.000	tNET	FF	2	R56C53[2][A]	Mdu/u_mdu/reg0_neg_cry_54_0/CIN
5.917	0.035	tINS	FF	1	R56C53[2][A]	Mdu/u_mdu/reg0_neg_cry_54_0/COUT
5.917	0.000	tNET	FF	2	R56C53[2][B]	Mdu/u_mdu/reg0_neg_cry_55_0/CIN
5.952	0.035	tINS	FF	1	R56C53[2][B]	Mdu/u_mdu/reg0_neg_cry_55_0/COUT
5.952	0.000	tNET	FF	2	R56C54[0][A]	Mdu/u_mdu/reg0_neg_cry_56_0/CIN
5.987	0.035	tINS	FF	1	R56C54[0][A]	Mdu/u_mdu/reg0_neg_cry_56_0/COUT
5.987	0.000	tNET	FF	2	R56C54[0][B]	Mdu/u_mdu/reg0_neg_cry_57_0/CIN
6.023	0.035	tINS	FF	1	R56C54[0][B]	Mdu/u_mdu/reg0_neg_cry_57_0/COUT
6.023	0.000	tNET	FF	2	R56C54[1][A]	Mdu/u_mdu/reg0_neg_cry_58_0/CIN
6.058	0.035	tINS	FF	1	R56C54[1][A]	Mdu/u_mdu/reg0_neg_cry_58_0/COUT
6.058	0.000	tNET	FF	2	R56C54[1][B]	Mdu/u_mdu/reg0_neg_cry_59_0/CIN
6.093	0.035	tINS	FF	1	R56C54[1][B]	Mdu/u_mdu/reg0_neg_cry_59_0/COUT
6.093	0.000	tNET	FF	2	R56C54[2][A]	Mdu/u_mdu/reg0_neg_cry_60_0/CIN
6.128	0.035	tINS	FF	1	R56C54[2][A]	Mdu/u_mdu/reg0_neg_cry_60_0/COUT
6.128	0.000	tNET	FF	2	R56C54[2][B]	Mdu/u_mdu/reg0_neg_cry_61_0/CIN
6.163	0.035	tINS	FF	1	R56C54[2][B]	Mdu/u_mdu/reg0_neg_cry_61_0/COUT
6.163	0.000	tNET	FF	2	R56C55[0][A]	Mdu/u_mdu/reg0_neg_cry_62_0/CIN
6.199	0.035	tINS	FF	1	R56C55[0][A]	Mdu/u_mdu/reg0_neg_cry_62_0/COUT
6.199	0.000	tNET	FF	2	R56C55[0][B]	Mdu/u_mdu/reg0_neg_s_63_0/CIN
6.669	0.470	tINS	FF	1	R56C55[0][B]	Mdu/u_mdu/reg0_neg_s_63_0/SUM
7.595	0.927	tNET	FF	1	R50C58[3][A]	Mdu/u_mdu/reg0_post_swap_2[31]/I2
8.150	0.555	tINS	FF	1	R50C58[3][A]	Mdu/u_mdu/reg0_post_swap_2[31]/F
8.150	0.000	tNET	FF	1	R50C58[3][A]	Mdu/u_mdu/reg0_post_swap_4[31]/I0
8.253	0.103	tINS	FF	2	R50C58[3][A]	Mdu/u_mdu/reg0_post_swap_4[31]/O
8.512	0.259	tNET	FF	1	R48C58[0][A]	Mdu/u_mdu/reg0_post_swap_5[31]/I1
8.965	0.453	tINS	FF	1	R48C58[0][A]	Mdu/u_mdu/reg0_post_swap_5[31]/F
9.771	0.806	tNET	FF	1	R43C58[0][A]	Mdu/u_mdu/res0_cZ[31]/I1
10.288	0.517	tINS	FF	3	R43C58[0][A]	Mdu/u_mdu/res0_cZ[31]/F
11.328	1.040	tNET	FF	1	BSRAM_R36[21]	memq_memq_0_15/DI1

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	578	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	BSRAM_R36[21]	memq_memq_0_15/CLKA
11.683	-0.200	tUnc				memq_memq_0_15
11.648	-0.035	tSu		1	BSRAM_R36[21]	memq_memq_0_15

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 3.854, 40.803%; route: 5.359, 56.741%; tC2Q: 0.232, 2.456%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path4

Path Summary:

Slack	0.348
Data Arrival Time	11.300
Data Required Time	11.648
From	Mdu/u_mdu/rs1_mul_Z[5]
To	Mdu/u_mdu/reg0_Z[37]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.683	0.683	tINS	RR	578	IOT48[A]	clk_ibuf/O
1.883	1.201	tNET	RR	1	R46C62[1][A]	Mdu/u_mdu/rs1_mul_Z[5]/CLK
2.115	0.232	tC2Q	RF	1	R46C62[1][A]	Mdu/u_mdu/rs1_mul_Z[5]/Q
3.013	0.898	tNET	FF	1	R46C62[3][B]	Mdu/u_mdu/adder_sum_s_5_sf_lofx_cZ/I2
3.568	0.555	tINS	FF	1	R46C62[3][B]	Mdu/u_mdu/adder_sum_s_5_sf_lofx_cZ/F
4.252	0.684	tNET	FF	2	R47C58[0][B]	Mdu/u_mdu/adder_sum_cry_5_0/I0
4.822	0.570	tINS	FR	1	R47C58[0][B]	Mdu/u_mdu/adder_sum_cry_5_0/COUT
4.822	0.000	tNET	RR	2	R47C58[1][A]	Mdu/u_mdu/adder_sum_cry_6_0/CIN
4.857	0.035	tINS	RF	1	R47C58[1][A]	Mdu/u_mdu/adder_sum_cry_6_0/COUT
4.857	0.000	tNET	FF	2	R47C58[1][B]	Mdu/u_mdu/adder_sum_cry_7_0/CIN
4.892	0.035	tINS	FF	1	R47C58[1][B]	Mdu/u_mdu/adder_sum_cry_7_0/COUT
4.892	0.000	tNET	FF	2	R47C58[2][A]	Mdu/u_mdu/adder_sum_cry_8_0/CIN
4.927	0.035	tINS	FF	1	R47C58[2][A]	Mdu/u_mdu/adder_sum_cry_8_0/COUT
4.927	0.000	tNET	FF	2	R47C58[2][B]	Mdu/u_mdu/adder_sum_cry_9_0/CIN
4.963	0.035	tINS	FF	1	R47C58[2][B]	Mdu/u_mdu/adder_sum_cry_9_0/COUT
4.963	0.000	tNET	FF	2	R47C59[0][A]	Mdu/u_mdu/adder_sum_cry_10_0/CIN
4.998	0.035	tINS	FF	1	R47C59[0][A]	Mdu/u_mdu/adder_sum_cry_10_0/COUT
4.998	0.000	tNET	FF	2	R47C59[0][B]	Mdu/u_mdu/adder_sum_cry_11_0/CIN
5.033	0.035	tINS	FF	1	R47C59[0][B]	Mdu/u_mdu/adder_sum_cry_11_0/COUT
5.033	0.000	tNET	FF	2	R47C59[1][A]	Mdu/u_mdu/adder_sum_cry_12_0/CIN
5.068	0.035	tINS	FF	1	R47C59[1][A]	Mdu/u_mdu/adder_sum_cry_12_0/COUT
5.068	0.000	tNET	FF	2	R47C59[1][B]	Mdu/u_mdu/adder_sum_cry_13_0/CIN
5.103	0.035	tINS	FF	1	R47C59[1][B]	Mdu/u_mdu/adder_sum_cry_13_0/COUT
5.103	0.000	tNET	FF	2	R47C59[2][A]	Mdu/u_mdu/adder_sum_cry_14_0/CIN
5.139	0.035	tINS	FF	1	R47C59[2][A]	Mdu/u_mdu/adder_sum_cry_14_0/COUT
5.139	0.000	tNET	FF	2	R47C59[2][B]	Mdu/u_mdu/adder_sum_cry_15_0/CIN
5.174	0.035	tINS	FF	1	R47C59[2][B]	Mdu/u_mdu/adder_sum_cry_15_0/COUT
5.174	0.000	tNET	FF	2	R47C60[0][A]	Mdu/u_mdu/adder_sum_cry_16_0/CIN
5.209	0.035	tINS	FF	1	R47C60[0][A]	Mdu/u_mdu/adder_sum_cry_16_0/COUT
5.209	0.000	tNET	FF	2	R47C60[0][B]	Mdu/u_mdu/adder_sum_cry_17_0/CIN
5.244	0.035	tINS	FF	1	R47C60[0][B]	Mdu/u_mdu/adder_sum_cry_17_0/COUT
5.244	0.000	tNET	FF	2	R47C60[1][A]	Mdu/u_mdu/adder_sum_cry_18_0/CIN
5.279	0.035	tINS	FF	1	R47C60[1][A]	Mdu/u_mdu/adder_sum_cry_18_0/COUT
5.279	0.000	tNET	FF	2	R47C60[1][B]	Mdu/u_mdu/adder_sum_cry_19_0/CIN
5.315	0.035	tINS	FF	1	R47C60[1][B]	Mdu/u_mdu/adder_sum_cry_19_0/COUT
5.315	0.000	tNET	FF	2	R47C60[2][A]	Mdu/u_mdu/adder_sum_cry_20_0/CIN
5.350	0.035	tINS	FF	1	R47C60[2][A]	Mdu/u_mdu/adder_sum_cry_20_0/COUT
5.350	0.000	tNET	FF	2	R47C60[2][B]	Mdu/u_mdu/adder_sum_cry_21_0/CIN
5.385	0.035	tINS	FF	1	R47C60[2][B]	Mdu/u_mdu/adder_sum_cry_21_0/COUT
5.385	0.000	tNET	FF	2	R47C61[0][A]	Mdu/u_mdu/adder_sum_cry_22_0/CIN
5.420	0.035	tINS	FF	1	R47C61[0][A]	Mdu/u_mdu/adder_sum_cry_22_0/COUT
5.420	0.000	tNET	FF	2	R47C61[0][B]	Mdu/u_mdu/adder_sum_cry_23_0/CIN
5.455	0.035	tINS	FF	1	R47C61[0][B]	Mdu/u_mdu/adder_sum_cry_23_0/COUT
5.455	0.000	tNET	FF	2	R47C61[1][A]	Mdu/u_mdu/adder_sum_cry_24_0/CIN
5.491	0.035	tINS	FF	1	R47C61[1][A]	Mdu/u_mdu/adder_sum_cry_24_0/COUT
5.491	0.000	tNET	FF	2	R47C61[1][B]	Mdu/u_mdu/adder_sum_cry_25_0/CIN
5.526	0.035	tINS	FF	1	R47C61[1][B]	Mdu/u_mdu/adder_sum_cry_25_0/COUT
5.526	0.000	tNET	FF	2	R47C61[2][A]	Mdu/u_mdu/adder_sum_cry_26_0/CIN
5.561	0.035	tINS	FF	1	R47C61[2][A]	Mdu/u_mdu/adder_sum_cry_26_0/COUT
5.561	0.000	tNET	FF	2	R47C61[2][B]	Mdu/u_mdu/adder_sum_cry_27_0/CIN
5.596	0.035	tINS	FF	1	R47C61[2][B]	Mdu/u_mdu/adder_sum_cry_27_0/COUT
5.596	0.000	tNET	FF	2	R47C62[0][A]	Mdu/u_mdu/adder_sum_cry_28_0/CIN
5.631	0.035	tINS	FF	1	R47C62[0][A]	Mdu/u_mdu/adder_sum_cry_28_0/COUT
5.631	0.000	tNET	FF	2	R47C62[0][B]	Mdu/u_mdu/adder_sum_cry_29_0/CIN
5.667	0.035	tINS	FF	1	R47C62[0][B]	Mdu/u_mdu/adder_sum_cry_29_0/COUT
5.667	0.000	tNET	FF	2	R47C62[1][A]	Mdu/u_mdu/adder_sum_cry_30_0/CIN
5.702	0.035	tINS	FF	1	R47C62[1][A]	Mdu/u_mdu/adder_sum_cry_30_0/COUT
5.702	0.000	tNET	FF	2	R47C62[1][B]	Mdu/u_mdu/adder_sum_cry_31_0/CIN
5.737	0.035	tINS	FF	1	R47C62[1][B]	Mdu/u_mdu/adder_sum_cry_31_0/COUT
5.737	0.000	tNET	FF	2	R47C62[2][A]	Mdu/u_mdu/adder_sum_s_32_0/CIN
6.207	0.470	tINS	FF	6	R47C62[2][A]	Mdu/u_mdu/adder_sum_s_32_0/SUM
7.175	0.968	tNET	FF	1	R37C55[1][B]	Mdu/u_mdu/reg0_exe_nx_ss0_cZ/I0
7.692	0.517	tINS	FF	50	R37C55[1][B]	Mdu/u_mdu/reg0_exe_nx_ss0_cZ/F
8.636	0.944	tNET	FF	1	R34C58[0][A]	Mdu/u_mdu/reg0_exe_nx_m0_cZ[37]/I2
9.153	0.517	tINS	FF	1	R34C58[0][A]	Mdu/u_mdu/reg0_exe_nx_m0_cZ[37]/F
9.153	0.000	tNET	FF	1	R34C58[0][A]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[37]/I0
9.256	0.103	tINS	FF	1	R34C58[0][A]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[37]/O
10.730	1.474	tNET	FF	1	R53C64[0][A]	Mdu/u_mdu/reg0_nx_cZ[37]/I0
11.300	0.570	tINS	FR	1	R53C64[0][A]	Mdu/u_mdu/reg0_nx_cZ[37]/F
11.300	0.000	tNET	RR	1	R53C64[0][A]	Mdu/u_mdu/reg0_Z[37]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	578	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R53C64[0][A]	Mdu/u_mdu/reg0_Z[37]/CLK
11.683	-0.200	tUnc				Mdu/u_mdu/reg0_Z[37]
11.648	-0.035	tSu		1	R53C64[0][A]	Mdu/u_mdu/reg0_Z[37]

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 4.217, 44.783%; route: 4.968, 52.754%; tC2Q: 0.232, 2.464%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path5

Path Summary:

Slack	0.371
Data Arrival Time	11.277
Data Required Time	11.648
From	Mdu/u_mdu/reg0_fast_Z[13]
To	memq_memq_0_14
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.683	0.683	tINS	RR	578	IOT48[A]	clk_ibuf/O
1.883	1.201	tNET	RR	1	R38C59[1][A]	Mdu/u_mdu/reg0_fast_Z[13]/CLK
2.115	0.232	tC2Q	RF	8	R38C59[1][A]	Mdu/u_mdu/reg0_fast_Z[13]/Q
3.516	1.401	tNET	FF	1	R51C54[3][B]	Mdu/u_mdu/reg0_neg_axb_12_par_0_cp_0_cZ/I1
4.033	0.517	tINS	FF	1	R51C54[3][B]	Mdu/u_mdu/reg0_neg_axb_12_par_0_cp_0_cZ/F
4.960	0.927	tNET	FF	2	R56C51[2][B]	Mdu/u_mdu/reg0_neg_axb_12_par_cp_0_0/I0
5.530	0.570	tINS	FR	1	R56C51[2][B]	Mdu/u_mdu/reg0_neg_axb_12_par_cp_0_0/COUT
5.530	0.000	tNET	RR	2	R56C52[0][A]	Mdu/u_mdu/reg0_neg_axb_16_par_cp_0_0/CIN
5.565	0.035	tINS	RF	1	R56C52[0][A]	Mdu/u_mdu/reg0_neg_axb_16_par_cp_0_0/COUT
5.565	0.000	tNET	FF	2	R56C52[0][B]	Mdu/u_mdu/reg0_neg_axb_19_par_cp_0/CIN
5.600	0.035	tINS	FF	1	R56C52[0][B]	Mdu/u_mdu/reg0_neg_axb_19_par_cp_0/COUT
5.600	0.000	tNET	FF	2	R56C52[1][A]	Mdu/u_mdu/reg0_neg_axb_23_par_cp_0/CIN
5.635	0.035	tINS	FF	1	R56C52[1][A]	Mdu/u_mdu/reg0_neg_axb_23_par_cp_0/COUT
5.635	0.000	tNET	FF	2	R56C52[1][B]	Mdu/u_mdu/reg0_neg_axb_27_par_cp_0/CIN
5.671	0.035	tINS	FF	1	R56C52[1][B]	Mdu/u_mdu/reg0_neg_axb_27_par_cp_0/COUT
5.671	0.000	tNET	FF	2	R56C52[2][A]	Mdu/u_mdu/reg0_neg_axb_31_par_cp_0/CIN
5.706	0.035	tINS	FF	1	R56C52[2][A]	Mdu/u_mdu/reg0_neg_axb_31_par_cp_0/COUT
5.706	0.000	tNET	FF	2	R56C52[2][B]	Mdu/u_mdu/reg0_neg_axb_34_par_1/CIN
5.741	0.035	tINS	FF	1	R56C52[2][B]	Mdu/u_mdu/reg0_neg_axb_34_par_1/COUT
5.741	0.000	tNET	FF	2	R56C53[0][A]	Mdu/u_mdu/reg0_neg_axb_38_par_1/CIN
5.776	0.035	tINS	FF	1	R56C53[0][A]	Mdu/u_mdu/reg0_neg_axb_38_par_1/COUT
5.776	0.000	tNET	FF	2	R56C53[0][B]	Mdu/u_mdu/reg0_neg_axb_42_par_1/CIN
5.811	0.035	tINS	FF	1	R56C53[0][B]	Mdu/u_mdu/reg0_neg_axb_42_par_1/COUT
5.811	0.000	tNET	FF	2	R56C53[1][A]	Mdu/u_mdu/reg0_neg_axb_46_par_1/CIN
5.847	0.035	tINS	FF	1	R56C53[1][A]	Mdu/u_mdu/reg0_neg_axb_46_par_1/COUT
5.847	0.000	tNET	FF	2	R56C53[1][B]	Mdu/u_mdu/reg0_neg_axb_50_par_1/CIN
5.882	0.035	tINS	FF	1	R56C53[1][B]	Mdu/u_mdu/reg0_neg_axb_50_par_1/COUT
5.882	0.000	tNET	FF	2	R56C53[2][A]	Mdu/u_mdu/reg0_neg_cry_54_0/CIN
5.917	0.035	tINS	FF	1	R56C53[2][A]	Mdu/u_mdu/reg0_neg_cry_54_0/COUT
5.917	0.000	tNET	FF	2	R56C53[2][B]	Mdu/u_mdu/reg0_neg_cry_55_0/CIN
5.952	0.035	tINS	FF	1	R56C53[2][B]	Mdu/u_mdu/reg0_neg_cry_55_0/COUT
5.952	0.000	tNET	FF	2	R56C54[0][A]	Mdu/u_mdu/reg0_neg_cry_56_0/CIN
5.987	0.035	tINS	FF	1	R56C54[0][A]	Mdu/u_mdu/reg0_neg_cry_56_0/COUT
5.987	0.000	tNET	FF	2	R56C54[0][B]	Mdu/u_mdu/reg0_neg_cry_57_0/CIN
6.023	0.035	tINS	FF	1	R56C54[0][B]	Mdu/u_mdu/reg0_neg_cry_57_0/COUT
6.023	0.000	tNET	FF	2	R56C54[1][A]	Mdu/u_mdu/reg0_neg_cry_58_0/CIN
6.058	0.035	tINS	FF	1	R56C54[1][A]	Mdu/u_mdu/reg0_neg_cry_58_0/COUT
6.058	0.000	tNET	FF	2	R56C54[1][B]	Mdu/u_mdu/reg0_neg_cry_59_0/CIN
6.093	0.035	tINS	FF	1	R56C54[1][B]	Mdu/u_mdu/reg0_neg_cry_59_0/COUT
6.093	0.000	tNET	FF	2	R56C54[2][A]	Mdu/u_mdu/reg0_neg_cry_60_0/CIN
6.128	0.035	tINS	FF	1	R56C54[2][A]	Mdu/u_mdu/reg0_neg_cry_60_0/COUT
6.128	0.000	tNET	FF	2	R56C54[2][B]	Mdu/u_mdu/reg0_neg_cry_61_0/CIN
6.598	0.470	tINS	FF	1	R56C54[2][B]	Mdu/u_mdu/reg0_neg_cry_61_0/SUM
7.161	0.563	tNET	FF	1	R53C54[1][A]	Mdu/u_mdu/reg0_post_swap_2[29]/I2
7.716	0.555	tINS	FF	1	R53C54[1][A]	Mdu/u_mdu/reg0_post_swap_2[29]/F
7.716	0.000	tNET	FF	1	R53C54[1][A]	Mdu/u_mdu/reg0_post_swap_4[29]/I0
7.819	0.103	tINS	FF	1	R53C54[1][A]	Mdu/u_mdu/reg0_post_swap_4[29]/O
8.974	1.155	tNET	FF	1	R40C61[3][B]	Mdu/u_mdu/reg0_post_swap_5[29]/I1
9.529	0.555	tINS	FF	2	R40C61[3][B]	Mdu/u_mdu/reg0_post_swap_5[29]/F
9.782	0.253	tNET	FF	1	R38C61[3][A]	Mdu/u_mdu/res0_cZ[29]/I1
10.337	0.555	tINS	FF	3	R38C61[3][A]	Mdu/u_mdu/res0_cZ[29]/F
11.277	0.940	tNET	FF	1	BSRAM_R45[19]	memq_memq_0_14/DI1

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	578	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	BSRAM_R45[19]	memq_memq_0_14/CLKA
11.683	-0.200	tUnc				memq_memq_0_14
11.648	-0.035	tSu		1	BSRAM_R45[19]	memq_memq_0_14

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 3.923, 41.765%; route: 5.239, 55.765%; tC2Q: 0.232, 2.470%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path6

Path Summary:

Slack	0.522
Data Arrival Time	11.126
Data Required Time	11.648
From	Mdu/u_mdu/rs1_mul_Z[5]
To	Mdu/u_mdu/reg0_Z[39]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.683	0.683	tINS	RR	578	IOT48[A]	clk_ibuf/O
1.883	1.201	tNET	RR	1	R46C62[1][A]	Mdu/u_mdu/rs1_mul_Z[5]/CLK
2.115	0.232	tC2Q	RF	1	R46C62[1][A]	Mdu/u_mdu/rs1_mul_Z[5]/Q
3.013	0.898	tNET	FF	1	R46C62[3][B]	Mdu/u_mdu/adder_sum_s_5_sf_lofx_cZ/I2
3.568	0.555	tINS	FF	1	R46C62[3][B]	Mdu/u_mdu/adder_sum_s_5_sf_lofx_cZ/F
4.252	0.684	tNET	FF	2	R47C58[0][B]	Mdu/u_mdu/adder_sum_cry_5_0/I0
4.822	0.570	tINS	FR	1	R47C58[0][B]	Mdu/u_mdu/adder_sum_cry_5_0/COUT
4.822	0.000	tNET	RR	2	R47C58[1][A]	Mdu/u_mdu/adder_sum_cry_6_0/CIN
4.857	0.035	tINS	RF	1	R47C58[1][A]	Mdu/u_mdu/adder_sum_cry_6_0/COUT
4.857	0.000	tNET	FF	2	R47C58[1][B]	Mdu/u_mdu/adder_sum_cry_7_0/CIN
4.892	0.035	tINS	FF	1	R47C58[1][B]	Mdu/u_mdu/adder_sum_cry_7_0/COUT
4.892	0.000	tNET	FF	2	R47C58[2][A]	Mdu/u_mdu/adder_sum_cry_8_0/CIN
4.927	0.035	tINS	FF	1	R47C58[2][A]	Mdu/u_mdu/adder_sum_cry_8_0/COUT
4.927	0.000	tNET	FF	2	R47C58[2][B]	Mdu/u_mdu/adder_sum_cry_9_0/CIN
4.963	0.035	tINS	FF	1	R47C58[2][B]	Mdu/u_mdu/adder_sum_cry_9_0/COUT
4.963	0.000	tNET	FF	2	R47C59[0][A]	Mdu/u_mdu/adder_sum_cry_10_0/CIN
4.998	0.035	tINS	FF	1	R47C59[0][A]	Mdu/u_mdu/adder_sum_cry_10_0/COUT
4.998	0.000	tNET	FF	2	R47C59[0][B]	Mdu/u_mdu/adder_sum_cry_11_0/CIN
5.033	0.035	tINS	FF	1	R47C59[0][B]	Mdu/u_mdu/adder_sum_cry_11_0/COUT
5.033	0.000	tNET	FF	2	R47C59[1][A]	Mdu/u_mdu/adder_sum_cry_12_0/CIN
5.068	0.035	tINS	FF	1	R47C59[1][A]	Mdu/u_mdu/adder_sum_cry_12_0/COUT
5.068	0.000	tNET	FF	2	R47C59[1][B]	Mdu/u_mdu/adder_sum_cry_13_0/CIN
5.103	0.035	tINS	FF	1	R47C59[1][B]	Mdu/u_mdu/adder_sum_cry_13_0/COUT
5.103	0.000	tNET	FF	2	R47C59[2][A]	Mdu/u_mdu/adder_sum_cry_14_0/CIN
5.139	0.035	tINS	FF	1	R47C59[2][A]	Mdu/u_mdu/adder_sum_cry_14_0/COUT
5.139	0.000	tNET	FF	2	R47C59[2][B]	Mdu/u_mdu/adder_sum_cry_15_0/CIN
5.174	0.035	tINS	FF	1	R47C59[2][B]	Mdu/u_mdu/adder_sum_cry_15_0/COUT
5.174	0.000	tNET	FF	2	R47C60[0][A]	Mdu/u_mdu/adder_sum_cry_16_0/CIN
5.209	0.035	tINS	FF	1	R47C60[0][A]	Mdu/u_mdu/adder_sum_cry_16_0/COUT
5.209	0.000	tNET	FF	2	R47C60[0][B]	Mdu/u_mdu/adder_sum_cry_17_0/CIN
5.244	0.035	tINS	FF	1	R47C60[0][B]	Mdu/u_mdu/adder_sum_cry_17_0/COUT
5.244	0.000	tNET	FF	2	R47C60[1][A]	Mdu/u_mdu/adder_sum_cry_18_0/CIN
5.279	0.035	tINS	FF	1	R47C60[1][A]	Mdu/u_mdu/adder_sum_cry_18_0/COUT
5.279	0.000	tNET	FF	2	R47C60[1][B]	Mdu/u_mdu/adder_sum_cry_19_0/CIN
5.315	0.035	tINS	FF	1	R47C60[1][B]	Mdu/u_mdu/adder_sum_cry_19_0/COUT
5.315	0.000	tNET	FF	2	R47C60[2][A]	Mdu/u_mdu/adder_sum_cry_20_0/CIN
5.350	0.035	tINS	FF	1	R47C60[2][A]	Mdu/u_mdu/adder_sum_cry_20_0/COUT
5.350	0.000	tNET	FF	2	R47C60[2][B]	Mdu/u_mdu/adder_sum_cry_21_0/CIN
5.385	0.035	tINS	FF	1	R47C60[2][B]	Mdu/u_mdu/adder_sum_cry_21_0/COUT
5.385	0.000	tNET	FF	2	R47C61[0][A]	Mdu/u_mdu/adder_sum_cry_22_0/CIN
5.420	0.035	tINS	FF	1	R47C61[0][A]	Mdu/u_mdu/adder_sum_cry_22_0/COUT
5.420	0.000	tNET	FF	2	R47C61[0][B]	Mdu/u_mdu/adder_sum_cry_23_0/CIN
5.455	0.035	tINS	FF	1	R47C61[0][B]	Mdu/u_mdu/adder_sum_cry_23_0/COUT
5.455	0.000	tNET	FF	2	R47C61[1][A]	Mdu/u_mdu/adder_sum_cry_24_0/CIN
5.491	0.035	tINS	FF	1	R47C61[1][A]	Mdu/u_mdu/adder_sum_cry_24_0/COUT
5.491	0.000	tNET	FF	2	R47C61[1][B]	Mdu/u_mdu/adder_sum_cry_25_0/CIN
5.526	0.035	tINS	FF	1	R47C61[1][B]	Mdu/u_mdu/adder_sum_cry_25_0/COUT
5.526	0.000	tNET	FF	2	R47C61[2][A]	Mdu/u_mdu/adder_sum_cry_26_0/CIN
5.561	0.035	tINS	FF	1	R47C61[2][A]	Mdu/u_mdu/adder_sum_cry_26_0/COUT
5.561	0.000	tNET	FF	2	R47C61[2][B]	Mdu/u_mdu/adder_sum_cry_27_0/CIN
5.596	0.035	tINS	FF	1	R47C61[2][B]	Mdu/u_mdu/adder_sum_cry_27_0/COUT
5.596	0.000	tNET	FF	2	R47C62[0][A]	Mdu/u_mdu/adder_sum_cry_28_0/CIN
5.631	0.035	tINS	FF	1	R47C62[0][A]	Mdu/u_mdu/adder_sum_cry_28_0/COUT
5.631	0.000	tNET	FF	2	R47C62[0][B]	Mdu/u_mdu/adder_sum_cry_29_0/CIN
5.667	0.035	tINS	FF	1	R47C62[0][B]	Mdu/u_mdu/adder_sum_cry_29_0/COUT
5.667	0.000	tNET	FF	2	R47C62[1][A]	Mdu/u_mdu/adder_sum_cry_30_0/CIN
5.702	0.035	tINS	FF	1	R47C62[1][A]	Mdu/u_mdu/adder_sum_cry_30_0/COUT
5.702	0.000	tNET	FF	2	R47C62[1][B]	Mdu/u_mdu/adder_sum_cry_31_0/CIN
5.737	0.035	tINS	FF	1	R47C62[1][B]	Mdu/u_mdu/adder_sum_cry_31_0/COUT
5.737	0.000	tNET	FF	2	R47C62[2][A]	Mdu/u_mdu/adder_sum_s_32_0/CIN
6.207	0.470	tINS	FF	6	R47C62[2][A]	Mdu/u_mdu/adder_sum_s_32_0/SUM
7.175	0.968	tNET	FF	1	R37C55[1][B]	Mdu/u_mdu/reg0_exe_nx_ss0_cZ/I0
7.692	0.517	tINS	FF	50	R37C55[1][B]	Mdu/u_mdu/reg0_exe_nx_ss0_cZ/F
8.498	0.806	tNET	FF	1	R33C59[2][A]	Mdu/u_mdu/reg0_exe_nx_m0_cZ[39]/I2
8.951	0.453	tINS	FF	1	R33C59[2][A]	Mdu/u_mdu/reg0_exe_nx_m0_cZ[39]/F
8.951	0.000	tNET	FF	1	R33C59[2][A]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[39]/I0
9.054	0.103	tINS	FF	1	R33C59[2][A]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[39]/O
10.577	1.523	tNET	FF	1	R51C62[1][B]	Mdu/u_mdu/reg0_nx_cZ[39]/I0
11.126	0.549	tINS	FR	1	R51C62[1][B]	Mdu/u_mdu/reg0_nx_cZ[39]/F
11.126	0.000	tNET	RR	1	R51C62[1][B]	Mdu/u_mdu/reg0_Z[39]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	578	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R51C62[1][B]	Mdu/u_mdu/reg0_Z[39]/CLK
11.683	-0.200	tUnc				Mdu/u_mdu/reg0_Z[39]
11.648	-0.035	tSu		1	R51C62[1][B]	Mdu/u_mdu/reg0_Z[39]

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 4.132, 44.708%; route: 4.879, 52.782%; tC2Q: 0.232, 2.510%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path7

Path Summary:

Slack	0.530
Data Arrival Time	11.119
Data Required Time	11.648
From	Mdu/u_mdu/div_shift_number_Z[1]
To	Mdu/u_mdu/reg0_Z[54]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.683	0.683	tINS	RR	578	IOT48[A]	clk_ibuf/O
1.883	1.201	tNET	RR	1	R29C56[1][B]	Mdu/u_mdu/div_shift_number_Z[1]/CLK
2.115	0.232	tC2Q	RF	114	R29C56[1][B]	Mdu/u_mdu/div_shift_number_Z[1]/Q
3.459	1.344	tNET	FF	1	R34C53[0][B]	Mdu/u_mdu/m14_0_03_1_cZ/I1
3.921	0.462	tINS	FR	1	R34C53[0][B]	Mdu/u_mdu/m14_0_03_1_cZ/F
4.093	0.172	tNET	RR	1	R34C54[2][A]	Mdu/u_mdu/m14_0_03_cZ/I1
4.610	0.517	tINS	RF	4	R34C54[2][A]	Mdu/u_mdu/m14_0_03_cZ/F
5.386	0.776	tNET	FF	1	R32C60[3][A]	Mdu/u_mdu/m22_2_03_0_0_cZ/I3
5.903	0.517	tINS	FF	2	R32C60[3][A]	Mdu/u_mdu/m22_2_03_0_0_cZ/F
6.306	0.403	tNET	FF	1	R30C60[3][A]	Mdu/u_mdu/m22_2_03_0_0_RNI5G1/I0
6.861	0.555	tINS	FF	2	R30C60[3][A]	Mdu/u_mdu/m22_2_03_0_0_RNI5G1/F
7.748	0.887	tNET	FF	1	R30C59[0][A]	Mdu/u_mdu/m54_4_03_0_0_cZ/I1
8.119	0.371	tINS	FF	1	R30C59[0][A]	Mdu/u_mdu/m54_4_03_0_0_cZ/F
9.240	1.121	tNET	FF	1	R46C58[2][A]	Mdu/u_mdu/reg0_exe_nx_m0_cZ[54]/I1
9.611	0.371	tINS	FF	1	R46C58[2][A]	Mdu/u_mdu/reg0_exe_nx_m0_cZ[54]/F
9.611	0.000	tNET	FF	1	R46C58[2][A]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[54]/I0
9.714	0.103	tINS	FF	1	R46C58[2][A]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[54]/O
10.570	0.856	tNET	FF	1	R53C58[1][A]	Mdu/u_mdu/reg0_nx_0[54]/I2
11.119	0.549	tINS	FR	1	R53C58[1][A]	Mdu/u_mdu/reg0_nx_0[54]/F
11.119	0.000	tNET	RR	1	R53C58[1][A]	Mdu/u_mdu/reg0_Z[54]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	578	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R53C58[1][A]	Mdu/u_mdu/reg0_Z[54]/CLK
11.683	-0.200	tUnc				Mdu/u_mdu/reg0_Z[54]
11.648	-0.035	tSu		1	R53C58[1][A]	Mdu/u_mdu/reg0_Z[54]

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	8
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 3.445, 37.302%; route: 5.558, 60.186%; tC2Q: 0.232, 2.512%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path8

Path Summary:

Slack	0.605
Data Arrival Time	11.044
Data Required Time	11.648
From	Mdu/u_mdu/reg0_fast_Z[13]
To	memq_memq_0_13
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.683	0.683	tINS	RR	578	IOT48[A]	clk_ibuf/O
1.883	1.201	tNET	RR	1	R38C59[1][A]	Mdu/u_mdu/reg0_fast_Z[13]/CLK
2.115	0.232	tC2Q	RF	8	R38C59[1][A]	Mdu/u_mdu/reg0_fast_Z[13]/Q
3.516	1.401	tNET	FF	1	R51C54[3][B]	Mdu/u_mdu/reg0_neg_axb_12_par_0_cp_0_cZ/I1
4.033	0.517	tINS	FF	1	R51C54[3][B]	Mdu/u_mdu/reg0_neg_axb_12_par_0_cp_0_cZ/F
4.960	0.927	tNET	FF	2	R56C51[2][B]	Mdu/u_mdu/reg0_neg_axb_12_par_cp_0_0/I0
5.530	0.570	tINS	FR	1	R56C51[2][B]	Mdu/u_mdu/reg0_neg_axb_12_par_cp_0_0/COUT
5.530	0.000	tNET	RR	2	R56C52[0][A]	Mdu/u_mdu/reg0_neg_axb_16_par_cp_0_0/CIN
5.565	0.035	tINS	RF	1	R56C52[0][A]	Mdu/u_mdu/reg0_neg_axb_16_par_cp_0_0/COUT
5.565	0.000	tNET	FF	2	R56C52[0][B]	Mdu/u_mdu/reg0_neg_axb_19_par_cp_0/CIN
5.600	0.035	tINS	FF	1	R56C52[0][B]	Mdu/u_mdu/reg0_neg_axb_19_par_cp_0/COUT
5.600	0.000	tNET	FF	2	R56C52[1][A]	Mdu/u_mdu/reg0_neg_axb_23_par_cp_0/CIN
5.635	0.035	tINS	FF	1	R56C52[1][A]	Mdu/u_mdu/reg0_neg_axb_23_par_cp_0/COUT
5.635	0.000	tNET	FF	2	R56C52[1][B]	Mdu/u_mdu/reg0_neg_axb_27_par_cp_0/CIN
5.671	0.035	tINS	FF	1	R56C52[1][B]	Mdu/u_mdu/reg0_neg_axb_27_par_cp_0/COUT
5.671	0.000	tNET	FF	2	R56C52[2][A]	Mdu/u_mdu/reg0_neg_axb_31_par_cp_0/CIN
5.706	0.035	tINS	FF	1	R56C52[2][A]	Mdu/u_mdu/reg0_neg_axb_31_par_cp_0/COUT
5.706	0.000	tNET	FF	2	R56C52[2][B]	Mdu/u_mdu/reg0_neg_axb_34_par_1/CIN
5.741	0.035	tINS	FF	1	R56C52[2][B]	Mdu/u_mdu/reg0_neg_axb_34_par_1/COUT
5.741	0.000	tNET	FF	2	R56C53[0][A]	Mdu/u_mdu/reg0_neg_axb_38_par_1/CIN
5.776	0.035	tINS	FF	1	R56C53[0][A]	Mdu/u_mdu/reg0_neg_axb_38_par_1/COUT
5.776	0.000	tNET	FF	2	R56C53[0][B]	Mdu/u_mdu/reg0_neg_axb_42_par_1/CIN
5.811	0.035	tINS	FF	1	R56C53[0][B]	Mdu/u_mdu/reg0_neg_axb_42_par_1/COUT
5.811	0.000	tNET	FF	2	R56C53[1][A]	Mdu/u_mdu/reg0_neg_axb_46_par_1/CIN
5.847	0.035	tINS	FF	1	R56C53[1][A]	Mdu/u_mdu/reg0_neg_axb_46_par_1/COUT
5.847	0.000	tNET	FF	2	R56C53[1][B]	Mdu/u_mdu/reg0_neg_axb_50_par_1/CIN
5.882	0.035	tINS	FF	1	R56C53[1][B]	Mdu/u_mdu/reg0_neg_axb_50_par_1/COUT
5.882	0.000	tNET	FF	2	R56C53[2][A]	Mdu/u_mdu/reg0_neg_cry_54_0/CIN
5.917	0.035	tINS	FF	1	R56C53[2][A]	Mdu/u_mdu/reg0_neg_cry_54_0/COUT
5.917	0.000	tNET	FF	2	R56C53[2][B]	Mdu/u_mdu/reg0_neg_cry_55_0/CIN
5.952	0.035	tINS	FF	1	R56C53[2][B]	Mdu/u_mdu/reg0_neg_cry_55_0/COUT
5.952	0.000	tNET	FF	2	R56C54[0][A]	Mdu/u_mdu/reg0_neg_cry_56_0/CIN
5.987	0.035	tINS	FF	1	R56C54[0][A]	Mdu/u_mdu/reg0_neg_cry_56_0/COUT
5.987	0.000	tNET	FF	2	R56C54[0][B]	Mdu/u_mdu/reg0_neg_cry_57_0/CIN
6.023	0.035	tINS	FF	1	R56C54[0][B]	Mdu/u_mdu/reg0_neg_cry_57_0/COUT
6.023	0.000	tNET	FF	2	R56C54[1][A]	Mdu/u_mdu/reg0_neg_cry_58_0/CIN
6.058	0.035	tINS	FF	1	R56C54[1][A]	Mdu/u_mdu/reg0_neg_cry_58_0/COUT
6.058	0.000	tNET	FF	2	R56C54[1][B]	Mdu/u_mdu/reg0_neg_cry_59_0/CIN
6.528	0.470	tINS	FF	1	R56C54[1][B]	Mdu/u_mdu/reg0_neg_cry_59_0/SUM
6.941	0.413	tNET	FF	1	R55C54[3][A]	Mdu/u_mdu/reg0_post_swap_2[27]/I2
7.394	0.453	tINS	FF	1	R55C54[3][A]	Mdu/u_mdu/reg0_post_swap_2[27]/F
7.394	0.000	tNET	FF	1	R55C54[3][A]	Mdu/u_mdu/reg0_post_swap_4[27]/I0
7.497	0.103	tINS	FF	2	R55C54[3][A]	Mdu/u_mdu/reg0_post_swap_4[27]/O
7.925	0.428	tNET	FF	1	R52C54[0][A]	Mdu/u_mdu/reg0_post_swap_5[27]/I1
8.296	0.371	tINS	FF	1	R52C54[0][A]	Mdu/u_mdu/reg0_post_swap_5[27]/F
9.389	1.093	tNET	FF	1	R39C54[0][B]	Mdu/u_mdu/res0_cZ[27]/I1
9.842	0.453	tINS	FF	3	R39C54[0][B]	Mdu/u_mdu/res0_cZ[27]/F
11.044	1.202	tNET	FF	1	BSRAM_R36[20]	memq_memq_0_13/DI1

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	578	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	BSRAM_R36[20]	memq_memq_0_13/CLKA
11.683	-0.200	tUnc				memq_memq_0_13
11.648	-0.035	tSu		1	BSRAM_R36[20]	memq_memq_0_13

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 3.465, 37.825%; route: 5.464, 59.643%; tC2Q: 0.232, 2.533%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path9

Path Summary:

Slack	0.629
Data Arrival Time	11.019
Data Required Time	11.648
From	Mdu/u_mdu/reg0_fast_Z[13]
To	memq_memq_0_9
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.683	0.683	tINS	RR	578	IOT48[A]	clk_ibuf/O
1.883	1.201	tNET	RR	1	R38C59[1][A]	Mdu/u_mdu/reg0_fast_Z[13]/CLK
2.115	0.232	tC2Q	RF	8	R38C59[1][A]	Mdu/u_mdu/reg0_fast_Z[13]/Q
3.360	1.245	tNET	FF	1	R51C56[1][B]	Mdu/u_mdu/reg0_neg_axb_12_par_0_cp_cZ/I1
3.915	0.555	tINS	FF	1	R51C56[1][B]	Mdu/u_mdu/reg0_neg_axb_12_par_0_cp_cZ/F
4.814	0.899	tNET	FF	2	R52C56[2][B]	Mdu/u_mdu/reg0_neg_axb_12_par_cp_1/I0
5.384	0.570	tINS	FR	1	R52C56[2][B]	Mdu/u_mdu/reg0_neg_axb_12_par_cp_1/COUT
5.384	0.000	tNET	RR	2	R52C57[0][A]	Mdu/u_mdu/reg0_neg_axb_16_par_cp_1/CIN
5.419	0.035	tINS	RF	1	R52C57[0][A]	Mdu/u_mdu/reg0_neg_axb_16_par_cp_1/COUT
5.419	0.000	tNET	FF	2	R52C57[0][B]	Mdu/u_mdu/reg0_neg_axb_19_par_1/CIN
5.454	0.035	tINS	FF	1	R52C57[0][B]	Mdu/u_mdu/reg0_neg_axb_19_par_1/COUT
5.454	0.000	tNET	FF	2	R52C57[1][A]	Mdu/u_mdu/reg0_neg_axb_23_par_1/CIN
5.490	0.035	tINS	FF	1	R52C57[1][A]	Mdu/u_mdu/reg0_neg_axb_23_par_1/COUT
5.490	0.000	tNET	FF	2	R52C57[1][B]	Mdu/u_mdu/reg0_neg_axb_27_par_1/CIN
5.525	0.035	tINS	FF	1	R52C57[1][B]	Mdu/u_mdu/reg0_neg_axb_27_par_1/COUT
5.525	0.000	tNET	FF	2	R52C57[2][A]	Mdu/u_mdu/reg0_neg_axb_31_par_1/CIN
5.560	0.035	tINS	FF	1	R52C57[2][A]	Mdu/u_mdu/reg0_neg_axb_31_par_1/COUT
5.560	0.000	tNET	FF	2	R52C57[2][B]	Mdu/u_mdu/reg0_neg_cry_34_0/CIN
5.595	0.035	tINS	FF	1	R52C57[2][B]	Mdu/u_mdu/reg0_neg_cry_34_0/COUT
5.595	0.000	tNET	FF	2	R52C58[0][A]	Mdu/u_mdu/reg0_neg_cry_35_0/CIN
5.630	0.035	tINS	FF	1	R52C58[0][A]	Mdu/u_mdu/reg0_neg_cry_35_0/COUT
5.630	0.000	tNET	FF	2	R52C58[0][B]	Mdu/u_mdu/reg0_neg_cry_36_0/CIN
5.666	0.035	tINS	FF	1	R52C58[0][B]	Mdu/u_mdu/reg0_neg_cry_36_0/COUT
5.666	0.000	tNET	FF	2	R52C58[1][A]	Mdu/u_mdu/reg0_neg_cry_37_0/CIN
5.701	0.035	tINS	FF	1	R52C58[1][A]	Mdu/u_mdu/reg0_neg_cry_37_0/COUT
5.701	0.000	tNET	FF	2	R52C58[1][B]	Mdu/u_mdu/reg0_neg_cry_38_0/CIN
5.736	0.035	tINS	FF	1	R52C58[1][B]	Mdu/u_mdu/reg0_neg_cry_38_0/COUT
5.736	0.000	tNET	FF	2	R52C58[2][A]	Mdu/u_mdu/reg0_neg_cry_39_0/CIN
5.771	0.035	tINS	FF	1	R52C58[2][A]	Mdu/u_mdu/reg0_neg_cry_39_0/COUT
5.771	0.000	tNET	FF	2	R52C58[2][B]	Mdu/u_mdu/reg0_neg_cry_40_0/CIN
5.806	0.035	tINS	FF	1	R52C58[2][B]	Mdu/u_mdu/reg0_neg_cry_40_0/COUT
5.806	0.000	tNET	FF	2	R52C59[0][A]	Mdu/u_mdu/reg0_neg_cry_41_0/CIN
5.842	0.035	tINS	FF	1	R52C59[0][A]	Mdu/u_mdu/reg0_neg_cry_41_0/COUT
5.842	0.000	tNET	FF	2	R52C59[0][B]	Mdu/u_mdu/reg0_neg_cry_42_0/CIN
5.877	0.035	tINS	FF	1	R52C59[0][B]	Mdu/u_mdu/reg0_neg_cry_42_0/COUT
5.877	0.000	tNET	FF	2	R52C59[1][A]	Mdu/u_mdu/reg0_neg_cry_43_0/CIN
5.912	0.035	tINS	FF	1	R52C59[1][A]	Mdu/u_mdu/reg0_neg_cry_43_0/COUT
5.912	0.000	tNET	FF	2	R52C59[1][B]	Mdu/u_mdu/reg0_neg_cry_44_0/CIN
5.947	0.035	tINS	FF	1	R52C59[1][B]	Mdu/u_mdu/reg0_neg_cry_44_0/COUT
5.947	0.000	tNET	FF	2	R52C59[2][A]	Mdu/u_mdu/reg0_neg_cry_45_0/CIN
5.982	0.035	tINS	FF	1	R52C59[2][A]	Mdu/u_mdu/reg0_neg_cry_45_0/COUT
5.982	0.000	tNET	FF	2	R52C59[2][B]	Mdu/u_mdu/reg0_neg_cry_46_0/CIN
6.018	0.035	tINS	FF	1	R52C59[2][B]	Mdu/u_mdu/reg0_neg_cry_46_0/COUT
6.018	0.000	tNET	FF	2	R52C60[0][A]	Mdu/u_mdu/reg0_neg_cry_47_0/CIN
6.053	0.035	tINS	FF	1	R52C60[0][A]	Mdu/u_mdu/reg0_neg_cry_47_0/COUT
6.053	0.000	tNET	FF	2	R52C60[0][B]	Mdu/u_mdu/reg0_neg_cry_48_0/CIN
6.088	0.035	tINS	FF	1	R52C60[0][B]	Mdu/u_mdu/reg0_neg_cry_48_0/COUT
6.088	0.000	tNET	FF	2	R52C60[1][A]	Mdu/u_mdu/reg0_neg_cry_49_0/CIN
6.123	0.035	tINS	FF	1	R52C60[1][A]	Mdu/u_mdu/reg0_neg_cry_49_0/COUT
6.123	0.000	tNET	FF	2	R52C60[1][B]	Mdu/u_mdu/reg0_neg_cry_50_0/CIN
6.158	0.035	tINS	FF	1	R52C60[1][B]	Mdu/u_mdu/reg0_neg_cry_50_0/COUT
6.158	0.000	tNET	FF	2	R52C60[2][A]	Mdu/u_mdu/reg0_neg_cry_51_0/CIN
6.628	0.470	tINS	FF	1	R52C60[2][A]	Mdu/u_mdu/reg0_neg_cry_51_0/SUM
7.312	0.684	tNET	FF	1	R55C58[2][A]	Mdu/u_mdu/reg0_post_swap_2[19]/I2
7.829	0.517	tINS	FF	1	R55C58[2][A]	Mdu/u_mdu/reg0_post_swap_2[19]/F
7.829	0.000	tNET	FF	1	R55C58[2][A]	Mdu/u_mdu/reg0_post_swap_4[19]/I0
7.932	0.103	tINS	FF	2	R55C58[2][A]	Mdu/u_mdu/reg0_post_swap_4[19]/O
8.556	0.623	tNET	FF	1	R48C58[2][A]	Mdu/u_mdu/reg0_post_swap_5[19]/I1
8.927	0.371	tINS	FF	1	R48C58[2][A]	Mdu/u_mdu/reg0_post_swap_5[19]/F
9.837	0.911	tNET	FF	1	R39C58[0][B]	Mdu/u_mdu/res0_cZ[19]/I1
10.354	0.517	tINS	FF	3	R39C58[0][B]	Mdu/u_mdu/res0_cZ[19]/F
11.019	0.665	tNET	FF	1	BSRAM_R36[18]	memq_memq_0_9/DI1

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	578	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	BSRAM_R36[18]	memq_memq_0_9/CLKA
11.683	-0.200	tUnc				memq_memq_0_9
11.648	-0.035	tSu		1	BSRAM_R36[18]	memq_memq_0_9

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 3.877, 42.440%; route: 5.027, 55.021%; tC2Q: 0.232, 2.539%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path10

Path Summary:

Slack	0.679
Data Arrival Time	10.970
Data Required Time	11.648
From	Mdu/u_mdu/reg0_fast_Z[13]
To	memq_memq_0_14
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.683	0.683	tINS	RR	578	IOT48[A]	clk_ibuf/O
1.883	1.201	tNET	RR	1	R38C59[1][A]	Mdu/u_mdu/reg0_fast_Z[13]/CLK
2.115	0.232	tC2Q	RF	8	R38C59[1][A]	Mdu/u_mdu/reg0_fast_Z[13]/Q
3.516	1.401	tNET	FF	1	R51C54[3][B]	Mdu/u_mdu/reg0_neg_axb_12_par_0_cp_0_cZ/I1
4.033	0.517	tINS	FF	1	R51C54[3][B]	Mdu/u_mdu/reg0_neg_axb_12_par_0_cp_0_cZ/F
4.960	0.927	tNET	FF	2	R56C51[2][B]	Mdu/u_mdu/reg0_neg_axb_12_par_cp_0_0/I0
5.530	0.570	tINS	FR	1	R56C51[2][B]	Mdu/u_mdu/reg0_neg_axb_12_par_cp_0_0/COUT
5.530	0.000	tNET	RR	2	R56C52[0][A]	Mdu/u_mdu/reg0_neg_axb_16_par_cp_0_0/CIN
5.565	0.035	tINS	RF	1	R56C52[0][A]	Mdu/u_mdu/reg0_neg_axb_16_par_cp_0_0/COUT
5.565	0.000	tNET	FF	2	R56C52[0][B]	Mdu/u_mdu/reg0_neg_axb_19_par_cp_0/CIN
5.600	0.035	tINS	FF	1	R56C52[0][B]	Mdu/u_mdu/reg0_neg_axb_19_par_cp_0/COUT
5.600	0.000	tNET	FF	2	R56C52[1][A]	Mdu/u_mdu/reg0_neg_axb_23_par_cp_0/CIN
5.635	0.035	tINS	FF	1	R56C52[1][A]	Mdu/u_mdu/reg0_neg_axb_23_par_cp_0/COUT
5.635	0.000	tNET	FF	2	R56C52[1][B]	Mdu/u_mdu/reg0_neg_axb_27_par_cp_0/CIN
5.671	0.035	tINS	FF	1	R56C52[1][B]	Mdu/u_mdu/reg0_neg_axb_27_par_cp_0/COUT
5.671	0.000	tNET	FF	2	R56C52[2][A]	Mdu/u_mdu/reg0_neg_axb_31_par_cp_0/CIN
5.706	0.035	tINS	FF	1	R56C52[2][A]	Mdu/u_mdu/reg0_neg_axb_31_par_cp_0/COUT
5.706	0.000	tNET	FF	2	R56C52[2][B]	Mdu/u_mdu/reg0_neg_axb_34_par_1/CIN
5.741	0.035	tINS	FF	1	R56C52[2][B]	Mdu/u_mdu/reg0_neg_axb_34_par_1/COUT
5.741	0.000	tNET	FF	2	R56C53[0][A]	Mdu/u_mdu/reg0_neg_axb_38_par_1/CIN
5.776	0.035	tINS	FF	1	R56C53[0][A]	Mdu/u_mdu/reg0_neg_axb_38_par_1/COUT
5.776	0.000	tNET	FF	2	R56C53[0][B]	Mdu/u_mdu/reg0_neg_axb_42_par_1/CIN
5.811	0.035	tINS	FF	1	R56C53[0][B]	Mdu/u_mdu/reg0_neg_axb_42_par_1/COUT
5.811	0.000	tNET	FF	2	R56C53[1][A]	Mdu/u_mdu/reg0_neg_axb_46_par_1/CIN
5.847	0.035	tINS	FF	1	R56C53[1][A]	Mdu/u_mdu/reg0_neg_axb_46_par_1/COUT
5.847	0.000	tNET	FF	2	R56C53[1][B]	Mdu/u_mdu/reg0_neg_axb_50_par_1/CIN
5.882	0.035	tINS	FF	1	R56C53[1][B]	Mdu/u_mdu/reg0_neg_axb_50_par_1/COUT
5.882	0.000	tNET	FF	2	R56C53[2][A]	Mdu/u_mdu/reg0_neg_cry_54_0/CIN
5.917	0.035	tINS	FF	1	R56C53[2][A]	Mdu/u_mdu/reg0_neg_cry_54_0/COUT
5.917	0.000	tNET	FF	2	R56C53[2][B]	Mdu/u_mdu/reg0_neg_cry_55_0/CIN
5.952	0.035	tINS	FF	1	R56C53[2][B]	Mdu/u_mdu/reg0_neg_cry_55_0/COUT
5.952	0.000	tNET	FF	2	R56C54[0][A]	Mdu/u_mdu/reg0_neg_cry_56_0/CIN
5.987	0.035	tINS	FF	1	R56C54[0][A]	Mdu/u_mdu/reg0_neg_cry_56_0/COUT
5.987	0.000	tNET	FF	2	R56C54[0][B]	Mdu/u_mdu/reg0_neg_cry_57_0/CIN
6.023	0.035	tINS	FF	1	R56C54[0][B]	Mdu/u_mdu/reg0_neg_cry_57_0/COUT
6.023	0.000	tNET	FF	2	R56C54[1][A]	Mdu/u_mdu/reg0_neg_cry_58_0/CIN
6.058	0.035	tINS	FF	1	R56C54[1][A]	Mdu/u_mdu/reg0_neg_cry_58_0/COUT
6.058	0.000	tNET	FF	2	R56C54[1][B]	Mdu/u_mdu/reg0_neg_cry_59_0/CIN
6.093	0.035	tINS	FF	1	R56C54[1][B]	Mdu/u_mdu/reg0_neg_cry_59_0/COUT
6.093	0.000	tNET	FF	2	R56C54[2][A]	Mdu/u_mdu/reg0_neg_cry_60_0/CIN
6.563	0.470	tINS	FF	1	R56C54[2][A]	Mdu/u_mdu/reg0_neg_cry_60_0/SUM
6.976	0.413	tNET	FF	1	R55C53[3][A]	Mdu/u_mdu/reg0_post_swap_2[28]/I2
7.531	0.555	tINS	FF	1	R55C53[3][A]	Mdu/u_mdu/reg0_post_swap_2[28]/F
7.531	0.000	tNET	FF	1	R55C53[3][A]	Mdu/u_mdu/reg0_post_swap_4[28]/I0
7.634	0.103	tINS	FF	2	R55C53[3][A]	Mdu/u_mdu/reg0_post_swap_4[28]/O
8.605	0.971	tNET	FF	1	R40C51[3][B]	Mdu/u_mdu/reg0_post_swap_5[28]/I1
9.067	0.462	tINS	FR	1	R40C51[3][B]	Mdu/u_mdu/reg0_post_swap_5[28]/F
9.068	0.001	tNET	RR	1	R40C51[2][A]	Mdu/u_mdu/res0_cZ[28]/I1
9.585	0.517	tINS	RF	3	R40C51[2][A]	Mdu/u_mdu/res0_cZ[28]/F
10.970	1.384	tNET	FF	1	BSRAM_R45[19]	memq_memq_0_14/DI0

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	578	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	BSRAM_R45[19]	memq_memq_0_14/CLKA
11.683	-0.200	tUnc				memq_memq_0_14
11.648	-0.035	tSu		1	BSRAM_R45[19]	memq_memq_0_14

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 3.757, 41.349%; route: 5.097, 56.098%; tC2Q: 0.232, 2.553%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path11

Path Summary:

Slack	0.713
Data Arrival Time	10.935
Data Required Time	11.648
From	Mdu/u_mdu/reg0_fast_Z[13]
To	Mdu/u_mdu/reg0_Z[19]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.683	0.683	tINS	RR	578	IOT48[A]	clk_ibuf/O
1.883	1.201	tNET	RR	1	R38C59[1][A]	Mdu/u_mdu/reg0_fast_Z[13]/CLK
2.115	0.232	tC2Q	RF	8	R38C59[1][A]	Mdu/u_mdu/reg0_fast_Z[13]/Q
3.360	1.245	tNET	FF	1	R51C56[1][B]	Mdu/u_mdu/reg0_neg_axb_12_par_0_cp_cZ/I1
3.915	0.555	tINS	FF	1	R51C56[1][B]	Mdu/u_mdu/reg0_neg_axb_12_par_0_cp_cZ/F
4.814	0.899	tNET	FF	2	R52C56[2][B]	Mdu/u_mdu/reg0_neg_axb_12_par_cp_1/I0
5.384	0.570	tINS	FR	1	R52C56[2][B]	Mdu/u_mdu/reg0_neg_axb_12_par_cp_1/COUT
5.384	0.000	tNET	RR	2	R52C57[0][A]	Mdu/u_mdu/reg0_neg_axb_16_par_cp_1/CIN
5.419	0.035	tINS	RF	1	R52C57[0][A]	Mdu/u_mdu/reg0_neg_axb_16_par_cp_1/COUT
5.419	0.000	tNET	FF	2	R52C57[0][B]	Mdu/u_mdu/reg0_neg_axb_19_par_1/CIN
5.454	0.035	tINS	FF	1	R52C57[0][B]	Mdu/u_mdu/reg0_neg_axb_19_par_1/COUT
5.454	0.000	tNET	FF	2	R52C57[1][A]	Mdu/u_mdu/reg0_neg_axb_23_par_1/CIN
5.490	0.035	tINS	FF	1	R52C57[1][A]	Mdu/u_mdu/reg0_neg_axb_23_par_1/COUT
5.490	0.000	tNET	FF	2	R52C57[1][B]	Mdu/u_mdu/reg0_neg_axb_27_par_1/CIN
5.525	0.035	tINS	FF	1	R52C57[1][B]	Mdu/u_mdu/reg0_neg_axb_27_par_1/COUT
5.525	0.000	tNET	FF	2	R52C57[2][A]	Mdu/u_mdu/reg0_neg_axb_31_par_1/CIN
5.560	0.035	tINS	FF	1	R52C57[2][A]	Mdu/u_mdu/reg0_neg_axb_31_par_1/COUT
5.560	0.000	tNET	FF	2	R52C57[2][B]	Mdu/u_mdu/reg0_neg_cry_34_0/CIN
5.595	0.035	tINS	FF	1	R52C57[2][B]	Mdu/u_mdu/reg0_neg_cry_34_0/COUT
5.595	0.000	tNET	FF	2	R52C58[0][A]	Mdu/u_mdu/reg0_neg_cry_35_0/CIN
5.630	0.035	tINS	FF	1	R52C58[0][A]	Mdu/u_mdu/reg0_neg_cry_35_0/COUT
5.630	0.000	tNET	FF	2	R52C58[0][B]	Mdu/u_mdu/reg0_neg_cry_36_0/CIN
5.666	0.035	tINS	FF	1	R52C58[0][B]	Mdu/u_mdu/reg0_neg_cry_36_0/COUT
5.666	0.000	tNET	FF	2	R52C58[1][A]	Mdu/u_mdu/reg0_neg_cry_37_0/CIN
5.701	0.035	tINS	FF	1	R52C58[1][A]	Mdu/u_mdu/reg0_neg_cry_37_0/COUT
5.701	0.000	tNET	FF	2	R52C58[1][B]	Mdu/u_mdu/reg0_neg_cry_38_0/CIN
5.736	0.035	tINS	FF	1	R52C58[1][B]	Mdu/u_mdu/reg0_neg_cry_38_0/COUT
5.736	0.000	tNET	FF	2	R52C58[2][A]	Mdu/u_mdu/reg0_neg_cry_39_0/CIN
5.771	0.035	tINS	FF	1	R52C58[2][A]	Mdu/u_mdu/reg0_neg_cry_39_0/COUT
5.771	0.000	tNET	FF	2	R52C58[2][B]	Mdu/u_mdu/reg0_neg_cry_40_0/CIN
5.806	0.035	tINS	FF	1	R52C58[2][B]	Mdu/u_mdu/reg0_neg_cry_40_0/COUT
5.806	0.000	tNET	FF	2	R52C59[0][A]	Mdu/u_mdu/reg0_neg_cry_41_0/CIN
5.842	0.035	tINS	FF	1	R52C59[0][A]	Mdu/u_mdu/reg0_neg_cry_41_0/COUT
5.842	0.000	tNET	FF	2	R52C59[0][B]	Mdu/u_mdu/reg0_neg_cry_42_0/CIN
5.877	0.035	tINS	FF	1	R52C59[0][B]	Mdu/u_mdu/reg0_neg_cry_42_0/COUT
5.877	0.000	tNET	FF	2	R52C59[1][A]	Mdu/u_mdu/reg0_neg_cry_43_0/CIN
5.912	0.035	tINS	FF	1	R52C59[1][A]	Mdu/u_mdu/reg0_neg_cry_43_0/COUT
5.912	0.000	tNET	FF	2	R52C59[1][B]	Mdu/u_mdu/reg0_neg_cry_44_0/CIN
5.947	0.035	tINS	FF	1	R52C59[1][B]	Mdu/u_mdu/reg0_neg_cry_44_0/COUT
5.947	0.000	tNET	FF	2	R52C59[2][A]	Mdu/u_mdu/reg0_neg_cry_45_0/CIN
5.982	0.035	tINS	FF	1	R52C59[2][A]	Mdu/u_mdu/reg0_neg_cry_45_0/COUT
5.982	0.000	tNET	FF	2	R52C59[2][B]	Mdu/u_mdu/reg0_neg_cry_46_0/CIN
6.018	0.035	tINS	FF	1	R52C59[2][B]	Mdu/u_mdu/reg0_neg_cry_46_0/COUT
6.018	0.000	tNET	FF	2	R52C60[0][A]	Mdu/u_mdu/reg0_neg_cry_47_0/CIN
6.053	0.035	tINS	FF	1	R52C60[0][A]	Mdu/u_mdu/reg0_neg_cry_47_0/COUT
6.053	0.000	tNET	FF	2	R52C60[0][B]	Mdu/u_mdu/reg0_neg_cry_48_0/CIN
6.088	0.035	tINS	FF	1	R52C60[0][B]	Mdu/u_mdu/reg0_neg_cry_48_0/COUT
6.088	0.000	tNET	FF	2	R52C60[1][A]	Mdu/u_mdu/reg0_neg_cry_49_0/CIN
6.123	0.035	tINS	FF	1	R52C60[1][A]	Mdu/u_mdu/reg0_neg_cry_49_0/COUT
6.123	0.000	tNET	FF	2	R52C60[1][B]	Mdu/u_mdu/reg0_neg_cry_50_0/CIN
6.158	0.035	tINS	FF	1	R52C60[1][B]	Mdu/u_mdu/reg0_neg_cry_50_0/COUT
6.158	0.000	tNET	FF	2	R52C60[2][A]	Mdu/u_mdu/reg0_neg_cry_51_0/CIN
6.628	0.470	tINS	FF	1	R52C60[2][A]	Mdu/u_mdu/reg0_neg_cry_51_0/SUM
7.312	0.684	tNET	FF	1	R55C58[2][A]	Mdu/u_mdu/reg0_post_swap_2[19]/I2
7.829	0.517	tINS	FF	1	R55C58[2][A]	Mdu/u_mdu/reg0_post_swap_2[19]/F
7.829	0.000	tNET	FF	1	R55C58[2][A]	Mdu/u_mdu/reg0_post_swap_4[19]/I0
7.932	0.103	tINS	FF	2	R55C58[2][A]	Mdu/u_mdu/reg0_post_swap_4[19]/O
8.709	0.777	tNET	FF	1	R48C58[1][A]	Mdu/u_mdu/un11_reg0_nx_cZ[19]_cZ/I1
9.226	0.517	tINS	FF	3	R48C58[1][A]	Mdu/u_mdu/un11_reg0_nx_cZ[19]_cZ/F
10.473	1.247	tNET	FF	1	R37C57[2][B]	Mdu/u_mdu/reg0_nx_cZ[19]/I3
10.935	0.462	tINS	FR	1	R37C57[2][B]	Mdu/u_mdu/reg0_nx_cZ[19]/F
10.935	0.000	tNET	RR	1	R37C57[2][B]	Mdu/u_mdu/reg0_Z[19]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	578	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R37C57[2][B]	Mdu/u_mdu/reg0_Z[19]/CLK
11.683	-0.200	tUnc				Mdu/u_mdu/reg0_Z[19]
11.648	-0.035	tSu		1	R37C57[2][B]	Mdu/u_mdu/reg0_Z[19]

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 3.968, 43.840%; route: 4.852, 53.597%; tC2Q: 0.232, 2.563%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path12

Path Summary:

Slack	0.733
Data Arrival Time	10.915
Data Required Time	11.648
From	Mdu/u_mdu/div_shift_number_Z[0]
To	Mdu/u_mdu/reg0_Z[47]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.683	0.683	tINS	RR	578	IOT48[A]	clk_ibuf/O
1.883	1.201	tNET	RR	1	R29C56[1][A]	Mdu/u_mdu/div_shift_number_Z[0]/CLK
2.115	0.232	tC2Q	RF	113	R29C56[1][A]	Mdu/u_mdu/div_shift_number_Z[0]/Q
3.297	1.182	tNET	FF	1	R32C62[2][B]	Mdu/u_mdu/m27_0_03_1_cZ/I0
3.867	0.570	tINS	FR	1	R32C62[2][B]	Mdu/u_mdu/m27_0_03_1_cZ/F
4.039	0.172	tNET	RR	1	R32C63[3][B]	Mdu/u_mdu/m27_0_03_cZ/I1
4.594	0.555	tINS	RF	4	R32C63[3][B]	Mdu/u_mdu/m27_0_03_cZ/F
5.263	0.669	tNET	FF	1	R33C62[2][B]	Mdu/u_mdu/m31_2_03_1_0_cZ/I2
5.780	0.517	tINS	FF	2	R33C62[2][B]	Mdu/u_mdu/m31_2_03_1_0_cZ/F
6.547	0.766	tNET	FF	1	R37C59[3][B]	Mdu/u_mdu/m31_2_03_0_0_RNI5IJ8/I1
7.064	0.517	tINS	FF	2	R37C59[3][B]	Mdu/u_mdu/m31_2_03_0_0_RNI5IJ8/F
7.587	0.523	tNET	FF	1	R43C59[0][A]	Mdu/u_mdu/m47_4_03_0_0_cZ/I0
8.104	0.517	tINS	FF	1	R43C59[0][A]	Mdu/u_mdu/m47_4_03_0_0_cZ/F
9.002	0.899	tNET	FF	1	R46C59[0][B]	Mdu/u_mdu/reg0_exe_nx_m1_cZ[47]/I1
9.557	0.555	tINS	FF	1	R46C59[0][B]	Mdu/u_mdu/reg0_exe_nx_m1_cZ[47]/F
9.557	0.000	tNET	FF	1	R46C59[0][A]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[47]/I1
9.660	0.103	tINS	FF	1	R46C59[0][A]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[47]/O
10.544	0.884	tNET	FF	1	R52C63[0][B]	Mdu/u_mdu/reg0_nx_cZ[47]/I0
10.915	0.371	tINS	FF	1	R52C63[0][B]	Mdu/u_mdu/reg0_nx_cZ[47]/F
10.915	0.000	tNET	FF	1	R52C63[0][B]	Mdu/u_mdu/reg0_Z[47]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	578	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R52C63[0][B]	Mdu/u_mdu/reg0_Z[47]/CLK
11.683	-0.200	tUnc				Mdu/u_mdu/reg0_Z[47]
11.648	-0.035	tSu		1	R52C63[0][B]	Mdu/u_mdu/reg0_Z[47]

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	8
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 3.705, 41.020%; route: 5.095, 56.412%; tC2Q: 0.232, 2.569%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path13

Path Summary:

Slack	0.761
Data Arrival Time	10.888
Data Required Time	11.648
From	Mdu/u_mdu/reg0_fast_Z[13]
To	memq_memq_0_15
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.683	0.683	tINS	RR	578	IOT48[A]	clk_ibuf/O
1.883	1.201	tNET	RR	1	R38C59[1][A]	Mdu/u_mdu/reg0_fast_Z[13]/CLK
2.115	0.232	tC2Q	RF	8	R38C59[1][A]	Mdu/u_mdu/reg0_fast_Z[13]/Q
3.516	1.401	tNET	FF	1	R51C54[3][B]	Mdu/u_mdu/reg0_neg_axb_12_par_0_cp_0_cZ/I1
4.033	0.517	tINS	FF	1	R51C54[3][B]	Mdu/u_mdu/reg0_neg_axb_12_par_0_cp_0_cZ/F
4.960	0.927	tNET	FF	2	R56C51[2][B]	Mdu/u_mdu/reg0_neg_axb_12_par_cp_0_0/I0
5.530	0.570	tINS	FR	1	R56C51[2][B]	Mdu/u_mdu/reg0_neg_axb_12_par_cp_0_0/COUT
5.530	0.000	tNET	RR	2	R56C52[0][A]	Mdu/u_mdu/reg0_neg_axb_16_par_cp_0_0/CIN
5.565	0.035	tINS	RF	1	R56C52[0][A]	Mdu/u_mdu/reg0_neg_axb_16_par_cp_0_0/COUT
5.565	0.000	tNET	FF	2	R56C52[0][B]	Mdu/u_mdu/reg0_neg_axb_19_par_cp_0/CIN
5.600	0.035	tINS	FF	1	R56C52[0][B]	Mdu/u_mdu/reg0_neg_axb_19_par_cp_0/COUT
5.600	0.000	tNET	FF	2	R56C52[1][A]	Mdu/u_mdu/reg0_neg_axb_23_par_cp_0/CIN
5.635	0.035	tINS	FF	1	R56C52[1][A]	Mdu/u_mdu/reg0_neg_axb_23_par_cp_0/COUT
5.635	0.000	tNET	FF	2	R56C52[1][B]	Mdu/u_mdu/reg0_neg_axb_27_par_cp_0/CIN
5.671	0.035	tINS	FF	1	R56C52[1][B]	Mdu/u_mdu/reg0_neg_axb_27_par_cp_0/COUT
5.671	0.000	tNET	FF	2	R56C52[2][A]	Mdu/u_mdu/reg0_neg_axb_31_par_cp_0/CIN
5.706	0.035	tINS	FF	1	R56C52[2][A]	Mdu/u_mdu/reg0_neg_axb_31_par_cp_0/COUT
5.706	0.000	tNET	FF	2	R56C52[2][B]	Mdu/u_mdu/reg0_neg_axb_34_par_1/CIN
5.741	0.035	tINS	FF	1	R56C52[2][B]	Mdu/u_mdu/reg0_neg_axb_34_par_1/COUT
5.741	0.000	tNET	FF	2	R56C53[0][A]	Mdu/u_mdu/reg0_neg_axb_38_par_1/CIN
5.776	0.035	tINS	FF	1	R56C53[0][A]	Mdu/u_mdu/reg0_neg_axb_38_par_1/COUT
5.776	0.000	tNET	FF	2	R56C53[0][B]	Mdu/u_mdu/reg0_neg_axb_42_par_1/CIN
5.811	0.035	tINS	FF	1	R56C53[0][B]	Mdu/u_mdu/reg0_neg_axb_42_par_1/COUT
5.811	0.000	tNET	FF	2	R56C53[1][A]	Mdu/u_mdu/reg0_neg_axb_46_par_1/CIN
5.847	0.035	tINS	FF	1	R56C53[1][A]	Mdu/u_mdu/reg0_neg_axb_46_par_1/COUT
5.847	0.000	tNET	FF	2	R56C53[1][B]	Mdu/u_mdu/reg0_neg_axb_50_par_1/CIN
5.882	0.035	tINS	FF	1	R56C53[1][B]	Mdu/u_mdu/reg0_neg_axb_50_par_1/COUT
5.882	0.000	tNET	FF	2	R56C53[2][A]	Mdu/u_mdu/reg0_neg_cry_54_0/CIN
5.917	0.035	tINS	FF	1	R56C53[2][A]	Mdu/u_mdu/reg0_neg_cry_54_0/COUT
5.917	0.000	tNET	FF	2	R56C53[2][B]	Mdu/u_mdu/reg0_neg_cry_55_0/CIN
5.952	0.035	tINS	FF	1	R56C53[2][B]	Mdu/u_mdu/reg0_neg_cry_55_0/COUT
5.952	0.000	tNET	FF	2	R56C54[0][A]	Mdu/u_mdu/reg0_neg_cry_56_0/CIN
5.987	0.035	tINS	FF	1	R56C54[0][A]	Mdu/u_mdu/reg0_neg_cry_56_0/COUT
5.987	0.000	tNET	FF	2	R56C54[0][B]	Mdu/u_mdu/reg0_neg_cry_57_0/CIN
6.023	0.035	tINS	FF	1	R56C54[0][B]	Mdu/u_mdu/reg0_neg_cry_57_0/COUT
6.023	0.000	tNET	FF	2	R56C54[1][A]	Mdu/u_mdu/reg0_neg_cry_58_0/CIN
6.058	0.035	tINS	FF	1	R56C54[1][A]	Mdu/u_mdu/reg0_neg_cry_58_0/COUT
6.058	0.000	tNET	FF	2	R56C54[1][B]	Mdu/u_mdu/reg0_neg_cry_59_0/CIN
6.093	0.035	tINS	FF	1	R56C54[1][B]	Mdu/u_mdu/reg0_neg_cry_59_0/COUT
6.093	0.000	tNET	FF	2	R56C54[2][A]	Mdu/u_mdu/reg0_neg_cry_60_0/CIN
6.128	0.035	tINS	FF	1	R56C54[2][A]	Mdu/u_mdu/reg0_neg_cry_60_0/COUT
6.128	0.000	tNET	FF	2	R56C54[2][B]	Mdu/u_mdu/reg0_neg_cry_61_0/CIN
6.163	0.035	tINS	FF	1	R56C54[2][B]	Mdu/u_mdu/reg0_neg_cry_61_0/COUT
6.163	0.000	tNET	FF	2	R56C55[0][A]	Mdu/u_mdu/reg0_neg_cry_62_0/CIN
6.633	0.470	tINS	FF	1	R56C55[0][A]	Mdu/u_mdu/reg0_neg_cry_62_0/SUM
7.047	0.413	tNET	FF	1	R53C55[2][A]	Mdu/u_mdu/reg0_post_swap_2[30]/I2
7.564	0.517	tINS	FF	1	R53C55[2][A]	Mdu/u_mdu/reg0_post_swap_2[30]/F
7.564	0.000	tNET	FF	1	R53C55[2][A]	Mdu/u_mdu/reg0_post_swap_4[30]/I0
7.667	0.103	tINS	FF	2	R53C55[2][A]	Mdu/u_mdu/reg0_post_swap_4[30]/O
8.605	0.938	tNET	FF	1	R40C55[3][B]	Mdu/u_mdu/reg0_post_swap_5[30]/I1
9.160	0.555	tINS	FF	1	R40C55[3][B]	Mdu/u_mdu/reg0_post_swap_5[30]/F
9.407	0.247	tNET	FF	1	R38C55[1][B]	Mdu/u_mdu/res0_cZ[30]/I1
9.924	0.517	tINS	FF	3	R38C55[1][B]	Mdu/u_mdu/res0_cZ[30]/F
10.888	0.964	tNET	FF	1	BSRAM_R36[21]	memq_memq_0_15/DI0

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	578	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	BSRAM_R36[21]	memq_memq_0_15/CLKA
11.683	-0.200	tUnc				memq_memq_0_15
11.648	-0.035	tSu		1	BSRAM_R36[21]	memq_memq_0_15

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 3.883, 43.119%; route: 4.890, 54.305%; tC2Q: 0.232, 2.576%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path14

Path Summary:

Slack	0.782
Data Arrival Time	10.867
Data Required Time	11.648
From	Mdu/u_mdu/reg0_fast_Z[13]
To	memq_memq_0_6
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.683	0.683	tINS	RR	578	IOT48[A]	clk_ibuf/O
1.883	1.201	tNET	RR	1	R38C59[1][A]	Mdu/u_mdu/reg0_fast_Z[13]/CLK
2.115	0.232	tC2Q	RF	8	R38C59[1][A]	Mdu/u_mdu/reg0_fast_Z[13]/Q
3.360	1.245	tNET	FF	1	R51C56[1][B]	Mdu/u_mdu/reg0_neg_axb_12_par_0_cp_cZ/I1
3.915	0.555	tINS	FF	1	R51C56[1][B]	Mdu/u_mdu/reg0_neg_axb_12_par_0_cp_cZ/F
4.814	0.899	tNET	FF	2	R52C56[2][B]	Mdu/u_mdu/reg0_neg_axb_12_par_cp_1/I0
5.384	0.570	tINS	FR	1	R52C56[2][B]	Mdu/u_mdu/reg0_neg_axb_12_par_cp_1/COUT
5.384	0.000	tNET	RR	2	R52C57[0][A]	Mdu/u_mdu/reg0_neg_axb_16_par_cp_1/CIN
5.419	0.035	tINS	RF	1	R52C57[0][A]	Mdu/u_mdu/reg0_neg_axb_16_par_cp_1/COUT
5.419	0.000	tNET	FF	2	R52C57[0][B]	Mdu/u_mdu/reg0_neg_axb_19_par_1/CIN
5.454	0.035	tINS	FF	1	R52C57[0][B]	Mdu/u_mdu/reg0_neg_axb_19_par_1/COUT
5.454	0.000	tNET	FF	2	R52C57[1][A]	Mdu/u_mdu/reg0_neg_axb_23_par_1/CIN
5.490	0.035	tINS	FF	1	R52C57[1][A]	Mdu/u_mdu/reg0_neg_axb_23_par_1/COUT
5.490	0.000	tNET	FF	2	R52C57[1][B]	Mdu/u_mdu/reg0_neg_axb_27_par_1/CIN
5.525	0.035	tINS	FF	1	R52C57[1][B]	Mdu/u_mdu/reg0_neg_axb_27_par_1/COUT
5.525	0.000	tNET	FF	2	R52C57[2][A]	Mdu/u_mdu/reg0_neg_axb_31_par_1/CIN
5.560	0.035	tINS	FF	1	R52C57[2][A]	Mdu/u_mdu/reg0_neg_axb_31_par_1/COUT
5.560	0.000	tNET	FF	2	R52C57[2][B]	Mdu/u_mdu/reg0_neg_cry_34_0/CIN
5.595	0.035	tINS	FF	1	R52C57[2][B]	Mdu/u_mdu/reg0_neg_cry_34_0/COUT
5.595	0.000	tNET	FF	2	R52C58[0][A]	Mdu/u_mdu/reg0_neg_cry_35_0/CIN
5.630	0.035	tINS	FF	1	R52C58[0][A]	Mdu/u_mdu/reg0_neg_cry_35_0/COUT
5.630	0.000	tNET	FF	2	R52C58[0][B]	Mdu/u_mdu/reg0_neg_cry_36_0/CIN
5.666	0.035	tINS	FF	1	R52C58[0][B]	Mdu/u_mdu/reg0_neg_cry_36_0/COUT
5.666	0.000	tNET	FF	2	R52C58[1][A]	Mdu/u_mdu/reg0_neg_cry_37_0/CIN
5.701	0.035	tINS	FF	1	R52C58[1][A]	Mdu/u_mdu/reg0_neg_cry_37_0/COUT
5.701	0.000	tNET	FF	2	R52C58[1][B]	Mdu/u_mdu/reg0_neg_cry_38_0/CIN
5.736	0.035	tINS	FF	1	R52C58[1][B]	Mdu/u_mdu/reg0_neg_cry_38_0/COUT
5.736	0.000	tNET	FF	2	R52C58[2][A]	Mdu/u_mdu/reg0_neg_cry_39_0/CIN
5.771	0.035	tINS	FF	1	R52C58[2][A]	Mdu/u_mdu/reg0_neg_cry_39_0/COUT
5.771	0.000	tNET	FF	2	R52C58[2][B]	Mdu/u_mdu/reg0_neg_cry_40_0/CIN
5.806	0.035	tINS	FF	1	R52C58[2][B]	Mdu/u_mdu/reg0_neg_cry_40_0/COUT
5.806	0.000	tNET	FF	2	R52C59[0][A]	Mdu/u_mdu/reg0_neg_cry_41_0/CIN
5.842	0.035	tINS	FF	1	R52C59[0][A]	Mdu/u_mdu/reg0_neg_cry_41_0/COUT
5.842	0.000	tNET	FF	2	R52C59[0][B]	Mdu/u_mdu/reg0_neg_cry_42_0/CIN
5.877	0.035	tINS	FF	1	R52C59[0][B]	Mdu/u_mdu/reg0_neg_cry_42_0/COUT
5.877	0.000	tNET	FF	2	R52C59[1][A]	Mdu/u_mdu/reg0_neg_cry_43_0/CIN
5.912	0.035	tINS	FF	1	R52C59[1][A]	Mdu/u_mdu/reg0_neg_cry_43_0/COUT
5.912	0.000	tNET	FF	2	R52C59[1][B]	Mdu/u_mdu/reg0_neg_cry_44_0/CIN
6.382	0.470	tINS	FF	1	R52C59[1][B]	Mdu/u_mdu/reg0_neg_cry_44_0/SUM
6.900	0.518	tNET	FF	1	R48C57[1][A]	Mdu/u_mdu/reg0_post_swap_2[12]/I2
7.271	0.371	tINS	FF	1	R48C57[1][A]	Mdu/u_mdu/reg0_post_swap_2[12]/F
7.271	0.000	tNET	FF	1	R48C57[1][A]	Mdu/u_mdu/reg0_post_swap_4[12]/I0
7.374	0.103	tINS	FF	1	R48C57[1][A]	Mdu/u_mdu/reg0_post_swap_4[12]/O
8.651	1.277	tNET	FF	1	R41C60[3][B]	Mdu/u_mdu/reg0_post_swap_5[12]/I1
9.113	0.462	tINS	FR	3	R41C60[3][B]	Mdu/u_mdu/reg0_post_swap_5[12]/F
9.115	0.003	tNET	RR	1	R41C60[3][A]	Mdu/u_mdu/res0_cZ[12]/I1
9.632	0.517	tINS	RF	3	R41C60[3][A]	Mdu/u_mdu/res0_cZ[12]/F
10.867	1.235	tNET	FF	1	BSRAM_R54[17]	memq_memq_0_6/DI0

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	578	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	BSRAM_R54[17]	memq_memq_0_6/CLKA
11.683	-0.200	tUnc				memq_memq_0_6
11.648	-0.035	tSu		1	BSRAM_R54[17]	memq_memq_0_6

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 3.576, 39.805%; route: 5.176, 57.612%; tC2Q: 0.232, 2.582%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path15

Path Summary:

Slack	0.786
Data Arrival Time	10.862
Data Required Time	11.648
From	Mdu/u_mdu/reg0_fast_Z[13]
To	Mdu/u_mdu/reg0_19_rep1_Z
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.683	0.683	tINS	RR	578	IOT48[A]	clk_ibuf/O
1.883	1.201	tNET	RR	1	R38C59[1][A]	Mdu/u_mdu/reg0_fast_Z[13]/CLK
2.115	0.232	tC2Q	RF	8	R38C59[1][A]	Mdu/u_mdu/reg0_fast_Z[13]/Q
3.360	1.245	tNET	FF	1	R51C56[1][B]	Mdu/u_mdu/reg0_neg_axb_12_par_0_cp_cZ/I1
3.915	0.555	tINS	FF	1	R51C56[1][B]	Mdu/u_mdu/reg0_neg_axb_12_par_0_cp_cZ/F
4.814	0.899	tNET	FF	2	R52C56[2][B]	Mdu/u_mdu/reg0_neg_axb_12_par_cp_1/I0
5.384	0.570	tINS	FR	1	R52C56[2][B]	Mdu/u_mdu/reg0_neg_axb_12_par_cp_1/COUT
5.384	0.000	tNET	RR	2	R52C57[0][A]	Mdu/u_mdu/reg0_neg_axb_16_par_cp_1/CIN
5.419	0.035	tINS	RF	1	R52C57[0][A]	Mdu/u_mdu/reg0_neg_axb_16_par_cp_1/COUT
5.419	0.000	tNET	FF	2	R52C57[0][B]	Mdu/u_mdu/reg0_neg_axb_19_par_1/CIN
5.454	0.035	tINS	FF	1	R52C57[0][B]	Mdu/u_mdu/reg0_neg_axb_19_par_1/COUT
5.454	0.000	tNET	FF	2	R52C57[1][A]	Mdu/u_mdu/reg0_neg_axb_23_par_1/CIN
5.490	0.035	tINS	FF	1	R52C57[1][A]	Mdu/u_mdu/reg0_neg_axb_23_par_1/COUT
5.490	0.000	tNET	FF	2	R52C57[1][B]	Mdu/u_mdu/reg0_neg_axb_27_par_1/CIN
5.525	0.035	tINS	FF	1	R52C57[1][B]	Mdu/u_mdu/reg0_neg_axb_27_par_1/COUT
5.525	0.000	tNET	FF	2	R52C57[2][A]	Mdu/u_mdu/reg0_neg_axb_31_par_1/CIN
5.560	0.035	tINS	FF	1	R52C57[2][A]	Mdu/u_mdu/reg0_neg_axb_31_par_1/COUT
5.560	0.000	tNET	FF	2	R52C57[2][B]	Mdu/u_mdu/reg0_neg_cry_34_0/CIN
5.595	0.035	tINS	FF	1	R52C57[2][B]	Mdu/u_mdu/reg0_neg_cry_34_0/COUT
5.595	0.000	tNET	FF	2	R52C58[0][A]	Mdu/u_mdu/reg0_neg_cry_35_0/CIN
5.630	0.035	tINS	FF	1	R52C58[0][A]	Mdu/u_mdu/reg0_neg_cry_35_0/COUT
5.630	0.000	tNET	FF	2	R52C58[0][B]	Mdu/u_mdu/reg0_neg_cry_36_0/CIN
5.666	0.035	tINS	FF	1	R52C58[0][B]	Mdu/u_mdu/reg0_neg_cry_36_0/COUT
5.666	0.000	tNET	FF	2	R52C58[1][A]	Mdu/u_mdu/reg0_neg_cry_37_0/CIN
5.701	0.035	tINS	FF	1	R52C58[1][A]	Mdu/u_mdu/reg0_neg_cry_37_0/COUT
5.701	0.000	tNET	FF	2	R52C58[1][B]	Mdu/u_mdu/reg0_neg_cry_38_0/CIN
5.736	0.035	tINS	FF	1	R52C58[1][B]	Mdu/u_mdu/reg0_neg_cry_38_0/COUT
5.736	0.000	tNET	FF	2	R52C58[2][A]	Mdu/u_mdu/reg0_neg_cry_39_0/CIN
5.771	0.035	tINS	FF	1	R52C58[2][A]	Mdu/u_mdu/reg0_neg_cry_39_0/COUT
5.771	0.000	tNET	FF	2	R52C58[2][B]	Mdu/u_mdu/reg0_neg_cry_40_0/CIN
5.806	0.035	tINS	FF	1	R52C58[2][B]	Mdu/u_mdu/reg0_neg_cry_40_0/COUT
5.806	0.000	tNET	FF	2	R52C59[0][A]	Mdu/u_mdu/reg0_neg_cry_41_0/CIN
5.842	0.035	tINS	FF	1	R52C59[0][A]	Mdu/u_mdu/reg0_neg_cry_41_0/COUT
5.842	0.000	tNET	FF	2	R52C59[0][B]	Mdu/u_mdu/reg0_neg_cry_42_0/CIN
5.877	0.035	tINS	FF	1	R52C59[0][B]	Mdu/u_mdu/reg0_neg_cry_42_0/COUT
5.877	0.000	tNET	FF	2	R52C59[1][A]	Mdu/u_mdu/reg0_neg_cry_43_0/CIN
5.912	0.035	tINS	FF	1	R52C59[1][A]	Mdu/u_mdu/reg0_neg_cry_43_0/COUT
5.912	0.000	tNET	FF	2	R52C59[1][B]	Mdu/u_mdu/reg0_neg_cry_44_0/CIN
5.947	0.035	tINS	FF	1	R52C59[1][B]	Mdu/u_mdu/reg0_neg_cry_44_0/COUT
5.947	0.000	tNET	FF	2	R52C59[2][A]	Mdu/u_mdu/reg0_neg_cry_45_0/CIN
5.982	0.035	tINS	FF	1	R52C59[2][A]	Mdu/u_mdu/reg0_neg_cry_45_0/COUT
5.982	0.000	tNET	FF	2	R52C59[2][B]	Mdu/u_mdu/reg0_neg_cry_46_0/CIN
6.018	0.035	tINS	FF	1	R52C59[2][B]	Mdu/u_mdu/reg0_neg_cry_46_0/COUT
6.018	0.000	tNET	FF	2	R52C60[0][A]	Mdu/u_mdu/reg0_neg_cry_47_0/CIN
6.053	0.035	tINS	FF	1	R52C60[0][A]	Mdu/u_mdu/reg0_neg_cry_47_0/COUT
6.053	0.000	tNET	FF	2	R52C60[0][B]	Mdu/u_mdu/reg0_neg_cry_48_0/CIN
6.088	0.035	tINS	FF	1	R52C60[0][B]	Mdu/u_mdu/reg0_neg_cry_48_0/COUT
6.088	0.000	tNET	FF	2	R52C60[1][A]	Mdu/u_mdu/reg0_neg_cry_49_0/CIN
6.123	0.035	tINS	FF	1	R52C60[1][A]	Mdu/u_mdu/reg0_neg_cry_49_0/COUT
6.123	0.000	tNET	FF	2	R52C60[1][B]	Mdu/u_mdu/reg0_neg_cry_50_0/CIN
6.158	0.035	tINS	FF	1	R52C60[1][B]	Mdu/u_mdu/reg0_neg_cry_50_0/COUT
6.158	0.000	tNET	FF	2	R52C60[2][A]	Mdu/u_mdu/reg0_neg_cry_51_0/CIN
6.628	0.470	tINS	FF	1	R52C60[2][A]	Mdu/u_mdu/reg0_neg_cry_51_0/SUM
7.312	0.684	tNET	FF	1	R55C58[2][A]	Mdu/u_mdu/reg0_post_swap_2[19]/I2
7.829	0.517	tINS	FF	1	R55C58[2][A]	Mdu/u_mdu/reg0_post_swap_2[19]/F
7.829	0.000	tNET	FF	1	R55C58[2][A]	Mdu/u_mdu/reg0_post_swap_4[19]/I0
7.932	0.103	tINS	FF	2	R55C58[2][A]	Mdu/u_mdu/reg0_post_swap_4[19]/O
8.709	0.777	tNET	FF	1	R48C58[1][A]	Mdu/u_mdu/un11_reg0_nx_cZ[19]_cZ/I1
9.226	0.517	tINS	FF	3	R48C58[1][A]	Mdu/u_mdu/un11_reg0_nx_cZ[19]_cZ/F
10.400	1.174	tNET	FF	1	R37C58[1][A]	Mdu/u_mdu/reg0_nx_rep1_cZ[19]/I3
10.862	0.462	tINS	FR	1	R37C58[1][A]	Mdu/u_mdu/reg0_nx_rep1_cZ[19]/F
10.862	0.000	tNET	RR	1	R37C58[1][A]	Mdu/u_mdu/reg0_19_rep1_Z/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	578	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R37C58[1][A]	Mdu/u_mdu/reg0_19_rep1_Z/CLK
11.683	-0.200	tUnc				Mdu/u_mdu/reg0_19_rep1_Z
11.648	-0.035	tSu		1	R37C58[1][A]	Mdu/u_mdu/reg0_19_rep1_Z

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 3.968, 44.197%; route: 4.779, 53.219%; tC2Q: 0.232, 2.584%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path16

Path Summary:

Slack	0.804
Data Arrival Time	10.844
Data Required Time	11.648
From	Mdu/u_mdu/rs1_mul_Z[5]
To	Mdu/u_mdu/reg0_Z[36]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.683	0.683	tINS	RR	578	IOT48[A]	clk_ibuf/O
1.883	1.201	tNET	RR	1	R46C62[1][A]	Mdu/u_mdu/rs1_mul_Z[5]/CLK
2.115	0.232	tC2Q	RF	1	R46C62[1][A]	Mdu/u_mdu/rs1_mul_Z[5]/Q
3.013	0.898	tNET	FF	1	R46C62[3][B]	Mdu/u_mdu/adder_sum_s_5_sf_lofx_cZ/I2
3.568	0.555	tINS	FF	1	R46C62[3][B]	Mdu/u_mdu/adder_sum_s_5_sf_lofx_cZ/F
4.252	0.684	tNET	FF	2	R47C58[0][B]	Mdu/u_mdu/adder_sum_cry_5_0/I0
4.822	0.570	tINS	FR	1	R47C58[0][B]	Mdu/u_mdu/adder_sum_cry_5_0/COUT
4.822	0.000	tNET	RR	2	R47C58[1][A]	Mdu/u_mdu/adder_sum_cry_6_0/CIN
4.857	0.035	tINS	RF	1	R47C58[1][A]	Mdu/u_mdu/adder_sum_cry_6_0/COUT
4.857	0.000	tNET	FF	2	R47C58[1][B]	Mdu/u_mdu/adder_sum_cry_7_0/CIN
4.892	0.035	tINS	FF	1	R47C58[1][B]	Mdu/u_mdu/adder_sum_cry_7_0/COUT
4.892	0.000	tNET	FF	2	R47C58[2][A]	Mdu/u_mdu/adder_sum_cry_8_0/CIN
4.927	0.035	tINS	FF	1	R47C58[2][A]	Mdu/u_mdu/adder_sum_cry_8_0/COUT
4.927	0.000	tNET	FF	2	R47C58[2][B]	Mdu/u_mdu/adder_sum_cry_9_0/CIN
4.963	0.035	tINS	FF	1	R47C58[2][B]	Mdu/u_mdu/adder_sum_cry_9_0/COUT
4.963	0.000	tNET	FF	2	R47C59[0][A]	Mdu/u_mdu/adder_sum_cry_10_0/CIN
4.998	0.035	tINS	FF	1	R47C59[0][A]	Mdu/u_mdu/adder_sum_cry_10_0/COUT
4.998	0.000	tNET	FF	2	R47C59[0][B]	Mdu/u_mdu/adder_sum_cry_11_0/CIN
5.033	0.035	tINS	FF	1	R47C59[0][B]	Mdu/u_mdu/adder_sum_cry_11_0/COUT
5.033	0.000	tNET	FF	2	R47C59[1][A]	Mdu/u_mdu/adder_sum_cry_12_0/CIN
5.068	0.035	tINS	FF	1	R47C59[1][A]	Mdu/u_mdu/adder_sum_cry_12_0/COUT
5.068	0.000	tNET	FF	2	R47C59[1][B]	Mdu/u_mdu/adder_sum_cry_13_0/CIN
5.103	0.035	tINS	FF	1	R47C59[1][B]	Mdu/u_mdu/adder_sum_cry_13_0/COUT
5.103	0.000	tNET	FF	2	R47C59[2][A]	Mdu/u_mdu/adder_sum_cry_14_0/CIN
5.139	0.035	tINS	FF	1	R47C59[2][A]	Mdu/u_mdu/adder_sum_cry_14_0/COUT
5.139	0.000	tNET	FF	2	R47C59[2][B]	Mdu/u_mdu/adder_sum_cry_15_0/CIN
5.174	0.035	tINS	FF	1	R47C59[2][B]	Mdu/u_mdu/adder_sum_cry_15_0/COUT
5.174	0.000	tNET	FF	2	R47C60[0][A]	Mdu/u_mdu/adder_sum_cry_16_0/CIN
5.209	0.035	tINS	FF	1	R47C60[0][A]	Mdu/u_mdu/adder_sum_cry_16_0/COUT
5.209	0.000	tNET	FF	2	R47C60[0][B]	Mdu/u_mdu/adder_sum_cry_17_0/CIN
5.244	0.035	tINS	FF	1	R47C60[0][B]	Mdu/u_mdu/adder_sum_cry_17_0/COUT
5.244	0.000	tNET	FF	2	R47C60[1][A]	Mdu/u_mdu/adder_sum_cry_18_0/CIN
5.279	0.035	tINS	FF	1	R47C60[1][A]	Mdu/u_mdu/adder_sum_cry_18_0/COUT
5.279	0.000	tNET	FF	2	R47C60[1][B]	Mdu/u_mdu/adder_sum_cry_19_0/CIN
5.315	0.035	tINS	FF	1	R47C60[1][B]	Mdu/u_mdu/adder_sum_cry_19_0/COUT
5.315	0.000	tNET	FF	2	R47C60[2][A]	Mdu/u_mdu/adder_sum_cry_20_0/CIN
5.350	0.035	tINS	FF	1	R47C60[2][A]	Mdu/u_mdu/adder_sum_cry_20_0/COUT
5.350	0.000	tNET	FF	2	R47C60[2][B]	Mdu/u_mdu/adder_sum_cry_21_0/CIN
5.385	0.035	tINS	FF	1	R47C60[2][B]	Mdu/u_mdu/adder_sum_cry_21_0/COUT
5.385	0.000	tNET	FF	2	R47C61[0][A]	Mdu/u_mdu/adder_sum_cry_22_0/CIN
5.420	0.035	tINS	FF	1	R47C61[0][A]	Mdu/u_mdu/adder_sum_cry_22_0/COUT
5.420	0.000	tNET	FF	2	R47C61[0][B]	Mdu/u_mdu/adder_sum_cry_23_0/CIN
5.455	0.035	tINS	FF	1	R47C61[0][B]	Mdu/u_mdu/adder_sum_cry_23_0/COUT
5.455	0.000	tNET	FF	2	R47C61[1][A]	Mdu/u_mdu/adder_sum_cry_24_0/CIN
5.491	0.035	tINS	FF	1	R47C61[1][A]	Mdu/u_mdu/adder_sum_cry_24_0/COUT
5.491	0.000	tNET	FF	2	R47C61[1][B]	Mdu/u_mdu/adder_sum_cry_25_0/CIN
5.526	0.035	tINS	FF	1	R47C61[1][B]	Mdu/u_mdu/adder_sum_cry_25_0/COUT
5.526	0.000	tNET	FF	2	R47C61[2][A]	Mdu/u_mdu/adder_sum_cry_26_0/CIN
5.561	0.035	tINS	FF	1	R47C61[2][A]	Mdu/u_mdu/adder_sum_cry_26_0/COUT
5.561	0.000	tNET	FF	2	R47C61[2][B]	Mdu/u_mdu/adder_sum_cry_27_0/CIN
5.596	0.035	tINS	FF	1	R47C61[2][B]	Mdu/u_mdu/adder_sum_cry_27_0/COUT
5.596	0.000	tNET	FF	2	R47C62[0][A]	Mdu/u_mdu/adder_sum_cry_28_0/CIN
5.631	0.035	tINS	FF	1	R47C62[0][A]	Mdu/u_mdu/adder_sum_cry_28_0/COUT
5.631	0.000	tNET	FF	2	R47C62[0][B]	Mdu/u_mdu/adder_sum_cry_29_0/CIN
5.667	0.035	tINS	FF	1	R47C62[0][B]	Mdu/u_mdu/adder_sum_cry_29_0/COUT
5.667	0.000	tNET	FF	2	R47C62[1][A]	Mdu/u_mdu/adder_sum_cry_30_0/CIN
5.702	0.035	tINS	FF	1	R47C62[1][A]	Mdu/u_mdu/adder_sum_cry_30_0/COUT
5.702	0.000	tNET	FF	2	R47C62[1][B]	Mdu/u_mdu/adder_sum_cry_31_0/CIN
5.737	0.035	tINS	FF	1	R47C62[1][B]	Mdu/u_mdu/adder_sum_cry_31_0/COUT
5.737	0.000	tNET	FF	2	R47C62[2][A]	Mdu/u_mdu/adder_sum_s_32_0/CIN
6.207	0.470	tINS	FF	6	R47C62[2][A]	Mdu/u_mdu/adder_sum_s_32_0/SUM
7.175	0.968	tNET	FF	1	R37C55[1][B]	Mdu/u_mdu/reg0_exe_nx_ss0_cZ/I0
7.692	0.517	tINS	FF	50	R37C55[1][B]	Mdu/u_mdu/reg0_exe_nx_ss0_cZ/F
8.536	0.844	tNET	FF	1	R31C59[2][A]	Mdu/u_mdu/reg0_exe_nx_m0_cZ[36]/I2
8.989	0.453	tINS	FF	1	R31C59[2][A]	Mdu/u_mdu/reg0_exe_nx_m0_cZ[36]/F
8.989	0.000	tNET	FF	1	R31C59[2][A]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[36]/I0
9.092	0.103	tINS	FF	1	R31C59[2][A]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[36]/O
10.295	1.203	tNET	FF	1	R50C61[2][A]	Mdu/u_mdu/reg0_nx_0[36]/I2
10.844	0.549	tINS	FR	1	R50C61[2][A]	Mdu/u_mdu/reg0_nx_0[36]/F
10.844	0.000	tNET	RR	1	R50C61[2][A]	Mdu/u_mdu/reg0_Z[36]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	578	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R50C61[2][A]	Mdu/u_mdu/reg0_Z[36]/CLK
11.683	-0.200	tUnc				Mdu/u_mdu/reg0_Z[36]
11.648	-0.035	tSu		1	R50C61[2][A]	Mdu/u_mdu/reg0_Z[36]

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 4.132, 46.112%; route: 4.597, 51.299%; tC2Q: 0.232, 2.589%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path17

Path Summary:

Slack	0.834
Data Arrival Time	10.815
Data Required Time	11.648
From	Mdu/u_mdu/div_shift_number_Z[0]
To	Mdu/u_mdu/reg0_Z[43]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.683	0.683	tINS	RR	578	IOT48[A]	clk_ibuf/O
1.883	1.201	tNET	RR	1	R29C56[1][A]	Mdu/u_mdu/div_shift_number_Z[0]/CLK
2.115	0.232	tC2Q	RF	113	R29C56[1][A]	Mdu/u_mdu/div_shift_number_Z[0]/Q
3.297	1.182	tNET	FF	1	R32C62[2][B]	Mdu/u_mdu/m27_0_03_1_cZ/I0
3.867	0.570	tINS	FR	1	R32C62[2][B]	Mdu/u_mdu/m27_0_03_1_cZ/F
4.039	0.172	tNET	RR	1	R32C63[3][B]	Mdu/u_mdu/m27_0_03_cZ/I1
4.594	0.555	tINS	RF	4	R32C63[3][B]	Mdu/u_mdu/m27_0_03_cZ/F
5.263	0.669	tNET	FF	1	R33C62[3][B]	Mdu/u_mdu/m27_2_03_1_0_cZ/I3
5.818	0.555	tINS	FF	2	R33C62[3][B]	Mdu/u_mdu/m27_2_03_1_0_cZ/F
6.237	0.419	tNET	FF	1	R35C62[3][A]	Mdu/u_mdu/m27_2_03_0_0_RNIFACJ/I1
6.792	0.555	tINS	FF	2	R35C62[3][A]	Mdu/u_mdu/m27_2_03_0_0_RNIFACJ/F
7.211	0.419	tNET	FF	1	R38C62[1][A]	Mdu/u_mdu/m43_4_03_0_0_cZ/I0
7.582	0.371	tINS	FF	1	R38C62[1][A]	Mdu/u_mdu/m43_4_03_0_0_cZ/F
8.675	1.093	tNET	FF	1	R47C59[3][B]	Mdu/u_mdu/reg0_exe_nx_m1_cZ[43]/I1
9.230	0.555	tINS	FF	1	R47C59[3][B]	Mdu/u_mdu/reg0_exe_nx_m1_cZ[43]/F
9.230	0.000	tNET	FF	1	R47C59[3][A]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[43]/I1
9.333	0.103	tINS	FF	1	R47C59[3][A]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[43]/O
10.266	0.933	tNET	FF	1	R52C63[2][A]	Mdu/u_mdu/reg0_nx_cZ[43]/I0
10.815	0.549	tINS	FR	1	R52C63[2][A]	Mdu/u_mdu/reg0_nx_cZ[43]/F
10.815	0.000	tNET	RR	1	R52C63[2][A]	Mdu/u_mdu/reg0_Z[43]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	578	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R52C63[2][A]	Mdu/u_mdu/reg0_Z[43]/CLK
11.683	-0.200	tUnc				Mdu/u_mdu/reg0_Z[43]
11.648	-0.035	tSu		1	R52C63[2][A]	Mdu/u_mdu/reg0_Z[43]

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	8
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 3.813, 42.692%; route: 4.886, 54.710%; tC2Q: 0.232, 2.598%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path18

Path Summary:

Slack	0.856
Data Arrival Time	10.793
Data Required Time	11.648
From	Mdu/u_mdu/reg0_fast_Z[13]
To	memq_memq_0_7
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.683	0.683	tINS	RR	578	IOT48[A]	clk_ibuf/O
1.883	1.201	tNET	RR	1	R38C59[1][A]	Mdu/u_mdu/reg0_fast_Z[13]/CLK
2.115	0.232	tC2Q	RF	8	R38C59[1][A]	Mdu/u_mdu/reg0_fast_Z[13]/Q
3.360	1.245	tNET	FF	1	R51C56[1][B]	Mdu/u_mdu/reg0_neg_axb_12_par_0_cp_cZ/I1
3.915	0.555	tINS	FF	1	R51C56[1][B]	Mdu/u_mdu/reg0_neg_axb_12_par_0_cp_cZ/F
4.814	0.899	tNET	FF	2	R52C56[2][B]	Mdu/u_mdu/reg0_neg_axb_12_par_cp_1/I0
5.384	0.570	tINS	FR	1	R52C56[2][B]	Mdu/u_mdu/reg0_neg_axb_12_par_cp_1/COUT
5.384	0.000	tNET	RR	2	R52C57[0][A]	Mdu/u_mdu/reg0_neg_axb_16_par_cp_1/CIN
5.419	0.035	tINS	RF	1	R52C57[0][A]	Mdu/u_mdu/reg0_neg_axb_16_par_cp_1/COUT
5.419	0.000	tNET	FF	2	R52C57[0][B]	Mdu/u_mdu/reg0_neg_axb_19_par_1/CIN
5.454	0.035	tINS	FF	1	R52C57[0][B]	Mdu/u_mdu/reg0_neg_axb_19_par_1/COUT
5.454	0.000	tNET	FF	2	R52C57[1][A]	Mdu/u_mdu/reg0_neg_axb_23_par_1/CIN
5.490	0.035	tINS	FF	1	R52C57[1][A]	Mdu/u_mdu/reg0_neg_axb_23_par_1/COUT
5.490	0.000	tNET	FF	2	R52C57[1][B]	Mdu/u_mdu/reg0_neg_axb_27_par_1/CIN
5.525	0.035	tINS	FF	1	R52C57[1][B]	Mdu/u_mdu/reg0_neg_axb_27_par_1/COUT
5.525	0.000	tNET	FF	2	R52C57[2][A]	Mdu/u_mdu/reg0_neg_axb_31_par_1/CIN
5.560	0.035	tINS	FF	1	R52C57[2][A]	Mdu/u_mdu/reg0_neg_axb_31_par_1/COUT
5.560	0.000	tNET	FF	2	R52C57[2][B]	Mdu/u_mdu/reg0_neg_cry_34_0/CIN
5.595	0.035	tINS	FF	1	R52C57[2][B]	Mdu/u_mdu/reg0_neg_cry_34_0/COUT
5.595	0.000	tNET	FF	2	R52C58[0][A]	Mdu/u_mdu/reg0_neg_cry_35_0/CIN
5.630	0.035	tINS	FF	1	R52C58[0][A]	Mdu/u_mdu/reg0_neg_cry_35_0/COUT
5.630	0.000	tNET	FF	2	R52C58[0][B]	Mdu/u_mdu/reg0_neg_cry_36_0/CIN
5.666	0.035	tINS	FF	1	R52C58[0][B]	Mdu/u_mdu/reg0_neg_cry_36_0/COUT
5.666	0.000	tNET	FF	2	R52C58[1][A]	Mdu/u_mdu/reg0_neg_cry_37_0/CIN
5.701	0.035	tINS	FF	1	R52C58[1][A]	Mdu/u_mdu/reg0_neg_cry_37_0/COUT
5.701	0.000	tNET	FF	2	R52C58[1][B]	Mdu/u_mdu/reg0_neg_cry_38_0/CIN
5.736	0.035	tINS	FF	1	R52C58[1][B]	Mdu/u_mdu/reg0_neg_cry_38_0/COUT
5.736	0.000	tNET	FF	2	R52C58[2][A]	Mdu/u_mdu/reg0_neg_cry_39_0/CIN
5.771	0.035	tINS	FF	1	R52C58[2][A]	Mdu/u_mdu/reg0_neg_cry_39_0/COUT
5.771	0.000	tNET	FF	2	R52C58[2][B]	Mdu/u_mdu/reg0_neg_cry_40_0/CIN
5.806	0.035	tINS	FF	1	R52C58[2][B]	Mdu/u_mdu/reg0_neg_cry_40_0/COUT
5.806	0.000	tNET	FF	2	R52C59[0][A]	Mdu/u_mdu/reg0_neg_cry_41_0/CIN
5.842	0.035	tINS	FF	1	R52C59[0][A]	Mdu/u_mdu/reg0_neg_cry_41_0/COUT
5.842	0.000	tNET	FF	2	R52C59[0][B]	Mdu/u_mdu/reg0_neg_cry_42_0/CIN
5.877	0.035	tINS	FF	1	R52C59[0][B]	Mdu/u_mdu/reg0_neg_cry_42_0/COUT
5.877	0.000	tNET	FF	2	R52C59[1][A]	Mdu/u_mdu/reg0_neg_cry_43_0/CIN
5.912	0.035	tINS	FF	1	R52C59[1][A]	Mdu/u_mdu/reg0_neg_cry_43_0/COUT
5.912	0.000	tNET	FF	2	R52C59[1][B]	Mdu/u_mdu/reg0_neg_cry_44_0/CIN
5.947	0.035	tINS	FF	1	R52C59[1][B]	Mdu/u_mdu/reg0_neg_cry_44_0/COUT
5.947	0.000	tNET	FF	2	R52C59[2][A]	Mdu/u_mdu/reg0_neg_cry_45_0/CIN
5.982	0.035	tINS	FF	1	R52C59[2][A]	Mdu/u_mdu/reg0_neg_cry_45_0/COUT
5.982	0.000	tNET	FF	2	R52C59[2][B]	Mdu/u_mdu/reg0_neg_cry_46_0/CIN
6.018	0.035	tINS	FF	1	R52C59[2][B]	Mdu/u_mdu/reg0_neg_cry_46_0/COUT
6.018	0.000	tNET	FF	2	R52C60[0][A]	Mdu/u_mdu/reg0_neg_cry_47_0/CIN
6.488	0.470	tINS	FF	1	R52C60[0][A]	Mdu/u_mdu/reg0_neg_cry_47_0/SUM
6.901	0.413	tNET	FF	1	R51C59[3][A]	Mdu/u_mdu/reg0_post_swap_2[15]/I2
7.456	0.555	tINS	FF	1	R51C59[3][A]	Mdu/u_mdu/reg0_post_swap_2[15]/F
7.456	0.000	tNET	FF	1	R51C59[3][A]	Mdu/u_mdu/reg0_post_swap_4[15]/I0
7.559	0.103	tINS	FF	1	R51C59[3][A]	Mdu/u_mdu/reg0_post_swap_4[15]/O
8.734	1.175	tNET	FF	1	R42C60[1][B]	Mdu/u_mdu/reg0_post_swap_5[15]/I1
9.105	0.371	tINS	FF	3	R42C60[1][B]	Mdu/u_mdu/reg0_post_swap_5[15]/F
9.870	0.765	tNET	FF	1	R38C56[3][A]	Mdu/u_mdu/res0_cZ[15]/I1
10.387	0.517	tINS	FF	3	R38C56[3][A]	Mdu/u_mdu/res0_cZ[15]/F
10.793	0.406	tNET	FF	1	BSRAM_R36[17]	memq_memq_0_7/DI1

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	578	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	BSRAM_R36[17]	memq_memq_0_7/CLKA
11.683	-0.200	tUnc				memq_memq_0_7
11.648	-0.035	tSu		1	BSRAM_R36[17]	memq_memq_0_7

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 3.775, 42.365%; route: 4.903, 55.031%; tC2Q: 0.232, 2.604%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path19

Path Summary:

Slack	0.861
Data Arrival Time	10.787
Data Required Time	11.648
From	Mdu/u_mdu/rs1_mul_Z[5]
To	Mdu/u_mdu/reg0_Z[45]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.683	0.683	tINS	RR	578	IOT48[A]	clk_ibuf/O
1.883	1.201	tNET	RR	1	R46C62[1][A]	Mdu/u_mdu/rs1_mul_Z[5]/CLK
2.115	0.232	tC2Q	RF	1	R46C62[1][A]	Mdu/u_mdu/rs1_mul_Z[5]/Q
3.013	0.898	tNET	FF	1	R46C62[3][B]	Mdu/u_mdu/adder_sum_s_5_sf_lofx_cZ/I2
3.568	0.555	tINS	FF	1	R46C62[3][B]	Mdu/u_mdu/adder_sum_s_5_sf_lofx_cZ/F
4.252	0.684	tNET	FF	2	R47C58[0][B]	Mdu/u_mdu/adder_sum_cry_5_0/I0
4.822	0.570	tINS	FR	1	R47C58[0][B]	Mdu/u_mdu/adder_sum_cry_5_0/COUT
4.822	0.000	tNET	RR	2	R47C58[1][A]	Mdu/u_mdu/adder_sum_cry_6_0/CIN
4.857	0.035	tINS	RF	1	R47C58[1][A]	Mdu/u_mdu/adder_sum_cry_6_0/COUT
4.857	0.000	tNET	FF	2	R47C58[1][B]	Mdu/u_mdu/adder_sum_cry_7_0/CIN
4.892	0.035	tINS	FF	1	R47C58[1][B]	Mdu/u_mdu/adder_sum_cry_7_0/COUT
4.892	0.000	tNET	FF	2	R47C58[2][A]	Mdu/u_mdu/adder_sum_cry_8_0/CIN
4.927	0.035	tINS	FF	1	R47C58[2][A]	Mdu/u_mdu/adder_sum_cry_8_0/COUT
4.927	0.000	tNET	FF	2	R47C58[2][B]	Mdu/u_mdu/adder_sum_cry_9_0/CIN
4.963	0.035	tINS	FF	1	R47C58[2][B]	Mdu/u_mdu/adder_sum_cry_9_0/COUT
4.963	0.000	tNET	FF	2	R47C59[0][A]	Mdu/u_mdu/adder_sum_cry_10_0/CIN
4.998	0.035	tINS	FF	1	R47C59[0][A]	Mdu/u_mdu/adder_sum_cry_10_0/COUT
4.998	0.000	tNET	FF	2	R47C59[0][B]	Mdu/u_mdu/adder_sum_cry_11_0/CIN
5.033	0.035	tINS	FF	1	R47C59[0][B]	Mdu/u_mdu/adder_sum_cry_11_0/COUT
5.033	0.000	tNET	FF	2	R47C59[1][A]	Mdu/u_mdu/adder_sum_cry_12_0/CIN
5.068	0.035	tINS	FF	1	R47C59[1][A]	Mdu/u_mdu/adder_sum_cry_12_0/COUT
5.068	0.000	tNET	FF	2	R47C59[1][B]	Mdu/u_mdu/adder_sum_cry_13_0/CIN
5.103	0.035	tINS	FF	1	R47C59[1][B]	Mdu/u_mdu/adder_sum_cry_13_0/COUT
5.103	0.000	tNET	FF	2	R47C59[2][A]	Mdu/u_mdu/adder_sum_cry_14_0/CIN
5.139	0.035	tINS	FF	1	R47C59[2][A]	Mdu/u_mdu/adder_sum_cry_14_0/COUT
5.139	0.000	tNET	FF	2	R47C59[2][B]	Mdu/u_mdu/adder_sum_cry_15_0/CIN
5.174	0.035	tINS	FF	1	R47C59[2][B]	Mdu/u_mdu/adder_sum_cry_15_0/COUT
5.174	0.000	tNET	FF	2	R47C60[0][A]	Mdu/u_mdu/adder_sum_cry_16_0/CIN
5.209	0.035	tINS	FF	1	R47C60[0][A]	Mdu/u_mdu/adder_sum_cry_16_0/COUT
5.209	0.000	tNET	FF	2	R47C60[0][B]	Mdu/u_mdu/adder_sum_cry_17_0/CIN
5.244	0.035	tINS	FF	1	R47C60[0][B]	Mdu/u_mdu/adder_sum_cry_17_0/COUT
5.244	0.000	tNET	FF	2	R47C60[1][A]	Mdu/u_mdu/adder_sum_cry_18_0/CIN
5.279	0.035	tINS	FF	1	R47C60[1][A]	Mdu/u_mdu/adder_sum_cry_18_0/COUT
5.279	0.000	tNET	FF	2	R47C60[1][B]	Mdu/u_mdu/adder_sum_cry_19_0/CIN
5.315	0.035	tINS	FF	1	R47C60[1][B]	Mdu/u_mdu/adder_sum_cry_19_0/COUT
5.315	0.000	tNET	FF	2	R47C60[2][A]	Mdu/u_mdu/adder_sum_cry_20_0/CIN
5.350	0.035	tINS	FF	1	R47C60[2][A]	Mdu/u_mdu/adder_sum_cry_20_0/COUT
5.350	0.000	tNET	FF	2	R47C60[2][B]	Mdu/u_mdu/adder_sum_cry_21_0/CIN
5.385	0.035	tINS	FF	1	R47C60[2][B]	Mdu/u_mdu/adder_sum_cry_21_0/COUT
5.385	0.000	tNET	FF	2	R47C61[0][A]	Mdu/u_mdu/adder_sum_cry_22_0/CIN
5.420	0.035	tINS	FF	1	R47C61[0][A]	Mdu/u_mdu/adder_sum_cry_22_0/COUT
5.420	0.000	tNET	FF	2	R47C61[0][B]	Mdu/u_mdu/adder_sum_cry_23_0/CIN
5.455	0.035	tINS	FF	1	R47C61[0][B]	Mdu/u_mdu/adder_sum_cry_23_0/COUT
5.455	0.000	tNET	FF	2	R47C61[1][A]	Mdu/u_mdu/adder_sum_cry_24_0/CIN
5.491	0.035	tINS	FF	1	R47C61[1][A]	Mdu/u_mdu/adder_sum_cry_24_0/COUT
5.491	0.000	tNET	FF	2	R47C61[1][B]	Mdu/u_mdu/adder_sum_cry_25_0/CIN
5.526	0.035	tINS	FF	1	R47C61[1][B]	Mdu/u_mdu/adder_sum_cry_25_0/COUT
5.526	0.000	tNET	FF	2	R47C61[2][A]	Mdu/u_mdu/adder_sum_cry_26_0/CIN
5.561	0.035	tINS	FF	1	R47C61[2][A]	Mdu/u_mdu/adder_sum_cry_26_0/COUT
5.561	0.000	tNET	FF	2	R47C61[2][B]	Mdu/u_mdu/adder_sum_cry_27_0/CIN
5.596	0.035	tINS	FF	1	R47C61[2][B]	Mdu/u_mdu/adder_sum_cry_27_0/COUT
5.596	0.000	tNET	FF	2	R47C62[0][A]	Mdu/u_mdu/adder_sum_cry_28_0/CIN
5.631	0.035	tINS	FF	1	R47C62[0][A]	Mdu/u_mdu/adder_sum_cry_28_0/COUT
5.631	0.000	tNET	FF	2	R47C62[0][B]	Mdu/u_mdu/adder_sum_cry_29_0/CIN
5.667	0.035	tINS	FF	1	R47C62[0][B]	Mdu/u_mdu/adder_sum_cry_29_0/COUT
5.667	0.000	tNET	FF	2	R47C62[1][A]	Mdu/u_mdu/adder_sum_cry_30_0/CIN
5.702	0.035	tINS	FF	1	R47C62[1][A]	Mdu/u_mdu/adder_sum_cry_30_0/COUT
5.702	0.000	tNET	FF	2	R47C62[1][B]	Mdu/u_mdu/adder_sum_cry_31_0/CIN
5.737	0.035	tINS	FF	1	R47C62[1][B]	Mdu/u_mdu/adder_sum_cry_31_0/COUT
5.737	0.000	tNET	FF	2	R47C62[2][A]	Mdu/u_mdu/adder_sum_s_32_0/CIN
6.207	0.470	tINS	FF	6	R47C62[2][A]	Mdu/u_mdu/adder_sum_s_32_0/SUM
7.175	0.968	tNET	FF	1	R37C55[1][B]	Mdu/u_mdu/reg0_exe_nx_ss0_cZ/I0
7.692	0.517	tINS	FF	50	R37C55[1][B]	Mdu/u_mdu/reg0_exe_nx_ss0_cZ/F
8.669	0.977	tNET	FF	1	R47C58[3][A]	Mdu/u_mdu/reg0_exe_nx_m0_cZ[45]/I2
9.186	0.517	tINS	FF	1	R47C58[3][A]	Mdu/u_mdu/reg0_exe_nx_m0_cZ[45]/F
9.186	0.000	tNET	FF	1	R47C58[3][A]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[45]/I0
9.289	0.103	tINS	FF	1	R47C58[3][A]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[45]/O
10.416	1.127	tNET	FF	1	R52C63[0][A]	Mdu/u_mdu/reg0_nx_cZ[45]/I0
10.787	0.371	tINS	FF	1	R52C63[0][A]	Mdu/u_mdu/reg0_nx_cZ[45]/F
10.787	0.000	tNET	FF	1	R52C63[0][A]	Mdu/u_mdu/reg0_Z[45]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	578	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R52C63[0][A]	Mdu/u_mdu/reg0_Z[45]/CLK
11.683	-0.200	tUnc				Mdu/u_mdu/reg0_Z[45]
11.648	-0.035	tSu		1	R52C63[0][A]	Mdu/u_mdu/reg0_Z[45]

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 4.018, 45.130%; route: 4.653, 52.264%; tC2Q: 0.232, 2.606%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path20

Path Summary:

Slack	0.863
Data Arrival Time	10.785
Data Required Time	11.648
From	Mdu/u_mdu/reg0_fast_Z[13]
To	Mdu/u_mdu/reg0_fast_Z[19]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.683	0.683	tINS	RR	578	IOT48[A]	clk_ibuf/O
1.883	1.201	tNET	RR	1	R38C59[1][A]	Mdu/u_mdu/reg0_fast_Z[13]/CLK
2.115	0.232	tC2Q	RF	8	R38C59[1][A]	Mdu/u_mdu/reg0_fast_Z[13]/Q
3.360	1.245	tNET	FF	1	R51C56[1][B]	Mdu/u_mdu/reg0_neg_axb_12_par_0_cp_cZ/I1
3.915	0.555	tINS	FF	1	R51C56[1][B]	Mdu/u_mdu/reg0_neg_axb_12_par_0_cp_cZ/F
4.814	0.899	tNET	FF	2	R52C56[2][B]	Mdu/u_mdu/reg0_neg_axb_12_par_cp_1/I0
5.384	0.570	tINS	FR	1	R52C56[2][B]	Mdu/u_mdu/reg0_neg_axb_12_par_cp_1/COUT
5.384	0.000	tNET	RR	2	R52C57[0][A]	Mdu/u_mdu/reg0_neg_axb_16_par_cp_1/CIN
5.419	0.035	tINS	RF	1	R52C57[0][A]	Mdu/u_mdu/reg0_neg_axb_16_par_cp_1/COUT
5.419	0.000	tNET	FF	2	R52C57[0][B]	Mdu/u_mdu/reg0_neg_axb_19_par_1/CIN
5.454	0.035	tINS	FF	1	R52C57[0][B]	Mdu/u_mdu/reg0_neg_axb_19_par_1/COUT
5.454	0.000	tNET	FF	2	R52C57[1][A]	Mdu/u_mdu/reg0_neg_axb_23_par_1/CIN
5.490	0.035	tINS	FF	1	R52C57[1][A]	Mdu/u_mdu/reg0_neg_axb_23_par_1/COUT
5.490	0.000	tNET	FF	2	R52C57[1][B]	Mdu/u_mdu/reg0_neg_axb_27_par_1/CIN
5.525	0.035	tINS	FF	1	R52C57[1][B]	Mdu/u_mdu/reg0_neg_axb_27_par_1/COUT
5.525	0.000	tNET	FF	2	R52C57[2][A]	Mdu/u_mdu/reg0_neg_axb_31_par_1/CIN
5.560	0.035	tINS	FF	1	R52C57[2][A]	Mdu/u_mdu/reg0_neg_axb_31_par_1/COUT
5.560	0.000	tNET	FF	2	R52C57[2][B]	Mdu/u_mdu/reg0_neg_cry_34_0/CIN
5.595	0.035	tINS	FF	1	R52C57[2][B]	Mdu/u_mdu/reg0_neg_cry_34_0/COUT
5.595	0.000	tNET	FF	2	R52C58[0][A]	Mdu/u_mdu/reg0_neg_cry_35_0/CIN
5.630	0.035	tINS	FF	1	R52C58[0][A]	Mdu/u_mdu/reg0_neg_cry_35_0/COUT
5.630	0.000	tNET	FF	2	R52C58[0][B]	Mdu/u_mdu/reg0_neg_cry_36_0/CIN
5.666	0.035	tINS	FF	1	R52C58[0][B]	Mdu/u_mdu/reg0_neg_cry_36_0/COUT
5.666	0.000	tNET	FF	2	R52C58[1][A]	Mdu/u_mdu/reg0_neg_cry_37_0/CIN
5.701	0.035	tINS	FF	1	R52C58[1][A]	Mdu/u_mdu/reg0_neg_cry_37_0/COUT
5.701	0.000	tNET	FF	2	R52C58[1][B]	Mdu/u_mdu/reg0_neg_cry_38_0/CIN
5.736	0.035	tINS	FF	1	R52C58[1][B]	Mdu/u_mdu/reg0_neg_cry_38_0/COUT
5.736	0.000	tNET	FF	2	R52C58[2][A]	Mdu/u_mdu/reg0_neg_cry_39_0/CIN
5.771	0.035	tINS	FF	1	R52C58[2][A]	Mdu/u_mdu/reg0_neg_cry_39_0/COUT
5.771	0.000	tNET	FF	2	R52C58[2][B]	Mdu/u_mdu/reg0_neg_cry_40_0/CIN
5.806	0.035	tINS	FF	1	R52C58[2][B]	Mdu/u_mdu/reg0_neg_cry_40_0/COUT
5.806	0.000	tNET	FF	2	R52C59[0][A]	Mdu/u_mdu/reg0_neg_cry_41_0/CIN
5.842	0.035	tINS	FF	1	R52C59[0][A]	Mdu/u_mdu/reg0_neg_cry_41_0/COUT
5.842	0.000	tNET	FF	2	R52C59[0][B]	Mdu/u_mdu/reg0_neg_cry_42_0/CIN
5.877	0.035	tINS	FF	1	R52C59[0][B]	Mdu/u_mdu/reg0_neg_cry_42_0/COUT
5.877	0.000	tNET	FF	2	R52C59[1][A]	Mdu/u_mdu/reg0_neg_cry_43_0/CIN
5.912	0.035	tINS	FF	1	R52C59[1][A]	Mdu/u_mdu/reg0_neg_cry_43_0/COUT
5.912	0.000	tNET	FF	2	R52C59[1][B]	Mdu/u_mdu/reg0_neg_cry_44_0/CIN
5.947	0.035	tINS	FF	1	R52C59[1][B]	Mdu/u_mdu/reg0_neg_cry_44_0/COUT
5.947	0.000	tNET	FF	2	R52C59[2][A]	Mdu/u_mdu/reg0_neg_cry_45_0/CIN
5.982	0.035	tINS	FF	1	R52C59[2][A]	Mdu/u_mdu/reg0_neg_cry_45_0/COUT
5.982	0.000	tNET	FF	2	R52C59[2][B]	Mdu/u_mdu/reg0_neg_cry_46_0/CIN
6.018	0.035	tINS	FF	1	R52C59[2][B]	Mdu/u_mdu/reg0_neg_cry_46_0/COUT
6.018	0.000	tNET	FF	2	R52C60[0][A]	Mdu/u_mdu/reg0_neg_cry_47_0/CIN
6.053	0.035	tINS	FF	1	R52C60[0][A]	Mdu/u_mdu/reg0_neg_cry_47_0/COUT
6.053	0.000	tNET	FF	2	R52C60[0][B]	Mdu/u_mdu/reg0_neg_cry_48_0/CIN
6.088	0.035	tINS	FF	1	R52C60[0][B]	Mdu/u_mdu/reg0_neg_cry_48_0/COUT
6.088	0.000	tNET	FF	2	R52C60[1][A]	Mdu/u_mdu/reg0_neg_cry_49_0/CIN
6.123	0.035	tINS	FF	1	R52C60[1][A]	Mdu/u_mdu/reg0_neg_cry_49_0/COUT
6.123	0.000	tNET	FF	2	R52C60[1][B]	Mdu/u_mdu/reg0_neg_cry_50_0/CIN
6.158	0.035	tINS	FF	1	R52C60[1][B]	Mdu/u_mdu/reg0_neg_cry_50_0/COUT
6.158	0.000	tNET	FF	2	R52C60[2][A]	Mdu/u_mdu/reg0_neg_cry_51_0/CIN
6.628	0.470	tINS	FF	1	R52C60[2][A]	Mdu/u_mdu/reg0_neg_cry_51_0/SUM
7.312	0.684	tNET	FF	1	R55C58[2][A]	Mdu/u_mdu/reg0_post_swap_2[19]/I2
7.829	0.517	tINS	FF	1	R55C58[2][A]	Mdu/u_mdu/reg0_post_swap_2[19]/F
7.829	0.000	tNET	FF	1	R55C58[2][A]	Mdu/u_mdu/reg0_post_swap_4[19]/I0
7.932	0.103	tINS	FF	2	R55C58[2][A]	Mdu/u_mdu/reg0_post_swap_4[19]/O
8.709	0.777	tNET	FF	1	R48C58[1][A]	Mdu/u_mdu/un11_reg0_nx_cZ[19]_cZ/I1
9.226	0.517	tINS	FF	3	R48C58[1][A]	Mdu/u_mdu/un11_reg0_nx_cZ[19]_cZ/F
10.323	1.097	tNET	FF	1	R37C57[0][B]	Mdu/u_mdu/reg0_nx_fast_cZ[19]/I3
10.785	0.462	tINS	FR	1	R37C57[0][B]	Mdu/u_mdu/reg0_nx_fast_cZ[19]/F
10.785	0.000	tNET	RR	1	R37C57[0][B]	Mdu/u_mdu/reg0_fast_Z[19]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	578	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R37C57[0][B]	Mdu/u_mdu/reg0_fast_Z[19]/CLK
11.683	-0.200	tUnc				Mdu/u_mdu/reg0_fast_Z[19]
11.648	-0.035	tSu		1	R37C57[0][B]	Mdu/u_mdu/reg0_fast_Z[19]

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 3.968, 44.578%; route: 4.702, 52.816%; tC2Q: 0.232, 2.606%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path21

Path Summary:

Slack	0.881
Data Arrival Time	10.767
Data Required Time	11.648
From	Mdu/u_mdu/reg0_fast_Z[9]
To	memq_memq_0_11
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.683	0.683	tINS	RR	578	IOT48[A]	clk_ibuf/O
1.883	1.201	tNET	RR	1	R51C57[2][A]	Mdu/u_mdu/reg0_fast_Z[9]/CLK
2.115	0.232	tC2Q	RF	7	R51C57[2][A]	Mdu/u_mdu/reg0_fast_Z[9]/Q
2.892	0.777	tNET	FF	1	R39C57[2][B]	Mdu/u_mdu/reg0_neg_axb_8_par_0_cZ/I2
3.447	0.555	tINS	FF	1	R39C57[2][B]	Mdu/u_mdu/reg0_neg_axb_8_par_0_cZ/F
4.103	0.656	tNET	FF	2	R39C62[2][A]	Mdu/u_mdu/reg0_neg_axb_8_par_1/I0
4.673	0.570	tINS	FR	1	R39C62[2][A]	Mdu/u_mdu/reg0_neg_axb_8_par_1/COUT
4.673	0.000	tNET	RR	2	R39C62[2][B]	Mdu/u_mdu/reg0_neg_axb_12_par_1/CIN
4.708	0.035	tINS	RF	1	R39C62[2][B]	Mdu/u_mdu/reg0_neg_axb_12_par_1/COUT
4.708	0.000	tNET	FF	2	R39C63[0][A]	Mdu/u_mdu/reg0_neg_axb_16_par_1/CIN
4.743	0.035	tINS	FF	1	R39C63[0][A]	Mdu/u_mdu/reg0_neg_axb_16_par_1/COUT
4.743	0.000	tNET	FF	2	R39C63[0][B]	Mdu/u_mdu/reg0_neg_cry_19_0/CIN
4.778	0.035	tINS	FF	1	R39C63[0][B]	Mdu/u_mdu/reg0_neg_cry_19_0/COUT
4.778	0.000	tNET	FF	2	R39C63[1][A]	Mdu/u_mdu/reg0_neg_cry_20_0/CIN
4.814	0.035	tINS	FF	1	R39C63[1][A]	Mdu/u_mdu/reg0_neg_cry_20_0/COUT
4.814	0.000	tNET	FF	2	R39C63[1][B]	Mdu/u_mdu/reg0_neg_cry_21_0/CIN
4.849	0.035	tINS	FF	1	R39C63[1][B]	Mdu/u_mdu/reg0_neg_cry_21_0/COUT
4.849	0.000	tNET	FF	2	R39C63[2][A]	Mdu/u_mdu/reg0_neg_cry_22_0/CIN
4.884	0.035	tINS	FF	1	R39C63[2][A]	Mdu/u_mdu/reg0_neg_cry_22_0/COUT
4.884	0.000	tNET	FF	2	R39C63[2][B]	Mdu/u_mdu/reg0_neg_cry_23_0/CIN
5.354	0.470	tINS	FF	3	R39C63[2][B]	Mdu/u_mdu/reg0_neg_cry_23_0/SUM
6.285	0.931	tNET	FF	1	R41C56[3][A]	Mdu/u_mdu/reg0_post_swap_1[23]/I2
6.738	0.453	tINS	FF	2	R41C56[3][A]	Mdu/u_mdu/reg0_post_swap_1[23]/F
7.699	0.961	tNET	FF	1	R53C53[3][A]	Mdu/u_mdu/reg0_post_swap_5[23]/I0
8.254	0.555	tINS	FF	1	R53C53[3][A]	Mdu/u_mdu/reg0_post_swap_5[23]/F
9.015	0.761	tNET	FF	1	R41C53[2][A]	Mdu/u_mdu/res0_cZ[23]/I1
9.570	0.555	tINS	FF	3	R41C53[2][A]	Mdu/u_mdu/res0_cZ[23]/F
10.767	1.198	tNET	FF	1	BSRAM_R36[19]	memq_memq_0_11/DI1

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	578	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	BSRAM_R36[19]	memq_memq_0_11/CLKA
11.683	-0.200	tUnc				memq_memq_0_11
11.648	-0.035	tSu		1	BSRAM_R36[19]	memq_memq_0_11

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	6
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 3.369, 37.924%; route: 5.283, 59.465%; tC2Q: 0.232, 2.611%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path22

Path Summary:

Slack	0.882
Data Arrival Time	10.766
Data Required Time	11.648
From	Mdu/u_mdu/reg0_fast_Z[13]
To	Mdu/u_mdu/reg0_fast_Z[26]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.683	0.683	tINS	RR	578	IOT48[A]	clk_ibuf/O
1.883	1.201	tNET	RR	1	R38C59[1][A]	Mdu/u_mdu/reg0_fast_Z[13]/CLK
2.115	0.232	tC2Q	RF	8	R38C59[1][A]	Mdu/u_mdu/reg0_fast_Z[13]/Q
3.516	1.401	tNET	FF	1	R51C54[3][B]	Mdu/u_mdu/reg0_neg_axb_12_par_0_cp_0_cZ/I1
4.033	0.517	tINS	FF	1	R51C54[3][B]	Mdu/u_mdu/reg0_neg_axb_12_par_0_cp_0_cZ/F
4.960	0.927	tNET	FF	2	R56C51[2][B]	Mdu/u_mdu/reg0_neg_axb_12_par_cp_0_0/I0
5.530	0.570	tINS	FR	1	R56C51[2][B]	Mdu/u_mdu/reg0_neg_axb_12_par_cp_0_0/COUT
5.530	0.000	tNET	RR	2	R56C52[0][A]	Mdu/u_mdu/reg0_neg_axb_16_par_cp_0_0/CIN
5.565	0.035	tINS	RF	1	R56C52[0][A]	Mdu/u_mdu/reg0_neg_axb_16_par_cp_0_0/COUT
5.565	0.000	tNET	FF	2	R56C52[0][B]	Mdu/u_mdu/reg0_neg_axb_19_par_cp_0/CIN
5.600	0.035	tINS	FF	1	R56C52[0][B]	Mdu/u_mdu/reg0_neg_axb_19_par_cp_0/COUT
5.600	0.000	tNET	FF	2	R56C52[1][A]	Mdu/u_mdu/reg0_neg_axb_23_par_cp_0/CIN
5.635	0.035	tINS	FF	1	R56C52[1][A]	Mdu/u_mdu/reg0_neg_axb_23_par_cp_0/COUT
5.635	0.000	tNET	FF	2	R56C52[1][B]	Mdu/u_mdu/reg0_neg_axb_27_par_cp_0/CIN
5.671	0.035	tINS	FF	1	R56C52[1][B]	Mdu/u_mdu/reg0_neg_axb_27_par_cp_0/COUT
5.671	0.000	tNET	FF	2	R56C52[2][A]	Mdu/u_mdu/reg0_neg_axb_31_par_cp_0/CIN
5.706	0.035	tINS	FF	1	R56C52[2][A]	Mdu/u_mdu/reg0_neg_axb_31_par_cp_0/COUT
5.706	0.000	tNET	FF	2	R56C52[2][B]	Mdu/u_mdu/reg0_neg_axb_34_par_1/CIN
5.741	0.035	tINS	FF	1	R56C52[2][B]	Mdu/u_mdu/reg0_neg_axb_34_par_1/COUT
5.741	0.000	tNET	FF	2	R56C53[0][A]	Mdu/u_mdu/reg0_neg_axb_38_par_1/CIN
5.776	0.035	tINS	FF	1	R56C53[0][A]	Mdu/u_mdu/reg0_neg_axb_38_par_1/COUT
5.776	0.000	tNET	FF	2	R56C53[0][B]	Mdu/u_mdu/reg0_neg_axb_42_par_1/CIN
5.811	0.035	tINS	FF	1	R56C53[0][B]	Mdu/u_mdu/reg0_neg_axb_42_par_1/COUT
5.811	0.000	tNET	FF	2	R56C53[1][A]	Mdu/u_mdu/reg0_neg_axb_46_par_1/CIN
5.847	0.035	tINS	FF	1	R56C53[1][A]	Mdu/u_mdu/reg0_neg_axb_46_par_1/COUT
5.847	0.000	tNET	FF	2	R56C53[1][B]	Mdu/u_mdu/reg0_neg_axb_50_par_1/CIN
5.882	0.035	tINS	FF	1	R56C53[1][B]	Mdu/u_mdu/reg0_neg_axb_50_par_1/COUT
5.882	0.000	tNET	FF	2	R56C53[2][A]	Mdu/u_mdu/reg0_neg_cry_54_0/CIN
5.917	0.035	tINS	FF	1	R56C53[2][A]	Mdu/u_mdu/reg0_neg_cry_54_0/COUT
5.917	0.000	tNET	FF	2	R56C53[2][B]	Mdu/u_mdu/reg0_neg_cry_55_0/CIN
5.952	0.035	tINS	FF	1	R56C53[2][B]	Mdu/u_mdu/reg0_neg_cry_55_0/COUT
5.952	0.000	tNET	FF	2	R56C54[0][A]	Mdu/u_mdu/reg0_neg_cry_56_0/CIN
5.987	0.035	tINS	FF	1	R56C54[0][A]	Mdu/u_mdu/reg0_neg_cry_56_0/COUT
5.987	0.000	tNET	FF	2	R56C54[0][B]	Mdu/u_mdu/reg0_neg_cry_57_0/CIN
6.023	0.035	tINS	FF	1	R56C54[0][B]	Mdu/u_mdu/reg0_neg_cry_57_0/COUT
6.023	0.000	tNET	FF	2	R56C54[1][A]	Mdu/u_mdu/reg0_neg_cry_58_0/CIN
6.493	0.470	tINS	FF	1	R56C54[1][A]	Mdu/u_mdu/reg0_neg_cry_58_0/SUM
7.298	0.806	tNET	FF	1	R53C54[2][A]	Mdu/u_mdu/reg0_post_swap_2_i_m2[26]/I2
7.815	0.517	tINS	FF	1	R53C54[2][A]	Mdu/u_mdu/reg0_post_swap_2_i_m2[26]/F
7.815	0.000	tNET	FF	1	R53C54[2][A]	Mdu/u_mdu/reg0_post_swap_5_i_m4[26]/I0
7.918	0.103	tINS	FF	2	R53C54[2][A]	Mdu/u_mdu/reg0_post_swap_5_i_m4[26]/O
8.889	0.971	tNET	FF	1	R38C55[1][A]	Mdu/u_mdu/un11_reg0_nx_cZ[26]_cZ/I1
9.260	0.371	tINS	FF	3	R38C55[1][A]	Mdu/u_mdu/un11_reg0_nx_cZ[26]_cZ/F
10.196	0.936	tNET	FF	1	R39C60[1][A]	Mdu/u_mdu/reg0_nx_fast_cZ[26]/I3
10.766	0.570	tINS	FR	1	R39C60[1][A]	Mdu/u_mdu/reg0_nx_fast_cZ[26]/F
10.766	0.000	tNET	RR	1	R39C60[1][A]	Mdu/u_mdu/reg0_fast_Z[26]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	578	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R39C60[1][A]	Mdu/u_mdu/reg0_fast_Z[26]/CLK
11.683	-0.200	tUnc				Mdu/u_mdu/reg0_fast_Z[26]
11.648	-0.035	tSu		1	R39C60[1][A]	Mdu/u_mdu/reg0_fast_Z[26]

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 3.611, 40.648%; route: 5.040, 56.740%; tC2Q: 0.232, 2.612%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path23

Path Summary:

Slack	0.887
Data Arrival Time	10.762
Data Required Time	11.648
From	Mdu/u_mdu/rs1_mul_Z[5]
To	Mdu/u_mdu/reg0_Z[38]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.683	0.683	tINS	RR	578	IOT48[A]	clk_ibuf/O
1.883	1.201	tNET	RR	1	R46C62[1][A]	Mdu/u_mdu/rs1_mul_Z[5]/CLK
2.115	0.232	tC2Q	RF	1	R46C62[1][A]	Mdu/u_mdu/rs1_mul_Z[5]/Q
3.013	0.898	tNET	FF	1	R46C62[3][B]	Mdu/u_mdu/adder_sum_s_5_sf_lofx_cZ/I2
3.568	0.555	tINS	FF	1	R46C62[3][B]	Mdu/u_mdu/adder_sum_s_5_sf_lofx_cZ/F
4.252	0.684	tNET	FF	2	R47C58[0][B]	Mdu/u_mdu/adder_sum_cry_5_0/I0
4.822	0.570	tINS	FR	1	R47C58[0][B]	Mdu/u_mdu/adder_sum_cry_5_0/COUT
4.822	0.000	tNET	RR	2	R47C58[1][A]	Mdu/u_mdu/adder_sum_cry_6_0/CIN
4.857	0.035	tINS	RF	1	R47C58[1][A]	Mdu/u_mdu/adder_sum_cry_6_0/COUT
4.857	0.000	tNET	FF	2	R47C58[1][B]	Mdu/u_mdu/adder_sum_cry_7_0/CIN
4.892	0.035	tINS	FF	1	R47C58[1][B]	Mdu/u_mdu/adder_sum_cry_7_0/COUT
4.892	0.000	tNET	FF	2	R47C58[2][A]	Mdu/u_mdu/adder_sum_cry_8_0/CIN
4.927	0.035	tINS	FF	1	R47C58[2][A]	Mdu/u_mdu/adder_sum_cry_8_0/COUT
4.927	0.000	tNET	FF	2	R47C58[2][B]	Mdu/u_mdu/adder_sum_cry_9_0/CIN
4.963	0.035	tINS	FF	1	R47C58[2][B]	Mdu/u_mdu/adder_sum_cry_9_0/COUT
4.963	0.000	tNET	FF	2	R47C59[0][A]	Mdu/u_mdu/adder_sum_cry_10_0/CIN
4.998	0.035	tINS	FF	1	R47C59[0][A]	Mdu/u_mdu/adder_sum_cry_10_0/COUT
4.998	0.000	tNET	FF	2	R47C59[0][B]	Mdu/u_mdu/adder_sum_cry_11_0/CIN
5.033	0.035	tINS	FF	1	R47C59[0][B]	Mdu/u_mdu/adder_sum_cry_11_0/COUT
5.033	0.000	tNET	FF	2	R47C59[1][A]	Mdu/u_mdu/adder_sum_cry_12_0/CIN
5.068	0.035	tINS	FF	1	R47C59[1][A]	Mdu/u_mdu/adder_sum_cry_12_0/COUT
5.068	0.000	tNET	FF	2	R47C59[1][B]	Mdu/u_mdu/adder_sum_cry_13_0/CIN
5.103	0.035	tINS	FF	1	R47C59[1][B]	Mdu/u_mdu/adder_sum_cry_13_0/COUT
5.103	0.000	tNET	FF	2	R47C59[2][A]	Mdu/u_mdu/adder_sum_cry_14_0/CIN
5.139	0.035	tINS	FF	1	R47C59[2][A]	Mdu/u_mdu/adder_sum_cry_14_0/COUT
5.139	0.000	tNET	FF	2	R47C59[2][B]	Mdu/u_mdu/adder_sum_cry_15_0/CIN
5.174	0.035	tINS	FF	1	R47C59[2][B]	Mdu/u_mdu/adder_sum_cry_15_0/COUT
5.174	0.000	tNET	FF	2	R47C60[0][A]	Mdu/u_mdu/adder_sum_cry_16_0/CIN
5.209	0.035	tINS	FF	1	R47C60[0][A]	Mdu/u_mdu/adder_sum_cry_16_0/COUT
5.209	0.000	tNET	FF	2	R47C60[0][B]	Mdu/u_mdu/adder_sum_cry_17_0/CIN
5.244	0.035	tINS	FF	1	R47C60[0][B]	Mdu/u_mdu/adder_sum_cry_17_0/COUT
5.244	0.000	tNET	FF	2	R47C60[1][A]	Mdu/u_mdu/adder_sum_cry_18_0/CIN
5.279	0.035	tINS	FF	1	R47C60[1][A]	Mdu/u_mdu/adder_sum_cry_18_0/COUT
5.279	0.000	tNET	FF	2	R47C60[1][B]	Mdu/u_mdu/adder_sum_cry_19_0/CIN
5.315	0.035	tINS	FF	1	R47C60[1][B]	Mdu/u_mdu/adder_sum_cry_19_0/COUT
5.315	0.000	tNET	FF	2	R47C60[2][A]	Mdu/u_mdu/adder_sum_cry_20_0/CIN
5.350	0.035	tINS	FF	1	R47C60[2][A]	Mdu/u_mdu/adder_sum_cry_20_0/COUT
5.350	0.000	tNET	FF	2	R47C60[2][B]	Mdu/u_mdu/adder_sum_cry_21_0/CIN
5.385	0.035	tINS	FF	1	R47C60[2][B]	Mdu/u_mdu/adder_sum_cry_21_0/COUT
5.385	0.000	tNET	FF	2	R47C61[0][A]	Mdu/u_mdu/adder_sum_cry_22_0/CIN
5.420	0.035	tINS	FF	1	R47C61[0][A]	Mdu/u_mdu/adder_sum_cry_22_0/COUT
5.420	0.000	tNET	FF	2	R47C61[0][B]	Mdu/u_mdu/adder_sum_cry_23_0/CIN
5.455	0.035	tINS	FF	1	R47C61[0][B]	Mdu/u_mdu/adder_sum_cry_23_0/COUT
5.455	0.000	tNET	FF	2	R47C61[1][A]	Mdu/u_mdu/adder_sum_cry_24_0/CIN
5.491	0.035	tINS	FF	1	R47C61[1][A]	Mdu/u_mdu/adder_sum_cry_24_0/COUT
5.491	0.000	tNET	FF	2	R47C61[1][B]	Mdu/u_mdu/adder_sum_cry_25_0/CIN
5.526	0.035	tINS	FF	1	R47C61[1][B]	Mdu/u_mdu/adder_sum_cry_25_0/COUT
5.526	0.000	tNET	FF	2	R47C61[2][A]	Mdu/u_mdu/adder_sum_cry_26_0/CIN
5.561	0.035	tINS	FF	1	R47C61[2][A]	Mdu/u_mdu/adder_sum_cry_26_0/COUT
5.561	0.000	tNET	FF	2	R47C61[2][B]	Mdu/u_mdu/adder_sum_cry_27_0/CIN
5.596	0.035	tINS	FF	1	R47C61[2][B]	Mdu/u_mdu/adder_sum_cry_27_0/COUT
5.596	0.000	tNET	FF	2	R47C62[0][A]	Mdu/u_mdu/adder_sum_cry_28_0/CIN
5.631	0.035	tINS	FF	1	R47C62[0][A]	Mdu/u_mdu/adder_sum_cry_28_0/COUT
5.631	0.000	tNET	FF	2	R47C62[0][B]	Mdu/u_mdu/adder_sum_cry_29_0/CIN
5.667	0.035	tINS	FF	1	R47C62[0][B]	Mdu/u_mdu/adder_sum_cry_29_0/COUT
5.667	0.000	tNET	FF	2	R47C62[1][A]	Mdu/u_mdu/adder_sum_cry_30_0/CIN
5.702	0.035	tINS	FF	1	R47C62[1][A]	Mdu/u_mdu/adder_sum_cry_30_0/COUT
5.702	0.000	tNET	FF	2	R47C62[1][B]	Mdu/u_mdu/adder_sum_cry_31_0/CIN
5.737	0.035	tINS	FF	1	R47C62[1][B]	Mdu/u_mdu/adder_sum_cry_31_0/COUT
5.737	0.000	tNET	FF	2	R47C62[2][A]	Mdu/u_mdu/adder_sum_s_32_0/CIN
6.207	0.470	tINS	FF	6	R47C62[2][A]	Mdu/u_mdu/adder_sum_s_32_0/SUM
7.175	0.968	tNET	FF	1	R37C55[1][B]	Mdu/u_mdu/reg0_exe_nx_ss0_cZ/I0
7.692	0.517	tINS	FF	50	R37C55[1][B]	Mdu/u_mdu/reg0_exe_nx_ss0_cZ/F
8.481	0.789	tNET	FF	1	R30C59[3][A]	Mdu/u_mdu/reg0_exe_nx_m0_cZ[38]/I2
8.934	0.453	tINS	FF	1	R30C59[3][A]	Mdu/u_mdu/reg0_exe_nx_m0_cZ[38]/F
8.934	0.000	tNET	FF	1	R30C59[3][A]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[38]/I0
9.037	0.103	tINS	FF	1	R30C59[3][A]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[38]/O
10.192	1.155	tNET	FF	1	R53C60[2][B]	Mdu/u_mdu/reg0_nx_0[38]/I2
10.762	0.570	tINS	FR	1	R53C60[2][B]	Mdu/u_mdu/reg0_nx_0[38]/F
10.762	0.000	tNET	RR	1	R53C60[2][B]	Mdu/u_mdu/reg0_Z[38]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	578	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R53C60[2][B]	Mdu/u_mdu/reg0_Z[38]/CLK
11.683	-0.200	tUnc				Mdu/u_mdu/reg0_Z[38]
11.648	-0.035	tSu		1	R53C60[2][B]	Mdu/u_mdu/reg0_Z[38]

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 4.153, 46.778%; route: 4.493, 50.608%; tC2Q: 0.232, 2.613%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path24

Path Summary:

Slack	0.887
Data Arrival Time	10.761
Data Required Time	11.648
From	Mdu/u_mdu/reg0_fast_Z[13]
To	memq_memq_0_5
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.683	0.683	tINS	RR	578	IOT48[A]	clk_ibuf/O
1.883	1.201	tNET	RR	1	R38C59[1][A]	Mdu/u_mdu/reg0_fast_Z[13]/CLK
2.115	0.232	tC2Q	RF	8	R38C59[1][A]	Mdu/u_mdu/reg0_fast_Z[13]/Q
3.360	1.245	tNET	FF	1	R51C56[1][B]	Mdu/u_mdu/reg0_neg_axb_12_par_0_cp_cZ/I1
3.915	0.555	tINS	FF	1	R51C56[1][B]	Mdu/u_mdu/reg0_neg_axb_12_par_0_cp_cZ/F
4.814	0.899	tNET	FF	2	R52C56[2][B]	Mdu/u_mdu/reg0_neg_axb_12_par_cp_1/I0
5.384	0.570	tINS	FR	1	R52C56[2][B]	Mdu/u_mdu/reg0_neg_axb_12_par_cp_1/COUT
5.384	0.000	tNET	RR	2	R52C57[0][A]	Mdu/u_mdu/reg0_neg_axb_16_par_cp_1/CIN
5.419	0.035	tINS	RF	1	R52C57[0][A]	Mdu/u_mdu/reg0_neg_axb_16_par_cp_1/COUT
5.419	0.000	tNET	FF	2	R52C57[0][B]	Mdu/u_mdu/reg0_neg_axb_19_par_1/CIN
5.454	0.035	tINS	FF	1	R52C57[0][B]	Mdu/u_mdu/reg0_neg_axb_19_par_1/COUT
5.454	0.000	tNET	FF	2	R52C57[1][A]	Mdu/u_mdu/reg0_neg_axb_23_par_1/CIN
5.490	0.035	tINS	FF	1	R52C57[1][A]	Mdu/u_mdu/reg0_neg_axb_23_par_1/COUT
5.490	0.000	tNET	FF	2	R52C57[1][B]	Mdu/u_mdu/reg0_neg_axb_27_par_1/CIN
5.525	0.035	tINS	FF	1	R52C57[1][B]	Mdu/u_mdu/reg0_neg_axb_27_par_1/COUT
5.525	0.000	tNET	FF	2	R52C57[2][A]	Mdu/u_mdu/reg0_neg_axb_31_par_1/CIN
5.560	0.035	tINS	FF	1	R52C57[2][A]	Mdu/u_mdu/reg0_neg_axb_31_par_1/COUT
5.560	0.000	tNET	FF	2	R52C57[2][B]	Mdu/u_mdu/reg0_neg_cry_34_0/CIN
5.595	0.035	tINS	FF	1	R52C57[2][B]	Mdu/u_mdu/reg0_neg_cry_34_0/COUT
5.595	0.000	tNET	FF	2	R52C58[0][A]	Mdu/u_mdu/reg0_neg_cry_35_0/CIN
5.630	0.035	tINS	FF	1	R52C58[0][A]	Mdu/u_mdu/reg0_neg_cry_35_0/COUT
5.630	0.000	tNET	FF	2	R52C58[0][B]	Mdu/u_mdu/reg0_neg_cry_36_0/CIN
5.666	0.035	tINS	FF	1	R52C58[0][B]	Mdu/u_mdu/reg0_neg_cry_36_0/COUT
5.666	0.000	tNET	FF	2	R52C58[1][A]	Mdu/u_mdu/reg0_neg_cry_37_0/CIN
5.701	0.035	tINS	FF	1	R52C58[1][A]	Mdu/u_mdu/reg0_neg_cry_37_0/COUT
5.701	0.000	tNET	FF	2	R52C58[1][B]	Mdu/u_mdu/reg0_neg_cry_38_0/CIN
5.736	0.035	tINS	FF	1	R52C58[1][B]	Mdu/u_mdu/reg0_neg_cry_38_0/COUT
5.736	0.000	tNET	FF	2	R52C58[2][A]	Mdu/u_mdu/reg0_neg_cry_39_0/CIN
5.771	0.035	tINS	FF	1	R52C58[2][A]	Mdu/u_mdu/reg0_neg_cry_39_0/COUT
5.771	0.000	tNET	FF	2	R52C58[2][B]	Mdu/u_mdu/reg0_neg_cry_40_0/CIN
5.806	0.035	tINS	FF	1	R52C58[2][B]	Mdu/u_mdu/reg0_neg_cry_40_0/COUT
5.806	0.000	tNET	FF	2	R52C59[0][A]	Mdu/u_mdu/reg0_neg_cry_41_0/CIN
5.842	0.035	tINS	FF	1	R52C59[0][A]	Mdu/u_mdu/reg0_neg_cry_41_0/COUT
5.842	0.000	tNET	FF	2	R52C59[0][B]	Mdu/u_mdu/reg0_neg_cry_42_0/CIN
5.877	0.035	tINS	FF	1	R52C59[0][B]	Mdu/u_mdu/reg0_neg_cry_42_0/COUT
5.877	0.000	tNET	FF	2	R52C59[1][A]	Mdu/u_mdu/reg0_neg_cry_43_0/CIN
6.347	0.470	tINS	FF	1	R52C59[1][A]	Mdu/u_mdu/reg0_neg_cry_43_0/SUM
6.517	0.170	tNET	FF	1	R51C59[1][A]	Mdu/u_mdu/reg0_post_swap_2[11]/I2
6.888	0.371	tINS	FF	1	R51C59[1][A]	Mdu/u_mdu/reg0_post_swap_2[11]/F
6.888	0.000	tNET	FF	1	R51C59[1][A]	Mdu/u_mdu/reg0_post_swap_4[11]/I0
6.991	0.103	tINS	FF	1	R51C59[1][A]	Mdu/u_mdu/reg0_post_swap_4[11]/O
7.831	0.840	tNET	FF	1	R42C59[1][B]	Mdu/u_mdu/reg0_post_swap_5[11]/I1
8.386	0.555	tINS	FF	4	R42C59[1][B]	Mdu/u_mdu/reg0_post_swap_5[11]/F
9.475	1.089	tNET	FF	1	R39C51[0][B]	Mdu/u_mdu/res0_cZ[11]/I1
9.992	0.517	tINS	FF	3	R39C51[0][B]	Mdu/u_mdu/res0_cZ[11]/F
10.761	0.770	tNET	FF	1	BSRAM_R45[15]	memq_memq_0_5/DI1

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	578	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	BSRAM_R45[15]	memq_memq_0_5/CLKA
11.683	-0.200	tUnc				memq_memq_0_5
11.648	-0.035	tSu		1	BSRAM_R45[15]	memq_memq_0_5

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 3.634, 40.930%; route: 5.012, 56.457%; tC2Q: 0.232, 2.613%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path25

Path Summary:

Slack	1.003
Data Arrival Time	10.645
Data Required Time	11.648
From	Mdu/u_mdu/rs1_mul_Z[5]
To	Mdu/u_mdu/reg0_Z[40]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.683	0.683	tINS	RR	578	IOT48[A]	clk_ibuf/O
1.883	1.201	tNET	RR	1	R46C62[1][A]	Mdu/u_mdu/rs1_mul_Z[5]/CLK
2.115	0.232	tC2Q	RF	1	R46C62[1][A]	Mdu/u_mdu/rs1_mul_Z[5]/Q
3.013	0.898	tNET	FF	1	R46C62[3][B]	Mdu/u_mdu/adder_sum_s_5_sf_lofx_cZ/I2
3.568	0.555	tINS	FF	1	R46C62[3][B]	Mdu/u_mdu/adder_sum_s_5_sf_lofx_cZ/F
4.252	0.684	tNET	FF	2	R47C58[0][B]	Mdu/u_mdu/adder_sum_cry_5_0/I0
4.822	0.570	tINS	FR	1	R47C58[0][B]	Mdu/u_mdu/adder_sum_cry_5_0/COUT
4.822	0.000	tNET	RR	2	R47C58[1][A]	Mdu/u_mdu/adder_sum_cry_6_0/CIN
4.857	0.035	tINS	RF	1	R47C58[1][A]	Mdu/u_mdu/adder_sum_cry_6_0/COUT
4.857	0.000	tNET	FF	2	R47C58[1][B]	Mdu/u_mdu/adder_sum_cry_7_0/CIN
4.892	0.035	tINS	FF	1	R47C58[1][B]	Mdu/u_mdu/adder_sum_cry_7_0/COUT
4.892	0.000	tNET	FF	2	R47C58[2][A]	Mdu/u_mdu/adder_sum_cry_8_0/CIN
4.927	0.035	tINS	FF	1	R47C58[2][A]	Mdu/u_mdu/adder_sum_cry_8_0/COUT
4.927	0.000	tNET	FF	2	R47C58[2][B]	Mdu/u_mdu/adder_sum_cry_9_0/CIN
4.963	0.035	tINS	FF	1	R47C58[2][B]	Mdu/u_mdu/adder_sum_cry_9_0/COUT
4.963	0.000	tNET	FF	2	R47C59[0][A]	Mdu/u_mdu/adder_sum_cry_10_0/CIN
4.998	0.035	tINS	FF	1	R47C59[0][A]	Mdu/u_mdu/adder_sum_cry_10_0/COUT
4.998	0.000	tNET	FF	2	R47C59[0][B]	Mdu/u_mdu/adder_sum_cry_11_0/CIN
5.033	0.035	tINS	FF	1	R47C59[0][B]	Mdu/u_mdu/adder_sum_cry_11_0/COUT
5.033	0.000	tNET	FF	2	R47C59[1][A]	Mdu/u_mdu/adder_sum_cry_12_0/CIN
5.068	0.035	tINS	FF	1	R47C59[1][A]	Mdu/u_mdu/adder_sum_cry_12_0/COUT
5.068	0.000	tNET	FF	2	R47C59[1][B]	Mdu/u_mdu/adder_sum_cry_13_0/CIN
5.103	0.035	tINS	FF	1	R47C59[1][B]	Mdu/u_mdu/adder_sum_cry_13_0/COUT
5.103	0.000	tNET	FF	2	R47C59[2][A]	Mdu/u_mdu/adder_sum_cry_14_0/CIN
5.139	0.035	tINS	FF	1	R47C59[2][A]	Mdu/u_mdu/adder_sum_cry_14_0/COUT
5.139	0.000	tNET	FF	2	R47C59[2][B]	Mdu/u_mdu/adder_sum_cry_15_0/CIN
5.174	0.035	tINS	FF	1	R47C59[2][B]	Mdu/u_mdu/adder_sum_cry_15_0/COUT
5.174	0.000	tNET	FF	2	R47C60[0][A]	Mdu/u_mdu/adder_sum_cry_16_0/CIN
5.209	0.035	tINS	FF	1	R47C60[0][A]	Mdu/u_mdu/adder_sum_cry_16_0/COUT
5.209	0.000	tNET	FF	2	R47C60[0][B]	Mdu/u_mdu/adder_sum_cry_17_0/CIN
5.244	0.035	tINS	FF	1	R47C60[0][B]	Mdu/u_mdu/adder_sum_cry_17_0/COUT
5.244	0.000	tNET	FF	2	R47C60[1][A]	Mdu/u_mdu/adder_sum_cry_18_0/CIN
5.279	0.035	tINS	FF	1	R47C60[1][A]	Mdu/u_mdu/adder_sum_cry_18_0/COUT
5.279	0.000	tNET	FF	2	R47C60[1][B]	Mdu/u_mdu/adder_sum_cry_19_0/CIN
5.315	0.035	tINS	FF	1	R47C60[1][B]	Mdu/u_mdu/adder_sum_cry_19_0/COUT
5.315	0.000	tNET	FF	2	R47C60[2][A]	Mdu/u_mdu/adder_sum_cry_20_0/CIN
5.350	0.035	tINS	FF	1	R47C60[2][A]	Mdu/u_mdu/adder_sum_cry_20_0/COUT
5.350	0.000	tNET	FF	2	R47C60[2][B]	Mdu/u_mdu/adder_sum_cry_21_0/CIN
5.385	0.035	tINS	FF	1	R47C60[2][B]	Mdu/u_mdu/adder_sum_cry_21_0/COUT
5.385	0.000	tNET	FF	2	R47C61[0][A]	Mdu/u_mdu/adder_sum_cry_22_0/CIN
5.420	0.035	tINS	FF	1	R47C61[0][A]	Mdu/u_mdu/adder_sum_cry_22_0/COUT
5.420	0.000	tNET	FF	2	R47C61[0][B]	Mdu/u_mdu/adder_sum_cry_23_0/CIN
5.455	0.035	tINS	FF	1	R47C61[0][B]	Mdu/u_mdu/adder_sum_cry_23_0/COUT
5.455	0.000	tNET	FF	2	R47C61[1][A]	Mdu/u_mdu/adder_sum_cry_24_0/CIN
5.491	0.035	tINS	FF	1	R47C61[1][A]	Mdu/u_mdu/adder_sum_cry_24_0/COUT
5.491	0.000	tNET	FF	2	R47C61[1][B]	Mdu/u_mdu/adder_sum_cry_25_0/CIN
5.526	0.035	tINS	FF	1	R47C61[1][B]	Mdu/u_mdu/adder_sum_cry_25_0/COUT
5.526	0.000	tNET	FF	2	R47C61[2][A]	Mdu/u_mdu/adder_sum_cry_26_0/CIN
5.561	0.035	tINS	FF	1	R47C61[2][A]	Mdu/u_mdu/adder_sum_cry_26_0/COUT
5.561	0.000	tNET	FF	2	R47C61[2][B]	Mdu/u_mdu/adder_sum_cry_27_0/CIN
5.596	0.035	tINS	FF	1	R47C61[2][B]	Mdu/u_mdu/adder_sum_cry_27_0/COUT
5.596	0.000	tNET	FF	2	R47C62[0][A]	Mdu/u_mdu/adder_sum_cry_28_0/CIN
5.631	0.035	tINS	FF	1	R47C62[0][A]	Mdu/u_mdu/adder_sum_cry_28_0/COUT
5.631	0.000	tNET	FF	2	R47C62[0][B]	Mdu/u_mdu/adder_sum_cry_29_0/CIN
5.667	0.035	tINS	FF	1	R47C62[0][B]	Mdu/u_mdu/adder_sum_cry_29_0/COUT
5.667	0.000	tNET	FF	2	R47C62[1][A]	Mdu/u_mdu/adder_sum_cry_30_0/CIN
5.702	0.035	tINS	FF	1	R47C62[1][A]	Mdu/u_mdu/adder_sum_cry_30_0/COUT
5.702	0.000	tNET	FF	2	R47C62[1][B]	Mdu/u_mdu/adder_sum_cry_31_0/CIN
5.737	0.035	tINS	FF	1	R47C62[1][B]	Mdu/u_mdu/adder_sum_cry_31_0/COUT
5.737	0.000	tNET	FF	2	R47C62[2][A]	Mdu/u_mdu/adder_sum_s_32_0/CIN
6.207	0.470	tINS	FF	6	R47C62[2][A]	Mdu/u_mdu/adder_sum_s_32_0/SUM
7.175	0.968	tNET	FF	1	R37C55[1][B]	Mdu/u_mdu/reg0_exe_nx_ss0_cZ/I0
7.692	0.517	tINS	FF	50	R37C55[1][B]	Mdu/u_mdu/reg0_exe_nx_ss0_cZ/F
8.477	0.785	tNET	FF	1	R44C59[2][A]	Mdu/u_mdu/reg0_exe_nx_m0_cZ[40]/I2
9.032	0.555	tINS	FF	1	R44C59[2][A]	Mdu/u_mdu/reg0_exe_nx_m0_cZ[40]/F
9.032	0.000	tNET	FF	1	R44C59[2][A]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[40]/I0
9.135	0.103	tINS	FF	1	R44C59[2][A]	Mdu/u_mdu/reg0_exe_nx_m2_cZ[40]/O
10.096	0.961	tNET	FF	1	R52C62[1][A]	Mdu/u_mdu/reg0_nx_cZ[40]/I0
10.645	0.549	tINS	FR	1	R52C62[1][A]	Mdu/u_mdu/reg0_nx_cZ[40]/F
10.645	0.000	tNET	RR	1	R52C62[1][A]	Mdu/u_mdu/reg0_Z[40]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	578	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R52C62[1][A]	Mdu/u_mdu/reg0_Z[40]/CLK
11.683	-0.200	tUnc				Mdu/u_mdu/reg0_Z[40]
11.648	-0.035	tSu		1	R52C62[1][A]	Mdu/u_mdu/reg0_Z[40]

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 4.234, 48.326%; route: 4.296, 49.026%; tC2Q: 0.232, 2.648%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Hold Analysis Report

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	0.213
Data Arrival Time	2.040
Data Required Time	1.826
From	u_la0_top/u_ao_mem_ctrl/data_reg_Z[85]
To	u_la0_top/u_ao_mem_ctrl/mem_mem_0_42
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	578	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R11C12[2][B]	u_la0_top/u_ao_mem_ctrl/data_reg_Z[85]/CLK
1.779	0.202	tC2Q	RR	1	R11C12[2][B]	u_la0_top/u_ao_mem_ctrl/data_reg_Z[85]/Q
2.040	0.260	tNET	RR	1	BSRAM_R10[2]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_42/DI1

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	578	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	BSRAM_R10[2]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_42/CLKA
1.577	0.000	tUnc				u_la0_top/u_ao_mem_ctrl/mem_mem_0_42
1.826	0.249	tHld		1	BSRAM_R10[2]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_42

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.260, 56.314%; tC2Q: 0.202, 43.686%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path2

Path Summary:

Slack	0.213
Data Arrival Time	2.040
Data Required Time	1.826
From	u_la0_top/u_ao_mem_ctrl/data_reg_Z[84]
To	u_la0_top/u_ao_mem_ctrl/mem_mem_0_42
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	578	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R11C12[2][A]	u_la0_top/u_ao_mem_ctrl/data_reg_Z[84]/CLK
1.779	0.202	tC2Q	RR	1	R11C12[2][A]	u_la0_top/u_ao_mem_ctrl/data_reg_Z[84]/Q
2.040	0.260	tNET	RR	1	BSRAM_R10[2]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_42/DI0

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	578	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	BSRAM_R10[2]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_42/CLKA
1.577	0.000	tUnc				u_la0_top/u_ao_mem_ctrl/mem_mem_0_42
1.826	0.249	tHld		1	BSRAM_R10[2]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_42

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.260, 56.314%; tC2Q: 0.202, 43.686%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path3

Path Summary:

Slack	0.225
Data Arrival Time	1.920
Data Required Time	1.695
From	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[10]
To	u_la0_top/u_ao_mem_ctrl/mem_mem_0_14
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	578	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R11C5[0][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[10]/CLK
1.778	0.201	tC2Q	RF	67	R11C5[0][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[10]/Q
1.920	0.142	tNET	FF	1	BSRAM_R10[0]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_14/ADA11

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	578	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	BSRAM_R10[0]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_14/CLKA
1.577	0.000	tUnc				u_la0_top/u_ao_mem_ctrl/mem_mem_0_14
1.695	0.118	tHld		1	BSRAM_R10[0]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_14

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.142, 41.325%; tC2Q: 0.201, 58.675%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path4

Path Summary:

Slack	0.233
Data Arrival Time	1.929
Data Required Time	1.695
From	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[12]
To	u_la0_top/u_ao_mem_ctrl/mem_mem_0_14
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	578	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R11C6[0][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[12]/CLK
1.779	0.202	tC2Q	RR	67	R11C6[0][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[12]/Q
1.929	0.149	tNET	RR	1	BSRAM_R10[0]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_14/ADA13

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	578	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	BSRAM_R10[0]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_14/CLKA
1.577	0.000	tUnc				u_la0_top/u_ao_mem_ctrl/mem_mem_0_14
1.695	0.118	tHld		1	BSRAM_R10[0]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_14

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.149, 42.496%; tC2Q: 0.202, 57.504%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path5

Path Summary:

Slack	0.342
Data Arrival Time	2.037
Data Required Time	1.695
From	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[6]
To	u_la0_top/u_ao_mem_ctrl/mem_mem_0_14
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	578	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R12C5[0][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[6]/CLK
1.779	0.202	tC2Q	RR	67	R12C5[0][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[6]/Q
2.037	0.258	tNET	RR	1	BSRAM_R10[0]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_14/ADA7

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	578	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	BSRAM_R10[0]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_14/CLKA
1.577	0.000	tUnc				u_la0_top/u_ao_mem_ctrl/mem_mem_0_14
1.695	0.118	tHld		1	BSRAM_R10[0]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_14

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.258, 56.063%; tC2Q: 0.202, 43.937%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path6

Path Summary:

Slack	0.352
Data Arrival Time	2.047
Data Required Time	1.695
From	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[11]
To	u_la0_top/u_ao_mem_ctrl/mem_mem_0_14
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	578	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R11C5[0][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[11]/CLK
1.779	0.202	tC2Q	RR	67	R11C5[0][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[11]/Q
2.047	0.268	tNET	RR	1	BSRAM_R10[0]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_14/ADA12

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	578	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	BSRAM_R10[0]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_14/CLKA
1.577	0.000	tUnc				u_la0_top/u_ao_mem_ctrl/mem_mem_0_14
1.695	0.118	tHld		1	BSRAM_R10[0]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_14

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.268, 56.996%; tC2Q: 0.202, 43.004%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path7

Path Summary:

Slack	0.354
Data Arrival Time	2.049
Data Required Time	1.695
From	cnt_1_Z[8]
To	memr_memr_0_15
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	578	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R39C47[2][A]	cnt_1_Z[8]/CLK
1.779	0.202	tC2Q	RR	33	R39C47[2][A]	cnt_1_Z[8]/Q
2.049	0.270	tNET	RR	1	BSRAM_R36[14]	memr_memr_0_15/ADB9

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	578	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	BSRAM_R36[14]	memr_memr_0_15/CLKB
1.577	0.000	tUnc				memr_memr_0_15
1.695	0.118	tHld		1	BSRAM_R36[14]	memr_memr_0_15

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.270, 57.198%; tC2Q: 0.202, 42.802%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path8

Path Summary:

Slack	0.354
Data Arrival Time	2.049
Data Required Time	1.695
From	cnt_1_Z[9]
To	memr_memr_0_15
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	578	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R39C47[2][B]	cnt_1_Z[9]/CLK
1.779	0.202	tC2Q	RR	33	R39C47[2][B]	cnt_1_Z[9]/Q
2.049	0.270	tNET	RR	1	BSRAM_R36[14]	memr_memr_0_15/ADB10

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	578	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	BSRAM_R36[14]	memr_memr_0_15/CLKB
1.577	0.000	tUnc				memr_memr_0_15
1.695	0.118	tHld		1	BSRAM_R36[14]	memr_memr_0_15

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.270, 57.203%; tC2Q: 0.202, 42.797%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path9

Path Summary:

Slack	0.359
Data Arrival Time	2.055
Data Required Time	1.695
From	cnt_1_Z[2]
To	memr_memr_0_13
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	578	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R39C46[2][A]	cnt_1_Z[2]/CLK
1.779	0.202	tC2Q	RR	33	R39C46[2][A]	cnt_1_Z[2]/Q
2.055	0.275	tNET	RR	1	BSRAM_R36[13]	memr_memr_0_13/ADB3

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	578	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	BSRAM_R36[13]	memr_memr_0_13/CLKB
1.577	0.000	tUnc				memr_memr_0_13
1.695	0.118	tHld		1	BSRAM_R36[13]	memr_memr_0_13

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.275, 57.682%; tC2Q: 0.202, 42.318%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path10

Path Summary:

Slack	0.361
Data Arrival Time	2.057
Data Required Time	1.695
From	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[1]
To	u_la0_top/u_ao_mem_ctrl/mem_mem_0_14
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	578	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R9C3[1][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[1]/CLK
1.779	0.202	tC2Q	RR	67	R9C3[1][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[1]/Q
2.057	0.277	tNET	RR	1	BSRAM_R10[0]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_14/ADA2

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	578	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	BSRAM_R10[0]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_14/CLKA
1.577	0.000	tUnc				u_la0_top/u_ao_mem_ctrl/mem_mem_0_14
1.695	0.118	tHld		1	BSRAM_R10[0]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_14

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.277, 57.861%; tC2Q: 0.202, 42.139%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path11

Path Summary:

Slack	0.366
Data Arrival Time	2.061
Data Required Time	1.695
From	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0]
To	u_la0_top/u_ao_mem_ctrl/mem_mem_0_14
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	578	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R9C3[1][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0]/CLK
1.779	0.202	tC2Q	RR	67	R9C3[1][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0]/Q
2.061	0.282	tNET	RR	1	BSRAM_R10[0]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_14/ADA1

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	578	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	BSRAM_R10[0]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_14/CLKA
1.577	0.000	tUnc				u_la0_top/u_ao_mem_ctrl/mem_mem_0_14
1.695	0.118	tHld		1	BSRAM_R10[0]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_14

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.282, 58.254%; tC2Q: 0.202, 41.746%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path12

Path Summary:

Slack	0.367
Data Arrival Time	2.063
Data Required Time	1.695
From	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[3]
To	u_la0_top/u_ao_mem_ctrl/mem_mem_0_14
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	578	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R9C3[2][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[3]/CLK
1.779	0.202	tC2Q	RR	67	R9C3[2][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[3]/Q
2.063	0.283	tNET	RR	1	BSRAM_R10[0]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_14/ADA4

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	578	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	BSRAM_R10[0]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_14/CLKA
1.577	0.000	tUnc				u_la0_top/u_ao_mem_ctrl/mem_mem_0_14
1.695	0.118	tHld		1	BSRAM_R10[0]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_14

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.283, 58.375%; tC2Q: 0.202, 41.625%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path13

Path Summary:

Slack	0.375
Data Arrival Time	2.201
Data Required Time	1.826
From	u_la0_top/u_ao_mem_ctrl/data_reg_Z[55]
To	u_la0_top/u_ao_mem_ctrl/mem_mem_0_27
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	578	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R20C21[0][B]	u_la0_top/u_ao_mem_ctrl/data_reg_Z[55]/CLK
1.779	0.202	tC2Q	RR	1	R20C21[0][B]	u_la0_top/u_ao_mem_ctrl/data_reg_Z[55]/Q
2.201	0.422	tNET	RR	1	BSRAM_R36[6]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_27/DI1

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	578	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	BSRAM_R36[6]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_27/CLKA
1.577	0.000	tUnc				u_la0_top/u_ao_mem_ctrl/mem_mem_0_27
1.826	0.249	tHld		1	BSRAM_R36[6]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_27

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.422, 67.614%; tC2Q: 0.202, 32.386%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path14

Path Summary:

Slack	0.421
Data Arrival Time	2.009
Data Required Time	1.588
From	Mdu/u_mdu/state[0]
To	m_Z[23]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	578	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R49C61[2][A]	Mdu/u_mdu/state[0]/CLK
1.778	0.201	tC2Q	RF	58	R49C61[2][A]	Mdu/u_mdu/state[0]/Q
1.778	0.000	tNET	FF	2	R34C49[1][A]	un1_m_cry_0_0/CIN
2.009	0.231	tINS	FF	1	R34C49[1][A]	un1_m_cry_0_0/SUM
2.009	0.000	tNET	FF	1	R34C49[1][A]	m_Z[23]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	578	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R34C49[1][A]	m_Z[23]/CLK
1.577	0.000	tUnc				m_Z[23]
1.588	0.011	tHld		1	R34C49[1][A]	m_Z[23]

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.231, 53.472%; route: 0.000, 0.000%; tC2Q: 0.201, 46.528%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path15

Path Summary:

Slack	0.427
Data Arrival Time	2.015
Data Required Time	1.588
From	u_la0_top/capture_window_sel_Z[0]
To	u_la0_top/capture_window_sel_Z[0]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	578	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R3C7[1][A]	u_la0_top/capture_window_sel_Z[0]/CLK
1.779	0.202	tC2Q	RR	7	R3C7[1][A]	u_la0_top/capture_window_sel_Z[0]/Q
1.783	0.004	tNET	RR	1	R3C7[1][A]	u_la0_top/capture_window_sel_3_cZ[0]/I2
2.015	0.232	tINS	RF	1	R3C7[1][A]	u_la0_top/capture_window_sel_3_cZ[0]/F
2.015	0.000	tNET	FF	1	R3C7[1][A]	u_la0_top/capture_window_sel_Z[0]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	578	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R3C7[1][A]	u_la0_top/capture_window_sel_Z[0]/CLK
1.577	0.000	tUnc				u_la0_top/capture_window_sel_Z[0]
1.588	0.011	tHld		1	R3C7[1][A]	u_la0_top/capture_window_sel_Z[0]

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.232, 53.008%; route: 0.004, 0.838%; tC2Q: 0.202, 46.154%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path16

Path Summary:

Slack	0.428
Data Arrival Time	2.016
Data Required Time	1.588
From	divisor_1[0]
To	divisor_1[0]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	578	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R34C51[0][A]	divisor_1[0]/CLK
1.779	0.202	tC2Q	RR	6	R34C51[0][A]	divisor_1[0]/Q
1.784	0.005	tNET	RR	1	R34C51[0][A]	remainder.divisor_1_1[0]/I0
2.016	0.232	tINS	RF	1	R34C51[0][A]	remainder.divisor_1_1[0]/F
2.016	0.000	tNET	FF	1	R34C51[0][A]	divisor_1[0]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	578	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R34C51[0][A]	divisor_1[0]/CLK
1.577	0.000	tUnc				divisor_1[0]
1.588	0.011	tHld		1	R34C51[0][A]	divisor_1[0]

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.232, 52.861%; route: 0.005, 1.114%; tC2Q: 0.202, 46.025%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path17

Path Summary:

Slack	0.428
Data Arrival Time	2.016
Data Required Time	1.588
From	divisor[24]
To	divisor[24]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	578	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R38C46[0][A]	divisor[24]/CLK
1.779	0.202	tC2Q	RR	6	R38C46[0][A]	divisor[24]/Q
1.784	0.005	tNET	RR	1	R38C46[0][A]	divisor_1_cZ[24]/I0
2.016	0.232	tINS	RF	1	R38C46[0][A]	divisor_1_cZ[24]/F
2.016	0.000	tNET	FF	1	R38C46[0][A]	divisor[24]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	578	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R38C46[0][A]	divisor[24]/CLK
1.577	0.000	tUnc				divisor[24]
1.588	0.011	tHld		1	R38C46[0][A]	divisor[24]

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.232, 52.861%; route: 0.005, 1.114%; tC2Q: 0.202, 46.025%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path18

Path Summary:

Slack	0.428
Data Arrival Time	2.016
Data Required Time	1.588
From	dividend[30]
To	dividend[30]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	578	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R38C49[0][A]	dividend[30]/CLK
1.779	0.202	tC2Q	RR	7	R38C49[0][A]	dividend[30]/Q
1.784	0.005	tNET	RR	1	R38C49[0][A]	dividend_1_cZ[30]/I0
2.016	0.232	tINS	RF	1	R38C49[0][A]	dividend_1_cZ[30]/F
2.016	0.000	tNET	FF	1	R38C49[0][A]	dividend[30]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	578	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R38C49[0][A]	dividend[30]/CLK
1.577	0.000	tUnc				dividend[30]
1.588	0.011	tHld		1	R38C49[0][A]	dividend[30]

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.232, 52.861%; route: 0.005, 1.114%; tC2Q: 0.202, 46.025%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path19

Path Summary:

Slack	0.428
Data Arrival Time	2.016
Data Required Time	1.588
From	divisor[31]
To	divisor[31]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	578	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R35C47[0][A]	divisor[31]/CLK
1.779	0.202	tC2Q	RR	61	R35C47[0][A]	divisor[31]/Q
1.784	0.005	tNET	RR	1	R35C47[0][A]	remainder.divisor_1[31]/I0
2.016	0.232	tINS	RF	1	R35C47[0][A]	remainder.divisor_1[31]/F
2.016	0.000	tNET	FF	1	R35C47[0][A]	divisor[31]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	578	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R35C47[0][A]	divisor[31]/CLK
1.577	0.000	tUnc				divisor[31]
1.588	0.011	tHld		1	R35C47[0][A]	divisor[31]

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.232, 52.861%; route: 0.005, 1.114%; tC2Q: 0.202, 46.025%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path20

Path Summary:

Slack	0.428
Data Arrival Time	2.016
Data Required Time	1.588
From	divisor[30]
To	divisor[30]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	578	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R38C48[1][A]	divisor[30]/CLK
1.779	0.202	tC2Q	RR	6	R38C48[1][A]	divisor[30]/Q
1.784	0.005	tNET	RR	1	R38C48[1][A]	divisor_1_cZ[30]/I0
2.016	0.232	tINS	RF	1	R38C48[1][A]	divisor_1_cZ[30]/F
2.016	0.000	tNET	FF	1	R38C48[1][A]	divisor[30]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	578	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R38C48[1][A]	divisor[30]/CLK
1.577	0.000	tUnc				divisor[30]
1.588	0.011	tHld		1	R38C48[1][A]	divisor[30]

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.232, 52.861%; route: 0.005, 1.114%; tC2Q: 0.202, 46.025%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path21

Path Summary:

Slack	0.429
Data Arrival Time	2.018
Data Required Time	1.588
From	dividend[28]
To	dividend[28]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	578	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R38C49[1][A]	dividend[28]/CLK
1.779	0.202	tC2Q	RR	7	R38C49[1][A]	dividend[28]/Q
1.786	0.006	tNET	RR	1	R38C49[1][A]	dividend_1_cZ[28]/I0
2.018	0.232	tINS	RF	1	R38C49[1][A]	dividend_1_cZ[28]/F
2.018	0.000	tNET	FF	1	R38C49[1][A]	dividend[28]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	578	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R38C49[1][A]	dividend[28]/CLK
1.577	0.000	tUnc				dividend[28]
1.588	0.011	tHld		1	R38C49[1][A]	dividend[28]

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.232, 52.714%; route: 0.006, 1.389%; tC2Q: 0.202, 45.898%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path22

Path Summary:

Slack	0.429
Data Arrival Time	2.018
Data Required Time	1.588
From	divisor[27]
To	divisor[27]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	578	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R34C48[0][A]	divisor[27]/CLK
1.779	0.202	tC2Q	RR	6	R34C48[0][A]	divisor[27]/Q
1.786	0.006	tNET	RR	1	R34C48[0][A]	divisor_1_cZ[27]/I0
2.018	0.232	tINS	RF	1	R34C48[0][A]	divisor_1_cZ[27]/F
2.018	0.000	tNET	FF	1	R34C48[0][A]	divisor[27]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	578	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R34C48[0][A]	divisor[27]/CLK
1.577	0.000	tUnc				divisor[27]
1.588	0.011	tHld		1	R34C48[0][A]	divisor[27]

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.232, 52.714%; route: 0.006, 1.389%; tC2Q: 0.202, 45.898%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path23

Path Summary:

Slack	0.429
Data Arrival Time	2.018
Data Required Time	1.588
From	Mdu/u_mdu/reg0_Z[54]
To	Mdu/u_mdu/reg0_Z[54]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	578	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R53C58[1][A]	Mdu/u_mdu/reg0_Z[54]/CLK
1.779	0.202	tC2Q	RR	12	R53C58[1][A]	Mdu/u_mdu/reg0_Z[54]/Q
1.786	0.006	tNET	RR	1	R53C58[1][A]	Mdu/u_mdu/reg0_nx_0[54]/I1
2.018	0.232	tINS	RF	1	R53C58[1][A]	Mdu/u_mdu/reg0_nx_0[54]/F
2.018	0.000	tNET	FF	1	R53C58[1][A]	Mdu/u_mdu/reg0_Z[54]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	578	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R53C58[1][A]	Mdu/u_mdu/reg0_Z[54]/CLK
1.577	0.000	tUnc				Mdu/u_mdu/reg0_Z[54]
1.588	0.011	tHld		1	R53C58[1][A]	Mdu/u_mdu/reg0_Z[54]

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.232, 52.714%; route: 0.006, 1.389%; tC2Q: 0.202, 45.898%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path24

Path Summary:

Slack	0.429
Data Arrival Time	2.018
Data Required Time	1.588
From	divisor[26]
To	divisor[26]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	578	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R35C48[0][A]	divisor[26]/CLK
1.779	0.202	tC2Q	RR	6	R35C48[0][A]	divisor[26]/Q
1.786	0.006	tNET	RR	1	R35C48[0][A]	divisor_1_cZ[26]/I0
2.018	0.232	tINS	RF	1	R35C48[0][A]	divisor_1_cZ[26]/F
2.018	0.000	tNET	FF	1	R35C48[0][A]	divisor[26]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	578	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R35C48[0][A]	divisor[26]/CLK
1.577	0.000	tUnc				divisor[26]
1.588	0.011	tHld		1	R35C48[0][A]	divisor[26]

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.232, 52.714%; route: 0.006, 1.389%; tC2Q: 0.202, 45.898%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path25

Path Summary:

Slack	0.432
Data Arrival Time	2.020
Data Required Time	1.588
From	Mdu/u_mdu/reg0_Z[50]
To	Mdu/u_mdu/reg0_Z[50]
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	578	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R46C61[0][A]	Mdu/u_mdu/reg0_Z[50]/CLK
1.779	0.202	tC2Q	RR	13	R46C61[0][A]	Mdu/u_mdu/reg0_Z[50]/Q
1.788	0.009	tNET	RR	1	R46C61[0][A]	Mdu/u_mdu/reg0_nx_0[50]/I1
2.020	0.232	tINS	RF	1	R46C61[0][A]	Mdu/u_mdu/reg0_nx_0[50]/F
2.020	0.000	tNET	FF	1	R46C61[0][A]	Mdu/u_mdu/reg0_Z[50]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	578	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R46C61[0][A]	Mdu/u_mdu/reg0_Z[50]/CLK
1.577	0.000	tUnc				Mdu/u_mdu/reg0_Z[50]
1.588	0.011	tHld		1	R46C61[0][A]	Mdu/u_mdu/reg0_Z[50]

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.232, 52.423%; route: 0.009, 1.933%; tC2Q: 0.202, 45.644%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Recovery Analysis Report

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	1.643
Data Arrival Time	10.005
Data Required Time	11.648
From	u_la0_top/rst_ao_Z
To	u_la0_top/triger_level_cnt_Z[0]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.688	0.688	tINS	FF	578	IOT48[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R9C3[0][B]	u_la0_top/rst_ao_Z/CLK
7.148	0.232	tC2Q	FF	49	R9C3[0][B]	u_la0_top/rst_ao_Z/Q
10.005	2.857	tNET	FF	1	R9C2[2][A]	u_la0_top/triger_level_cnt_Z[0]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	578	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R9C2[2][A]	u_la0_top/triger_level_cnt_Z[0]/CLK
11.683	-0.200	tUnc				u_la0_top/triger_level_cnt_Z[0]
11.648	-0.035	tSu		1	R9C2[2][A]	u_la0_top/triger_level_cnt_Z[0]

Path Statistics:

Clock Skew	-0.033
Setup Relationship	5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.857, 92.490%; tC2Q: 0.232, 7.510%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path2

Path Summary:

Slack	1.643
Data Arrival Time	10.005
Data Required Time	11.648
From	u_la0_top/rst_ao_Z
To	u_la0_top/triger_level_cnt_Z[2]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.688	0.688	tINS	FF	578	IOT48[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R9C3[0][B]	u_la0_top/rst_ao_Z/CLK
7.148	0.232	tC2Q	FF	49	R9C3[0][B]	u_la0_top/rst_ao_Z/Q
10.005	2.857	tNET	FF	1	R12C5[1][B]	u_la0_top/triger_level_cnt_Z[2]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	578	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R12C5[1][B]	u_la0_top/triger_level_cnt_Z[2]/CLK
11.683	-0.200	tUnc				u_la0_top/triger_level_cnt_Z[2]
11.648	-0.035	tSu		1	R12C5[1][B]	u_la0_top/triger_level_cnt_Z[2]

Path Statistics:

Clock Skew	-0.033
Setup Relationship	5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.857, 92.490%; tC2Q: 0.232, 7.510%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path3

Path Summary:

Slack	1.643
Data Arrival Time	10.005
Data Required Time	11.648
From	u_la0_top/rst_ao_Z
To	u_la0_top/capture_window_sel[3]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.688	0.688	tINS	FF	578	IOT48[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R9C3[0][B]	u_la0_top/rst_ao_Z/CLK
7.148	0.232	tC2Q	FF	49	R9C3[0][B]	u_la0_top/rst_ao_Z/Q
10.005	2.857	tNET	FF	1	R8C2[2][B]	u_la0_top/capture_window_sel[3]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	578	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R8C2[2][B]	u_la0_top/capture_window_sel[3]/CLK
11.683	-0.200	tUnc				u_la0_top/capture_window_sel[3]
11.648	-0.035	tSu		1	R8C2[2][B]	u_la0_top/capture_window_sel[3]

Path Statistics:

Clock Skew	-0.033
Setup Relationship	5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.857, 92.490%; tC2Q: 0.232, 7.510%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path4

Path Summary:

Slack	1.643
Data Arrival Time	10.005
Data Required Time	11.648
From	u_la0_top/rst_ao_Z
To	u_la0_top/internal_reg_force_triger_syn_Z[0]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.688	0.688	tINS	FF	578	IOT48[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R9C3[0][B]	u_la0_top/rst_ao_Z/CLK
7.148	0.232	tC2Q	FF	49	R9C3[0][B]	u_la0_top/rst_ao_Z/Q
10.005	2.857	tNET	FF	1	R11C6[2][B]	u_la0_top/internal_reg_force_triger_syn_Z[0]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	578	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R11C6[2][B]	u_la0_top/internal_reg_force_triger_syn_Z[0]/CLK
11.683	-0.200	tUnc				u_la0_top/internal_reg_force_triger_syn_Z[0]
11.648	-0.035	tSu		1	R11C6[2][B]	u_la0_top/internal_reg_force_triger_syn_Z[0]

Path Statistics:

Clock Skew	-0.033
Setup Relationship	5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.857, 92.490%; tC2Q: 0.232, 7.510%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path5

Path Summary:

Slack	1.643
Data Arrival Time	10.005
Data Required Time	11.648
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_length_Z[12]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.688	0.688	tINS	FF	578	IOT48[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R9C3[0][B]	u_la0_top/rst_ao_Z/CLK
7.148	0.232	tC2Q	FF	49	R9C3[0][B]	u_la0_top/rst_ao_Z/Q
10.005	2.857	tNET	FF	1	R2C4[2][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[12]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	578	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R2C4[2][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[12]/CLK
11.683	-0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_length_Z[12]
11.648	-0.035	tSu		1	R2C4[2][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[12]

Path Statistics:

Clock Skew	-0.033
Setup Relationship	5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.857, 92.490%; tC2Q: 0.232, 7.510%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path6

Path Summary:

Slack	1.643
Data Arrival Time	10.005
Data Required Time	11.648
From	u_la0_top/rst_ao_Z
To	u_la0_top/internal_reg_start_syn_Z[0]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.688	0.688	tINS	FF	578	IOT48[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R9C3[0][B]	u_la0_top/rst_ao_Z/CLK
7.148	0.232	tC2Q	FF	49	R9C3[0][B]	u_la0_top/rst_ao_Z/Q
10.005	2.857	tNET	FF	1	R9C11[0][A]	u_la0_top/internal_reg_start_syn_Z[0]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	578	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R9C11[0][A]	u_la0_top/internal_reg_start_syn_Z[0]/CLK
11.683	-0.200	tUnc				u_la0_top/internal_reg_start_syn_Z[0]
11.648	-0.035	tSu		1	R9C11[0][A]	u_la0_top/internal_reg_start_syn_Z[0]

Path Statistics:

Clock Skew	-0.033
Setup Relationship	5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.857, 92.490%; tC2Q: 0.232, 7.510%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path7

Path Summary:

Slack	1.643
Data Arrival Time	10.005
Data Required Time	11.648
From	u_la0_top/rst_ao_Z
To	u_la0_top/internal_reg_start_dly_Z[0]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.688	0.688	tINS	FF	578	IOT48[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R9C3[0][B]	u_la0_top/rst_ao_Z/CLK
7.148	0.232	tC2Q	FF	49	R9C3[0][B]	u_la0_top/rst_ao_Z/Q
10.005	2.857	tNET	FF	1	R3C7[0][B]	u_la0_top/internal_reg_start_dly_Z[0]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	578	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R3C7[0][B]	u_la0_top/internal_reg_start_dly_Z[0]/CLK
11.683	-0.200	tUnc				u_la0_top/internal_reg_start_dly_Z[0]
11.648	-0.035	tSu		1	R3C7[0][B]	u_la0_top/internal_reg_start_dly_Z[0]

Path Statistics:

Clock Skew	-0.033
Setup Relationship	5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.857, 92.490%; tC2Q: 0.232, 7.510%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path8

Path Summary:

Slack	1.643
Data Arrival Time	10.005
Data Required Time	11.648
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.688	0.688	tINS	FF	578	IOT48[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R9C3[0][B]	u_la0_top/rst_ao_Z/CLK
7.148	0.232	tC2Q	FF	49	R9C3[0][B]	u_la0_top/rst_ao_Z/Q
10.005	2.857	tNET	FF	1	R8C11[1][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	578	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R8C11[1][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z/CLK
11.683	-0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z
11.648	-0.035	tSu		1	R8C11[1][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z

Path Statistics:

Clock Skew	-0.033
Setup Relationship	5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.857, 92.490%; tC2Q: 0.232, 7.510%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path9

Path Summary:

Slack	1.643
Data Arrival Time	10.005
Data Required Time	11.648
From	u_la0_top/rst_ao_Z
To	u_la0_top/capture_window_sel_Z[2]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.688	0.688	tINS	FF	578	IOT48[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R9C3[0][B]	u_la0_top/rst_ao_Z/CLK
7.148	0.232	tC2Q	FF	49	R9C3[0][B]	u_la0_top/rst_ao_Z/Q
10.005	2.857	tNET	FF	1	R3C7[2][A]	u_la0_top/capture_window_sel_Z[2]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	578	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R3C7[2][A]	u_la0_top/capture_window_sel_Z[2]/CLK
11.683	-0.200	tUnc				u_la0_top/capture_window_sel_Z[2]
11.648	-0.035	tSu		1	R3C7[2][A]	u_la0_top/capture_window_sel_Z[2]

Path Statistics:

Clock Skew	-0.033
Setup Relationship	5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.857, 92.490%; tC2Q: 0.232, 7.510%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path10

Path Summary:

Slack	1.643
Data Arrival Time	10.005
Data Required Time	11.648
From	u_la0_top/rst_ao_Z
To	u_la0_top/capture_end_dly_Z
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.688	0.688	tINS	FF	578	IOT48[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R9C3[0][B]	u_la0_top/rst_ao_Z/CLK
7.148	0.232	tC2Q	FF	49	R9C3[0][B]	u_la0_top/rst_ao_Z/Q
10.005	2.857	tNET	FF	1	R11C2[2][B]	u_la0_top/capture_end_dly_Z/PRESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	578	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R11C2[2][B]	u_la0_top/capture_end_dly_Z/CLK
11.683	-0.200	tUnc				u_la0_top/capture_end_dly_Z
11.648	-0.035	tSu		1	R11C2[2][B]	u_la0_top/capture_end_dly_Z

Path Statistics:

Clock Skew	-0.033
Setup Relationship	5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.857, 92.490%; tC2Q: 0.232, 7.510%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path11

Path Summary:

Slack	1.643
Data Arrival Time	10.005
Data Required Time	11.648
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.688	0.688	tINS	FF	578	IOT48[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R9C3[0][B]	u_la0_top/rst_ao_Z/CLK
7.148	0.232	tC2Q	FF	49	R9C3[0][B]	u_la0_top/rst_ao_Z/Q
10.005	2.857	tNET	FF	1	R9C3[1][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	578	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R9C3[1][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0]/CLK
11.683	-0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0]
11.648	-0.035	tSu		1	R9C3[1][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0]

Path Statistics:

Clock Skew	-0.033
Setup Relationship	5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.857, 92.490%; tC2Q: 0.232, 7.510%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path12

Path Summary:

Slack	1.643
Data Arrival Time	10.005
Data Required Time	11.648
From	u_la0_top/rst_ao_Z
To	u_la0_top/capture_window_sel_Z[1]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.688	0.688	tINS	FF	578	IOT48[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R9C3[0][B]	u_la0_top/rst_ao_Z/CLK
7.148	0.232	tC2Q	FF	49	R9C3[0][B]	u_la0_top/rst_ao_Z/Q
10.005	2.857	tNET	FF	1	R3C7[1][B]	u_la0_top/capture_window_sel_Z[1]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	578	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R3C7[1][B]	u_la0_top/capture_window_sel_Z[1]/CLK
11.683	-0.200	tUnc				u_la0_top/capture_window_sel_Z[1]
11.648	-0.035	tSu		1	R3C7[1][B]	u_la0_top/capture_window_sel_Z[1]

Path Statistics:

Clock Skew	-0.033
Setup Relationship	5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.857, 92.490%; tC2Q: 0.232, 7.510%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path13

Path Summary:

Slack	1.643
Data Arrival Time	10.005
Data Required Time	11.648
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_length_Z[4]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.688	0.688	tINS	FF	578	IOT48[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R9C3[0][B]	u_la0_top/rst_ao_Z/CLK
7.148	0.232	tC2Q	FF	49	R9C3[0][B]	u_la0_top/rst_ao_Z/Q
10.005	2.857	tNET	FF	1	R8C2[0][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[4]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	578	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R8C2[0][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[4]/CLK
11.683	-0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_length_Z[4]
11.648	-0.035	tSu		1	R8C2[0][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[4]

Path Statistics:

Clock Skew	-0.033
Setup Relationship	5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.857, 92.490%; tC2Q: 0.232, 7.510%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path14

Path Summary:

Slack	1.643
Data Arrival Time	10.005
Data Required Time	11.648
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_length_Z[3]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.688	0.688	tINS	FF	578	IOT48[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R9C3[0][B]	u_la0_top/rst_ao_Z/CLK
7.148	0.232	tC2Q	FF	49	R9C3[0][B]	u_la0_top/rst_ao_Z/Q
10.005	2.857	tNET	FF	1	R11C9[1][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[3]/PRESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	578	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R11C9[1][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[3]/CLK
11.683	-0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_length_Z[3]
11.648	-0.035	tSu		1	R11C9[1][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[3]

Path Statistics:

Clock Skew	-0.033
Setup Relationship	5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.857, 92.490%; tC2Q: 0.232, 7.510%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path15

Path Summary:

Slack	1.643
Data Arrival Time	10.005
Data Required Time	11.648
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_length_Z[9]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.688	0.688	tINS	FF	578	IOT48[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R9C3[0][B]	u_la0_top/rst_ao_Z/CLK
7.148	0.232	tC2Q	FF	49	R9C3[0][B]	u_la0_top/rst_ao_Z/Q
10.005	2.857	tNET	FF	1	R11C2[1][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[9]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	578	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R11C2[1][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[9]/CLK
11.683	-0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_length_Z[9]
11.648	-0.035	tSu		1	R11C2[1][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[9]

Path Statistics:

Clock Skew	-0.033
Setup Relationship	5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.857, 92.490%; tC2Q: 0.232, 7.510%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path16

Path Summary:

Slack	1.643
Data Arrival Time	10.005
Data Required Time	11.648
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[12]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.688	0.688	tINS	FF	578	IOT48[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R9C3[0][B]	u_la0_top/rst_ao_Z/CLK
7.148	0.232	tC2Q	FF	49	R9C3[0][B]	u_la0_top/rst_ao_Z/Q
10.005	2.857	tNET	FF	1	R11C6[0][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[12]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	578	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R11C6[0][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[12]/CLK
11.683	-0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[12]
11.648	-0.035	tSu		1	R11C6[0][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[12]

Path Statistics:

Clock Skew	-0.033
Setup Relationship	5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.857, 92.490%; tC2Q: 0.232, 7.510%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path17

Path Summary:

Slack	1.643
Data Arrival Time	10.005
Data Required Time	11.648
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[2]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.688	0.688	tINS	FF	578	IOT48[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R9C3[0][B]	u_la0_top/rst_ao_Z/CLK
7.148	0.232	tC2Q	FF	49	R9C3[0][B]	u_la0_top/rst_ao_Z/Q
10.005	2.857	tNET	FF	1	R9C3[2][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[2]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	578	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R9C3[2][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[2]/CLK
11.683	-0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[2]
11.648	-0.035	tSu		1	R9C3[2][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[2]

Path Statistics:

Clock Skew	-0.033
Setup Relationship	5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.857, 92.490%; tC2Q: 0.232, 7.510%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path18

Path Summary:

Slack	1.643
Data Arrival Time	10.005
Data Required Time	11.648
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[1]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.688	0.688	tINS	FF	578	IOT48[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R9C3[0][B]	u_la0_top/rst_ao_Z/CLK
7.148	0.232	tC2Q	FF	49	R9C3[0][B]	u_la0_top/rst_ao_Z/Q
10.005	2.857	tNET	FF	1	R9C3[1][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[1]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	578	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R9C3[1][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[1]/CLK
11.683	-0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[1]
11.648	-0.035	tSu		1	R9C3[1][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[1]

Path Statistics:

Clock Skew	-0.033
Setup Relationship	5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.857, 92.490%; tC2Q: 0.232, 7.510%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path19

Path Summary:

Slack	1.643
Data Arrival Time	10.005
Data Required Time	11.648
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_length_Z[7]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.688	0.688	tINS	FF	578	IOT48[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R9C3[0][B]	u_la0_top/rst_ao_Z/CLK
7.148	0.232	tC2Q	FF	49	R9C3[0][B]	u_la0_top/rst_ao_Z/Q
10.005	2.857	tNET	FF	1	R11C2[2][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[7]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	578	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R11C2[2][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[7]/CLK
11.683	-0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_length_Z[7]
11.648	-0.035	tSu		1	R11C2[2][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[7]

Path Statistics:

Clock Skew	-0.033
Setup Relationship	5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.857, 92.490%; tC2Q: 0.232, 7.510%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path20

Path Summary:

Slack	1.643
Data Arrival Time	10.005
Data Required Time	11.648
From	u_la0_top/rst_ao_Z
To	u_la0_top/trigger_seq_start_Z
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.688	0.688	tINS	FF	578	IOT48[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R9C3[0][B]	u_la0_top/rst_ao_Z/CLK
7.148	0.232	tC2Q	FF	49	R9C3[0][B]	u_la0_top/rst_ao_Z/Q
10.005	2.857	tNET	FF	1	R11C6[1][A]	u_la0_top/trigger_seq_start_Z/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	578	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R11C6[1][A]	u_la0_top/trigger_seq_start_Z/CLK
11.683	-0.200	tUnc				u_la0_top/trigger_seq_start_Z
11.648	-0.035	tSu		1	R11C6[1][A]	u_la0_top/trigger_seq_start_Z

Path Statistics:

Clock Skew	-0.033
Setup Relationship	5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.857, 92.490%; tC2Q: 0.232, 7.510%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path21

Path Summary:

Slack	1.643
Data Arrival Time	10.005
Data Required Time	11.648
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[9]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.688	0.688	tINS	FF	578	IOT48[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R9C3[0][B]	u_la0_top/rst_ao_Z/CLK
7.148	0.232	tC2Q	FF	49	R9C3[0][B]	u_la0_top/rst_ao_Z/Q
10.005	2.857	tNET	FF	1	R11C2[0][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[9]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	578	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R11C2[0][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[9]/CLK
11.683	-0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[9]
11.648	-0.035	tSu		1	R11C2[0][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[9]

Path Statistics:

Clock Skew	-0.033
Setup Relationship	5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.857, 92.490%; tC2Q: 0.232, 7.510%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path22

Path Summary:

Slack	1.643
Data Arrival Time	10.005
Data Required Time	11.648
From	u_la0_top/rst_ao_Z
To	u_la0_top/genblk1.u_ao_match_0/match_sep
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.688	0.688	tINS	FF	578	IOT48[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R9C3[0][B]	u_la0_top/rst_ao_Z/CLK
7.148	0.232	tC2Q	FF	49	R9C3[0][B]	u_la0_top/rst_ao_Z/Q
10.005	2.857	tNET	FF	1	R3C7[0][A]	u_la0_top/genblk1.u_ao_match_0/match_sep/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	578	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R3C7[0][A]	u_la0_top/genblk1.u_ao_match_0/match_sep/CLK
11.683	-0.200	tUnc				u_la0_top/genblk1.u_ao_match_0/match_sep
11.648	-0.035	tSu		1	R3C7[0][A]	u_la0_top/genblk1.u_ao_match_0/match_sep

Path Statistics:

Clock Skew	-0.033
Setup Relationship	5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.857, 92.490%; tC2Q: 0.232, 7.510%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path23

Path Summary:

Slack	1.643
Data Arrival Time	10.005
Data Required Time	11.648
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[3]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.688	0.688	tINS	FF	578	IOT48[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R9C3[0][B]	u_la0_top/rst_ao_Z/CLK
7.148	0.232	tC2Q	FF	49	R9C3[0][B]	u_la0_top/rst_ao_Z/Q
10.005	2.857	tNET	FF	1	R9C3[2][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[3]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	578	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R9C3[2][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[3]/CLK
11.683	-0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[3]
11.648	-0.035	tSu		1	R9C3[2][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[3]

Path Statistics:

Clock Skew	-0.033
Setup Relationship	5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.857, 92.490%; tC2Q: 0.232, 7.510%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path24

Path Summary:

Slack	1.643
Data Arrival Time	10.005
Data Required Time	11.648
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.688	0.688	tINS	FF	578	IOT48[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R9C3[0][B]	u_la0_top/rst_ao_Z/CLK
7.148	0.232	tC2Q	FF	49	R9C3[0][B]	u_la0_top/rst_ao_Z/Q
10.005	2.857	tNET	FF	1	R11C2[0][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	578	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R11C2[0][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8]/CLK
11.683	-0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8]
11.648	-0.035	tSu		1	R11C2[0][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8]

Path Statistics:

Clock Skew	-0.033
Setup Relationship	5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.857, 92.490%; tC2Q: 0.232, 7.510%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path25

Path Summary:

Slack	1.643
Data Arrival Time	10.005
Data Required Time	11.648
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_length_Z[2]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.688	0.688	tINS	FF	578	IOT48[A]	clk_ibuf/O
6.916	1.228	tNET	FF	1	R9C3[0][B]	u_la0_top/rst_ao_Z/CLK
7.148	0.232	tC2Q	FF	49	R9C3[0][B]	u_la0_top/rst_ao_Z/Q
10.005	2.857	tNET	FF	1	R9C2[2][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[2]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
10.682	0.683	tINS	RR	578	IOT48[A]	clk_ibuf/O
11.883	1.201	tNET	RR	1	R9C2[2][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[2]/CLK
11.683	-0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_length_Z[2]
11.648	-0.035	tSu		1	R9C2[2][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[2]

Path Statistics:

Clock Skew	-0.033
Setup Relationship	5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.857, 92.490%; tC2Q: 0.232, 7.510%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Removal Analysis Report

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	6.772
Data Arrival Time	8.560
Data Required Time	1.788
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.677	0.678	tINS	FF	578	IOT48[A]	clk_ibuf/O
6.590	0.913	tNET	FF	1	R9C3[0][B]	u_la0_top/rst_ao_Z/CLK
6.792	0.202	tC2Q	FR	49	R9C3[0][B]	u_la0_top/rst_ao_Z/Q
8.560	1.768	tNET	RR	1	R8C11[1][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	578	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R8C11[1][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z/CLK
1.777	0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z
1.788	0.011	tHld		1	R8C11[1][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.768, 89.747%; tC2Q: 0.202, 10.253%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path2

Path Summary:

Slack	6.772
Data Arrival Time	8.560
Data Required Time	1.788
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_loop_Z
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.677	0.678	tINS	FF	578	IOT48[A]	clk_ibuf/O
6.590	0.913	tNET	FF	1	R9C3[0][B]	u_la0_top/rst_ao_Z/CLK
6.792	0.202	tC2Q	FR	49	R9C3[0][B]	u_la0_top/rst_ao_Z/Q
8.560	1.768	tNET	RR	1	R8C11[2][A]	u_la0_top/u_ao_mem_ctrl/capture_loop_Z/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	578	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R8C11[2][A]	u_la0_top/u_ao_mem_ctrl/capture_loop_Z/CLK
1.777	0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_loop_Z
1.788	0.011	tHld		1	R8C11[2][A]	u_la0_top/u_ao_mem_ctrl/capture_loop_Z

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.768, 89.747%; tC2Q: 0.202, 10.253%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path3

Path Summary:

Slack	6.772
Data Arrival Time	8.560
Data Required Time	1.788
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_length_Z[0]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.677	0.678	tINS	FF	578	IOT48[A]	clk_ibuf/O
6.590	0.913	tNET	FF	1	R9C3[0][B]	u_la0_top/rst_ao_Z/CLK
6.792	0.202	tC2Q	FR	49	R9C3[0][B]	u_la0_top/rst_ao_Z/Q
8.560	1.768	tNET	RR	1	R11C8[0][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[0]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	578	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R11C8[0][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[0]/CLK
1.777	0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_length_Z[0]
1.788	0.011	tHld		1	R11C8[0][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[0]

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.768, 89.747%; tC2Q: 0.202, 10.253%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path4

Path Summary:

Slack	6.772
Data Arrival Time	8.560
Data Required Time	1.788
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_length_Z[1]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.677	0.678	tINS	FF	578	IOT48[A]	clk_ibuf/O
6.590	0.913	tNET	FF	1	R9C3[0][B]	u_la0_top/rst_ao_Z/CLK
6.792	0.202	tC2Q	FR	49	R9C3[0][B]	u_la0_top/rst_ao_Z/Q
8.560	1.768	tNET	RR	1	R8C11[0][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[1]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	578	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R8C11[0][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[1]/CLK
1.777	0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_length_Z[1]
1.788	0.011	tHld		1	R8C11[0][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[1]

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.768, 89.747%; tC2Q: 0.202, 10.253%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path5

Path Summary:

Slack	6.772
Data Arrival Time	8.560
Data Required Time	1.788
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_length_Z[2]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.677	0.678	tINS	FF	578	IOT48[A]	clk_ibuf/O
6.590	0.913	tNET	FF	1	R9C3[0][B]	u_la0_top/rst_ao_Z/CLK
6.792	0.202	tC2Q	FR	49	R9C3[0][B]	u_la0_top/rst_ao_Z/Q
8.560	1.768	tNET	RR	1	R9C2[2][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[2]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	578	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R9C2[2][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[2]/CLK
1.777	0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_length_Z[2]
1.788	0.011	tHld		1	R9C2[2][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[2]

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.768, 89.747%; tC2Q: 0.202, 10.253%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path6

Path Summary:

Slack	6.772
Data Arrival Time	8.560
Data Required Time	1.788
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_length_Z[4]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.677	0.678	tINS	FF	578	IOT48[A]	clk_ibuf/O
6.590	0.913	tNET	FF	1	R9C3[0][B]	u_la0_top/rst_ao_Z/CLK
6.792	0.202	tC2Q	FR	49	R9C3[0][B]	u_la0_top/rst_ao_Z/Q
8.560	1.768	tNET	RR	1	R8C2[0][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[4]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	578	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R8C2[0][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[4]/CLK
1.777	0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_length_Z[4]
1.788	0.011	tHld		1	R8C2[0][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[4]

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.768, 89.747%; tC2Q: 0.202, 10.253%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path7

Path Summary:

Slack	6.772
Data Arrival Time	8.560
Data Required Time	1.788
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_length_Z[5]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.677	0.678	tINS	FF	578	IOT48[A]	clk_ibuf/O
6.590	0.913	tNET	FF	1	R9C3[0][B]	u_la0_top/rst_ao_Z/CLK
6.792	0.202	tC2Q	FR	49	R9C3[0][B]	u_la0_top/rst_ao_Z/Q
8.560	1.768	tNET	RR	1	R8C3[2][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[5]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	578	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R8C3[2][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[5]/CLK
1.777	0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_length_Z[5]
1.788	0.011	tHld		1	R8C3[2][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[5]

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.768, 89.747%; tC2Q: 0.202, 10.253%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path8

Path Summary:

Slack	6.772
Data Arrival Time	8.560
Data Required Time	1.788
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_length_Z[7]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.677	0.678	tINS	FF	578	IOT48[A]	clk_ibuf/O
6.590	0.913	tNET	FF	1	R9C3[0][B]	u_la0_top/rst_ao_Z/CLK
6.792	0.202	tC2Q	FR	49	R9C3[0][B]	u_la0_top/rst_ao_Z/Q
8.560	1.768	tNET	RR	1	R11C2[2][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[7]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	578	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R11C2[2][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[7]/CLK
1.777	0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_length_Z[7]
1.788	0.011	tHld		1	R11C2[2][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[7]

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.768, 89.747%; tC2Q: 0.202, 10.253%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path9

Path Summary:

Slack	6.772
Data Arrival Time	8.560
Data Required Time	1.788
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_length_Z[8]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.677	0.678	tINS	FF	578	IOT48[A]	clk_ibuf/O
6.590	0.913	tNET	FF	1	R9C3[0][B]	u_la0_top/rst_ao_Z/CLK
6.792	0.202	tC2Q	FR	49	R9C3[0][B]	u_la0_top/rst_ao_Z/Q
8.560	1.768	tNET	RR	1	R11C2[1][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[8]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	578	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R11C2[1][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[8]/CLK
1.777	0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_length_Z[8]
1.788	0.011	tHld		1	R11C2[1][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[8]

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.768, 89.747%; tC2Q: 0.202, 10.253%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path10

Path Summary:

Slack	6.772
Data Arrival Time	8.560
Data Required Time	1.788
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_length_Z[9]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.677	0.678	tINS	FF	578	IOT48[A]	clk_ibuf/O
6.590	0.913	tNET	FF	1	R9C3[0][B]	u_la0_top/rst_ao_Z/CLK
6.792	0.202	tC2Q	FR	49	R9C3[0][B]	u_la0_top/rst_ao_Z/Q
8.560	1.768	tNET	RR	1	R11C2[1][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[9]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	578	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R11C2[1][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[9]/CLK
1.777	0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_length_Z[9]
1.788	0.011	tHld		1	R11C2[1][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[9]

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.768, 89.747%; tC2Q: 0.202, 10.253%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path11

Path Summary:

Slack	6.772
Data Arrival Time	8.560
Data Required Time	1.788
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_length_Z[10]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.677	0.678	tINS	FF	578	IOT48[A]	clk_ibuf/O
6.590	0.913	tNET	FF	1	R9C3[0][B]	u_la0_top/rst_ao_Z/CLK
6.792	0.202	tC2Q	FR	49	R9C3[0][B]	u_la0_top/rst_ao_Z/Q
8.560	1.768	tNET	RR	1	R8C2[2][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[10]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	578	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R8C2[2][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[10]/CLK
1.777	0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_length_Z[10]
1.788	0.011	tHld		1	R8C2[2][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[10]

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.768, 89.747%; tC2Q: 0.202, 10.253%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path12

Path Summary:

Slack	6.772
Data Arrival Time	8.560
Data Required Time	1.788
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_length_Z[11]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.677	0.678	tINS	FF	578	IOT48[A]	clk_ibuf/O
6.590	0.913	tNET	FF	1	R9C3[0][B]	u_la0_top/rst_ao_Z/CLK
6.792	0.202	tC2Q	FR	49	R9C3[0][B]	u_la0_top/rst_ao_Z/Q
8.560	1.768	tNET	RR	1	R8C2[0][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[11]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	578	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R8C2[0][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[11]/CLK
1.777	0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_length_Z[11]
1.788	0.011	tHld		1	R8C2[0][B]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[11]

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.768, 89.747%; tC2Q: 0.202, 10.253%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path13

Path Summary:

Slack	6.772
Data Arrival Time	8.560
Data Required Time	1.788
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_length_Z[12]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.677	0.678	tINS	FF	578	IOT48[A]	clk_ibuf/O
6.590	0.913	tNET	FF	1	R9C3[0][B]	u_la0_top/rst_ao_Z/CLK
6.792	0.202	tC2Q	FR	49	R9C3[0][B]	u_la0_top/rst_ao_Z/Q
8.560	1.768	tNET	RR	1	R2C4[2][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[12]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	578	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R2C4[2][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[12]/CLK
1.777	0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_length_Z[12]
1.788	0.011	tHld		1	R2C4[2][A]	u_la0_top/u_ao_mem_ctrl/capture_length_Z[12]

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.768, 89.747%; tC2Q: 0.202, 10.253%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path14

Path Summary:

Slack	6.772
Data Arrival Time	8.560
Data Required Time	1.788
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.677	0.678	tINS	FF	578	IOT48[A]	clk_ibuf/O
6.590	0.913	tNET	FF	1	R9C3[0][B]	u_la0_top/rst_ao_Z/CLK
6.792	0.202	tC2Q	FR	49	R9C3[0][B]	u_la0_top/rst_ao_Z/Q
8.560	1.768	tNET	RR	1	R9C3[1][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	578	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R9C3[1][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0]/CLK
1.777	0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0]
1.788	0.011	tHld		1	R9C3[1][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0]

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.768, 89.747%; tC2Q: 0.202, 10.253%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path15

Path Summary:

Slack	6.772
Data Arrival Time	8.560
Data Required Time	1.788
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[1]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.677	0.678	tINS	FF	578	IOT48[A]	clk_ibuf/O
6.590	0.913	tNET	FF	1	R9C3[0][B]	u_la0_top/rst_ao_Z/CLK
6.792	0.202	tC2Q	FR	49	R9C3[0][B]	u_la0_top/rst_ao_Z/Q
8.560	1.768	tNET	RR	1	R9C3[1][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[1]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	578	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R9C3[1][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[1]/CLK
1.777	0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[1]
1.788	0.011	tHld		1	R9C3[1][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[1]

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.768, 89.747%; tC2Q: 0.202, 10.253%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path16

Path Summary:

Slack	6.772
Data Arrival Time	8.560
Data Required Time	1.788
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[2]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.677	0.678	tINS	FF	578	IOT48[A]	clk_ibuf/O
6.590	0.913	tNET	FF	1	R9C3[0][B]	u_la0_top/rst_ao_Z/CLK
6.792	0.202	tC2Q	FR	49	R9C3[0][B]	u_la0_top/rst_ao_Z/Q
8.560	1.768	tNET	RR	1	R9C3[2][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[2]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	578	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R9C3[2][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[2]/CLK
1.777	0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[2]
1.788	0.011	tHld		1	R9C3[2][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[2]

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.768, 89.747%; tC2Q: 0.202, 10.253%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path17

Path Summary:

Slack	6.772
Data Arrival Time	8.560
Data Required Time	1.788
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[3]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.677	0.678	tINS	FF	578	IOT48[A]	clk_ibuf/O
6.590	0.913	tNET	FF	1	R9C3[0][B]	u_la0_top/rst_ao_Z/CLK
6.792	0.202	tC2Q	FR	49	R9C3[0][B]	u_la0_top/rst_ao_Z/Q
8.560	1.768	tNET	RR	1	R9C3[2][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[3]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	578	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R9C3[2][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[3]/CLK
1.777	0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[3]
1.788	0.011	tHld		1	R9C3[2][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[3]

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.768, 89.747%; tC2Q: 0.202, 10.253%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path18

Path Summary:

Slack	6.772
Data Arrival Time	8.560
Data Required Time	1.788
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[4]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.677	0.678	tINS	FF	578	IOT48[A]	clk_ibuf/O
6.590	0.913	tNET	FF	1	R9C3[0][B]	u_la0_top/rst_ao_Z/CLK
6.792	0.202	tC2Q	FR	49	R9C3[0][B]	u_la0_top/rst_ao_Z/Q
8.560	1.768	tNET	RR	1	R9C2[0][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[4]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	578	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R9C2[0][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[4]/CLK
1.777	0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[4]
1.788	0.011	tHld		1	R9C2[0][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[4]

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.768, 89.747%; tC2Q: 0.202, 10.253%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path19

Path Summary:

Slack	6.772
Data Arrival Time	8.560
Data Required Time	1.788
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[5]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.677	0.678	tINS	FF	578	IOT48[A]	clk_ibuf/O
6.590	0.913	tNET	FF	1	R9C3[0][B]	u_la0_top/rst_ao_Z/CLK
6.792	0.202	tC2Q	FR	49	R9C3[0][B]	u_la0_top/rst_ao_Z/Q
8.560	1.768	tNET	RR	1	R11C6[0][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[5]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	578	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R11C6[0][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[5]/CLK
1.777	0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[5]
1.788	0.011	tHld		1	R11C6[0][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[5]

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.768, 89.747%; tC2Q: 0.202, 10.253%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path20

Path Summary:

Slack	6.772
Data Arrival Time	8.560
Data Required Time	1.788
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[6]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.677	0.678	tINS	FF	578	IOT48[A]	clk_ibuf/O
6.590	0.913	tNET	FF	1	R9C3[0][B]	u_la0_top/rst_ao_Z/CLK
6.792	0.202	tC2Q	FR	49	R9C3[0][B]	u_la0_top/rst_ao_Z/Q
8.560	1.768	tNET	RR	1	R12C5[0][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[6]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	578	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R12C5[0][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[6]/CLK
1.777	0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[6]
1.788	0.011	tHld		1	R12C5[0][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[6]

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.768, 89.747%; tC2Q: 0.202, 10.253%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path21

Path Summary:

Slack	6.772
Data Arrival Time	8.560
Data Required Time	1.788
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[7]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.677	0.678	tINS	FF	578	IOT48[A]	clk_ibuf/O
6.590	0.913	tNET	FF	1	R9C3[0][B]	u_la0_top/rst_ao_Z/CLK
6.792	0.202	tC2Q	FR	49	R9C3[0][B]	u_la0_top/rst_ao_Z/Q
8.560	1.768	tNET	RR	1	R9C2[0][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[7]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	578	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R9C2[0][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[7]/CLK
1.777	0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[7]
1.788	0.011	tHld		1	R9C2[0][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[7]

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.768, 89.747%; tC2Q: 0.202, 10.253%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path22

Path Summary:

Slack	6.772
Data Arrival Time	8.560
Data Required Time	1.788
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.677	0.678	tINS	FF	578	IOT48[A]	clk_ibuf/O
6.590	0.913	tNET	FF	1	R9C3[0][B]	u_la0_top/rst_ao_Z/CLK
6.792	0.202	tC2Q	FR	49	R9C3[0][B]	u_la0_top/rst_ao_Z/Q
8.560	1.768	tNET	RR	1	R11C2[0][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	578	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R11C2[0][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8]/CLK
1.777	0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8]
1.788	0.011	tHld		1	R11C2[0][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8]

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.768, 89.747%; tC2Q: 0.202, 10.253%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path23

Path Summary:

Slack	6.772
Data Arrival Time	8.560
Data Required Time	1.788
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[9]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.677	0.678	tINS	FF	578	IOT48[A]	clk_ibuf/O
6.590	0.913	tNET	FF	1	R9C3[0][B]	u_la0_top/rst_ao_Z/CLK
6.792	0.202	tC2Q	FR	49	R9C3[0][B]	u_la0_top/rst_ao_Z/Q
8.560	1.768	tNET	RR	1	R11C2[0][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[9]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	578	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R11C2[0][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[9]/CLK
1.777	0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[9]
1.788	0.011	tHld		1	R11C2[0][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[9]

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.768, 89.747%; tC2Q: 0.202, 10.253%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path24

Path Summary:

Slack	6.772
Data Arrival Time	8.560
Data Required Time	1.788
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[10]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.677	0.678	tINS	FF	578	IOT48[A]	clk_ibuf/O
6.590	0.913	tNET	FF	1	R9C3[0][B]	u_la0_top/rst_ao_Z/CLK
6.792	0.202	tC2Q	FR	49	R9C3[0][B]	u_la0_top/rst_ao_Z/Q
8.560	1.768	tNET	RR	1	R11C5[0][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[10]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	578	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R11C5[0][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[10]/CLK
1.777	0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[10]
1.788	0.011	tHld		1	R11C5[0][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[10]

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.768, 89.747%; tC2Q: 0.202, 10.253%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path25

Path Summary:

Slack	6.772
Data Arrival Time	8.560
Data Required Time	1.788
From	u_la0_top/rst_ao_Z
To	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[11]
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	1	IOT48[A]	clk_ibuf/I
5.677	0.678	tINS	FF	578	IOT48[A]	clk_ibuf/O
6.590	0.913	tNET	FF	1	R9C3[0][B]	u_la0_top/rst_ao_Z/CLK
6.792	0.202	tC2Q	FR	49	R9C3[0][B]	u_la0_top/rst_ao_Z/Q
8.560	1.768	tNET	RR	1	R11C5[0][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[11]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK(clock)
0.000	0.000	tCL	RR	1	IOT48[A]	clk_ibuf/I
0.675	0.675	tINS	RR	578	IOT48[A]	clk_ibuf/O
1.577	0.902	tNET	RR	1	R11C5[0][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[11]/CLK
1.777	0.200	tUnc				u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[11]
1.788	0.011	tHld		1	R11C5[0][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[11]

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-5.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.768, 89.747%; tC2Q: 0.202, 10.253%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Minimum Pulse Width Report:

Report Command:report_min_pulse_width -nworst 10 -detail

MPW1

MPW Summary:

Slack:	3.662
Actual Width:	4.662
Required Width:	1.000
Type:	Low Pulse Width
Clock:	DEFAULT_CLK
Objects:	cnt_1_Z[12]

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	clk_ibuf/I
5.688	0.688	tINS	FF	clk_ibuf/O
6.916	1.228	tNET	FF	cnt_1_Z[12]/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	clk_ibuf/I
10.675	0.675	tINS	RR	clk_ibuf/O
11.577	0.902	tNET	RR	cnt_1_Z[12]/CLK

MPW2

MPW Summary:

Slack:	3.662
Actual Width:	4.662
Required Width:	1.000
Type:	Low Pulse Width
Clock:	DEFAULT_CLK
Objects:	cnt_1_Z[10]

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	clk_ibuf/I
5.688	0.688	tINS	FF	clk_ibuf/O
6.916	1.228	tNET	FF	cnt_1_Z[10]/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	clk_ibuf/I
10.675	0.675	tINS	RR	clk_ibuf/O
11.577	0.902	tNET	RR	cnt_1_Z[10]/CLK

MPW3

MPW Summary:

Slack:	3.662
Actual Width:	4.662
Required Width:	1.000
Type:	Low Pulse Width
Clock:	DEFAULT_CLK
Objects:	cnt_1_Z[6]

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	clk_ibuf/I
5.688	0.688	tINS	FF	clk_ibuf/O
6.916	1.228	tNET	FF	cnt_1_Z[6]/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	clk_ibuf/I
10.675	0.675	tINS	RR	clk_ibuf/O
11.577	0.902	tNET	RR	cnt_1_Z[6]/CLK

MPW4

MPW Summary:

Slack:	3.662
Actual Width:	4.662
Required Width:	1.000
Type:	Low Pulse Width
Clock:	DEFAULT_CLK
Objects:	cnt_Z[11]

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	clk_ibuf/I
5.688	0.688	tINS	FF	clk_ibuf/O
6.916	1.228	tNET	FF	cnt_Z[11]/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	clk_ibuf/I
10.675	0.675	tINS	RR	clk_ibuf/O
11.577	0.902	tNET	RR	cnt_Z[11]/CLK

MPW5

MPW Summary:

Slack:	3.662
Actual Width:	4.662
Required Width:	1.000
Type:	Low Pulse Width
Clock:	DEFAULT_CLK
Objects:	divisor[29]

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	clk_ibuf/I
5.688	0.688	tINS	FF	clk_ibuf/O
6.916	1.228	tNET	FF	divisor[29]/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	clk_ibuf/I
10.675	0.675	tINS	RR	clk_ibuf/O
11.577	0.902	tNET	RR	divisor[29]/CLK

MPW6

MPW Summary:

Slack:	3.662
Actual Width:	4.662
Required Width:	1.000
Type:	Low Pulse Width
Clock:	DEFAULT_CLK
Objects:	m_Z[30]

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	clk_ibuf/I
5.688	0.688	tINS	FF	clk_ibuf/O
6.916	1.228	tNET	FF	m_Z[30]/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	clk_ibuf/I
10.675	0.675	tINS	RR	clk_ibuf/O
11.577	0.902	tNET	RR	m_Z[30]/CLK

MPW7

MPW Summary:

Slack:	3.662
Actual Width:	4.662
Required Width:	1.000
Type:	Low Pulse Width
Clock:	DEFAULT_CLK
Objects:	memq_memq_0_15

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	clk_ibuf/I
5.688	0.688	tINS	FF	clk_ibuf/O
6.916	1.228	tNET	FF	memq_memq_0_15/CLKA

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	clk_ibuf/I
10.675	0.675	tINS	RR	clk_ibuf/O
11.577	0.902	tNET	RR	memq_memq_0_15/CLKA

MPW8

MPW Summary:

Slack:	3.662
Actual Width:	4.662
Required Width:	1.000
Type:	Low Pulse Width
Clock:	DEFAULT_CLK
Objects:	Mdu/u_mdu/reg0_fast_Z[15]

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	clk_ibuf/I
5.688	0.688	tINS	FF	clk_ibuf/O
6.916	1.228	tNET	FF	Mdu/u_mdu/reg0_fast_Z[15]/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	clk_ibuf/I
10.675	0.675	tINS	RR	clk_ibuf/O
11.577	0.902	tNET	RR	Mdu/u_mdu/reg0_fast_Z[15]/CLK

MPW9

MPW Summary:

Slack:	3.662
Actual Width:	4.662
Required Width:	1.000
Type:	Low Pulse Width
Clock:	DEFAULT_CLK
Objects:	u_la0_top/u_ao_mem_ctrl/capture_loop_Z

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	clk_ibuf/I
5.688	0.688	tINS	FF	clk_ibuf/O
6.916	1.228	tNET	FF	u_la0_top/u_ao_mem_ctrl/capture_loop_Z/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	clk_ibuf/I
10.675	0.675	tINS	RR	clk_ibuf/O
11.577	0.902	tNET	RR	u_la0_top/u_ao_mem_ctrl/capture_loop_Z/CLK

MPW10

MPW Summary:

Slack:	3.662
Actual Width:	4.662
Required Width:	1.000
Type:	Low Pulse Width
Clock:	DEFAULT_CLK
Objects:	u_la0_top/u_ao_mem_ctrl/data_reg_Z[116]

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			DEFAULT_CLK(clock)
5.000	0.000	tCL	FF	clk_ibuf/I
5.688	0.688	tINS	FF	clk_ibuf/O
6.916	1.228	tNET	FF	u_la0_top/u_ao_mem_ctrl/data_reg_Z[116]/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			DEFAULT_CLK(clock)
10.000	0.000	tCL	RR	clk_ibuf/I
10.675	0.675	tINS	RR	clk_ibuf/O
11.577	0.902	tNET	RR	u_la0_top/u_ao_mem_ctrl/data_reg_Z[116]/CLK

High Fanout Nets Report:

Report Command:report_high_fanout_nets -max_nets 10

FANOUT	NET NAME	WORST SLACK	MAX DELAY
336	clk_c	0.056	1.228
114	div_shift_number[1]	0.530	1.722
113	div_shift_number[0]	0.578	1.610
100	reg0_en	5.135	1.941
96	neg_result	2.496	2.323
92	state[1]	5.727	2.568
81	hi_result	3.736	2.333
74	reg0_exe_nx_sm0	2.136	1.348
71	state[3]	4.986	3.070
70	m0_2_03_1	2.084	1.685

Route Congestions Report:

Report Command:report_route_congestion -max_grids 10

GRID LOC	ROUTE CONGESTIONS
R39C49	0.833
R38C58	0.819
R38C59	0.806
R39C50	0.792
R39C55	0.792
R29C55	0.792
R39C47	0.764
R39C53	0.764
R38C48	0.764
R56C35	0.764

Timing Exceptions Report:

Setup Analysis Report

Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Hold Analysis Report

Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Recovery Analysis Report

Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Removal Analysis Report

Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Timing Constraints Report:

SDC Command Type	State	Detail Command