Timing Messages

Report Title	Timing Analysis Report
Design File	E:\Gowin_haogang\project\Gowin_USB3_2_Ref\Gowin_USB3_2_UVC_BULK_Ref\release\Gowin_USB3_2_GEN2_UVC_BULK_Ref_DK_USB_GW5AT_LV60UG225_V1.0\prj\impl\gwsynthesis\prj.vg
Physical Constraints File	E:\Gowin_haogang\project\Gowin_USB3_2_Ref\Gowin_USB3_2_UVC_BULK_Ref\release\Gowin_USB3_2_GEN2_UVC_BULK_Ref_DK_USB_GW5AT_LV60UG225_V1.0\prj\src\top.cst
Timing Constraint File	E:\Gowin_haogang\project\Gowin_USB3_2_Ref\Gowin_USB3_2_UVC_BULK_Ref\release\Gowin_USB3_2_GEN2_UVC_BULK_Ref_DK_USB_GW5AT_LV60UG225_V1.0\prj\src\top.sdc
Tool Version	V1.9.12.03 (64-bit)
Part Number	GW5AT-LV60UG225C2/I1
Device	GW5AT-60
Device Version	B
Created Time	Fri Jul 24 16:28:35 2026
Legal Announcement	Copyright (C)2014-2026 Gowin Semiconductor Corporation. All rights reserved.

Timing Summaries

STA Tool Run Summary:

Setup Delay Model	Slow 0.93V 0C C2/I1
Hold Delay Model	Fast 0.975V 85C C2/I1
Numbers of Paths Analyzed	44125
Numbers of Endpoints Analyzed	62279
Numbers of Falling Endpoints	12
Numbers of Setup Violated Endpoints	0
Numbers of Hold Violated Endpoints	0

Clock Summary:

NO.	Clock Name	Type	Period	Frequency(MHz)	Rise	Fall	Source	Master	Objects
1	pclk	Base	6.250	160.000	0.000	3.200			pclk
2	q0_lane1_fabric_rx_clk	Base	6.250	160.000	0.000	3.200			SerDes_Top_inst/q0_lane1_fabric_rx_clk
3	drp_clk	Base	10.000	100.000	0.000	5.000			SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst_drp_clk_o[1]
4	clk_24m	Base	41.667	24.000	0.000	20.834			clk_24m
5	sys_clk	Base	5.000	200.000	0.000	2.500			sys_clk
6	rgb_clk	Base	6.250	160.000	0.000	3.125			rgb_clk
7	dma_clk	Base	7.273	137.495	0.000	3.636			dma_clk
8	memory_clk	Base	1.818	550.055	0.000	0.909			memory_clk
9	sys_clk_p	Base	5.000	200.000	0.000	2.500			Inst_sys_clk_in/I
10	cnt4_clr	Base	10.000	100.000	0.000	5.000			cnt4_clr_s0/Q
11	Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk	Generated	6.723	148.750	0.000	3.361	Inst_sys_clk_in/O	sys_clk	Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1

Max Frequency Summary:

NO.	Clock Name	Constraint	Actual Fmax	Logic Level	Entity
1	pclk	160.000(MHz)	161.710(MHz)	6	TOP
2	q0_lane1_fabric_rx_clk	160.000(MHz)	175.544(MHz)	9	TOP
3	drp_clk	100.000(MHz)	165.294(MHz)	9	TOP
4	clk_24m	24.000(MHz)	229.402(MHz)	2	TOP
5	sys_clk	200.000(MHz)	464.414(MHz)	3	TOP
6	rgb_clk	160.000(MHz)	210.940(MHz)	7	TOP
7	dma_clk	137.495(MHz)	181.687(MHz)	10	TOP
8	cnt4_clr	100.000(MHz)	1522.070(MHz)	2	TOP
9	Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk	148.750(MHz)	201.598(MHz)	2	TOP

No timing paths to get frequency of memory_clk!

No timing paths to get frequency of sys_clk_p!

Total Negative Slack Summary:

Clock Name	Analysis Type	Endpoints TNS	Number of Endpoints
pclk	Setup	0.000	0
pclk	Hold	0.000	0
q0_lane1_fabric_rx_clk	Setup	0.000	0
q0_lane1_fabric_rx_clk	Hold	0.000	0
drp_clk	Setup	0.000	0
drp_clk	Hold	0.000	0
clk_24m	Setup	0.000	0
clk_24m	Hold	0.000	0
sys_clk	Setup	0.000	0
sys_clk	Hold	0.000	0
rgb_clk	Setup	0.000	0
rgb_clk	Hold	0.000	0
dma_clk	Setup	0.000	0
dma_clk	Hold	0.000	0
memory_clk	Setup	0.000	0
memory_clk	Hold	0.000	0
sys_clk_p	Setup	0.000	0
sys_clk_p	Hold	0.000	0
cnt4_clr	Setup	0.000	0
cnt4_clr	Hold	0.000	0
Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk	Setup	0.000	0
Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk	Hold	0.000	0

Timing Details

Path Slacks Table:

Setup Paths Table

Report Command:report_timing -setup -max_paths 100 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	0.066	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/Q	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_14_s2/D	pclk:[R]	pclk:[R]	6.250	0.007	6.131
2	0.066	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/Q	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_14_s1/D	pclk:[R]	pclk:[R]	6.250	0.007	6.131
3	0.066	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/Q	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_12_s2/D	pclk:[R]	pclk:[R]	6.250	0.014	6.007
4	0.069	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/Q	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_46_s1/D	pclk:[R]	pclk:[R]	6.250	0.014	6.121
5	0.073	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/Q	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_12_s1/D	pclk:[R]	pclk:[R]	6.250	0.007	6.007
6	0.078	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/Q	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_46_s2/D	pclk:[R]	pclk:[R]	6.250	0.007	6.120
7	0.086	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_header_pkt_68_s0/Q	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_hp_9_s0/D	pclk:[R]	pclk:[R]	6.250	0.014	5.987
8	0.095	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/Q	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_54_s2/D	pclk:[R]	pclk:[R]	6.250	0.014	6.096
9	0.095	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/Q	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_54_s1/D	pclk:[R]	pclk:[R]	6.250	0.014	6.096
10	0.107	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_header_pkt_68_s0/Q	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_hp_9_s1/D	pclk:[R]	pclk:[R]	6.250	0.007	5.972
11	0.190	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/Q	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_27_s1/D	pclk:[R]	pclk:[R]	6.250	0.007	5.890
12	0.201	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/Q	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_44_s2/D	pclk:[R]	pclk:[R]	6.250	0.000	6.003
13	0.201	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/Q	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_44_s1/D	pclk:[R]	pclk:[R]	6.250	0.000	6.003
14	0.211	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/Q	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_41_s2/D	pclk:[R]	pclk:[R]	6.250	0.007	5.987
15	0.211	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/Q	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_41_s1/D	pclk:[R]	pclk:[R]	6.250	0.007	5.987
16	0.236	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/Q	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_27_s2/D	pclk:[R]	pclk:[R]	6.250	0.000	5.850
17	0.261	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/state_4_s1/Q	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/state_0_s0/D	pclk:[R]	pclk:[R]	6.250	-0.007	5.950
18	0.279	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/Q	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_59_s2/D	pclk:[R]	pclk:[R]	6.250	0.007	5.918
19	0.279	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/Q	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_59_s1/D	pclk:[R]	pclk:[R]	6.250	0.007	5.918
20	0.320	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/Q	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_22_s2/D	pclk:[R]	pclk:[R]	6.250	0.007	5.759
21	0.320	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/Q	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_22_s1/D	pclk:[R]	pclk:[R]	6.250	0.007	5.759
22	0.327	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/Q	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_1_s2/D	pclk:[R]	pclk:[R]	6.250	0.014	5.864
23	0.332	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/Q	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_1_s1/D	pclk:[R]	pclk:[R]	6.250	0.007	5.865
24	0.349	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/Q	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_25_s2/D	pclk:[R]	pclk:[R]	6.250	0.007	5.848
25	0.349	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/Q	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_25_s1/D	pclk:[R]	pclk:[R]	6.250	0.007	5.848
26	0.360	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/Q	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_62_s2/D	pclk:[R]	pclk:[R]	6.250	0.014	5.712
27	0.379	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/reset_n_d_s0/Q	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_6_s1/D	pclk:[R]	pclk:[R]	6.250	-0.014	5.720
28	0.397	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/Q	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_38_s2/D	pclk:[R]	pclk:[R]	6.250	0.014	5.793
29	0.397	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/Q	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_38_s1/D	pclk:[R]	pclk:[R]	6.250	0.014	5.793
30	0.401	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_header_pkt_48_s0/Q	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_hp_4_s1/D	pclk:[R]	pclk:[R]	6.250	0.000	5.803
31	0.401	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_header_pkt_48_s0/Q	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_hp_4_s0/D	pclk:[R]	pclk:[R]	6.250	0.000	5.803
32	0.407	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/Q	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_30_s2/D	pclk:[R]	pclk:[R]	6.250	0.007	5.627
33	0.407	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/Q	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_30_s1/D	pclk:[R]	pclk:[R]	6.250	0.007	5.627
34	0.426	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/Q	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_3_s2/D	pclk:[R]	pclk:[R]	6.250	0.000	5.660
35	0.426	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/Q	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_3_s1/D	pclk:[R]	pclk:[R]	6.250	0.000	5.660
36	0.427	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/Q	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_9_s2/D	pclk:[R]	pclk:[R]	6.250	0.007	5.771
37	0.433	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/Q	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_62_s1/D	pclk:[R]	pclk:[R]	6.250	0.007	5.765
38	0.441	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/Q	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_9_s1/D	pclk:[R]	pclk:[R]	6.250	0.007	5.756
39	0.453	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/Q	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_35_s2/D	pclk:[R]	pclk:[R]	6.250	0.000	5.587
40	0.460	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_dpp_length_2_s4/Q	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_dpp_17_s1/D	pclk:[R]	pclk:[R]	6.250	0.000	5.744
41	0.460	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_dpp_length_2_s4/Q	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_dpp_17_s0/D	pclk:[R]	pclk:[R]	6.250	0.000	5.744
42	0.484	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/reset_n_d_s0/Q	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_6_s2/D	pclk:[R]	pclk:[R]	6.250	-0.007	5.609
43	0.519	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/state_4_s1/Q	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/ts_loopback_latch_0_s2/CE	pclk:[R]	pclk:[R]	6.250	-0.363	5.870
44	0.519	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/state_4_s1/Q	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/ts_loopback_latch_1_s2/CE	pclk:[R]	pclk:[R]	6.250	-0.363	5.870
45	0.519	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/state_4_s1/Q	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/ts_loopback_latch_2_s2/CE	pclk:[R]	pclk:[R]	6.250	-0.363	5.870
46	0.519	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/state_4_s1/Q	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/ts_loopback_latch_3_s2/CE	pclk:[R]	pclk:[R]	6.250	-0.363	5.870
47	0.527	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/Q	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_49_s2/D	pclk:[R]	pclk:[R]	6.250	0.000	5.677
48	0.527	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/Q	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_49_s1/D	pclk:[R]	pclk:[R]	6.250	0.000	5.677
49	0.537	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/Q	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_43_s1/D	pclk:[R]	pclk:[R]	6.250	0.014	5.654
50	0.553	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_p132brxgears/skp_head_num_0_s0/Q	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_p132brxgears/head_num_latch_add8_0_s0/D	q0_lane1_fabric_rx_clk:[R]	q0_lane1_fabric_rx_clk:[R]	6.250	0.000	5.651
51	0.569	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/Q	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_43_s2/D	pclk:[R]	pclk:[R]	6.250	0.007	5.629
52	0.571	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/Q	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_17_s2/D	pclk:[R]	pclk:[R]	6.250	0.014	5.456
53	0.571	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/Q	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_20_s2/D	pclk:[R]	pclk:[R]	6.250	0.007	5.463
54	0.571	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/Q	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_20_s1/D	pclk:[R]	pclk:[R]	6.250	0.007	5.463
55	0.574	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_dpp_length_2_s4/Q	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_dpp_9_s1/D	pclk:[R]	pclk:[R]	6.250	0.000	5.513
56	0.584	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/Q	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_11_s2/D	pclk:[R]	pclk:[R]	6.250	0.000	5.621
57	0.585	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/Q	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_11_s1/D	pclk:[R]	pclk:[R]	6.250	0.000	5.619
58	0.587	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/Q	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_36_s1/D	pclk:[R]	pclk:[R]	6.250	0.007	5.493
59	0.597	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/Q	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_35_s1/D	pclk:[R]	pclk:[R]	6.250	0.007	5.437
60	0.598	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/Q	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_4_s1/D	pclk:[R]	pclk:[R]	6.250	0.007	5.599
61	0.600	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_dpp_length_2_s4/Q	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_dpp_9_s0/D	pclk:[R]	pclk:[R]	6.250	0.000	5.604
62	0.602	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/Q	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_19_s2/D	pclk:[R]	pclk:[R]	6.250	0.007	5.477
63	0.605	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/Q	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_57_s1/D	pclk:[R]	pclk:[R]	6.250	0.007	5.593
64	0.609	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/Q	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_19_s1/D	pclk:[R]	pclk:[R]	6.250	0.000	5.477
65	0.612	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/Q	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_57_s2/D	pclk:[R]	pclk:[R]	6.250	0.014	5.578
66	0.617	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_p132brxgears/skp_head_num_0_s0/Q	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_p132brxgears/head_num_latch_add8_2_s0/D	q0_lane1_fabric_rx_clk:[R]	q0_lane1_fabric_rx_clk:[R]	6.250	0.000	5.587
67	0.625	UserLayer_top_inst/ControlTransfer_inst/bmRequestType_latch_1_s0/Q	UserLayer_top_inst/ControlTransfer_inst/transfer_in_data_mux_36_s0/D	pclk:[R]	pclk:[R]	6.250	0.007	5.572
68	0.635	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_header_pkt_78_s0/Q	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_hp_3_s0/D	pclk:[R]	pclk:[R]	6.250	0.007	5.444
69	0.661	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/Q	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_33_s2/D	pclk:[R]	pclk:[R]	6.250	0.000	5.543
70	0.661	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/Q	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_33_s1/D	pclk:[R]	pclk:[R]	6.250	0.000	5.543
71	0.667	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/tx_data_encode_5g_20_s0/Q	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_encode_8b10b_4ch/enc3/dout_6_s0/D	pclk:[R]	pclk:[R]	6.250	0.007	5.531
72	0.677	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_p132brxgears/skp_head_num_0_s0/Q	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_p132brxgears/head_num_latch_0_s0/D	q0_lane1_fabric_rx_clk:[R]	q0_lane1_fabric_rx_clk:[R]	6.250	0.000	5.527
73	0.688	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/Q	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_17_s1/D	pclk:[R]	pclk:[R]	6.250	0.007	5.346
74	0.688	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_p132brxgears/skp_head_num_0_s0/Q	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_p132brxgears/head_num_latch_add8_1_s0/D	q0_lane1_fabric_rx_clk:[R]	q0_lane1_fabric_rx_clk:[R]	6.250	0.007	5.509
75	0.694	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_dpp_length_2_s4/Q	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_dpp_22_s1/D	pclk:[R]	pclk:[R]	6.250	0.000	5.510
76	0.694	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_dpp_length_2_s4/Q	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_dpp_22_s0/D	pclk:[R]	pclk:[R]	6.250	0.000	5.510
77	0.715	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/state_4_s1/Q	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/train_sym_skp_5_s2/D	pclk:[R]	pclk:[R]	6.250	-0.007	5.495
78	0.717	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/Q	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_36_s2/D	pclk:[R]	pclk:[R]	6.250	0.014	5.356
79	0.723	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_p132brxgears/skp_head_num_0_s0/Q	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_p132brxgears/head_num_latch_3_s0/D	q0_lane1_fabric_rx_clk:[R]	q0_lane1_fabric_rx_clk:[R]	6.250	0.000	5.481
80	0.742	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/Q	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_4_s2/D	pclk:[R]	pclk:[R]	6.250	0.000	5.462
81	0.747	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/Q	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_52_s2/D	pclk:[R]	pclk:[R]	6.250	0.014	5.444
82	0.747	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/Q	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_52_s1/D	pclk:[R]	pclk:[R]	6.250	0.014	5.444
83	0.747	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/GEN1_DPP_buff/mem_mem_0_0_s/DO[30]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_dpp_30_s1/D	pclk:[R]	pclk:[R]	6.250	0.007	5.332
84	0.747	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/GEN1_DPP_buff/mem_mem_0_0_s/DO[30]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_dpp_30_s0/D	pclk:[R]	pclk:[R]	6.250	0.007	5.332
85	0.749	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/Q	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_28_s2/D	pclk:[R]	pclk:[R]	6.250	0.000	5.455
86	0.751	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/Q	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_28_s1/D	pclk:[R]	pclk:[R]	6.250	0.000	5.454
87	0.754	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/dpp_buff_inst/shifter_byte_sel[1]_5_s0/Q	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/dpp_buff_inst/shifter[1]_0_s0/D	pclk:[R]	pclk:[R]	6.250	0.000	5.450
88	0.758	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_header_pkt_78_s0/Q	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_hp_3_s1/D	pclk:[R]	pclk:[R]	6.250	0.007	5.322
89	0.767	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/training_s2/Q	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/train_sym_sync_7_s2/CE	pclk:[R]	pclk:[R]	6.250	-0.007	5.266
90	0.767	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/training_s2/Q	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/train_sym_sync_8_s2/CE	pclk:[R]	pclk:[R]	6.250	-0.007	5.266
91	0.774	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/training_s2/Q	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/train_sym_sync_5_s2/CE	pclk:[R]	pclk:[R]	6.250	0.000	5.252
92	0.774	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/training_s2/Q	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/train_sym_sync_6_s2/CE	pclk:[R]	pclk:[R]	6.250	0.000	5.252
93	0.796	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/state_4_s1/Q	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/train_sym_skp_4_s2/D	pclk:[R]	pclk:[R]	6.250	-0.007	5.415
94	0.800	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/dpp_buff_inst/shifter_byte_sel[15]_0_s0/Q	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/dpp_buff_inst/shifter[15]_0_s0/D	pclk:[R]	pclk:[R]	6.250	0.000	5.405
95	0.813	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/state_4_s1/Q	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_5g/state_0_s0/D	pclk:[R]	pclk:[R]	6.250	-0.370	5.761
96	0.825	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/training_s2/Q	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/train_sym_sync_13_s2/CE	pclk:[R]	pclk:[R]	6.250	-0.007	5.207
97	0.831	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/state_4_s1/Q	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/train_sym_skp_7_s2/D	pclk:[R]	pclk:[R]	6.250	0.000	5.373
98	0.833	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_dpp_length_2_s4/Q	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_dpp_11_s1/D	pclk:[R]	pclk:[R]	6.250	-0.007	5.378
99	0.833	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_dpp_length_2_s4/Q	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_dpp_11_s0/D	pclk:[R]	pclk:[R]	6.250	-0.007	5.378
100	0.835	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_dpp_length_2_s4/Q	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_dpp_4_s1/D	pclk:[R]	pclk:[R]	6.250	-0.007	5.376

Hold Paths Table

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	0.038	DDR3_Memory_Interface_Top_inst/gw3_top/u_gwmc_top/gw_wr_data0/wr_buf_din_66_s0/Q	DDR3_Memory_Interface_Top_inst/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_1_s/DI[30]	dma_clk:[R]	dma_clk:[R]	0.000	-0.184	0.254
2	0.038	DDR3_Memory_Interface_Top_inst/gw3_top/u_gwmc_top/gw_wr_data0/wr_buf_din_65_s0/Q	DDR3_Memory_Interface_Top_inst/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_1_s/DI[29]	dma_clk:[R]	dma_clk:[R]	0.000	-0.184	0.254
3	0.043	u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_data_19_s0/Q	u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.mem_Big.mem_0_2_s/DI[3]	rgb_clk:[R]	rgb_clk:[R]	0.000	-0.177	0.254
4	0.043	u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_data_35_s0/Q	u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.mem_Big.mem_0_4_s/DI[3]	rgb_clk:[R]	rgb_clk:[R]	0.000	-0.177	0.254
5	0.043	DDR3_Memory_Interface_Top_inst/gw3_top/u_gwmc_top/gw_wr_data0/wr_buf_din_75_s0/Q	DDR3_Memory_Interface_Top_inst/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_2_s/DI[3]	dma_clk:[R]	dma_clk:[R]	0.000	-0.177	0.254
6	0.043	DDR3_Memory_Interface_Top_inst/gw3_top/u_gwmc_top/gw_wr_data0/wr_buf_din_42_s0/Q	DDR3_Memory_Interface_Top_inst/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_1_s/DI[6]	dma_clk:[R]	dma_clk:[R]	0.000	-0.177	0.254
7	0.047	DDR3_Memory_Interface_Top_inst/gw3_top/u_gwmc_top/gw_wr_data0/wr_buf_din_89_s0/Q	DDR3_Memory_Interface_Top_inst/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_2_s/DI[17]	dma_clk:[R]	dma_clk:[R]	0.000	-0.174	0.254
8	0.049	DDR3_Memory_Interface_Top_inst/gw3_top/u_gwmc_top/gw_wr_data0/wr_buf_din_92_s0/Q	DDR3_Memory_Interface_Top_inst/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_2_s/DI[20]	dma_clk:[R]	dma_clk:[R]	0.000	-0.174	0.254
9	0.049	DDR3_Memory_Interface_Top_inst/gw3_top/u_gwmc_top/gw_wr_data0/wr_buf_din_91_s0/Q	DDR3_Memory_Interface_Top_inst/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_2_s/DI[19]	dma_clk:[R]	dma_clk:[R]	0.000	-0.174	0.254
10	0.082	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/rx_dph_len_d[5]_8_s0/Q	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/rx_dph_len_d[6]_0_s9/DI[0]	pclk:[R]	pclk:[R]	0.000	0.000	0.127
11	0.090	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_26_s1/Q	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/sync_fifo_inst/mem_mem_0_0_s/DI[26]	pclk:[R]	pclk:[R]	0.000	-0.177	0.299
12	0.105	DDR3_Memory_Interface_Top_inst/gw3_top/u_gwmc_top/gw_wr_data0/wr_buf_din_67_s0/Q	DDR3_Memory_Interface_Top_inst/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_1_s/DI[31]	dma_clk:[R]	dma_clk:[R]	0.000	-0.184	0.321
13	0.107	DDR3_Memory_Interface_Top_inst/gw3_top/u_gwmc_top/gw_wr_data0/wr_buf_din_48_s0/Q	DDR3_Memory_Interface_Top_inst/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_1_s/DI[12]	dma_clk:[R]	dma_clk:[R]	0.000	-0.181	0.321
14	0.109	DDR3_Memory_Interface_Top_inst/gw3_top/u_gwmc_top/gw_wr_data0/wr_buf_din_54_s0/Q	DDR3_Memory_Interface_Top_inst/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_1_s/DI[18]	dma_clk:[R]	dma_clk:[R]	0.000	-0.181	0.321
15	0.116	DDR3_Memory_Interface_Top_inst/gw3_top/u_gwmc_top/gw_wr_data0/wr_buf_din_95_s0/Q	DDR3_Memory_Interface_Top_inst/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_2_s/DI[23]	dma_clk:[R]	dma_clk:[R]	0.000	-0.174	0.321
16	0.119	DDR3_Memory_Interface_Top_inst/gw3_top/u_gwmc_top/gw_wr_data0/wr_buf_din_64_s0/Q	DDR3_Memory_Interface_Top_inst/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_1_s/DI[28]	dma_clk:[R]	dma_clk:[R]	0.000	-0.184	0.335
17	0.120	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/VALUE_rrr_10_s0/Q	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/dq_iobuf_gen[10].dq_iodelay/VALUE	dma_clk:[R]	dma_clk:[R]	0.000	-0.007	0.127
18	0.122	DDR3_Memory_Interface_Top_inst/gw3_top/u_gwmc_top/gw_wr_data0/wr_buf_din_69_s0/Q	DDR3_Memory_Interface_Top_inst/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_1_s/DI[33]	dma_clk:[R]	dma_clk:[R]	0.000	-0.181	0.335
19	0.122	DDR3_Memory_Interface_Top_inst/gw3_top/u_gwmc_top/gw_wr_data0/wr_buf_din_29_s0/Q	DDR3_Memory_Interface_Top_inst/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_0_s/DI[29]	dma_clk:[R]	dma_clk:[R]	0.000	-0.181	0.335
20	0.123	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/VALUE_rrr_12_s0/Q	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/dq_iobuf_gen[12].dq_iodelay/VALUE	dma_clk:[R]	dma_clk:[R]	0.000	-0.004	0.127
21	0.123	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/VALUE_rrr_11_s0/Q	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/dq_iobuf_gen[11].dq_iodelay/VALUE	dma_clk:[R]	dma_clk:[R]	0.000	-0.004	0.127
22	0.123	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/VALUE_rrr_9_s0/Q	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/dq_iobuf_gen[9].dq_iodelay/VALUE	dma_clk:[R]	dma_clk:[R]	0.000	-0.004	0.127
23	0.123	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/VALUE_rrr_0_s0/Q	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/dq_iobuf_gen[0].dq_iodelay/VALUE	dma_clk:[R]	dma_clk:[R]	0.000	-0.004	0.127
24	0.123	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/DQS_VALUE_rrr_0_s0/Q	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/dqs_iobuf_gen[0].dqs_iodelay/VALUE	dma_clk:[R]	dma_clk:[R]	0.000	-0.004	0.127
25	0.124	DDR3_Memory_Interface_Top_inst/gw3_top/u_gwmc_top/gw_wr_data0/wr_buf_din_44_s0/Q	DDR3_Memory_Interface_Top_inst/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_1_s/DI[8]	dma_clk:[R]	dma_clk:[R]	0.000	-0.177	0.335

Recovery Paths Table

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	0.306	u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0/Q	u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.mem_Small.mem_0_1_s/RESET	Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk:[F]	Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk:[R]	3.361	0.004	2.993
2	0.578	u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0/Q	u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.mem_Small.mem_0_3_s/RESET	Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk:[F]	Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk:[R]	3.361	-0.003	2.729
3	0.741	u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0/Q	u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.mem_Small.mem_0_5_s/RESET	Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk:[F]	Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk:[R]	3.361	-0.009	2.572
4	1.677	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/internel_resetn_s0/Q	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/tx_data_en_encode_o_r1_s0/CLEAR	pclk:[R]	pclk:[R]	6.250	0.000	4.323
5	0.879	line_fifo_inst/fifo_inst/reset_r_1_s0/Q	line_fifo_inst/fifo_inst/Equal.rq2_wptr_2_s0/CLEAR	pclk:[F]	pclk:[R]	3.050	-0.001	1.922
6	0.879	line_fifo_inst/fifo_inst/reset_r_1_s0/Q	line_fifo_inst/fifo_inst/Equal.rq1_wptr_2_s0/CLEAR	pclk:[F]	pclk:[R]	3.050	-0.001	1.922
7	0.918	line_fifo_inst/fifo_inst/reset_r_1_s0/Q	line_fifo_inst/fifo_inst/Equal.rptr_0_s0/CLEAR	pclk:[F]	pclk:[R]	3.050	-0.014	1.896
8	0.918	line_fifo_inst/fifo_inst/reset_r_1_s0/Q	line_fifo_inst/fifo_inst/Equal.rptr_2_s0/CLEAR	pclk:[F]	pclk:[R]	3.050	-0.014	1.896
9	0.918	line_fifo_inst/fifo_inst/reset_r_1_s0/Q	line_fifo_inst/fifo_inst/Equal.rptr_8_s0/CLEAR	pclk:[F]	pclk:[R]	3.050	-0.014	1.896
10	0.918	line_fifo_inst/fifo_inst/reset_r_1_s0/Q	line_fifo_inst/fifo_inst/Equal.rq2_wptr_4_s0/CLEAR	pclk:[F]	pclk:[R]	3.050	-0.014	1.896
11	0.918	line_fifo_inst/fifo_inst/reset_r_1_s0/Q	line_fifo_inst/fifo_inst/Equal.rq2_wptr_6_s0/CLEAR	pclk:[F]	pclk:[R]	3.050	-0.014	1.896
12	0.918	line_fifo_inst/fifo_inst/reset_r_1_s0/Q	line_fifo_inst/fifo_inst/Equal.rq2_wptr_10_s0/CLEAR	pclk:[F]	pclk:[R]	3.050	-0.014	1.896
13	0.918	line_fifo_inst/fifo_inst/reset_r_1_s0/Q	line_fifo_inst/fifo_inst/Equal.rq1_wptr_4_s0/CLEAR	pclk:[F]	pclk:[R]	3.050	-0.014	1.896
14	0.918	line_fifo_inst/fifo_inst/reset_r_1_s0/Q	line_fifo_inst/fifo_inst/Equal.rq1_wptr_11_s0/CLEAR	pclk:[F]	pclk:[R]	3.050	-0.014	1.896
15	1.005	u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0/Q	u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.mem_Small.mem_0_0_s/RESET	Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk:[F]	Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk:[R]	3.361	0.004	2.295
16	1.005	u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0/Q	u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.mem_Small.mem_0_7_s/RESET	Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk:[F]	Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk:[R]	3.361	-0.003	2.301
17	2.051	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/Q	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_lcmd_57_s1/PRESET	pclk:[R]	pclk:[R]	6.250	0.007	3.942
18	2.065	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/internel_resetn_s0/Q	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/tx_data_en_encode_o_r1_s1/PRESET	pclk:[R]	pclk:[R]	6.250	0.000	3.935
19	1.043	line_fifo_inst/fifo_inst/reset_r_1_s0/Q	line_fifo_inst/fifo_inst/Equal.rptr_3_s0/CLEAR	pclk:[F]	pclk:[R]	3.050	-0.001	1.758
20	1.043	line_fifo_inst/fifo_inst/reset_r_1_s0/Q	line_fifo_inst/fifo_inst/Equal.rptr_4_s0/CLEAR	pclk:[F]	pclk:[R]	3.050	-0.001	1.758
21	1.047	line_fifo_inst/fifo_inst/reset_r_1_s0/Q	line_fifo_inst/fifo_inst/Equal.rq2_wptr_3_s0/CLEAR	pclk:[F]	pclk:[R]	3.050	-0.001	1.754
22	1.050	line_fifo_inst/fifo_inst/reset_r_1_s0/Q	line_fifo_inst/fifo_inst/Rnum_6_s0/CLEAR	pclk:[F]	pclk:[R]	3.050	-0.008	1.758
23	1.050	line_fifo_inst/fifo_inst/reset_r_1_s0/Q	line_fifo_inst/fifo_inst/Rnum_7_s0/CLEAR	pclk:[F]	pclk:[R]	3.050	-0.008	1.758
24	1.050	line_fifo_inst/fifo_inst/reset_r_1_s0/Q	line_fifo_inst/fifo_inst/Rnum_8_s0/CLEAR	pclk:[F]	pclk:[R]	3.050	-0.008	1.758
25	1.050	line_fifo_inst/fifo_inst/reset_r_1_s0/Q	line_fifo_inst/fifo_inst/Rnum_9_s0/CLEAR	pclk:[F]	pclk:[R]	3.050	-0.008	1.758

Removal Paths Table

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	0.256	frame_read_inst/rst_n_d_1_s0/Q	frame_read_inst/h_cnt_3_s1/CLEAR	Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk:[R]	Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk:[R]	0.000	0.000	0.208
2	0.256	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/prot_rst_n_s0/Q	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/ltssm_go_u_d0_0_s0/CLEAR	pclk:[R]	pclk:[R]	0.000	0.000	0.208
3	0.314	SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/rstn_s0/Q	SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wrdata_o_0_s1/CLEAR	drp_clk:[R]	drp_clk:[R]	0.000	0.000	0.266
4	0.314	SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/rstn_s0/Q	SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wrdata_o_1_s1/CLEAR	drp_clk:[R]	drp_clk:[R]	0.000	0.000	0.266
5	0.314	SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/rstn_s0/Q	SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wrdata_o_2_s1/CLEAR	drp_clk:[R]	drp_clk:[R]	0.000	0.000	0.266
6	0.314	SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/rstn_s0/Q	SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wrdata_o_3_s1/CLEAR	drp_clk:[R]	drp_clk:[R]	0.000	0.000	0.266
7	0.314	SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/rstn_s0/Q	SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wrdata_o_6_s1/CLEAR	drp_clk:[R]	drp_clk:[R]	0.000	0.000	0.266
8	0.314	SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/rstn_s0/Q	SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wrdata_o_7_s1/CLEAR	drp_clk:[R]	drp_clk:[R]	0.000	0.000	0.266
9	0.314	SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/rstn_s0/Q	SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_addr_o_3_s1/CLEAR	drp_clk:[R]	drp_clk:[R]	0.000	0.000	0.266
10	0.314	SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/rstn_s0/Q	SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_addr_o_4_s1/CLEAR	drp_clk:[R]	drp_clk:[R]	0.000	0.000	0.266
11	0.347	testpattern_yuv_inst/rst_n_local_s0/Q	testpattern_yuv_inst/yuv_data_57_s0/CLEAR	rgb_clk:[R]	rgb_clk:[R]	0.000	-0.004	0.302
12	0.347	frame_read_inst/rst_n_d_1_s0/Q	frame_read_inst/h_cnt_0_s1/CLEAR	Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk:[R]	Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk:[R]	0.000	0.000	0.300
13	0.347	frame_read_inst/rst_n_d_1_s0/Q	frame_read_inst/h_cnt_1_s1/CLEAR	Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk:[R]	Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk:[R]	0.000	0.000	0.300
14	0.347	frame_read_inst/rst_n_d_1_s0/Q	frame_read_inst/h_cnt_2_s1/CLEAR	Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk:[R]	Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk:[R]	0.000	0.000	0.300
15	0.347	frame_read_inst/rst_n_d_1_s0/Q	frame_read_inst/h_cnt_4_s1/CLEAR	Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk:[R]	Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk:[R]	0.000	0.000	0.300
16	0.347	frame_read_inst/rst_n_d_1_s0/Q	frame_read_inst/h_cnt_5_s1/CLEAR	Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk:[R]	Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk:[R]	0.000	0.000	0.300
17	0.347	frame_read_inst/rst_n_d_1_s0/Q	frame_read_inst/h_cnt_6_s1/CLEAR	Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk:[R]	Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk:[R]	0.000	0.000	0.300
18	0.353	SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/rstn_s0/Q	SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/drp_addr_serdes_4_s0/CLEAR	drp_clk:[R]	drp_clk:[R]	0.000	0.000	0.305
19	0.355	frame_read_inst/rst_n_d_1_s0/Q	frame_read_inst/v_cnt_0_s1/CLEAR	Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk:[R]	Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk:[R]	0.000	-0.007	0.315
20	0.355	frame_read_inst/rst_n_d_1_s0/Q	frame_read_inst/v_cnt_1_s1/CLEAR	Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk:[R]	Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk:[R]	0.000	-0.007	0.315
21	0.355	frame_read_inst/rst_n_d_1_s0/Q	frame_read_inst/v_cnt_4_s1/CLEAR	Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk:[R]	Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk:[R]	0.000	-0.007	0.315
22	0.356	SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/rstn_s0/Q	SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_addr_o_0_s1/CLEAR	drp_clk:[R]	drp_clk:[R]	0.000	0.000	0.309
23	0.356	SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/rstn_s0/Q	SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_addr_o_1_s1/CLEAR	drp_clk:[R]	drp_clk:[R]	0.000	0.000	0.309
24	0.356	SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/rstn_s0/Q	SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_addr_o_2_s1/CLEAR	drp_clk:[R]	drp_clk:[R]	0.000	0.000	0.309
25	0.356	SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/rstn_s0/Q	SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/drp_addr_serdes_0_s0/CLEAR	drp_clk:[R]	drp_clk:[R]	0.000	0.000	0.309

Minimum Pulse Width Table:

Report Command:report_min_pulse_width -nworst 10 -detail

Number	Slack	Actual Width	Required Width	Type	Clock	Objects
1	0.817	1.593	0.776	Low Pulse Width	Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk	u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.mem_Small.mem_0_4_s
2	0.819	1.595	0.776	High Pulse Width	Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk	u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.mem_Small.mem_0_4_s
3	0.821	1.596	0.776	Low Pulse Width	Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk	u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.mem_Small.mem_0_2_s
4	0.822	1.598	0.776	High Pulse Width	Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk	u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.mem_Small.mem_0_2_s
5	0.824	1.600	0.776	Low Pulse Width	Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk	u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.mem_Small.mem_0_6_s
6	0.826	1.601	0.776	High Pulse Width	Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk	u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.mem_Small.mem_0_6_s
7	0.963	1.739	0.776	Low Pulse Width	rgb_clk	u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.mem_Big.mem_0_7_s
8	0.965	1.741	0.776	High Pulse Width	rgb_clk	u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.mem_Big.mem_0_7_s
9	0.966	1.742	0.776	Low Pulse Width	rgb_clk	u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.mem_Big.mem_0_0_s
10	0.966	1.742	0.776	Low Pulse Width	rgb_clk	u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.mem_Big.mem_0_1_s

Timing Report By Analysis Type:

Setup Analysis Report

Report Command:report_timing -setup -max_paths 100 -max_common_paths 1

Path1

Path Summary:

Slack	0.066
Data Arrival Time	7.651
Data Required Time	7.717
From	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0
To	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_14_s2
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
1.520	1.520	tNET	RR	1	R2C91[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/CLK
1.795	0.275	tC2Q	RR	2624	R2C91[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/Q
3.706	1.910	tNET	RR	1	R3C91[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_lcmd_22_s8/I2
4.085	0.379	tINS	RR	1	R3C91[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_lcmd_22_s8/F
4.200	0.115	tNET	RR	1	R2C91[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3097_s18/I2
4.579	0.379	tINS	RR	3	R2C91[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3097_s18/F
5.462	0.883	tNET	RR	1	R33C91[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5588_s5/I2
5.794	0.332	tINS	RR	1	R33C91[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5588_s5/F
6.223	0.429	tNET	RR	1	R41C89[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5588_s3/I0
6.602	0.379	tINS	RR	1	R41C89[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5588_s3/F
6.852	0.250	tNET	RR	1	R43C89[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5588_s0/I3
7.210	0.358	tINS	RR	2	R43C89[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5588_s0/F
7.651	0.441	tNET	RR	1	R44C88[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_14_s2/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.250	6.250					active clock edge time
6.250	0.000					pclk
6.250	0.000	tCL	RR	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.763	1.513	tNET	RR	1	R44C88[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_14_s2/CLK
7.717	-0.046	tSu		1	R44C88[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_14_s2

Path Statistics:

Clock Skew	-0.007
Setup Relationship	6.250
Logic Level	6
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.520, 100.000%
Arrival Data Path Delay	cell: 1.827, 29.798%; route: 4.029, 65.710%; tC2Q: 0.275, 4.492%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.513, 100.000%

Path2

Path Summary:

Slack	0.066
Data Arrival Time	7.651
Data Required Time	7.717
From	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0
To	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_14_s1
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
1.520	1.520	tNET	RR	1	R2C91[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/CLK
1.795	0.275	tC2Q	RR	2624	R2C91[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/Q
3.706	1.910	tNET	RR	1	R3C91[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_lcmd_22_s8/I2
4.085	0.379	tINS	RR	1	R3C91[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_lcmd_22_s8/F
4.200	0.115	tNET	RR	1	R2C91[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3097_s18/I2
4.579	0.379	tINS	RR	3	R2C91[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3097_s18/F
5.462	0.883	tNET	RR	1	R33C91[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5588_s5/I2
5.794	0.332	tINS	RR	1	R33C91[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5588_s5/F
6.223	0.429	tNET	RR	1	R41C89[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5588_s3/I0
6.602	0.379	tINS	RR	1	R41C89[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5588_s3/F
6.852	0.250	tNET	RR	1	R43C89[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5588_s0/I3
7.210	0.358	tINS	RR	2	R43C89[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5588_s0/F
7.651	0.441	tNET	RR	1	R44C88[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_14_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.250	6.250					active clock edge time
6.250	0.000					pclk
6.250	0.000	tCL	RR	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.763	1.513	tNET	RR	1	R44C88[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_14_s1/CLK
7.717	-0.046	tSu		1	R44C88[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_14_s1

Path Statistics:

Clock Skew	-0.007
Setup Relationship	6.250
Logic Level	6
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.520, 100.000%
Arrival Data Path Delay	cell: 1.827, 29.798%; route: 4.029, 65.710%; tC2Q: 0.275, 4.492%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.513, 100.000%

Path3

Path Summary:

Slack	0.066
Data Arrival Time	7.527
Data Required Time	7.593
From	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0
To	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_12_s2
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
1.520	1.520	tNET	RR	1	R2C91[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/CLK
1.795	0.275	tC2Q	RR	2624	R2C91[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/Q
3.721	1.926	tNET	RR	1	R2C97[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_lcmd_20_s8/I2
3.910	0.189	tINS	RR	1	R2C97[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_lcmd_20_s8/F
4.026	0.115	tNET	RR	1	R2C96[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3099_s20/I2
4.358	0.332	tINS	RR	3	R2C96[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3099_s20/F
5.520	1.162	tNET	RR	1	R37C91[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5590_s6/I2
5.891	0.372	tINS	RR	1	R37C91[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5590_s6/F
6.533	0.642	tNET	RR	1	R40C86[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5590_s3/I1
6.908	0.375	tINS	RR	1	R40C86[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5590_s3/F
6.910	0.002	tNET	RR	1	R40C86[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5590_s0/I3
7.289	0.379	tINS	RR	2	R40C86[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5590_s0/F
7.527	0.238	tNET	RR	1	R40C85[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_12_s2/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.250	6.250					active clock edge time
6.250	0.000					pclk
6.250	0.000	tCL	RR	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.757	1.507	tNET	RR	1	R40C85[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_12_s2/CLK
7.593	-0.164	tSu		1	R40C85[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_12_s2

Path Statistics:

Clock Skew	-0.014
Setup Relationship	6.250
Logic Level	6
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.520, 100.000%
Arrival Data Path Delay	cell: 1.647, 27.420%; route: 4.084, 67.995%; tC2Q: 0.275, 4.585%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.507, 100.000%

Path4

Path Summary:

Slack	0.069
Data Arrival Time	7.641
Data Required Time	7.711
From	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0
To	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_46_s1
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
1.520	1.520	tNET	RR	1	R2C91[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/CLK
1.795	0.275	tC2Q	RR	2624	R2C91[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/Q
3.706	1.910	tNET	RR	1	R3C91[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_lcmd_22_s8/I2
4.085	0.379	tINS	RR	1	R3C91[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_lcmd_22_s8/F
4.200	0.115	tNET	RR	1	R2C91[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3097_s18/I2
4.579	0.379	tINS	RR	3	R2C91[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3097_s18/F
5.462	0.883	tNET	RR	1	R33C91[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5556_s4/I2
5.794	0.332	tINS	RR	1	R33C91[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5556_s4/F
6.294	0.500	tNET	RR	1	R34C84[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5556_s2/I1
6.503	0.209	tINS	RF	1	R34C84[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5556_s2/F
6.840	0.337	tNET	FF	1	R42C82[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5556_s1/I0
7.199	0.358	tINS	FR	2	R42C82[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5556_s1/F
7.641	0.443	tNET	RR	1	R43C81[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_46_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.250	6.250					active clock edge time
6.250	0.000					pclk
6.250	0.000	tCL	RR	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.757	1.507	tNET	RR	1	R43C81[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_46_s1/CLK
7.711	-0.046	tSu		1	R43C81[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_46_s1

Path Statistics:

Clock Skew	-0.014
Setup Relationship	6.250
Logic Level	6
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.520, 100.000%
Arrival Data Path Delay	cell: 1.657, 27.068%; route: 4.189, 68.433%; tC2Q: 0.275, 4.499%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.507, 100.000%

Path5

Path Summary:

Slack	0.073
Data Arrival Time	7.527
Data Required Time	7.600
From	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0
To	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_12_s1
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
1.520	1.520	tNET	RR	1	R2C91[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/CLK
1.795	0.275	tC2Q	RR	2624	R2C91[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/Q
3.721	1.926	tNET	RR	1	R2C97[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_lcmd_20_s8/I2
3.910	0.189	tINS	RR	1	R2C97[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_lcmd_20_s8/F
4.026	0.115	tNET	RR	1	R2C96[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3099_s20/I2
4.358	0.332	tINS	RR	3	R2C96[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3099_s20/F
5.520	1.162	tNET	RR	1	R37C91[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5590_s6/I2
5.891	0.372	tINS	RR	1	R37C91[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5590_s6/F
6.533	0.642	tNET	RR	1	R40C86[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5590_s3/I1
6.908	0.375	tINS	RR	1	R40C86[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5590_s3/F
6.910	0.002	tNET	RR	1	R40C86[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5590_s0/I3
7.289	0.379	tINS	RR	2	R40C86[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5590_s0/F
7.527	0.238	tNET	RR	1	R40C84[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_12_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.250	6.250					active clock edge time
6.250	0.000					pclk
6.250	0.000	tCL	RR	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.763	1.513	tNET	RR	1	R40C84[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_12_s1/CLK
7.600	-0.164	tSu		1	R40C84[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_12_s1

Path Statistics:

Clock Skew	-0.007
Setup Relationship	6.250
Logic Level	6
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.520, 100.000%
Arrival Data Path Delay	cell: 1.647, 27.420%; route: 4.084, 67.995%; tC2Q: 0.275, 4.585%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.513, 100.000%

Path6

Path Summary:

Slack	0.078
Data Arrival Time	7.640
Data Required Time	7.717
From	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0
To	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_46_s2
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
1.520	1.520	tNET	RR	1	R2C91[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/CLK
1.795	0.275	tC2Q	RR	2624	R2C91[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/Q
3.706	1.910	tNET	RR	1	R3C91[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_lcmd_22_s8/I2
4.085	0.379	tINS	RR	1	R3C91[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_lcmd_22_s8/F
4.200	0.115	tNET	RR	1	R2C91[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3097_s18/I2
4.579	0.379	tINS	RR	3	R2C91[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3097_s18/F
5.462	0.883	tNET	RR	1	R33C91[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5556_s4/I2
5.794	0.332	tINS	RR	1	R33C91[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5556_s4/F
6.294	0.500	tNET	RR	1	R34C84[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5556_s2/I1
6.503	0.209	tINS	RF	1	R34C84[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5556_s2/F
6.840	0.337	tNET	FF	1	R42C82[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5556_s1/I0
7.199	0.358	tINS	FR	2	R42C82[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5556_s1/F
7.640	0.441	tNET	RR	1	R43C80[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_46_s2/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.250	6.250					active clock edge time
6.250	0.000					pclk
6.250	0.000	tCL	RR	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.763	1.513	tNET	RR	1	R43C80[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_46_s2/CLK
7.717	-0.046	tSu		1	R43C80[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_46_s2

Path Statistics:

Clock Skew	-0.007
Setup Relationship	6.250
Logic Level	6
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.520, 100.000%
Arrival Data Path Delay	cell: 1.657, 27.076%; route: 4.187, 68.424%; tC2Q: 0.275, 4.500%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.513, 100.000%

Path7

Path Summary:

Slack	0.086
Data Arrival Time	7.507
Data Required Time	7.593
From	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_header_pkt_68_s0
To	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_hp_9_s0
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
1.520	1.520	tNET	RR	1	R23C83[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_header_pkt_68_s0/CLK
1.795	0.275	tC2Q	RR	8	R23C83[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_header_pkt_68_s0/Q
2.862	1.066	tNET	RR	1	R23C83[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3758_s50/I3
3.241	0.379	tINS	RR	1	R23C83[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3758_s50/F
4.212	0.971	tNET	RR	1	R23C83[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3758_s41/I3
4.591	0.379	tINS	RR	2	R23C83[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3758_s41/F
4.958	0.367	tNET	RR	1	R24C82[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3754_s31/I3
5.330	0.372	tINS	RR	2	R24C82[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3754_s31/F
5.679	0.349	tNET	RR	1	R25C80[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3754_s27/I0
6.058	0.379	tINS	RR	1	R25C80[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3754_s27/F
6.196	0.139	tNET	RR	1	R25C80[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3754_s23/I1
6.575	0.379	tINS	RR	1	R25C80[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3754_s23/F
6.923	0.347	tNET	RR	1	R26C80[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3754_s22/I0
7.255	0.332	tINS	RR	2	R26C80[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3754_s22/F
7.507	0.252	tNET	RR	1	R26C81[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_hp_9_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.250	6.250					active clock edge time
6.250	0.000					pclk
6.250	0.000	tCL	RR	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.757	1.507	tNET	RR	1	R26C81[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_hp_9_s0/CLK
7.593	-0.164	tSu		1	R26C81[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_hp_9_s0

Path Statistics:

Clock Skew	-0.014
Setup Relationship	6.250
Logic Level	7
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.520, 100.000%
Arrival Data Path Delay	cell: 2.219, 37.072%; route: 3.492, 58.328%; tC2Q: 0.275, 4.600%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.507, 100.000%

Path8

Path Summary:

Slack	0.095
Data Arrival Time	7.616
Data Required Time	7.711
From	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0
To	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_54_s2
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
1.520	1.520	tNET	RR	1	R2C91[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/CLK
1.795	0.275	tC2Q	RR	2624	R2C91[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/Q
3.721	1.926	tNET	RR	1	R2C96[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_lcmd_14_s8/I2
3.930	0.209	tINS	RF	1	R2C96[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_lcmd_14_s8/F
4.036	0.106	tNET	FF	1	R3C96[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3105_s20/I2
4.369	0.332	tINS	FR	3	R3C96[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3105_s20/F
5.368	0.999	tNET	RR	1	R36C92[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5548_s4/I2
5.739	0.372	tINS	RR	1	R36C92[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5548_s4/F
6.076	0.337	tNET	RR	1	R36C84[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5548_s2/I1
6.451	0.375	tINS	RR	1	R36C84[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5548_s2/F
6.940	0.489	tNET	RR	1	R40C82[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5548_s1/I0
7.312	0.372	tINS	RR	2	R40C82[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5548_s1/F
7.616	0.304	tNET	RR	1	R40C81[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_54_s2/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.250	6.250					active clock edge time
6.250	0.000					pclk
6.250	0.000	tCL	RR	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.757	1.507	tNET	RR	1	R40C81[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_54_s2/CLK
7.711	-0.046	tSu		1	R40C81[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_54_s2

Path Statistics:

Clock Skew	-0.014
Setup Relationship	6.250
Logic Level	6
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.520, 100.000%
Arrival Data Path Delay	cell: 1.660, 27.226%; route: 4.161, 68.256%; tC2Q: 0.275, 4.518%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.507, 100.000%

Path9

Path Summary:

Slack	0.095
Data Arrival Time	7.616
Data Required Time	7.711
From	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0
To	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_54_s1
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
1.520	1.520	tNET	RR	1	R2C91[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/CLK
1.795	0.275	tC2Q	RR	2624	R2C91[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/Q
3.721	1.926	tNET	RR	1	R2C96[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_lcmd_14_s8/I2
3.930	0.209	tINS	RF	1	R2C96[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_lcmd_14_s8/F
4.036	0.106	tNET	FF	1	R3C96[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3105_s20/I2
4.369	0.332	tINS	FR	3	R3C96[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3105_s20/F
5.368	0.999	tNET	RR	1	R36C92[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5548_s4/I2
5.739	0.372	tINS	RR	1	R36C92[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5548_s4/F
6.076	0.337	tNET	RR	1	R36C84[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5548_s2/I1
6.451	0.375	tINS	RR	1	R36C84[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5548_s2/F
6.940	0.489	tNET	RR	1	R40C82[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5548_s1/I0
7.312	0.372	tINS	RR	2	R40C82[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5548_s1/F
7.616	0.304	tNET	RR	1	R40C81[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_54_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.250	6.250					active clock edge time
6.250	0.000					pclk
6.250	0.000	tCL	RR	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.757	1.507	tNET	RR	1	R40C81[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_54_s1/CLK
7.711	-0.046	tSu		1	R40C81[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_54_s1

Path Statistics:

Clock Skew	-0.014
Setup Relationship	6.250
Logic Level	6
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.520, 100.000%
Arrival Data Path Delay	cell: 1.660, 27.226%; route: 4.161, 68.256%; tC2Q: 0.275, 4.518%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.507, 100.000%

Path10

Path Summary:

Slack	0.107
Data Arrival Time	7.492
Data Required Time	7.600
From	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_header_pkt_68_s0
To	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_hp_9_s1
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
1.520	1.520	tNET	RR	1	R23C83[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_header_pkt_68_s0/CLK
1.795	0.275	tC2Q	RR	8	R23C83[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_header_pkt_68_s0/Q
2.862	1.066	tNET	RR	1	R23C83[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3758_s50/I3
3.241	0.379	tINS	RR	1	R23C83[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3758_s50/F
4.212	0.971	tNET	RR	1	R23C83[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3758_s41/I3
4.591	0.379	tINS	RR	2	R23C83[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3758_s41/F
4.958	0.367	tNET	RR	1	R24C82[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3754_s31/I3
5.330	0.372	tINS	RR	2	R24C82[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3754_s31/F
5.679	0.349	tNET	RR	1	R25C80[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3754_s27/I0
6.058	0.379	tINS	RR	1	R25C80[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3754_s27/F
6.196	0.139	tNET	RR	1	R25C80[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3754_s23/I1
6.575	0.379	tINS	RR	1	R25C80[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3754_s23/F
6.923	0.347	tNET	RR	1	R26C80[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3754_s22/I0
7.255	0.332	tINS	RR	2	R26C80[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3754_s22/F
7.492	0.238	tNET	RR	1	R26C82[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_hp_9_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.250	6.250					active clock edge time
6.250	0.000					pclk
6.250	0.000	tCL	RR	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.763	1.513	tNET	RR	1	R26C82[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_hp_9_s1/CLK
7.600	-0.164	tSu		1	R26C82[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_hp_9_s1

Path Statistics:

Clock Skew	-0.007
Setup Relationship	6.250
Logic Level	7
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.520, 100.000%
Arrival Data Path Delay	cell: 2.219, 37.161%; route: 3.478, 58.228%; tC2Q: 0.275, 4.611%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.513, 100.000%

Path11

Path Summary:

Slack	0.190
Data Arrival Time	7.410
Data Required Time	7.600
From	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0
To	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_27_s1
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
1.520	1.520	tNET	RR	1	R2C91[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/CLK
1.795	0.275	tC2Q	RR	2624	R2C91[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/Q
3.721	1.926	tNET	RR	1	R2C97[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_lcmd_3_s8/I2
3.930	0.209	tINS	RF	1	R2C97[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_lcmd_3_s8/F
4.036	0.106	tNET	FF	1	R3C97[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3116_s17/I2
4.369	0.332	tINS	FR	3	R3C97[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3116_s17/F
5.557	1.188	tNET	RR	1	R35C91[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5575_s5/I2
5.746	0.189	tINS	RR	1	R35C91[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5575_s5/F
6.149	0.403	tNET	RR	1	R40C89[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5575_s3/I0
6.524	0.375	tINS	RR	1	R40C89[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5575_s3/F
6.663	0.139	tNET	RR	1	R40C88[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5575_s0/I3
7.021	0.358	tINS	RR	2	R40C88[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5575_s0/F
7.410	0.389	tNET	RR	1	R42C86[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_27_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.250	6.250					active clock edge time
6.250	0.000					pclk
6.250	0.000	tCL	RR	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.763	1.513	tNET	RR	1	R42C86[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_27_s1/CLK
7.600	-0.164	tSu		1	R42C86[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_27_s1

Path Statistics:

Clock Skew	-0.007
Setup Relationship	6.250
Logic Level	6
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.520, 100.000%
Arrival Data Path Delay	cell: 1.463, 24.847%; route: 4.151, 70.477%; tC2Q: 0.275, 4.676%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.513, 100.000%

Path12

Path Summary:

Slack	0.201
Data Arrival Time	7.523
Data Required Time	7.724
From	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0
To	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_44_s2
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
1.520	1.520	tNET	RR	1	R2C91[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/CLK
1.795	0.275	tC2Q	RR	2624	R2C91[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/Q
3.721	1.926	tNET	RR	1	R2C97[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_lcmd_20_s8/I2
3.910	0.189	tINS	RR	1	R2C97[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_lcmd_20_s8/F
4.026	0.115	tNET	RR	1	R2C96[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3099_s20/I2
4.358	0.332	tINS	RR	3	R2C96[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3099_s20/F
5.617	1.259	tNET	RR	1	R37C91[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5558_s4/I2
5.806	0.189	tINS	RR	1	R37C91[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5558_s4/F
6.281	0.475	tNET	RR	1	R37C83[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5558_s2/I1
6.580	0.299	tINS	RR	1	R37C83[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5558_s2/F
6.858	0.278	tNET	RR	1	R43C83[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5558_s1/I0
7.233	0.375	tINS	RR	2	R43C83[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5558_s1/F
7.523	0.290	tNET	RR	1	R43C83[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_44_s2/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.250	6.250					active clock edge time
6.250	0.000					pclk
6.250	0.000	tCL	RR	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.770	1.520	tNET	RR	1	R43C83[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_44_s2/CLK
7.724	-0.046	tSu		1	R43C83[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_44_s2

Path Statistics:

Clock Skew	0.000
Setup Relationship	6.250
Logic Level	6
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.520, 100.000%
Arrival Data Path Delay	cell: 1.384, 23.058%; route: 4.343, 72.354%; tC2Q: 0.275, 4.588%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.520, 100.000%

Path13

Path Summary:

Slack	0.201
Data Arrival Time	7.523
Data Required Time	7.724
From	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0
To	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_44_s1
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
1.520	1.520	tNET	RR	1	R2C91[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/CLK
1.795	0.275	tC2Q	RR	2624	R2C91[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/Q
3.721	1.926	tNET	RR	1	R2C97[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_lcmd_20_s8/I2
3.910	0.189	tINS	RR	1	R2C97[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_lcmd_20_s8/F
4.026	0.115	tNET	RR	1	R2C96[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3099_s20/I2
4.358	0.332	tINS	RR	3	R2C96[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3099_s20/F
5.617	1.259	tNET	RR	1	R37C91[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5558_s4/I2
5.806	0.189	tINS	RR	1	R37C91[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5558_s4/F
6.281	0.475	tNET	RR	1	R37C83[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5558_s2/I1
6.580	0.299	tINS	RR	1	R37C83[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5558_s2/F
6.858	0.278	tNET	RR	1	R43C83[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5558_s1/I0
7.233	0.375	tINS	RR	2	R43C83[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5558_s1/F
7.523	0.290	tNET	RR	1	R43C83[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_44_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.250	6.250					active clock edge time
6.250	0.000					pclk
6.250	0.000	tCL	RR	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.770	1.520	tNET	RR	1	R43C83[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_44_s1/CLK
7.724	-0.046	tSu		1	R43C83[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_44_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	6.250
Logic Level	6
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.520, 100.000%
Arrival Data Path Delay	cell: 1.384, 23.058%; route: 4.343, 72.354%; tC2Q: 0.275, 4.588%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.520, 100.000%

Path14

Path Summary:

Slack	0.211
Data Arrival Time	7.507
Data Required Time	7.717
From	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0
To	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_41_s2
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
1.520	1.520	tNET	RR	1	R2C91[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/CLK
1.795	0.275	tC2Q	RR	2624	R2C91[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/Q
3.712	1.917	tNET	RR	1	R3C96[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_lcmd_17_s8/I2
3.921	0.209	tINS	RF	1	R3C96[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_lcmd_17_s8/F
4.028	0.106	tNET	FF	1	R3C95[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3102_s18/I2
4.197	0.169	tINS	FF	3	R3C95[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3102_s18/F
5.242	1.045	tNET	FF	1	R37C91[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5561_s4/I2
5.617	0.375	tINS	FR	1	R37C91[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5561_s4/F
5.952	0.335	tNET	RR	1	R37C85[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5561_s2/I1
6.331	0.379	tINS	RR	1	R37C85[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5561_s2/F
6.734	0.403	tNET	RR	1	R43C85[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5561_s1/I0
7.066	0.332	tINS	RR	2	R43C85[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5561_s1/F
7.507	0.441	tNET	RR	1	R43C84[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_41_s2/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.250	6.250					active clock edge time
6.250	0.000					pclk
6.250	0.000	tCL	RR	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.763	1.513	tNET	RR	1	R43C84[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_41_s2/CLK
7.717	-0.046	tSu		1	R43C84[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_41_s2

Path Statistics:

Clock Skew	-0.007
Setup Relationship	6.250
Logic Level	6
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.520, 100.000%
Arrival Data Path Delay	cell: 1.464, 24.459%; route: 4.247, 70.941%; tC2Q: 0.275, 4.600%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.513, 100.000%

Path15

Path Summary:

Slack	0.211
Data Arrival Time	7.507
Data Required Time	7.717
From	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0
To	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_41_s1
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
1.520	1.520	tNET	RR	1	R2C91[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/CLK
1.795	0.275	tC2Q	RR	2624	R2C91[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/Q
3.712	1.917	tNET	RR	1	R3C96[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_lcmd_17_s8/I2
3.921	0.209	tINS	RF	1	R3C96[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_lcmd_17_s8/F
4.028	0.106	tNET	FF	1	R3C95[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3102_s18/I2
4.197	0.169	tINS	FF	3	R3C95[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3102_s18/F
5.242	1.045	tNET	FF	1	R37C91[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5561_s4/I2
5.617	0.375	tINS	FR	1	R37C91[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5561_s4/F
5.952	0.335	tNET	RR	1	R37C85[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5561_s2/I1
6.331	0.379	tINS	RR	1	R37C85[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5561_s2/F
6.734	0.403	tNET	RR	1	R43C85[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5561_s1/I0
7.066	0.332	tINS	RR	2	R43C85[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5561_s1/F
7.507	0.441	tNET	RR	1	R43C84[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_41_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.250	6.250					active clock edge time
6.250	0.000					pclk
6.250	0.000	tCL	RR	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.763	1.513	tNET	RR	1	R43C84[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_41_s1/CLK
7.717	-0.046	tSu		1	R43C84[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_41_s1

Path Statistics:

Clock Skew	-0.007
Setup Relationship	6.250
Logic Level	6
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.520, 100.000%
Arrival Data Path Delay	cell: 1.464, 24.459%; route: 4.247, 70.941%; tC2Q: 0.275, 4.600%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.513, 100.000%

Path16

Path Summary:

Slack	0.236
Data Arrival Time	7.370
Data Required Time	7.606
From	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0
To	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_27_s2
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
1.520	1.520	tNET	RR	1	R2C91[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/CLK
1.795	0.275	tC2Q	RR	2624	R2C91[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/Q
3.721	1.926	tNET	RR	1	R2C97[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_lcmd_3_s8/I2
3.930	0.209	tINS	RF	1	R2C97[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_lcmd_3_s8/F
4.036	0.106	tNET	FF	1	R3C97[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3116_s17/I2
4.369	0.332	tINS	FR	3	R3C97[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3116_s17/F
5.557	1.188	tNET	RR	1	R35C91[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5575_s5/I2
5.746	0.189	tINS	RR	1	R35C91[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5575_s5/F
6.149	0.403	tNET	RR	1	R40C89[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5575_s3/I0
6.524	0.375	tINS	RR	1	R40C89[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5575_s3/F
6.663	0.139	tNET	RR	1	R40C88[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5575_s0/I3
7.021	0.358	tINS	RR	2	R40C88[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5575_s0/F
7.370	0.349	tNET	RR	1	R42C87[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_27_s2/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.250	6.250					active clock edge time
6.250	0.000					pclk
6.250	0.000	tCL	RR	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.770	1.520	tNET	RR	1	R42C87[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_27_s2/CLK
7.606	-0.164	tSu		1	R42C87[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_27_s2

Path Statistics:

Clock Skew	0.000
Setup Relationship	6.250
Logic Level	6
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.520, 100.000%
Arrival Data Path Delay	cell: 1.463, 25.015%; route: 4.111, 70.277%; tC2Q: 0.275, 4.708%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.520, 100.000%

Path17

Path Summary:

Slack	0.261
Data Arrival Time	7.456
Data Required Time	7.717
From	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/state_4_s1
To	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/state_0_s0
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
1.507	1.507	tNET	RR	1	R61C72[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/state_4_s1/CLK
1.771	0.265	tC2Q	RF	64	R61C72[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/state_4_s1/Q
4.542	2.771	tNET	FF	1	R36C68[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_5g/n1755_s30/I2
4.731	0.189	tINS	FR	5	R36C68[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_5g/n1755_s30/F
5.255	0.524	tNET	RR	1	R43C73[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/n3700_s60/I2
5.630	0.375	tINS	RR	1	R43C73[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/n3700_s60/F
5.744	0.113	tNET	RR	1	R42C73[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/n3700_s54/I3
6.115	0.372	tINS	RR	1	R42C73[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/n3700_s54/F
6.463	0.347	tNET	RR	1	R42C71[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/n3700_s48/I3
6.842	0.379	tINS	RR	1	R42C71[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/n3700_s48/F
7.078	0.236	tNET	RR	1	R40C71[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/n3700_s44/I3
7.456	0.379	tINS	RR	1	R40C71[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/n3700_s44/F
7.456	0.000	tNET	RR	1	R40C71[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/state_0_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.250	6.250					active clock edge time
6.250	0.000					pclk
6.250	0.000	tCL	RR	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.763	1.513	tNET	RR	1	R40C71[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/state_0_s0/CLK
7.717	-0.046	tSu		1	R40C71[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/state_0_s0

Path Statistics:

Clock Skew	0.007
Setup Relationship	6.250
Logic Level	6
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.507, 100.000%
Arrival Data Path Delay	cell: 1.694, 28.468%; route: 3.991, 67.085%; tC2Q: 0.265, 4.447%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.513, 100.000%

Path18

Path Summary:

Slack	0.279
Data Arrival Time	7.438
Data Required Time	7.717
From	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0
To	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_59_s2
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
1.520	1.520	tNET	RR	1	R2C91[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/CLK
1.795	0.275	tC2Q	RR	2624	R2C91[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/Q
3.721	1.926	tNET	RR	1	R2C97[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_lcmd_3_s8/I2
3.930	0.209	tINS	RF	1	R2C97[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_lcmd_3_s8/F
4.036	0.106	tNET	FF	1	R3C97[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3116_s17/I2
4.369	0.332	tINS	FR	3	R3C97[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3116_s17/F
5.557	1.188	tNET	RR	1	R35C91[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5543_s4/I2
5.889	0.332	tINS	RR	1	R35C91[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5543_s4/F
6.223	0.335	tNET	RR	1	R35C85[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5543_s2/I1
6.556	0.332	tINS	RR	1	R35C85[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5543_s2/F
6.835	0.280	tNET	RR	1	R44C85[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5543_s1/I0
7.134	0.299	tINS	RR	2	R44C85[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5543_s1/F
7.438	0.304	tNET	RR	1	R44C84[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_59_s2/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.250	6.250					active clock edge time
6.250	0.000					pclk
6.250	0.000	tCL	RR	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.763	1.513	tNET	RR	1	R44C84[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_59_s2/CLK
7.717	-0.046	tSu		1	R44C84[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_59_s2

Path Statistics:

Clock Skew	-0.007
Setup Relationship	6.250
Logic Level	6
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.520, 100.000%
Arrival Data Path Delay	cell: 1.504, 25.411%; route: 4.139, 69.936%; tC2Q: 0.275, 4.653%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.513, 100.000%

Path19

Path Summary:

Slack	0.279
Data Arrival Time	7.438
Data Required Time	7.717
From	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0
To	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_59_s1
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
1.520	1.520	tNET	RR	1	R2C91[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/CLK
1.795	0.275	tC2Q	RR	2624	R2C91[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/Q
3.721	1.926	tNET	RR	1	R2C97[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_lcmd_3_s8/I2
3.930	0.209	tINS	RF	1	R2C97[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_lcmd_3_s8/F
4.036	0.106	tNET	FF	1	R3C97[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3116_s17/I2
4.369	0.332	tINS	FR	3	R3C97[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3116_s17/F
5.557	1.188	tNET	RR	1	R35C91[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5543_s4/I2
5.889	0.332	tINS	RR	1	R35C91[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5543_s4/F
6.223	0.335	tNET	RR	1	R35C85[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5543_s2/I1
6.556	0.332	tINS	RR	1	R35C85[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5543_s2/F
6.835	0.280	tNET	RR	1	R44C85[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5543_s1/I0
7.134	0.299	tINS	RR	2	R44C85[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5543_s1/F
7.438	0.304	tNET	RR	1	R44C84[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_59_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.250	6.250					active clock edge time
6.250	0.000					pclk
6.250	0.000	tCL	RR	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.763	1.513	tNET	RR	1	R44C84[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_59_s1/CLK
7.717	-0.046	tSu		1	R44C84[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_59_s1

Path Statistics:

Clock Skew	-0.007
Setup Relationship	6.250
Logic Level	6
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.520, 100.000%
Arrival Data Path Delay	cell: 1.504, 25.411%; route: 4.139, 69.936%; tC2Q: 0.275, 4.653%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.513, 100.000%

Path20

Path Summary:

Slack	0.320
Data Arrival Time	7.279
Data Required Time	7.600
From	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0
To	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_22_s2
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
1.520	1.520	tNET	RR	1	R2C91[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/CLK
1.795	0.275	tC2Q	RR	2624	R2C91[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/Q
3.721	1.926	tNET	RR	1	R2C96[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_lcmd_14_s8/I2
3.930	0.209	tINS	RF	1	R2C96[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_lcmd_14_s8/F
4.036	0.106	tNET	FF	1	R3C96[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3105_s20/I2
4.369	0.332	tINS	FR	3	R3C96[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3105_s20/F
5.306	0.938	tNET	RR	1	R36C92[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5580_s5/I2
5.685	0.379	tINS	RR	1	R36C92[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5580_s5/F
6.141	0.455	tNET	RR	1	R40C88[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5580_s3/I0
6.473	0.332	tINS	RR	1	R40C88[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5580_s3/F
6.572	0.099	tNET	RR	1	R40C88[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5580_s0/I3
6.930	0.358	tINS	RR	2	R40C88[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5580_s0/F
7.279	0.349	tNET	RR	1	R40C86[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_22_s2/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.250	6.250					active clock edge time
6.250	0.000					pclk
6.250	0.000	tCL	RR	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.763	1.513	tNET	RR	1	R40C86[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_22_s2/CLK
7.600	-0.164	tSu		1	R40C86[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_22_s2

Path Statistics:

Clock Skew	-0.007
Setup Relationship	6.250
Logic Level	6
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.520, 100.000%
Arrival Data Path Delay	cell: 1.610, 27.957%; route: 3.874, 67.261%; tC2Q: 0.275, 4.782%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.513, 100.000%

Path21

Path Summary:

Slack	0.320
Data Arrival Time	7.279
Data Required Time	7.600
From	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0
To	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_22_s1
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
1.520	1.520	tNET	RR	1	R2C91[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/CLK
1.795	0.275	tC2Q	RR	2624	R2C91[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/Q
3.721	1.926	tNET	RR	1	R2C96[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_lcmd_14_s8/I2
3.930	0.209	tINS	RF	1	R2C96[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_lcmd_14_s8/F
4.036	0.106	tNET	FF	1	R3C96[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3105_s20/I2
4.369	0.332	tINS	FR	3	R3C96[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3105_s20/F
5.306	0.938	tNET	RR	1	R36C92[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5580_s5/I2
5.685	0.379	tINS	RR	1	R36C92[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5580_s5/F
6.141	0.455	tNET	RR	1	R40C88[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5580_s3/I0
6.473	0.332	tINS	RR	1	R40C88[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5580_s3/F
6.572	0.099	tNET	RR	1	R40C88[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5580_s0/I3
6.930	0.358	tINS	RR	2	R40C88[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5580_s0/F
7.279	0.349	tNET	RR	1	R40C86[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_22_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.250	6.250					active clock edge time
6.250	0.000					pclk
6.250	0.000	tCL	RR	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.763	1.513	tNET	RR	1	R40C86[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_22_s1/CLK
7.600	-0.164	tSu		1	R40C86[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_22_s1

Path Statistics:

Clock Skew	-0.007
Setup Relationship	6.250
Logic Level	6
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.520, 100.000%
Arrival Data Path Delay	cell: 1.610, 27.957%; route: 3.874, 67.261%; tC2Q: 0.275, 4.782%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.513, 100.000%

Path22

Path Summary:

Slack	0.327
Data Arrival Time	7.384
Data Required Time	7.711
From	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0
To	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_1_s2
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
1.520	1.520	tNET	RR	1	R2C91[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/CLK
1.795	0.275	tC2Q	RR	2624	R2C91[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/Q
3.714	1.919	tNET	RR	1	R2C92[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_lcmd_25_s8/I2
3.903	0.189	tINS	RR	1	R2C92[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_lcmd_25_s8/F
4.004	0.101	tNET	RR	1	R2C92[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3094_s18/I2
4.383	0.379	tINS	RR	3	R2C92[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3094_s18/F
5.323	0.940	tNET	RR	1	R34C91[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5601_s5/I2
5.512	0.189	tINS	RR	1	R34C91[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5601_s5/F
5.995	0.482	tNET	RR	1	R40C89[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5601_s3/I0
6.184	0.189	tINS	RR	1	R40C89[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5601_s3/F
6.571	0.387	tNET	RR	1	R43C87[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5601_s0/I3
6.943	0.372	tINS	RR	2	R43C87[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5601_s0/F
7.384	0.441	tNET	RR	1	R44C85[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_1_s2/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.250	6.250					active clock edge time
6.250	0.000					pclk
6.250	0.000	tCL	RR	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.757	1.507	tNET	RR	1	R44C85[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_1_s2/CLK
7.711	-0.046	tSu		1	R44C85[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_1_s2

Path Statistics:

Clock Skew	-0.014
Setup Relationship	6.250
Logic Level	6
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.520, 100.000%
Arrival Data Path Delay	cell: 1.318, 22.471%; route: 4.271, 72.832%; tC2Q: 0.275, 4.697%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.507, 100.000%

Path23

Path Summary:

Slack	0.332
Data Arrival Time	7.385
Data Required Time	7.717
From	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0
To	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_1_s1
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
1.520	1.520	tNET	RR	1	R2C91[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/CLK
1.795	0.275	tC2Q	RR	2624	R2C91[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/Q
3.714	1.919	tNET	RR	1	R2C92[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_lcmd_25_s8/I2
3.903	0.189	tINS	RR	1	R2C92[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_lcmd_25_s8/F
4.004	0.101	tNET	RR	1	R2C92[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3094_s18/I2
4.383	0.379	tINS	RR	3	R2C92[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3094_s18/F
5.323	0.940	tNET	RR	1	R34C91[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5601_s5/I2
5.512	0.189	tINS	RR	1	R34C91[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5601_s5/F
5.995	0.482	tNET	RR	1	R40C89[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5601_s3/I0
6.184	0.189	tINS	RR	1	R40C89[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5601_s3/F
6.571	0.387	tNET	RR	1	R43C87[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5601_s0/I3
6.943	0.372	tINS	RR	2	R43C87[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5601_s0/F
7.385	0.443	tNET	RR	1	R44C86[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_1_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.250	6.250					active clock edge time
6.250	0.000					pclk
6.250	0.000	tCL	RR	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.763	1.513	tNET	RR	1	R44C86[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_1_s1/CLK
7.717	-0.046	tSu		1	R44C86[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_1_s1

Path Statistics:

Clock Skew	-0.007
Setup Relationship	6.250
Logic Level	6
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.520, 100.000%
Arrival Data Path Delay	cell: 1.318, 22.464%; route: 4.272, 72.840%; tC2Q: 0.275, 4.695%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.513, 100.000%

Path24

Path Summary:

Slack	0.349
Data Arrival Time	7.368
Data Required Time	7.717
From	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0
To	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_25_s2
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
1.520	1.520	tNET	RR	1	R2C91[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/CLK
1.795	0.275	tC2Q	RR	2624	R2C91[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/Q
3.711	1.915	tNET	RR	1	R20C90[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_lcmd_1_s8/I2
4.090	0.379	tINS	RR	1	R20C90[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_lcmd_1_s8/F
4.205	0.115	tNET	RR	1	R20C91[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3118_s17/I2
4.537	0.332	tINS	RR	3	R20C91[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3118_s17/F
4.976	0.439	tNET	RR	1	R37C91[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5577_s6/I2
5.355	0.379	tINS	RR	1	R37C91[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5577_s6/F
5.962	0.608	tNET	RR	1	R40C88[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5577_s3/I1
6.334	0.372	tINS	RR	1	R40C88[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5577_s3/F
6.570	0.236	tNET	RR	1	R42C88[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5577_s0/I3
6.942	0.372	tINS	RR	2	R42C88[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5577_s0/F
7.368	0.427	tNET	RR	1	R44C88[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_25_s2/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.250	6.250					active clock edge time
6.250	0.000					pclk
6.250	0.000	tCL	RR	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.763	1.513	tNET	RR	1	R44C88[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_25_s2/CLK
7.717	-0.046	tSu		1	R44C88[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_25_s2

Path Statistics:

Clock Skew	-0.007
Setup Relationship	6.250
Logic Level	6
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.520, 100.000%
Arrival Data Path Delay	cell: 1.833, 31.348%; route: 3.740, 63.943%; tC2Q: 0.275, 4.709%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.513, 100.000%

Path25

Path Summary:

Slack	0.349
Data Arrival Time	7.368
Data Required Time	7.717
From	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0
To	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_25_s1
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
1.520	1.520	tNET	RR	1	R2C91[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/CLK
1.795	0.275	tC2Q	RR	2624	R2C91[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/Q
3.711	1.915	tNET	RR	1	R20C90[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_lcmd_1_s8/I2
4.090	0.379	tINS	RR	1	R20C90[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_lcmd_1_s8/F
4.205	0.115	tNET	RR	1	R20C91[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3118_s17/I2
4.537	0.332	tINS	RR	3	R20C91[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3118_s17/F
4.976	0.439	tNET	RR	1	R37C91[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5577_s6/I2
5.355	0.379	tINS	RR	1	R37C91[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5577_s6/F
5.962	0.608	tNET	RR	1	R40C88[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5577_s3/I1
6.334	0.372	tINS	RR	1	R40C88[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5577_s3/F
6.570	0.236	tNET	RR	1	R42C88[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5577_s0/I3
6.942	0.372	tINS	RR	2	R42C88[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5577_s0/F
7.368	0.427	tNET	RR	1	R44C88[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_25_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.250	6.250					active clock edge time
6.250	0.000					pclk
6.250	0.000	tCL	RR	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.763	1.513	tNET	RR	1	R44C88[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_25_s1/CLK
7.717	-0.046	tSu		1	R44C88[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_25_s1

Path Statistics:

Clock Skew	-0.007
Setup Relationship	6.250
Logic Level	6
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.520, 100.000%
Arrival Data Path Delay	cell: 1.833, 31.348%; route: 3.740, 63.943%; tC2Q: 0.275, 4.709%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.513, 100.000%

Path26

Path Summary:

Slack	0.360
Data Arrival Time	7.232
Data Required Time	7.593
From	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0
To	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_62_s2
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
1.520	1.520	tNET	RR	1	R2C91[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/CLK
1.795	0.275	tC2Q	RR	2624	R2C91[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/Q
3.721	1.926	tNET	RR	1	R2C97[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_lcmd_6_s8/I2
3.910	0.189	tINS	RR	1	R2C97[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_lcmd_6_s8/F
4.026	0.115	tNET	RR	1	R3C97[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3113_s17/I2
4.234	0.209	tINS	RF	3	R3C97[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3113_s17/F
5.376	1.141	tNET	FF	1	R35C91[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5540_s4/I2
5.747	0.372	tINS	FR	1	R35C91[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5540_s4/F
5.998	0.250	tNET	RR	1	R35C88[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5540_s2/I1
6.296	0.299	tINS	RR	1	R35C88[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5540_s2/F
6.601	0.305	tNET	RR	1	R43C87[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5540_s1/I0
6.980	0.379	tINS	RR	2	R43C87[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5540_s1/F
7.232	0.252	tNET	RR	1	R43C85[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_62_s2/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.250	6.250					active clock edge time
6.250	0.000					pclk
6.250	0.000	tCL	RR	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.757	1.507	tNET	RR	1	R43C85[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_62_s2/CLK
7.593	-0.164	tSu		1	R43C85[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_62_s2

Path Statistics:

Clock Skew	-0.014
Setup Relationship	6.250
Logic Level	6
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.520, 100.000%
Arrival Data Path Delay	cell: 1.447, 25.335%; route: 3.990, 69.844%; tC2Q: 0.275, 4.821%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.507, 100.000%

Path27

Path Summary:

Slack	0.379
Data Arrival Time	7.227
Data Required Time	7.606
From	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/reset_n_d_s0
To	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_6_s1
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
1.507	1.507	tNET	RR	1	R37C85[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/reset_n_d_s0/CLK
1.771	0.265	tC2Q	RF	159	R37C85[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/reset_n_d_s0/Q
3.900	2.128	tNET	FF	1	R50C81[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_dpp_30_s8/I2
4.279	0.379	tINS	FR	1	R50C81[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_dpp_30_s8/F
4.282	0.004	tNET	RR	1	R50C81[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5564_s3/I2
4.614	0.332	tINS	RR	3	R50C81[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5564_s3/F
5.276	0.661	tNET	RR	1	R39C83[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5596_s5/I1
5.634	0.358	tINS	RR	1	R39C83[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5596_s5/F
6.021	0.387	tNET	RR	1	R39C88[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5596_s3/I0
6.400	0.379	tINS	RR	1	R39C88[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5596_s3/F
6.499	0.099	tNET	RR	1	R39C88[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5596_s0/I3
6.878	0.379	tINS	RR	2	R39C88[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5596_s0/F
7.227	0.349	tNET	RR	1	R40C87[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_6_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.250	6.250					active clock edge time
6.250	0.000					pclk
6.250	0.000	tCL	RR	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.770	1.520	tNET	RR	1	R40C87[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_6_s1/CLK
7.606	-0.164	tSu		1	R40C87[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_6_s1

Path Statistics:

Clock Skew	0.014
Setup Relationship	6.250
Logic Level	6
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.507, 100.000%
Arrival Data Path Delay	cell: 1.827, 31.938%; route: 3.629, 63.436%; tC2Q: 0.265, 4.626%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.520, 100.000%

Path28

Path Summary:

Slack	0.397
Data Arrival Time	7.313
Data Required Time	7.711
From	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0
To	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_38_s2
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
1.520	1.520	tNET	RR	1	R2C91[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/CLK
1.795	0.275	tC2Q	RR	2624	R2C91[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/Q
3.711	1.915	tNET	RR	1	R20C90[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_lcmd_30_s8/I2
4.090	0.379	tINS	RR	1	R20C90[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_lcmd_30_s8/F
4.190	0.101	tNET	RR	1	R20C90[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3089_s22/I2
4.562	0.372	tINS	RR	3	R20C90[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3089_s22/F
5.113	0.551	tNET	RR	1	R36C91[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5564_s4/I2
5.485	0.372	tINS	RR	1	R36C91[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5564_s4/F
5.812	0.328	tNET	RR	1	R36C83[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5564_s2/I1
6.187	0.375	tINS	RR	1	R36C83[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5564_s2/F
6.479	0.292	tNET	RR	1	R43C83[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5564_s1/I0
6.854	0.375	tINS	RR	2	R43C83[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5564_s1/F
7.313	0.459	tNET	RR	1	R44C81[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_38_s2/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.250	6.250					active clock edge time
6.250	0.000					pclk
6.250	0.000	tCL	RR	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.757	1.507	tNET	RR	1	R44C81[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_38_s2/CLK
7.711	-0.046	tSu		1	R44C81[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_38_s2

Path Statistics:

Clock Skew	-0.014
Setup Relationship	6.250
Logic Level	6
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.520, 100.000%
Arrival Data Path Delay	cell: 1.873, 32.329%; route: 3.645, 62.918%; tC2Q: 0.275, 4.754%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.507, 100.000%

Path29

Path Summary:

Slack	0.397
Data Arrival Time	7.313
Data Required Time	7.711
From	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0
To	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_38_s1
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
1.520	1.520	tNET	RR	1	R2C91[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/CLK
1.795	0.275	tC2Q	RR	2624	R2C91[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/Q
3.711	1.915	tNET	RR	1	R20C90[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_lcmd_30_s8/I2
4.090	0.379	tINS	RR	1	R20C90[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_lcmd_30_s8/F
4.190	0.101	tNET	RR	1	R20C90[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3089_s22/I2
4.562	0.372	tINS	RR	3	R20C90[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3089_s22/F
5.113	0.551	tNET	RR	1	R36C91[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5564_s4/I2
5.485	0.372	tINS	RR	1	R36C91[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5564_s4/F
5.812	0.328	tNET	RR	1	R36C83[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5564_s2/I1
6.187	0.375	tINS	RR	1	R36C83[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5564_s2/F
6.479	0.292	tNET	RR	1	R43C83[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5564_s1/I0
6.854	0.375	tINS	RR	2	R43C83[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5564_s1/F
7.313	0.459	tNET	RR	1	R44C81[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_38_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.250	6.250					active clock edge time
6.250	0.000					pclk
6.250	0.000	tCL	RR	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.757	1.507	tNET	RR	1	R44C81[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_38_s1/CLK
7.711	-0.046	tSu		1	R44C81[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_38_s1

Path Statistics:

Clock Skew	-0.014
Setup Relationship	6.250
Logic Level	6
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.520, 100.000%
Arrival Data Path Delay	cell: 1.873, 32.329%; route: 3.645, 62.918%; tC2Q: 0.275, 4.754%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.507, 100.000%

Path30

Path Summary:

Slack	0.401
Data Arrival Time	7.317
Data Required Time	7.717
From	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_header_pkt_48_s0
To	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_hp_4_s1
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
1.513	1.513	tNET	RR	1	R25C84[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_header_pkt_48_s0/CLK
1.789	0.275	tC2Q	RR	5	R25C84[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_header_pkt_48_s0/Q
2.557	0.769	tNET	RR	1	R25C84[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3758_s51/I1
2.929	0.372	tINS	RR	2	R25C84[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3758_s51/F
3.278	0.349	tNET	RR	1	R23C84[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3759_s37/I2
3.650	0.372	tINS	RR	1	R23C84[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3759_s37/F
3.789	0.139	tNET	RR	1	R24C84[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3759_s32/I3
4.121	0.332	tINS	RR	1	R24C84[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3759_s32/F
5.355	1.235	tNET	RR	1	R25C84[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3759_s26/I3
5.731	0.375	tINS	RR	2	R25C84[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3759_s26/F
6.008	0.277	tNET	RR	1	R26C85[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3759_s24/I0
6.383	0.375	tINS	RR	1	R26C85[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3759_s24/F
6.497	0.113	tNET	RR	1	R26C86[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3759_s22/I2
6.876	0.379	tINS	RR	2	R26C86[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3759_s22/F
7.317	0.441	tNET	RR	1	R26C88[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_hp_4_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.250	6.250					active clock edge time
6.250	0.000					pclk
6.250	0.000	tCL	RR	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.763	1.513	tNET	RR	1	R26C88[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_hp_4_s1/CLK
7.717	-0.046	tSu		1	R26C88[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_hp_4_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	6.250
Logic Level	7
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.513, 100.000%
Arrival Data Path Delay	cell: 2.205, 37.996%; route: 3.323, 57.258%; tC2Q: 0.275, 4.746%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.513, 100.000%

Path31

Path Summary:

Slack	0.401
Data Arrival Time	7.317
Data Required Time	7.717
From	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_header_pkt_48_s0
To	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_hp_4_s0
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
1.513	1.513	tNET	RR	1	R25C84[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_header_pkt_48_s0/CLK
1.789	0.275	tC2Q	RR	5	R25C84[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_header_pkt_48_s0/Q
2.557	0.769	tNET	RR	1	R25C84[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3758_s51/I1
2.929	0.372	tINS	RR	2	R25C84[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3758_s51/F
3.278	0.349	tNET	RR	1	R23C84[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3759_s37/I2
3.650	0.372	tINS	RR	1	R23C84[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3759_s37/F
3.789	0.139	tNET	RR	1	R24C84[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3759_s32/I3
4.121	0.332	tINS	RR	1	R24C84[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3759_s32/F
5.355	1.235	tNET	RR	1	R25C84[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3759_s26/I3
5.731	0.375	tINS	RR	2	R25C84[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3759_s26/F
6.008	0.277	tNET	RR	1	R26C85[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3759_s24/I0
6.383	0.375	tINS	RR	1	R26C85[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3759_s24/F
6.497	0.113	tNET	RR	1	R26C86[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3759_s22/I2
6.876	0.379	tINS	RR	2	R26C86[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3759_s22/F
7.317	0.441	tNET	RR	1	R26C88[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_hp_4_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.250	6.250					active clock edge time
6.250	0.000					pclk
6.250	0.000	tCL	RR	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.763	1.513	tNET	RR	1	R26C88[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_hp_4_s0/CLK
7.717	-0.046	tSu		1	R26C88[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_hp_4_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	6.250
Logic Level	7
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.513, 100.000%
Arrival Data Path Delay	cell: 2.205, 37.996%; route: 3.323, 57.258%; tC2Q: 0.275, 4.746%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.513, 100.000%

Path32

Path Summary:

Slack	0.407
Data Arrival Time	7.147
Data Required Time	7.554
From	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0
To	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_30_s2
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
1.520	1.520	tNET	RR	1	R2C91[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/CLK
1.795	0.275	tC2Q	RR	2624	R2C91[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/Q
3.721	1.926	tNET	RR	1	R2C97[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_lcmd_6_s8/I2
3.910	0.189	tINS	RR	1	R2C97[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_lcmd_6_s8/F
4.026	0.115	tNET	RR	1	R3C97[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3113_s17/I2
4.234	0.209	tINS	RF	3	R3C97[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3113_s17/F
5.376	1.141	tNET	FF	1	R35C91[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5572_s5/I2
5.747	0.372	tINS	FR	1	R35C91[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5572_s5/F
6.151	0.403	tNET	RR	1	R40C90[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5572_s3/I0
6.529	0.379	tINS	RR	1	R40C90[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5572_s3/F
6.628	0.099	tNET	RR	1	R40C90[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5572_s0/I3
6.798	0.169	tINS	RF	2	R40C90[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5572_s0/F
7.147	0.349	tNET	FF	1	R42C88[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_30_s2/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.250	6.250					active clock edge time
6.250	0.000					pclk
6.250	0.000	tCL	RR	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.763	1.513	tNET	RR	1	R42C88[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_30_s2/CLK
7.554	-0.210	tSu		1	R42C88[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_30_s2

Path Statistics:

Clock Skew	-0.007
Setup Relationship	6.250
Logic Level	6
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.520, 100.000%
Arrival Data Path Delay	cell: 1.318, 23.417%; route: 4.034, 71.689%; tC2Q: 0.275, 4.894%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.513, 100.000%

Path33

Path Summary:

Slack	0.407
Data Arrival Time	7.147
Data Required Time	7.554
From	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0
To	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_30_s1
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
1.520	1.520	tNET	RR	1	R2C91[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/CLK
1.795	0.275	tC2Q	RR	2624	R2C91[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/Q
3.721	1.926	tNET	RR	1	R2C97[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_lcmd_6_s8/I2
3.910	0.189	tINS	RR	1	R2C97[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_lcmd_6_s8/F
4.026	0.115	tNET	RR	1	R3C97[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3113_s17/I2
4.234	0.209	tINS	RF	3	R3C97[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3113_s17/F
5.376	1.141	tNET	FF	1	R35C91[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5572_s5/I2
5.747	0.372	tINS	FR	1	R35C91[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5572_s5/F
6.151	0.403	tNET	RR	1	R40C90[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5572_s3/I0
6.529	0.379	tINS	RR	1	R40C90[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5572_s3/F
6.628	0.099	tNET	RR	1	R40C90[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5572_s0/I3
6.798	0.169	tINS	RF	2	R40C90[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5572_s0/F
7.147	0.349	tNET	FF	1	R42C88[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_30_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.250	6.250					active clock edge time
6.250	0.000					pclk
6.250	0.000	tCL	RR	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.763	1.513	tNET	RR	1	R42C88[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_30_s1/CLK
7.554	-0.210	tSu		1	R42C88[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_30_s1

Path Statistics:

Clock Skew	-0.007
Setup Relationship	6.250
Logic Level	6
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.520, 100.000%
Arrival Data Path Delay	cell: 1.318, 23.417%; route: 4.034, 71.689%; tC2Q: 0.275, 4.894%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.513, 100.000%

Path34

Path Summary:

Slack	0.426
Data Arrival Time	7.180
Data Required Time	7.606
From	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0
To	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_3_s2
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
1.520	1.520	tNET	RR	1	R2C91[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/CLK
1.795	0.275	tC2Q	RR	2624	R2C91[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/Q
3.721	1.926	tNET	RR	1	R2C97[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_lcmd_27_s8/I2
3.910	0.189	tINS	RR	1	R2C97[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_lcmd_27_s8/F
4.026	0.115	tNET	RR	1	R2C96[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3092_s21/I2
4.215	0.189	tINS	RR	3	R2C96[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3092_s21/F
5.240	1.025	tNET	RR	1	R36C92[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5599_s6/I2
5.619	0.379	tINS	RR	1	R36C92[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5599_s6/F
6.151	0.532	tNET	RR	1	R39C88[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5599_s3/I1
6.483	0.332	tINS	RR	1	R39C88[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5599_s3/F
6.596	0.113	tNET	RR	1	R39C88[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5599_s0/I3
6.928	0.332	tINS	RR	2	R39C88[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5599_s0/F
7.180	0.252	tNET	RR	1	R40C87[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_3_s2/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.250	6.250					active clock edge time
6.250	0.000					pclk
6.250	0.000	tCL	RR	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.770	1.520	tNET	RR	1	R40C87[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_3_s2/CLK
7.606	-0.164	tSu		1	R40C87[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_3_s2

Path Statistics:

Clock Skew	0.000
Setup Relationship	6.250
Logic Level	6
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.520, 100.000%
Arrival Data Path Delay	cell: 1.421, 25.107%; route: 3.964, 70.027%; tC2Q: 0.275, 4.866%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.520, 100.000%

Path35

Path Summary:

Slack	0.426
Data Arrival Time	7.180
Data Required Time	7.606
From	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0
To	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_3_s1
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
1.520	1.520	tNET	RR	1	R2C91[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/CLK
1.795	0.275	tC2Q	RR	2624	R2C91[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/Q
3.721	1.926	tNET	RR	1	R2C97[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_lcmd_27_s8/I2
3.910	0.189	tINS	RR	1	R2C97[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_lcmd_27_s8/F
4.026	0.115	tNET	RR	1	R2C96[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3092_s21/I2
4.215	0.189	tINS	RR	3	R2C96[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3092_s21/F
5.240	1.025	tNET	RR	1	R36C92[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5599_s6/I2
5.619	0.379	tINS	RR	1	R36C92[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5599_s6/F
6.151	0.532	tNET	RR	1	R39C88[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5599_s3/I1
6.483	0.332	tINS	RR	1	R39C88[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5599_s3/F
6.596	0.113	tNET	RR	1	R39C88[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5599_s0/I3
6.928	0.332	tINS	RR	2	R39C88[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5599_s0/F
7.180	0.252	tNET	RR	1	R40C87[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_3_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.250	6.250					active clock edge time
6.250	0.000					pclk
6.250	0.000	tCL	RR	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.770	1.520	tNET	RR	1	R40C87[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_3_s1/CLK
7.606	-0.164	tSu		1	R40C87[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_3_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	6.250
Logic Level	6
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.520, 100.000%
Arrival Data Path Delay	cell: 1.421, 25.107%; route: 3.964, 70.027%; tC2Q: 0.275, 4.866%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.520, 100.000%

Path36

Path Summary:

Slack	0.427
Data Arrival Time	7.291
Data Required Time	7.717
From	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0
To	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_9_s2
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
1.520	1.520	tNET	RR	1	R2C91[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/CLK
1.795	0.275	tC2Q	RR	2624	R2C91[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/Q
3.712	1.917	tNET	RR	1	R3C96[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_lcmd_17_s8/I2
3.921	0.209	tINS	RF	1	R3C96[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_lcmd_17_s8/F
4.028	0.106	tNET	FF	1	R3C95[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3102_s18/I2
4.197	0.169	tINS	FF	3	R3C95[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3102_s18/F
5.242	1.045	tNET	FF	1	R37C91[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5593_s5/I2
5.621	0.379	tINS	FR	1	R37C91[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5593_s5/F
6.147	0.527	tNET	RR	1	R42C88[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5593_s3/I0
6.336	0.189	tINS	RR	1	R42C88[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5593_s3/F
6.338	0.002	tNET	RR	1	R42C88[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5593_s0/I3
6.713	0.375	tINS	RR	2	R42C88[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5593_s0/F
7.291	0.578	tNET	RR	1	R44C86[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_9_s2/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.250	6.250					active clock edge time
6.250	0.000					pclk
6.250	0.000	tCL	RR	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.763	1.513	tNET	RR	1	R44C86[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_9_s2/CLK
7.717	-0.046	tSu		1	R44C86[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_9_s2

Path Statistics:

Clock Skew	-0.007
Setup Relationship	6.250
Logic Level	6
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.520, 100.000%
Arrival Data Path Delay	cell: 1.321, 22.895%; route: 4.174, 72.333%; tC2Q: 0.275, 4.772%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.513, 100.000%

Path37

Path Summary:

Slack	0.433
Data Arrival Time	7.285
Data Required Time	7.717
From	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0
To	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_62_s1
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
1.520	1.520	tNET	RR	1	R2C91[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/CLK
1.795	0.275	tC2Q	RR	2624	R2C91[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/Q
3.721	1.926	tNET	RR	1	R2C97[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_lcmd_6_s8/I2
3.910	0.189	tINS	RR	1	R2C97[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_lcmd_6_s8/F
4.026	0.115	tNET	RR	1	R3C97[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3113_s17/I2
4.234	0.209	tINS	RF	3	R3C97[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3113_s17/F
5.376	1.141	tNET	FF	1	R35C91[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5540_s4/I2
5.747	0.372	tINS	FR	1	R35C91[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5540_s4/F
5.998	0.250	tNET	RR	1	R35C88[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5540_s2/I1
6.296	0.299	tINS	RR	1	R35C88[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5540_s2/F
6.601	0.305	tNET	RR	1	R43C87[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5540_s1/I0
6.980	0.379	tINS	RR	2	R43C87[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5540_s1/F
7.285	0.304	tNET	RR	1	R43C86[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_62_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.250	6.250					active clock edge time
6.250	0.000					pclk
6.250	0.000	tCL	RR	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.763	1.513	tNET	RR	1	R43C86[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_62_s1/CLK
7.717	-0.046	tSu		1	R43C86[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_62_s1

Path Statistics:

Clock Skew	-0.007
Setup Relationship	6.250
Logic Level	6
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.520, 100.000%
Arrival Data Path Delay	cell: 1.447, 25.105%; route: 4.042, 70.117%; tC2Q: 0.275, 4.778%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.513, 100.000%

Path38

Path Summary:

Slack	0.441
Data Arrival Time	7.277
Data Required Time	7.717
From	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0
To	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_9_s1
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
1.520	1.520	tNET	RR	1	R2C91[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/CLK
1.795	0.275	tC2Q	RR	2624	R2C91[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/Q
3.712	1.917	tNET	RR	1	R3C96[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_lcmd_17_s8/I2
3.921	0.209	tINS	RF	1	R3C96[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_lcmd_17_s8/F
4.028	0.106	tNET	FF	1	R3C95[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3102_s18/I2
4.197	0.169	tINS	FF	3	R3C95[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3102_s18/F
5.242	1.045	tNET	FF	1	R37C91[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5593_s5/I2
5.621	0.379	tINS	FR	1	R37C91[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5593_s5/F
6.147	0.527	tNET	RR	1	R42C88[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5593_s3/I0
6.336	0.189	tINS	RR	1	R42C88[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5593_s3/F
6.338	0.002	tNET	RR	1	R42C88[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5593_s0/I3
6.713	0.375	tINS	RR	2	R42C88[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5593_s0/F
7.277	0.563	tNET	RR	1	R44C86[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_9_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.250	6.250					active clock edge time
6.250	0.000					pclk
6.250	0.000	tCL	RR	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.763	1.513	tNET	RR	1	R44C86[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_9_s1/CLK
7.717	-0.046	tSu		1	R44C86[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_9_s1

Path Statistics:

Clock Skew	-0.007
Setup Relationship	6.250
Logic Level	6
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.520, 100.000%
Arrival Data Path Delay	cell: 1.321, 22.952%; route: 4.160, 72.264%; tC2Q: 0.275, 4.784%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.513, 100.000%

Path39

Path Summary:

Slack	0.453
Data Arrival Time	7.107
Data Required Time	7.560
From	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0
To	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_35_s2
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
1.520	1.520	tNET	RR	1	R2C91[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/CLK
1.795	0.275	tC2Q	RR	2624	R2C91[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/Q
3.721	1.926	tNET	RR	1	R2C97[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_lcmd_27_s8/I2
3.910	0.189	tINS	RR	1	R2C97[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_lcmd_27_s8/F
4.026	0.115	tNET	RR	1	R2C96[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3092_s21/I2
4.195	0.169	tINS	RF	3	R2C96[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3092_s21/F
5.268	1.073	tNET	FF	1	R36C92[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5567_s4/I2
5.457	0.189	tINS	FR	1	R36C92[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5567_s4/F
5.930	0.473	tNET	RR	1	R37C84[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5567_s2/I1
6.288	0.358	tINS	RR	1	R37C84[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5567_s2/F
6.597	0.309	tNET	RR	1	R40C84[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5567_s1/I0
6.872	0.275	tINS	RF	2	R40C84[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5567_s1/F
7.107	0.235	tNET	FF	1	R40C83[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_35_s2/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.250	6.250					active clock edge time
6.250	0.000					pclk
6.250	0.000	tCL	RR	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.770	1.520	tNET	RR	1	R40C83[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_35_s2/CLK
7.560	-0.210	tSu		1	R40C83[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_35_s2

Path Statistics:

Clock Skew	0.000
Setup Relationship	6.250
Logic Level	6
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.520, 100.000%
Arrival Data Path Delay	cell: 1.181, 21.134%; route: 4.131, 73.937%; tC2Q: 0.275, 4.929%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.520, 100.000%

Path40

Path Summary:

Slack	0.460
Data Arrival Time	7.257
Data Required Time	7.717
From	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_dpp_length_2_s4
To	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_dpp_17_s1
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
1.513	1.513	tNET	RR	1	R49C98[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_dpp_length_2_s4/CLK
1.789	0.275	tC2Q	RR	9	R49C98[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_dpp_length_2_s4/Q
2.068	0.279	tNET	RR	1	R50C99[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/dpp_crc_append/n1507_s0/I2
2.400	0.332	tINS	RR	5	R50C99[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/dpp_crc_append/n1507_s0/F
2.865	0.465	tNET	RR	1	R44C101[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n4740_s20/I3
3.237	0.372	tINS	RR	5	R44C101[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n4740_s20/F
3.929	0.692	tNET	RR	1	R45C88[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n4740_s18/I1
4.308	0.379	tINS	RR	38	R45C88[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n4740_s18/F
5.366	1.058	tNET	RR	1	R49C87[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n4721_s14/I2
5.738	0.372	tINS	RR	1	R49C87[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n4721_s14/F
5.988	0.250	tNET	RR	1	R48C86[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n4721_s11/I1
6.287	0.299	tINS	RR	1	R48C86[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n4721_s11/F
6.400	0.113	tNET	RR	1	R48C85[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n4721_s10/I0
6.759	0.358	tINS	RR	2	R48C85[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n4721_s10/F
7.257	0.499	tNET	RR	1	R46C84[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_dpp_17_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.250	6.250					active clock edge time
6.250	0.000					pclk
6.250	0.000	tCL	RR	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.763	1.513	tNET	RR	1	R46C84[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_dpp_17_s1/CLK
7.717	-0.046	tSu		1	R46C84[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_dpp_17_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	6.250
Logic Level	7
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.513, 100.000%
Arrival Data Path Delay	cell: 2.111, 36.760%; route: 3.357, 58.446%; tC2Q: 0.275, 4.795%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.513, 100.000%

Path41

Path Summary:

Slack	0.460
Data Arrival Time	7.257
Data Required Time	7.717
From	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_dpp_length_2_s4
To	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_dpp_17_s0
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
1.513	1.513	tNET	RR	1	R49C98[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_dpp_length_2_s4/CLK
1.789	0.275	tC2Q	RR	9	R49C98[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_dpp_length_2_s4/Q
2.068	0.279	tNET	RR	1	R50C99[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/dpp_crc_append/n1507_s0/I2
2.400	0.332	tINS	RR	5	R50C99[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/dpp_crc_append/n1507_s0/F
2.865	0.465	tNET	RR	1	R44C101[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n4740_s20/I3
3.237	0.372	tINS	RR	5	R44C101[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n4740_s20/F
3.929	0.692	tNET	RR	1	R45C88[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n4740_s18/I1
4.308	0.379	tINS	RR	38	R45C88[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n4740_s18/F
5.366	1.058	tNET	RR	1	R49C87[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n4721_s14/I2
5.738	0.372	tINS	RR	1	R49C87[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n4721_s14/F
5.988	0.250	tNET	RR	1	R48C86[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n4721_s11/I1
6.287	0.299	tINS	RR	1	R48C86[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n4721_s11/F
6.400	0.113	tNET	RR	1	R48C85[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n4721_s10/I0
6.759	0.358	tINS	RR	2	R48C85[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n4721_s10/F
7.257	0.499	tNET	RR	1	R46C84[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_dpp_17_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.250	6.250					active clock edge time
6.250	0.000					pclk
6.250	0.000	tCL	RR	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.763	1.513	tNET	RR	1	R46C84[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_dpp_17_s0/CLK
7.717	-0.046	tSu		1	R46C84[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_dpp_17_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	6.250
Logic Level	7
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.513, 100.000%
Arrival Data Path Delay	cell: 2.111, 36.760%; route: 3.357, 58.446%; tC2Q: 0.275, 4.795%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.513, 100.000%

Path42

Path Summary:

Slack	0.484
Data Arrival Time	7.115
Data Required Time	7.600
From	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/reset_n_d_s0
To	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_6_s2
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
1.507	1.507	tNET	RR	1	R37C85[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/reset_n_d_s0/CLK
1.771	0.265	tC2Q	RF	159	R37C85[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/reset_n_d_s0/Q
3.900	2.128	tNET	FF	1	R50C81[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_dpp_30_s8/I2
4.279	0.379	tINS	FR	1	R50C81[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_dpp_30_s8/F
4.282	0.004	tNET	RR	1	R50C81[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5564_s3/I2
4.614	0.332	tINS	RR	3	R50C81[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5564_s3/F
5.276	0.661	tNET	RR	1	R39C83[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5596_s5/I1
5.634	0.358	tINS	RR	1	R39C83[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5596_s5/F
6.021	0.387	tNET	RR	1	R39C88[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5596_s3/I0
6.400	0.379	tINS	RR	1	R39C88[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5596_s3/F
6.499	0.099	tNET	RR	1	R39C88[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5596_s0/I3
6.878	0.379	tINS	RR	2	R39C88[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5596_s0/F
7.115	0.238	tNET	RR	1	R40C88[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_6_s2/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.250	6.250					active clock edge time
6.250	0.000					pclk
6.250	0.000	tCL	RR	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.763	1.513	tNET	RR	1	R40C88[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_6_s2/CLK
7.600	-0.164	tSu		1	R40C88[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_6_s2

Path Statistics:

Clock Skew	0.007
Setup Relationship	6.250
Logic Level	6
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.507, 100.000%
Arrival Data Path Delay	cell: 1.827, 32.574%; route: 3.517, 62.709%; tC2Q: 0.265, 4.718%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.513, 100.000%

Path43

Path Summary:

Slack	0.519
Data Arrival Time	7.376
Data Required Time	7.896
From	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/state_4_s1
To	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/ts_loopback_latch_0_s2
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
1.507	1.507	tNET	RR	1	R61C72[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/state_4_s1/CLK
1.771	0.265	tC2Q	RF	64	R61C72[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/state_4_s1/Q
4.831	3.060	tNET	FF	1	R36C60[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_5g/ts_hot_reset_latch_3_s7/I1
5.020	0.189	tINS	FR	2	R36C60[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_5g/ts_hot_reset_latch_3_s7/F
5.135	0.115	tNET	RR	1	R35C60[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_5g/ts_hot_reset_latch_3_s5/I1
5.344	0.209	tINS	RF	2	R35C60[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_5g/ts_hot_reset_latch_3_s5/F
5.933	0.589	tNET	FF	1	R34C71[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/ts_hot_reset_latch_3_s6/I2
6.308	0.375	tINS	FR	1	R34C71[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/ts_hot_reset_latch_3_s6/F
6.447	0.139	tNET	RR	1	R36C71[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/ts_hot_reset_latch_3_s4/I1
6.636	0.189	tINS	RR	5	R36C71[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/ts_hot_reset_latch_3_s4/F
6.751	0.115	tNET	RR	1	R36C70[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/ts_loopback_latch_3_s4/I2
7.126	0.375	tINS	RR	4	R36C70[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/ts_loopback_latch_3_s4/F
7.376	0.250	tNET	RR	1	R36C69[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/ts_loopback_latch_0_s2/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.250	6.250					active clock edge time
6.250	0.000					pclk
6.250	0.000	tCL	RR	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
8.120	1.870	tNET	RR	1	R36C69[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/ts_loopback_latch_0_s2/CLK
7.896	-0.224	tSu		1	R36C69[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/ts_loopback_latch_0_s2

Path Statistics:

Clock Skew	0.363
Setup Relationship	6.250
Logic Level	6
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.507, 100.000%
Arrival Data Path Delay	cell: 1.337, 22.784%; route: 4.268, 72.708%; tC2Q: 0.265, 4.508%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.870, 100.000%

Path44

Path Summary:

Slack	0.519
Data Arrival Time	7.376
Data Required Time	7.896
From	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/state_4_s1
To	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/ts_loopback_latch_1_s2
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
1.507	1.507	tNET	RR	1	R61C72[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/state_4_s1/CLK
1.771	0.265	tC2Q	RF	64	R61C72[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/state_4_s1/Q
4.831	3.060	tNET	FF	1	R36C60[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_5g/ts_hot_reset_latch_3_s7/I1
5.020	0.189	tINS	FR	2	R36C60[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_5g/ts_hot_reset_latch_3_s7/F
5.135	0.115	tNET	RR	1	R35C60[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_5g/ts_hot_reset_latch_3_s5/I1
5.344	0.209	tINS	RF	2	R35C60[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_5g/ts_hot_reset_latch_3_s5/F
5.933	0.589	tNET	FF	1	R34C71[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/ts_hot_reset_latch_3_s6/I2
6.308	0.375	tINS	FR	1	R34C71[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/ts_hot_reset_latch_3_s6/F
6.447	0.139	tNET	RR	1	R36C71[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/ts_hot_reset_latch_3_s4/I1
6.636	0.189	tINS	RR	5	R36C71[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/ts_hot_reset_latch_3_s4/F
6.751	0.115	tNET	RR	1	R36C70[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/ts_loopback_latch_3_s4/I2
7.126	0.375	tINS	RR	4	R36C70[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/ts_loopback_latch_3_s4/F
7.376	0.250	tNET	RR	1	R36C69[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/ts_loopback_latch_1_s2/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.250	6.250					active clock edge time
6.250	0.000					pclk
6.250	0.000	tCL	RR	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
8.120	1.870	tNET	RR	1	R36C69[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/ts_loopback_latch_1_s2/CLK
7.896	-0.224	tSu		1	R36C69[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/ts_loopback_latch_1_s2

Path Statistics:

Clock Skew	0.363
Setup Relationship	6.250
Logic Level	6
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.507, 100.000%
Arrival Data Path Delay	cell: 1.337, 22.784%; route: 4.268, 72.708%; tC2Q: 0.265, 4.508%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.870, 100.000%

Path45

Path Summary:

Slack	0.519
Data Arrival Time	7.376
Data Required Time	7.896
From	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/state_4_s1
To	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/ts_loopback_latch_2_s2
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
1.507	1.507	tNET	RR	1	R61C72[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/state_4_s1/CLK
1.771	0.265	tC2Q	RF	64	R61C72[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/state_4_s1/Q
4.831	3.060	tNET	FF	1	R36C60[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_5g/ts_hot_reset_latch_3_s7/I1
5.020	0.189	tINS	FR	2	R36C60[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_5g/ts_hot_reset_latch_3_s7/F
5.135	0.115	tNET	RR	1	R35C60[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_5g/ts_hot_reset_latch_3_s5/I1
5.344	0.209	tINS	RF	2	R35C60[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_5g/ts_hot_reset_latch_3_s5/F
5.933	0.589	tNET	FF	1	R34C71[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/ts_hot_reset_latch_3_s6/I2
6.308	0.375	tINS	FR	1	R34C71[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/ts_hot_reset_latch_3_s6/F
6.447	0.139	tNET	RR	1	R36C71[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/ts_hot_reset_latch_3_s4/I1
6.636	0.189	tINS	RR	5	R36C71[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/ts_hot_reset_latch_3_s4/F
6.751	0.115	tNET	RR	1	R36C70[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/ts_loopback_latch_3_s4/I2
7.126	0.375	tINS	RR	4	R36C70[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/ts_loopback_latch_3_s4/F
7.376	0.250	tNET	RR	1	R36C69[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/ts_loopback_latch_2_s2/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.250	6.250					active clock edge time
6.250	0.000					pclk
6.250	0.000	tCL	RR	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
8.120	1.870	tNET	RR	1	R36C69[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/ts_loopback_latch_2_s2/CLK
7.896	-0.224	tSu		1	R36C69[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/ts_loopback_latch_2_s2

Path Statistics:

Clock Skew	0.363
Setup Relationship	6.250
Logic Level	6
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.507, 100.000%
Arrival Data Path Delay	cell: 1.337, 22.784%; route: 4.268, 72.708%; tC2Q: 0.265, 4.508%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.870, 100.000%

Path46

Path Summary:

Slack	0.519
Data Arrival Time	7.376
Data Required Time	7.896
From	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/state_4_s1
To	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/ts_loopback_latch_3_s2
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
1.507	1.507	tNET	RR	1	R61C72[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/state_4_s1/CLK
1.771	0.265	tC2Q	RF	64	R61C72[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/state_4_s1/Q
4.831	3.060	tNET	FF	1	R36C60[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_5g/ts_hot_reset_latch_3_s7/I1
5.020	0.189	tINS	FR	2	R36C60[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_5g/ts_hot_reset_latch_3_s7/F
5.135	0.115	tNET	RR	1	R35C60[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_5g/ts_hot_reset_latch_3_s5/I1
5.344	0.209	tINS	RF	2	R35C60[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_5g/ts_hot_reset_latch_3_s5/F
5.933	0.589	tNET	FF	1	R34C71[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/ts_hot_reset_latch_3_s6/I2
6.308	0.375	tINS	FR	1	R34C71[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/ts_hot_reset_latch_3_s6/F
6.447	0.139	tNET	RR	1	R36C71[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/ts_hot_reset_latch_3_s4/I1
6.636	0.189	tINS	RR	5	R36C71[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/ts_hot_reset_latch_3_s4/F
6.751	0.115	tNET	RR	1	R36C70[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/ts_loopback_latch_3_s4/I2
7.126	0.375	tINS	RR	4	R36C70[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/ts_loopback_latch_3_s4/F
7.376	0.250	tNET	RR	1	R36C69[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/ts_loopback_latch_3_s2/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.250	6.250					active clock edge time
6.250	0.000					pclk
6.250	0.000	tCL	RR	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
8.120	1.870	tNET	RR	1	R36C69[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/ts_loopback_latch_3_s2/CLK
7.896	-0.224	tSu		1	R36C69[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/ts_loopback_latch_3_s2

Path Statistics:

Clock Skew	0.363
Setup Relationship	6.250
Logic Level	6
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.507, 100.000%
Arrival Data Path Delay	cell: 1.337, 22.784%; route: 4.268, 72.708%; tC2Q: 0.265, 4.508%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.870, 100.000%

Path47

Path Summary:

Slack	0.527
Data Arrival Time	7.197
Data Required Time	7.724
From	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0
To	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_49_s2
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
1.520	1.520	tNET	RR	1	R2C91[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/CLK
1.795	0.275	tC2Q	RR	2624	R2C91[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/Q
3.706	1.910	tNET	RR	1	R2C91[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_lcmd_9_s8/I2
4.005	0.299	tINS	RR	1	R2C91[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_lcmd_9_s8/F
4.105	0.101	tNET	RR	1	R2C91[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3110_s17/I2
4.294	0.189	tINS	RR	3	R2C91[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3110_s17/F
5.096	0.802	tNET	RR	1	R34C91[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5553_s4/I2
5.468	0.372	tINS	RR	1	R34C91[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5553_s4/F
5.778	0.310	tNET	RR	1	R34C83[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5553_s2/I1
6.156	0.379	tINS	RR	1	R34C83[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5553_s2/F
6.579	0.423	tNET	RR	1	R42C83[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5553_s1/I0
6.770	0.191	tINS	RR	2	R42C83[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5553_s1/F
7.197	0.427	tNET	RR	1	R44C83[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_49_s2/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.250	6.250					active clock edge time
6.250	0.000					pclk
6.250	0.000	tCL	RR	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.770	1.520	tNET	RR	1	R44C83[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_49_s2/CLK
7.724	-0.046	tSu		1	R44C83[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_49_s2

Path Statistics:

Clock Skew	0.000
Setup Relationship	6.250
Logic Level	6
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.520, 100.000%
Arrival Data Path Delay	cell: 1.429, 25.176%; route: 3.972, 69.972%; tC2Q: 0.275, 4.851%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.520, 100.000%

Path48

Path Summary:

Slack	0.527
Data Arrival Time	7.197
Data Required Time	7.724
From	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0
To	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_49_s1
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
1.520	1.520	tNET	RR	1	R2C91[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/CLK
1.795	0.275	tC2Q	RR	2624	R2C91[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/Q
3.706	1.910	tNET	RR	1	R2C91[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_lcmd_9_s8/I2
4.005	0.299	tINS	RR	1	R2C91[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_lcmd_9_s8/F
4.105	0.101	tNET	RR	1	R2C91[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3110_s17/I2
4.294	0.189	tINS	RR	3	R2C91[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3110_s17/F
5.096	0.802	tNET	RR	1	R34C91[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5553_s4/I2
5.468	0.372	tINS	RR	1	R34C91[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5553_s4/F
5.778	0.310	tNET	RR	1	R34C83[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5553_s2/I1
6.156	0.379	tINS	RR	1	R34C83[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5553_s2/F
6.579	0.423	tNET	RR	1	R42C83[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5553_s1/I0
6.770	0.191	tINS	RR	2	R42C83[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5553_s1/F
7.197	0.427	tNET	RR	1	R44C83[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_49_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.250	6.250					active clock edge time
6.250	0.000					pclk
6.250	0.000	tCL	RR	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.770	1.520	tNET	RR	1	R44C83[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_49_s1/CLK
7.724	-0.046	tSu		1	R44C83[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_49_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	6.250
Logic Level	6
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.520, 100.000%
Arrival Data Path Delay	cell: 1.429, 25.176%; route: 3.972, 69.972%; tC2Q: 0.275, 4.851%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.520, 100.000%

Path49

Path Summary:

Slack	0.537
Data Arrival Time	7.174
Data Required Time	7.711
From	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0
To	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_43_s1
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
1.520	1.520	tNET	RR	1	R2C91[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/CLK
1.795	0.275	tC2Q	RR	2624	R2C91[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/Q
3.711	1.915	tNET	RR	1	R27C90[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_lcmd_19_s8/I2
4.090	0.379	tINS	RR	1	R27C90[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_lcmd_19_s8/F
4.190	0.101	tNET	RR	1	R27C90[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3100_s18/I2
4.569	0.379	tINS	RR	3	R27C90[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3100_s18/F
4.937	0.368	tNET	RR	1	R35C89[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5559_s4/I2
5.309	0.372	tINS	RR	1	R35C89[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5559_s4/F
5.791	0.482	tNET	RR	1	R36C83[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5559_s2/I1
6.163	0.372	tINS	RR	1	R36C83[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5559_s2/F
6.455	0.292	tNET	RR	1	R43C83[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5559_s1/I0
6.826	0.372	tINS	RR	2	R43C83[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5559_s1/F
7.174	0.347	tNET	RR	1	R43C81[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_43_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.250	6.250					active clock edge time
6.250	0.000					pclk
6.250	0.000	tCL	RR	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.757	1.507	tNET	RR	1	R43C81[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_43_s1/CLK
7.711	-0.046	tSu		1	R43C81[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_43_s1

Path Statistics:

Clock Skew	-0.014
Setup Relationship	6.250
Logic Level	6
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.520, 100.000%
Arrival Data Path Delay	cell: 1.873, 33.126%; route: 3.505, 62.003%; tC2Q: 0.275, 4.871%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.507, 100.000%

Path50

Path Summary:

Slack	0.553
Data Arrival Time	7.782
Data Required Time	8.336
From	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_p132brxgears/skp_head_num_0_s0
To	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_p132brxgears/head_num_latch_add8_0_s0
Launch Clk	q0_lane1_fabric_rx_clk:[R]
Latch Clk	q0_lane1_fabric_rx_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					q0_lane1_fabric_rx_clk
0.000	0.000	tCL	RR	1622	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_RX_O_FABRIC_CLK
2.132	2.132	tNET	RR	1	R44C52[0][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_p132brxgears/skp_head_num_0_s0/CLK
2.407	0.275	tC2Q	RR	42	R44C52[0][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_p132brxgears/skp_head_num_0_s0/Q
3.851	1.444	tNET	RR	1	R40C42[2][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_p132brxgears/n717_s86/I2
4.183	0.332	tINS	RR	1	R40C42[2][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_p132brxgears/n717_s86/F
4.183	0.000	tNET	RR	1	R40C42[2][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_p132brxgears/n717_s80/I1
4.281	0.098	tINS	RR	1	R40C42[2][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_p132brxgears/n717_s80/O
4.281	0.000	tNET	RR	1	R40C42[2][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_p132brxgears/n717_s75/I1
4.343	0.062	tINS	RR	1	R40C42[2][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_p132brxgears/n717_s75/O
4.808	0.464	tNET	RR	1	R41C47[3][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_p132brxgears/n1123_s18/I1
5.017	0.209	tINS	RF	2	R41C47[3][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_p132brxgears/n1123_s18/F
5.359	0.342	tNET	FF	1	R42C51[2][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_p132brxgears/n1127_s6/I3
5.548	0.189	tINS	FR	2	R42C51[2][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_p132brxgears/n1127_s6/F
5.551	0.004	tNET	RR	1	R42C51[2][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_p132brxgears/n1127_s5/I2
5.930	0.379	tINS	RR	2	R42C51[2][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_p132brxgears/n1127_s5/F
6.045	0.115	tNET	RR	1	R42C52[3][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_p132brxgears/n1127_s4/I0
6.421	0.375	tINS	RR	2	R42C52[3][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_p132brxgears/n1127_s4/F
6.658	0.238	tNET	RR	1	R43C52[1][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_p132brxgears/n1131_s2/S0
6.840	0.182	tINS	RR	1	R43C52[1][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_p132brxgears/n1131_s2/O
7.090	0.250	tNET	RR	1	R43C52[3][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_p132brxgears/n1164_s1/I0
7.448	0.358	tINS	RR	1	R43C52[3][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_p132brxgears/n1164_s1/F
7.450	0.002	tNET	RR	1	R43C52[0][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_p132brxgears/n1164_s0/I1
7.782	0.332	tINS	RR	1	R43C52[0][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_p132brxgears/n1164_s0/F
7.782	0.000	tNET	RR	1	R43C52[0][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_p132brxgears/head_num_latch_add8_0_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.250	6.250					active clock edge time
6.250	0.000					q0_lane1_fabric_rx_clk
6.250	0.000	tCL	RR	1622	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_RX_O_FABRIC_CLK
8.382	2.132	tNET	RR	1	R43C52[0][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_p132brxgears/head_num_latch_add8_0_s0/CLK
8.336	-0.046	tSu		1	R43C52[0][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_p132brxgears/head_num_latch_add8_0_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	6.250
Logic Level	9
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.132, 100.000%
Arrival Data Path Delay	cell: 2.516, 44.533%; route: 2.859, 50.593%; tC2Q: 0.275, 4.874%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.132, 100.000%

Path51

Path Summary:

Slack	0.569
Data Arrival Time	7.149
Data Required Time	7.717
From	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0
To	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_43_s2
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
1.520	1.520	tNET	RR	1	R2C91[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/CLK
1.795	0.275	tC2Q	RR	2624	R2C91[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/Q
3.711	1.915	tNET	RR	1	R27C90[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_lcmd_19_s8/I2
4.090	0.379	tINS	RR	1	R27C90[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_lcmd_19_s8/F
4.190	0.101	tNET	RR	1	R27C90[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3100_s18/I2
4.569	0.379	tINS	RR	3	R27C90[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3100_s18/F
4.937	0.368	tNET	RR	1	R35C89[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5559_s4/I2
5.309	0.372	tINS	RR	1	R35C89[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5559_s4/F
5.791	0.482	tNET	RR	1	R36C83[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5559_s2/I1
6.163	0.372	tINS	RR	1	R36C83[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5559_s2/F
6.455	0.292	tNET	RR	1	R43C83[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5559_s1/I0
6.826	0.372	tINS	RR	2	R43C83[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5559_s1/F
7.149	0.322	tNET	RR	1	R43C82[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_43_s2/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.250	6.250					active clock edge time
6.250	0.000					pclk
6.250	0.000	tCL	RR	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.763	1.513	tNET	RR	1	R43C82[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_43_s2/CLK
7.717	-0.046	tSu		1	R43C82[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_43_s2

Path Statistics:

Clock Skew	-0.007
Setup Relationship	6.250
Logic Level	6
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.520, 100.000%
Arrival Data Path Delay	cell: 1.873, 33.275%; route: 3.480, 61.832%; tC2Q: 0.275, 4.893%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.513, 100.000%

Path52

Path Summary:

Slack	0.571
Data Arrival Time	6.976
Data Required Time	7.547
From	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0
To	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_17_s2
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
1.520	1.520	tNET	RR	1	R2C91[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/CLK
1.795	0.275	tC2Q	RR	2624	R2C91[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/Q
3.704	1.908	tNET	RR	1	R2C91[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_lcmd_41_s8/I2
4.062	0.358	tINS	RR	1	R2C91[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_lcmd_41_s8/F
4.177	0.115	tNET	RR	1	R2C90[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3078_s17/I2
4.509	0.332	tINS	RR	2	R2C90[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3078_s17/F
5.696	1.186	tNET	RR	1	R39C89[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5585_s1/I2
6.071	0.375	tINS	RR	1	R39C89[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5585_s1/F
6.458	0.387	tNET	RR	1	R42C87[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5585_s0/I0
6.627	0.169	tINS	RF	2	R42C87[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5585_s0/F
6.976	0.349	tNET	FF	1	R40C85[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_17_s2/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.250	6.250					active clock edge time
6.250	0.000					pclk
6.250	0.000	tCL	RR	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.757	1.507	tNET	RR	1	R40C85[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_17_s2/CLK
7.547	-0.210	tSu		1	R40C85[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_17_s2

Path Statistics:

Clock Skew	-0.014
Setup Relationship	6.250
Logic Level	5
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.520, 100.000%
Arrival Data Path Delay	cell: 1.235, 22.631%; route: 3.946, 72.322%; tC2Q: 0.275, 5.047%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.507, 100.000%

Path53

Path Summary:

Slack	0.571
Data Arrival Time	6.983
Data Required Time	7.554
From	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0
To	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_20_s2
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
1.520	1.520	tNET	RR	1	R2C91[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/CLK
1.795	0.275	tC2Q	RR	2624	R2C91[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/Q
3.714	1.919	tNET	RR	1	R2C92[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_lcmd_44_s8/I2
3.923	0.209	tINS	RF	1	R2C92[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_lcmd_44_s8/F
3.930	0.007	tNET	FF	1	R2C92[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3075_s17/I2
4.288	0.358	tINS	FR	2	R2C92[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3075_s17/F
5.963	1.675	tNET	RR	1	R39C89[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5582_s1/I2
6.342	0.379	tINS	RR	1	R39C89[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5582_s1/F
6.729	0.387	tNET	RR	1	R42C88[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5582_s0/I0
6.898	0.169	tINS	RF	2	R42C88[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5582_s0/F
6.983	0.085	tNET	FF	1	R42C88[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_20_s2/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.250	6.250					active clock edge time
6.250	0.000					pclk
6.250	0.000	tCL	RR	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.763	1.513	tNET	RR	1	R42C88[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_20_s2/CLK
7.554	-0.210	tSu		1	R42C88[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_20_s2

Path Statistics:

Clock Skew	-0.007
Setup Relationship	6.250
Logic Level	5
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.520, 100.000%
Arrival Data Path Delay	cell: 1.115, 20.412%; route: 4.073, 74.547%; tC2Q: 0.275, 5.041%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.513, 100.000%

Path54

Path Summary:

Slack	0.571
Data Arrival Time	6.983
Data Required Time	7.554
From	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0
To	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_20_s1
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
1.520	1.520	tNET	RR	1	R2C91[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/CLK
1.795	0.275	tC2Q	RR	2624	R2C91[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/Q
3.714	1.919	tNET	RR	1	R2C92[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_lcmd_44_s8/I2
3.923	0.209	tINS	RF	1	R2C92[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_lcmd_44_s8/F
3.930	0.007	tNET	FF	1	R2C92[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3075_s17/I2
4.288	0.358	tINS	FR	2	R2C92[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3075_s17/F
5.963	1.675	tNET	RR	1	R39C89[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5582_s1/I2
6.342	0.379	tINS	RR	1	R39C89[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5582_s1/F
6.729	0.387	tNET	RR	1	R42C88[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5582_s0/I0
6.898	0.169	tINS	RF	2	R42C88[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5582_s0/F
6.983	0.085	tNET	FF	1	R42C88[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_20_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.250	6.250					active clock edge time
6.250	0.000					pclk
6.250	0.000	tCL	RR	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.763	1.513	tNET	RR	1	R42C88[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_20_s1/CLK
7.554	-0.210	tSu		1	R42C88[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_20_s1

Path Statistics:

Clock Skew	-0.007
Setup Relationship	6.250
Logic Level	5
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.520, 100.000%
Arrival Data Path Delay	cell: 1.115, 20.412%; route: 4.073, 74.547%; tC2Q: 0.275, 5.041%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.513, 100.000%

Path55

Path Summary:

Slack	0.574
Data Arrival Time	7.026
Data Required Time	7.600
From	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_dpp_length_2_s4
To	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_dpp_9_s1
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
1.513	1.513	tNET	RR	1	R49C98[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_dpp_length_2_s4/CLK
1.789	0.275	tC2Q	RR	9	R49C98[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_dpp_length_2_s4/Q
2.068	0.279	tNET	RR	1	R50C99[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/dpp_crc_append/n1507_s0/I2
2.400	0.332	tINS	RR	5	R50C99[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/dpp_crc_append/n1507_s0/F
2.865	0.465	tNET	RR	1	R44C101[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n4740_s20/I3
3.237	0.372	tINS	RR	5	R44C101[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n4740_s20/F
3.929	0.692	tNET	RR	1	R45C88[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n4740_s18/I1
4.308	0.379	tINS	RR	38	R45C88[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n4740_s18/F
5.364	1.057	tNET	RR	1	R50C86[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n4729_s14/I2
5.573	0.209	tINS	RF	1	R50C86[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n4729_s14/F
5.992	0.419	tNET	FF	1	R49C82[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n4729_s11/I1
6.371	0.379	tINS	FR	1	R49C82[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n4729_s11/F
6.470	0.099	tNET	RR	1	R49C82[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n4729_s10/I0
6.659	0.189	tINS	RR	2	R49C82[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n4729_s10/F
7.026	0.367	tNET	RR	1	R48C82[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_dpp_9_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.250	6.250					active clock edge time
6.250	0.000					pclk
6.250	0.000	tCL	RR	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.763	1.513	tNET	RR	1	R48C82[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_dpp_9_s1/CLK
7.600	-0.164	tSu		1	R48C82[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_dpp_9_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	6.250
Logic Level	7
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.513, 100.000%
Arrival Data Path Delay	cell: 1.859, 33.731%; route: 3.378, 61.273%; tC2Q: 0.275, 4.996%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.513, 100.000%

Path56

Path Summary:

Slack	0.584
Data Arrival Time	7.141
Data Required Time	7.724
From	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0
To	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_11_s2
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
1.520	1.520	tNET	RR	1	R2C91[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/CLK
1.795	0.275	tC2Q	RR	2624	R2C91[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/Q
3.697	1.902	tNET	RR	1	R3C92[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_lcmd_51_s8/I2
4.076	0.379	tINS	RR	1	R3C92[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_lcmd_51_s8/F
4.218	0.142	tNET	RR	1	R3C91[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3068_s18/I2
4.550	0.332	tINS	RR	2	R3C91[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3068_s18/F
5.706	1.156	tNET	RR	1	R39C91[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5591_s2/I2
6.064	0.358	tINS	RR	1	R39C91[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5591_s2/F
6.399	0.335	tNET	RR	1	R43C89[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5591_s0/I1
6.698	0.299	tINS	RR	2	R43C89[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5591_s0/F
7.141	0.443	tNET	RR	1	R44C87[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_11_s2/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.250	6.250					active clock edge time
6.250	0.000					pclk
6.250	0.000	tCL	RR	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.770	1.520	tNET	RR	1	R44C87[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_11_s2/CLK
7.724	-0.046	tSu		1	R44C87[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_11_s2

Path Statistics:

Clock Skew	0.000
Setup Relationship	6.250
Logic Level	5
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.520, 100.000%
Arrival Data Path Delay	cell: 1.368, 24.339%; route: 3.977, 70.761%; tC2Q: 0.275, 4.900%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.520, 100.000%

Path57

Path Summary:

Slack	0.585
Data Arrival Time	7.139
Data Required Time	7.724
From	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0
To	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_11_s1
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
1.520	1.520	tNET	RR	1	R2C91[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/CLK
1.795	0.275	tC2Q	RR	2624	R2C91[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/Q
3.697	1.902	tNET	RR	1	R3C92[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_lcmd_51_s8/I2
4.076	0.379	tINS	RR	1	R3C92[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_lcmd_51_s8/F
4.218	0.142	tNET	RR	1	R3C91[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3068_s18/I2
4.550	0.332	tINS	RR	2	R3C91[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3068_s18/F
5.706	1.156	tNET	RR	1	R39C91[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5591_s2/I2
6.064	0.358	tINS	RR	1	R39C91[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5591_s2/F
6.399	0.335	tNET	RR	1	R43C89[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5591_s0/I1
6.698	0.299	tINS	RR	2	R43C89[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5591_s0/F
7.139	0.441	tNET	RR	1	R44C87[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_11_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.250	6.250					active clock edge time
6.250	0.000					pclk
6.250	0.000	tCL	RR	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.770	1.520	tNET	RR	1	R44C87[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_11_s1/CLK
7.724	-0.046	tSu		1	R44C87[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_11_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	6.250
Logic Level	5
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.520, 100.000%
Arrival Data Path Delay	cell: 1.368, 24.347%; route: 3.975, 70.751%; tC2Q: 0.275, 4.901%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.520, 100.000%

Path58

Path Summary:

Slack	0.587
Data Arrival Time	7.013
Data Required Time	7.600
From	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0
To	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_36_s1
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
1.520	1.520	tNET	RR	1	R2C91[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/CLK
1.795	0.275	tC2Q	RR	2624	R2C91[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/Q
3.721	1.926	tNET	RR	1	R2C96[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_lcmd_28_s8/I2
3.910	0.189	tINS	RR	1	R2C96[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_lcmd_28_s8/F
4.026	0.115	tNET	RR	1	R3C96[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3091_s22/I2
4.215	0.189	tINS	RR	3	R3C96[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3091_s22/F
5.213	0.998	tNET	RR	1	R35C92[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5566_s4/I2
5.422	0.209	tINS	RF	1	R35C92[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5566_s4/F
5.784	0.363	tNET	FF	1	R35C85[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5566_s2/I1
6.116	0.332	tINS	FR	1	R35C85[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5566_s2/F
6.396	0.280	tNET	RR	1	R43C85[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5566_s1/I0
6.775	0.379	tINS	RR	2	R43C85[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5566_s1/F
7.013	0.238	tNET	RR	1	R43C84[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_36_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.250	6.250					active clock edge time
6.250	0.000					pclk
6.250	0.000	tCL	RR	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.763	1.513	tNET	RR	1	R43C84[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_36_s1/CLK
7.600	-0.164	tSu		1	R43C84[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_36_s1

Path Statistics:

Clock Skew	-0.007
Setup Relationship	6.250
Logic Level	6
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.520, 100.000%
Arrival Data Path Delay	cell: 1.298, 23.628%; route: 3.920, 71.358%; tC2Q: 0.275, 5.014%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.513, 100.000%

Path59

Path Summary:

Slack	0.597
Data Arrival Time	6.957
Data Required Time	7.554
From	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0
To	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_35_s1
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
1.520	1.520	tNET	RR	1	R2C91[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/CLK
1.795	0.275	tC2Q	RR	2624	R2C91[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/Q
3.721	1.926	tNET	RR	1	R2C97[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_lcmd_27_s8/I2
3.910	0.189	tINS	RR	1	R2C97[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_lcmd_27_s8/F
4.026	0.115	tNET	RR	1	R2C96[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3092_s21/I2
4.195	0.169	tINS	RF	3	R2C96[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3092_s21/F
5.268	1.073	tNET	FF	1	R36C92[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5567_s4/I2
5.457	0.189	tINS	FR	1	R36C92[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5567_s4/F
5.930	0.473	tNET	RR	1	R37C84[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5567_s2/I1
6.288	0.358	tINS	RR	1	R37C84[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5567_s2/F
6.597	0.309	tNET	RR	1	R40C84[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5567_s1/I0
6.872	0.275	tINS	RF	2	R40C84[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5567_s1/F
6.957	0.085	tNET	FF	1	R40C84[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_35_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.250	6.250					active clock edge time
6.250	0.000					pclk
6.250	0.000	tCL	RR	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.763	1.513	tNET	RR	1	R40C84[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_35_s1/CLK
7.554	-0.210	tSu		1	R40C84[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_35_s1

Path Statistics:

Clock Skew	-0.007
Setup Relationship	6.250
Logic Level	6
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.520, 100.000%
Arrival Data Path Delay	cell: 1.181, 21.718%; route: 3.981, 73.216%; tC2Q: 0.275, 5.065%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.513, 100.000%

Path60

Path Summary:

Slack	0.598
Data Arrival Time	7.119
Data Required Time	7.717
From	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0
To	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_4_s1
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
1.520	1.520	tNET	RR	1	R2C91[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/CLK
1.795	0.275	tC2Q	RR	2624	R2C91[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/Q
3.712	1.917	tNET	RR	1	R3C98[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_lcmd_60_s8/I2
4.071	0.358	tINS	RR	1	R3C98[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_lcmd_60_s8/F
4.171	0.101	tNET	RR	1	R3C98[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3059_s19/I2
4.470	0.299	tINS	RR	2	R3C98[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3059_s19/F
5.701	1.230	tNET	RR	1	R36C89[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5598_s2/I2
5.890	0.189	tINS	RR	1	R36C89[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5598_s2/F
6.306	0.417	tNET	RR	1	R43C87[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5598_s0/I1
6.678	0.372	tINS	RR	2	R43C87[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5598_s0/F
7.119	0.441	tNET	RR	1	R44C86[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_4_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.250	6.250					active clock edge time
6.250	0.000					pclk
6.250	0.000	tCL	RR	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.763	1.513	tNET	RR	1	R44C86[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_4_s1/CLK
7.717	-0.046	tSu		1	R44C86[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_4_s1

Path Statistics:

Clock Skew	-0.007
Setup Relationship	6.250
Logic Level	5
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.520, 100.000%
Arrival Data Path Delay	cell: 1.218, 21.749%; route: 4.106, 73.332%; tC2Q: 0.275, 4.919%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.513, 100.000%

Path61

Path Summary:

Slack	0.600
Data Arrival Time	7.118
Data Required Time	7.717
From	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_dpp_length_2_s4
To	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_dpp_9_s0
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
1.513	1.513	tNET	RR	1	R49C98[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_dpp_length_2_s4/CLK
1.789	0.275	tC2Q	RR	9	R49C98[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_dpp_length_2_s4/Q
2.068	0.279	tNET	RR	1	R50C99[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/dpp_crc_append/n1507_s0/I2
2.400	0.332	tINS	RR	5	R50C99[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/dpp_crc_append/n1507_s0/F
2.865	0.465	tNET	RR	1	R44C101[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n4740_s20/I3
3.237	0.372	tINS	RR	5	R44C101[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n4740_s20/F
3.929	0.692	tNET	RR	1	R45C88[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n4740_s18/I1
4.308	0.379	tINS	RR	38	R45C88[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n4740_s18/F
5.364	1.057	tNET	RR	1	R50C86[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n4729_s14/I2
5.573	0.209	tINS	RF	1	R50C86[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n4729_s14/F
5.992	0.419	tNET	FF	1	R49C82[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n4729_s11/I1
6.371	0.379	tINS	FR	1	R49C82[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n4729_s11/F
6.470	0.099	tNET	RR	1	R49C82[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n4729_s10/I0
6.659	0.189	tINS	RR	2	R49C82[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n4729_s10/F
7.118	0.459	tNET	RR	1	R48C82[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_dpp_9_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.250	6.250					active clock edge time
6.250	0.000					pclk
6.250	0.000	tCL	RR	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.763	1.513	tNET	RR	1	R48C82[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_dpp_9_s0/CLK
7.717	-0.046	tSu		1	R48C82[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_dpp_9_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	6.250
Logic Level	7
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.513, 100.000%
Arrival Data Path Delay	cell: 1.859, 33.178%; route: 3.470, 61.908%; tC2Q: 0.275, 4.914%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.513, 100.000%

Path62

Path Summary:

Slack	0.602
Data Arrival Time	6.997
Data Required Time	7.600
From	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0
To	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_19_s2
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
1.520	1.520	tNET	RR	1	R2C91[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/CLK
1.795	0.275	tC2Q	RR	2624	R2C91[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/Q
3.711	1.915	tNET	RR	1	R2C98[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_lcmd_43_s8/I2
4.090	0.379	tINS	RR	1	R2C98[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_lcmd_43_s8/F
4.190	0.101	tNET	RR	1	R2C98[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3076_s17/I2
4.569	0.379	tINS	RR	2	R2C98[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3076_s17/F
5.784	1.215	tNET	RR	1	R39C89[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5583_s2/I2
6.163	0.379	tINS	RR	1	R39C89[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5583_s2/F
6.277	0.113	tNET	RR	1	R40C89[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5583_s0/I1
6.648	0.372	tINS	RR	2	R40C89[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5583_s0/F
6.997	0.349	tNET	RR	1	R40C88[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_19_s2/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.250	6.250					active clock edge time
6.250	0.000					pclk
6.250	0.000	tCL	RR	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.763	1.513	tNET	RR	1	R40C88[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_19_s2/CLK
7.600	-0.164	tSu		1	R40C88[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_19_s2

Path Statistics:

Clock Skew	-0.007
Setup Relationship	6.250
Logic Level	5
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.520, 100.000%
Arrival Data Path Delay	cell: 1.508, 27.539%; route: 3.694, 67.433%; tC2Q: 0.275, 5.028%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.513, 100.000%

Path63

Path Summary:

Slack	0.605
Data Arrival Time	7.113
Data Required Time	7.717
From	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0
To	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_57_s1
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
1.520	1.520	tNET	RR	1	R2C91[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/CLK
1.795	0.275	tC2Q	RR	2624	R2C91[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/Q
3.711	1.915	tNET	RR	1	R20C90[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_lcmd_1_s8/I2
4.090	0.379	tINS	RR	1	R20C90[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_lcmd_1_s8/F
4.205	0.115	tNET	RR	1	R20C91[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3118_s17/I2
4.537	0.332	tINS	RR	3	R20C91[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3118_s17/F
4.976	0.439	tNET	RR	1	R37C91[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5545_s4/I2
5.348	0.372	tINS	RR	1	R37C91[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5545_s4/F
5.683	0.335	tNET	RR	1	R37C85[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5545_s2/I1
6.054	0.372	tINS	RR	1	R37C85[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5545_s2/F
6.430	0.375	tNET	RR	1	R43C85[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5545_s1/I0
6.808	0.379	tINS	RR	2	R43C85[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5545_s1/F
7.113	0.304	tNET	RR	1	R43C84[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_57_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.250	6.250					active clock edge time
6.250	0.000					pclk
6.250	0.000	tCL	RR	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.763	1.513	tNET	RR	1	R43C84[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_57_s1/CLK
7.717	-0.046	tSu		1	R43C84[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_57_s1

Path Statistics:

Clock Skew	-0.007
Setup Relationship	6.250
Logic Level	6
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.520, 100.000%
Arrival Data Path Delay	cell: 1.833, 32.781%; route: 3.484, 62.295%; tC2Q: 0.275, 4.924%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.513, 100.000%

Path64

Path Summary:

Slack	0.609
Data Arrival Time	6.997
Data Required Time	7.606
From	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0
To	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_19_s1
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
1.520	1.520	tNET	RR	1	R2C91[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/CLK
1.795	0.275	tC2Q	RR	2624	R2C91[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/Q
3.711	1.915	tNET	RR	1	R2C98[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_lcmd_43_s8/I2
4.090	0.379	tINS	RR	1	R2C98[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_lcmd_43_s8/F
4.190	0.101	tNET	RR	1	R2C98[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3076_s17/I2
4.569	0.379	tINS	RR	2	R2C98[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3076_s17/F
5.784	1.215	tNET	RR	1	R39C89[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5583_s2/I2
6.163	0.379	tINS	RR	1	R39C89[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5583_s2/F
6.277	0.113	tNET	RR	1	R40C89[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5583_s0/I1
6.648	0.372	tINS	RR	2	R40C89[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5583_s0/F
6.997	0.349	tNET	RR	1	R40C87[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_19_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.250	6.250					active clock edge time
6.250	0.000					pclk
6.250	0.000	tCL	RR	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.770	1.520	tNET	RR	1	R40C87[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_19_s1/CLK
7.606	-0.164	tSu		1	R40C87[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_19_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	6.250
Logic Level	5
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.520, 100.000%
Arrival Data Path Delay	cell: 1.508, 27.539%; route: 3.694, 67.433%; tC2Q: 0.275, 5.028%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.520, 100.000%

Path65

Path Summary:

Slack	0.612
Data Arrival Time	7.098
Data Required Time	7.711
From	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0
To	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_57_s2
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
1.520	1.520	tNET	RR	1	R2C91[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/CLK
1.795	0.275	tC2Q	RR	2624	R2C91[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/Q
3.711	1.915	tNET	RR	1	R20C90[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_lcmd_1_s8/I2
4.090	0.379	tINS	RR	1	R20C90[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_lcmd_1_s8/F
4.205	0.115	tNET	RR	1	R20C91[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3118_s17/I2
4.537	0.332	tINS	RR	3	R20C91[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3118_s17/F
4.976	0.439	tNET	RR	1	R37C91[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5545_s4/I2
5.348	0.372	tINS	RR	1	R37C91[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5545_s4/F
5.683	0.335	tNET	RR	1	R37C85[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5545_s2/I1
6.054	0.372	tINS	RR	1	R37C85[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5545_s2/F
6.430	0.375	tNET	RR	1	R43C85[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5545_s1/I0
6.808	0.379	tINS	RR	2	R43C85[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5545_s1/F
7.098	0.290	tNET	RR	1	R43C85[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_57_s2/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.250	6.250					active clock edge time
6.250	0.000					pclk
6.250	0.000	tCL	RR	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.757	1.507	tNET	RR	1	R43C85[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_57_s2/CLK
7.711	-0.046	tSu		1	R43C85[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_57_s2

Path Statistics:

Clock Skew	-0.014
Setup Relationship	6.250
Logic Level	6
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.520, 100.000%
Arrival Data Path Delay	cell: 1.833, 32.865%; route: 3.469, 62.197%; tC2Q: 0.275, 4.937%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.507, 100.000%

Path66

Path Summary:

Slack	0.617
Data Arrival Time	7.718
Data Required Time	8.336
From	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_p132brxgears/skp_head_num_0_s0
To	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_p132brxgears/head_num_latch_add8_2_s0
Launch Clk	q0_lane1_fabric_rx_clk:[R]
Latch Clk	q0_lane1_fabric_rx_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					q0_lane1_fabric_rx_clk
0.000	0.000	tCL	RR	1622	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_RX_O_FABRIC_CLK
2.132	2.132	tNET	RR	1	R44C52[0][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_p132brxgears/skp_head_num_0_s0/CLK
2.407	0.275	tC2Q	RR	42	R44C52[0][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_p132brxgears/skp_head_num_0_s0/Q
3.851	1.444	tNET	RR	1	R40C42[2][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_p132brxgears/n717_s86/I2
4.183	0.332	tINS	RR	1	R40C42[2][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_p132brxgears/n717_s86/F
4.183	0.000	tNET	RR	1	R40C42[2][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_p132brxgears/n717_s80/I1
4.281	0.098	tINS	RR	1	R40C42[2][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_p132brxgears/n717_s80/O
4.281	0.000	tNET	RR	1	R40C42[2][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_p132brxgears/n717_s75/I1
4.343	0.062	tINS	RR	1	R40C42[2][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_p132brxgears/n717_s75/O
4.808	0.464	tNET	RR	1	R41C47[3][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_p132brxgears/n1123_s18/I1
5.017	0.209	tINS	RF	2	R41C47[3][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_p132brxgears/n1123_s18/F
5.359	0.342	tNET	FF	1	R42C51[2][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_p132brxgears/n1127_s6/I3
5.548	0.189	tINS	FR	2	R42C51[2][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_p132brxgears/n1127_s6/F
5.551	0.004	tNET	RR	1	R42C51[2][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_p132brxgears/n1127_s5/I2
5.930	0.379	tINS	RR	2	R42C51[2][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_p132brxgears/n1127_s5/F
6.031	0.101	tNET	RR	1	R42C51[3][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_p132brxgears/n1158_s7/I3
6.406	0.375	tINS	RR	5	R42C51[3][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_p132brxgears/n1158_s7/F
6.662	0.256	tNET	RR	1	R44C50[3][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_p132brxgears/n1162_s2/I3
7.037	0.375	tINS	RR	1	R44C50[3][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_p132brxgears/n1162_s2/F
7.039	0.002	tNET	RR	1	R44C50[3][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_p132brxgears/n1162_s1/I0
7.338	0.299	tINS	RR	1	R44C50[3][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_p132brxgears/n1162_s1/F
7.339	0.002	tNET	RR	1	R44C50[1][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_p132brxgears/n1162_s0/I1
7.718	0.379	tINS	RR	1	R44C50[1][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_p132brxgears/n1162_s0/F
7.718	0.000	tNET	RR	1	R44C50[1][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_p132brxgears/head_num_latch_add8_2_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.250	6.250					active clock edge time
6.250	0.000					q0_lane1_fabric_rx_clk
6.250	0.000	tCL	RR	1622	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_RX_O_FABRIC_CLK
8.382	2.132	tNET	RR	1	R44C50[1][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_p132brxgears/head_num_latch_add8_2_s0/CLK
8.336	-0.046	tSu		1	R44C50[1][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_p132brxgears/head_num_latch_add8_2_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	6.250
Logic Level	9
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.132, 100.000%
Arrival Data Path Delay	cell: 2.697, 48.280%; route: 2.614, 46.790%; tC2Q: 0.275, 4.930%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.132, 100.000%

Path67

Path Summary:

Slack	0.625
Data Arrival Time	7.092
Data Required Time	7.717
From	UserLayer_top_inst/ControlTransfer_inst/bmRequestType_latch_1_s0
To	UserLayer_top_inst/ControlTransfer_inst/transfer_in_data_mux_36_s0
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
1.520	1.520	tNET	RR	1	R62C119[3][A]	UserLayer_top_inst/ControlTransfer_inst/bmRequestType_latch_1_s0/CLK
1.795	0.275	tC2Q	RR	1	R62C119[3][A]	UserLayer_top_inst/ControlTransfer_inst/bmRequestType_latch_1_s0/Q
2.226	0.430	tNET	RR	1	R62C117[0][B]	UserLayer_top_inst/ControlTransfer_inst/n4645_s20/I0
2.558	0.332	tINS	RR	7	R62C117[0][B]	UserLayer_top_inst/ControlTransfer_inst/n4645_s20/F
2.855	0.297	tNET	RR	1	R64C119[1][A]	UserLayer_top_inst/ControlTransfer_inst/n4645_s16/I1
3.226	0.372	tINS	RR	59	R64C119[1][A]	UserLayer_top_inst/ControlTransfer_inst/n4645_s16/F
4.675	1.448	tNET	RR	1	R70C125[0][A]	UserLayer_top_inst/ControlTransfer_inst/n4655_s11/I1
5.046	0.372	tINS	RR	7	R70C125[0][A]	UserLayer_top_inst/ControlTransfer_inst/n4655_s11/F
5.516	0.470	tNET	RR	1	R72C120[1][A]	UserLayer_top_inst/ControlTransfer_inst/n4597_s17/I3
5.895	0.379	tINS	RR	1	R72C120[1][A]	UserLayer_top_inst/ControlTransfer_inst/n4597_s17/F
6.145	0.250	tNET	RR	1	R72C122[2][B]	UserLayer_top_inst/ControlTransfer_inst/n4597_s13/I3
6.524	0.379	tINS	RR	1	R72C122[2][B]	UserLayer_top_inst/ControlTransfer_inst/n4597_s13/F
6.760	0.236	tNET	RR	1	R70C122[2][B]	UserLayer_top_inst/ControlTransfer_inst/n4597_s11/I2
7.092	0.332	tINS	RR	1	R70C122[2][B]	UserLayer_top_inst/ControlTransfer_inst/n4597_s11/F
7.092	0.000	tNET	RR	1	R70C122[2][B]	UserLayer_top_inst/ControlTransfer_inst/transfer_in_data_mux_36_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.250	6.250					active clock edge time
6.250	0.000					pclk
6.250	0.000	tCL	RR	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.763	1.513	tNET	RR	1	R70C122[2][B]	UserLayer_top_inst/ControlTransfer_inst/transfer_in_data_mux_36_s0/CLK
7.717	-0.046	tSu		1	R70C122[2][B]	UserLayer_top_inst/ControlTransfer_inst/transfer_in_data_mux_36_s0

Path Statistics:

Clock Skew	-0.007
Setup Relationship	6.250
Logic Level	7
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.520, 100.000%
Arrival Data Path Delay	cell: 2.165, 38.863%; route: 3.131, 56.194%; tC2Q: 0.275, 4.943%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.513, 100.000%

Path68

Path Summary:

Slack	0.635
Data Arrival Time	6.957
Data Required Time	7.593
From	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_header_pkt_78_s0
To	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_hp_3_s0
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
1.513	1.513	tNET	RR	1	R27C80[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_header_pkt_78_s0/CLK
1.789	0.275	tC2Q	RR	5	R27C80[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_header_pkt_78_s0/Q
2.070	0.281	tNET	RR	1	R25C82[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3751_s39/I1
2.448	0.379	tINS	RR	1	R25C82[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3751_s39/F
3.529	1.081	tNET	RR	1	R25C83[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3751_s37/I0
3.905	0.375	tINS	RR	2	R25C83[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3751_s37/F
4.896	0.991	tNET	RR	1	R22C83[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3760_s30/I1
5.274	0.379	tINS	RR	1	R22C83[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3760_s30/F
5.276	0.002	tNET	RR	1	R22C83[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3760_s26/I0
5.485	0.209	tINS	RF	2	R22C83[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3760_s26/F
5.492	0.007	tNET	FF	1	R22C83[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3760_s24/I0
5.824	0.332	tINS	FR	1	R22C83[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3760_s24/F
6.211	0.387	tNET	RR	1	R23C86[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3760_s22/I2
6.583	0.372	tINS	RR	2	R23C86[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3760_s22/F
6.957	0.374	tNET	RR	1	R25C85[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_hp_3_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.250	6.250					active clock edge time
6.250	0.000					pclk
6.250	0.000	tCL	RR	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.757	1.507	tNET	RR	1	R25C85[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_hp_3_s0/CLK
7.593	-0.164	tSu		1	R25C85[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_hp_3_s0

Path Statistics:

Clock Skew	-0.007
Setup Relationship	6.250
Logic Level	7
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.513, 100.000%
Arrival Data Path Delay	cell: 2.046, 37.576%; route: 3.123, 57.365%; tC2Q: 0.275, 5.059%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.507, 100.000%

Path69

Path Summary:

Slack	0.661
Data Arrival Time	7.063
Data Required Time	7.724
From	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0
To	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_33_s2
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
1.520	1.520	tNET	RR	1	R2C91[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/CLK
1.795	0.275	tC2Q	RR	2624	R2C91[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/Q
3.714	1.919	tNET	RR	1	R2C92[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_lcmd_25_s8/I2
3.903	0.189	tINS	RR	1	R2C92[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_lcmd_25_s8/F
4.004	0.101	tNET	RR	1	R2C92[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3094_s18/I2
4.383	0.379	tINS	RR	3	R2C92[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3094_s18/F
5.323	0.940	tNET	RR	1	R34C91[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5569_s4/I2
5.512	0.189	tINS	RR	1	R34C91[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5569_s4/F
5.847	0.335	tNET	RR	1	R34C85[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5569_s2/I1
6.036	0.189	tINS	RR	1	R34C85[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5569_s2/F
6.355	0.319	tNET	RR	1	R44C85[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5569_s1/I0
6.734	0.379	tINS	RR	2	R44C85[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5569_s1/F
7.063	0.329	tNET	RR	1	R44C83[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_33_s2/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.250	6.250					active clock edge time
6.250	0.000					pclk
6.250	0.000	tCL	RR	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.770	1.520	tNET	RR	1	R44C83[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_33_s2/CLK
7.724	-0.046	tSu		1	R44C83[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_33_s2

Path Statistics:

Clock Skew	0.000
Setup Relationship	6.250
Logic Level	6
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.520, 100.000%
Arrival Data Path Delay	cell: 1.325, 23.900%; route: 3.943, 71.132%; tC2Q: 0.275, 4.968%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.520, 100.000%

Path70

Path Summary:

Slack	0.661
Data Arrival Time	7.063
Data Required Time	7.724
From	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0
To	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_33_s1
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
1.520	1.520	tNET	RR	1	R2C91[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/CLK
1.795	0.275	tC2Q	RR	2624	R2C91[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/Q
3.714	1.919	tNET	RR	1	R2C92[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_lcmd_25_s8/I2
3.903	0.189	tINS	RR	1	R2C92[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_lcmd_25_s8/F
4.004	0.101	tNET	RR	1	R2C92[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3094_s18/I2
4.383	0.379	tINS	RR	3	R2C92[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3094_s18/F
5.323	0.940	tNET	RR	1	R34C91[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5569_s4/I2
5.512	0.189	tINS	RR	1	R34C91[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5569_s4/F
5.847	0.335	tNET	RR	1	R34C85[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5569_s2/I1
6.036	0.189	tINS	RR	1	R34C85[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5569_s2/F
6.355	0.319	tNET	RR	1	R44C85[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5569_s1/I0
6.734	0.379	tINS	RR	2	R44C85[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5569_s1/F
7.063	0.329	tNET	RR	1	R44C83[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_33_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.250	6.250					active clock edge time
6.250	0.000					pclk
6.250	0.000	tCL	RR	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.770	1.520	tNET	RR	1	R44C83[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_33_s1/CLK
7.724	-0.046	tSu		1	R44C83[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_33_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	6.250
Logic Level	6
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.520, 100.000%
Arrival Data Path Delay	cell: 1.325, 23.900%; route: 3.943, 71.132%; tC2Q: 0.275, 4.968%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.520, 100.000%

Path71

Path Summary:

Slack	0.667
Data Arrival Time	7.051
Data Required Time	7.717
From	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/tx_data_encode_5g_20_s0
To	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_encode_8b10b_4ch/enc3/dout_6_s0
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
1.520	1.520	tNET	RR	1	R70C54[1][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/tx_data_encode_5g_20_s0/CLK
1.795	0.275	tC2Q	RR	27	R70C54[1][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/tx_data_encode_5g_20_s0/Q
2.095	0.300	tNET	RR	1	R71C56[1][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_encode_8b10b_4ch/enc2/b6_4_s18/I1
2.474	0.379	tINS	RR	1	R71C56[1][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_encode_8b10b_4ch/enc2/b6_4_s18/F
2.573	0.099	tNET	RR	1	R71C56[1][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_encode_8b10b_4ch/enc2/b6_4_s16/I3
2.952	0.379	tINS	RR	2	R71C56[1][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_encode_8b10b_4ch/enc2/b6_4_s16/F
3.204	0.252	tNET	RR	1	R71C59[1][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_encode_8b10b_4ch/enc3/b6_4_s8/I0
3.393	0.189	tINS	RR	2	R71C59[1][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_encode_8b10b_4ch/enc3/b6_4_s8/F
3.809	0.416	tNET	RR	1	R71C55[2][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_encode_8b10b_4ch/enc3/b6_4_s5/I2
4.180	0.372	tINS	RR	1	R71C55[2][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_encode_8b10b_4ch/enc3/b6_4_s5/F
4.279	0.099	tNET	RR	1	R71C55[2][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_encode_8b10b_4ch/enc3/b6_4_s2/I0
4.658	0.379	tINS	RR	28	R71C55[2][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_encode_8b10b_4ch/enc3/b6_4_s2/F
5.153	0.495	tNET	RR	1	R72C60[2][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_encode_8b10b_4ch/enc3/b6_5_s2/I3
5.525	0.372	tINS	RR	9	R72C60[2][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_encode_8b10b_4ch/enc3/b6_5_s2/F
5.789	0.264	tNET	RR	1	R71C59[1][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_encode_8b10b_4ch/enc3/b4_3_s36/I3
6.121	0.332	tINS	RR	1	R71C59[1][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_encode_8b10b_4ch/enc3/b4_3_s36/F
6.220	0.099	tNET	RR	1	R71C59[3][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_encode_8b10b_4ch/enc3/b4_3_s33/I3
6.578	0.358	tINS	RR	2	R71C59[3][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_encode_8b10b_4ch/enc3/b4_3_s33/F
6.679	0.101	tNET	RR	1	R71C59[0][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_encode_8b10b_4ch/enc3/b4_3_s32/I3
7.051	0.372	tINS	RR	1	R71C59[0][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_encode_8b10b_4ch/enc3/b4_3_s32/F
7.051	0.000	tNET	RR	1	R71C59[0][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_encode_8b10b_4ch/enc3/dout_6_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.250	6.250					active clock edge time
6.250	0.000					pclk
6.250	0.000	tCL	RR	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.763	1.513	tNET	RR	1	R71C59[0][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_encode_8b10b_4ch/enc3/dout_6_s0/CLK
7.717	-0.046	tSu		1	R71C59[0][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_encode_8b10b_4ch/enc3/dout_6_s0

Path Statistics:

Clock Skew	-0.007
Setup Relationship	6.250
Logic Level	10
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.520, 100.000%
Arrival Data Path Delay	cell: 3.131, 56.615%; route: 2.124, 38.405%; tC2Q: 0.275, 4.980%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.513, 100.000%

Path72

Path Summary:

Slack	0.677
Data Arrival Time	7.659
Data Required Time	8.336
From	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_p132brxgears/skp_head_num_0_s0
To	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_p132brxgears/head_num_latch_0_s0
Launch Clk	q0_lane1_fabric_rx_clk:[R]
Latch Clk	q0_lane1_fabric_rx_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					q0_lane1_fabric_rx_clk
0.000	0.000	tCL	RR	1622	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_RX_O_FABRIC_CLK
2.132	2.132	tNET	RR	1	R44C52[0][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_p132brxgears/skp_head_num_0_s0/CLK
2.407	0.275	tC2Q	RR	42	R44C52[0][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_p132brxgears/skp_head_num_0_s0/Q
3.851	1.444	tNET	RR	1	R40C42[2][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_p132brxgears/n717_s86/I2
4.183	0.332	tINS	RR	1	R40C42[2][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_p132brxgears/n717_s86/F
4.183	0.000	tNET	RR	1	R40C42[2][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_p132brxgears/n717_s80/I1
4.281	0.098	tINS	RR	1	R40C42[2][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_p132brxgears/n717_s80/O
4.281	0.000	tNET	RR	1	R40C42[2][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_p132brxgears/n717_s75/I1
4.343	0.062	tINS	RR	1	R40C42[2][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_p132brxgears/n717_s75/O
4.808	0.464	tNET	RR	1	R41C47[3][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_p132brxgears/n1123_s18/I1
5.017	0.209	tINS	RF	2	R41C47[3][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_p132brxgears/n1123_s18/F
5.359	0.342	tNET	FF	1	R42C51[2][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_p132brxgears/n1127_s6/I3
5.548	0.189	tINS	FR	2	R42C51[2][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_p132brxgears/n1127_s6/F
5.551	0.004	tNET	RR	1	R42C51[2][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_p132brxgears/n1127_s5/I2
5.930	0.379	tINS	RR	2	R42C51[2][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_p132brxgears/n1127_s5/F
6.045	0.115	tNET	RR	1	R42C52[3][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_p132brxgears/n1127_s4/I0
6.421	0.375	tINS	RR	2	R42C52[3][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_p132brxgears/n1127_s4/F
6.521	0.101	tNET	RR	1	R42C52[0][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_p132brxgears/n1127_s2/S0
6.703	0.182	tINS	RR	1	R42C52[0][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_p132brxgears/n1127_s2/O
6.953	0.250	tNET	RR	1	R42C52[1][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_p132brxgears/n1160_s1/I0
7.285	0.332	tINS	RR	1	R42C52[1][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_p132brxgears/n1160_s1/F
7.287	0.002	tNET	RR	1	R42C52[2][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_p132brxgears/n1160_s0/I1
7.659	0.372	tINS	RR	1	R42C52[2][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_p132brxgears/n1160_s0/F
7.659	0.000	tNET	RR	1	R42C52[2][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_p132brxgears/head_num_latch_0_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.250	6.250					active clock edge time
6.250	0.000					q0_lane1_fabric_rx_clk
6.250	0.000	tCL	RR	1622	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_RX_O_FABRIC_CLK
8.382	2.132	tNET	RR	1	R42C52[2][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_p132brxgears/head_num_latch_0_s0/CLK
8.336	-0.046	tSu		1	R42C52[2][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_p132brxgears/head_num_latch_0_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	6.250
Logic Level	9
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.132, 100.000%
Arrival Data Path Delay	cell: 2.530, 45.771%; route: 2.722, 49.247%; tC2Q: 0.275, 4.982%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.132, 100.000%

Path73

Path Summary:

Slack	0.688
Data Arrival Time	6.866
Data Required Time	7.554
From	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0
To	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_17_s1
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
1.520	1.520	tNET	RR	1	R2C91[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/CLK
1.795	0.275	tC2Q	RR	2624	R2C91[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/Q
3.704	1.908	tNET	RR	1	R2C91[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_lcmd_41_s8/I2
4.062	0.358	tINS	RR	1	R2C91[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_lcmd_41_s8/F
4.177	0.115	tNET	RR	1	R2C90[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3078_s17/I2
4.509	0.332	tINS	RR	2	R2C90[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3078_s17/F
5.696	1.186	tNET	RR	1	R39C89[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5585_s1/I2
6.071	0.375	tINS	RR	1	R39C89[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5585_s1/F
6.458	0.387	tNET	RR	1	R42C87[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5585_s0/I0
6.627	0.169	tINS	RF	2	R42C87[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5585_s0/F
6.866	0.238	tNET	FF	1	R40C86[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_17_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.250	6.250					active clock edge time
6.250	0.000					pclk
6.250	0.000	tCL	RR	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.763	1.513	tNET	RR	1	R40C86[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_17_s1/CLK
7.554	-0.210	tSu		1	R40C86[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_17_s1

Path Statistics:

Clock Skew	-0.007
Setup Relationship	6.250
Logic Level	5
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.520, 100.000%
Arrival Data Path Delay	cell: 1.235, 23.100%; route: 3.835, 71.748%; tC2Q: 0.275, 5.152%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.513, 100.000%

Path74

Path Summary:

Slack	0.688
Data Arrival Time	7.641
Data Required Time	8.329
From	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_p132brxgears/skp_head_num_0_s0
To	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_p132brxgears/head_num_latch_add8_1_s0
Launch Clk	q0_lane1_fabric_rx_clk:[R]
Latch Clk	q0_lane1_fabric_rx_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					q0_lane1_fabric_rx_clk
0.000	0.000	tCL	RR	1622	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_RX_O_FABRIC_CLK
2.132	2.132	tNET	RR	1	R44C52[0][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_p132brxgears/skp_head_num_0_s0/CLK
2.407	0.275	tC2Q	RR	42	R44C52[0][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_p132brxgears/skp_head_num_0_s0/Q
3.851	1.444	tNET	RR	1	R40C42[2][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_p132brxgears/n717_s86/I2
4.183	0.332	tINS	RR	1	R40C42[2][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_p132brxgears/n717_s86/F
4.183	0.000	tNET	RR	1	R40C42[2][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_p132brxgears/n717_s80/I1
4.281	0.098	tINS	RR	1	R40C42[2][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_p132brxgears/n717_s80/O
4.281	0.000	tNET	RR	1	R40C42[2][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_p132brxgears/n717_s75/I1
4.343	0.062	tINS	RR	1	R40C42[2][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_p132brxgears/n717_s75/O
4.808	0.464	tNET	RR	1	R41C47[3][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_p132brxgears/n1123_s18/I1
5.017	0.209	tINS	RF	2	R41C47[3][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_p132brxgears/n1123_s18/F
5.359	0.342	tNET	FF	1	R42C51[2][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_p132brxgears/n1127_s6/I3
5.548	0.189	tINS	FR	2	R42C51[2][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_p132brxgears/n1127_s6/F
5.551	0.004	tNET	RR	1	R42C51[2][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_p132brxgears/n1127_s5/I2
5.930	0.379	tINS	RR	2	R42C51[2][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_p132brxgears/n1127_s5/F
6.031	0.101	tNET	RR	1	R42C51[3][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_p132brxgears/n1158_s7/I3
6.406	0.375	tINS	RR	5	R42C51[3][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_p132brxgears/n1158_s7/F
6.662	0.256	tNET	RR	1	R44C50[2][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_p132brxgears/n1163_s1/I1
7.033	0.372	tINS	RR	1	R44C50[2][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_p132brxgears/n1163_s1/F
7.269	0.236	tNET	RR	1	R44C51[0][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_p132brxgears/n1163_s0/I0
7.641	0.372	tINS	RR	1	R44C51[0][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_p132brxgears/n1163_s0/F
7.641	0.000	tNET	RR	1	R44C51[0][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_p132brxgears/head_num_latch_add8_1_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.250	6.250					active clock edge time
6.250	0.000					q0_lane1_fabric_rx_clk
6.250	0.000	tCL	RR	1622	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_RX_O_FABRIC_CLK
8.375	2.125	tNET	RR	1	R44C51[0][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_p132brxgears/head_num_latch_add8_1_s0/CLK
8.329	-0.046	tSu		1	R44C51[0][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_p132brxgears/head_num_latch_add8_1_s0

Path Statistics:

Clock Skew	-0.007
Setup Relationship	6.250
Logic Level	8
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.132, 100.000%
Arrival Data Path Delay	cell: 2.388, 43.339%; route: 2.846, 51.662%; tC2Q: 0.275, 4.999%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.125, 100.000%

Path75

Path Summary:

Slack	0.694
Data Arrival Time	7.023
Data Required Time	7.717
From	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_dpp_length_2_s4
To	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_dpp_22_s1
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
1.513	1.513	tNET	RR	1	R49C98[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_dpp_length_2_s4/CLK
1.789	0.275	tC2Q	RR	9	R49C98[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_dpp_length_2_s4/Q
2.068	0.279	tNET	RR	1	R50C99[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/dpp_crc_append/n1507_s0/I2
2.400	0.332	tINS	RR	5	R50C99[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/dpp_crc_append/n1507_s0/F
2.865	0.465	tNET	RR	1	R44C101[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n4740_s20/I3
3.237	0.372	tINS	RR	5	R44C101[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n4740_s20/F
3.929	0.692	tNET	RR	1	R45C88[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n4740_s18/I1
4.308	0.379	tINS	RR	38	R45C88[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n4740_s18/F
5.056	0.748	tNET	RR	1	R49C82[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n4716_s15/I2
5.427	0.372	tINS	RR	1	R49C82[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n4716_s15/F
5.526	0.099	tNET	RR	1	R49C82[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n4716_s13/I0
5.898	0.372	tINS	RR	1	R49C82[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n4716_s13/F
6.148	0.250	tNET	RR	1	R48C81[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n4716_s19/I2
6.524	0.375	tINS	RR	2	R48C81[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n4716_s19/F
7.023	0.500	tNET	RR	1	R46C80[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_dpp_22_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.250	6.250					active clock edge time
6.250	0.000					pclk
6.250	0.000	tCL	RR	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.763	1.513	tNET	RR	1	R46C80[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_dpp_22_s1/CLK
7.717	-0.046	tSu		1	R46C80[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_dpp_22_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	6.250
Logic Level	7
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.513, 100.000%
Arrival Data Path Delay	cell: 2.201, 39.954%; route: 3.033, 55.047%; tC2Q: 0.275, 4.998%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.513, 100.000%

Path76

Path Summary:

Slack	0.694
Data Arrival Time	7.023
Data Required Time	7.717
From	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_dpp_length_2_s4
To	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_dpp_22_s0
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
1.513	1.513	tNET	RR	1	R49C98[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_dpp_length_2_s4/CLK
1.789	0.275	tC2Q	RR	9	R49C98[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_dpp_length_2_s4/Q
2.068	0.279	tNET	RR	1	R50C99[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/dpp_crc_append/n1507_s0/I2
2.400	0.332	tINS	RR	5	R50C99[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/dpp_crc_append/n1507_s0/F
2.865	0.465	tNET	RR	1	R44C101[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n4740_s20/I3
3.237	0.372	tINS	RR	5	R44C101[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n4740_s20/F
3.929	0.692	tNET	RR	1	R45C88[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n4740_s18/I1
4.308	0.379	tINS	RR	38	R45C88[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n4740_s18/F
5.056	0.748	tNET	RR	1	R49C82[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n4716_s15/I2
5.427	0.372	tINS	RR	1	R49C82[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n4716_s15/F
5.526	0.099	tNET	RR	1	R49C82[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n4716_s13/I0
5.898	0.372	tINS	RR	1	R49C82[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n4716_s13/F
6.148	0.250	tNET	RR	1	R48C81[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n4716_s19/I2
6.524	0.375	tINS	RR	2	R48C81[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n4716_s19/F
7.023	0.500	tNET	RR	1	R46C80[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_dpp_22_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.250	6.250					active clock edge time
6.250	0.000					pclk
6.250	0.000	tCL	RR	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.763	1.513	tNET	RR	1	R46C80[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_dpp_22_s0/CLK
7.717	-0.046	tSu		1	R46C80[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_dpp_22_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	6.250
Logic Level	7
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.513, 100.000%
Arrival Data Path Delay	cell: 2.201, 39.954%; route: 3.033, 55.047%; tC2Q: 0.275, 4.998%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.513, 100.000%

Path77

Path Summary:

Slack	0.715
Data Arrival Time	7.002
Data Required Time	7.717
From	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/state_4_s1
To	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/train_sym_skp_5_s2
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
1.507	1.507	tNET	RR	1	R61C72[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/state_4_s1/CLK
1.771	0.265	tC2Q	RF	64	R61C72[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/state_4_s1/Q
3.883	2.112	tNET	FF	1	R43C70[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_5g/n1753_s33/I2
4.262	0.379	tINS	FR	3	R43C70[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_5g/n1753_s33/F
4.268	0.005	tNET	RR	1	R43C70[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/train_sym_skp_6_s12/I0
4.647	0.379	tINS	RR	13	R43C70[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/train_sym_skp_6_s12/F
5.125	0.479	tNET	RR	1	R42C76[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/train_sym_skp_2_s18/I3
5.501	0.375	tINS	RR	3	R42C76[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/train_sym_skp_2_s18/F
5.643	0.142	tNET	RR	1	R42C77[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/n3852_s29/I2
6.022	0.379	tINS	RR	9	R42C77[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/n3852_s29/F
6.289	0.267	tNET	RR	1	R41C78[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/n3848_s30/I2
6.621	0.332	tINS	RR	1	R41C78[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/n3848_s30/F
6.623	0.002	tNET	RR	1	R41C78[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/n3848_s28/I1
7.002	0.379	tINS	RR	1	R41C78[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/n3848_s28/F
7.002	0.000	tNET	RR	1	R41C78[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/train_sym_skp_5_s2/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.250	6.250					active clock edge time
6.250	0.000					pclk
6.250	0.000	tCL	RR	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.763	1.513	tNET	RR	1	R41C78[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/train_sym_skp_5_s2/CLK
7.717	-0.046	tSu		1	R41C78[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/train_sym_skp_5_s2

Path Statistics:

Clock Skew	0.007
Setup Relationship	6.250
Logic Level	7
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.507, 100.000%
Arrival Data Path Delay	cell: 2.223, 40.452%; route: 3.008, 54.733%; tC2Q: 0.265, 4.815%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.513, 100.000%

Path78

Path Summary:

Slack	0.717
Data Arrival Time	6.876
Data Required Time	7.593
From	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0
To	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_36_s2
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
1.520	1.520	tNET	RR	1	R2C91[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/CLK
1.795	0.275	tC2Q	RR	2624	R2C91[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/Q
3.721	1.926	tNET	RR	1	R2C96[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_lcmd_28_s8/I2
3.910	0.189	tINS	RR	1	R2C96[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_lcmd_28_s8/F
4.026	0.115	tNET	RR	1	R3C96[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3091_s22/I2
4.215	0.189	tINS	RR	3	R3C96[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3091_s22/F
5.213	0.998	tNET	RR	1	R35C92[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5566_s4/I2
5.422	0.209	tINS	RF	1	R35C92[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5566_s4/F
5.784	0.363	tNET	FF	1	R35C85[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5566_s2/I1
6.116	0.332	tINS	FR	1	R35C85[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5566_s2/F
6.396	0.280	tNET	RR	1	R43C85[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5566_s1/I0
6.775	0.379	tINS	RR	2	R43C85[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5566_s1/F
6.876	0.101	tNET	RR	1	R43C85[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_36_s2/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.250	6.250					active clock edge time
6.250	0.000					pclk
6.250	0.000	tCL	RR	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.757	1.507	tNET	RR	1	R43C85[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_36_s2/CLK
7.593	-0.164	tSu		1	R43C85[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_36_s2

Path Statistics:

Clock Skew	-0.014
Setup Relationship	6.250
Logic Level	6
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.520, 100.000%
Arrival Data Path Delay	cell: 1.298, 24.231%; route: 3.783, 70.627%; tC2Q: 0.275, 5.142%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.507, 100.000%

Path79

Path Summary:

Slack	0.723
Data Arrival Time	7.613
Data Required Time	8.336
From	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_p132brxgears/skp_head_num_0_s0
To	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_p132brxgears/head_num_latch_3_s0
Launch Clk	q0_lane1_fabric_rx_clk:[R]
Latch Clk	q0_lane1_fabric_rx_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					q0_lane1_fabric_rx_clk
0.000	0.000	tCL	RR	1622	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_RX_O_FABRIC_CLK
2.132	2.132	tNET	RR	1	R44C52[0][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_p132brxgears/skp_head_num_0_s0/CLK
2.407	0.275	tC2Q	RR	42	R44C52[0][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_p132brxgears/skp_head_num_0_s0/Q
3.851	1.444	tNET	RR	1	R40C42[2][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_p132brxgears/n717_s86/I2
4.183	0.332	tINS	RR	1	R40C42[2][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_p132brxgears/n717_s86/F
4.183	0.000	tNET	RR	1	R40C42[2][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_p132brxgears/n717_s80/I1
4.281	0.098	tINS	RR	1	R40C42[2][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_p132brxgears/n717_s80/O
4.281	0.000	tNET	RR	1	R40C42[2][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_p132brxgears/n717_s75/I1
4.343	0.062	tINS	RR	1	R40C42[2][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_p132brxgears/n717_s75/O
4.808	0.464	tNET	RR	1	R41C47[3][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_p132brxgears/n1123_s18/I1
5.017	0.209	tINS	RF	2	R41C47[3][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_p132brxgears/n1123_s18/F
5.359	0.342	tNET	FF	1	R42C51[2][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_p132brxgears/n1127_s6/I3
5.548	0.189	tINS	FR	2	R42C51[2][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_p132brxgears/n1127_s6/F
5.551	0.004	tNET	RR	1	R42C51[2][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_p132brxgears/n1127_s5/I2
5.930	0.379	tINS	RR	2	R42C51[2][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_p132brxgears/n1127_s5/F
6.031	0.101	tNET	RR	1	R42C51[3][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_p132brxgears/n1158_s7/I3
6.406	0.375	tINS	RR	5	R42C51[3][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_p132brxgears/n1158_s7/F
6.523	0.117	tNET	RR	1	R42C50[3][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_p132brxgears/n1157_s2/I3
6.898	0.375	tINS	RR	1	R42C50[3][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_p132brxgears/n1157_s2/F
6.900	0.002	tNET	RR	1	R42C50[2][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_p132brxgears/n1157_s1/I1
7.232	0.332	tINS	RR	1	R42C50[2][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_p132brxgears/n1157_s1/F
7.234	0.002	tNET	RR	1	R42C50[1][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_p132brxgears/n1157_s0/I2
7.613	0.379	tINS	RR	1	R42C50[1][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_p132brxgears/n1157_s0/F
7.613	0.000	tNET	RR	1	R42C50[1][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_p132brxgears/head_num_latch_3_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.250	6.250					active clock edge time
6.250	0.000					q0_lane1_fabric_rx_clk
6.250	0.000	tCL	RR	1622	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_RX_O_FABRIC_CLK
8.382	2.132	tNET	RR	1	R42C50[1][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_p132brxgears/head_num_latch_3_s0/CLK
8.336	-0.046	tSu		1	R42C50[1][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_p132brxgears/head_num_latch_3_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	6.250
Logic Level	9
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.132, 100.000%
Arrival Data Path Delay	cell: 2.731, 49.815%; route: 2.475, 45.160%; tC2Q: 0.275, 5.024%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.132, 100.000%

Path80

Path Summary:

Slack	0.742
Data Arrival Time	6.982
Data Required Time	7.724
From	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0
To	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_4_s2
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
1.520	1.520	tNET	RR	1	R2C91[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/CLK
1.795	0.275	tC2Q	RR	2624	R2C91[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/Q
3.712	1.917	tNET	RR	1	R3C98[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_lcmd_60_s8/I2
4.071	0.358	tINS	RR	1	R3C98[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_lcmd_60_s8/F
4.171	0.101	tNET	RR	1	R3C98[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3059_s19/I2
4.470	0.299	tINS	RR	2	R3C98[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3059_s19/F
5.701	1.230	tNET	RR	1	R36C89[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5598_s2/I2
5.890	0.189	tINS	RR	1	R36C89[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5598_s2/F
6.306	0.417	tNET	RR	1	R43C87[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5598_s0/I1
6.678	0.372	tINS	RR	2	R43C87[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5598_s0/F
6.982	0.304	tNET	RR	1	R44C87[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_4_s2/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.250	6.250					active clock edge time
6.250	0.000					pclk
6.250	0.000	tCL	RR	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.770	1.520	tNET	RR	1	R44C87[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_4_s2/CLK
7.724	-0.046	tSu		1	R44C87[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_4_s2

Path Statistics:

Clock Skew	0.000
Setup Relationship	6.250
Logic Level	5
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.520, 100.000%
Arrival Data Path Delay	cell: 1.218, 22.294%; route: 3.969, 72.664%; tC2Q: 0.275, 5.042%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.520, 100.000%

Path81

Path Summary:

Slack	0.747
Data Arrival Time	6.964
Data Required Time	7.711
From	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0
To	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_52_s2
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
1.520	1.520	tNET	RR	1	R2C91[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/CLK
1.795	0.275	tC2Q	RR	2624	R2C91[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/Q
3.706	1.910	tNET	RR	1	R20C91[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_lcmd_12_s8/I2
4.005	0.299	tINS	RR	1	R20C91[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_lcmd_12_s8/F
4.105	0.101	tNET	RR	1	R20C91[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3107_s22/I2
4.294	0.189	tINS	RR	3	R20C91[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3107_s22/F
4.873	0.579	tNET	RR	1	R37C92[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5550_s4/I2
5.082	0.209	tINS	RF	1	R37C92[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5550_s4/F
5.463	0.381	tNET	FF	1	R37C83[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5550_s2/I1
5.821	0.358	tINS	FR	1	R37C83[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5550_s2/F
6.129	0.309	tNET	RR	1	R40C83[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5550_s1/I0
6.505	0.375	tINS	RR	2	R40C83[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5550_s1/F
6.964	0.459	tNET	RR	1	R40C81[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_52_s2/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.250	6.250					active clock edge time
6.250	0.000					pclk
6.250	0.000	tCL	RR	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.757	1.507	tNET	RR	1	R40C81[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_52_s2/CLK
7.711	-0.046	tSu		1	R40C81[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_52_s2

Path Statistics:

Clock Skew	-0.014
Setup Relationship	6.250
Logic Level	6
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.520, 100.000%
Arrival Data Path Delay	cell: 1.430, 26.271%; route: 3.738, 68.670%; tC2Q: 0.275, 5.059%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.507, 100.000%

Path82

Path Summary:

Slack	0.747
Data Arrival Time	6.964
Data Required Time	7.711
From	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0
To	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_52_s1
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
1.520	1.520	tNET	RR	1	R2C91[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/CLK
1.795	0.275	tC2Q	RR	2624	R2C91[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/Q
3.706	1.910	tNET	RR	1	R20C91[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_lcmd_12_s8/I2
4.005	0.299	tINS	RR	1	R20C91[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_lcmd_12_s8/F
4.105	0.101	tNET	RR	1	R20C91[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3107_s22/I2
4.294	0.189	tINS	RR	3	R20C91[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3107_s22/F
4.873	0.579	tNET	RR	1	R37C92[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5550_s4/I2
5.082	0.209	tINS	RF	1	R37C92[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5550_s4/F
5.463	0.381	tNET	FF	1	R37C83[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5550_s2/I1
5.821	0.358	tINS	FR	1	R37C83[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5550_s2/F
6.129	0.309	tNET	RR	1	R40C83[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5550_s1/I0
6.505	0.375	tINS	RR	2	R40C83[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5550_s1/F
6.964	0.459	tNET	RR	1	R40C81[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_52_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.250	6.250					active clock edge time
6.250	0.000					pclk
6.250	0.000	tCL	RR	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.757	1.507	tNET	RR	1	R40C81[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_52_s1/CLK
7.711	-0.046	tSu		1	R40C81[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_52_s1

Path Statistics:

Clock Skew	-0.014
Setup Relationship	6.250
Logic Level	6
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.520, 100.000%
Arrival Data Path Delay	cell: 1.430, 26.271%; route: 3.738, 68.670%; tC2Q: 0.275, 5.059%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.507, 100.000%

Path83

Path Summary:

Slack	0.747
Data Arrival Time	6.853
Data Required Time	7.600
From	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/GEN1_DPP_buff/mem_mem_0_0_s
To	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_dpp_30_s1
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
1.520	1.520	tNET	RR	36	BSRAM_R56[19][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/GEN1_DPP_buff/mem_mem_0_0_s/CLKB
2.973	1.453	tC2Q	RF	1	BSRAM_R56[19][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/GEN1_DPP_buff/mem_mem_0_0_s/DO[30]
3.308	0.336	tNET	FF	1	R50C92[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n4708_s14/I0
3.687	0.379	tINS	FR	2	R50C92[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n4708_s14/F
4.103	0.416	tNET	RR	1	R50C87[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n4708_s17/I0
4.475	0.372	tINS	RR	1	R50C87[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n4708_s17/F
4.588	0.113	tNET	RR	1	R50C87[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n4708_s16/I2
4.946	0.358	tINS	RR	1	R50C87[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n4708_s16/F
5.351	0.405	tNET	RR	1	R50C83[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n4708_s15/I1
5.710	0.358	tINS	RR	1	R50C83[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n4708_s15/F
5.841	0.131	tNET	RR	1	R50C83[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n4708_s12/I1
6.216	0.375	tINS	RR	1	R50C83[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n4708_s12/F
6.218	0.002	tNET	RR	1	R50C83[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n4708_s11/I0
6.597	0.379	tINS	RR	2	R50C83[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n4708_s11/F
6.853	0.256	tNET	RR	1	R50C82[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_dpp_30_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.250	6.250					active clock edge time
6.250	0.000					pclk
6.250	0.000	tCL	RR	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.763	1.513	tNET	RR	1	R50C82[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_dpp_30_s1/CLK
7.600	-0.164	tSu		1	R50C82[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_dpp_30_s1

Path Statistics:

Clock Skew	-0.007
Setup Relationship	6.250
Logic Level	7
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.520, 100.000%
Arrival Data Path Delay	cell: 2.221, 41.654%; route: 1.659, 31.105%; tC2Q: 1.453, 27.241%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.513, 100.000%

Path84

Path Summary:

Slack	0.747
Data Arrival Time	6.853
Data Required Time	7.600
From	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/GEN1_DPP_buff/mem_mem_0_0_s
To	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_dpp_30_s0
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
1.520	1.520	tNET	RR	36	BSRAM_R56[19][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/GEN1_DPP_buff/mem_mem_0_0_s/CLKB
2.973	1.453	tC2Q	RF	1	BSRAM_R56[19][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/GEN1_DPP_buff/mem_mem_0_0_s/DO[30]
3.308	0.336	tNET	FF	1	R50C92[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n4708_s14/I0
3.687	0.379	tINS	FR	2	R50C92[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n4708_s14/F
4.103	0.416	tNET	RR	1	R50C87[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n4708_s17/I0
4.475	0.372	tINS	RR	1	R50C87[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n4708_s17/F
4.588	0.113	tNET	RR	1	R50C87[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n4708_s16/I2
4.946	0.358	tINS	RR	1	R50C87[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n4708_s16/F
5.351	0.405	tNET	RR	1	R50C83[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n4708_s15/I1
5.710	0.358	tINS	RR	1	R50C83[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n4708_s15/F
5.841	0.131	tNET	RR	1	R50C83[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n4708_s12/I1
6.216	0.375	tINS	RR	1	R50C83[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n4708_s12/F
6.218	0.002	tNET	RR	1	R50C83[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n4708_s11/I0
6.597	0.379	tINS	RR	2	R50C83[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n4708_s11/F
6.853	0.256	tNET	RR	1	R50C82[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_dpp_30_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.250	6.250					active clock edge time
6.250	0.000					pclk
6.250	0.000	tCL	RR	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.763	1.513	tNET	RR	1	R50C82[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_dpp_30_s0/CLK
7.600	-0.164	tSu		1	R50C82[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_dpp_30_s0

Path Statistics:

Clock Skew	-0.007
Setup Relationship	6.250
Logic Level	7
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.520, 100.000%
Arrival Data Path Delay	cell: 2.221, 41.654%; route: 1.659, 31.105%; tC2Q: 1.453, 27.241%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.513, 100.000%

Path85

Path Summary:

Slack	0.749
Data Arrival Time	6.975
Data Required Time	7.724
From	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0
To	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_28_s2
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
1.520	1.520	tNET	RR	1	R2C91[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/CLK
1.795	0.275	tC2Q	RR	2624	R2C91[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/Q
3.706	1.910	tNET	RR	1	R4C91[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_lcmd_36_s8/I2
3.895	0.189	tINS	RR	1	R4C91[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_lcmd_36_s8/F
3.996	0.101	tNET	RR	1	R4C91[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3083_s18/I2
4.354	0.358	tINS	RR	2	R4C91[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3083_s18/F
5.612	1.258	tNET	RR	1	R39C88[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5574_s1/I2
5.984	0.372	tINS	RR	1	R39C88[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5574_s1/F
6.234	0.250	tNET	RR	1	R42C88[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5574_s0/I0
6.533	0.299	tINS	RR	2	R42C88[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5574_s0/F
6.975	0.443	tNET	RR	1	R43C87[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_28_s2/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.250	6.250					active clock edge time
6.250	0.000					pclk
6.250	0.000	tCL	RR	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.770	1.520	tNET	RR	1	R43C87[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_28_s2/CLK
7.724	-0.046	tSu		1	R43C87[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_28_s2

Path Statistics:

Clock Skew	0.000
Setup Relationship	6.250
Logic Level	5
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.520, 100.000%
Arrival Data Path Delay	cell: 1.218, 22.321%; route: 3.962, 72.631%; tC2Q: 0.275, 5.048%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.520, 100.000%

Path86

Path Summary:

Slack	0.751
Data Arrival Time	6.974
Data Required Time	7.724
From	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0
To	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_28_s1
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
1.520	1.520	tNET	RR	1	R2C91[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/CLK
1.795	0.275	tC2Q	RR	2624	R2C91[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/Q
3.706	1.910	tNET	RR	1	R4C91[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_lcmd_36_s8/I2
3.895	0.189	tINS	RR	1	R4C91[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_lcmd_36_s8/F
3.996	0.101	tNET	RR	1	R4C91[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3083_s18/I2
4.354	0.358	tINS	RR	2	R4C91[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3083_s18/F
5.612	1.258	tNET	RR	1	R39C88[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5574_s1/I2
5.984	0.372	tINS	RR	1	R39C88[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5574_s1/F
6.234	0.250	tNET	RR	1	R42C88[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5574_s0/I0
6.533	0.299	tINS	RR	2	R42C88[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5574_s0/F
6.974	0.441	tNET	RR	1	R43C87[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_28_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.250	6.250					active clock edge time
6.250	0.000					pclk
6.250	0.000	tCL	RR	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.770	1.520	tNET	RR	1	R43C87[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_28_s1/CLK
7.724	-0.046	tSu		1	R43C87[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_28_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	6.250
Logic Level	5
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.520, 100.000%
Arrival Data Path Delay	cell: 1.218, 22.329%; route: 3.960, 72.621%; tC2Q: 0.275, 5.050%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.520, 100.000%

Path87

Path Summary:

Slack	0.754
Data Arrival Time	6.964
Data Required Time	7.717
From	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/dpp_buff_inst/shifter_byte_sel[1]_5_s0
To	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/dpp_buff_inst/shifter[1]_0_s0
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
1.513	1.513	tNET	RR	1	R13C104[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/dpp_buff_inst/shifter_byte_sel[1]_5_s0/CLK
1.789	0.275	tC2Q	RR	4	R13C104[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/dpp_buff_inst/shifter_byte_sel[1]_5_s0/Q
2.480	0.691	tNET	RR	1	R14C103[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/dpp_buff_inst/n1157_s38/I3
2.669	0.189	tINS	RR	2	R14C103[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/dpp_buff_inst/n1157_s38/F
3.058	0.389	tNET	RR	1	R16C102[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/dpp_buff_inst/n1157_s37/I2
3.416	0.358	tINS	RR	2	R16C102[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/dpp_buff_inst/n1157_s37/F
3.420	0.004	tNET	RR	1	R16C102[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/dpp_buff_inst/n1157_s32/I2
3.798	0.379	tINS	RR	9	R16C102[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/dpp_buff_inst/n1157_s32/F
4.451	0.652	tNET	RR	1	R13C103[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/dpp_buff_inst/n1157_s17/I0
4.809	0.358	tINS	RR	8	R13C103[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/dpp_buff_inst/n1157_s17/F
5.423	0.614	tNET	RR	1	R12C105[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/dpp_buff_inst/n1164_s12/I2
5.795	0.372	tINS	RR	1	R12C105[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/dpp_buff_inst/n1164_s12/F
6.585	0.790	tNET	RR	1	R15C106[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/dpp_buff_inst/n1164_s10/I1
6.964	0.379	tINS	RR	1	R15C106[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/dpp_buff_inst/n1164_s10/F
6.964	0.000	tNET	RR	1	R15C106[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/dpp_buff_inst/shifter[1]_0_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.250	6.250					active clock edge time
6.250	0.000					pclk
6.250	0.000	tCL	RR	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.763	1.513	tNET	RR	1	R15C106[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/dpp_buff_inst/shifter[1]_0_s0/CLK
7.717	-0.046	tSu		1	R15C106[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/dpp_buff_inst/shifter[1]_0_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	6.250
Logic Level	7
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.513, 100.000%
Arrival Data Path Delay	cell: 2.035, 37.335%; route: 3.140, 57.612%; tC2Q: 0.275, 5.053%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.513, 100.000%

Path88

Path Summary:

Slack	0.758
Data Arrival Time	6.835
Data Required Time	7.593
From	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_header_pkt_78_s0
To	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_hp_3_s1
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
1.513	1.513	tNET	RR	1	R27C80[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_header_pkt_78_s0/CLK
1.789	0.275	tC2Q	RR	5	R27C80[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_header_pkt_78_s0/Q
2.070	0.281	tNET	RR	1	R25C82[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3751_s39/I1
2.448	0.379	tINS	RR	1	R25C82[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3751_s39/F
3.529	1.081	tNET	RR	1	R25C83[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3751_s37/I0
3.905	0.375	tINS	RR	2	R25C83[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3751_s37/F
4.896	0.991	tNET	RR	1	R22C83[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3760_s30/I1
5.274	0.379	tINS	RR	1	R22C83[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3760_s30/F
5.276	0.002	tNET	RR	1	R22C83[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3760_s26/I0
5.485	0.209	tINS	RF	2	R22C83[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3760_s26/F
5.492	0.007	tNET	FF	1	R22C83[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3760_s24/I0
5.824	0.332	tINS	FR	1	R22C83[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3760_s24/F
6.211	0.387	tNET	RR	1	R23C86[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3760_s22/I2
6.583	0.372	tINS	RR	2	R23C86[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3760_s22/F
6.835	0.252	tNET	RR	1	R24C85[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_hp_3_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.250	6.250					active clock edge time
6.250	0.000					pclk
6.250	0.000	tCL	RR	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.757	1.507	tNET	RR	1	R24C85[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_hp_3_s1/CLK
7.593	-0.164	tSu		1	R24C85[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_hp_3_s1

Path Statistics:

Clock Skew	-0.007
Setup Relationship	6.250
Logic Level	7
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.513, 100.000%
Arrival Data Path Delay	cell: 2.046, 38.441%; route: 3.001, 56.384%; tC2Q: 0.275, 5.175%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.507, 100.000%

Path89

Path Summary:

Slack	0.767
Data Arrival Time	6.772
Data Required Time	7.539
From	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/training_s2
To	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/train_sym_sync_7_s2
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
1.507	1.507	tNET	RR	1	R54C68[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/training_s2/CLK
1.771	0.265	tC2Q	RF	37	R54C68[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/training_s2/Q
3.208	1.437	tNET	FF	1	R35C67[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_5g/train_count_19_s9/I3
3.580	0.372	tINS	FR	5	R35C67[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_5g/train_count_19_s9/F
4.066	0.486	tNET	RR	1	R40C71[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/train_sym_sync_4_s5/I0
4.424	0.358	tINS	RR	3	R40C71[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/train_sym_sync_4_s5/F
5.071	0.647	tNET	RR	1	R43C75[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/train_sym_sync_4_s6/I3
5.443	0.372	tINS	RR	6	R43C75[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/train_sym_sync_4_s6/F
5.722	0.279	tNET	RR	1	R45C77[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/train_sym_sync_15_s4/I0
5.931	0.209	tINS	RF	3	R45C77[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/train_sym_sync_15_s4/F
6.070	0.140	tNET	FF	1	R46C77[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/train_sym_sync_13_s6/I3
6.449	0.379	tINS	FR	9	R46C77[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/train_sym_sync_13_s6/F
6.772	0.323	tNET	RR	1	R48C76[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/train_sym_sync_7_s2/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.250	6.250					active clock edge time
6.250	0.000					pclk
6.250	0.000	tCL	RR	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.763	1.513	tNET	RR	1	R48C76[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/train_sym_sync_7_s2/CLK
7.539	-0.224	tSu		1	R48C76[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/train_sym_sync_7_s2

Path Statistics:

Clock Skew	0.007
Setup Relationship	6.250
Logic Level	6
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.507, 100.000%
Arrival Data Path Delay	cell: 1.689, 32.080%; route: 3.312, 62.895%; tC2Q: 0.265, 5.025%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.513, 100.000%

Path90

Path Summary:

Slack	0.767
Data Arrival Time	6.772
Data Required Time	7.539
From	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/training_s2
To	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/train_sym_sync_8_s2
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
1.507	1.507	tNET	RR	1	R54C68[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/training_s2/CLK
1.771	0.265	tC2Q	RF	37	R54C68[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/training_s2/Q
3.208	1.437	tNET	FF	1	R35C67[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_5g/train_count_19_s9/I3
3.580	0.372	tINS	FR	5	R35C67[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_5g/train_count_19_s9/F
4.066	0.486	tNET	RR	1	R40C71[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/train_sym_sync_4_s5/I0
4.424	0.358	tINS	RR	3	R40C71[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/train_sym_sync_4_s5/F
5.071	0.647	tNET	RR	1	R43C75[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/train_sym_sync_4_s6/I3
5.443	0.372	tINS	RR	6	R43C75[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/train_sym_sync_4_s6/F
5.722	0.279	tNET	RR	1	R45C77[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/train_sym_sync_15_s4/I0
5.931	0.209	tINS	RF	3	R45C77[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/train_sym_sync_15_s4/F
6.070	0.140	tNET	FF	1	R46C77[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/train_sym_sync_13_s6/I3
6.449	0.379	tINS	FR	9	R46C77[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/train_sym_sync_13_s6/F
6.772	0.323	tNET	RR	1	R48C76[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/train_sym_sync_8_s2/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.250	6.250					active clock edge time
6.250	0.000					pclk
6.250	0.000	tCL	RR	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.763	1.513	tNET	RR	1	R48C76[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/train_sym_sync_8_s2/CLK
7.539	-0.224	tSu		1	R48C76[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/train_sym_sync_8_s2

Path Statistics:

Clock Skew	0.007
Setup Relationship	6.250
Logic Level	6
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.507, 100.000%
Arrival Data Path Delay	cell: 1.689, 32.080%; route: 3.312, 62.895%; tC2Q: 0.265, 5.025%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.513, 100.000%

Path91

Path Summary:

Slack	0.774
Data Arrival Time	6.758
Data Required Time	7.532
From	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/training_s2
To	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/train_sym_sync_5_s2
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
1.507	1.507	tNET	RR	1	R54C68[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/training_s2/CLK
1.771	0.265	tC2Q	RF	37	R54C68[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/training_s2/Q
3.208	1.437	tNET	FF	1	R35C67[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_5g/train_count_19_s9/I3
3.580	0.372	tINS	FR	5	R35C67[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_5g/train_count_19_s9/F
4.066	0.486	tNET	RR	1	R40C71[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/train_sym_sync_4_s5/I0
4.424	0.358	tINS	RR	3	R40C71[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/train_sym_sync_4_s5/F
5.071	0.647	tNET	RR	1	R43C75[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/train_sym_sync_4_s6/I3
5.443	0.372	tINS	RR	6	R43C75[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/train_sym_sync_4_s6/F
5.722	0.279	tNET	RR	1	R45C77[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/train_sym_sync_15_s4/I0
5.931	0.209	tINS	RF	3	R45C77[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/train_sym_sync_15_s4/F
6.070	0.140	tNET	FF	1	R46C77[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/train_sym_sync_13_s6/I3
6.449	0.379	tINS	FR	9	R46C77[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/train_sym_sync_13_s6/F
6.758	0.309	tNET	RR	1	R48C77[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/train_sym_sync_5_s2/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.250	6.250					active clock edge time
6.250	0.000					pclk
6.250	0.000	tCL	RR	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.757	1.507	tNET	RR	1	R48C77[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/train_sym_sync_5_s2/CLK
7.532	-0.224	tSu		1	R48C77[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/train_sym_sync_5_s2

Path Statistics:

Clock Skew	0.000
Setup Relationship	6.250
Logic Level	6
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.507, 100.000%
Arrival Data Path Delay	cell: 1.689, 32.168%; route: 3.298, 62.793%; tC2Q: 0.265, 5.039%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.507, 100.000%

Path92

Path Summary:

Slack	0.774
Data Arrival Time	6.758
Data Required Time	7.532
From	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/training_s2
To	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/train_sym_sync_6_s2
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
1.507	1.507	tNET	RR	1	R54C68[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/training_s2/CLK
1.771	0.265	tC2Q	RF	37	R54C68[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/training_s2/Q
3.208	1.437	tNET	FF	1	R35C67[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_5g/train_count_19_s9/I3
3.580	0.372	tINS	FR	5	R35C67[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_5g/train_count_19_s9/F
4.066	0.486	tNET	RR	1	R40C71[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/train_sym_sync_4_s5/I0
4.424	0.358	tINS	RR	3	R40C71[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/train_sym_sync_4_s5/F
5.071	0.647	tNET	RR	1	R43C75[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/train_sym_sync_4_s6/I3
5.443	0.372	tINS	RR	6	R43C75[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/train_sym_sync_4_s6/F
5.722	0.279	tNET	RR	1	R45C77[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/train_sym_sync_15_s4/I0
5.931	0.209	tINS	RF	3	R45C77[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/train_sym_sync_15_s4/F
6.070	0.140	tNET	FF	1	R46C77[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/train_sym_sync_13_s6/I3
6.449	0.379	tINS	FR	9	R46C77[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/train_sym_sync_13_s6/F
6.758	0.309	tNET	RR	1	R48C77[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/train_sym_sync_6_s2/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.250	6.250					active clock edge time
6.250	0.000					pclk
6.250	0.000	tCL	RR	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.757	1.507	tNET	RR	1	R48C77[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/train_sym_sync_6_s2/CLK
7.532	-0.224	tSu		1	R48C77[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/train_sym_sync_6_s2

Path Statistics:

Clock Skew	0.000
Setup Relationship	6.250
Logic Level	6
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.507, 100.000%
Arrival Data Path Delay	cell: 1.689, 32.168%; route: 3.298, 62.793%; tC2Q: 0.265, 5.039%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.507, 100.000%

Path93

Path Summary:

Slack	0.796
Data Arrival Time	6.922
Data Required Time	7.717
From	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/state_4_s1
To	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/train_sym_skp_4_s2
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
1.507	1.507	tNET	RR	1	R61C72[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/state_4_s1/CLK
1.771	0.265	tC2Q	RF	64	R61C72[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/state_4_s1/Q
3.883	2.112	tNET	FF	1	R43C70[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_5g/n1753_s33/I2
4.262	0.379	tINS	FR	3	R43C70[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_5g/n1753_s33/F
4.268	0.005	tNET	RR	1	R43C70[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/train_sym_skp_6_s12/I0
4.647	0.379	tINS	RR	13	R43C70[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/train_sym_skp_6_s12/F
5.125	0.479	tNET	RR	1	R42C76[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/train_sym_skp_2_s18/I3
5.501	0.375	tINS	RR	3	R42C76[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/train_sym_skp_2_s18/F
5.643	0.142	tNET	RR	1	R42C77[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/n3852_s29/I2
6.022	0.379	tINS	RR	9	R42C77[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/n3852_s29/F
6.289	0.267	tNET	RR	1	R41C78[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/n3850_s29/I2
6.588	0.299	tINS	RR	1	R41C78[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/n3850_s29/F
6.590	0.002	tNET	RR	1	R41C78[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/n3850_s28/I3
6.922	0.332	tINS	RR	1	R41C78[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/n3850_s28/F
6.922	0.000	tNET	RR	1	R41C78[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/train_sym_skp_4_s2/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.250	6.250					active clock edge time
6.250	0.000					pclk
6.250	0.000	tCL	RR	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.763	1.513	tNET	RR	1	R41C78[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/train_sym_skp_4_s2/CLK
7.717	-0.046	tSu		1	R41C78[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/train_sym_skp_4_s2

Path Statistics:

Clock Skew	0.007
Setup Relationship	6.250
Logic Level	7
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.507, 100.000%
Arrival Data Path Delay	cell: 2.143, 39.571%; route: 3.008, 55.543%; tC2Q: 0.265, 4.886%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.513, 100.000%

Path94

Path Summary:

Slack	0.800
Data Arrival Time	6.925
Data Required Time	7.724
From	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/dpp_buff_inst/shifter_byte_sel[15]_0_s0
To	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/dpp_buff_inst/shifter[15]_0_s0
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
1.520	1.520	tNET	RR	1	R12C111[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/dpp_buff_inst/shifter_byte_sel[15]_0_s0/CLK
1.795	0.275	tC2Q	RR	4	R12C111[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/dpp_buff_inst/shifter_byte_sel[15]_0_s0/Q
2.049	0.254	tNET	RR	1	R13C112[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/dpp_buff_inst/n2641_s38/I0
2.421	0.372	tINS	RR	2	R13C112[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/dpp_buff_inst/n2641_s38/F
2.785	0.364	tNET	RR	1	R13C106[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/dpp_buff_inst/n2641_s37/I2
3.117	0.332	tINS	RR	2	R13C106[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/dpp_buff_inst/n2641_s37/F
3.232	0.115	tNET	RR	1	R14C106[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/dpp_buff_inst/n2641_s33/I2
3.611	0.379	tINS	RR	9	R14C106[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/dpp_buff_inst/n2641_s33/F
4.193	0.582	tNET	RR	1	R13C113[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/dpp_buff_inst/n2641_s17/I1
4.565	0.372	tINS	RR	8	R13C113[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/dpp_buff_inst/n2641_s17/F
5.335	0.770	tNET	RR	1	R13C105[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/dpp_buff_inst/n2648_s12/I2
5.710	0.375	tINS	RR	1	R13C105[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/dpp_buff_inst/n2648_s12/F
6.553	0.842	tNET	RR	1	R12C119[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/dpp_buff_inst/n2648_s10/I1
6.925	0.372	tINS	RR	1	R12C119[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/dpp_buff_inst/n2648_s10/F
6.925	0.000	tNET	RR	1	R12C119[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/dpp_buff_inst/shifter[15]_0_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.250	6.250					active clock edge time
6.250	0.000					pclk
6.250	0.000	tCL	RR	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.770	1.520	tNET	RR	1	R12C119[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/dpp_buff_inst/shifter[15]_0_s0/CLK
7.724	-0.046	tSu		1	R12C119[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/dpp_buff_inst/shifter[15]_0_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	6.250
Logic Level	7
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.520, 100.000%
Arrival Data Path Delay	cell: 2.201, 40.733%; route: 2.928, 54.172%; tC2Q: 0.275, 5.096%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.520, 100.000%

Path95

Path Summary:

Slack	0.813
Data Arrival Time	7.267
Data Required Time	8.081
From	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/state_4_s1
To	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_5g/state_0_s0
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
1.507	1.507	tNET	RR	1	R61C72[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/state_4_s1/CLK
1.771	0.265	tC2Q	RF	64	R61C72[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/state_4_s1/Q
3.883	2.112	tNET	FF	1	R43C70[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_5g/n1753_s33/I2
4.262	0.379	tINS	FR	3	R43C70[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_5g/n1753_s33/F
4.268	0.005	tNET	RR	1	R43C70[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/train_sym_skp_6_s12/I0
4.647	0.379	tINS	RR	13	R43C70[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/train_sym_skp_6_s12/F
5.320	0.673	tNET	RR	1	R34C63[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_5g/n1760_s31/I2
5.692	0.372	tINS	RR	2	R34C63[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_5g/n1760_s31/F
5.792	0.101	tNET	RR	1	R34C63[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_5g/n1765_s34/I3
6.168	0.375	tINS	RR	1	R34C63[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_5g/n1765_s34/F
6.418	0.250	tNET	RR	1	R33C62[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_5g/n1765_s31/I0
6.790	0.372	tINS	RR	1	R33C62[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_5g/n1765_s31/F
6.889	0.099	tNET	RR	1	R33C62[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_5g/n1765_s29/I1
7.267	0.379	tINS	RR	1	R33C62[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_5g/n1765_s29/F
7.267	0.000	tNET	RR	1	R33C62[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_5g/state_0_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.250	6.250					active clock edge time
6.250	0.000					pclk
6.250	0.000	tCL	RR	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
8.127	1.876	tNET	RR	1	R33C62[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_5g/state_0_s0/CLK
8.081	-0.046	tSu		1	R33C62[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_5g/state_0_s0

Path Statistics:

Clock Skew	0.370
Setup Relationship	6.250
Logic Level	7
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.507, 100.000%
Arrival Data Path Delay	cell: 2.255, 39.150%; route: 3.241, 56.257%; tC2Q: 0.265, 4.593%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.876, 100.000%

Path96

Path Summary:

Slack	0.825
Data Arrival Time	6.714
Data Required Time	7.539
From	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/training_s2
To	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/train_sym_sync_13_s2
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
1.507	1.507	tNET	RR	1	R54C68[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/training_s2/CLK
1.771	0.265	tC2Q	RF	37	R54C68[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/training_s2/Q
3.208	1.437	tNET	FF	1	R35C67[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_5g/train_count_19_s9/I3
3.580	0.372	tINS	FR	5	R35C67[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_5g/train_count_19_s9/F
4.066	0.486	tNET	RR	1	R40C71[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/train_sym_sync_4_s5/I0
4.424	0.358	tINS	RR	3	R40C71[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/train_sym_sync_4_s5/F
5.071	0.647	tNET	RR	1	R43C75[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/train_sym_sync_4_s6/I3
5.443	0.372	tINS	RR	6	R43C75[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/train_sym_sync_4_s6/F
5.722	0.279	tNET	RR	1	R45C77[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/train_sym_sync_15_s4/I0
5.931	0.209	tINS	RF	3	R45C77[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/train_sym_sync_15_s4/F
6.070	0.140	tNET	FF	1	R46C77[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/train_sym_sync_13_s6/I3
6.449	0.379	tINS	FR	9	R46C77[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/train_sym_sync_13_s6/F
6.714	0.265	tNET	RR	1	R45C78[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/train_sym_sync_13_s2/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.250	6.250					active clock edge time
6.250	0.000					pclk
6.250	0.000	tCL	RR	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.763	1.513	tNET	RR	1	R45C78[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/train_sym_sync_13_s2/CLK
7.539	-0.224	tSu		1	R45C78[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/train_sym_sync_13_s2

Path Statistics:

Clock Skew	0.007
Setup Relationship	6.250
Logic Level	6
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.507, 100.000%
Arrival Data Path Delay	cell: 1.689, 32.440%; route: 3.253, 62.478%; tC2Q: 0.265, 5.081%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.513, 100.000%

Path97

Path Summary:

Slack	0.831
Data Arrival Time	6.880
Data Required Time	7.711
From	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/state_4_s1
To	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/train_sym_skp_7_s2
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
1.507	1.507	tNET	RR	1	R61C72[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/state_4_s1/CLK
1.771	0.265	tC2Q	RF	64	R61C72[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/state_4_s1/Q
3.883	2.112	tNET	FF	1	R43C70[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_5g/n1753_s33/I2
4.262	0.379	tINS	FR	3	R43C70[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_5g/n1753_s33/F
4.379	0.117	tNET	RR	1	R43C71[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/n3690_s45/I1
4.751	0.372	tINS	RR	5	R43C71[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/n3690_s45/F
4.895	0.144	tNET	RR	1	R43C73[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/n3898_s14/I2
5.104	0.209	tINS	RF	5	R43C73[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/n3898_s14/F
5.558	0.454	tNET	FF	1	R41C76[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/n3844_s39/I0
5.917	0.358	tINS	FR	1	R41C76[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/n3844_s39/F
6.030	0.113	tNET	RR	1	R41C77[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/n3844_s36/I3
6.402	0.372	tINS	RR	1	R41C77[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/n3844_s36/F
6.501	0.099	tNET	RR	1	R41C77[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/n3844_s33/I3
6.880	0.379	tINS	RR	1	R41C77[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/n3844_s33/F
6.880	0.000	tNET	RR	1	R41C77[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/train_sym_skp_7_s2/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.250	6.250					active clock edge time
6.250	0.000					pclk
6.250	0.000	tCL	RR	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.757	1.507	tNET	RR	1	R41C77[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/train_sym_skp_7_s2/CLK
7.711	-0.046	tSu		1	R41C77[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/train_sym_skp_7_s2

Path Statistics:

Clock Skew	0.000
Setup Relationship	6.250
Logic Level	7
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.507, 100.000%
Arrival Data Path Delay	cell: 2.068, 38.492%; route: 3.040, 56.583%; tC2Q: 0.265, 4.925%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.507, 100.000%

Path98

Path Summary:

Slack	0.833
Data Arrival Time	6.891
Data Required Time	7.724
From	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_dpp_length_2_s4
To	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_dpp_11_s1
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
1.513	1.513	tNET	RR	1	R49C98[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_dpp_length_2_s4/CLK
1.789	0.275	tC2Q	RR	9	R49C98[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_dpp_length_2_s4/Q
2.068	0.279	tNET	RR	1	R50C99[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/dpp_crc_append/n1507_s0/I2
2.400	0.332	tINS	RR	5	R50C99[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/dpp_crc_append/n1507_s0/F
2.865	0.465	tNET	RR	1	R44C101[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n4740_s20/I3
3.237	0.372	tINS	RR	5	R44C101[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n4740_s20/F
3.929	0.692	tNET	RR	1	R45C88[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n4740_s18/I1
4.308	0.379	tINS	RR	38	R45C88[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n4740_s18/F
5.194	0.887	tNET	RR	1	R50C82[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n4727_s14/I2
5.573	0.379	tINS	RR	1	R50C82[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n4727_s14/F
5.687	0.113	tNET	RR	1	R50C81[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n4727_s12/I0
6.019	0.332	tINS	RR	1	R50C81[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n4727_s12/F
6.269	0.250	tNET	RR	1	R50C79[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n4727_s18/I2
6.601	0.332	tINS	RR	2	R50C79[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n4727_s18/F
6.891	0.290	tNET	RR	1	R50C79[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_dpp_11_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.250	6.250					active clock edge time
6.250	0.000					pclk
6.250	0.000	tCL	RR	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.770	1.520	tNET	RR	1	R50C79[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_dpp_11_s1/CLK
7.724	-0.046	tSu		1	R50C79[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_dpp_11_s1

Path Statistics:

Clock Skew	0.007
Setup Relationship	6.250
Logic Level	7
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.513, 100.000%
Arrival Data Path Delay	cell: 2.126, 39.531%; route: 2.976, 55.347%; tC2Q: 0.275, 5.121%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.520, 100.000%

Path99

Path Summary:

Slack	0.833
Data Arrival Time	6.891
Data Required Time	7.724
From	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_dpp_length_2_s4
To	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_dpp_11_s0
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
1.513	1.513	tNET	RR	1	R49C98[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_dpp_length_2_s4/CLK
1.789	0.275	tC2Q	RR	9	R49C98[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_dpp_length_2_s4/Q
2.068	0.279	tNET	RR	1	R50C99[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/dpp_crc_append/n1507_s0/I2
2.400	0.332	tINS	RR	5	R50C99[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/dpp_crc_append/n1507_s0/F
2.865	0.465	tNET	RR	1	R44C101[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n4740_s20/I3
3.237	0.372	tINS	RR	5	R44C101[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n4740_s20/F
3.929	0.692	tNET	RR	1	R45C88[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n4740_s18/I1
4.308	0.379	tINS	RR	38	R45C88[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n4740_s18/F
5.194	0.887	tNET	RR	1	R50C82[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n4727_s14/I2
5.573	0.379	tINS	RR	1	R50C82[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n4727_s14/F
5.687	0.113	tNET	RR	1	R50C81[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n4727_s12/I0
6.019	0.332	tINS	RR	1	R50C81[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n4727_s12/F
6.269	0.250	tNET	RR	1	R50C79[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n4727_s18/I2
6.601	0.332	tINS	RR	2	R50C79[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n4727_s18/F
6.891	0.290	tNET	RR	1	R50C79[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_dpp_11_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.250	6.250					active clock edge time
6.250	0.000					pclk
6.250	0.000	tCL	RR	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.770	1.520	tNET	RR	1	R50C79[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_dpp_11_s0/CLK
7.724	-0.046	tSu		1	R50C79[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_dpp_11_s0

Path Statistics:

Clock Skew	0.007
Setup Relationship	6.250
Logic Level	7
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.513, 100.000%
Arrival Data Path Delay	cell: 2.126, 39.531%; route: 2.976, 55.347%; tC2Q: 0.275, 5.121%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.520, 100.000%

Path100

Path Summary:

Slack	0.835
Data Arrival Time	6.889
Data Required Time	7.724
From	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_dpp_length_2_s4
To	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_dpp_4_s1
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
1.513	1.513	tNET	RR	1	R49C98[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_dpp_length_2_s4/CLK
1.789	0.275	tC2Q	RR	9	R49C98[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_dpp_length_2_s4/Q
2.068	0.279	tNET	RR	1	R50C99[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/dpp_crc_append/n1507_s0/I2
2.400	0.332	tINS	RR	5	R50C99[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/dpp_crc_append/n1507_s0/F
2.865	0.465	tNET	RR	1	R44C101[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n4740_s20/I3
3.237	0.372	tINS	RR	5	R44C101[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n4740_s20/F
3.929	0.692	tNET	RR	1	R45C88[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n4740_s18/I1
4.308	0.379	tINS	RR	38	R45C88[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n4740_s18/F
5.194	0.887	tNET	RR	1	R51C82[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n4734_s14/I2
5.553	0.358	tINS	RR	1	R51C82[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n4734_s14/F
5.788	0.236	tNET	RR	1	R51C81[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n4734_s12/I0
6.120	0.332	tINS	RR	1	R51C81[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n4734_s12/F
6.234	0.113	tNET	RR	1	R50C81[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n4734_s18/I2
6.423	0.189	tINS	RR	2	R50C81[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n4734_s18/F
6.889	0.466	tNET	RR	1	R48C79[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_dpp_4_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.250	6.250					active clock edge time
6.250	0.000					pclk
6.250	0.000	tCL	RR	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.770	1.520	tNET	RR	1	R48C79[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_dpp_4_s1/CLK
7.724	-0.046	tSu		1	R48C79[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_dpp_4_s1

Path Statistics:

Clock Skew	0.007
Setup Relationship	6.250
Logic Level	7
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.513, 100.000%
Arrival Data Path Delay	cell: 1.962, 36.498%; route: 3.138, 58.379%; tC2Q: 0.275, 5.123%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.520, 100.000%

Hold Analysis Report

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	0.038
Data Arrival Time	0.856
Data Required Time	0.818
From	DDR3_Memory_Interface_Top_inst/gw3_top/u_gwmc_top/gw_wr_data0/wr_buf_din_66_s0
To	DDR3_Memory_Interface_Top_inst/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_1_s
Launch Clk	dma_clk:[R]
Latch Clk	dma_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					dma_clk
0.000	0.000	tCL	RR	3995	BOTTOMSIDE[0]	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.602	0.602	tNET	RR	1	R39C19[0][B]	DDR3_Memory_Interface_Top_inst/gw3_top/u_gwmc_top/gw_wr_data0/wr_buf_din_66_s0/CLK
0.732	0.130	tC2Q	RR	1	R39C19[0][B]	DDR3_Memory_Interface_Top_inst/gw3_top/u_gwmc_top/gw_wr_data0/wr_buf_din_66_s0/Q
0.856	0.124	tNET	RR	1	BSRAM_R38[2][B]	DDR3_Memory_Interface_Top_inst/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_1_s/DI[30]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					dma_clk
0.000	0.000	tCL	RR	3995	BOTTOMSIDE[0]	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.787	0.787	tNET	RR	1	BSRAM_R38[2][B]	DDR3_Memory_Interface_Top_inst/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_1_s/CLKA
0.818	0.032	tHld		1	BSRAM_R38[2][B]	DDR3_Memory_Interface_Top_inst/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_1_s

Path Statistics:

Clock Skew	0.184
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.602, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.124, 48.936%; tC2Q: 0.130, 51.064%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.787, 100.000%

Path2

Path Summary:

Slack	0.038
Data Arrival Time	0.856
Data Required Time	0.818
From	DDR3_Memory_Interface_Top_inst/gw3_top/u_gwmc_top/gw_wr_data0/wr_buf_din_65_s0
To	DDR3_Memory_Interface_Top_inst/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_1_s
Launch Clk	dma_clk:[R]
Latch Clk	dma_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					dma_clk
0.000	0.000	tCL	RR	3995	BOTTOMSIDE[0]	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.602	0.602	tNET	RR	1	R39C19[1][B]	DDR3_Memory_Interface_Top_inst/gw3_top/u_gwmc_top/gw_wr_data0/wr_buf_din_65_s0/CLK
0.732	0.130	tC2Q	RR	1	R39C19[1][B]	DDR3_Memory_Interface_Top_inst/gw3_top/u_gwmc_top/gw_wr_data0/wr_buf_din_65_s0/Q
0.856	0.124	tNET	RR	1	BSRAM_R38[2][B]	DDR3_Memory_Interface_Top_inst/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_1_s/DI[29]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					dma_clk
0.000	0.000	tCL	RR	3995	BOTTOMSIDE[0]	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.787	0.787	tNET	RR	1	BSRAM_R38[2][B]	DDR3_Memory_Interface_Top_inst/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_1_s/CLKA
0.818	0.032	tHld		1	BSRAM_R38[2][B]	DDR3_Memory_Interface_Top_inst/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_1_s

Path Statistics:

Clock Skew	0.184
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.602, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.124, 48.936%; tC2Q: 0.130, 51.064%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.787, 100.000%

Path3

Path Summary:

Slack	0.043
Data Arrival Time	1.174
Data Required Time	1.130
From	u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_data_19_s0
To	u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.mem_Big.mem_0_2_s
Launch Clk	rgb_clk:[R]
Latch Clk	rgb_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rgb_clk
0.000	0.000	tCL	RR	431	PLL_L[1]	Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
0.920	0.920	tNET	RR	1	R40C14[1][A]	u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_data_19_s0/CLK
1.049	0.130	tC2Q	RR	1	R40C14[1][A]	u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_data_19_s0/Q
1.174	0.124	tNET	RR	1	BSRAM_R38[2][A]	u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.mem_Big.mem_0_2_s/DI[3]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rgb_clk
0.000	0.000	tCL	RR	431	PLL_L[1]	Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
1.097	1.097	tNET	RR	1	BSRAM_R38[2][A]	u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.mem_Big.mem_0_2_s/CLKA
1.130	0.033	tHld		1	BSRAM_R38[2][A]	u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.mem_Big.mem_0_2_s

Path Statistics:

Clock Skew	0.177
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.920, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.124, 48.936%; tC2Q: 0.130, 51.064%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.097, 100.000%

Path4

Path Summary:

Slack	0.043
Data Arrival Time	1.177
Data Required Time	1.134
From	u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_data_35_s0
To	u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.mem_Big.mem_0_4_s
Launch Clk	rgb_clk:[R]
Latch Clk	rgb_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rgb_clk
0.000	0.000	tCL	RR	431	PLL_L[1]	Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
0.923	0.923	tNET	RR	1	R39C11[2][A]	u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_data_35_s0/CLK
1.053	0.130	tC2Q	RR	1	R39C11[2][A]	u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_data_35_s0/Q
1.177	0.124	tNET	RR	1	BSRAM_R38[1]	u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.mem_Big.mem_0_4_s/DI[3]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rgb_clk
0.000	0.000	tCL	RR	431	PLL_L[1]	Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
1.101	1.101	tNET	RR	1	BSRAM_R38[1]	u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.mem_Big.mem_0_4_s/CLKA
1.134	0.033	tHld		1	BSRAM_R38[1]	u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.mem_Big.mem_0_4_s

Path Statistics:

Clock Skew	0.177
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.923, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.124, 48.936%; tC2Q: 0.130, 51.064%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.101, 100.000%

Path5

Path Summary:

Slack	0.043
Data Arrival Time	0.859
Data Required Time	0.816
From	DDR3_Memory_Interface_Top_inst/gw3_top/u_gwmc_top/gw_wr_data0/wr_buf_din_75_s0
To	DDR3_Memory_Interface_Top_inst/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_2_s
Launch Clk	dma_clk:[R]
Latch Clk	dma_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					dma_clk
0.000	0.000	tCL	RR	3995	BOTTOMSIDE[0]	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.606	0.606	tNET	RR	1	R39C20[1][A]	DDR3_Memory_Interface_Top_inst/gw3_top/u_gwmc_top/gw_wr_data0/wr_buf_din_75_s0/CLK
0.735	0.130	tC2Q	RR	1	R39C20[1][A]	DDR3_Memory_Interface_Top_inst/gw3_top/u_gwmc_top/gw_wr_data0/wr_buf_din_75_s0/Q
0.859	0.124	tNET	RR	1	BSRAM_R38[3]	DDR3_Memory_Interface_Top_inst/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_2_s/DI[3]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					dma_clk
0.000	0.000	tCL	RR	3995	BOTTOMSIDE[0]	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.783	0.783	tNET	RR	1	BSRAM_R38[3]	DDR3_Memory_Interface_Top_inst/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_2_s/CLKA
0.816	0.033	tHld		1	BSRAM_R38[3]	DDR3_Memory_Interface_Top_inst/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_2_s

Path Statistics:

Clock Skew	0.177
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.606, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.124, 48.936%; tC2Q: 0.130, 51.064%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.783, 100.000%

Path6

Path Summary:

Slack	0.043
Data Arrival Time	0.863
Data Required Time	0.820
From	DDR3_Memory_Interface_Top_inst/gw3_top/u_gwmc_top/gw_wr_data0/wr_buf_din_42_s0
To	DDR3_Memory_Interface_Top_inst/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_1_s
Launch Clk	dma_clk:[R]
Latch Clk	dma_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					dma_clk
0.000	0.000	tCL	RR	3995	BOTTOMSIDE[0]	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.609	0.609	tNET	RR	1	R39C17[3][A]	DDR3_Memory_Interface_Top_inst/gw3_top/u_gwmc_top/gw_wr_data0/wr_buf_din_42_s0/CLK
0.739	0.130	tC2Q	RR	1	R39C17[3][A]	DDR3_Memory_Interface_Top_inst/gw3_top/u_gwmc_top/gw_wr_data0/wr_buf_din_42_s0/Q
0.863	0.124	tNET	RR	1	BSRAM_R38[2][B]	DDR3_Memory_Interface_Top_inst/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_1_s/DI[6]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					dma_clk
0.000	0.000	tCL	RR	3995	BOTTOMSIDE[0]	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.787	0.787	tNET	RR	1	BSRAM_R38[2][B]	DDR3_Memory_Interface_Top_inst/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_1_s/CLKA
0.820	0.033	tHld		1	BSRAM_R38[2][B]	DDR3_Memory_Interface_Top_inst/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_1_s

Path Statistics:

Clock Skew	0.177
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.609, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.124, 48.936%; tC2Q: 0.130, 51.064%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.787, 100.000%

Path7

Path Summary:

Slack	0.047
Data Arrival Time	0.863
Data Required Time	0.816
From	DDR3_Memory_Interface_Top_inst/gw3_top/u_gwmc_top/gw_wr_data0/wr_buf_din_89_s0
To	DDR3_Memory_Interface_Top_inst/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_2_s
Launch Clk	dma_clk:[R]
Latch Clk	dma_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					dma_clk
0.000	0.000	tCL	RR	3995	BOTTOMSIDE[0]	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.609	0.609	tNET	RR	1	R39C21[1][A]	DDR3_Memory_Interface_Top_inst/gw3_top/u_gwmc_top/gw_wr_data0/wr_buf_din_89_s0/CLK
0.739	0.130	tC2Q	RR	1	R39C21[1][A]	DDR3_Memory_Interface_Top_inst/gw3_top/u_gwmc_top/gw_wr_data0/wr_buf_din_89_s0/Q
0.863	0.124	tNET	RR	1	BSRAM_R38[3]	DDR3_Memory_Interface_Top_inst/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_2_s/DI[17]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					dma_clk
0.000	0.000	tCL	RR	3995	BOTTOMSIDE[0]	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.783	0.783	tNET	RR	1	BSRAM_R38[3]	DDR3_Memory_Interface_Top_inst/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_2_s/CLKA
0.816	0.033	tHld		1	BSRAM_R38[3]	DDR3_Memory_Interface_Top_inst/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_2_s

Path Statistics:

Clock Skew	0.174
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.609, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.124, 48.936%; tC2Q: 0.130, 51.064%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.783, 100.000%

Path8

Path Summary:

Slack	0.049
Data Arrival Time	0.863
Data Required Time	0.814
From	DDR3_Memory_Interface_Top_inst/gw3_top/u_gwmc_top/gw_wr_data0/wr_buf_din_92_s0
To	DDR3_Memory_Interface_Top_inst/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_2_s
Launch Clk	dma_clk:[R]
Latch Clk	dma_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					dma_clk
0.000	0.000	tCL	RR	3995	BOTTOMSIDE[0]	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.609	0.609	tNET	RR	1	R39C21[2][B]	DDR3_Memory_Interface_Top_inst/gw3_top/u_gwmc_top/gw_wr_data0/wr_buf_din_92_s0/CLK
0.739	0.130	tC2Q	RR	1	R39C21[2][B]	DDR3_Memory_Interface_Top_inst/gw3_top/u_gwmc_top/gw_wr_data0/wr_buf_din_92_s0/Q
0.863	0.124	tNET	RR	1	BSRAM_R38[3]	DDR3_Memory_Interface_Top_inst/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_2_s/DI[20]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					dma_clk
0.000	0.000	tCL	RR	3995	BOTTOMSIDE[0]	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.783	0.783	tNET	RR	1	BSRAM_R38[3]	DDR3_Memory_Interface_Top_inst/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_2_s/CLKA
0.814	0.032	tHld		1	BSRAM_R38[3]	DDR3_Memory_Interface_Top_inst/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_2_s

Path Statistics:

Clock Skew	0.174
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.609, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.124, 48.936%; tC2Q: 0.130, 51.064%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.783, 100.000%

Path9

Path Summary:

Slack	0.049
Data Arrival Time	0.863
Data Required Time	0.814
From	DDR3_Memory_Interface_Top_inst/gw3_top/u_gwmc_top/gw_wr_data0/wr_buf_din_91_s0
To	DDR3_Memory_Interface_Top_inst/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_2_s
Launch Clk	dma_clk:[R]
Latch Clk	dma_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					dma_clk
0.000	0.000	tCL	RR	3995	BOTTOMSIDE[0]	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.609	0.609	tNET	RR	1	R39C21[0][A]	DDR3_Memory_Interface_Top_inst/gw3_top/u_gwmc_top/gw_wr_data0/wr_buf_din_91_s0/CLK
0.739	0.130	tC2Q	RR	1	R39C21[0][A]	DDR3_Memory_Interface_Top_inst/gw3_top/u_gwmc_top/gw_wr_data0/wr_buf_din_91_s0/Q
0.863	0.124	tNET	RR	1	BSRAM_R38[3]	DDR3_Memory_Interface_Top_inst/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_2_s/DI[19]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					dma_clk
0.000	0.000	tCL	RR	3995	BOTTOMSIDE[0]	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.783	0.783	tNET	RR	1	BSRAM_R38[3]	DDR3_Memory_Interface_Top_inst/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_2_s/CLKA
0.814	0.032	tHld		1	BSRAM_R38[3]	DDR3_Memory_Interface_Top_inst/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_2_s

Path Statistics:

Clock Skew	0.174
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.609, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.124, 48.936%; tC2Q: 0.130, 51.064%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.783, 100.000%

Path10

Path Summary:

Slack	0.082
Data Arrival Time	0.735
Data Required Time	0.653
From	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/rx_dph_len_d[5]_8_s0
To	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/rx_dph_len_d[6]_0_s9
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
0.608	0.608	tNET	RR	1	R39C98[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/rx_dph_len_d[5]_8_s0/CLK
0.735	0.127	tC2Q	RF	1	R39C98[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/rx_dph_len_d[5]_8_s0/Q
0.735	0.000	tNET	FF	1	R39C100	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/rx_dph_len_d[6]_0_s9/DI[0]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
0.608	0.608	tNET	RR	1	R39C100	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/rx_dph_len_d[6]_0_s9/CLK
0.653	0.045	tHld		1	R39C100	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/rx_dph_len_d[6]_0_s9

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.608, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.127, 100.000%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.608, 100.000%

Path11

Path Summary:

Slack	0.090
Data Arrival Time	0.907
Data Required Time	0.817
From	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_26_s1
To	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/sync_fifo_inst/mem_mem_0_0_s
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
0.608	0.608	tNET	RR	1	R40C82[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_26_s1/CLK
0.735	0.127	tC2Q	RF	2	R40C82[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_26_s1/Q
0.907	0.172	tNET	FF	1	BSRAM_R38[14][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/sync_fifo_inst/mem_mem_0_0_s/DI[26]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
0.786	0.786	tNET	RR	1	BSRAM_R38[14][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/sync_fifo_inst/mem_mem_0_0_s/CLKA
0.817	0.032	tHld		1	BSRAM_R38[14][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/sync_fifo_inst/mem_mem_0_0_s

Path Statistics:

Clock Skew	0.177
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.608, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.172, 57.530%; tC2Q: 0.127, 42.470%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.786, 100.000%

Path12

Path Summary:

Slack	0.105
Data Arrival Time	0.923
Data Required Time	0.818
From	DDR3_Memory_Interface_Top_inst/gw3_top/u_gwmc_top/gw_wr_data0/wr_buf_din_67_s0
To	DDR3_Memory_Interface_Top_inst/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_1_s
Launch Clk	dma_clk:[R]
Latch Clk	dma_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					dma_clk
0.000	0.000	tCL	RR	3995	BOTTOMSIDE[0]	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.602	0.602	tNET	RR	1	R39C19[3][A]	DDR3_Memory_Interface_Top_inst/gw3_top/u_gwmc_top/gw_wr_data0/wr_buf_din_67_s0/CLK
0.732	0.130	tC2Q	RR	1	R39C19[3][A]	DDR3_Memory_Interface_Top_inst/gw3_top/u_gwmc_top/gw_wr_data0/wr_buf_din_67_s0/Q
0.923	0.192	tNET	RR	1	BSRAM_R38[2][B]	DDR3_Memory_Interface_Top_inst/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_1_s/DI[31]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					dma_clk
0.000	0.000	tCL	RR	3995	BOTTOMSIDE[0]	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.787	0.787	tNET	RR	1	BSRAM_R38[2][B]	DDR3_Memory_Interface_Top_inst/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_1_s/CLKA
0.818	0.032	tHld		1	BSRAM_R38[2][B]	DDR3_Memory_Interface_Top_inst/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_1_s

Path Statistics:

Clock Skew	0.184
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.602, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.192, 59.664%; tC2Q: 0.130, 40.336%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.787, 100.000%

Path13

Path Summary:

Slack	0.107
Data Arrival Time	0.927
Data Required Time	0.820
From	DDR3_Memory_Interface_Top_inst/gw3_top/u_gwmc_top/gw_wr_data0/wr_buf_din_48_s0
To	DDR3_Memory_Interface_Top_inst/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_1_s
Launch Clk	dma_clk:[R]
Latch Clk	dma_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					dma_clk
0.000	0.000	tCL	RR	3995	BOTTOMSIDE[0]	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.606	0.606	tNET	RR	1	R40C18[2][B]	DDR3_Memory_Interface_Top_inst/gw3_top/u_gwmc_top/gw_wr_data0/wr_buf_din_48_s0/CLK
0.735	0.130	tC2Q	RR	1	R40C18[2][B]	DDR3_Memory_Interface_Top_inst/gw3_top/u_gwmc_top/gw_wr_data0/wr_buf_din_48_s0/Q
0.927	0.192	tNET	RR	1	BSRAM_R38[2][B]	DDR3_Memory_Interface_Top_inst/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_1_s/DI[12]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					dma_clk
0.000	0.000	tCL	RR	3995	BOTTOMSIDE[0]	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.787	0.787	tNET	RR	1	BSRAM_R38[2][B]	DDR3_Memory_Interface_Top_inst/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_1_s/CLKA
0.820	0.033	tHld		1	BSRAM_R38[2][B]	DDR3_Memory_Interface_Top_inst/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_1_s

Path Statistics:

Clock Skew	0.181
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.606, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.192, 59.664%; tC2Q: 0.130, 40.336%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.787, 100.000%

Path14

Path Summary:

Slack	0.109
Data Arrival Time	0.927
Data Required Time	0.818
From	DDR3_Memory_Interface_Top_inst/gw3_top/u_gwmc_top/gw_wr_data0/wr_buf_din_54_s0
To	DDR3_Memory_Interface_Top_inst/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_1_s
Launch Clk	dma_clk:[R]
Latch Clk	dma_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					dma_clk
0.000	0.000	tCL	RR	3995	BOTTOMSIDE[0]	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.606	0.606	tNET	RR	1	R40C18[0][B]	DDR3_Memory_Interface_Top_inst/gw3_top/u_gwmc_top/gw_wr_data0/wr_buf_din_54_s0/CLK
0.735	0.130	tC2Q	RR	1	R40C18[0][B]	DDR3_Memory_Interface_Top_inst/gw3_top/u_gwmc_top/gw_wr_data0/wr_buf_din_54_s0/Q
0.927	0.192	tNET	RR	1	BSRAM_R38[2][B]	DDR3_Memory_Interface_Top_inst/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_1_s/DI[18]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					dma_clk
0.000	0.000	tCL	RR	3995	BOTTOMSIDE[0]	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.787	0.787	tNET	RR	1	BSRAM_R38[2][B]	DDR3_Memory_Interface_Top_inst/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_1_s/CLKA
0.818	0.032	tHld		1	BSRAM_R38[2][B]	DDR3_Memory_Interface_Top_inst/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_1_s

Path Statistics:

Clock Skew	0.181
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.606, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.192, 59.664%; tC2Q: 0.130, 40.336%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.787, 100.000%

Path15

Path Summary:

Slack	0.116
Data Arrival Time	0.931
Data Required Time	0.814
From	DDR3_Memory_Interface_Top_inst/gw3_top/u_gwmc_top/gw_wr_data0/wr_buf_din_95_s0
To	DDR3_Memory_Interface_Top_inst/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_2_s
Launch Clk	dma_clk:[R]
Latch Clk	dma_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					dma_clk
0.000	0.000	tCL	RR	3995	BOTTOMSIDE[0]	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.609	0.609	tNET	RR	1	R39C21[3][B]	DDR3_Memory_Interface_Top_inst/gw3_top/u_gwmc_top/gw_wr_data0/wr_buf_din_95_s0/CLK
0.739	0.130	tC2Q	RR	1	R39C21[3][B]	DDR3_Memory_Interface_Top_inst/gw3_top/u_gwmc_top/gw_wr_data0/wr_buf_din_95_s0/Q
0.931	0.192	tNET	RR	1	BSRAM_R38[3]	DDR3_Memory_Interface_Top_inst/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_2_s/DI[23]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					dma_clk
0.000	0.000	tCL	RR	3995	BOTTOMSIDE[0]	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.783	0.783	tNET	RR	1	BSRAM_R38[3]	DDR3_Memory_Interface_Top_inst/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_2_s/CLKA
0.814	0.032	tHld		1	BSRAM_R38[3]	DDR3_Memory_Interface_Top_inst/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_2_s

Path Statistics:

Clock Skew	0.174
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.609, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.192, 59.664%; tC2Q: 0.130, 40.336%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.783, 100.000%

Path16

Path Summary:

Slack	0.119
Data Arrival Time	0.937
Data Required Time	0.818
From	DDR3_Memory_Interface_Top_inst/gw3_top/u_gwmc_top/gw_wr_data0/wr_buf_din_64_s0
To	DDR3_Memory_Interface_Top_inst/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_1_s
Launch Clk	dma_clk:[R]
Latch Clk	dma_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					dma_clk
0.000	0.000	tCL	RR	3995	BOTTOMSIDE[0]	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.602	0.602	tNET	RR	1	R39C19[0][A]	DDR3_Memory_Interface_Top_inst/gw3_top/u_gwmc_top/gw_wr_data0/wr_buf_din_64_s0/CLK
0.732	0.130	tC2Q	RR	1	R39C19[0][A]	DDR3_Memory_Interface_Top_inst/gw3_top/u_gwmc_top/gw_wr_data0/wr_buf_din_64_s0/Q
0.937	0.205	tNET	RR	1	BSRAM_R38[2][B]	DDR3_Memory_Interface_Top_inst/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_1_s/DI[28]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					dma_clk
0.000	0.000	tCL	RR	3995	BOTTOMSIDE[0]	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.787	0.787	tNET	RR	1	BSRAM_R38[2][B]	DDR3_Memory_Interface_Top_inst/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_1_s/CLKA
0.818	0.032	tHld		1	BSRAM_R38[2][B]	DDR3_Memory_Interface_Top_inst/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_1_s

Path Statistics:

Clock Skew	0.184
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.602, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.205, 61.290%; tC2Q: 0.130, 38.710%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.787, 100.000%

Path17

Path Summary:

Slack	0.120
Data Arrival Time	0.729
Data Required Time	0.609
From	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/VALUE_rrr_10_s0
To	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/dq_iobuf_gen[10].dq_iodelay
Launch Clk	dma_clk:[R]
Latch Clk	dma_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					dma_clk
0.000	0.000	tCL	RR	3995	BOTTOMSIDE[0]	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.602	0.602	tNET	RR	1	R71C15[2][B]	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/VALUE_rrr_10_s0/CLK
0.729	0.127	tC2Q	RF	1	R71C15[2][B]	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/VALUE_rrr_10_s0/Q
0.729	0.000	tNET	FF	1	IOB16[B]	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/dq_iobuf_gen[10].dq_iodelay/VALUE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					dma_clk
0.000	0.000	tCL	RR	3995	BOTTOMSIDE[0]	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.609	0.609	tNET	RR	1	IOB16[B]	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[2].u_ides8_dq/PCLK
0.609	0.000	tHld		1	IOB16[B]	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/dq_iobuf_gen[10].dq_iodelay

Path Statistics:

Clock Skew	0.007
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.602, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.127, 100.000%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.609, 100.000%

Path18

Path Summary:

Slack	0.122
Data Arrival Time	0.941
Data Required Time	0.818
From	DDR3_Memory_Interface_Top_inst/gw3_top/u_gwmc_top/gw_wr_data0/wr_buf_din_69_s0
To	DDR3_Memory_Interface_Top_inst/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_1_s
Launch Clk	dma_clk:[R]
Latch Clk	dma_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					dma_clk
0.000	0.000	tCL	RR	3995	BOTTOMSIDE[0]	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.606	0.606	tNET	RR	1	R39C18[1][A]	DDR3_Memory_Interface_Top_inst/gw3_top/u_gwmc_top/gw_wr_data0/wr_buf_din_69_s0/CLK
0.735	0.130	tC2Q	RR	1	R39C18[1][A]	DDR3_Memory_Interface_Top_inst/gw3_top/u_gwmc_top/gw_wr_data0/wr_buf_din_69_s0/Q
0.941	0.205	tNET	RR	1	BSRAM_R38[2][B]	DDR3_Memory_Interface_Top_inst/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_1_s/DI[33]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					dma_clk
0.000	0.000	tCL	RR	3995	BOTTOMSIDE[0]	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.787	0.787	tNET	RR	1	BSRAM_R38[2][B]	DDR3_Memory_Interface_Top_inst/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_1_s/CLKA
0.818	0.032	tHld		1	BSRAM_R38[2][B]	DDR3_Memory_Interface_Top_inst/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_1_s

Path Statistics:

Clock Skew	0.181
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.606, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.205, 61.290%; tC2Q: 0.130, 38.710%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.787, 100.000%

Path19

Path Summary:

Slack	0.122
Data Arrival Time	0.941
Data Required Time	0.818
From	DDR3_Memory_Interface_Top_inst/gw3_top/u_gwmc_top/gw_wr_data0/wr_buf_din_29_s0
To	DDR3_Memory_Interface_Top_inst/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_0_s
Launch Clk	dma_clk:[R]
Latch Clk	dma_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					dma_clk
0.000	0.000	tCL	RR	3995	BOTTOMSIDE[0]	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.606	0.606	tNET	RR	1	R39C8[2][B]	DDR3_Memory_Interface_Top_inst/gw3_top/u_gwmc_top/gw_wr_data0/wr_buf_din_29_s0/CLK
0.735	0.130	tC2Q	RR	1	R39C8[2][B]	DDR3_Memory_Interface_Top_inst/gw3_top/u_gwmc_top/gw_wr_data0/wr_buf_din_29_s0/Q
0.941	0.205	tNET	RR	1	BSRAM_R38[0][A]	DDR3_Memory_Interface_Top_inst/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_0_s/DI[29]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					dma_clk
0.000	0.000	tCL	RR	3995	BOTTOMSIDE[0]	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.787	0.787	tNET	RR	1	BSRAM_R38[0][A]	DDR3_Memory_Interface_Top_inst/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_0_s/CLKA
0.818	0.032	tHld		1	BSRAM_R38[0][A]	DDR3_Memory_Interface_Top_inst/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_0_s

Path Statistics:

Clock Skew	0.181
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.606, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.205, 61.290%; tC2Q: 0.130, 38.710%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.787, 100.000%

Path20

Path Summary:

Slack	0.123
Data Arrival Time	0.729
Data Required Time	0.606
From	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/VALUE_rrr_12_s0
To	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/dq_iobuf_gen[12].dq_iodelay
Launch Clk	dma_clk:[R]
Latch Clk	dma_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					dma_clk
0.000	0.000	tCL	RR	3995	BOTTOMSIDE[0]	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.602	0.602	tNET	RR	1	R71C15[1][B]	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/VALUE_rrr_12_s0/CLK
0.729	0.127	tC2Q	RF	1	R71C15[1][B]	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/VALUE_rrr_12_s0/Q
0.729	0.000	tNET	FF	1	IOB14[A]	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/dq_iobuf_gen[12].dq_iodelay/VALUE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					dma_clk
0.000	0.000	tCL	RR	3995	BOTTOMSIDE[0]	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.606	0.606	tNET	RR	1	IOB14[A]	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[4].u_ides8_dq/PCLK
0.606	0.000	tHld		1	IOB14[A]	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/dq_iobuf_gen[12].dq_iodelay

Path Statistics:

Clock Skew	0.004
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.602, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.127, 100.000%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.606, 100.000%

Path21

Path Summary:

Slack	0.123
Data Arrival Time	0.733
Data Required Time	0.609
From	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/VALUE_rrr_11_s0
To	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/dq_iobuf_gen[11].dq_iodelay
Launch Clk	dma_clk:[R]
Latch Clk	dma_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					dma_clk
0.000	0.000	tCL	RR	3995	BOTTOMSIDE[0]	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.606	0.606	tNET	RR	1	R72C8[2][A]	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/VALUE_rrr_11_s0/CLK
0.733	0.127	tC2Q	RF	1	R72C8[2][A]	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/VALUE_rrr_11_s0/Q
0.733	0.000	tNET	FF	1	IOB1[A]	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/dq_iobuf_gen[11].dq_iodelay/VALUE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					dma_clk
0.000	0.000	tCL	RR	3995	BOTTOMSIDE[0]	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.609	0.609	tNET	RR	1	IOB1[A]	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[3].u_ides8_dq/PCLK
0.609	0.000	tHld		1	IOB1[A]	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/dq_iobuf_gen[11].dq_iodelay

Path Statistics:

Clock Skew	0.004
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.606, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.127, 100.000%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.609, 100.000%

Path22

Path Summary:

Slack	0.123
Data Arrival Time	0.733
Data Required Time	0.609
From	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/VALUE_rrr_9_s0
To	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/dq_iobuf_gen[9].dq_iodelay
Launch Clk	dma_clk:[R]
Latch Clk	dma_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					dma_clk
0.000	0.000	tCL	RR	3995	BOTTOMSIDE[0]	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.606	0.606	tNET	RR	1	R72C8[1][A]	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/VALUE_rrr_9_s0/CLK
0.733	0.127	tC2Q	RF	1	R72C8[1][A]	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/VALUE_rrr_9_s0/Q
0.733	0.000	tNET	FF	1	IOB5[A]	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/dq_iobuf_gen[9].dq_iodelay/VALUE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					dma_clk
0.000	0.000	tCL	RR	3995	BOTTOMSIDE[0]	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.609	0.609	tNET	RR	1	IOB5[A]	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[1].u_ides8_dq/PCLK
0.609	0.000	tHld		1	IOB5[A]	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/dq_iobuf_gen[9].dq_iodelay

Path Statistics:

Clock Skew	0.004
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.606, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.127, 100.000%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.609, 100.000%

Path23

Path Summary:

Slack	0.123
Data Arrival Time	0.733
Data Required Time	0.609
From	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/VALUE_rrr_0_s0
To	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/dq_iobuf_gen[0].dq_iodelay
Launch Clk	dma_clk:[R]
Latch Clk	dma_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					dma_clk
0.000	0.000	tCL	RR	3995	BOTTOMSIDE[0]	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.606	0.606	tNET	RR	1	R71C22[3][B]	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/VALUE_rrr_0_s0/CLK
0.733	0.127	tC2Q	RF	1	R71C22[3][B]	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/VALUE_rrr_0_s0/Q
0.733	0.000	tNET	FF	1	IOB24[B]	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/dq_iobuf_gen[0].dq_iodelay/VALUE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					dma_clk
0.000	0.000	tCL	RR	3995	BOTTOMSIDE[0]	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.609	0.609	tNET	RR	1	IOB24[B]	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[0].u_ides8_dq/PCLK
0.609	0.000	tHld		1	IOB24[B]	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/dq_iobuf_gen[0].dq_iodelay

Path Statistics:

Clock Skew	0.004
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.606, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.127, 100.000%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.609, 100.000%

Path24

Path Summary:

Slack	0.123
Data Arrival Time	0.729
Data Required Time	0.606
From	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/DQS_VALUE_rrr_0_s0
To	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/dqs_iobuf_gen[0].dqs_iodelay
Launch Clk	dma_clk:[R]
Latch Clk	dma_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					dma_clk
0.000	0.000	tCL	RR	3995	BOTTOMSIDE[0]	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.602	0.602	tNET	RR	1	R73C11[0][B]	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/DQS_VALUE_rrr_0_s0/CLK
0.729	0.127	tC2Q	RF	1	R73C11[0][B]	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/DQS_VALUE_rrr_0_s0/Q
0.729	0.000	tNET	FF	1	IOB26[A]	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/dqs_iobuf_gen[0].dqs_iodelay/VALUE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					dma_clk
0.000	0.000	tCL	RR	3995	BOTTOMSIDE[0]	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.606	0.606	tNET	RR	1	IOB26[A]	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_ides8_dqs/PCLK
0.606	0.000	tHld		1	IOB26[A]	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/dqs_iobuf_gen[0].dqs_iodelay

Path Statistics:

Clock Skew	0.004
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.602, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.127, 100.000%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.606, 100.000%

Path25

Path Summary:

Slack	0.124
Data Arrival Time	0.944
Data Required Time	0.820
From	DDR3_Memory_Interface_Top_inst/gw3_top/u_gwmc_top/gw_wr_data0/wr_buf_din_44_s0
To	DDR3_Memory_Interface_Top_inst/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_1_s
Launch Clk	dma_clk:[R]
Latch Clk	dma_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					dma_clk
0.000	0.000	tCL	RR	3995	BOTTOMSIDE[0]	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.609	0.609	tNET	RR	1	R41C17[2][A]	DDR3_Memory_Interface_Top_inst/gw3_top/u_gwmc_top/gw_wr_data0/wr_buf_din_44_s0/CLK
0.739	0.130	tC2Q	RR	1	R41C17[2][A]	DDR3_Memory_Interface_Top_inst/gw3_top/u_gwmc_top/gw_wr_data0/wr_buf_din_44_s0/Q
0.944	0.205	tNET	RR	1	BSRAM_R38[2][B]	DDR3_Memory_Interface_Top_inst/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_1_s/DI[8]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					dma_clk
0.000	0.000	tCL	RR	3995	BOTTOMSIDE[0]	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.787	0.787	tNET	RR	1	BSRAM_R38[2][B]	DDR3_Memory_Interface_Top_inst/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_1_s/CLKA
0.820	0.033	tHld		1	BSRAM_R38[2][B]	DDR3_Memory_Interface_Top_inst/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_1_s

Path Statistics:

Clock Skew	0.177
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.609, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.205, 61.290%; tC2Q: 0.130, 38.710%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.787, 100.000%

Recovery Analysis Report

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	0.306
Data Arrival Time	8.914
Data Required Time	9.221
From	u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0
To	u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.mem_Small.mem_0_1_s
Launch Clk	Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk:[F]
Latch Clk	Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
3.361	3.361					active clock edge time
3.361	0.000					Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk
4.412	1.051	tCL	FF	158	PLL_L[1]	Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1
5.921	1.509	tNET	FF	1	R46C28[0][A]	u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0/CLK
6.240	0.319	tC2Q	FF	63	R46C28[0][A]	u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0/Q
8.914	2.675	tNET	FF	16	BSRAM_R56[7][A]	u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.mem_Small.mem_0_1_s/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.723	6.723					active clock edge time
6.723	0.000					Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk
7.773	1.051	tCL	RR	158	PLL_L[1]	Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1
9.278	1.505	tNET	RR	1	BSRAM_R56[7][A]	u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.mem_Small.mem_0_1_s/CLKB
9.221	-0.058	tSu		1	BSRAM_R56[7][A]	u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.mem_Small.mem_0_1_s

Path Statistics:

Clock Skew	-0.004
Setup Relationship	3.361
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.509, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.675, 89.357%; tC2Q: 0.319, 10.643%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.505, 100.000%

Path2

Path Summary:

Slack	0.578
Data Arrival Time	8.650
Data Required Time	9.227
From	u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0
To	u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.mem_Small.mem_0_3_s
Launch Clk	Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk:[F]
Latch Clk	Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
3.361	3.361					active clock edge time
3.361	0.000					Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk
4.412	1.051	tCL	FF	158	PLL_L[1]	Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1
5.921	1.509	tNET	FF	1	R46C28[0][A]	u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0/CLK
6.240	0.319	tC2Q	FF	63	R46C28[0][A]	u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0/Q
8.650	2.410	tNET	FF	16	BSRAM_R56[6]	u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.mem_Small.mem_0_3_s/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.723	6.723					active clock edge time
6.723	0.000					Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk
7.773	1.051	tCL	RR	158	PLL_L[1]	Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1
9.285	1.512	tNET	RR	1	BSRAM_R56[6]	u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.mem_Small.mem_0_3_s/CLKB
9.227	-0.058	tSu		1	BSRAM_R56[6]	u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.mem_Small.mem_0_3_s

Path Statistics:

Clock Skew	0.003
Setup Relationship	3.361
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.509, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.410, 88.325%; tC2Q: 0.319, 11.675%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.512, 100.000%

Path3

Path Summary:

Slack	0.741
Data Arrival Time	8.493
Data Required Time	9.234
From	u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0
To	u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.mem_Small.mem_0_5_s
Launch Clk	Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk:[F]
Latch Clk	Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
3.361	3.361					active clock edge time
3.361	0.000					Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk
4.412	1.051	tCL	FF	158	PLL_L[1]	Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1
5.921	1.509	tNET	FF	1	R46C28[0][A]	u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0/CLK
6.240	0.319	tC2Q	FF	63	R46C28[0][A]	u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0/Q
8.493	2.254	tNET	FF	16	BSRAM_R56[5][B]	u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.mem_Small.mem_0_5_s/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.723	6.723					active clock edge time
6.723	0.000					Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk
7.773	1.051	tCL	RR	158	PLL_L[1]	Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1
9.292	1.518	tNET	RR	1	BSRAM_R56[5][B]	u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.mem_Small.mem_0_5_s/CLKB
9.234	-0.058	tSu		1	BSRAM_R56[5][B]	u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.mem_Small.mem_0_5_s

Path Statistics:

Clock Skew	0.009
Setup Relationship	3.361
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.509, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.254, 87.614%; tC2Q: 0.319, 12.386%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.518, 100.000%

Path4

Path Summary:

Slack	1.677
Data Arrival Time	5.843
Data Required Time	7.520
From	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/internel_resetn_s0
To	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/tx_data_en_encode_o_r1_s0
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
1.520	1.520	tNET	RR	1	R50C42[0][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/internel_resetn_s0/CLK
1.795	0.275	tC2Q	RR	595	R50C42[0][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/internel_resetn_s0/Q
4.762	2.966	tNET	RR	1	R67C58[0][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/tx_data_en_encode_o_s12/I3
4.951	0.189	tINS	RR	3	R67C58[0][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/tx_data_en_encode_o_s12/F
5.070	0.119	tNET	RR	1	R67C58[0][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/n3235_s2/I3
5.343	0.274	tINS	RF	1	R67C58[0][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/n3235_s2/F
5.843	0.500	tNET	FF	1	R67C58[1][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/tx_data_en_encode_o_r1_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.250	6.250					active clock edge time
6.250	0.000					pclk
6.250	0.000	tCL	RR	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.770	1.520	tNET	RR	1	R67C58[1][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/tx_data_en_encode_o_r1_s0/CLK
7.520	-0.250	tSu		1	R67C58[1][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/tx_data_en_encode_o_r1_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	6.250
Logic Level	3
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.520, 100.000%
Arrival Data Path Delay	cell: 0.463, 10.702%; route: 3.585, 82.927%; tC2Q: 0.275, 6.371%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.520, 100.000%

Path5

Path Summary:

Slack	0.879
Data Arrival Time	6.627
Data Required Time	7.506
From	line_fifo_inst/fifo_inst/reset_r_1_s0
To	line_fifo_inst/fifo_inst/Equal.rq2_wptr_2_s0
Launch Clk	pclk:[F]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
3.200	3.200					active clock edge time
3.200	0.000					pclk
3.200	0.000	tCL	FF	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
4.706	1.506	tNET	FF	1	R64C97[2][A]	line_fifo_inst/fifo_inst/reset_r_1_s0/CLK
5.024	0.319	tC2Q	FF	68	R64C97[2][A]	line_fifo_inst/fifo_inst/reset_r_1_s0/Q
6.627	1.603	tNET	FF	1	R64C101[2][A]	line_fifo_inst/fifo_inst/Equal.rq2_wptr_2_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.250	6.250					active clock edge time
6.250	0.000					pclk
6.250	0.000	tCL	RR	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.757	1.507	tNET	RR	1	R64C101[2][A]	line_fifo_inst/fifo_inst/Equal.rq2_wptr_2_s0/CLK
7.506	-0.250	tSu		1	R64C101[2][A]	line_fifo_inst/fifo_inst/Equal.rq2_wptr_2_s0

Path Statistics:

Clock Skew	0.001
Setup Relationship	3.050
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.506, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.603, 83.419%; tC2Q: 0.319, 16.581%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.507, 100.000%

Path6

Path Summary:

Slack	0.879
Data Arrival Time	6.627
Data Required Time	7.506
From	line_fifo_inst/fifo_inst/reset_r_1_s0
To	line_fifo_inst/fifo_inst/Equal.rq1_wptr_2_s0
Launch Clk	pclk:[F]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
3.200	3.200					active clock edge time
3.200	0.000					pclk
3.200	0.000	tCL	FF	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
4.706	1.506	tNET	FF	1	R64C97[2][A]	line_fifo_inst/fifo_inst/reset_r_1_s0/CLK
5.024	0.319	tC2Q	FF	68	R64C97[2][A]	line_fifo_inst/fifo_inst/reset_r_1_s0/Q
6.627	1.603	tNET	FF	1	R64C101[0][B]	line_fifo_inst/fifo_inst/Equal.rq1_wptr_2_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.250	6.250					active clock edge time
6.250	0.000					pclk
6.250	0.000	tCL	RR	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.757	1.507	tNET	RR	1	R64C101[0][B]	line_fifo_inst/fifo_inst/Equal.rq1_wptr_2_s0/CLK
7.506	-0.250	tSu		1	R64C101[0][B]	line_fifo_inst/fifo_inst/Equal.rq1_wptr_2_s0

Path Statistics:

Clock Skew	0.001
Setup Relationship	3.050
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.506, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.603, 83.419%; tC2Q: 0.319, 16.581%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.507, 100.000%

Path7

Path Summary:

Slack	0.918
Data Arrival Time	6.602
Data Required Time	7.520
From	line_fifo_inst/fifo_inst/reset_r_1_s0
To	line_fifo_inst/fifo_inst/Equal.rptr_0_s0
Launch Clk	pclk:[F]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
3.200	3.200					active clock edge time
3.200	0.000					pclk
3.200	0.000	tCL	FF	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
4.706	1.506	tNET	FF	1	R64C97[2][A]	line_fifo_inst/fifo_inst/reset_r_1_s0/CLK
5.024	0.319	tC2Q	FF	68	R64C97[2][A]	line_fifo_inst/fifo_inst/reset_r_1_s0/Q
6.602	1.578	tNET	FF	1	R69C103[0][A]	line_fifo_inst/fifo_inst/Equal.rptr_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.250	6.250					active clock edge time
6.250	0.000					pclk
6.250	0.000	tCL	RR	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.770	1.520	tNET	RR	1	R69C103[0][A]	line_fifo_inst/fifo_inst/Equal.rptr_0_s0/CLK
7.520	-0.250	tSu		1	R69C103[0][A]	line_fifo_inst/fifo_inst/Equal.rptr_0_s0

Path Statistics:

Clock Skew	0.014
Setup Relationship	3.050
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.506, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.578, 83.199%; tC2Q: 0.319, 16.801%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.520, 100.000%

Path8

Path Summary:

Slack	0.918
Data Arrival Time	6.602
Data Required Time	7.520
From	line_fifo_inst/fifo_inst/reset_r_1_s0
To	line_fifo_inst/fifo_inst/Equal.rptr_2_s0
Launch Clk	pclk:[F]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
3.200	3.200					active clock edge time
3.200	0.000					pclk
3.200	0.000	tCL	FF	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
4.706	1.506	tNET	FF	1	R64C97[2][A]	line_fifo_inst/fifo_inst/reset_r_1_s0/CLK
5.024	0.319	tC2Q	FF	68	R64C97[2][A]	line_fifo_inst/fifo_inst/reset_r_1_s0/Q
6.602	1.578	tNET	FF	1	R69C103[2][B]	line_fifo_inst/fifo_inst/Equal.rptr_2_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.250	6.250					active clock edge time
6.250	0.000					pclk
6.250	0.000	tCL	RR	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.770	1.520	tNET	RR	1	R69C103[2][B]	line_fifo_inst/fifo_inst/Equal.rptr_2_s0/CLK
7.520	-0.250	tSu		1	R69C103[2][B]	line_fifo_inst/fifo_inst/Equal.rptr_2_s0

Path Statistics:

Clock Skew	0.014
Setup Relationship	3.050
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.506, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.578, 83.199%; tC2Q: 0.319, 16.801%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.520, 100.000%

Path9

Path Summary:

Slack	0.918
Data Arrival Time	6.602
Data Required Time	7.520
From	line_fifo_inst/fifo_inst/reset_r_1_s0
To	line_fifo_inst/fifo_inst/Equal.rptr_8_s0
Launch Clk	pclk:[F]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
3.200	3.200					active clock edge time
3.200	0.000					pclk
3.200	0.000	tCL	FF	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
4.706	1.506	tNET	FF	1	R64C97[2][A]	line_fifo_inst/fifo_inst/reset_r_1_s0/CLK
5.024	0.319	tC2Q	FF	68	R64C97[2][A]	line_fifo_inst/fifo_inst/reset_r_1_s0/Q
6.602	1.578	tNET	FF	1	R66C103[2][A]	line_fifo_inst/fifo_inst/Equal.rptr_8_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.250	6.250					active clock edge time
6.250	0.000					pclk
6.250	0.000	tCL	RR	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.770	1.520	tNET	RR	1	R66C103[2][A]	line_fifo_inst/fifo_inst/Equal.rptr_8_s0/CLK
7.520	-0.250	tSu		1	R66C103[2][A]	line_fifo_inst/fifo_inst/Equal.rptr_8_s0

Path Statistics:

Clock Skew	0.014
Setup Relationship	3.050
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.506, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.578, 83.199%; tC2Q: 0.319, 16.801%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.520, 100.000%

Path10

Path Summary:

Slack	0.918
Data Arrival Time	6.602
Data Required Time	7.520
From	line_fifo_inst/fifo_inst/reset_r_1_s0
To	line_fifo_inst/fifo_inst/Equal.rq2_wptr_4_s0
Launch Clk	pclk:[F]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
3.200	3.200					active clock edge time
3.200	0.000					pclk
3.200	0.000	tCL	FF	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
4.706	1.506	tNET	FF	1	R64C97[2][A]	line_fifo_inst/fifo_inst/reset_r_1_s0/CLK
5.024	0.319	tC2Q	FF	68	R64C97[2][A]	line_fifo_inst/fifo_inst/reset_r_1_s0/Q
6.602	1.578	tNET	FF	1	R69C103[0][B]	line_fifo_inst/fifo_inst/Equal.rq2_wptr_4_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.250	6.250					active clock edge time
6.250	0.000					pclk
6.250	0.000	tCL	RR	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.770	1.520	tNET	RR	1	R69C103[0][B]	line_fifo_inst/fifo_inst/Equal.rq2_wptr_4_s0/CLK
7.520	-0.250	tSu		1	R69C103[0][B]	line_fifo_inst/fifo_inst/Equal.rq2_wptr_4_s0

Path Statistics:

Clock Skew	0.014
Setup Relationship	3.050
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.506, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.578, 83.199%; tC2Q: 0.319, 16.801%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.520, 100.000%

Path11

Path Summary:

Slack	0.918
Data Arrival Time	6.602
Data Required Time	7.520
From	line_fifo_inst/fifo_inst/reset_r_1_s0
To	line_fifo_inst/fifo_inst/Equal.rq2_wptr_6_s0
Launch Clk	pclk:[F]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
3.200	3.200					active clock edge time
3.200	0.000					pclk
3.200	0.000	tCL	FF	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
4.706	1.506	tNET	FF	1	R64C97[2][A]	line_fifo_inst/fifo_inst/reset_r_1_s0/CLK
5.024	0.319	tC2Q	FF	68	R64C97[2][A]	line_fifo_inst/fifo_inst/reset_r_1_s0/Q
6.602	1.578	tNET	FF	1	R69C103[1][B]	line_fifo_inst/fifo_inst/Equal.rq2_wptr_6_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.250	6.250					active clock edge time
6.250	0.000					pclk
6.250	0.000	tCL	RR	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.770	1.520	tNET	RR	1	R69C103[1][B]	line_fifo_inst/fifo_inst/Equal.rq2_wptr_6_s0/CLK
7.520	-0.250	tSu		1	R69C103[1][B]	line_fifo_inst/fifo_inst/Equal.rq2_wptr_6_s0

Path Statistics:

Clock Skew	0.014
Setup Relationship	3.050
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.506, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.578, 83.199%; tC2Q: 0.319, 16.801%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.520, 100.000%

Path12

Path Summary:

Slack	0.918
Data Arrival Time	6.602
Data Required Time	7.520
From	line_fifo_inst/fifo_inst/reset_r_1_s0
To	line_fifo_inst/fifo_inst/Equal.rq2_wptr_10_s0
Launch Clk	pclk:[F]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
3.200	3.200					active clock edge time
3.200	0.000					pclk
3.200	0.000	tCL	FF	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
4.706	1.506	tNET	FF	1	R64C97[2][A]	line_fifo_inst/fifo_inst/reset_r_1_s0/CLK
5.024	0.319	tC2Q	FF	68	R64C97[2][A]	line_fifo_inst/fifo_inst/reset_r_1_s0/Q
6.602	1.578	tNET	FF	1	R69C103[1][A]	line_fifo_inst/fifo_inst/Equal.rq2_wptr_10_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.250	6.250					active clock edge time
6.250	0.000					pclk
6.250	0.000	tCL	RR	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.770	1.520	tNET	RR	1	R69C103[1][A]	line_fifo_inst/fifo_inst/Equal.rq2_wptr_10_s0/CLK
7.520	-0.250	tSu		1	R69C103[1][A]	line_fifo_inst/fifo_inst/Equal.rq2_wptr_10_s0

Path Statistics:

Clock Skew	0.014
Setup Relationship	3.050
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.506, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.578, 83.199%; tC2Q: 0.319, 16.801%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.520, 100.000%

Path13

Path Summary:

Slack	0.918
Data Arrival Time	6.602
Data Required Time	7.520
From	line_fifo_inst/fifo_inst/reset_r_1_s0
To	line_fifo_inst/fifo_inst/Equal.rq1_wptr_4_s0
Launch Clk	pclk:[F]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
3.200	3.200					active clock edge time
3.200	0.000					pclk
3.200	0.000	tCL	FF	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
4.706	1.506	tNET	FF	1	R64C97[2][A]	line_fifo_inst/fifo_inst/reset_r_1_s0/CLK
5.024	0.319	tC2Q	FF	68	R64C97[2][A]	line_fifo_inst/fifo_inst/reset_r_1_s0/Q
6.602	1.578	tNET	FF	1	R66C103[0][A]	line_fifo_inst/fifo_inst/Equal.rq1_wptr_4_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.250	6.250					active clock edge time
6.250	0.000					pclk
6.250	0.000	tCL	RR	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.770	1.520	tNET	RR	1	R66C103[0][A]	line_fifo_inst/fifo_inst/Equal.rq1_wptr_4_s0/CLK
7.520	-0.250	tSu		1	R66C103[0][A]	line_fifo_inst/fifo_inst/Equal.rq1_wptr_4_s0

Path Statistics:

Clock Skew	0.014
Setup Relationship	3.050
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.506, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.578, 83.199%; tC2Q: 0.319, 16.801%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.520, 100.000%

Path14

Path Summary:

Slack	0.918
Data Arrival Time	6.602
Data Required Time	7.520
From	line_fifo_inst/fifo_inst/reset_r_1_s0
To	line_fifo_inst/fifo_inst/Equal.rq1_wptr_11_s0
Launch Clk	pclk:[F]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
3.200	3.200					active clock edge time
3.200	0.000					pclk
3.200	0.000	tCL	FF	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
4.706	1.506	tNET	FF	1	R64C97[2][A]	line_fifo_inst/fifo_inst/reset_r_1_s0/CLK
5.024	0.319	tC2Q	FF	68	R64C97[2][A]	line_fifo_inst/fifo_inst/reset_r_1_s0/Q
6.602	1.578	tNET	FF	1	R66C103[0][B]	line_fifo_inst/fifo_inst/Equal.rq1_wptr_11_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.250	6.250					active clock edge time
6.250	0.000					pclk
6.250	0.000	tCL	RR	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.770	1.520	tNET	RR	1	R66C103[0][B]	line_fifo_inst/fifo_inst/Equal.rq1_wptr_11_s0/CLK
7.520	-0.250	tSu		1	R66C103[0][B]	line_fifo_inst/fifo_inst/Equal.rq1_wptr_11_s0

Path Statistics:

Clock Skew	0.014
Setup Relationship	3.050
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.506, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.578, 83.199%; tC2Q: 0.319, 16.801%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.520, 100.000%

Path15

Path Summary:

Slack	1.005
Data Arrival Time	8.216
Data Required Time	9.221
From	u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0
To	u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.mem_Small.mem_0_0_s
Launch Clk	Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk:[F]
Latch Clk	Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
3.361	3.361					active clock edge time
3.361	0.000					Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk
4.412	1.051	tCL	FF	158	PLL_L[1]	Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1
5.921	1.509	tNET	FF	1	R46C28[0][A]	u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0/CLK
6.240	0.319	tC2Q	FF	63	R46C28[0][A]	u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0/Q
8.216	1.976	tNET	FF	16	BSRAM_R56[4]	u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.mem_Small.mem_0_0_s/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.723	6.723					active clock edge time
6.723	0.000					Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk
7.773	1.051	tCL	RR	158	PLL_L[1]	Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1
9.278	1.505	tNET	RR	1	BSRAM_R56[4]	u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.mem_Small.mem_0_0_s/CLKB
9.221	-0.058	tSu		1	BSRAM_R56[4]	u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.mem_Small.mem_0_0_s

Path Statistics:

Clock Skew	-0.004
Setup Relationship	3.361
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.509, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.976, 86.118%; tC2Q: 0.319, 13.882%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.505, 100.000%

Path16

Path Summary:

Slack	1.005
Data Arrival Time	8.222
Data Required Time	9.227
From	u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0
To	u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.mem_Small.mem_0_7_s
Launch Clk	Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk:[F]
Latch Clk	Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
3.361	3.361					active clock edge time
3.361	0.000					Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk
4.412	1.051	tCL	FF	158	PLL_L[1]	Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1
5.921	1.509	tNET	FF	1	R46C28[0][A]	u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0/CLK
6.240	0.319	tC2Q	FF	63	R46C28[0][A]	u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0/Q
8.222	1.983	tNET	FF	16	BSRAM_R56[5][A]	u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.mem_Small.mem_0_7_s/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.723	6.723					active clock edge time
6.723	0.000					Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk
7.773	1.051	tCL	RR	158	PLL_L[1]	Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1
9.285	1.512	tNET	RR	1	BSRAM_R56[5][A]	u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.mem_Small.mem_0_7_s/CLKB
9.227	-0.058	tSu		1	BSRAM_R56[5][A]	u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.mem_Small.mem_0_7_s

Path Statistics:

Clock Skew	0.003
Setup Relationship	3.361
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.509, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.983, 86.156%; tC2Q: 0.319, 13.844%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.512, 100.000%

Path17

Path Summary:

Slack	2.051
Data Arrival Time	5.462
Data Required Time	7.513
From	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0
To	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_lcmd_57_s1
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
1.520	1.520	tNET	RR	1	R2C91[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/CLK
1.795	0.275	tC2Q	RR	2624	R2C91[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/Q
3.711	1.915	tNET	RR	1	R8C98[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n27050_s1/I0
4.014	0.303	tINS	RF	32	R8C98[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n27050_s1/F
5.462	1.448	tNET	FF	1	R2C98[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_lcmd_57_s1/PRESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.250	6.250					active clock edge time
6.250	0.000					pclk
6.250	0.000	tCL	RR	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.763	1.513	tNET	RR	1	R2C98[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_lcmd_57_s1/CLK
7.513	-0.250	tSu		1	R2C98[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_lcmd_57_s1

Path Statistics:

Clock Skew	-0.007
Setup Relationship	6.250
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.520, 100.000%
Arrival Data Path Delay	cell: 0.303, 7.694%; route: 3.363, 85.320%; tC2Q: 0.275, 6.986%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.513, 100.000%

Path18

Path Summary:

Slack	2.065
Data Arrival Time	5.455
Data Required Time	7.520
From	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/internel_resetn_s0
To	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/tx_data_en_encode_o_r1_s1
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
1.520	1.520	tNET	RR	1	R50C42[0][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/internel_resetn_s0/CLK
1.795	0.275	tC2Q	RR	595	R50C42[0][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/internel_resetn_s0/Q
4.762	2.966	tNET	RR	1	R67C58[0][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/tx_data_en_encode_o_s12/I3
4.951	0.189	tINS	RR	3	R67C58[0][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/tx_data_en_encode_o_s12/F
5.093	0.142	tNET	RR	1	R67C58[1][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/n3233_s2/I3
5.374	0.281	tINS	RF	1	R67C58[1][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/n3233_s2/F
5.455	0.081	tNET	FF	1	R67C58[2][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/tx_data_en_encode_o_r1_s1/PRESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.250	6.250					active clock edge time
6.250	0.000					pclk
6.250	0.000	tCL	RR	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.770	1.520	tNET	RR	1	R67C58[2][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/tx_data_en_encode_o_r1_s1/CLK
7.520	-0.250	tSu		1	R67C58[2][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/tx_data_en_encode_o_r1_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	6.250
Logic Level	3
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.520, 100.000%
Arrival Data Path Delay	cell: 0.470, 11.940%; route: 3.190, 81.061%; tC2Q: 0.275, 6.999%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.520, 100.000%

Path19

Path Summary:

Slack	1.043
Data Arrival Time	6.463
Data Required Time	7.506
From	line_fifo_inst/fifo_inst/reset_r_1_s0
To	line_fifo_inst/fifo_inst/Equal.rptr_3_s0
Launch Clk	pclk:[F]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
3.200	3.200					active clock edge time
3.200	0.000					pclk
3.200	0.000	tCL	FF	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
4.706	1.506	tNET	FF	1	R64C97[2][A]	line_fifo_inst/fifo_inst/reset_r_1_s0/CLK
5.024	0.319	tC2Q	FF	68	R64C97[2][A]	line_fifo_inst/fifo_inst/reset_r_1_s0/Q
6.463	1.439	tNET	FF	1	R67C101[0][A]	line_fifo_inst/fifo_inst/Equal.rptr_3_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.250	6.250					active clock edge time
6.250	0.000					pclk
6.250	0.000	tCL	RR	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.757	1.507	tNET	RR	1	R67C101[0][A]	line_fifo_inst/fifo_inst/Equal.rptr_3_s0/CLK
7.506	-0.250	tSu		1	R67C101[0][A]	line_fifo_inst/fifo_inst/Equal.rptr_3_s0

Path Statistics:

Clock Skew	0.001
Setup Relationship	3.050
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.506, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.439, 81.874%; tC2Q: 0.319, 18.126%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.507, 100.000%

Path20

Path Summary:

Slack	1.043
Data Arrival Time	6.463
Data Required Time	7.506
From	line_fifo_inst/fifo_inst/reset_r_1_s0
To	line_fifo_inst/fifo_inst/Equal.rptr_4_s0
Launch Clk	pclk:[F]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
3.200	3.200					active clock edge time
3.200	0.000					pclk
3.200	0.000	tCL	FF	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
4.706	1.506	tNET	FF	1	R64C97[2][A]	line_fifo_inst/fifo_inst/reset_r_1_s0/CLK
5.024	0.319	tC2Q	FF	68	R64C97[2][A]	line_fifo_inst/fifo_inst/reset_r_1_s0/Q
6.463	1.439	tNET	FF	1	R67C101[0][B]	line_fifo_inst/fifo_inst/Equal.rptr_4_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.250	6.250					active clock edge time
6.250	0.000					pclk
6.250	0.000	tCL	RR	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.757	1.507	tNET	RR	1	R67C101[0][B]	line_fifo_inst/fifo_inst/Equal.rptr_4_s0/CLK
7.506	-0.250	tSu		1	R67C101[0][B]	line_fifo_inst/fifo_inst/Equal.rptr_4_s0

Path Statistics:

Clock Skew	0.001
Setup Relationship	3.050
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.506, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.439, 81.874%; tC2Q: 0.319, 18.126%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.507, 100.000%

Path21

Path Summary:

Slack	1.047
Data Arrival Time	6.460
Data Required Time	7.506
From	line_fifo_inst/fifo_inst/reset_r_1_s0
To	line_fifo_inst/fifo_inst/Equal.rq2_wptr_3_s0
Launch Clk	pclk:[F]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
3.200	3.200					active clock edge time
3.200	0.000					pclk
3.200	0.000	tCL	FF	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
4.706	1.506	tNET	FF	1	R64C97[2][A]	line_fifo_inst/fifo_inst/reset_r_1_s0/CLK
5.024	0.319	tC2Q	FF	68	R64C97[2][A]	line_fifo_inst/fifo_inst/reset_r_1_s0/Q
6.460	1.436	tNET	FF	1	R70C101[3][A]	line_fifo_inst/fifo_inst/Equal.rq2_wptr_3_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.250	6.250					active clock edge time
6.250	0.000					pclk
6.250	0.000	tCL	RR	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.757	1.507	tNET	RR	1	R70C101[3][A]	line_fifo_inst/fifo_inst/Equal.rq2_wptr_3_s0/CLK
7.506	-0.250	tSu		1	R70C101[3][A]	line_fifo_inst/fifo_inst/Equal.rq2_wptr_3_s0

Path Statistics:

Clock Skew	0.001
Setup Relationship	3.050
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.506, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.436, 81.837%; tC2Q: 0.319, 18.163%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.507, 100.000%

Path22

Path Summary:

Slack	1.050
Data Arrival Time	6.463
Data Required Time	7.513
From	line_fifo_inst/fifo_inst/reset_r_1_s0
To	line_fifo_inst/fifo_inst/Rnum_6_s0
Launch Clk	pclk:[F]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
3.200	3.200					active clock edge time
3.200	0.000					pclk
3.200	0.000	tCL	FF	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
4.706	1.506	tNET	FF	1	R64C97[2][A]	line_fifo_inst/fifo_inst/reset_r_1_s0/CLK
5.024	0.319	tC2Q	FF	68	R64C97[2][A]	line_fifo_inst/fifo_inst/reset_r_1_s0/Q
6.463	1.439	tNET	FF	1	R72C102[0][A]	line_fifo_inst/fifo_inst/Rnum_6_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.250	6.250					active clock edge time
6.250	0.000					pclk
6.250	0.000	tCL	RR	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.763	1.513	tNET	RR	1	R72C102[0][A]	line_fifo_inst/fifo_inst/Rnum_6_s0/CLK
7.513	-0.250	tSu		1	R72C102[0][A]	line_fifo_inst/fifo_inst/Rnum_6_s0

Path Statistics:

Clock Skew	0.008
Setup Relationship	3.050
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.506, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.439, 81.874%; tC2Q: 0.319, 18.126%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.513, 100.000%

Path23

Path Summary:

Slack	1.050
Data Arrival Time	6.463
Data Required Time	7.513
From	line_fifo_inst/fifo_inst/reset_r_1_s0
To	line_fifo_inst/fifo_inst/Rnum_7_s0
Launch Clk	pclk:[F]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
3.200	3.200					active clock edge time
3.200	0.000					pclk
3.200	0.000	tCL	FF	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
4.706	1.506	tNET	FF	1	R64C97[2][A]	line_fifo_inst/fifo_inst/reset_r_1_s0/CLK
5.024	0.319	tC2Q	FF	68	R64C97[2][A]	line_fifo_inst/fifo_inst/reset_r_1_s0/Q
6.463	1.439	tNET	FF	1	R72C102[0][B]	line_fifo_inst/fifo_inst/Rnum_7_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.250	6.250					active clock edge time
6.250	0.000					pclk
6.250	0.000	tCL	RR	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.763	1.513	tNET	RR	1	R72C102[0][B]	line_fifo_inst/fifo_inst/Rnum_7_s0/CLK
7.513	-0.250	tSu		1	R72C102[0][B]	line_fifo_inst/fifo_inst/Rnum_7_s0

Path Statistics:

Clock Skew	0.008
Setup Relationship	3.050
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.506, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.439, 81.874%; tC2Q: 0.319, 18.126%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.513, 100.000%

Path24

Path Summary:

Slack	1.050
Data Arrival Time	6.463
Data Required Time	7.513
From	line_fifo_inst/fifo_inst/reset_r_1_s0
To	line_fifo_inst/fifo_inst/Rnum_8_s0
Launch Clk	pclk:[F]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
3.200	3.200					active clock edge time
3.200	0.000					pclk
3.200	0.000	tCL	FF	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
4.706	1.506	tNET	FF	1	R64C97[2][A]	line_fifo_inst/fifo_inst/reset_r_1_s0/CLK
5.024	0.319	tC2Q	FF	68	R64C97[2][A]	line_fifo_inst/fifo_inst/reset_r_1_s0/Q
6.463	1.439	tNET	FF	1	R72C102[1][A]	line_fifo_inst/fifo_inst/Rnum_8_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.250	6.250					active clock edge time
6.250	0.000					pclk
6.250	0.000	tCL	RR	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.763	1.513	tNET	RR	1	R72C102[1][A]	line_fifo_inst/fifo_inst/Rnum_8_s0/CLK
7.513	-0.250	tSu		1	R72C102[1][A]	line_fifo_inst/fifo_inst/Rnum_8_s0

Path Statistics:

Clock Skew	0.008
Setup Relationship	3.050
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.506, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.439, 81.874%; tC2Q: 0.319, 18.126%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.513, 100.000%

Path25

Path Summary:

Slack	1.050
Data Arrival Time	6.463
Data Required Time	7.513
From	line_fifo_inst/fifo_inst/reset_r_1_s0
To	line_fifo_inst/fifo_inst/Rnum_9_s0
Launch Clk	pclk:[F]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
3.200	3.200					active clock edge time
3.200	0.000					pclk
3.200	0.000	tCL	FF	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
4.706	1.506	tNET	FF	1	R64C97[2][A]	line_fifo_inst/fifo_inst/reset_r_1_s0/CLK
5.024	0.319	tC2Q	FF	68	R64C97[2][A]	line_fifo_inst/fifo_inst/reset_r_1_s0/Q
6.463	1.439	tNET	FF	1	R72C102[1][B]	line_fifo_inst/fifo_inst/Rnum_9_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.250	6.250					active clock edge time
6.250	0.000					pclk
6.250	0.000	tCL	RR	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.763	1.513	tNET	RR	1	R72C102[1][B]	line_fifo_inst/fifo_inst/Rnum_9_s0/CLK
7.513	-0.250	tSu		1	R72C102[1][B]	line_fifo_inst/fifo_inst/Rnum_9_s0

Path Statistics:

Clock Skew	0.008
Setup Relationship	3.050
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.506, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.439, 81.874%; tC2Q: 0.319, 18.126%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.513, 100.000%

Removal Analysis Report

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	0.256
Data Arrival Time	1.178
Data Required Time	0.923
From	frame_read_inst/rst_n_d_1_s0
To	frame_read_inst/h_cnt_3_s1
Launch Clk	Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk:[R]
Latch Clk	Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk
0.368	0.368	tCL	RR	158	PLL_L[1]	Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1
0.970	0.602	tNET	RR	1	R41C21[1][B]	frame_read_inst/rst_n_d_1_s0/CLK
1.100	0.130	tC2Q	RR	25	R41C21[1][B]	frame_read_inst/rst_n_d_1_s0/Q
1.178	0.078	tNET	RR	1	R41C21[0][B]	frame_read_inst/h_cnt_3_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk
0.368	0.368	tCL	RR	158	PLL_L[1]	Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1
0.970	0.602	tNET	RR	1	R41C21[0][B]	frame_read_inst/h_cnt_3_s1/CLK
0.923	-0.048	tHld		1	R41C21[0][B]	frame_read_inst/h_cnt_3_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.602, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.078, 37.662%; tC2Q: 0.130, 62.338%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.602, 100.000%

Path2

Path Summary:

Slack	0.256
Data Arrival Time	0.816
Data Required Time	0.561
From	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/prot_rst_n_s0
To	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/ltssm_go_u_d0_0_s0
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
0.608	0.608	tNET	RR	1	R63C73[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/prot_rst_n_s0/CLK
0.738	0.130	tC2Q	RR	5	R63C73[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/prot_rst_n_s0/Q
0.816	0.078	tNET	RR	1	R63C73[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/ltssm_go_u_d0_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12075	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
0.608	0.608	tNET	RR	1	R63C73[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/ltssm_go_u_d0_0_s0/CLK
0.561	-0.048	tHld		1	R63C73[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/ltssm_go_u_d0_0_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.608, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.078, 37.662%; tC2Q: 0.130, 62.338%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.608, 100.000%

Path3

Path Summary:

Slack	0.314
Data Arrival Time	1.927
Data Required Time	1.613
From	SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/rstn_s0
To	SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wrdata_o_0_s1
Launch Clk	drp_clk:[R]
Latch Clk	drp_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					drp_clk
0.000	0.000	tCL	RR	272	R2C2	SerDes_Top_inst/gtr12_quad_inst0/FABRIC_CM_LIFE_CLK_O
1.660	1.660	tNET	RR	1	R16C77[1][A]	SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/rstn_s0/CLK
1.790	0.130	tC2Q	RR	144	R16C77[1][A]	SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/rstn_s0/Q
1.927	0.137	tNET	RR	1	R24C75[2][B]	SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wrdata_o_0_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					drp_clk
0.000	0.000	tCL	RR	272	R2C2	SerDes_Top_inst/gtr12_quad_inst0/FABRIC_CM_LIFE_CLK_O
1.660	1.660	tNET	RR	1	R24C75[2][B]	SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wrdata_o_0_s1/CLK
1.613	-0.048	tHld		1	R24C75[2][B]	SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wrdata_o_0_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.660, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.137, 51.351%; tC2Q: 0.130, 48.649%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.660, 100.000%

Path4

Path Summary:

Slack	0.314
Data Arrival Time	1.927
Data Required Time	1.613
From	SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/rstn_s0
To	SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wrdata_o_1_s1
Launch Clk	drp_clk:[R]
Latch Clk	drp_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					drp_clk
0.000	0.000	tCL	RR	272	R2C2	SerDes_Top_inst/gtr12_quad_inst0/FABRIC_CM_LIFE_CLK_O
1.660	1.660	tNET	RR	1	R16C77[1][A]	SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/rstn_s0/CLK
1.790	0.130	tC2Q	RR	144	R16C77[1][A]	SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/rstn_s0/Q
1.927	0.137	tNET	RR	1	R24C75[2][A]	SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wrdata_o_1_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					drp_clk
0.000	0.000	tCL	RR	272	R2C2	SerDes_Top_inst/gtr12_quad_inst0/FABRIC_CM_LIFE_CLK_O
1.660	1.660	tNET	RR	1	R24C75[2][A]	SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wrdata_o_1_s1/CLK
1.613	-0.048	tHld		1	R24C75[2][A]	SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wrdata_o_1_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.660, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.137, 51.351%; tC2Q: 0.130, 48.649%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.660, 100.000%

Path5

Path Summary:

Slack	0.314
Data Arrival Time	1.927
Data Required Time	1.613
From	SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/rstn_s0
To	SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wrdata_o_2_s1
Launch Clk	drp_clk:[R]
Latch Clk	drp_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					drp_clk
0.000	0.000	tCL	RR	272	R2C2	SerDes_Top_inst/gtr12_quad_inst0/FABRIC_CM_LIFE_CLK_O
1.660	1.660	tNET	RR	1	R16C77[1][A]	SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/rstn_s0/CLK
1.790	0.130	tC2Q	RR	144	R16C77[1][A]	SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/rstn_s0/Q
1.927	0.137	tNET	RR	1	R24C75[0][B]	SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wrdata_o_2_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					drp_clk
0.000	0.000	tCL	RR	272	R2C2	SerDes_Top_inst/gtr12_quad_inst0/FABRIC_CM_LIFE_CLK_O
1.660	1.660	tNET	RR	1	R24C75[0][B]	SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wrdata_o_2_s1/CLK
1.613	-0.048	tHld		1	R24C75[0][B]	SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wrdata_o_2_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.660, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.137, 51.351%; tC2Q: 0.130, 48.649%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.660, 100.000%

Path6

Path Summary:

Slack	0.314
Data Arrival Time	1.927
Data Required Time	1.613
From	SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/rstn_s0
To	SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wrdata_o_3_s1
Launch Clk	drp_clk:[R]
Latch Clk	drp_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					drp_clk
0.000	0.000	tCL	RR	272	R2C2	SerDes_Top_inst/gtr12_quad_inst0/FABRIC_CM_LIFE_CLK_O
1.660	1.660	tNET	RR	1	R16C77[1][A]	SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/rstn_s0/CLK
1.790	0.130	tC2Q	RR	144	R16C77[1][A]	SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/rstn_s0/Q
1.927	0.137	tNET	RR	1	R24C75[0][A]	SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wrdata_o_3_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					drp_clk
0.000	0.000	tCL	RR	272	R2C2	SerDes_Top_inst/gtr12_quad_inst0/FABRIC_CM_LIFE_CLK_O
1.660	1.660	tNET	RR	1	R24C75[0][A]	SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wrdata_o_3_s1/CLK
1.613	-0.048	tHld		1	R24C75[0][A]	SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wrdata_o_3_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.660, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.137, 51.351%; tC2Q: 0.130, 48.649%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.660, 100.000%

Path7

Path Summary:

Slack	0.314
Data Arrival Time	1.927
Data Required Time	1.613
From	SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/rstn_s0
To	SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wrdata_o_6_s1
Launch Clk	drp_clk:[R]
Latch Clk	drp_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					drp_clk
0.000	0.000	tCL	RR	272	R2C2	SerDes_Top_inst/gtr12_quad_inst0/FABRIC_CM_LIFE_CLK_O
1.660	1.660	tNET	RR	1	R16C77[1][A]	SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/rstn_s0/CLK
1.790	0.130	tC2Q	RR	144	R16C77[1][A]	SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/rstn_s0/Q
1.927	0.137	tNET	RR	1	R24C75[3][B]	SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wrdata_o_6_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					drp_clk
0.000	0.000	tCL	RR	272	R2C2	SerDes_Top_inst/gtr12_quad_inst0/FABRIC_CM_LIFE_CLK_O
1.660	1.660	tNET	RR	1	R24C75[3][B]	SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wrdata_o_6_s1/CLK
1.613	-0.048	tHld		1	R24C75[3][B]	SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wrdata_o_6_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.660, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.137, 51.351%; tC2Q: 0.130, 48.649%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.660, 100.000%

Path8

Path Summary:

Slack	0.314
Data Arrival Time	1.927
Data Required Time	1.613
From	SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/rstn_s0
To	SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wrdata_o_7_s1
Launch Clk	drp_clk:[R]
Latch Clk	drp_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					drp_clk
0.000	0.000	tCL	RR	272	R2C2	SerDes_Top_inst/gtr12_quad_inst0/FABRIC_CM_LIFE_CLK_O
1.660	1.660	tNET	RR	1	R16C77[1][A]	SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/rstn_s0/CLK
1.790	0.130	tC2Q	RR	144	R16C77[1][A]	SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/rstn_s0/Q
1.927	0.137	tNET	RR	1	R24C75[3][A]	SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wrdata_o_7_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					drp_clk
0.000	0.000	tCL	RR	272	R2C2	SerDes_Top_inst/gtr12_quad_inst0/FABRIC_CM_LIFE_CLK_O
1.660	1.660	tNET	RR	1	R24C75[3][A]	SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wrdata_o_7_s1/CLK
1.613	-0.048	tHld		1	R24C75[3][A]	SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wrdata_o_7_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.660, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.137, 51.351%; tC2Q: 0.130, 48.649%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.660, 100.000%

Path9

Path Summary:

Slack	0.314
Data Arrival Time	1.927
Data Required Time	1.613
From	SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/rstn_s0
To	SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_addr_o_3_s1
Launch Clk	drp_clk:[R]
Latch Clk	drp_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					drp_clk
0.000	0.000	tCL	RR	272	R2C2	SerDes_Top_inst/gtr12_quad_inst0/FABRIC_CM_LIFE_CLK_O
1.660	1.660	tNET	RR	1	R16C77[1][A]	SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/rstn_s0/CLK
1.790	0.130	tC2Q	RR	144	R16C77[1][A]	SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/rstn_s0/Q
1.927	0.137	tNET	RR	1	R24C75[1][A]	SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_addr_o_3_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					drp_clk
0.000	0.000	tCL	RR	272	R2C2	SerDes_Top_inst/gtr12_quad_inst0/FABRIC_CM_LIFE_CLK_O
1.660	1.660	tNET	RR	1	R24C75[1][A]	SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_addr_o_3_s1/CLK
1.613	-0.048	tHld		1	R24C75[1][A]	SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_addr_o_3_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.660, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.137, 51.351%; tC2Q: 0.130, 48.649%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.660, 100.000%

Path10

Path Summary:

Slack	0.314
Data Arrival Time	1.927
Data Required Time	1.613
From	SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/rstn_s0
To	SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_addr_o_4_s1
Launch Clk	drp_clk:[R]
Latch Clk	drp_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					drp_clk
0.000	0.000	tCL	RR	272	R2C2	SerDes_Top_inst/gtr12_quad_inst0/FABRIC_CM_LIFE_CLK_O
1.660	1.660	tNET	RR	1	R16C77[1][A]	SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/rstn_s0/CLK
1.790	0.130	tC2Q	RR	144	R16C77[1][A]	SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/rstn_s0/Q
1.927	0.137	tNET	RR	1	R24C75[1][B]	SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_addr_o_4_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					drp_clk
0.000	0.000	tCL	RR	272	R2C2	SerDes_Top_inst/gtr12_quad_inst0/FABRIC_CM_LIFE_CLK_O
1.660	1.660	tNET	RR	1	R24C75[1][B]	SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_addr_o_4_s1/CLK
1.613	-0.048	tHld		1	R24C75[1][B]	SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_addr_o_4_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.660, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.137, 51.351%; tC2Q: 0.130, 48.649%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.660, 100.000%

Path11

Path Summary:

Slack	0.347
Data Arrival Time	1.400
Data Required Time	1.053
From	testpattern_yuv_inst/rst_n_local_s0
To	testpattern_yuv_inst/yuv_data_57_s0
Launch Clk	rgb_clk:[R]
Latch Clk	rgb_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rgb_clk
0.000	0.000	tCL	RR	431	PLL_L[1]	Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
1.097	1.097	tNET	RR	1	R31C14[0][B]	testpattern_yuv_inst/rst_n_local_s0/CLK
1.227	0.130	tC2Q	RR	198	R31C14[0][B]	testpattern_yuv_inst/rst_n_local_s0/Q
1.400	0.173	tNET	RR	1	R31C11[1][A]	testpattern_yuv_inst/yuv_data_57_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rgb_clk
0.000	0.000	tCL	RR	431	PLL_L[1]	Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
1.101	1.101	tNET	RR	1	R31C11[1][A]	testpattern_yuv_inst/yuv_data_57_s0/CLK
1.053	-0.048	tHld		1	R31C11[1][A]	testpattern_yuv_inst/yuv_data_57_s0

Path Statistics:

Clock Skew	0.004
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.097, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.173, 57.143%; tC2Q: 0.130, 42.857%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.101, 100.000%

Path12

Path Summary:

Slack	0.347
Data Arrival Time	1.270
Data Required Time	0.923
From	frame_read_inst/rst_n_d_1_s0
To	frame_read_inst/h_cnt_0_s1
Launch Clk	Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk:[R]
Latch Clk	Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk
0.368	0.368	tCL	RR	158	PLL_L[1]	Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1
0.970	0.602	tNET	RR	1	R41C21[1][B]	frame_read_inst/rst_n_d_1_s0/CLK
1.100	0.130	tC2Q	RR	25	R41C21[1][B]	frame_read_inst/rst_n_d_1_s0/Q
1.270	0.170	tNET	RR	1	R42C21[2][B]	frame_read_inst/h_cnt_0_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk
0.368	0.368	tCL	RR	158	PLL_L[1]	Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1
0.970	0.602	tNET	RR	1	R42C21[2][B]	frame_read_inst/h_cnt_0_s1/CLK
0.923	-0.048	tHld		1	R42C21[2][B]	frame_read_inst/h_cnt_0_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.602, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.170, 56.757%; tC2Q: 0.130, 43.243%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.602, 100.000%

Path13

Path Summary:

Slack	0.347
Data Arrival Time	1.270
Data Required Time	0.923
From	frame_read_inst/rst_n_d_1_s0
To	frame_read_inst/h_cnt_1_s1
Launch Clk	Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk:[R]
Latch Clk	Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk
0.368	0.368	tCL	RR	158	PLL_L[1]	Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1
0.970	0.602	tNET	RR	1	R41C21[1][B]	frame_read_inst/rst_n_d_1_s0/CLK
1.100	0.130	tC2Q	RR	25	R41C21[1][B]	frame_read_inst/rst_n_d_1_s0/Q
1.270	0.170	tNET	RR	1	R42C21[2][A]	frame_read_inst/h_cnt_1_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk
0.368	0.368	tCL	RR	158	PLL_L[1]	Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1
0.970	0.602	tNET	RR	1	R42C21[2][A]	frame_read_inst/h_cnt_1_s1/CLK
0.923	-0.048	tHld		1	R42C21[2][A]	frame_read_inst/h_cnt_1_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.602, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.170, 56.757%; tC2Q: 0.130, 43.243%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.602, 100.000%

Path14

Path Summary:

Slack	0.347
Data Arrival Time	1.270
Data Required Time	0.923
From	frame_read_inst/rst_n_d_1_s0
To	frame_read_inst/h_cnt_2_s1
Launch Clk	Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk:[R]
Latch Clk	Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk
0.368	0.368	tCL	RR	158	PLL_L[1]	Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1
0.970	0.602	tNET	RR	1	R41C21[1][B]	frame_read_inst/rst_n_d_1_s0/CLK
1.100	0.130	tC2Q	RR	25	R41C21[1][B]	frame_read_inst/rst_n_d_1_s0/Q
1.270	0.170	tNET	RR	1	R42C21[3][A]	frame_read_inst/h_cnt_2_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk
0.368	0.368	tCL	RR	158	PLL_L[1]	Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1
0.970	0.602	tNET	RR	1	R42C21[3][A]	frame_read_inst/h_cnt_2_s1/CLK
0.923	-0.048	tHld		1	R42C21[3][A]	frame_read_inst/h_cnt_2_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.602, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.170, 56.757%; tC2Q: 0.130, 43.243%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.602, 100.000%

Path15

Path Summary:

Slack	0.347
Data Arrival Time	1.270
Data Required Time	0.923
From	frame_read_inst/rst_n_d_1_s0
To	frame_read_inst/h_cnt_4_s1
Launch Clk	Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk:[R]
Latch Clk	Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk
0.368	0.368	tCL	RR	158	PLL_L[1]	Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1
0.970	0.602	tNET	RR	1	R41C21[1][B]	frame_read_inst/rst_n_d_1_s0/CLK
1.100	0.130	tC2Q	RR	25	R41C21[1][B]	frame_read_inst/rst_n_d_1_s0/Q
1.270	0.170	tNET	RR	1	R42C21[0][B]	frame_read_inst/h_cnt_4_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk
0.368	0.368	tCL	RR	158	PLL_L[1]	Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1
0.970	0.602	tNET	RR	1	R42C21[0][B]	frame_read_inst/h_cnt_4_s1/CLK
0.923	-0.048	tHld		1	R42C21[0][B]	frame_read_inst/h_cnt_4_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.602, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.170, 56.757%; tC2Q: 0.130, 43.243%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.602, 100.000%

Path16

Path Summary:

Slack	0.347
Data Arrival Time	1.270
Data Required Time	0.923
From	frame_read_inst/rst_n_d_1_s0
To	frame_read_inst/h_cnt_5_s1
Launch Clk	Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk:[R]
Latch Clk	Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk
0.368	0.368	tCL	RR	158	PLL_L[1]	Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1
0.970	0.602	tNET	RR	1	R41C21[1][B]	frame_read_inst/rst_n_d_1_s0/CLK
1.100	0.130	tC2Q	RR	25	R41C21[1][B]	frame_read_inst/rst_n_d_1_s0/Q
1.270	0.170	tNET	RR	1	R42C21[1][B]	frame_read_inst/h_cnt_5_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk
0.368	0.368	tCL	RR	158	PLL_L[1]	Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1
0.970	0.602	tNET	RR	1	R42C21[1][B]	frame_read_inst/h_cnt_5_s1/CLK
0.923	-0.048	tHld		1	R42C21[1][B]	frame_read_inst/h_cnt_5_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.602, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.170, 56.757%; tC2Q: 0.130, 43.243%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.602, 100.000%

Path17

Path Summary:

Slack	0.347
Data Arrival Time	1.270
Data Required Time	0.923
From	frame_read_inst/rst_n_d_1_s0
To	frame_read_inst/h_cnt_6_s1
Launch Clk	Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk:[R]
Latch Clk	Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk
0.368	0.368	tCL	RR	158	PLL_L[1]	Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1
0.970	0.602	tNET	RR	1	R41C21[1][B]	frame_read_inst/rst_n_d_1_s0/CLK
1.100	0.130	tC2Q	RR	25	R41C21[1][B]	frame_read_inst/rst_n_d_1_s0/Q
1.270	0.170	tNET	RR	1	R42C21[1][A]	frame_read_inst/h_cnt_6_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk
0.368	0.368	tCL	RR	158	PLL_L[1]	Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1
0.970	0.602	tNET	RR	1	R42C21[1][A]	frame_read_inst/h_cnt_6_s1/CLK
0.923	-0.048	tHld		1	R42C21[1][A]	frame_read_inst/h_cnt_6_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.602, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.170, 56.757%; tC2Q: 0.130, 43.243%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.602, 100.000%

Path18

Path Summary:

Slack	0.353
Data Arrival Time	1.966
Data Required Time	1.613
From	SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/rstn_s0
To	SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/drp_addr_serdes_4_s0
Launch Clk	drp_clk:[R]
Latch Clk	drp_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					drp_clk
0.000	0.000	tCL	RR	272	R2C2	SerDes_Top_inst/gtr12_quad_inst0/FABRIC_CM_LIFE_CLK_O
1.660	1.660	tNET	RR	1	R16C77[1][A]	SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/rstn_s0/CLK
1.790	0.130	tC2Q	RR	144	R16C77[1][A]	SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/rstn_s0/Q
1.966	0.176	tNET	RR	1	R17C75[0][A]	SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/drp_addr_serdes_4_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					drp_clk
0.000	0.000	tCL	RR	272	R2C2	SerDes_Top_inst/gtr12_quad_inst0/FABRIC_CM_LIFE_CLK_O
1.660	1.660	tNET	RR	1	R17C75[0][A]	SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/drp_addr_serdes_4_s0/CLK
1.613	-0.048	tHld		1	R17C75[0][A]	SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/drp_addr_serdes_4_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.660, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.176, 57.522%; tC2Q: 0.130, 42.478%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.660, 100.000%

Path19

Path Summary:

Slack	0.355
Data Arrival Time	1.285
Data Required Time	0.930
From	frame_read_inst/rst_n_d_1_s0
To	frame_read_inst/v_cnt_0_s1
Launch Clk	Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk:[R]
Latch Clk	Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk
0.368	0.368	tCL	RR	158	PLL_L[1]	Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1
0.970	0.602	tNET	RR	1	R41C21[1][B]	frame_read_inst/rst_n_d_1_s0/CLK
1.100	0.130	tC2Q	RR	25	R41C21[1][B]	frame_read_inst/rst_n_d_1_s0/Q
1.285	0.185	tNET	RR	1	R40C23[0][A]	frame_read_inst/v_cnt_0_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk
0.368	0.368	tCL	RR	158	PLL_L[1]	Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1
0.977	0.609	tNET	RR	1	R40C23[0][A]	frame_read_inst/v_cnt_0_s1/CLK
0.930	-0.048	tHld		1	R40C23[0][A]	frame_read_inst/v_cnt_0_s1

Path Statistics:

Clock Skew	0.007
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.602, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.185, 58.857%; tC2Q: 0.130, 41.143%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.609, 100.000%

Path20

Path Summary:

Slack	0.355
Data Arrival Time	1.285
Data Required Time	0.930
From	frame_read_inst/rst_n_d_1_s0
To	frame_read_inst/v_cnt_1_s1
Launch Clk	Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk:[R]
Latch Clk	Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk
0.368	0.368	tCL	RR	158	PLL_L[1]	Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1
0.970	0.602	tNET	RR	1	R41C21[1][B]	frame_read_inst/rst_n_d_1_s0/CLK
1.100	0.130	tC2Q	RR	25	R41C21[1][B]	frame_read_inst/rst_n_d_1_s0/Q
1.285	0.185	tNET	RR	1	R40C23[0][B]	frame_read_inst/v_cnt_1_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk
0.368	0.368	tCL	RR	158	PLL_L[1]	Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1
0.977	0.609	tNET	RR	1	R40C23[0][B]	frame_read_inst/v_cnt_1_s1/CLK
0.930	-0.048	tHld		1	R40C23[0][B]	frame_read_inst/v_cnt_1_s1

Path Statistics:

Clock Skew	0.007
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.602, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.185, 58.857%; tC2Q: 0.130, 41.143%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.609, 100.000%

Path21

Path Summary:

Slack	0.355
Data Arrival Time	1.285
Data Required Time	0.930
From	frame_read_inst/rst_n_d_1_s0
To	frame_read_inst/v_cnt_4_s1
Launch Clk	Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk:[R]
Latch Clk	Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk
0.368	0.368	tCL	RR	158	PLL_L[1]	Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1
0.970	0.602	tNET	RR	1	R41C21[1][B]	frame_read_inst/rst_n_d_1_s0/CLK
1.100	0.130	tC2Q	RR	25	R41C21[1][B]	frame_read_inst/rst_n_d_1_s0/Q
1.285	0.185	tNET	RR	1	R40C23[1][A]	frame_read_inst/v_cnt_4_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk
0.368	0.368	tCL	RR	158	PLL_L[1]	Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1
0.977	0.609	tNET	RR	1	R40C23[1][A]	frame_read_inst/v_cnt_4_s1/CLK
0.930	-0.048	tHld		1	R40C23[1][A]	frame_read_inst/v_cnt_4_s1

Path Statistics:

Clock Skew	0.007
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.602, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.185, 58.857%; tC2Q: 0.130, 41.143%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.609, 100.000%

Path22

Path Summary:

Slack	0.356
Data Arrival Time	1.969
Data Required Time	1.613
From	SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/rstn_s0
To	SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_addr_o_0_s1
Launch Clk	drp_clk:[R]
Latch Clk	drp_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					drp_clk
0.000	0.000	tCL	RR	272	R2C2	SerDes_Top_inst/gtr12_quad_inst0/FABRIC_CM_LIFE_CLK_O
1.660	1.660	tNET	RR	1	R16C77[1][A]	SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/rstn_s0/CLK
1.790	0.130	tC2Q	RR	144	R16C77[1][A]	SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/rstn_s0/Q
1.969	0.179	tNET	RR	1	R15C75[2][A]	SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_addr_o_0_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					drp_clk
0.000	0.000	tCL	RR	272	R2C2	SerDes_Top_inst/gtr12_quad_inst0/FABRIC_CM_LIFE_CLK_O
1.660	1.660	tNET	RR	1	R15C75[2][A]	SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_addr_o_0_s1/CLK
1.613	-0.048	tHld		1	R15C75[2][A]	SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_addr_o_0_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.660, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.179, 58.017%; tC2Q: 0.130, 41.983%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.660, 100.000%

Path23

Path Summary:

Slack	0.356
Data Arrival Time	1.969
Data Required Time	1.613
From	SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/rstn_s0
To	SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_addr_o_1_s1
Launch Clk	drp_clk:[R]
Latch Clk	drp_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					drp_clk
0.000	0.000	tCL	RR	272	R2C2	SerDes_Top_inst/gtr12_quad_inst0/FABRIC_CM_LIFE_CLK_O
1.660	1.660	tNET	RR	1	R16C77[1][A]	SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/rstn_s0/CLK
1.790	0.130	tC2Q	RR	144	R16C77[1][A]	SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/rstn_s0/Q
1.969	0.179	tNET	RR	1	R15C75[2][B]	SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_addr_o_1_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					drp_clk
0.000	0.000	tCL	RR	272	R2C2	SerDes_Top_inst/gtr12_quad_inst0/FABRIC_CM_LIFE_CLK_O
1.660	1.660	tNET	RR	1	R15C75[2][B]	SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_addr_o_1_s1/CLK
1.613	-0.048	tHld		1	R15C75[2][B]	SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_addr_o_1_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.660, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.179, 58.017%; tC2Q: 0.130, 41.983%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.660, 100.000%

Path24

Path Summary:

Slack	0.356
Data Arrival Time	1.969
Data Required Time	1.613
From	SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/rstn_s0
To	SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_addr_o_2_s1
Launch Clk	drp_clk:[R]
Latch Clk	drp_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					drp_clk
0.000	0.000	tCL	RR	272	R2C2	SerDes_Top_inst/gtr12_quad_inst0/FABRIC_CM_LIFE_CLK_O
1.660	1.660	tNET	RR	1	R16C77[1][A]	SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/rstn_s0/CLK
1.790	0.130	tC2Q	RR	144	R16C77[1][A]	SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/rstn_s0/Q
1.969	0.179	tNET	RR	1	R15C75[0][A]	SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_addr_o_2_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					drp_clk
0.000	0.000	tCL	RR	272	R2C2	SerDes_Top_inst/gtr12_quad_inst0/FABRIC_CM_LIFE_CLK_O
1.660	1.660	tNET	RR	1	R15C75[0][A]	SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_addr_o_2_s1/CLK
1.613	-0.048	tHld		1	R15C75[0][A]	SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_addr_o_2_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.660, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.179, 58.017%; tC2Q: 0.130, 41.983%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.660, 100.000%

Path25

Path Summary:

Slack	0.356
Data Arrival Time	1.969
Data Required Time	1.613
From	SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/rstn_s0
To	SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/drp_addr_serdes_0_s0
Launch Clk	drp_clk:[R]
Latch Clk	drp_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					drp_clk
0.000	0.000	tCL	RR	272	R2C2	SerDes_Top_inst/gtr12_quad_inst0/FABRIC_CM_LIFE_CLK_O
1.660	1.660	tNET	RR	1	R16C77[1][A]	SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/rstn_s0/CLK
1.790	0.130	tC2Q	RR	144	R16C77[1][A]	SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/rstn_s0/Q
1.969	0.179	tNET	RR	1	R15C75[1][A]	SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/drp_addr_serdes_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					drp_clk
0.000	0.000	tCL	RR	272	R2C2	SerDes_Top_inst/gtr12_quad_inst0/FABRIC_CM_LIFE_CLK_O
1.660	1.660	tNET	RR	1	R15C75[1][A]	SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/drp_addr_serdes_0_s0/CLK
1.613	-0.048	tHld		1	R15C75[1][A]	SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/drp_addr_serdes_0_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.660, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.179, 58.017%; tC2Q: 0.130, 41.983%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.660, 100.000%

Minimum Pulse Width Report:

Report Command:report_min_pulse_width -nworst 10 -detail

MPW1

MPW Summary:

Slack:	0.817
Actual Width:	1.593
Required Width:	0.776
Type:	Low Pulse Width
Clock:	Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk
Objects:	u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.mem_Small.mem_0_4_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
3.361	0.000			active clock edge time
3.361	0.000			Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk
4.412	1.051	tCL	FF	Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1
6.284	1.872	tNET	FF	u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.mem_Small.mem_0_4_s/CLKB

Early clock Path:

AT	DELAY	TYPE	RF	NODE
6.723	0.000			active clock edge time
6.723	0.000			Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk
7.091	0.368	tCL	RR	Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1
7.877	0.787	tNET	RR	u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.mem_Small.mem_0_4_s/CLKB

MPW2

MPW Summary:

Slack:	0.819
Actual Width:	1.595
Required Width:	0.776
Type:	High Pulse Width
Clock:	Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk
Objects:	u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.mem_Small.mem_0_4_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk
1.051	1.051	tCL	RR	Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1
2.925	1.875	tNET	RR	u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.mem_Small.mem_0_4_s/CLKB

Early clock Path:

AT	DELAY	TYPE	RF	NODE
3.361	0.000			active clock edge time
3.361	0.000			Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk
3.729	0.368	tCL	FF	Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1
4.521	0.791	tNET	FF	u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.mem_Small.mem_0_4_s/CLKB

MPW3

MPW Summary:

Slack:	0.821
Actual Width:	1.596
Required Width:	0.776
Type:	Low Pulse Width
Clock:	Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk
Objects:	u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.mem_Small.mem_0_2_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
3.361	0.000			active clock edge time
3.361	0.000			Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk
4.412	1.051	tCL	FF	Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1
6.277	1.865	tNET	FF	u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.mem_Small.mem_0_2_s/CLKB

Early clock Path:

AT	DELAY	TYPE	RF	NODE
6.723	0.000			active clock edge time
6.723	0.000			Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk
7.091	0.368	tCL	RR	Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1
7.874	0.783	tNET	RR	u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.mem_Small.mem_0_2_s/CLKB

MPW4

MPW Summary:

Slack:	0.822
Actual Width:	1.598
Required Width:	0.776
Type:	High Pulse Width
Clock:	Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk
Objects:	u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.mem_Small.mem_0_2_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk
1.051	1.051	tCL	RR	Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1
2.919	1.868	tNET	RR	u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.mem_Small.mem_0_2_s/CLKB

Early clock Path:

AT	DELAY	TYPE	RF	NODE
3.361	0.000			active clock edge time
3.361	0.000			Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk
3.729	0.368	tCL	FF	Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1
4.517	0.787	tNET	FF	u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.mem_Small.mem_0_2_s/CLKB

MPW5

MPW Summary:

Slack:	0.824
Actual Width:	1.600
Required Width:	0.776
Type:	Low Pulse Width
Clock:	Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk
Objects:	u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.mem_Small.mem_0_6_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
3.361	0.000			active clock edge time
3.361	0.000			Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk
4.412	1.051	tCL	FF	Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1
6.271	1.858	tNET	FF	u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.mem_Small.mem_0_6_s/CLKB

Early clock Path:

AT	DELAY	TYPE	RF	NODE
6.723	0.000			active clock edge time
6.723	0.000			Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk
7.091	0.368	tCL	RR	Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1
7.870	0.779	tNET	RR	u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.mem_Small.mem_0_6_s/CLKB

MPW6

MPW Summary:

Slack:	0.826
Actual Width:	1.601
Required Width:	0.776
Type:	High Pulse Width
Clock:	Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk
Objects:	u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.mem_Small.mem_0_6_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk
1.051	1.051	tCL	RR	Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1
2.912	1.861	tNET	RR	u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.mem_Small.mem_0_6_s/CLKB

Early clock Path:

AT	DELAY	TYPE	RF	NODE
3.361	0.000			active clock edge time
3.361	0.000			Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk
3.729	0.368	tCL	FF	Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1
4.513	0.784	tNET	FF	u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.mem_Small.mem_0_6_s/CLKB

MPW7

MPW Summary:

Slack:	0.963
Actual Width:	1.739
Required Width:	0.776
Type:	Low Pulse Width
Clock:	rgb_clk
Objects:	u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.mem_Big.mem_0_7_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
3.125	0.000			active clock edge time
3.125	0.000			rgb_clk
3.125	0.000	tCL	FF	Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
5.615	2.490	tNET	FF	u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.mem_Big.mem_0_7_s/CLKA

Early clock Path:

AT	DELAY	TYPE	RF	NODE
6.250	0.000			active clock edge time
6.250	0.000			rgb_clk
6.250	0.000	tCL	RR	Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
7.354	1.104	tNET	RR	u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.mem_Big.mem_0_7_s/CLKA

MPW8

MPW Summary:

Slack:	0.965
Actual Width:	1.741
Required Width:	0.776
Type:	High Pulse Width
Clock:	rgb_clk
Objects:	u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.mem_Big.mem_0_7_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			rgb_clk
0.000	0.000	tCL	RR	Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
2.493	2.493	tNET	RR	u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.mem_Big.mem_0_7_s/CLKA

Early clock Path:

AT	DELAY	TYPE	RF	NODE
3.125	0.000			active clock edge time
3.125	0.000			rgb_clk
3.125	0.000	tCL	FF	Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
4.234	1.109	tNET	FF	u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.mem_Big.mem_0_7_s/CLKA

MPW9

MPW Summary:

Slack:	0.966
Actual Width:	1.742
Required Width:	0.776
Type:	Low Pulse Width
Clock:	rgb_clk
Objects:	u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.mem_Big.mem_0_0_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
3.125	0.000			active clock edge time
3.125	0.000			rgb_clk
3.125	0.000	tCL	FF	Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
5.609	2.484	tNET	FF	u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.mem_Big.mem_0_0_s/CLKA

Early clock Path:

AT	DELAY	TYPE	RF	NODE
6.250	0.000			active clock edge time
6.250	0.000			rgb_clk
6.250	0.000	tCL	RR	Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
7.351	1.101	tNET	RR	u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.mem_Big.mem_0_0_s/CLKA

MPW10

MPW Summary:

Slack:	0.966
Actual Width:	1.742
Required Width:	0.776
Type:	Low Pulse Width
Clock:	rgb_clk
Objects:	u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.mem_Big.mem_0_1_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
3.125	0.000			active clock edge time
3.125	0.000			rgb_clk
3.125	0.000	tCL	FF	Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
5.609	2.484	tNET	FF	u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.mem_Big.mem_0_1_s/CLKA

Early clock Path:

AT	DELAY	TYPE	RF	NODE
6.250	0.000			active clock edge time
6.250	0.000			rgb_clk
6.250	0.000	tCL	RR	Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
7.351	1.101	tNET	RR	u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.mem_Big.mem_0_1_s/CLKA

High Fanout Nets Report:

Report Command:report_high_fanout_nets -max_nets 10

FANOUT	NET NAME	WORST SLACK	MAX DELAY
12075	pclk	0.066	1.876
3995	dma_clk	1.769	1.875
2624	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0	0.066	2.012
1622	SerDes_Top_inst/q0_lane1_fabric_rx_clk	0.553	2.495
954	UserLayer_top_inst/rst_n_d[1]	3.225	2.519
868	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/rx_reset_n	1.903	2.898
625	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/fast_reset_n	1.748	3.138
595	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/internel_resetn	1.352	3.167
470	clk_24m_d	37.308	2.207
431	rgb_clk	1.509	2.493

Route Congestions Report:

Report Command:report_route_congestion -max_grids 10

GRID LOC	ROUTE CONGESTIONS
R32C115	95.83%
R23C82	91.67%
R30C114	90.28%
R32C116	90.28%
R69C82	90.28%
R24C84	90.28%
R25C83	90.28%
R23C83	88.89%
R23C84	88.89%
R33C113	87.50%

Timing Exceptions Report:

Setup Analysis Report

Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Hold Analysis Report

Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Recovery Analysis Report

Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Removal Analysis Report

Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Timing Constraints Report:

SDC Command Type	State	Detail Command
TC_CLOCK	Actived	create_clock -name pclk -period 6.25 -waveform {0 3.2} [get_nets {pclk}]
TC_CLOCK	Actived	create_clock -name q0_lane1_fabric_rx_clk -period 6.25 -waveform {0 3.2} [get_nets {SerDes_Top_inst/q0_lane1_fabric_rx_clk}]
TC_CLOCK	Actived	create_clock -name drp_clk -period 10 -waveform {0 5} [get_nets {SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst_drp_clk_o[1]}]
TC_CLOCK	Actived	create_clock -name clk_24m -period 41.667 -waveform {0 20.834} [get_nets {clk_24m}]
TC_CLOCK	Actived	create_clock -name sys_clk -period 5 -waveform {0 2.5} [get_nets {sys_clk}]
TC_CLOCK	Actived	create_clock -name rgb_clk -period 6.25 -waveform {0 3.125} [get_nets {rgb_clk}]
TC_CLOCK	Actived	create_clock -name dma_clk -period 7.273 -waveform {0 3.636} [get_nets {dma_clk}]
TC_CLOCK	Actived	create_clock -name memory_clk -period 1.818 -waveform {0 0.909} [get_nets {memory_clk}]
TC_CLOCK_GROUP	Actived	set_clock_groups -asynchronous -group [get_clocks {pclk}]
TC_CLOCK_GROUP	Actived	set_clock_groups -asynchronous -group [get_clocks {q0_lane1_fabric_rx_clk}]
TC_CLOCK_GROUP	Actived	set_clock_groups -asynchronous -group [get_clocks {drp_clk}]
TC_CLOCK_GROUP	Actived	set_clock_groups -asynchronous -group [get_clocks {sys_clk}]
TC_CLOCK_GROUP	Actived	set_clock_groups -asynchronous -group [get_clocks {rgb_clk}]
TC_CLOCK_GROUP	Actived	set_clock_groups -asynchronous -group [get_clocks {dma_clk}]
TC_CLOCK_GROUP	Actived	set_clock_groups -asynchronous -group [get_clocks {clk_24m}]
TC_CLOCK_GROUP	Actived	set_clock_groups -asynchronous -group [get_clocks {memory_clk}]
TC_REPORT_TIMING	Actived	report_timing -setup -max_paths 100 -max_common_paths 1