Synthesis Messages

Report Title	GowinSynthesis Report
Design File	E:\Gowin_haogang\project\Gowin_USB3_2_Ref\Gowin_USB3_2_UVC_BULK_Ref\release\Gowin_USB3_2_GEN2_UVC_BULK_Ref_DK_USB_GW5AT_LV60UG225_V1.0\prj\src\UVCDefine.v E:\Gowin_haogang\project\Gowin_USB3_2_Ref\Gowin_USB3_2_UVC_BULK_Ref\release\Gowin_USB3_2_GEN2_UVC_BULK_Ref_DK_USB_GW5AT_LV60UG225_V1.0\prj\src\ddr3_memory_interface0\ddr3_memory_interface.v E:\Gowin_haogang\project\Gowin_USB3_2_Ref\Gowin_USB3_2_UVC_BULK_Ref\release\Gowin_USB3_2_GEN2_UVC_BULK_Ref_DK_USB_GW5AT_LV60UG225_V1.0\prj\src\ddr_pll\ddr_pll.v E:\Gowin_haogang\project\Gowin_USB3_2_Ref\Gowin_USB3_2_UVC_BULK_Ref\release\Gowin_USB3_2_GEN2_UVC_BULK_Ref_DK_USB_GW5AT_LV60UG225_V1.0\prj\src\ddr_pll\ddr_pll_mod.v E:\Gowin_haogang\project\Gowin_USB3_2_Ref\Gowin_USB3_2_UVC_BULK_Ref\release\Gowin_USB3_2_GEN2_UVC_BULK_Ref_DK_USB_GW5AT_LV60UG225_V1.0\prj\src\debounce\debounce.v E:\Gowin_haogang\project\Gowin_USB3_2_Ref\Gowin_USB3_2_UVC_BULK_Ref\release\Gowin_USB3_2_GEN2_UVC_BULK_Ref_DK_USB_GW5AT_LV60UG225_V1.0\prj\src\frame_read\frame_read.v E:\Gowin_haogang\project\Gowin_USB3_2_Ref\Gowin_USB3_2_UVC_BULK_Ref\release\Gowin_USB3_2_GEN2_UVC_BULK_Ref_DK_USB_GW5AT_LV60UG225_V1.0\prj\src\gowin_pll\gowin_pll.v E:\Gowin_haogang\project\Gowin_USB3_2_Ref\Gowin_USB3_2_UVC_BULK_Ref\release\Gowin_USB3_2_GEN2_UVC_BULK_Ref_DK_USB_GW5AT_LV60UG225_V1.0\prj\src\gowin_pll\gowin_pll_mod.v E:\Gowin_haogang\project\Gowin_USB3_2_Ref\Gowin_USB3_2_UVC_BULK_Ref\release\Gowin_USB3_2_GEN2_UVC_BULK_Ref_DK_USB_GW5AT_LV60UG225_V1.0\prj\src\gowin_pll_serdes\gowin_pll_serdes.v E:\Gowin_haogang\project\Gowin_USB3_2_Ref\Gowin_USB3_2_UVC_BULK_Ref\release\Gowin_USB3_2_GEN2_UVC_BULK_Ref_DK_USB_GW5AT_LV60UG225_V1.0\prj\src\gowin_pll_serdes\gowin_pll_serdes_mod.v E:\Gowin_haogang\project\Gowin_USB3_2_Ref\Gowin_USB3_2_UVC_BULK_Ref\release\Gowin_USB3_2_GEN2_UVC_BULK_Ref_DK_USB_GW5AT_LV60UG225_V1.0\prj\src\i2c_master\i2c_master.v E:\Gowin_haogang\project\Gowin_USB3_2_Ref\Gowin_USB3_2_UVC_BULK_Ref\release\Gowin_USB3_2_GEN2_UVC_BULK_Ref_DK_USB_GW5AT_LV60UG225_V1.0\prj\src\iic\gw_i2c_master.v E:\Gowin_haogang\project\Gowin_USB3_2_Ref\Gowin_USB3_2_UVC_BULK_Ref\release\Gowin_USB3_2_GEN2_UVC_BULK_Ref_DK_USB_GW5AT_LV60UG225_V1.0\prj\src\iic\iic_controller.v E:\Gowin_haogang\project\Gowin_USB3_2_Ref\Gowin_USB3_2_UVC_BULK_Ref\release\Gowin_USB3_2_GEN2_UVC_BULK_Ref_DK_USB_GW5AT_LV60UG225_V1.0\prj\src\iic\master_sram_iic.v E:\Gowin_haogang\project\Gowin_USB3_2_Ref\Gowin_USB3_2_UVC_BULK_Ref\release\Gowin_USB3_2_GEN2_UVC_BULK_Ref_DK_USB_GW5AT_LV60UG225_V1.0\prj\src\line_fifo\line_fifo.v E:\Gowin_haogang\project\Gowin_USB3_2_Ref\Gowin_USB3_2_UVC_BULK_Ref\release\Gowin_USB3_2_GEN2_UVC_BULK_Ref_DK_USB_GW5AT_LV60UG225_V1.0\prj\src\pll_init.v E:\Gowin_haogang\project\Gowin_USB3_2_Ref\Gowin_USB3_2_UVC_BULK_Ref\release\Gowin_USB3_2_GEN2_UVC_BULK_Ref_DK_USB_GW5AT_LV60UG225_V1.0\prj\src\pll_mDRP_intf.v E:\Gowin_haogang\project\Gowin_USB3_2_Ref\Gowin_USB3_2_UVC_BULK_Ref\release\Gowin_USB3_2_GEN2_UVC_BULK_Ref_DK_USB_GW5AT_LV60UG225_V1.0\prj\src\serdes\serdes.v E:\Gowin_haogang\project\Gowin_USB3_2_Ref\Gowin_USB3_2_UVC_BULK_Ref\release\Gowin_USB3_2_GEN2_UVC_BULK_Ref_DK_USB_GW5AT_LV60UG225_V1.0\prj\src\serdes\upar_arbiter\upar_arbiter.v E:\Gowin_haogang\project\Gowin_USB3_2_Ref\Gowin_USB3_2_UVC_BULK_Ref\release\Gowin_USB3_2_GEN2_UVC_BULK_Ref_DK_USB_GW5AT_LV60UG225_V1.0\prj\src\serdes\usb3_1_phy\usb3_1_phy.v E:\Gowin_haogang\project\Gowin_USB3_2_Ref\Gowin_USB3_2_UVC_BULK_Ref\release\Gowin_USB3_2_GEN2_UVC_BULK_Ref_DK_USB_GW5AT_LV60UG225_V1.0\prj\src\testpattern_yuv\rgb888_to_yuv422.v E:\Gowin_haogang\project\Gowin_USB3_2_Ref\Gowin_USB3_2_UVC_BULK_Ref\release\Gowin_USB3_2_GEN2_UVC_BULK_Ref_DK_USB_GW5AT_LV60UG225_V1.0\prj\src\testpattern_yuv\testpattern.v E:\Gowin_haogang\project\Gowin_USB3_2_Ref\Gowin_USB3_2_UVC_BULK_Ref\release\Gowin_USB3_2_GEN2_UVC_BULK_Ref_DK_USB_GW5AT_LV60UG225_V1.0\prj\src\testpattern_yuv\testpattern_yuv.v E:\Gowin_haogang\project\Gowin_USB3_2_Ref\Gowin_USB3_2_UVC_BULK_Ref\release\Gowin_USB3_2_GEN2_UVC_BULK_Ref_DK_USB_GW5AT_LV60UG225_V1.0\prj\src\top.sv E:\Gowin_haogang\project\Gowin_USB3_2_Ref\Gowin_USB3_2_UVC_BULK_Ref\release\Gowin_USB3_2_GEN2_UVC_BULK_Ref_DK_USB_GW5AT_LV60UG225_V1.0\prj\src\usb3_2_user_layer\ControlTransfer.v E:\Gowin_haogang\project\Gowin_USB3_2_Ref\Gowin_USB3_2_UVC_BULK_Ref\release\Gowin_USB3_2_GEN2_UVC_BULK_Ref_DK_USB_GW5AT_LV60UG225_V1.0\prj\src\usb3_2_user_layer\UserLayer_top.sv E:\Gowin_haogang\project\Gowin_USB3_2_Ref\Gowin_USB3_2_UVC_BULK_Ref\release\Gowin_USB3_2_GEN2_UVC_BULK_Ref_DK_USB_GW5AT_LV60UG225_V1.0\prj\src\usb3_2_user_layer\descriptors\usb_descrip_define.v E:\Gowin_haogang\project\Gowin_USB3_2_Ref\Gowin_USB3_2_UVC_BULK_Ref\release\Gowin_USB3_2_GEN2_UVC_BULK_Ref_DK_USB_GW5AT_LV60UG225_V1.0\prj\src\usb3_2_user_layer\ep2_IN.v E:\Gowin_haogang\project\Gowin_USB3_2_Ref\Gowin_USB3_2_UVC_BULK_Ref\release\Gowin_USB3_2_GEN2_UVC_BULK_Ref_DK_USB_GW5AT_LV60UG225_V1.0\prj\src\video_frame_buffer\video_frame_buffer.v E:\Gowin_haogang\project\Gowin_USB3_2_Ref\Gowin_USB3_2_UVC_BULK_Ref\release\Gowin_USB3_2_GEN2_UVC_BULK_Ref_DK_USB_GW5AT_LV60UG225_V1.0\prj\src\usb3_2_device_controller\transfer_in_mem.v E:\Gowin_haogang\project\Gowin_USB3_2_Ref\Gowin_USB3_2_UVC_BULK_Ref\release\Gowin_USB3_2_GEN2_UVC_BULK_Ref_DK_USB_GW5AT_LV60UG225_V1.0\prj\src\usb3_2_device_controller\transfer_in_mem_ping_pong.v E:\Gowin_haogang\project\Gowin_USB3_2_Ref\Gowin_USB3_2_UVC_BULK_Ref\release\Gowin_USB3_2_GEN2_UVC_BULK_Ref_DK_USB_GW5AT_LV60UG225_V1.0\prj\src\usb3_2_device_controller\transfer_out_mem.v E:\Gowin_haogang\project\Gowin_USB3_2_Ref\Gowin_USB3_2_UVC_BULK_Ref\release\Gowin_USB3_2_GEN2_UVC_BULK_Ref_DK_USB_GW5AT_LV60UG225_V1.0\prj\src\usb3_2_device_controller\transfer_out_mem_ping_pong.v E:\Gowin_haogang\project\Gowin_USB3_2_Ref\Gowin_USB3_2_UVC_BULK_Ref\release\Gowin_USB3_2_GEN2_UVC_BULK_Ref_DK_USB_GW5AT_LV60UG225_V1.0\prj\src\usb3_2_device_controller\usb3_2_device_controller.sv E:\Gowin_haogang\project\Gowin_USB3_2_Ref\Gowin_USB3_2_UVC_BULK_Ref\release\Gowin_USB3_2_GEN2_UVC_BULK_Ref_DK_USB_GW5AT_LV60UG225_V1.0\prj\src\usb3_2_device_controller\USB3_2_Device_Controller_Top.sv E:\Gowin_haogang\project\Gowin_USB3_2_Ref\Gowin_USB3_2_UVC_BULK_Ref\release\Gowin_USB3_2_GEN2_UVC_BULK_Ref_DK_USB_GW5AT_LV60UG225_V1.0\prj\src\usb3_2_device_controller\usb3_const.vh E:\Gowin_haogang\project\Gowin_USB3_2_Ref\Gowin_USB3_2_UVC_BULK_Ref\release\Gowin_USB3_2_GEN2_UVC_BULK_Ref_DK_USB_GW5AT_LV60UG225_V1.0\prj\src\usb3_2_device_controller\usb3_ep.v E:\Gowin_haogang\project\Gowin_USB3_2_Ref\Gowin_USB3_2_UVC_BULK_Ref\release\Gowin_USB3_2_GEN2_UVC_BULK_Ref_DK_USB_GW5AT_LV60UG225_V1.0\prj\src\usb3_2_device_controller\usb3_ep0.v E:\Gowin_haogang\project\Gowin_USB3_2_Ref\Gowin_USB3_2_UVC_BULK_Ref\release\Gowin_USB3_2_GEN2_UVC_BULK_Ref_DK_USB_GW5AT_LV60UG225_V1.0\prj\src\usb3_2_device_controller\usb3_ep0in_ram.v E:\Gowin_haogang\project\Gowin_USB3_2_Ref\Gowin_USB3_2_UVC_BULK_Ref\release\Gowin_USB3_2_GEN2_UVC_BULK_Ref_DK_USB_GW5AT_LV60UG225_V1.0\prj\src\usb3_2_device_controller\usb3_macro_define.v E:\Gowin_haogang\project\Gowin_USB3_2_Ref\Gowin_USB3_2_UVC_BULK_Ref\release\Gowin_USB3_2_GEN2_UVC_BULK_Ref_DK_USB_GW5AT_LV60UG225_V1.0\prj\src\usb3_2_device_controller\usb3_protocol.sv E:\Gowin_haogang\project\Gowin_USB3_2_Ref\Gowin_USB3_2_UVC_BULK_Ref\release\Gowin_USB3_2_GEN2_UVC_BULK_Ref_DK_USB_GW5AT_LV60UG225_V1.0\prj\src\usb3_2_device_controller\usb3_link.vg E:\Gowin_haogang\project\Gowin_USB3_2_Ref\Gowin_USB3_2_UVC_BULK_Ref\release\Gowin_USB3_2_GEN2_UVC_BULK_Ref_DK_USB_GW5AT_LV60UG225_V1.0\prj\src\usb3_2_device_controller\usb3_ltssm_device.vg E:\Gowin_haogang\project\Gowin_USB3_2_Ref\Gowin_USB3_2_UVC_BULK_Ref\release\Gowin_USB3_2_GEN2_UVC_BULK_Ref_DK_USB_GW5AT_LV60UG225_V1.0\prj\src\usb3_2_device_controller\usb3_pipe.vg
GowinSynthesis Constraints File	---
Tool Version	V1.9.12.03 (64-bit)
Part Number	GW5AT-LV60UG225C2/I1
Device	GW5AT-60
Device Version	B
Created Time	Fri Jul 24 16:18:17 2026
Legal Announcement	Copyright (C)2014-2026 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module	top
Synthesis Process	Running parser: CPU time = 0h 0m 12s, Elapsed time = 0h 0m 9s, Peak memory usage = 536.355MB Running netlist conversion: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 9s, Elapsed time = 0h 0m 8s, Peak memory usage = 536.355MB Optimizing Phase 1: CPU time = 0h 0m 3s, Elapsed time = 0h 0m 3s, Peak memory usage = 536.355MB Optimizing Phase 2: CPU time = 0h 0m 14s, Elapsed time = 0h 0m 14s, Peak memory usage = 536.355MB Running inference: Inferring Phase 0: CPU time = 0h 0m 10s, Elapsed time = 0h 0m 10s, Peak memory usage = 536.355MB Inferring Phase 1: CPU time = 0h 0m 0.578s, Elapsed time = 0h 0m 0.567s, Peak memory usage = 536.355MB Inferring Phase 2: CPU time = 0h 0m 0.578s, Elapsed time = 0h 0m 0.584s, Peak memory usage = 536.355MB Inferring Phase 3: CPU time = 0h 0m 0.328s, Elapsed time = 0h 0m 0.325s, Peak memory usage = 536.355MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 10s, Elapsed time = 0h 0m 10s, Peak memory usage = 536.355MB Tech-Mapping Phase 1: CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s, Peak memory usage = 536.355MB Tech-Mapping Phase 2: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 536.355MB Tech-Mapping Phase 3: CPU time = 0h 0m 18s, Elapsed time = 0h 0m 18s, Peak memory usage = 536.355MB Tech-Mapping Phase 4: CPU time = 0h 0m 3s, Elapsed time = 0h 0m 4s, Peak memory usage = 536.355MB Generate output files: CPU time = 0h 0m 5s, Elapsed time = 0h 0m 4s, Peak memory usage = 656.891MB
Total Time and Memory Usage	CPU time = 0h 1m 28s, Elapsed time = 0h 1m 24s, Peak memory usage = 656.891MB

Resource

Resource Usage Summary

Resource	Usage
I/O Port	69
I/O Buf	1256
IBUF	816
OBUF	415
TBUF	2
IOBUF	18
TLVDS_IBUF	1
ELVDS_OBUF	2
ELVDS_IOBUF	2
Register	18770
DFFSE	343
DFFRE	3636
DFFPE	623
DFFCE	14168
LUT	27063
LUT2	3247
LUT3	8107
LUT4	15709
ALU	1050
ALU	1050
SSRAM	81
RAM16SDP1	3
RAM16SDP2	1
RAM16SDP4	77
INV	663
INV	663
IOLOGIC	104
IDES8	18
OSER8	24
OSER8_MEM	20
IODELAY	42
DSP
MULTALU27X18	1
MULT12X12	7
MULTADDALU12X12	1
BSRAM	61
SDPB	48
SDPX9B	11
pROM	2
CLOCK	6
CLKDIV	1
DQS	2
DDRDLL	1
PLLA	2

Resource Utilization Summary

Resource	Usage	Utilization
Logic	29262(27726 LUT, 1050 ALU, 81 RAM16) / 59904	49%
Register	18770 / 60228	32%
--Register as Latch	0 / 60228	0%
--Register as FF	18770 / 60228	32%
BSRAM	61 / 118	52%

Timing

Clock Summary:

NO.	Clock Name	Type	Period	Frequency(MHz)	Fall	Source	Master	Object
1	sys_clk_p	Base	5.000	200.000	2.500			Inst_sys_clk_in/I
2	clk_24m	Base	41.667	24.000	20.833			clk_24m_ibuf/I
3	pclk	Base	10.000	100.000	5.000			USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/local_clk_ibuf/I
4	pclk_gowin	Base	10.000	100.000	5.000			USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/local_clk_ibuf/I
5	pclk_gowin_gowin	Base	10.000	100.000	5.000			USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/local_clk_ibuf/I
6	line_fifo_inst/fifo_inst/n4_6_3	Base	10.000	100.000	5.000			line_fifo_inst/fifo_inst/n4_6_s0/F
7	cnt4_clr	Base	10.000	100.000	5.000			cnt4_clr_s0/Q
8	Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0.default_gen_clk	Generated	20.000	50.000	10.000	Inst_sys_clk_in/I	sys_clk_p	Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
9	Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk	Generated	6.723	148.750	3.361	Inst_sys_clk_in/I	sys_clk_p	Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1
10	ddr_pll_inst/u_pll/PLLA_inst/CLKOUT2.default_gen_clk	Generated	1.821	549.000	0.911	clk_24m_ibuf/I	clk_24m	ddr_pll_inst/u_pll/PLLA_inst/CLKOUT2
11	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk	Generated	7.286	137.250	3.643	ddr_pll_inst/u_pll/PLLA_inst/CLKOUT2	ddr_pll_inst/u_pll/PLLA_inst/CLKOUT2.default_gen_clk	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT

Max Frequency Summary:

NO.	Clock Name	Constraint	Actual Fmax	Logic Level	Entity
1	sys_clk_p	200.000(MHz)	483.723(MHz)	3	TOP
2	clk_24m	24.000(MHz)	194.898(MHz)	7	TOP
3	pclk	100.000(MHz)	186.930(MHz)	9	TOP
4	pclk_gowin	100.000(MHz)	191.077(MHz)	8	TOP
5	pclk_gowin_gowin	100.000(MHz)	158.596(MHz)	7	TOP
6	line_fifo_inst/fifo_inst/n4_6_3	100.000(MHz)	1691.189(MHz)	1	TOP
7	cnt4_clr	100.000(MHz)	806.322(MHz)	2	TOP
8	Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0.default_gen_clk	50.000(MHz)	182.749(MHz)	7	TOP
9	Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk	148.750(MHz)	172.801(MHz)	10	TOP
10	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk	137.250(MHz)	1691.190(MHz)	1	TOP

Detail Timing Paths Information

Path 1

Path Summary:

Slack	-2.713
Data Arrival Time	1045.056
Data Required Time	1042.343
From	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/ddr_sync/ddr_init_st_s0
To	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_state.READ_CALIBRATION_s0
Launch Clk	clk_24m[R]
Latch Clk	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
1041.667	1041.667				active clock edge time
1041.667	0.000				clk_24m
1041.667	0.000	tCL	RR	1	clk_24m_ibuf/I
1041.667	0.000	tINS	RR	470	clk_24m_ibuf/O
1041.937	0.270	tNET	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/ddr_sync/ddr_init_st_s0/CLK
1042.212	0.275	tC2Q	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/ddr_sync/ddr_init_st_s0/Q
1042.482	0.270	tNET	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state.RESET_WAIT_s19/I1
1042.854	0.372	tINS	RR	4	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state.RESET_WAIT_s19/F
1043.124	0.270	tNET	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state.LOAD_MR_s26/I1
1043.496	0.372	tINS	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state.LOAD_MR_s26/F
1043.766	0.270	tNET	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state.WRLVL_LOAD_MR1_s20/I1
1044.137	0.372	tINS	RR	17	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state.WRLVL_LOAD_MR1_s20/F
1044.407	0.270	tNET	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state.READ_CALIBRATION_s19/I0
1044.786	0.379	tINS	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state.READ_CALIBRATION_s19/F
1045.056	0.270	tNET	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_state.READ_CALIBRATION_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
1041.894	1041.894				active clock edge time
1041.894	0.000				DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
1042.155	0.261	tCL	RR	3995	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1042.425	0.270	tNET	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_state.READ_CALIBRATION_s0/CLK
1042.390	-0.035	tUnc			DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_state.READ_CALIBRATION_s0
1042.344	-0.046	tSu		1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_state.READ_CALIBRATION_s0

Path Statistics:

Clock Skew:	0.261
Setup Relationship:	0.228
Logic Level:	5
Arrival Clock Path Delay:	cell: 0.000, 0.000%; route: 0.270, 100.000%
Arrival Data Path Delay:	cell: 1.494, 47.893%; route: 1.350, 43.278%; tC2Q: 0.275, 8.829%
Required Clock Path Delay:	cell: 0.000, 0.000%; route: 0.270, 100.000%

Path 2

Path Summary:

Slack	-2.713
Data Arrival Time	1045.056
Data Required Time	1042.343
From	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/ddr_sync/ddr_init_st_s0
To	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_state.WRLVL_MODE_CLOSE1_WAIT_s0
Launch Clk	clk_24m[R]
Latch Clk	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
1041.667	1041.667				active clock edge time
1041.667	0.000				clk_24m
1041.667	0.000	tCL	RR	1	clk_24m_ibuf/I
1041.667	0.000	tINS	RR	470	clk_24m_ibuf/O
1041.937	0.270	tNET	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/ddr_sync/ddr_init_st_s0/CLK
1042.212	0.275	tC2Q	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/ddr_sync/ddr_init_st_s0/Q
1042.482	0.270	tNET	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state.RESET_WAIT_s19/I1
1042.854	0.372	tINS	RR	4	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state.RESET_WAIT_s19/F
1043.124	0.270	tNET	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state.LOAD_MR_s26/I1
1043.496	0.372	tINS	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state.LOAD_MR_s26/F
1043.766	0.270	tNET	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state.WRLVL_LOAD_MR1_s20/I1
1044.137	0.372	tINS	RR	17	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state.WRLVL_LOAD_MR1_s20/F
1044.407	0.270	tNET	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state.WRLVL_MODE_CLOSE1_WAIT_s19/I0
1044.786	0.379	tINS	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state.WRLVL_MODE_CLOSE1_WAIT_s19/F
1045.056	0.270	tNET	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_state.WRLVL_MODE_CLOSE1_WAIT_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
1041.894	1041.894				active clock edge time
1041.894	0.000				DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
1042.155	0.261	tCL	RR	3995	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1042.425	0.270	tNET	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_state.WRLVL_MODE_CLOSE1_WAIT_s0/CLK
1042.390	-0.035	tUnc			DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_state.WRLVL_MODE_CLOSE1_WAIT_s0
1042.344	-0.046	tSu		1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_state.WRLVL_MODE_CLOSE1_WAIT_s0

Path Statistics:

Clock Skew:	0.261
Setup Relationship:	0.228
Logic Level:	5
Arrival Clock Path Delay:	cell: 0.000, 0.000%; route: 0.270, 100.000%
Arrival Data Path Delay:	cell: 1.494, 47.893%; route: 1.350, 43.278%; tC2Q: 0.275, 8.829%
Required Clock Path Delay:	cell: 0.000, 0.000%; route: 0.270, 100.000%

Path 3

Path Summary:

Slack	-2.713
Data Arrival Time	1045.056
Data Required Time	1042.343
From	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/ddr_sync/ddr_init_st_s0
To	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_state.WRLVL_LOAD_MR1_WAIT_s0
Launch Clk	clk_24m[R]
Latch Clk	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
1041.667	1041.667				active clock edge time
1041.667	0.000				clk_24m
1041.667	0.000	tCL	RR	1	clk_24m_ibuf/I
1041.667	0.000	tINS	RR	470	clk_24m_ibuf/O
1041.937	0.270	tNET	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/ddr_sync/ddr_init_st_s0/CLK
1042.212	0.275	tC2Q	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/ddr_sync/ddr_init_st_s0/Q
1042.482	0.270	tNET	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state.RESET_WAIT_s19/I1
1042.854	0.372	tINS	RR	4	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state.RESET_WAIT_s19/F
1043.124	0.270	tNET	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state.LOAD_MR_s26/I1
1043.496	0.372	tINS	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state.LOAD_MR_s26/F
1043.766	0.270	tNET	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state.WRLVL_LOAD_MR1_s20/I1
1044.137	0.372	tINS	RR	17	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state.WRLVL_LOAD_MR1_s20/F
1044.407	0.270	tNET	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state.WRLVL_LOAD_MR1_WAIT_s19/I0
1044.786	0.379	tINS	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state.WRLVL_LOAD_MR1_WAIT_s19/F
1045.056	0.270	tNET	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_state.WRLVL_LOAD_MR1_WAIT_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
1041.894	1041.894				active clock edge time
1041.894	0.000				DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
1042.155	0.261	tCL	RR	3995	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1042.425	0.270	tNET	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_state.WRLVL_LOAD_MR1_WAIT_s0/CLK
1042.390	-0.035	tUnc			DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_state.WRLVL_LOAD_MR1_WAIT_s0
1042.344	-0.046	tSu		1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_state.WRLVL_LOAD_MR1_WAIT_s0

Path Statistics:

Clock Skew:	0.261
Setup Relationship:	0.228
Logic Level:	5
Arrival Clock Path Delay:	cell: 0.000, 0.000%; route: 0.270, 100.000%
Arrival Data Path Delay:	cell: 1.494, 47.893%; route: 1.350, 43.278%; tC2Q: 0.275, 8.829%
Required Clock Path Delay:	cell: 0.000, 0.000%; route: 0.270, 100.000%

Path 4

Path Summary:

Slack	-2.713
Data Arrival Time	1045.056
Data Required Time	1042.343
From	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/ddr_sync/ddr_init_st_s0
To	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_state.WRLVL_LOAD_MR2_WAIT_s0
Launch Clk	clk_24m[R]
Latch Clk	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
1041.667	1041.667				active clock edge time
1041.667	0.000				clk_24m
1041.667	0.000	tCL	RR	1	clk_24m_ibuf/I
1041.667	0.000	tINS	RR	470	clk_24m_ibuf/O
1041.937	0.270	tNET	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/ddr_sync/ddr_init_st_s0/CLK
1042.212	0.275	tC2Q	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/ddr_sync/ddr_init_st_s0/Q
1042.482	0.270	tNET	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state.RESET_WAIT_s19/I1
1042.854	0.372	tINS	RR	4	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state.RESET_WAIT_s19/F
1043.124	0.270	tNET	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state.LOAD_MR_s26/I1
1043.496	0.372	tINS	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state.LOAD_MR_s26/F
1043.766	0.270	tNET	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state.WRLVL_LOAD_MR1_s20/I1
1044.137	0.372	tINS	RR	17	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state.WRLVL_LOAD_MR1_s20/F
1044.407	0.270	tNET	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state.WRLVL_LOAD_MR2_WAIT_s19/I0
1044.786	0.379	tINS	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state.WRLVL_LOAD_MR2_WAIT_s19/F
1045.056	0.270	tNET	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_state.WRLVL_LOAD_MR2_WAIT_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
1041.894	1041.894				active clock edge time
1041.894	0.000				DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
1042.155	0.261	tCL	RR	3995	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1042.425	0.270	tNET	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_state.WRLVL_LOAD_MR2_WAIT_s0/CLK
1042.390	-0.035	tUnc			DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_state.WRLVL_LOAD_MR2_WAIT_s0
1042.344	-0.046	tSu		1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_state.WRLVL_LOAD_MR2_WAIT_s0

Path Statistics:

Clock Skew:	0.261
Setup Relationship:	0.228
Logic Level:	5
Arrival Clock Path Delay:	cell: 0.000, 0.000%; route: 0.270, 100.000%
Arrival Data Path Delay:	cell: 1.494, 47.893%; route: 1.350, 43.278%; tC2Q: 0.275, 8.829%
Required Clock Path Delay:	cell: 0.000, 0.000%; route: 0.270, 100.000%

Path 5

Path Summary:

Slack	-2.713
Data Arrival Time	1045.056
Data Required Time	1042.343
From	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/ddr_sync/ddr_init_st_s0
To	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_state.ZQCL_WAIT_s0
Launch Clk	clk_24m[R]
Latch Clk	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
1041.667	1041.667				active clock edge time
1041.667	0.000				clk_24m
1041.667	0.000	tCL	RR	1	clk_24m_ibuf/I
1041.667	0.000	tINS	RR	470	clk_24m_ibuf/O
1041.937	0.270	tNET	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/ddr_sync/ddr_init_st_s0/CLK
1042.212	0.275	tC2Q	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/ddr_sync/ddr_init_st_s0/Q
1042.482	0.270	tNET	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state.RESET_WAIT_s19/I1
1042.854	0.372	tINS	RR	4	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state.RESET_WAIT_s19/F
1043.124	0.270	tNET	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state.LOAD_MR_s26/I1
1043.496	0.372	tINS	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state.LOAD_MR_s26/F
1043.766	0.270	tNET	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state.WRLVL_LOAD_MR1_s20/I1
1044.137	0.372	tINS	RR	17	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state.WRLVL_LOAD_MR1_s20/F
1044.407	0.270	tNET	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state.ZQCL_WAIT_s19/I0
1044.786	0.379	tINS	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state.ZQCL_WAIT_s19/F
1045.056	0.270	tNET	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_state.ZQCL_WAIT_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
1041.894	1041.894				active clock edge time
1041.894	0.000				DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
1042.155	0.261	tCL	RR	3995	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1042.425	0.270	tNET	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_state.ZQCL_WAIT_s0/CLK
1042.390	-0.035	tUnc			DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_state.ZQCL_WAIT_s0
1042.344	-0.046	tSu		1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_state.ZQCL_WAIT_s0

Path Statistics:

Clock Skew:	0.261
Setup Relationship:	0.228
Logic Level:	5
Arrival Clock Path Delay:	cell: 0.000, 0.000%; route: 0.270, 100.000%
Arrival Data Path Delay:	cell: 1.494, 47.893%; route: 1.350, 43.278%; tC2Q: 0.275, 8.829%
Required Clock Path Delay:	cell: 0.000, 0.000%; route: 0.270, 100.000%

Path 6

Path Summary:

Slack	-2.713
Data Arrival Time	1045.056
Data Required Time	1042.343
From	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/ddr_sync/ddr_init_st_s0
To	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_state.LOAD_MR_WAIT_s0
Launch Clk	clk_24m[R]
Latch Clk	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
1041.667	1041.667				active clock edge time
1041.667	0.000				clk_24m
1041.667	0.000	tCL	RR	1	clk_24m_ibuf/I
1041.667	0.000	tINS	RR	470	clk_24m_ibuf/O
1041.937	0.270	tNET	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/ddr_sync/ddr_init_st_s0/CLK
1042.212	0.275	tC2Q	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/ddr_sync/ddr_init_st_s0/Q
1042.482	0.270	tNET	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state.RESET_WAIT_s19/I1
1042.854	0.372	tINS	RR	4	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state.RESET_WAIT_s19/F
1043.124	0.270	tNET	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state.LOAD_MR_s26/I1
1043.496	0.372	tINS	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state.LOAD_MR_s26/F
1043.766	0.270	tNET	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state.WRLVL_LOAD_MR1_s20/I1
1044.137	0.372	tINS	RR	17	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state.WRLVL_LOAD_MR1_s20/F
1044.407	0.270	tNET	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state.LOAD_MR_WAIT_s19/I0
1044.786	0.379	tINS	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state.LOAD_MR_WAIT_s19/F
1045.056	0.270	tNET	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_state.LOAD_MR_WAIT_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
1041.894	1041.894				active clock edge time
1041.894	0.000				DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
1042.155	0.261	tCL	RR	3995	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1042.425	0.270	tNET	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_state.LOAD_MR_WAIT_s0/CLK
1042.390	-0.035	tUnc			DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_state.LOAD_MR_WAIT_s0
1042.344	-0.046	tSu		1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_state.LOAD_MR_WAIT_s0

Path Statistics:

Clock Skew:	0.261
Setup Relationship:	0.228
Logic Level:	5
Arrival Clock Path Delay:	cell: 0.000, 0.000%; route: 0.270, 100.000%
Arrival Data Path Delay:	cell: 1.494, 47.893%; route: 1.350, 43.278%; tC2Q: 0.275, 8.829%
Required Clock Path Delay:	cell: 0.000, 0.000%; route: 0.270, 100.000%

Path 7

Path Summary:

Slack	-2.713
Data Arrival Time	1045.056
Data Required Time	1042.343
From	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/ddr_sync/ddr_init_st_s0
To	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_state.XPR_WAIT_s0
Launch Clk	clk_24m[R]
Latch Clk	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
1041.667	1041.667				active clock edge time
1041.667	0.000				clk_24m
1041.667	0.000	tCL	RR	1	clk_24m_ibuf/I
1041.667	0.000	tINS	RR	470	clk_24m_ibuf/O
1041.937	0.270	tNET	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/ddr_sync/ddr_init_st_s0/CLK
1042.212	0.275	tC2Q	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/ddr_sync/ddr_init_st_s0/Q
1042.482	0.270	tNET	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state.RESET_WAIT_s19/I1
1042.854	0.372	tINS	RR	4	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state.RESET_WAIT_s19/F
1043.124	0.270	tNET	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state.LOAD_MR_s26/I1
1043.496	0.372	tINS	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state.LOAD_MR_s26/F
1043.766	0.270	tNET	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state.WRLVL_LOAD_MR1_s20/I1
1044.137	0.372	tINS	RR	17	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state.WRLVL_LOAD_MR1_s20/F
1044.407	0.270	tNET	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state.XPR_WAIT_s19/I0
1044.786	0.379	tINS	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state.XPR_WAIT_s19/F
1045.056	0.270	tNET	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_state.XPR_WAIT_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
1041.894	1041.894				active clock edge time
1041.894	0.000				DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
1042.155	0.261	tCL	RR	3995	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1042.425	0.270	tNET	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_state.XPR_WAIT_s0/CLK
1042.390	-0.035	tUnc			DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_state.XPR_WAIT_s0
1042.344	-0.046	tSu		1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_state.XPR_WAIT_s0

Path Statistics:

Clock Skew:	0.261
Setup Relationship:	0.228
Logic Level:	5
Arrival Clock Path Delay:	cell: 0.000, 0.000%; route: 0.270, 100.000%
Arrival Data Path Delay:	cell: 1.494, 47.893%; route: 1.350, 43.278%; tC2Q: 0.275, 8.829%
Required Clock Path Delay:	cell: 0.000, 0.000%; route: 0.270, 100.000%

Path 8

Path Summary:

Slack	-2.713
Data Arrival Time	1045.056
Data Required Time	1042.343
From	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/ddr_sync/ddr_init_st_s0
To	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_state.CKE_EN_s0
Launch Clk	clk_24m[R]
Latch Clk	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
1041.667	1041.667				active clock edge time
1041.667	0.000				clk_24m
1041.667	0.000	tCL	RR	1	clk_24m_ibuf/I
1041.667	0.000	tINS	RR	470	clk_24m_ibuf/O
1041.937	0.270	tNET	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/ddr_sync/ddr_init_st_s0/CLK
1042.212	0.275	tC2Q	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/ddr_sync/ddr_init_st_s0/Q
1042.482	0.270	tNET	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state.RESET_WAIT_s19/I1
1042.854	0.372	tINS	RR	4	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state.RESET_WAIT_s19/F
1043.124	0.270	tNET	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state.LOAD_MR_s26/I1
1043.496	0.372	tINS	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state.LOAD_MR_s26/F
1043.766	0.270	tNET	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state.WRLVL_LOAD_MR1_s20/I1
1044.137	0.372	tINS	RR	17	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state.WRLVL_LOAD_MR1_s20/F
1044.407	0.270	tNET	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state.CKE_EN_s18/I0
1044.786	0.379	tINS	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state.CKE_EN_s18/F
1045.056	0.270	tNET	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_state.CKE_EN_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
1041.894	1041.894				active clock edge time
1041.894	0.000				DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
1042.155	0.261	tCL	RR	3995	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1042.425	0.270	tNET	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_state.CKE_EN_s0/CLK
1042.390	-0.035	tUnc			DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_state.CKE_EN_s0
1042.344	-0.046	tSu		1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_state.CKE_EN_s0

Path Statistics:

Clock Skew:	0.261
Setup Relationship:	0.228
Logic Level:	5
Arrival Clock Path Delay:	cell: 0.000, 0.000%; route: 0.270, 100.000%
Arrival Data Path Delay:	cell: 1.494, 47.893%; route: 1.350, 43.278%; tC2Q: 0.275, 8.829%
Required Clock Path Delay:	cell: 0.000, 0.000%; route: 0.270, 100.000%

Path 9

Path Summary:

Slack	-2.713
Data Arrival Time	1045.056
Data Required Time	1042.343
From	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/ddr_sync/ddr_init_st_s0
To	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_state.IDLE_s0
Launch Clk	clk_24m[R]
Latch Clk	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
1041.667	1041.667				active clock edge time
1041.667	0.000				clk_24m
1041.667	0.000	tCL	RR	1	clk_24m_ibuf/I
1041.667	0.000	tINS	RR	470	clk_24m_ibuf/O
1041.937	0.270	tNET	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/ddr_sync/ddr_init_st_s0/CLK
1042.212	0.275	tC2Q	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/ddr_sync/ddr_init_st_s0/Q
1042.482	0.270	tNET	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state.RESET_WAIT_s19/I1
1042.854	0.372	tINS	RR	4	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state.RESET_WAIT_s19/F
1043.124	0.270	tNET	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state.LOAD_MR_s26/I1
1043.496	0.372	tINS	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state.LOAD_MR_s26/F
1043.766	0.270	tNET	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state.WRLVL_LOAD_MR1_s20/I1
1044.137	0.372	tINS	RR	17	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state.WRLVL_LOAD_MR1_s20/F
1044.407	0.270	tNET	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state.IDLE_s18/I0
1044.786	0.379	tINS	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state.IDLE_s18/F
1045.056	0.270	tNET	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_state.IDLE_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
1041.894	1041.894				active clock edge time
1041.894	0.000				DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
1042.155	0.261	tCL	RR	3995	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1042.425	0.270	tNET	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_state.IDLE_s0/CLK
1042.390	-0.035	tUnc			DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_state.IDLE_s0
1042.344	-0.046	tSu		1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_state.IDLE_s0

Path Statistics:

Clock Skew:	0.261
Setup Relationship:	0.228
Logic Level:	5
Arrival Clock Path Delay:	cell: 0.000, 0.000%; route: 0.270, 100.000%
Arrival Data Path Delay:	cell: 1.494, 47.893%; route: 1.350, 43.278%; tC2Q: 0.275, 8.829%
Required Clock Path Delay:	cell: 0.000, 0.000%; route: 0.270, 100.000%

Path 10

Path Summary:

Slack	-2.713
Data Arrival Time	1045.056
Data Required Time	1042.343
From	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/ddr_sync/ddr_init_st_s0
To	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_state.WRLVL_MODE_CLOSE2_s0
Launch Clk	clk_24m[R]
Latch Clk	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
1041.667	1041.667				active clock edge time
1041.667	0.000				clk_24m
1041.667	0.000	tCL	RR	1	clk_24m_ibuf/I
1041.667	0.000	tINS	RR	470	clk_24m_ibuf/O
1041.937	0.270	tNET	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/ddr_sync/ddr_init_st_s0/CLK
1042.212	0.275	tC2Q	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/ddr_sync/ddr_init_st_s0/Q
1042.482	0.270	tNET	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state.RESET_WAIT_s19/I1
1042.854	0.372	tINS	RR	4	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state.RESET_WAIT_s19/F
1043.124	0.270	tNET	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state.LOAD_MR_s26/I1
1043.496	0.372	tINS	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state.LOAD_MR_s26/F
1043.766	0.270	tNET	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state.WRLVL_LOAD_MR1_s20/I1
1044.137	0.372	tINS	RR	17	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state.WRLVL_LOAD_MR1_s20/F
1044.407	0.270	tNET	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state.WRLVL_MODE_CLOSE2_s19/I0
1044.786	0.379	tINS	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state.WRLVL_MODE_CLOSE2_s19/F
1045.056	0.270	tNET	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_state.WRLVL_MODE_CLOSE2_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
1041.894	1041.894				active clock edge time
1041.894	0.000				DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
1042.155	0.261	tCL	RR	3995	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1042.425	0.270	tNET	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_state.WRLVL_MODE_CLOSE2_s0/CLK
1042.390	-0.035	tUnc			DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_state.WRLVL_MODE_CLOSE2_s0
1042.344	-0.046	tSu		1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_state.WRLVL_MODE_CLOSE2_s0

Path Statistics:

Clock Skew:	0.261
Setup Relationship:	0.228
Logic Level:	5
Arrival Clock Path Delay:	cell: 0.000, 0.000%; route: 0.270, 100.000%
Arrival Data Path Delay:	cell: 1.494, 47.893%; route: 1.350, 43.278%; tC2Q: 0.275, 8.829%
Required Clock Path Delay:	cell: 0.000, 0.000%; route: 0.270, 100.000%

Path 11

Path Summary:

Slack	-2.713
Data Arrival Time	1045.056
Data Required Time	1042.343
From	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/ddr_sync/ddr_init_st_s0
To	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_state.WRLVL_MODE_CLOSE1_s0
Launch Clk	clk_24m[R]
Latch Clk	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
1041.667	1041.667				active clock edge time
1041.667	0.000				clk_24m
1041.667	0.000	tCL	RR	1	clk_24m_ibuf/I
1041.667	0.000	tINS	RR	470	clk_24m_ibuf/O
1041.937	0.270	tNET	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/ddr_sync/ddr_init_st_s0/CLK
1042.212	0.275	tC2Q	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/ddr_sync/ddr_init_st_s0/Q
1042.482	0.270	tNET	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state.RESET_WAIT_s19/I1
1042.854	0.372	tINS	RR	4	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state.RESET_WAIT_s19/F
1043.124	0.270	tNET	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state.LOAD_MR_s26/I1
1043.496	0.372	tINS	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state.LOAD_MR_s26/F
1043.766	0.270	tNET	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state.WRLVL_LOAD_MR1_s20/I1
1044.137	0.372	tINS	RR	17	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state.WRLVL_LOAD_MR1_s20/F
1044.407	0.270	tNET	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state.WRLVL_MODE_CLOSE1_s18/I0
1044.786	0.379	tINS	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state.WRLVL_MODE_CLOSE1_s18/F
1045.056	0.270	tNET	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_state.WRLVL_MODE_CLOSE1_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
1041.894	1041.894				active clock edge time
1041.894	0.000				DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
1042.155	0.261	tCL	RR	3995	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1042.425	0.270	tNET	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_state.WRLVL_MODE_CLOSE1_s0/CLK
1042.390	-0.035	tUnc			DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_state.WRLVL_MODE_CLOSE1_s0
1042.344	-0.046	tSu		1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_state.WRLVL_MODE_CLOSE1_s0

Path Statistics:

Clock Skew:	0.261
Setup Relationship:	0.228
Logic Level:	5
Arrival Clock Path Delay:	cell: 0.000, 0.000%; route: 0.270, 100.000%
Arrival Data Path Delay:	cell: 1.494, 47.893%; route: 1.350, 43.278%; tC2Q: 0.275, 8.829%
Required Clock Path Delay:	cell: 0.000, 0.000%; route: 0.270, 100.000%

Path 12

Path Summary:

Slack	-2.713
Data Arrival Time	1045.056
Data Required Time	1042.343
From	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/ddr_sync/ddr_init_st_s0
To	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_state.WRLVL_LOAD_MR1_s0
Launch Clk	clk_24m[R]
Latch Clk	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
1041.667	1041.667				active clock edge time
1041.667	0.000				clk_24m
1041.667	0.000	tCL	RR	1	clk_24m_ibuf/I
1041.667	0.000	tINS	RR	470	clk_24m_ibuf/O
1041.937	0.270	tNET	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/ddr_sync/ddr_init_st_s0/CLK
1042.212	0.275	tC2Q	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/ddr_sync/ddr_init_st_s0/Q
1042.482	0.270	tNET	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state.RESET_WAIT_s19/I1
1042.854	0.372	tINS	RR	4	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state.RESET_WAIT_s19/F
1043.124	0.270	tNET	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state.LOAD_MR_s26/I1
1043.496	0.372	tINS	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state.LOAD_MR_s26/F
1043.766	0.270	tNET	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state.WRLVL_LOAD_MR1_s20/I1
1044.137	0.372	tINS	RR	17	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state.WRLVL_LOAD_MR1_s20/F
1044.407	0.270	tNET	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state.WRLVL_LOAD_MR1_s19/I0
1044.786	0.379	tINS	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state.WRLVL_LOAD_MR1_s19/F
1045.056	0.270	tNET	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_state.WRLVL_LOAD_MR1_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
1041.894	1041.894				active clock edge time
1041.894	0.000				DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
1042.155	0.261	tCL	RR	3995	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1042.425	0.270	tNET	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_state.WRLVL_LOAD_MR1_s0/CLK
1042.390	-0.035	tUnc			DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_state.WRLVL_LOAD_MR1_s0
1042.344	-0.046	tSu		1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_state.WRLVL_LOAD_MR1_s0

Path Statistics:

Clock Skew:	0.261
Setup Relationship:	0.228
Logic Level:	5
Arrival Clock Path Delay:	cell: 0.000, 0.000%; route: 0.270, 100.000%
Arrival Data Path Delay:	cell: 1.494, 47.893%; route: 1.350, 43.278%; tC2Q: 0.275, 8.829%
Required Clock Path Delay:	cell: 0.000, 0.000%; route: 0.270, 100.000%

Path 13

Path Summary:

Slack	-2.706
Data Arrival Time	1045.049
Data Required Time	1042.343
From	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/ddr_sync/ddr_init_st_s0
To	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_state.EYE_SCAN_s0
Launch Clk	clk_24m[R]
Latch Clk	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
1041.667	1041.667				active clock edge time
1041.667	0.000				clk_24m
1041.667	0.000	tCL	RR	1	clk_24m_ibuf/I
1041.667	0.000	tINS	RR	470	clk_24m_ibuf/O
1041.937	0.270	tNET	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/ddr_sync/ddr_init_st_s0/CLK
1042.212	0.275	tC2Q	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/ddr_sync/ddr_init_st_s0/Q
1042.482	0.270	tNET	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state.RESET_WAIT_s19/I1
1042.854	0.372	tINS	RR	4	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state.RESET_WAIT_s19/F
1043.124	0.270	tNET	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state.LOAD_MR_s26/I1
1043.496	0.372	tINS	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state.LOAD_MR_s26/F
1043.766	0.270	tNET	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state.WRLVL_LOAD_MR1_s20/I1
1044.137	0.372	tINS	RR	17	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state.WRLVL_LOAD_MR1_s20/F
1044.407	0.270	tNET	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state.EYE_SCAN_s21/I1
1044.779	0.372	tINS	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state.EYE_SCAN_s21/F
1045.049	0.270	tNET	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_state.EYE_SCAN_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
1041.894	1041.894				active clock edge time
1041.894	0.000				DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
1042.155	0.261	tCL	RR	3995	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1042.425	0.270	tNET	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_state.EYE_SCAN_s0/CLK
1042.390	-0.035	tUnc			DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_state.EYE_SCAN_s0
1042.344	-0.046	tSu		1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_state.EYE_SCAN_s0

Path Statistics:

Clock Skew:	0.261
Setup Relationship:	0.228
Logic Level:	5
Arrival Clock Path Delay:	cell: 0.000, 0.000%; route: 0.270, 100.000%
Arrival Data Path Delay:	cell: 1.487, 47.773%; route: 1.350, 43.378%; tC2Q: 0.275, 8.849%
Required Clock Path Delay:	cell: 0.000, 0.000%; route: 0.270, 100.000%

Path 14

Path Summary:

Slack	-2.706
Data Arrival Time	1045.049
Data Required Time	1042.343
From	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/ddr_sync/ddr_init_st_s0
To	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_state.RESET_WAIT_s0
Launch Clk	clk_24m[R]
Latch Clk	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
1041.667	1041.667				active clock edge time
1041.667	0.000				clk_24m
1041.667	0.000	tCL	RR	1	clk_24m_ibuf/I
1041.667	0.000	tINS	RR	470	clk_24m_ibuf/O
1041.937	0.270	tNET	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/ddr_sync/ddr_init_st_s0/CLK
1042.212	0.275	tC2Q	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/ddr_sync/ddr_init_st_s0/Q
1042.482	0.270	tNET	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state.RESET_WAIT_s19/I1
1042.854	0.372	tINS	RR	4	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state.RESET_WAIT_s19/F
1043.124	0.270	tNET	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state.LOAD_MR_s26/I1
1043.496	0.372	tINS	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state.LOAD_MR_s26/F
1043.766	0.270	tNET	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state.WRLVL_LOAD_MR1_s20/I1
1044.137	0.372	tINS	RR	17	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state.WRLVL_LOAD_MR1_s20/F
1044.407	0.270	tNET	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state.RESET_WAIT_s18/I1
1044.779	0.372	tINS	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state.RESET_WAIT_s18/F
1045.049	0.270	tNET	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_state.RESET_WAIT_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
1041.894	1041.894				active clock edge time
1041.894	0.000				DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
1042.155	0.261	tCL	RR	3995	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1042.425	0.270	tNET	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_state.RESET_WAIT_s0/CLK
1042.390	-0.035	tUnc			DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_state.RESET_WAIT_s0
1042.344	-0.046	tSu		1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_state.RESET_WAIT_s0

Path Statistics:

Clock Skew:	0.261
Setup Relationship:	0.228
Logic Level:	5
Arrival Clock Path Delay:	cell: 0.000, 0.000%; route: 0.270, 100.000%
Arrival Data Path Delay:	cell: 1.487, 47.773%; route: 1.350, 43.378%; tC2Q: 0.275, 8.849%
Required Clock Path Delay:	cell: 0.000, 0.000%; route: 0.270, 100.000%

Path 15

Path Summary:

Slack	-2.666
Data Arrival Time	1045.009
Data Required Time	1042.343
From	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/ddr_sync/ddr_init_st_s0
To	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_state.BURST_MODE_RECOVER_s0
Launch Clk	clk_24m[R]
Latch Clk	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
1041.667	1041.667				active clock edge time
1041.667	0.000				clk_24m
1041.667	0.000	tCL	RR	1	clk_24m_ibuf/I
1041.667	0.000	tINS	RR	470	clk_24m_ibuf/O
1041.937	0.270	tNET	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/ddr_sync/ddr_init_st_s0/CLK
1042.212	0.275	tC2Q	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/ddr_sync/ddr_init_st_s0/Q
1042.482	0.270	tNET	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state.RESET_WAIT_s19/I1
1042.854	0.372	tINS	RR	4	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state.RESET_WAIT_s19/F
1043.124	0.270	tNET	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state.LOAD_MR_s26/I1
1043.496	0.372	tINS	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state.LOAD_MR_s26/F
1043.766	0.270	tNET	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state.WRLVL_LOAD_MR1_s20/I1
1044.137	0.372	tINS	RR	17	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state.WRLVL_LOAD_MR1_s20/F
1044.407	0.270	tNET	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state.BURST_MODE_RECOVER_s18/I2
1044.739	0.332	tINS	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state.BURST_MODE_RECOVER_s18/F
1045.009	0.270	tNET	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_state.BURST_MODE_RECOVER_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
1041.894	1041.894				active clock edge time
1041.894	0.000				DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
1042.155	0.261	tCL	RR	3995	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1042.425	0.270	tNET	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_state.BURST_MODE_RECOVER_s0/CLK
1042.390	-0.035	tUnc			DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_state.BURST_MODE_RECOVER_s0
1042.344	-0.046	tSu		1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_state.BURST_MODE_RECOVER_s0

Path Statistics:

Clock Skew:	0.261
Setup Relationship:	0.228
Logic Level:	5
Arrival Clock Path Delay:	cell: 0.000, 0.000%; route: 0.270, 100.000%
Arrival Data Path Delay:	cell: 1.447, 47.100%; route: 1.350, 43.937%; tC2Q: 0.275, 8.963%
Required Clock Path Delay:	cell: 0.000, 0.000%; route: 0.270, 100.000%

Path 16

Path Summary:

Slack	-2.666
Data Arrival Time	1045.009
Data Required Time	1042.343
From	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/ddr_sync/ddr_init_st_s0
To	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_state.WRITE_LEVELING_s0
Launch Clk	clk_24m[R]
Latch Clk	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
1041.667	1041.667				active clock edge time
1041.667	0.000				clk_24m
1041.667	0.000	tCL	RR	1	clk_24m_ibuf/I
1041.667	0.000	tINS	RR	470	clk_24m_ibuf/O
1041.937	0.270	tNET	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/ddr_sync/ddr_init_st_s0/CLK
1042.212	0.275	tC2Q	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/ddr_sync/ddr_init_st_s0/Q
1042.482	0.270	tNET	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state.RESET_WAIT_s19/I1
1042.854	0.372	tINS	RR	4	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state.RESET_WAIT_s19/F
1043.124	0.270	tNET	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state.LOAD_MR_s26/I1
1043.496	0.372	tINS	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state.LOAD_MR_s26/F
1043.766	0.270	tNET	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state.WRLVL_LOAD_MR1_s20/I1
1044.137	0.372	tINS	RR	17	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state.WRLVL_LOAD_MR1_s20/F
1044.407	0.270	tNET	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state.WRITE_LEVELING_s18/I2
1044.739	0.332	tINS	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state.WRITE_LEVELING_s18/F
1045.009	0.270	tNET	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_state.WRITE_LEVELING_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
1041.894	1041.894				active clock edge time
1041.894	0.000				DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
1042.155	0.261	tCL	RR	3995	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1042.425	0.270	tNET	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_state.WRITE_LEVELING_s0/CLK
1042.390	-0.035	tUnc			DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_state.WRITE_LEVELING_s0
1042.344	-0.046	tSu		1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_state.WRITE_LEVELING_s0

Path Statistics:

Clock Skew:	0.261
Setup Relationship:	0.228
Logic Level:	5
Arrival Clock Path Delay:	cell: 0.000, 0.000%; route: 0.270, 100.000%
Arrival Data Path Delay:	cell: 1.447, 47.100%; route: 1.350, 43.937%; tC2Q: 0.275, 8.963%
Required Clock Path Delay:	cell: 0.000, 0.000%; route: 0.270, 100.000%

Path 17

Path Summary:

Slack	-2.666
Data Arrival Time	1045.009
Data Required Time	1042.343
From	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/ddr_sync/ddr_init_st_s0
To	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_state.WRLVL_LOAD_MR2_s0
Launch Clk	clk_24m[R]
Latch Clk	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
1041.667	1041.667				active clock edge time
1041.667	0.000				clk_24m
1041.667	0.000	tCL	RR	1	clk_24m_ibuf/I
1041.667	0.000	tINS	RR	470	clk_24m_ibuf/O
1041.937	0.270	tNET	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/ddr_sync/ddr_init_st_s0/CLK
1042.212	0.275	tC2Q	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/ddr_sync/ddr_init_st_s0/Q
1042.482	0.270	tNET	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state.RESET_WAIT_s19/I1
1042.854	0.372	tINS	RR	4	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state.RESET_WAIT_s19/F
1043.124	0.270	tNET	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state.LOAD_MR_s26/I1
1043.496	0.372	tINS	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state.LOAD_MR_s26/F
1043.766	0.270	tNET	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state.WRLVL_LOAD_MR1_s20/I1
1044.137	0.372	tINS	RR	17	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state.WRLVL_LOAD_MR1_s20/F
1044.407	0.270	tNET	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state.WRLVL_LOAD_MR2_s18/I2
1044.739	0.332	tINS	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state.WRLVL_LOAD_MR2_s18/F
1045.009	0.270	tNET	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_state.WRLVL_LOAD_MR2_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
1041.894	1041.894				active clock edge time
1041.894	0.000				DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
1042.155	0.261	tCL	RR	3995	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1042.425	0.270	tNET	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_state.WRLVL_LOAD_MR2_s0/CLK
1042.390	-0.035	tUnc			DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_state.WRLVL_LOAD_MR2_s0
1042.344	-0.046	tSu		1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_state.WRLVL_LOAD_MR2_s0

Path Statistics:

Clock Skew:	0.261
Setup Relationship:	0.228
Logic Level:	5
Arrival Clock Path Delay:	cell: 0.000, 0.000%; route: 0.270, 100.000%
Arrival Data Path Delay:	cell: 1.447, 47.100%; route: 1.350, 43.937%; tC2Q: 0.275, 8.963%
Required Clock Path Delay:	cell: 0.000, 0.000%; route: 0.270, 100.000%

Path 18

Path Summary:

Slack	-2.341
Data Arrival Time	1044.684
Data Required Time	1042.343
From	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/ddr_sync/ddr_init_st_s0
To	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/timer_cnt0_0_s1
Launch Clk	clk_24m[R]
Latch Clk	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
1041.667	1041.667				active clock edge time
1041.667	0.000				clk_24m
1041.667	0.000	tCL	RR	1	clk_24m_ibuf/I
1041.667	0.000	tINS	RR	470	clk_24m_ibuf/O
1041.937	0.270	tNET	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/ddr_sync/ddr_init_st_s0/CLK
1042.212	0.275	tC2Q	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/ddr_sync/ddr_init_st_s0/Q
1042.482	0.270	tNET	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state.RESET_WAIT_s19/I1
1042.854	0.372	tINS	RR	4	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state.RESET_WAIT_s19/F
1043.124	0.270	tNET	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/timer_cnt0_7_s7/I3
1043.313	0.189	tINS	RR	2	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/timer_cnt0_7_s7/F
1043.583	0.270	tNET	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/n1235_s5/I3
1043.772	0.189	tINS	RR	7	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/n1235_s5/F
1044.042	0.270	tNET	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/n1235_s3/I1
1044.414	0.372	tINS	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/n1235_s3/F
1044.684	0.270	tNET	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/timer_cnt0_0_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
1041.894	1041.894				active clock edge time
1041.894	0.000				DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
1042.155	0.261	tCL	RR	3995	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1042.425	0.270	tNET	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/timer_cnt0_0_s1/CLK
1042.390	-0.035	tUnc			DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/timer_cnt0_0_s1
1042.344	-0.046	tSu		1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/timer_cnt0_0_s1

Path Statistics:

Clock Skew:	0.261
Setup Relationship:	0.228
Logic Level:	5
Arrival Clock Path Delay:	cell: 0.000, 0.000%; route: 0.270, 100.000%
Arrival Data Path Delay:	cell: 1.121, 40.826%; route: 1.350, 49.148%; tC2Q: 0.275, 10.026%
Required Clock Path Delay:	cell: 0.000, 0.000%; route: 0.270, 100.000%

Path 19

Path Summary:

Slack	-2.301
Data Arrival Time	1044.644
Data Required Time	1042.343
From	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/ddr_sync/ddr_init_st_s0
To	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/timer_cnt0_1_s1
Launch Clk	clk_24m[R]
Latch Clk	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
1041.667	1041.667				active clock edge time
1041.667	0.000				clk_24m
1041.667	0.000	tCL	RR	1	clk_24m_ibuf/I
1041.667	0.000	tINS	RR	470	clk_24m_ibuf/O
1041.937	0.270	tNET	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/ddr_sync/ddr_init_st_s0/CLK
1042.212	0.275	tC2Q	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/ddr_sync/ddr_init_st_s0/Q
1042.482	0.270	tNET	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state.RESET_WAIT_s19/I1
1042.854	0.372	tINS	RR	4	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state.RESET_WAIT_s19/F
1043.124	0.270	tNET	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/timer_cnt0_7_s7/I3
1043.313	0.189	tINS	RR	2	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/timer_cnt0_7_s7/F
1043.583	0.270	tNET	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/n1235_s5/I3
1043.772	0.189	tINS	RR	7	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/n1235_s5/F
1044.042	0.270	tNET	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/n1234_s3/I2
1044.374	0.332	tINS	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/n1234_s3/F
1044.644	0.270	tNET	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/timer_cnt0_1_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
1041.894	1041.894				active clock edge time
1041.894	0.000				DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
1042.155	0.261	tCL	RR	3995	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1042.425	0.270	tNET	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/timer_cnt0_1_s1/CLK
1042.390	-0.035	tUnc			DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/timer_cnt0_1_s1
1042.344	-0.046	tSu		1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/timer_cnt0_1_s1

Path Statistics:

Clock Skew:	0.261
Setup Relationship:	0.228
Logic Level:	5
Arrival Clock Path Delay:	cell: 0.000, 0.000%; route: 0.270, 100.000%
Arrival Data Path Delay:	cell: 1.082, 39.960%; route: 1.350, 49.867%; tC2Q: 0.275, 10.173%
Required Clock Path Delay:	cell: 0.000, 0.000%; route: 0.270, 100.000%

Path 20

Path Summary:

Slack	-2.301
Data Arrival Time	1044.644
Data Required Time	1042.343
From	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/ddr_sync/ddr_init_st_s0
To	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/timer_cnt0_3_s1
Launch Clk	clk_24m[R]
Latch Clk	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
1041.667	1041.667				active clock edge time
1041.667	0.000				clk_24m
1041.667	0.000	tCL	RR	1	clk_24m_ibuf/I
1041.667	0.000	tINS	RR	470	clk_24m_ibuf/O
1041.937	0.270	tNET	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/ddr_sync/ddr_init_st_s0/CLK
1042.212	0.275	tC2Q	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/ddr_sync/ddr_init_st_s0/Q
1042.482	0.270	tNET	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state.RESET_WAIT_s19/I1
1042.854	0.372	tINS	RR	4	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state.RESET_WAIT_s19/F
1043.124	0.270	tNET	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/timer_cnt0_7_s7/I3
1043.313	0.189	tINS	RR	2	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/timer_cnt0_7_s7/F
1043.583	0.270	tNET	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/n1235_s5/I3
1043.772	0.189	tINS	RR	7	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/n1235_s5/F
1044.042	0.270	tNET	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/n1232_s3/I2
1044.374	0.332	tINS	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/n1232_s3/F
1044.644	0.270	tNET	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/timer_cnt0_3_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
1041.894	1041.894				active clock edge time
1041.894	0.000				DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
1042.155	0.261	tCL	RR	3995	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1042.425	0.270	tNET	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/timer_cnt0_3_s1/CLK
1042.390	-0.035	tUnc			DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/timer_cnt0_3_s1
1042.344	-0.046	tSu		1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/timer_cnt0_3_s1

Path Statistics:

Clock Skew:	0.261
Setup Relationship:	0.228
Logic Level:	5
Arrival Clock Path Delay:	cell: 0.000, 0.000%; route: 0.270, 100.000%
Arrival Data Path Delay:	cell: 1.082, 39.960%; route: 1.350, 49.867%; tC2Q: 0.275, 10.173%
Required Clock Path Delay:	cell: 0.000, 0.000%; route: 0.270, 100.000%

Path 21

Path Summary:

Slack	-2.301
Data Arrival Time	1044.644
Data Required Time	1042.343
From	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/ddr_sync/ddr_init_st_s0
To	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/timer_cnt0_5_s1
Launch Clk	clk_24m[R]
Latch Clk	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
1041.667	1041.667				active clock edge time
1041.667	0.000				clk_24m
1041.667	0.000	tCL	RR	1	clk_24m_ibuf/I
1041.667	0.000	tINS	RR	470	clk_24m_ibuf/O
1041.937	0.270	tNET	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/ddr_sync/ddr_init_st_s0/CLK
1042.212	0.275	tC2Q	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/ddr_sync/ddr_init_st_s0/Q
1042.482	0.270	tNET	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state.RESET_WAIT_s19/I1
1042.854	0.372	tINS	RR	4	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state.RESET_WAIT_s19/F
1043.124	0.270	tNET	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/timer_cnt0_7_s7/I3
1043.313	0.189	tINS	RR	2	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/timer_cnt0_7_s7/F
1043.583	0.270	tNET	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/n1235_s5/I3
1043.772	0.189	tINS	RR	7	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/n1235_s5/F
1044.042	0.270	tNET	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/n1230_s3/I2
1044.374	0.332	tINS	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/n1230_s3/F
1044.644	0.270	tNET	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/timer_cnt0_5_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
1041.894	1041.894				active clock edge time
1041.894	0.000				DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
1042.155	0.261	tCL	RR	3995	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1042.425	0.270	tNET	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/timer_cnt0_5_s1/CLK
1042.390	-0.035	tUnc			DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/timer_cnt0_5_s1
1042.344	-0.046	tSu		1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/timer_cnt0_5_s1

Path Statistics:

Clock Skew:	0.261
Setup Relationship:	0.228
Logic Level:	5
Arrival Clock Path Delay:	cell: 0.000, 0.000%; route: 0.270, 100.000%
Arrival Data Path Delay:	cell: 1.082, 39.960%; route: 1.350, 49.867%; tC2Q: 0.275, 10.173%
Required Clock Path Delay:	cell: 0.000, 0.000%; route: 0.270, 100.000%

Path 22

Path Summary:

Slack	-2.301
Data Arrival Time	1044.644
Data Required Time	1042.343
From	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/ddr_sync/ddr_init_st_s0
To	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/timer_cnt0_6_s1
Launch Clk	clk_24m[R]
Latch Clk	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
1041.667	1041.667				active clock edge time
1041.667	0.000				clk_24m
1041.667	0.000	tCL	RR	1	clk_24m_ibuf/I
1041.667	0.000	tINS	RR	470	clk_24m_ibuf/O
1041.937	0.270	tNET	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/ddr_sync/ddr_init_st_s0/CLK
1042.212	0.275	tC2Q	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/ddr_sync/ddr_init_st_s0/Q
1042.482	0.270	tNET	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state.RESET_WAIT_s19/I1
1042.854	0.372	tINS	RR	4	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state.RESET_WAIT_s19/F
1043.124	0.270	tNET	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/timer_cnt0_7_s7/I3
1043.313	0.189	tINS	RR	2	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/timer_cnt0_7_s7/F
1043.583	0.270	tNET	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/n1235_s5/I3
1043.772	0.189	tINS	RR	7	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/n1235_s5/F
1044.042	0.270	tNET	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/n1229_s3/I2
1044.374	0.332	tINS	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/n1229_s3/F
1044.644	0.270	tNET	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/timer_cnt0_6_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
1041.894	1041.894				active clock edge time
1041.894	0.000				DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
1042.155	0.261	tCL	RR	3995	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1042.425	0.270	tNET	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/timer_cnt0_6_s1/CLK
1042.390	-0.035	tUnc			DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/timer_cnt0_6_s1
1042.344	-0.046	tSu		1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/timer_cnt0_6_s1

Path Statistics:

Clock Skew:	0.261
Setup Relationship:	0.228
Logic Level:	5
Arrival Clock Path Delay:	cell: 0.000, 0.000%; route: 0.270, 100.000%
Arrival Data Path Delay:	cell: 1.082, 39.960%; route: 1.350, 49.867%; tC2Q: 0.275, 10.173%
Required Clock Path Delay:	cell: 0.000, 0.000%; route: 0.270, 100.000%

Path 23

Path Summary:

Slack	-2.158
Data Arrival Time	1044.501
Data Required Time	1042.343
From	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/ddr_sync/ddr_init_st_s0
To	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/timer_cnt0_2_s1
Launch Clk	clk_24m[R]
Latch Clk	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
1041.667	1041.667				active clock edge time
1041.667	0.000				clk_24m
1041.667	0.000	tCL	RR	1	clk_24m_ibuf/I
1041.667	0.000	tINS	RR	470	clk_24m_ibuf/O
1041.937	0.270	tNET	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/ddr_sync/ddr_init_st_s0/CLK
1042.212	0.275	tC2Q	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/ddr_sync/ddr_init_st_s0/Q
1042.482	0.270	tNET	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state.RESET_WAIT_s19/I1
1042.854	0.372	tINS	RR	4	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state.RESET_WAIT_s19/F
1043.124	0.270	tNET	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/timer_cnt0_7_s7/I3
1043.313	0.189	tINS	RR	2	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/timer_cnt0_7_s7/F
1043.583	0.270	tNET	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/n1235_s5/I3
1043.772	0.189	tINS	RR	7	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/n1235_s5/F
1044.042	0.270	tNET	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/n1233_s3/I3
1044.231	0.189	tINS	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/n1233_s3/F
1044.501	0.270	tNET	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/timer_cnt0_2_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
1041.894	1041.894				active clock edge time
1041.894	0.000				DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
1042.155	0.261	tCL	RR	3995	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1042.425	0.270	tNET	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/timer_cnt0_2_s1/CLK
1042.390	-0.035	tUnc			DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/timer_cnt0_2_s1
1042.344	-0.046	tSu		1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/timer_cnt0_2_s1

Path Statistics:

Clock Skew:	0.261
Setup Relationship:	0.228
Logic Level:	5
Arrival Clock Path Delay:	cell: 0.000, 0.000%; route: 0.270, 100.000%
Arrival Data Path Delay:	cell: 0.939, 36.609%; route: 1.350, 52.650%; tC2Q: 0.275, 10.741%
Required Clock Path Delay:	cell: 0.000, 0.000%; route: 0.270, 100.000%

Path 24

Path Summary:

Slack	-2.158
Data Arrival Time	1044.501
Data Required Time	1042.343
From	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/ddr_sync/ddr_init_st_s0
To	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/timer_cnt0_4_s1
Launch Clk	clk_24m[R]
Latch Clk	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
1041.667	1041.667				active clock edge time
1041.667	0.000				clk_24m
1041.667	0.000	tCL	RR	1	clk_24m_ibuf/I
1041.667	0.000	tINS	RR	470	clk_24m_ibuf/O
1041.937	0.270	tNET	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/ddr_sync/ddr_init_st_s0/CLK
1042.212	0.275	tC2Q	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/ddr_sync/ddr_init_st_s0/Q
1042.482	0.270	tNET	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state.RESET_WAIT_s19/I1
1042.854	0.372	tINS	RR	4	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state.RESET_WAIT_s19/F
1043.124	0.270	tNET	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/timer_cnt0_7_s7/I3
1043.313	0.189	tINS	RR	2	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/timer_cnt0_7_s7/F
1043.583	0.270	tNET	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/n1235_s5/I3
1043.772	0.189	tINS	RR	7	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/n1235_s5/F
1044.042	0.270	tNET	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/n1231_s3/I3
1044.231	0.189	tINS	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/n1231_s3/F
1044.501	0.270	tNET	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/timer_cnt0_4_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
1041.894	1041.894				active clock edge time
1041.894	0.000				DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
1042.155	0.261	tCL	RR	3995	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1042.425	0.270	tNET	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/timer_cnt0_4_s1/CLK
1042.390	-0.035	tUnc			DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/timer_cnt0_4_s1
1042.344	-0.046	tSu		1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/timer_cnt0_4_s1

Path Statistics:

Clock Skew:	0.261
Setup Relationship:	0.228
Logic Level:	5
Arrival Clock Path Delay:	cell: 0.000, 0.000%; route: 0.270, 100.000%
Arrival Data Path Delay:	cell: 0.939, 36.609%; route: 1.350, 52.650%; tC2Q: 0.275, 10.741%
Required Clock Path Delay:	cell: 0.000, 0.000%; route: 0.270, 100.000%

Path 25

Path Summary:

Slack	-2.032
Data Arrival Time	1044.375
Data Required Time	1042.343
From	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/ddr_sync/ddr_init_st_s0
To	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_state.ZQCL_s0
Launch Clk	clk_24m[R]
Latch Clk	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
1041.667	1041.667				active clock edge time
1041.667	0.000				clk_24m
1041.667	0.000	tCL	RR	1	clk_24m_ibuf/I
1041.667	0.000	tINS	RR	470	clk_24m_ibuf/O
1041.937	0.270	tNET	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/ddr_sync/ddr_init_st_s0/CLK
1042.212	0.275	tC2Q	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/ddr_sync/ddr_init_st_s0/Q
1042.482	0.270	tNET	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state.RESET_WAIT_s19/I1
1042.854	0.372	tINS	RR	4	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state.RESET_WAIT_s19/F
1043.124	0.270	tNET	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state.LOAD_MR_s33/I2
1043.456	0.332	tINS	RR	2	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state.LOAD_MR_s33/F
1043.726	0.270	tNET	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state.ZQCL_s22/I0
1044.105	0.379	tINS	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state.ZQCL_s22/F
1044.375	0.270	tNET	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_state.ZQCL_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
1041.894	1041.894				active clock edge time
1041.894	0.000				DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
1042.155	0.261	tCL	RR	3995	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1042.425	0.270	tNET	RR	1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_state.ZQCL_s0/CLK
1042.390	-0.035	tUnc			DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_state.ZQCL_s0
1042.344	-0.046	tSu		1	DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/init_state.ZQCL_s0

Path Statistics:

Clock Skew:	0.261
Setup Relationship:	0.228
Logic Level:	4
Arrival Clock Path Delay:	cell: 0.000, 0.000%; route: 0.270, 100.000%
Arrival Data Path Delay:	cell: 1.083, 44.407%; route: 1.080, 44.297%; tC2Q: 0.275, 11.296%
Required Clock Path Delay:	cell: 0.000, 0.000%; route: 0.270, 100.000%