Synthesis Messages

Report Title	GowinSynthesis Report
Design File	D:\Gowin\Gowin_V1.9.12.02_x64\IDE\ipcore\SERDES_IP\data\Upar_Arbiter\upar_arbiter.v D:\Gowin\Gowin_V1.9.12.02_x64\IDE\ipcore\SERDES_IP\data\Upar_Arbiter\upar_arbiter_wrap.v
GowinSynthesis Constraints File	---
Tool Version	V1.9.12.02 (64-bit)
Part Number	GW5AT-LV60PG484AES
Device	GW5AT-60
Device Version	B
Created Time	Tue Mar 17 15:10:11 2026
Legal Announcement	Copyright (C)2014-2026 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module	\~upar_arbiter_wrap.SerDes_Top
Synthesis Process	Running parser:     CPU time = 0h 0m 0.156s, Elapsed time = 0h 0m 0.158s, Peak memory usage = 75.992MB Running netlist conversion:     CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.009s, Peak memory usage = 75.992MB Running device independent optimization:     Optimizing Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.016s, Peak memory usage = 75.992MB     Optimizing Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.011s, Peak memory usage = 75.992MB     Optimizing Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.016s, Peak memory usage = 75.992MB Running inference:     Inferring Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.009s, Peak memory usage = 75.992MB     Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 75.992MB     Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 75.992MB     Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 75.992MB Running technical mapping:     Tech-Mapping Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.015s, Peak memory usage = 75.992MB     Tech-Mapping Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.007s, Peak memory usage = 75.992MB     Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 75.992MB     Tech-Mapping Phase 3: CPU time = 0h 0m 0.14s, Elapsed time = 0h 0m 0.193s, Peak memory usage = 99.141MB     Tech-Mapping Phase 4: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.068s, Peak memory usage = 99.141MB Generate output files:     CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.03s, Peak memory usage = 99.141MB
Total Time and Memory Usage	CPU time = 0h 0m 0.463s, Elapsed time = 0h 0m 0.541s, Peak memory usage = 99.141MB

Resource

Resource Usage Summary

Resource	Usage
I/O Port	511
I/O Buf	511
IBUF	299
OBUF	212
Register	282
DFFPE	4
DFFCE	278
LUT	369
LUT2	132
LUT3	165
LUT4	72
INV	1
INV	1

Resource Utilization Summary

Resource	Usage	Utilization
Logic	370(370 LUT, 0 ALU) / 59904	<1%
Register	282 / 60780	<1%
--Register as Latch	0 / 60780	0%
--Register as FF	282 / 60780	<1%
BSRAM	0 / 118	0%

Timing

Clock Summary:

NO.	Clock Name	Type	Period	Frequency(MHz)	Rise	Fall	Source	Master	Object
1	upar_clk_i	Base	10.000	100.000	0.000	5.000			upar_clk_i_ibuf/I

Max Frequency Summary:

NO.	Clock Name	Constraint	Actual Fmax	Logic Level	Entity
1	upar_clk_i	100.000(MHz)	321.130(MHz)	4	TOP

Detail Timing Paths Information

Path 1

Path Summary:

Slack	6.886
Data Arrival Time	3.394
Data Required Time	10.280
From	u_upar_arbiter/cur_grant_3_s0
To	u_upar_arbiter/drp_num_1_s0
Launch Clk	upar_clk_i[R]
Latch Clk	upar_clk_i[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
0.000	0.000				active clock edge time
0.000	0.000				upar_clk_i
0.000	0.000	tCL	RR	1	upar_clk_i_ibuf/I
0.000	0.000	tINS	RR	282	upar_clk_i_ibuf/O
0.337	0.337	tNET	RR	1	u_upar_arbiter/cur_grant_3_s0/CLK
0.682	0.344	tC2Q	RR	2	u_upar_arbiter/cur_grant_3_s0/Q
1.019	0.337	tNET	RR	1	u_upar_arbiter/n341_s2/I2
1.434	0.415	tINS	RR	4	u_upar_arbiter/n341_s2/F
1.772	0.337	tNET	RR	1	u_upar_arbiter/drp_num_pre[3]_1_s1/I0
2.245	0.474	tINS	RR	1	u_upar_arbiter/drp_num_pre[3]_1_s1/F
2.583	0.337	tNET	RR	1	u_upar_arbiter/drp_num_pre[3]_1_s0/I0
3.057	0.474	tINS	RR	1	u_upar_arbiter/drp_num_pre[3]_1_s0/F
3.394	0.337	tNET	RR	1	u_upar_arbiter/drp_num_1_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
10.000	10.000				active clock edge time
10.000	0.000				upar_clk_i
10.000	0.000	tCL	RR	1	upar_clk_i_ibuf/I
10.000	0.000	tINS	RR	282	upar_clk_i_ibuf/O
10.337	0.337	tNET	RR	1	u_upar_arbiter/drp_num_1_s0/CLK
10.280	-0.057	tSu		1	u_upar_arbiter/drp_num_1_s0

Path Statistics:

Clock Skew:	0.000
Setup Relationship:	10.000
Logic Level:	4
Arrival Clock Path Delay:	cell: 0.000, 0.000%; route: 0.337, 100.000%
Arrival Data Path Delay:	cell: 1.362, 44.572%; route: 1.350, 44.166%; tC2Q: 0.344, 11.262%
Required Clock Path Delay:	cell: 0.000, 0.000%; route: 0.337, 100.000%

Path 2

Path Summary:

Slack	6.945
Data Arrival Time	3.336
Data Required Time	10.280
From	u_upar_arbiter/judg_addr_state_cnt_0_s0
To	u_upar_arbiter/cur_state_0_s0
Launch Clk	upar_clk_i[R]
Latch Clk	upar_clk_i[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
0.000	0.000				active clock edge time
0.000	0.000				upar_clk_i
0.000	0.000	tCL	RR	1	upar_clk_i_ibuf/I
0.000	0.000	tINS	RR	282	upar_clk_i_ibuf/O
0.337	0.337	tNET	RR	1	u_upar_arbiter/judg_addr_state_cnt_0_s0/CLK
0.682	0.344	tC2Q	RR	72	u_upar_arbiter/judg_addr_state_cnt_0_s0/Q
1.019	0.337	tNET	RR	1	u_upar_arbiter/n689_s2/I0
1.493	0.474	tINS	RR	2	u_upar_arbiter/n689_s2/F
1.830	0.337	tNET	RR	1	u_upar_arbiter/next_state_0_s7/I2
2.245	0.415	tINS	RR	1	u_upar_arbiter/next_state_0_s7/F
2.583	0.337	tNET	RR	1	u_upar_arbiter/next_state_0_s5/I2
2.998	0.415	tINS	RR	1	u_upar_arbiter/next_state_0_s5/F
3.336	0.337	tNET	RR	1	u_upar_arbiter/cur_state_0_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
10.000	10.000				active clock edge time
10.000	0.000				upar_clk_i
10.000	0.000	tCL	RR	1	upar_clk_i_ibuf/I
10.000	0.000	tINS	RR	282	upar_clk_i_ibuf/O
10.337	0.337	tNET	RR	1	u_upar_arbiter/cur_state_0_s0/CLK
10.280	-0.057	tSu		1	u_upar_arbiter/cur_state_0_s0

Path Statistics:

Clock Skew:	0.000
Setup Relationship:	10.000
Logic Level:	4
Arrival Clock Path Delay:	cell: 0.000, 0.000%; route: 0.337, 100.000%
Arrival Data Path Delay:	cell: 1.304, 43.490%; route: 1.350, 45.028%; tC2Q: 0.344, 11.482%
Required Clock Path Delay:	cell: 0.000, 0.000%; route: 0.337, 100.000%

Path 3

Path Summary:

Slack	7.003
Data Arrival Time	3.277
Data Required Time	10.280
From	u_upar_arbiter/cur_grant_2_s0
To	u_upar_arbiter/drp_num_0_s0
Launch Clk	upar_clk_i[R]
Latch Clk	upar_clk_i[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
0.000	0.000				active clock edge time
0.000	0.000				upar_clk_i
0.000	0.000	tCL	RR	1	upar_clk_i_ibuf/I
0.000	0.000	tINS	RR	282	upar_clk_i_ibuf/O
0.337	0.337	tNET	RR	1	u_upar_arbiter/cur_grant_2_s0/CLK
0.682	0.344	tC2Q	RR	1	u_upar_arbiter/cur_grant_2_s0/Q
1.019	0.337	tNET	RR	1	u_upar_arbiter/n341_s3/I2
1.434	0.415	tINS	RR	6	u_upar_arbiter/n341_s3/F
1.772	0.337	tNET	RR	1	u_upar_arbiter/drp_num_pre[3]_0_s1/I2
2.187	0.415	tINS	RR	1	u_upar_arbiter/drp_num_pre[3]_0_s1/F
2.524	0.337	tNET	RR	1	u_upar_arbiter/drp_num_pre[3]_0_s0/I2
2.940	0.415	tINS	RR	1	u_upar_arbiter/drp_num_pre[3]_0_s0/F
3.277	0.337	tNET	RR	1	u_upar_arbiter/drp_num_0_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
10.000	10.000				active clock edge time
10.000	0.000				upar_clk_i
10.000	0.000	tCL	RR	1	upar_clk_i_ibuf/I
10.000	0.000	tINS	RR	282	upar_clk_i_ibuf/O
10.337	0.337	tNET	RR	1	u_upar_arbiter/drp_num_0_s0/CLK
10.280	-0.057	tSu		1	u_upar_arbiter/drp_num_0_s0

Path Statistics:

Clock Skew:	0.000
Setup Relationship:	10.000
Logic Level:	4
Arrival Clock Path Delay:	cell: 0.000, 0.000%; route: 0.337, 100.000%
Arrival Data Path Delay:	cell: 1.245, 42.365%; route: 1.350, 45.924%; tC2Q: 0.344, 11.711%
Required Clock Path Delay:	cell: 0.000, 0.000%; route: 0.337, 100.000%

Path 4

Path Summary:

Slack	7.003
Data Arrival Time	3.277
Data Required Time	10.280
From	u_upar_arbiter/cur_grant_2_s0
To	u_upar_arbiter/cur_grant_1_s0
Launch Clk	upar_clk_i[R]
Latch Clk	upar_clk_i[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
0.000	0.000				active clock edge time
0.000	0.000				upar_clk_i
0.000	0.000	tCL	RR	1	upar_clk_i_ibuf/I
0.000	0.000	tINS	RR	282	upar_clk_i_ibuf/O
0.337	0.337	tNET	RR	1	u_upar_arbiter/cur_grant_2_s0/CLK
0.682	0.344	tC2Q	RR	1	u_upar_arbiter/cur_grant_2_s0/Q
1.019	0.337	tNET	RR	1	u_upar_arbiter/n341_s3/I2
1.434	0.415	tINS	RR	6	u_upar_arbiter/n341_s3/F
1.772	0.337	tNET	RR	1	u_upar_arbiter/n343_s1/I2
2.187	0.415	tINS	RR	1	u_upar_arbiter/n343_s1/F
2.524	0.337	tNET	RR	1	u_upar_arbiter/n343_s0/I2
2.940	0.415	tINS	RR	1	u_upar_arbiter/n343_s0/F
3.277	0.337	tNET	RR	1	u_upar_arbiter/cur_grant_1_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
10.000	10.000				active clock edge time
10.000	0.000				upar_clk_i
10.000	0.000	tCL	RR	1	upar_clk_i_ibuf/I
10.000	0.000	tINS	RR	282	upar_clk_i_ibuf/O
10.337	0.337	tNET	RR	1	u_upar_arbiter/cur_grant_1_s0/CLK
10.280	-0.057	tSu		1	u_upar_arbiter/cur_grant_1_s0

Path Statistics:

Clock Skew:	0.000
Setup Relationship:	10.000
Logic Level:	4
Arrival Clock Path Delay:	cell: 0.000, 0.000%; route: 0.337, 100.000%
Arrival Data Path Delay:	cell: 1.245, 42.365%; route: 1.350, 45.924%; tC2Q: 0.344, 11.711%
Required Clock Path Delay:	cell: 0.000, 0.000%; route: 0.337, 100.000%

Path 5

Path Summary:

Slack	7.361
Data Arrival Time	2.919
Data Required Time	10.280
From	u_upar_arbiter/cur_grant_0_s0
To	u_upar_arbiter/cur_grant_3_s0
Launch Clk	upar_clk_i[R]
Latch Clk	upar_clk_i[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
0.000	0.000				active clock edge time
0.000	0.000				upar_clk_i
0.000	0.000	tCL	RR	1	upar_clk_i_ibuf/I
0.000	0.000	tINS	RR	282	upar_clk_i_ibuf/O
0.337	0.337	tNET	RR	1	u_upar_arbiter/cur_grant_0_s0/CLK
0.682	0.344	tC2Q	RR	3	u_upar_arbiter/cur_grant_0_s0/Q
1.019	0.337	tNET	RR	1	u_upar_arbiter/n341_s6/I2
1.434	0.415	tINS	RR	2	u_upar_arbiter/n341_s6/F
1.772	0.337	tNET	RR	1	u_upar_arbiter/n341_s7/I3
2.008	0.236	tINS	RR	3	u_upar_arbiter/n341_s7/F
2.346	0.337	tNET	RR	1	u_upar_arbiter/n341_s0/I3
2.582	0.236	tINS	RR	1	u_upar_arbiter/n341_s0/F
2.919	0.337	tNET	RR	1	u_upar_arbiter/cur_grant_3_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
10.000	10.000				active clock edge time
10.000	0.000				upar_clk_i
10.000	0.000	tCL	RR	1	upar_clk_i_ibuf/I
10.000	0.000	tINS	RR	282	upar_clk_i_ibuf/O
10.337	0.337	tNET	RR	1	u_upar_arbiter/cur_grant_3_s0/CLK
10.280	-0.057	tSu		1	u_upar_arbiter/cur_grant_3_s0

Path Statistics:

Clock Skew:	0.000
Setup Relationship:	10.000
Logic Level:	4
Arrival Clock Path Delay:	cell: 0.000, 0.000%; route: 0.337, 100.000%
Arrival Data Path Delay:	cell: 0.888, 34.379%; route: 1.350, 52.288%; tC2Q: 0.344, 13.333%
Required Clock Path Delay:	cell: 0.000, 0.000%; route: 0.337, 100.000%