Synthesis Messages
| Report Title | GowinSynthesis Report |
| Design File | D:\Gowin\Gowin_V1.9.12.02_x64\IDE\ipcore\SDIDecoder\data\sdi_decoder_top.v D:\Gowin\Gowin_V1.9.12.02_x64\IDE\ipcore\SDIDecoder\data\sdi_decoder_wrapper.v |
| GowinSynthesis Constraints File | --- |
| Tool Version | V1.9.12.02 (64-bit) |
| Part Number | GW5AT-LV60PG484AES |
| Device | GW5AT-60 |
| Device Version | B |
| Created Time | Thu Mar 12 14:38:12 2026 |
| Legal Announcement | Copyright (C)2014-2026 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
| Top Level Module | SDI_Decoder_Top |
| Synthesis Process | Running parser: CPU time = 0h 0m 0.39s, Elapsed time = 0h 0m 0.413s, Peak memory usage = 105.797MB Running netlist conversion: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.062s, Peak memory usage = 105.797MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0.265s, Elapsed time = 0h 0m 0.256s, Peak memory usage = 105.797MB Optimizing Phase 1: CPU time = 0h 0m 0.14s, Elapsed time = 0h 0m 0.139s, Peak memory usage = 105.797MB Optimizing Phase 2: CPU time = 0h 0m 0.265s, Elapsed time = 0h 0m 0.279s, Peak memory usage = 105.797MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0.109s, Elapsed time = 0h 0m 0.103s, Peak memory usage = 105.797MB Inferring Phase 1: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.072s, Peak memory usage = 105.797MB Inferring Phase 2: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.028s, Peak memory usage = 105.797MB Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.013s, Peak memory usage = 105.797MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0.328s, Elapsed time = 0h 0m 0.326s, Peak memory usage = 105.797MB Tech-Mapping Phase 1: CPU time = 0h 0m 0.093s, Elapsed time = 0h 0m 0.088s, Peak memory usage = 105.797MB Tech-Mapping Phase 2: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.039s, Peak memory usage = 105.797MB Tech-Mapping Phase 3: CPU time = 0h 0m 4s, Elapsed time = 0h 0m 4s, Peak memory usage = 127.520MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.296s, Elapsed time = 0h 0m 0.4s, Peak memory usage = 127.520MB Generate output files: CPU time = 0h 0m 0.281s, Elapsed time = 0h 0m 0.272s, Peak memory usage = 127.707MB |
| Total Time and Memory Usage | CPU time = 0h 0m 6s, Elapsed time = 0h 0m 6s, Peak memory usage = 127.707MB |
Resource
Resource Usage Summary
| Resource | Usage |
| I/O Port | 404 |
| I/O Buf | 333 |
| IBUF | 60 |
| OBUF | 273 |
| Register | 3003 |
| DFFRE | 13 |
| DFFPE | 16 |
| DFFCE | 2974 |
| LUT | 2479 |
| LUT2 | 241 |
| LUT3 | 1066 |
| LUT4 | 1172 |
| MUX | 72 |
| MUX2 | 72 |
| INV | 4 |
| INV | 4 |
| BSRAM | 14 |
| SDPB | 2 |
| SDPX9B | 12 |
Resource Utilization Summary
| Resource | Usage | Utilization |
| Logic | 2555(2555 LUT, 0 ALU) / 59904 | 5% |
| Register | 3003 / 60780 | 5% |
| --Register as Latch | 0 / 60780 | 0% |
| --Register as FF | 3003 / 60780 | 5% |
| BSRAM | 14 / 118 | 12% |
Timing
Clock Summary:
| NO. | Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
|---|---|---|---|---|---|---|---|---|---|
| 1 | I_clk | Base | 10.000 | 100.000 | 0.000 | 5.000 | I_clk_ibuf/I | ||
| 2 | I_drp_clk | Base | 10.000 | 100.000 | 0.000 | 5.000 | I_drp_clk_ibuf/I |
Max Frequency Summary:
| NO. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
|---|---|---|---|---|---|
| 1 | I_clk | 100.000(MHz) | 202.020(MHz) | 6 | TOP |
| 2 | I_drp_clk | 100.000(MHz) | 238.244(MHz) | 5 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:| Slack | 5.050 |
| Data Arrival Time | 5.007 |
| Data Required Time | 10.057 |
| From | sdi_decoder_wrapper_inst/rx_sd_wrapper_inst/rx_link_data_align_20bit_sd/align_data_d1_13_s0 |
| To | sdi_decoder_wrapper_inst/rx_sd_wrapper_inst/rx_sd_data_audio_data_inst/audio_allign_type_s1 |
| Launch Clk | I_clk[R] |
| Latch Clk | I_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | |||
| 0.000 | 0.000 | I_clk | |||
| 0.000 | 0.000 | tCL | RR | 1 | I_clk_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 2941 | I_clk_ibuf/O |
| 0.337 | 0.337 | tNET | RR | 1 | sdi_decoder_wrapper_inst/rx_sd_wrapper_inst/rx_link_data_align_20bit_sd/align_data_d1_13_s0/CLK |
| 0.682 | 0.344 | tC2Q | RR | 5 | sdi_decoder_wrapper_inst/rx_sd_wrapper_inst/rx_link_data_align_20bit_sd/align_data_d1_13_s0/Q |
| 1.019 | 0.337 | tNET | RR | 1 | sdi_decoder_wrapper_inst/rx_sd_wrapper_inst/rx_sd_allign_patch_inst/datas1_d1_3_s10/I0 |
| 1.493 | 0.474 | tINS | RR | 1 | sdi_decoder_wrapper_inst/rx_sd_wrapper_inst/rx_sd_allign_patch_inst/datas1_d1_3_s10/F |
| 1.830 | 0.337 | tNET | RR | 1 | sdi_decoder_wrapper_inst/rx_sd_wrapper_inst/rx_sd_allign_patch_inst/allign_patch_datas2_3_s/I2 |
| 2.245 | 0.415 | tINS | RR | 4 | sdi_decoder_wrapper_inst/rx_sd_wrapper_inst/rx_sd_allign_patch_inst/allign_patch_datas2_3_s/F |
| 2.583 | 0.337 | tNET | RR | 1 | sdi_decoder_wrapper_inst/rx_sd_wrapper_inst/rx_sd_data_audio_data_inst/n193_s7/I0 |
| 3.057 | 0.474 | tINS | RR | 1 | sdi_decoder_wrapper_inst/rx_sd_wrapper_inst/rx_sd_data_audio_data_inst/n193_s7/F |
| 3.394 | 0.337 | tNET | RR | 1 | sdi_decoder_wrapper_inst/rx_sd_wrapper_inst/rx_sd_data_audio_data_inst/n193_s2/I0 |
| 3.868 | 0.474 | tINS | RR | 1 | sdi_decoder_wrapper_inst/rx_sd_wrapper_inst/rx_sd_data_audio_data_inst/n193_s2/F |
| 4.205 | 0.337 | tNET | RR | 1 | sdi_decoder_wrapper_inst/rx_sd_wrapper_inst/rx_sd_data_audio_data_inst/n193_s0/I1 |
| 4.670 | 0.465 | tINS | RR | 2 | sdi_decoder_wrapper_inst/rx_sd_wrapper_inst/rx_sd_data_audio_data_inst/n193_s0/F |
| 5.007 | 0.337 | tNET | RR | 1 | sdi_decoder_wrapper_inst/rx_sd_wrapper_inst/rx_sd_data_audio_data_inst/audio_allign_type_s1/CE |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | |||
| 10.000 | 0.000 | I_clk | |||
| 10.000 | 0.000 | tCL | RR | 1 | I_clk_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 2941 | I_clk_ibuf/O |
| 10.337 | 0.337 | tNET | RR | 1 | sdi_decoder_wrapper_inst/rx_sd_wrapper_inst/rx_sd_data_audio_data_inst/audio_allign_type_s1/CLK |
| 10.057 | -0.280 | tSu | 1 | sdi_decoder_wrapper_inst/rx_sd_wrapper_inst/rx_sd_data_audio_data_inst/audio_allign_type_s1 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 6 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.337, 100.000% |
| Arrival Data Path Delay: | cell: 2.301, 49.265%; route: 2.025, 43.363%; tC2Q: 0.344, 7.372% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.337, 100.000% |
Path 2
Path Summary:| Slack | 5.050 |
| Data Arrival Time | 5.007 |
| Data Required Time | 10.057 |
| From | sdi_decoder_wrapper_inst/rx_sd_wrapper_inst/rx_link_data_align_20bit_sd/align_data_d1_13_s0 |
| To | sdi_decoder_wrapper_inst/rx_sd_wrapper_inst/rx_sd_fvhd_gen_inst/V_flag_s0 |
| Launch Clk | I_clk[R] |
| Latch Clk | I_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | |||
| 0.000 | 0.000 | I_clk | |||
| 0.000 | 0.000 | tCL | RR | 1 | I_clk_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 2941 | I_clk_ibuf/O |
| 0.337 | 0.337 | tNET | RR | 1 | sdi_decoder_wrapper_inst/rx_sd_wrapper_inst/rx_link_data_align_20bit_sd/align_data_d1_13_s0/CLK |
| 0.682 | 0.344 | tC2Q | RR | 5 | sdi_decoder_wrapper_inst/rx_sd_wrapper_inst/rx_link_data_align_20bit_sd/align_data_d1_13_s0/Q |
| 1.019 | 0.337 | tNET | RR | 1 | sdi_decoder_wrapper_inst/rx_sd_wrapper_inst/rx_sd_allign_patch_inst/datas1_d1_3_s10/I0 |
| 1.493 | 0.474 | tINS | RR | 1 | sdi_decoder_wrapper_inst/rx_sd_wrapper_inst/rx_sd_allign_patch_inst/datas1_d1_3_s10/F |
| 1.830 | 0.337 | tNET | RR | 1 | sdi_decoder_wrapper_inst/rx_sd_wrapper_inst/rx_sd_allign_patch_inst/allign_patch_datas2_3_s/I2 |
| 2.245 | 0.415 | tINS | RR | 4 | sdi_decoder_wrapper_inst/rx_sd_wrapper_inst/rx_sd_allign_patch_inst/allign_patch_datas2_3_s/F |
| 2.583 | 0.337 | tNET | RR | 1 | sdi_decoder_wrapper_inst/rx_sd_wrapper_inst/rx_sd_fvhd_gen_inst/H_flag_s4/I0 |
| 3.057 | 0.474 | tINS | RR | 1 | sdi_decoder_wrapper_inst/rx_sd_wrapper_inst/rx_sd_fvhd_gen_inst/H_flag_s4/F |
| 3.394 | 0.337 | tNET | RR | 1 | sdi_decoder_wrapper_inst/rx_sd_wrapper_inst/rx_sd_fvhd_gen_inst/H_flag_s3/I0 |
| 3.868 | 0.474 | tINS | RR | 4 | sdi_decoder_wrapper_inst/rx_sd_wrapper_inst/rx_sd_fvhd_gen_inst/H_flag_s3/F |
| 4.205 | 0.337 | tNET | RR | 1 | sdi_decoder_wrapper_inst/rx_sd_wrapper_inst/rx_sd_fvhd_gen_inst/eav_s0/I1 |
| 4.670 | 0.465 | tINS | RR | 4 | sdi_decoder_wrapper_inst/rx_sd_wrapper_inst/rx_sd_fvhd_gen_inst/eav_s0/F |
| 5.007 | 0.337 | tNET | RR | 1 | sdi_decoder_wrapper_inst/rx_sd_wrapper_inst/rx_sd_fvhd_gen_inst/V_flag_s0/CE |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | |||
| 10.000 | 0.000 | I_clk | |||
| 10.000 | 0.000 | tCL | RR | 1 | I_clk_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 2941 | I_clk_ibuf/O |
| 10.337 | 0.337 | tNET | RR | 1 | sdi_decoder_wrapper_inst/rx_sd_wrapper_inst/rx_sd_fvhd_gen_inst/V_flag_s0/CLK |
| 10.057 | -0.280 | tSu | 1 | sdi_decoder_wrapper_inst/rx_sd_wrapper_inst/rx_sd_fvhd_gen_inst/V_flag_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 6 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.337, 100.000% |
| Arrival Data Path Delay: | cell: 2.301, 49.265%; route: 2.025, 43.363%; tC2Q: 0.344, 7.372% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.337, 100.000% |
Path 3
Path Summary:| Slack | 5.050 |
| Data Arrival Time | 5.007 |
| Data Required Time | 10.057 |
| From | sdi_decoder_wrapper_inst/rx_sd_wrapper_inst/rx_link_data_align_20bit_sd/align_data_d1_13_s0 |
| To | sdi_decoder_wrapper_inst/rx_sd_wrapper_inst/rx_sd_fvhd_gen_inst/F_flag_s0 |
| Launch Clk | I_clk[R] |
| Latch Clk | I_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | |||
| 0.000 | 0.000 | I_clk | |||
| 0.000 | 0.000 | tCL | RR | 1 | I_clk_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 2941 | I_clk_ibuf/O |
| 0.337 | 0.337 | tNET | RR | 1 | sdi_decoder_wrapper_inst/rx_sd_wrapper_inst/rx_link_data_align_20bit_sd/align_data_d1_13_s0/CLK |
| 0.682 | 0.344 | tC2Q | RR | 5 | sdi_decoder_wrapper_inst/rx_sd_wrapper_inst/rx_link_data_align_20bit_sd/align_data_d1_13_s0/Q |
| 1.019 | 0.337 | tNET | RR | 1 | sdi_decoder_wrapper_inst/rx_sd_wrapper_inst/rx_sd_allign_patch_inst/datas1_d1_3_s10/I0 |
| 1.493 | 0.474 | tINS | RR | 1 | sdi_decoder_wrapper_inst/rx_sd_wrapper_inst/rx_sd_allign_patch_inst/datas1_d1_3_s10/F |
| 1.830 | 0.337 | tNET | RR | 1 | sdi_decoder_wrapper_inst/rx_sd_wrapper_inst/rx_sd_allign_patch_inst/allign_patch_datas2_3_s/I2 |
| 2.245 | 0.415 | tINS | RR | 4 | sdi_decoder_wrapper_inst/rx_sd_wrapper_inst/rx_sd_allign_patch_inst/allign_patch_datas2_3_s/F |
| 2.583 | 0.337 | tNET | RR | 1 | sdi_decoder_wrapper_inst/rx_sd_wrapper_inst/rx_sd_fvhd_gen_inst/H_flag_s4/I0 |
| 3.057 | 0.474 | tINS | RR | 1 | sdi_decoder_wrapper_inst/rx_sd_wrapper_inst/rx_sd_fvhd_gen_inst/H_flag_s4/F |
| 3.394 | 0.337 | tNET | RR | 1 | sdi_decoder_wrapper_inst/rx_sd_wrapper_inst/rx_sd_fvhd_gen_inst/H_flag_s3/I0 |
| 3.868 | 0.474 | tINS | RR | 4 | sdi_decoder_wrapper_inst/rx_sd_wrapper_inst/rx_sd_fvhd_gen_inst/H_flag_s3/F |
| 4.205 | 0.337 | tNET | RR | 1 | sdi_decoder_wrapper_inst/rx_sd_wrapper_inst/rx_sd_fvhd_gen_inst/eav_s0/I1 |
| 4.670 | 0.465 | tINS | RR | 4 | sdi_decoder_wrapper_inst/rx_sd_wrapper_inst/rx_sd_fvhd_gen_inst/eav_s0/F |
| 5.007 | 0.337 | tNET | RR | 1 | sdi_decoder_wrapper_inst/rx_sd_wrapper_inst/rx_sd_fvhd_gen_inst/F_flag_s0/CE |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | |||
| 10.000 | 0.000 | I_clk | |||
| 10.000 | 0.000 | tCL | RR | 1 | I_clk_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 2941 | I_clk_ibuf/O |
| 10.337 | 0.337 | tNET | RR | 1 | sdi_decoder_wrapper_inst/rx_sd_wrapper_inst/rx_sd_fvhd_gen_inst/F_flag_s0/CLK |
| 10.057 | -0.280 | tSu | 1 | sdi_decoder_wrapper_inst/rx_sd_wrapper_inst/rx_sd_fvhd_gen_inst/F_flag_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 6 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.337, 100.000% |
| Arrival Data Path Delay: | cell: 2.301, 49.265%; route: 2.025, 43.363%; tC2Q: 0.344, 7.372% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.337, 100.000% |
Path 4
Path Summary:| Slack | 5.273 |
| Data Arrival Time | 5.007 |
| Data Required Time | 10.280 |
| From | sdi_decoder_wrapper_inst/rx_sd_wrapper_inst/rx_link_data_align_20bit_sd/align_data_d1_13_s0 |
| To | sdi_decoder_wrapper_inst/rx_sd_wrapper_inst/rx_sd_fvhd_gen_inst/de_flag_s1 |
| Launch Clk | I_clk[R] |
| Latch Clk | I_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | |||
| 0.000 | 0.000 | I_clk | |||
| 0.000 | 0.000 | tCL | RR | 1 | I_clk_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 2941 | I_clk_ibuf/O |
| 0.337 | 0.337 | tNET | RR | 1 | sdi_decoder_wrapper_inst/rx_sd_wrapper_inst/rx_link_data_align_20bit_sd/align_data_d1_13_s0/CLK |
| 0.682 | 0.344 | tC2Q | RR | 5 | sdi_decoder_wrapper_inst/rx_sd_wrapper_inst/rx_link_data_align_20bit_sd/align_data_d1_13_s0/Q |
| 1.019 | 0.337 | tNET | RR | 1 | sdi_decoder_wrapper_inst/rx_sd_wrapper_inst/rx_sd_allign_patch_inst/datas1_d1_3_s10/I0 |
| 1.493 | 0.474 | tINS | RR | 1 | sdi_decoder_wrapper_inst/rx_sd_wrapper_inst/rx_sd_allign_patch_inst/datas1_d1_3_s10/F |
| 1.830 | 0.337 | tNET | RR | 1 | sdi_decoder_wrapper_inst/rx_sd_wrapper_inst/rx_sd_allign_patch_inst/allign_patch_datas2_3_s/I2 |
| 2.245 | 0.415 | tINS | RR | 4 | sdi_decoder_wrapper_inst/rx_sd_wrapper_inst/rx_sd_allign_patch_inst/allign_patch_datas2_3_s/F |
| 2.583 | 0.337 | tNET | RR | 1 | sdi_decoder_wrapper_inst/rx_sd_wrapper_inst/rx_sd_fvhd_gen_inst/H_flag_s4/I0 |
| 3.057 | 0.474 | tINS | RR | 1 | sdi_decoder_wrapper_inst/rx_sd_wrapper_inst/rx_sd_fvhd_gen_inst/H_flag_s4/F |
| 3.394 | 0.337 | tNET | RR | 1 | sdi_decoder_wrapper_inst/rx_sd_wrapper_inst/rx_sd_fvhd_gen_inst/H_flag_s3/I0 |
| 3.868 | 0.474 | tINS | RR | 4 | sdi_decoder_wrapper_inst/rx_sd_wrapper_inst/rx_sd_fvhd_gen_inst/H_flag_s3/F |
| 4.205 | 0.337 | tNET | RR | 1 | sdi_decoder_wrapper_inst/rx_sd_wrapper_inst/rx_sd_fvhd_gen_inst/sav_s0/I1 |
| 4.670 | 0.465 | tINS | RR | 1 | sdi_decoder_wrapper_inst/rx_sd_wrapper_inst/rx_sd_fvhd_gen_inst/sav_s0/F |
| 5.007 | 0.337 | tNET | RR | 1 | sdi_decoder_wrapper_inst/rx_sd_wrapper_inst/rx_sd_fvhd_gen_inst/de_flag_s1/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | |||
| 10.000 | 0.000 | I_clk | |||
| 10.000 | 0.000 | tCL | RR | 1 | I_clk_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 2941 | I_clk_ibuf/O |
| 10.337 | 0.337 | tNET | RR | 1 | sdi_decoder_wrapper_inst/rx_sd_wrapper_inst/rx_sd_fvhd_gen_inst/de_flag_s1/CLK |
| 10.280 | -0.057 | tSu | 1 | sdi_decoder_wrapper_inst/rx_sd_wrapper_inst/rx_sd_fvhd_gen_inst/de_flag_s1 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 6 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.337, 100.000% |
| Arrival Data Path Delay: | cell: 2.301, 49.265%; route: 2.025, 43.363%; tC2Q: 0.344, 7.372% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.337, 100.000% |
Path 5
Path Summary:| Slack | 5.273 |
| Data Arrival Time | 5.007 |
| Data Required Time | 10.280 |
| From | sdi_decoder_wrapper_inst/rx_sd_wrapper_inst/rx_link_data_align_20bit_sd/align_data_d1_13_s0 |
| To | sdi_decoder_wrapper_inst/rx_sd_wrapper_inst/rx_sd_fvhd_gen_inst/H_flag_s1 |
| Launch Clk | I_clk[R] |
| Latch Clk | I_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | |||
| 0.000 | 0.000 | I_clk | |||
| 0.000 | 0.000 | tCL | RR | 1 | I_clk_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 2941 | I_clk_ibuf/O |
| 0.337 | 0.337 | tNET | RR | 1 | sdi_decoder_wrapper_inst/rx_sd_wrapper_inst/rx_link_data_align_20bit_sd/align_data_d1_13_s0/CLK |
| 0.682 | 0.344 | tC2Q | RR | 5 | sdi_decoder_wrapper_inst/rx_sd_wrapper_inst/rx_link_data_align_20bit_sd/align_data_d1_13_s0/Q |
| 1.019 | 0.337 | tNET | RR | 1 | sdi_decoder_wrapper_inst/rx_sd_wrapper_inst/rx_sd_allign_patch_inst/datas1_d1_3_s10/I0 |
| 1.493 | 0.474 | tINS | RR | 1 | sdi_decoder_wrapper_inst/rx_sd_wrapper_inst/rx_sd_allign_patch_inst/datas1_d1_3_s10/F |
| 1.830 | 0.337 | tNET | RR | 1 | sdi_decoder_wrapper_inst/rx_sd_wrapper_inst/rx_sd_allign_patch_inst/allign_patch_datas2_3_s/I2 |
| 2.245 | 0.415 | tINS | RR | 4 | sdi_decoder_wrapper_inst/rx_sd_wrapper_inst/rx_sd_allign_patch_inst/allign_patch_datas2_3_s/F |
| 2.583 | 0.337 | tNET | RR | 1 | sdi_decoder_wrapper_inst/rx_sd_wrapper_inst/rx_sd_fvhd_gen_inst/H_flag_s4/I0 |
| 3.057 | 0.474 | tINS | RR | 1 | sdi_decoder_wrapper_inst/rx_sd_wrapper_inst/rx_sd_fvhd_gen_inst/H_flag_s4/F |
| 3.394 | 0.337 | tNET | RR | 1 | sdi_decoder_wrapper_inst/rx_sd_wrapper_inst/rx_sd_fvhd_gen_inst/H_flag_s3/I0 |
| 3.868 | 0.474 | tINS | RR | 4 | sdi_decoder_wrapper_inst/rx_sd_wrapper_inst/rx_sd_fvhd_gen_inst/H_flag_s3/F |
| 4.205 | 0.337 | tNET | RR | 1 | sdi_decoder_wrapper_inst/rx_sd_wrapper_inst/rx_sd_fvhd_gen_inst/eav_s0/I1 |
| 4.670 | 0.465 | tINS | RR | 4 | sdi_decoder_wrapper_inst/rx_sd_wrapper_inst/rx_sd_fvhd_gen_inst/eav_s0/F |
| 5.007 | 0.337 | tNET | RR | 1 | sdi_decoder_wrapper_inst/rx_sd_wrapper_inst/rx_sd_fvhd_gen_inst/H_flag_s1/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | |||
| 10.000 | 0.000 | I_clk | |||
| 10.000 | 0.000 | tCL | RR | 1 | I_clk_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 2941 | I_clk_ibuf/O |
| 10.337 | 0.337 | tNET | RR | 1 | sdi_decoder_wrapper_inst/rx_sd_wrapper_inst/rx_sd_fvhd_gen_inst/H_flag_s1/CLK |
| 10.280 | -0.057 | tSu | 1 | sdi_decoder_wrapper_inst/rx_sd_wrapper_inst/rx_sd_fvhd_gen_inst/H_flag_s1 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 6 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.337, 100.000% |
| Arrival Data Path Delay: | cell: 2.301, 49.265%; route: 2.025, 43.363%; tC2Q: 0.344, 7.372% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.337, 100.000% |