Synthesis Messages
| Report Title | GowinSynthesis Report |
| Design File | E:\Gowin_Board_5at_SDI\DK_START_GW5AT-LV60PG484A_V1.1\Q_V1.1_new\Gowin_SDI_RefDesign_2600202_60k484_v1.1_sdi1_l2_cpll_ref\project\src\adv7513_iic_init.v E:\Gowin_Board_5at_SDI\DK_START_GW5AT-LV60PG484A_V1.1\Q_V1.1_new\Gowin_SDI_RefDesign_2600202_60k484_v1.1_sdi1_l2_cpll_ref\project\src\adv7513_rst.v E:\Gowin_Board_5at_SDI\DK_START_GW5AT-LV60PG484A_V1.1\Q_V1.1_new\Gowin_SDI_RefDesign_2600202_60k484_v1.1_sdi1_l2_cpll_ref\project\src\drp_ctrl.v E:\Gowin_Board_5at_SDI\DK_START_GW5AT-LV60PG484A_V1.1\Q_V1.1_new\Gowin_SDI_RefDesign_2600202_60k484_v1.1_sdi1_l2_cpll_ref\project\src\drp_sel.v E:\Gowin_Board_5at_SDI\DK_START_GW5AT-LV60PG484A_V1.1\Q_V1.1_new\Gowin_SDI_RefDesign_2600202_60k484_v1.1_sdi1_l2_cpll_ref\project\src\encoder_rate_polling_change.v E:\Gowin_Board_5at_SDI\DK_START_GW5AT-LV60PG484A_V1.1\Q_V1.1_new\Gowin_SDI_RefDesign_2600202_60k484_v1.1_sdi1_l2_cpll_ref\project\src\gowin_osc\gowin_osc.v E:\Gowin_Board_5at_SDI\DK_START_GW5AT-LV60PG484A_V1.1\Q_V1.1_new\Gowin_SDI_RefDesign_2600202_60k484_v1.1_sdi1_l2_cpll_ref\project\src\gowin_pll\adv7513_pll.v E:\Gowin_Board_5at_SDI\DK_START_GW5AT-LV60PG484A_V1.1\Q_V1.1_new\Gowin_SDI_RefDesign_2600202_60k484_v1.1_sdi1_l2_cpll_ref\project\src\gowin_pll\adv7513_pll_mod.v E:\Gowin_Board_5at_SDI\DK_START_GW5AT-LV60PG484A_V1.1\Q_V1.1_new\Gowin_SDI_RefDesign_2600202_60k484_v1.1_sdi1_l2_cpll_ref\project\src\gowin_pll\sys_pll.v E:\Gowin_Board_5at_SDI\DK_START_GW5AT-LV60PG484A_V1.1\Q_V1.1_new\Gowin_SDI_RefDesign_2600202_60k484_v1.1_sdi1_l2_cpll_ref\project\src\gowin_pll\sys_pll_mod.v E:\Gowin_Board_5at_SDI\DK_START_GW5AT-LV60PG484A_V1.1\Q_V1.1_new\Gowin_SDI_RefDesign_2600202_60k484_v1.1_sdi1_l2_cpll_ref\project\src\hvtol_cal_i.v E:\Gowin_Board_5at_SDI\DK_START_GW5AT-LV60PG484A_V1.1\Q_V1.1_new\Gowin_SDI_RefDesign_2600202_60k484_v1.1_sdi1_l2_cpll_ref\project\src\i2c_master\i2c_master.v E:\Gowin_Board_5at_SDI\DK_START_GW5AT-LV60PG484A_V1.1\Q_V1.1_new\Gowin_SDI_RefDesign_2600202_60k484_v1.1_sdi1_l2_cpll_ref\project\src\i2s_interface\i2s_clkdiv4\i2s_clkdiv4.v E:\Gowin_Board_5at_SDI\DK_START_GW5AT-LV60PG484A_V1.1\Q_V1.1_new\Gowin_SDI_RefDesign_2600202_60k484_v1.1_sdi1_l2_cpll_ref\project\src\i2s_interface\i2s_output_pcm5102.v E:\Gowin_Board_5at_SDI\DK_START_GW5AT-LV60PG484A_V1.1\Q_V1.1_new\Gowin_SDI_RefDesign_2600202_60k484_v1.1_sdi1_l2_cpll_ref\project\src\i2s_interface\i2s_sample_pcm2706.v E:\Gowin_Board_5at_SDI\DK_START_GW5AT-LV60PG484A_V1.1\Q_V1.1_new\Gowin_SDI_RefDesign_2600202_60k484_v1.1_sdi1_l2_cpll_ref\project\src\interlaced_gen.v E:\Gowin_Board_5at_SDI\DK_START_GW5AT-LV60PG484A_V1.1\Q_V1.1_new\Gowin_SDI_RefDesign_2600202_60k484_v1.1_sdi1_l2_cpll_ref\project\src\key_debounceN.v E:\Gowin_Board_5at_SDI\DK_START_GW5AT-LV60PG484A_V1.1\Q_V1.1_new\Gowin_SDI_RefDesign_2600202_60k484_v1.1_sdi1_l2_cpll_ref\project\src\pll_init.v E:\Gowin_Board_5at_SDI\DK_START_GW5AT-LV60PG484A_V1.1\Q_V1.1_new\Gowin_SDI_RefDesign_2600202_60k484_v1.1_sdi1_l2_cpll_ref\project\src\rgb_to_yc\rgb_yc422.v E:\Gowin_Board_5at_SDI\DK_START_GW5AT-LV60PG484A_V1.1\Q_V1.1_new\Gowin_SDI_RefDesign_2600202_60k484_v1.1_sdi1_l2_cpll_ref\project\src\sdi_audio_buffer_pro\sdi_audio_buffer_fifo\sdi_audio_buffer_fifo.v E:\Gowin_Board_5at_SDI\DK_START_GW5AT-LV60PG484A_V1.1\Q_V1.1_new\Gowin_SDI_RefDesign_2600202_60k484_v1.1_sdi1_l2_cpll_ref\project\src\sdi_audio_buffer_pro\sdi_audio_buffer_pro.v E:\Gowin_Board_5at_SDI\DK_START_GW5AT-LV60PG484A_V1.1\Q_V1.1_new\Gowin_SDI_RefDesign_2600202_60k484_v1.1_sdi1_l2_cpll_ref\project\src\sdi_decoder\sdi_decoder.v E:\Gowin_Board_5at_SDI\DK_START_GW5AT-LV60PG484A_V1.1\Q_V1.1_new\Gowin_SDI_RefDesign_2600202_60k484_v1.1_sdi1_l2_cpll_ref\project\src\sdi_encoder\sdi_encoder.v E:\Gowin_Board_5at_SDI\DK_START_GW5AT-LV60PG484A_V1.1\Q_V1.1_new\Gowin_SDI_RefDesign_2600202_60k484_v1.1_sdi1_l2_cpll_ref\project\src\serdes\customized_phy\customized_phy.v E:\Gowin_Board_5at_SDI\DK_START_GW5AT-LV60PG484A_V1.1\Q_V1.1_new\Gowin_SDI_RefDesign_2600202_60k484_v1.1_sdi1_l2_cpll_ref\project\src\serdes\serdes.v E:\Gowin_Board_5at_SDI\DK_START_GW5AT-LV60PG484A_V1.1\Q_V1.1_new\Gowin_SDI_RefDesign_2600202_60k484_v1.1_sdi1_l2_cpll_ref\project\src\serdes\upar_arbiter\upar_arbiter.v E:\Gowin_Board_5at_SDI\DK_START_GW5AT-LV60PG484A_V1.1\Q_V1.1_new\Gowin_SDI_RefDesign_2600202_60k484_v1.1_sdi1_l2_cpll_ref\project\src\testpattern.v E:\Gowin_Board_5at_SDI\DK_START_GW5AT-LV60PG484A_V1.1\Q_V1.1_new\Gowin_SDI_RefDesign_2600202_60k484_v1.1_sdi1_l2_cpll_ref\project\src\video_top.v E:\Gowin_Board_5at_SDI\DK_START_GW5AT-LV60PG484A_V1.1\Q_V1.1_new\Gowin_SDI_RefDesign_2600202_60k484_v1.1_sdi1_l2_cpll_ref\project\src\yc_to_rgb\yc422_rgb.v |
| GowinSynthesis Constraints File | --- |
| Tool Version | V1.9.12.02 (64-bit) |
| Part Number | GW5AT-LV60PG484AES |
| Device | GW5AT-60 |
| Device Version | B |
| Created Time | Wed Mar 25 10:18:33 2026 |
| Legal Announcement | Copyright (C)2014-2026 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
| Top Level Module | video_top |
| Synthesis Process | Running parser: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 394.336MB Running netlist conversion: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 394.336MB Optimizing Phase 1: CPU time = 0h 0m 0.578s, Elapsed time = 0h 0m 0.579s, Peak memory usage = 394.336MB Optimizing Phase 2: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 394.336MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0.468s, Elapsed time = 0h 0m 0.47s, Peak memory usage = 394.336MB Inferring Phase 1: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.06s, Peak memory usage = 394.336MB Inferring Phase 2: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.072s, Peak memory usage = 394.336MB Inferring Phase 3: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.068s, Peak memory usage = 394.336MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 394.336MB Tech-Mapping Phase 1: CPU time = 0h 0m 0.234s, Elapsed time = 0h 0m 0.236s, Peak memory usage = 394.336MB Tech-Mapping Phase 2: CPU time = 0h 0m 0.093s, Elapsed time = 0h 0m 0.096s, Peak memory usage = 394.336MB Tech-Mapping Phase 3: CPU time = 0h 0m 5s, Elapsed time = 0h 0m 5s, Peak memory usage = 395.508MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.625s, Elapsed time = 0h 0m 0.728s, Peak memory usage = 395.859MB Generate output files: CPU time = 0h 0m 0.5s, Elapsed time = 0h 0m 0.595s, Peak memory usage = 419.809MB |
| Total Time and Memory Usage | CPU time = 0h 0m 11s, Elapsed time = 0h 0m 11s, Peak memory usage = 419.809MB |
Resource
Resource Usage Summary
| Resource | Usage |
| I/O Port | 46 |
| I/O Buf | 42 |
| IBUF | 2 |
| OBUF | 37 |
| IOBUF | 2 |
| TLVDS_IBUF | 1 |
| Register | 8220 |
| DFFSE | 2 |
| DFFRE | 361 |
| DFFPE | 61 |
| DFFCE | 7796 |
| LUT | 7811 |
| LUT2 | 1045 |
| LUT3 | 2688 |
| LUT4 | 4078 |
| MUX | 144 |
| MUX2 | 144 |
| ALU | 686 |
| ALU | 686 |
| ROM16 | 120 |
| ROM16 | 120 |
| INV | 45 |
| INV | 45 |
| IOLOGIC | 3 |
| ODDR | 3 |
| BSRAM | 35 |
| SDPB | 11 |
| SDPX9B | 24 |
| CLOCK | 4 |
| CLKDIV | 1 |
| PLLA | 2 |
| OSCA | 1 |
| GTR12_QUADA | 1 |
| GTR12_UPARA | 1 |
Resource Utilization Summary
| Resource | Usage | Utilization |
| Logic | 8806(8000 LUT, 686 ALU, 120 ROM16) / 59904 | 15% |
| Register | 8220 / 60780 | 14% |
| --Register as Latch | 0 / 60780 | 0% |
| --Register as FF | 8220 / 60780 | 14% |
| BSRAM | 35 / 118 | 30% |
Timing
Clock Summary:
| NO. | Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
|---|---|---|---|---|---|---|---|---|---|
| 1 | Gowin_OSC_inst/osc_inst/OSCOUT.default_clk | Base | 47.619 | 21.000 | 0.000 | 23.810 | Gowin_OSC_inst/osc_inst/OSCOUT | ||
| 2 | I_clk_p | Base | 5.000 | 200.000 | 0.000 | 2.500 | IB_clk_inst/I | ||
| 3 | sdi_audio_buffer_pro_tx_inst/sdi_audio_buffer_fifo_inst/fifo_inst/n4_6_3 | Base | 10.000 | 100.000 | 0.000 | 5.000 | sdi_audio_buffer_pro_tx_inst/sdi_audio_buffer_fifo_inst/fifo_inst/n4_6_s0/F | ||
| 4 | sdi_audio_buffer_pro_tx_inst/sdi_audio_buffer_fifo_inst/fifo_inst/n9_6_3 | Base | 10.000 | 100.000 | 0.000 | 5.000 | sdi_audio_buffer_pro_tx_inst/sdi_audio_buffer_fifo_inst/fifo_inst/n9_6_s0/F | ||
| 5 | i2s_clkdiv4_inst0/clkdiv_inst/CLKOUT.default_gen_clk | Generated | 40.000 | 25.000 | 0.000 | 20.000 | DEFAULT_CLK | i2s_clkdiv4_inst0/clkdiv_inst/CLKOUT | |
| 6 | sys_pll_inst/u_pll/PLLA_inst/CLKOUT0.default_gen_clk | Generated | 20.000 | 50.000 | 0.000 | 10.000 | IB_clk_inst/I | I_clk_p | sys_pll_inst/u_pll/PLLA_inst/CLKOUT0 |
Max Frequency Summary:
| NO. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
|---|---|---|---|---|---|
| 1 | Gowin_OSC_inst/osc_inst/OSCOUT.default_clk | 21.000(MHz) | 182.486(MHz) | 7 | TOP |
| 2 | sdi_audio_buffer_pro_tx_inst/sdi_audio_buffer_fifo_inst/fifo_inst/n4_6_3 | 100.000(MHz) | 1352.951(MHz) | 1 | TOP |
| 3 | sdi_audio_buffer_pro_tx_inst/sdi_audio_buffer_fifo_inst/fifo_inst/n9_6_3 | 100.000(MHz) | 1352.951(MHz) | 1 | TOP |
| 4 | i2s_clkdiv4_inst0/clkdiv_inst/CLKOUT.default_gen_clk | 25.000(MHz) | 202.112(MHz) | 7 | TOP |
| 5 | sys_pll_inst/u_pll/PLLA_inst/CLKOUT0.default_gen_clk | 50.000(MHz) | 180.558(MHz) | 7 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:| Slack | 9.261 |
| Data Arrival Time | 1.019 |
| Data Required Time | 10.280 |
| From | sdi_audio_buffer_pro_rx_inst/sdi_audio_buffer_fifo_inst/fifo_inst/reset_w_0_s0 |
| To | sdi_audio_buffer_pro_rx_inst/sdi_audio_buffer_fifo_inst/fifo_inst/reset_w_1_s0 |
| Launch Clk | sdi_audio_buffer_pro_tx_inst/sdi_audio_buffer_fifo_inst/fifo_inst/n9_6_3[R] |
| Latch Clk | sdi_audio_buffer_pro_tx_inst/sdi_audio_buffer_fifo_inst/fifo_inst/n9_6_3[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | |||
| 0.000 | 0.000 | sdi_audio_buffer_pro_tx_inst/sdi_audio_buffer_fifo_inst/fifo_inst/n9_6_3 | |||
| 0.000 | 0.000 | tCL | RR | 4 | sdi_audio_buffer_pro_tx_inst/sdi_audio_buffer_fifo_inst/fifo_inst/n9_6_s0/F |
| 0.337 | 0.337 | tNET | RR | 1 | sdi_audio_buffer_pro_rx_inst/sdi_audio_buffer_fifo_inst/fifo_inst/reset_w_0_s0/CLK |
| 0.682 | 0.344 | tC2Q | RR | 1 | sdi_audio_buffer_pro_rx_inst/sdi_audio_buffer_fifo_inst/fifo_inst/reset_w_0_s0/Q |
| 1.019 | 0.337 | tNET | RR | 1 | sdi_audio_buffer_pro_rx_inst/sdi_audio_buffer_fifo_inst/fifo_inst/reset_w_1_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | |||
| 10.000 | 0.000 | sdi_audio_buffer_pro_tx_inst/sdi_audio_buffer_fifo_inst/fifo_inst/n9_6_3 | |||
| 10.000 | 0.000 | tCL | RR | 4 | sdi_audio_buffer_pro_tx_inst/sdi_audio_buffer_fifo_inst/fifo_inst/n9_6_s0/F |
| 10.337 | 0.337 | tNET | RR | 1 | sdi_audio_buffer_pro_rx_inst/sdi_audio_buffer_fifo_inst/fifo_inst/reset_w_1_s0/CLK |
| 10.280 | -0.057 | tSu | 1 | sdi_audio_buffer_pro_rx_inst/sdi_audio_buffer_fifo_inst/fifo_inst/reset_w_1_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 1 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.337, 100.000% |
| Arrival Data Path Delay: | cell: 0.000, 0.000%; route: 0.337, 49.505%; tC2Q: 0.344, 50.495% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.337, 100.000% |
Path 2
Path Summary:| Slack | 9.261 |
| Data Arrival Time | 1.019 |
| Data Required Time | 10.280 |
| From | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_audio_data_wrapper_inst/tx_audio_data_store_inst/tx_hd_audio_fifo_data/reset_r_0_s0 |
| To | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_audio_data_wrapper_inst/tx_audio_data_store_inst/tx_hd_audio_fifo_data/reset_w_1_s0 |
| Launch Clk | sdi_audio_buffer_pro_tx_inst/sdi_audio_buffer_fifo_inst/fifo_inst/n4_6_3[R] |
| Latch Clk | sdi_audio_buffer_pro_tx_inst/sdi_audio_buffer_fifo_inst/fifo_inst/n4_6_3[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | |||
| 0.000 | 0.000 | sdi_audio_buffer_pro_tx_inst/sdi_audio_buffer_fifo_inst/fifo_inst/n4_6_3 | |||
| 0.000 | 0.000 | tCL | RR | 4 | sdi_audio_buffer_pro_tx_inst/sdi_audio_buffer_fifo_inst/fifo_inst/n4_6_s0/F |
| 0.337 | 0.337 | tNET | RR | 1 | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_audio_data_wrapper_inst/tx_audio_data_store_inst/tx_hd_audio_fifo_data/reset_r_0_s0/CLK |
| 0.682 | 0.344 | tC2Q | RR | 1 | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_audio_data_wrapper_inst/tx_audio_data_store_inst/tx_hd_audio_fifo_data/reset_r_0_s0/Q |
| 1.019 | 0.337 | tNET | RR | 1 | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_audio_data_wrapper_inst/tx_audio_data_store_inst/tx_hd_audio_fifo_data/reset_w_1_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | |||
| 10.000 | 0.000 | sdi_audio_buffer_pro_tx_inst/sdi_audio_buffer_fifo_inst/fifo_inst/n4_6_3 | |||
| 10.000 | 0.000 | tCL | RR | 4 | sdi_audio_buffer_pro_tx_inst/sdi_audio_buffer_fifo_inst/fifo_inst/n4_6_s0/F |
| 10.337 | 0.337 | tNET | RR | 1 | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_audio_data_wrapper_inst/tx_audio_data_store_inst/tx_hd_audio_fifo_data/reset_w_1_s0/CLK |
| 10.280 | -0.057 | tSu | 1 | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_audio_data_wrapper_inst/tx_audio_data_store_inst/tx_hd_audio_fifo_data/reset_w_1_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 1 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.337, 100.000% |
| Arrival Data Path Delay: | cell: 0.000, 0.000%; route: 0.337, 49.505%; tC2Q: 0.344, 50.495% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.337, 100.000% |
Path 3
Path Summary:| Slack | 9.261 |
| Data Arrival Time | 1.019 |
| Data Required Time | 10.280 |
| From | sdi_audio_buffer_pro_tx_inst/sdi_audio_buffer_fifo_inst/fifo_inst/reset_r_0_s0 |
| To | sdi_audio_buffer_pro_tx_inst/sdi_audio_buffer_fifo_inst/fifo_inst/reset_r_1_s0 |
| Launch Clk | sdi_audio_buffer_pro_tx_inst/sdi_audio_buffer_fifo_inst/fifo_inst/n4_6_3[R] |
| Latch Clk | sdi_audio_buffer_pro_tx_inst/sdi_audio_buffer_fifo_inst/fifo_inst/n4_6_3[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | |||
| 0.000 | 0.000 | sdi_audio_buffer_pro_tx_inst/sdi_audio_buffer_fifo_inst/fifo_inst/n4_6_3 | |||
| 0.000 | 0.000 | tCL | RR | 4 | sdi_audio_buffer_pro_tx_inst/sdi_audio_buffer_fifo_inst/fifo_inst/n4_6_s0/F |
| 0.337 | 0.337 | tNET | RR | 1 | sdi_audio_buffer_pro_tx_inst/sdi_audio_buffer_fifo_inst/fifo_inst/reset_r_0_s0/CLK |
| 0.682 | 0.344 | tC2Q | RR | 1 | sdi_audio_buffer_pro_tx_inst/sdi_audio_buffer_fifo_inst/fifo_inst/reset_r_0_s0/Q |
| 1.019 | 0.337 | tNET | RR | 1 | sdi_audio_buffer_pro_tx_inst/sdi_audio_buffer_fifo_inst/fifo_inst/reset_r_1_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | |||
| 10.000 | 0.000 | sdi_audio_buffer_pro_tx_inst/sdi_audio_buffer_fifo_inst/fifo_inst/n4_6_3 | |||
| 10.000 | 0.000 | tCL | RR | 4 | sdi_audio_buffer_pro_tx_inst/sdi_audio_buffer_fifo_inst/fifo_inst/n4_6_s0/F |
| 10.337 | 0.337 | tNET | RR | 1 | sdi_audio_buffer_pro_tx_inst/sdi_audio_buffer_fifo_inst/fifo_inst/reset_r_1_s0/CLK |
| 10.280 | -0.057 | tSu | 1 | sdi_audio_buffer_pro_tx_inst/sdi_audio_buffer_fifo_inst/fifo_inst/reset_r_1_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 1 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.337, 100.000% |
| Arrival Data Path Delay: | cell: 0.000, 0.000%; route: 0.337, 49.505%; tC2Q: 0.344, 50.495% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.337, 100.000% |
Path 4
Path Summary:| Slack | 9.261 |
| Data Arrival Time | 1.019 |
| Data Required Time | 10.280 |
| From | sdi_audio_buffer_pro_tx_inst/sdi_audio_buffer_fifo_inst/fifo_inst/reset_w_0_s0 |
| To | sdi_audio_buffer_pro_tx_inst/sdi_audio_buffer_fifo_inst/fifo_inst/reset_w_1_s0 |
| Launch Clk | sdi_audio_buffer_pro_tx_inst/sdi_audio_buffer_fifo_inst/fifo_inst/n9_6_3[R] |
| Latch Clk | sdi_audio_buffer_pro_tx_inst/sdi_audio_buffer_fifo_inst/fifo_inst/n9_6_3[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | |||
| 0.000 | 0.000 | sdi_audio_buffer_pro_tx_inst/sdi_audio_buffer_fifo_inst/fifo_inst/n9_6_3 | |||
| 0.000 | 0.000 | tCL | RR | 4 | sdi_audio_buffer_pro_tx_inst/sdi_audio_buffer_fifo_inst/fifo_inst/n9_6_s0/F |
| 0.337 | 0.337 | tNET | RR | 1 | sdi_audio_buffer_pro_tx_inst/sdi_audio_buffer_fifo_inst/fifo_inst/reset_w_0_s0/CLK |
| 0.682 | 0.344 | tC2Q | RR | 1 | sdi_audio_buffer_pro_tx_inst/sdi_audio_buffer_fifo_inst/fifo_inst/reset_w_0_s0/Q |
| 1.019 | 0.337 | tNET | RR | 1 | sdi_audio_buffer_pro_tx_inst/sdi_audio_buffer_fifo_inst/fifo_inst/reset_w_1_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | |||
| 10.000 | 0.000 | sdi_audio_buffer_pro_tx_inst/sdi_audio_buffer_fifo_inst/fifo_inst/n9_6_3 | |||
| 10.000 | 0.000 | tCL | RR | 4 | sdi_audio_buffer_pro_tx_inst/sdi_audio_buffer_fifo_inst/fifo_inst/n9_6_s0/F |
| 10.337 | 0.337 | tNET | RR | 1 | sdi_audio_buffer_pro_tx_inst/sdi_audio_buffer_fifo_inst/fifo_inst/reset_w_1_s0/CLK |
| 10.280 | -0.057 | tSu | 1 | sdi_audio_buffer_pro_tx_inst/sdi_audio_buffer_fifo_inst/fifo_inst/reset_w_1_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 1 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.337, 100.000% |
| Arrival Data Path Delay: | cell: 0.000, 0.000%; route: 0.337, 49.505%; tC2Q: 0.344, 50.495% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.337, 100.000% |
Path 5
Path Summary:| Slack | 14.462 |
| Data Arrival Time | 6.156 |
| Data Required Time | 20.618 |
| From | sys_5s_cnt_8_s0 |
| To | sys_5s_cnt_1_s0 |
| Launch Clk | sys_pll_inst/u_pll/PLLA_inst/CLKOUT0.default_gen_clk[R] |
| Latch Clk | sys_pll_inst/u_pll/PLLA_inst/CLKOUT0.default_gen_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | |||
| 0.000 | 0.000 | sys_pll_inst/u_pll/PLLA_inst/CLKOUT0.default_gen_clk | |||
| 0.337 | 0.337 | tCL | RR | 240 | sys_pll_inst/u_pll/PLLA_inst/CLKOUT0 |
| 0.675 | 0.337 | tNET | RR | 1 | sys_5s_cnt_8_s0/CLK |
| 1.019 | 0.344 | tC2Q | RR | 6 | sys_5s_cnt_8_s0/Q |
| 1.357 | 0.337 | tNET | RR | 1 | n257_s9/I0 |
| 1.830 | 0.474 | tINS | RR | 1 | n257_s9/F |
| 2.168 | 0.337 | tNET | RR | 1 | n257_s8/I2 |
| 2.583 | 0.415 | tINS | RR | 1 | n257_s8/F |
| 2.920 | 0.337 | tNET | RR | 1 | n257_s7/I1 |
| 3.385 | 0.465 | tINS | RR | 1 | n257_s7/F |
| 3.723 | 0.337 | tNET | RR | 1 | n257_s4/I0 |
| 4.196 | 0.474 | tINS | RR | 1 | n257_s4/F |
| 4.534 | 0.337 | tNET | RR | 1 | n257_s2/I0 |
| 5.007 | 0.474 | tINS | RR | 28 | n257_s2/F |
| 5.345 | 0.337 | tNET | RR | 1 | n256_s2/I0 |
| 5.819 | 0.474 | tINS | RR | 1 | n256_s2/F |
| 6.156 | 0.337 | tNET | RR | 1 | sys_5s_cnt_1_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 20.000 | 20.000 | active clock edge time | |||
| 20.000 | 0.000 | sys_pll_inst/u_pll/PLLA_inst/CLKOUT0.default_gen_clk | |||
| 20.337 | 0.337 | tCL | RR | 240 | sys_pll_inst/u_pll/PLLA_inst/CLKOUT0 |
| 20.675 | 0.337 | tNET | RR | 1 | sys_5s_cnt_1_s0/CLK |
| 20.618 | -0.057 | tSu | 1 | sys_5s_cnt_1_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 20.000 |
| Logic Level: | 7 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.337, 100.000% |
| Arrival Data Path Delay: | cell: 2.774, 50.616%; route: 2.362, 43.103%; tC2Q: 0.344, 6.281% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.337, 100.000% |