Synthesis Messages

Report Title GowinSynthesis Report
Design File D:\Gowin\Gowin_V1.9.12_x64\IDE\ipcore\SERDES_IP\IPlib\PCIE\data\pcie_controller_encrypt.v
D:\Gowin\Gowin_V1.9.12_x64\IDE\ipcore\SERDES_IP\IPlib\PCIE\data\pcie_controller_top.v
GowinSynthesis Constraints File ---
Tool Version V1.9.12 (64-bit)
Part Number GW5AT-LV60UG225C2/I1
Device GW5AT-60
Device Version B
Created Time Tue Oct 21 14:45:12 2025
Legal Announcement Copyright (C)2014-2025 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module PCIE_Controller_Top
Synthesis Process Running parser:
    CPU time = 0h 0m 0.171s, Elapsed time = 0h 0m 0.196s, Peak memory usage = 83.672MB
Running netlist conversion:
    CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.059s, Peak memory usage = 83.672MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.026s, Peak memory usage = 83.672MB
    Optimizing Phase 1: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.03s, Peak memory usage = 83.672MB
    Optimizing Phase 2: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.022s, Peak memory usage = 83.672MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.023s, Peak memory usage = 83.672MB
    Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 83.672MB
    Inferring Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.007s, Peak memory usage = 83.672MB
    Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 83.672MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.021s, Peak memory usage = 83.672MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.009s, Peak memory usage = 83.672MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 83.672MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.12s, Peak memory usage = 106.707MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.069s, Peak memory usage = 106.707MB
Generate output files:
    CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.055s, Peak memory usage = 106.707MB
Total Time and Memory Usage CPU time = 0h 0m 0.557s, Elapsed time = 0h 0m 0.643s, Peak memory usage = 106.707MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 2316
I/O Buf 2287
    IBUF 1443
    OBUF 844
Register 714
    DFFRE 684
    DFFPE 2
    DFFCE 28
LUT 23
    LUT2 9
    LUT3 2
    LUT4 12
ALU 14
    ALU 14
INV 3
    INV 3

Resource Utilization Summary

Resource Usage Utilization
Logic 40(26 LUT, 14 ALU) / 59904 <1%
Register 714 / 60228 2%
  --Register as Latch 0 / 60228 0%
  --Register as FF 714 / 60228 2%
BSRAM 0 / 118 0%

Timing

Clock Summary:

NO. Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
1 pcie_tl_clk_i Base 10.000 100.000 0.000 5.000 pcie_tl_clk_i_ibuf/I
2 pcie_half_clk_i Base 10.000 100.000 0.000 5.000 pcie_half_clk_i_ibuf/I

Max Frequency Summary:

NO. Clock Name Constraint Actual Fmax Logic Level Entity
1 pcie_tl_clk_i 100.000(MHz) 435.351(MHz) 3 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack 7.703
Data Arrival Time 2.348
Data Required Time 10.051
From u_pcie_controller/u_pcie_linkup/cnt_1_s1
To u_pcie_controller/u_pcie_linkup/cnt_7_s1
Launch Clk pcie_tl_clk_i[R]
Latch Clk pcie_tl_clk_i[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 pcie_tl_clk_i
0.000 0.000 tCL RR 1 pcie_tl_clk_i_ibuf/I
0.000 0.000 tINS RR 49 pcie_tl_clk_i_ibuf/O
0.300 0.300 tNET RR 1 u_pcie_controller/u_pcie_linkup/cnt_1_s1/CLK
0.606 0.306 tC2Q RR 4 u_pcie_controller/u_pcie_linkup/cnt_1_s1/Q
0.906 0.300 tNET RR 1 u_pcie_controller/u_pcie_linkup/cnt_7_s4/I0
1.327 0.421 tINS RR 4 u_pcie_controller/u_pcie_linkup/cnt_7_s4/F
1.627 0.300 tNET RR 1 u_pcie_controller/u_pcie_linkup/cnt_7_s3/I0
2.048 0.421 tINS RR 1 u_pcie_controller/u_pcie_linkup/cnt_7_s3/F
2.348 0.300 tNET RR 1 u_pcie_controller/u_pcie_linkup/cnt_7_s1/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 pcie_tl_clk_i
10.000 0.000 tCL RR 1 pcie_tl_clk_i_ibuf/I
10.000 0.000 tINS RR 49 pcie_tl_clk_i_ibuf/O
10.300 0.300 tNET RR 1 u_pcie_controller/u_pcie_linkup/cnt_7_s1/CLK
10.051 -0.249 tSu 1 u_pcie_controller/u_pcie_linkup/cnt_7_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 3
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.300, 100.000%
Arrival Data Path Delay: cell: 0.842, 41.113%; route: 0.900, 43.946%; tC2Q: 0.306, 14.941%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.300, 100.000%

Path 2

Path Summary:
Slack 7.865
Data Arrival Time 2.137
Data Required Time 10.002
From u_pcie_controller/pl_test_out_rr_0_s0
To u_pcie_controller/pl_eq_rx_det_s0
Launch Clk pcie_tl_clk_i[R]
Latch Clk pcie_tl_clk_i[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 pcie_tl_clk_i
0.000 0.000 tCL RR 1 pcie_tl_clk_i_ibuf/I
0.000 0.000 tINS RR 49 pcie_tl_clk_i_ibuf/O
0.300 0.300 tNET RR 1 u_pcie_controller/pl_test_out_rr_0_s0/CLK
0.606 0.306 tC2Q RR 1 u_pcie_controller/pl_test_out_rr_0_s0/Q
0.906 0.300 tNET RR 1 u_pcie_controller/n200_s1/I0
1.327 0.421 tINS RR 3 u_pcie_controller/n200_s1/F
1.627 0.300 tNET RR 1 u_pcie_controller/pl_eq_rx_det_s3/I3
1.837 0.210 tINS RR 1 u_pcie_controller/pl_eq_rx_det_s3/F
2.137 0.300 tNET RR 1 u_pcie_controller/pl_eq_rx_det_s0/RESET
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 pcie_tl_clk_i
10.000 0.000 tCL RR 1 pcie_tl_clk_i_ibuf/I
10.000 0.000 tINS RR 49 pcie_tl_clk_i_ibuf/O
10.300 0.300 tNET RR 1 u_pcie_controller/pl_eq_rx_det_s0/CLK
10.002 -0.298 tSu 1 u_pcie_controller/pl_eq_rx_det_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 3
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.300, 100.000%
Arrival Data Path Delay: cell: 0.631, 34.349%; route: 0.900, 48.993%; tC2Q: 0.306, 16.658%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.300, 100.000%

Path 3

Path Summary:
Slack 7.901
Data Arrival Time 2.348
Data Required Time 10.249
From u_pcie_controller/u_pcie_linkup/cnt_1_s1
To u_pcie_controller/u_pcie_linkup/cnt_6_s1
Launch Clk pcie_tl_clk_i[R]
Latch Clk pcie_tl_clk_i[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 pcie_tl_clk_i
0.000 0.000 tCL RR 1 pcie_tl_clk_i_ibuf/I
0.000 0.000 tINS RR 49 pcie_tl_clk_i_ibuf/O
0.300 0.300 tNET RR 1 u_pcie_controller/u_pcie_linkup/cnt_1_s1/CLK
0.606 0.306 tC2Q RR 4 u_pcie_controller/u_pcie_linkup/cnt_1_s1/Q
0.906 0.300 tNET RR 1 u_pcie_controller/u_pcie_linkup/cnt_7_s4/I0
1.327 0.421 tINS RR 4 u_pcie_controller/u_pcie_linkup/cnt_7_s4/F
1.627 0.300 tNET RR 1 u_pcie_controller/u_pcie_linkup/n27_s2/I0
2.048 0.421 tINS RR 1 u_pcie_controller/u_pcie_linkup/n27_s2/F
2.348 0.300 tNET RR 1 u_pcie_controller/u_pcie_linkup/cnt_6_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 pcie_tl_clk_i
10.000 0.000 tCL RR 1 pcie_tl_clk_i_ibuf/I
10.000 0.000 tINS RR 49 pcie_tl_clk_i_ibuf/O
10.300 0.300 tNET RR 1 u_pcie_controller/u_pcie_linkup/cnt_6_s1/CLK
10.249 -0.051 tSu 1 u_pcie_controller/u_pcie_linkup/cnt_6_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 3
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.300, 100.000%
Arrival Data Path Delay: cell: 0.842, 41.113%; route: 0.900, 43.946%; tC2Q: 0.306, 14.941%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.300, 100.000%

Path 4

Path Summary:
Slack 7.909
Data Arrival Time 2.340
Data Required Time 10.249
From u_pcie_controller/u_pcie_linkup/cnt_1_s1
To u_pcie_controller/u_pcie_linkup/cnt_3_s1
Launch Clk pcie_tl_clk_i[R]
Latch Clk pcie_tl_clk_i[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 pcie_tl_clk_i
0.000 0.000 tCL RR 1 pcie_tl_clk_i_ibuf/I
0.000 0.000 tINS RR 49 pcie_tl_clk_i_ibuf/O
0.300 0.300 tNET RR 1 u_pcie_controller/u_pcie_linkup/cnt_1_s1/CLK
0.606 0.306 tC2Q RR 4 u_pcie_controller/u_pcie_linkup/cnt_1_s1/Q
0.906 0.300 tNET RR 1 u_pcie_controller/u_pcie_linkup/n31_s3/I0
1.327 0.421 tINS RR 1 u_pcie_controller/u_pcie_linkup/n31_s3/F
1.627 0.300 tNET RR 1 u_pcie_controller/u_pcie_linkup/n30_s2/I1
2.040 0.413 tINS RR 1 u_pcie_controller/u_pcie_linkup/n30_s2/F
2.340 0.300 tNET RR 1 u_pcie_controller/u_pcie_linkup/cnt_3_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 pcie_tl_clk_i
10.000 0.000 tCL RR 1 pcie_tl_clk_i_ibuf/I
10.000 0.000 tINS RR 49 pcie_tl_clk_i_ibuf/O
10.300 0.300 tNET RR 1 u_pcie_controller/u_pcie_linkup/cnt_3_s1/CLK
10.249 -0.051 tSu 1 u_pcie_controller/u_pcie_linkup/cnt_3_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 3
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.300, 100.000%
Arrival Data Path Delay: cell: 0.834, 40.882%; route: 0.900, 44.118%; tC2Q: 0.306, 15.000%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.300, 100.000%

Path 5

Path Summary:
Slack 7.909
Data Arrival Time 2.340
Data Required Time 10.249
From u_pcie_controller/u_pcie_linkup/cnt_1_s1
To u_pcie_controller/u_pcie_linkup/cnt_4_s1
Launch Clk pcie_tl_clk_i[R]
Latch Clk pcie_tl_clk_i[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 pcie_tl_clk_i
0.000 0.000 tCL RR 1 pcie_tl_clk_i_ibuf/I
0.000 0.000 tINS RR 49 pcie_tl_clk_i_ibuf/O
0.300 0.300 tNET RR 1 u_pcie_controller/u_pcie_linkup/cnt_1_s1/CLK
0.606 0.306 tC2Q RR 4 u_pcie_controller/u_pcie_linkup/cnt_1_s1/Q
0.906 0.300 tNET RR 1 u_pcie_controller/u_pcie_linkup/cnt_7_s4/I0
1.327 0.421 tINS RR 4 u_pcie_controller/u_pcie_linkup/cnt_7_s4/F
1.627 0.300 tNET RR 1 u_pcie_controller/u_pcie_linkup/n29_s3/I1
2.040 0.413 tINS RR 1 u_pcie_controller/u_pcie_linkup/n29_s3/F
2.340 0.300 tNET RR 1 u_pcie_controller/u_pcie_linkup/cnt_4_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 pcie_tl_clk_i
10.000 0.000 tCL RR 1 pcie_tl_clk_i_ibuf/I
10.000 0.000 tINS RR 49 pcie_tl_clk_i_ibuf/O
10.300 0.300 tNET RR 1 u_pcie_controller/u_pcie_linkup/cnt_4_s1/CLK
10.249 -0.051 tSu 1 u_pcie_controller/u_pcie_linkup/cnt_4_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 3
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.300, 100.000%
Arrival Data Path Delay: cell: 0.834, 40.882%; route: 0.900, 44.118%; tC2Q: 0.306, 15.000%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.300, 100.000%