Synthesis Messages

Report Title GowinSynthesis Report
Design File D:\Gowin\Gowin_V1.9.12.01_x64\IDE\ipcore\PCIe_SGDMA\data\pcie_sgdma.v
D:\Gowin\Gowin_V1.9.12.01_x64\IDE\ipcore\PCIe_SGDMA\data\pcie_sgdma_wrapper.v
GowinSynthesis Constraints File ---
Tool Version V1.9.12.01 (64-bit)
Part Number GW5AT-LV60UG225C2/I1
Device GW5AT-60
Device Version B
Created Time Wed Jan 7 14:56:21 2026
Legal Announcement Copyright (C)2014-2025 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module pcie_sgdma
Synthesis Process Running parser:
    CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 248.930MB
Running netlist conversion:
    CPU time = 0h 0m 0.5s, Elapsed time = 0h 0m 0.499s, Peak memory usage = 248.930MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 4s, Elapsed time = 0h 0m 4s, Peak memory usage = 248.930MB
    Optimizing Phase 1: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 248.930MB
    Optimizing Phase 2: CPU time = 0h 0m 4s, Elapsed time = 0h 0m 5s, Peak memory usage = 248.930MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s, Peak memory usage = 248.930MB
    Inferring Phase 1: CPU time = 0h 0m 0.89s, Elapsed time = 0h 0m 0.886s, Peak memory usage = 248.930MB
    Inferring Phase 2: CPU time = 0h 0m 0.218s, Elapsed time = 0h 0m 0.215s, Peak memory usage = 248.930MB
    Inferring Phase 3: CPU time = 0h 0m 0.093s, Elapsed time = 0h 0m 0.102s, Peak memory usage = 248.930MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s, Peak memory usage = 248.930MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0.89s, Elapsed time = 0h 0m 0.917s, Peak memory usage = 248.930MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 248.930MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 10s, Elapsed time = 0h 0m 10s, Peak memory usage = 248.930MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 248.930MB
Generate output files:
    CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 295.223MB
Total Time and Memory Usage CPU time = 0h 0m 29s, Elapsed time = 0h 0m 30s, Peak memory usage = 295.223MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 1597
I/O Buf 1545
    IBUF 708
    OBUF 837
Register 9710
    DFFRE 2
    DFFPE 36
    DFFCE 9672
LUT 7454
    LUT2 1013
    LUT3 1453
    LUT4 4988
ALU 586
    ALU 586
INV 12
    INV 12
BSRAM 32
    SDPB 27
    SDPX9B 5

Resource Utilization Summary

Resource Usage Utilization
Logic 8052(7466 LUT, 586 ALU) / 59904 14%
Register 9710 / 60228 17%
  --Register as Latch 0 / 60228 0%
  --Register as FF 9710 / 60228 17%
BSRAM 32 / 118 28%

Timing

Clock Summary:

NO. Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
1 clk Base 10.000 100.000 0.000 5.000 clk_ibuf/I
2 pcie_tl_drp_clk Base 10.000 100.000 0.000 5.000 pcie_tl_drp_clk_ibuf/I

Max Frequency Summary:

NO. Clock Name Constraint Actual Fmax Logic Level Entity
1 clk 100.000(MHz) 121.124(MHz) 13 TOP
2 pcie_tl_drp_clk 100.000(MHz) 445.434(MHz) 3 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack 1.744
Data Arrival Time 8.505
Data Required Time 10.249
From top/u_dma/u_c2h_all_engines/u_c2h_all_engines_tlp_tx_mux/c_state.S_TLP_TX_s2
To top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_data_fifo/empty_s0
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.000 0.000 tINS RR 9685 clk_ibuf/O
0.300 0.300 tNET RR 1 top/u_dma/u_c2h_all_engines/u_c2h_all_engines_tlp_tx_mux/c_state.S_TLP_TX_s2/CLK
0.606 0.306 tC2Q RR 272 top/u_dma/u_c2h_all_engines/u_c2h_all_engines_tlp_tx_mux/c_state.S_TLP_TX_s2/Q
0.906 0.300 tNET RR 1 top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_c2h_engine_tlp_tx_mux/n362_s3/I0
1.327 0.421 tINS RR 43 top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_c2h_engine_tlp_tx_mux/n362_s3/F
1.627 0.300 tNET RR 1 top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_c2h_data/tlp_tx_eop_int_s5/I0
2.048 0.421 tINS RR 13 top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_c2h_data/tlp_tx_eop_int_s5/F
2.348 0.300 tNET RR 1 top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_data_fifo/n16_s1/I0
2.769 0.421 tINS RR 5 top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_data_fifo/n16_s1/F
3.069 0.300 tNET RR 1 top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_data_fifo/n16_s2/I1
3.482 0.413 tINS RR 17 top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_data_fifo/n16_s2/F
3.782 0.300 tNET RR 2 top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_data_fifo/next_cnt_0_s/I1
4.232 0.450 tINS RF 1 top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_data_fifo/next_cnt_0_s/COUT
4.232 0.000 tNET FF 2 top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_data_fifo/next_cnt_1_s/CIN
4.272 0.040 tINS FR 1 top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_data_fifo/next_cnt_1_s/COUT
4.272 0.000 tNET RR 2 top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_data_fifo/next_cnt_2_s/CIN
4.312 0.040 tINS RR 1 top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_data_fifo/next_cnt_2_s/COUT
4.312 0.000 tNET RR 2 top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_data_fifo/next_cnt_3_s/CIN
4.352 0.040 tINS RR 1 top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_data_fifo/next_cnt_3_s/COUT
4.352 0.000 tNET RR 2 top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_data_fifo/next_cnt_4_s/CIN
4.547 0.195 tINS RR 6 top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_data_fifo/next_cnt_4_s/SUM
4.847 0.300 tNET RR 1 top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_data_fifo/next_cnt_5_s7/I1
5.260 0.413 tINS RR 1 top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_data_fifo/next_cnt_5_s7/F
5.560 0.300 tNET RR 1 top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_data_fifo/next_cnt_5_s6/I0
5.981 0.421 tINS RR 8 top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_data_fifo/next_cnt_5_s6/F
6.281 0.300 tNET RR 1 top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_data_fifo/next_cnt_6_s6/I1
6.694 0.413 tINS RR 3 top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_data_fifo/next_cnt_6_s6/F
6.994 0.300 tNET RR 2 top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_data_fifo/next_cnt_7_s4/I1
7.444 0.450 tINS RF 1 top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_data_fifo/next_cnt_7_s4/COUT
7.444 0.000 tNET FF 2 top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_data_fifo/next_cnt_8_s4/CIN
7.484 0.040 tINS FR 1 top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_data_fifo/next_cnt_8_s4/COUT
7.784 0.300 tNET RR 1 top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_data_fifo/n883_s1/I0
8.205 0.421 tINS RR 1 top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_data_fifo/n883_s1/F
8.505 0.300 tNET RR 1 top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_data_fifo/empty_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk
10.000 0.000 tCL RR 1 clk_ibuf/I
10.000 0.000 tINS RR 9685 clk_ibuf/O
10.300 0.300 tNET RR 1 top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_data_fifo/empty_s0/CLK
10.249 -0.051 tSu 1 top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_data_fifo/empty_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 13
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.300, 100.000%
Arrival Data Path Delay: cell: 4.599, 56.052%; route: 3.300, 40.219%; tC2Q: 0.306, 3.729%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.300, 100.000%

Path 2

Path Summary:
Slack 2.542
Data Arrival Time 7.707
Data Required Time 10.249
From top/u_dma/u_c2h_all_engines/u_c2h_all_engines_tlp_tx_mux/c_state.S_TLP_TX_s2
To top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_data_fifo/full_s0
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.000 0.000 tINS RR 9685 clk_ibuf/O
0.300 0.300 tNET RR 1 top/u_dma/u_c2h_all_engines/u_c2h_all_engines_tlp_tx_mux/c_state.S_TLP_TX_s2/CLK
0.606 0.306 tC2Q RR 272 top/u_dma/u_c2h_all_engines/u_c2h_all_engines_tlp_tx_mux/c_state.S_TLP_TX_s2/Q
0.906 0.300 tNET RR 1 top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_c2h_engine_tlp_tx_mux/n362_s3/I0
1.327 0.421 tINS RR 43 top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_c2h_engine_tlp_tx_mux/n362_s3/F
1.627 0.300 tNET RR 1 top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_c2h_data/tlp_tx_eop_int_s5/I0
2.048 0.421 tINS RR 13 top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_c2h_data/tlp_tx_eop_int_s5/F
2.348 0.300 tNET RR 1 top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_data_fifo/n16_s1/I0
2.769 0.421 tINS RR 5 top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_data_fifo/n16_s1/F
3.069 0.300 tNET RR 1 top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_data_fifo/n16_s2/I1
3.482 0.413 tINS RR 17 top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_data_fifo/n16_s2/F
3.782 0.300 tNET RR 2 top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_data_fifo/next_cnt_0_s/I1
4.232 0.450 tINS RF 1 top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_data_fifo/next_cnt_0_s/COUT
4.232 0.000 tNET FF 2 top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_data_fifo/next_cnt_1_s/CIN
4.272 0.040 tINS FR 1 top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_data_fifo/next_cnt_1_s/COUT
4.272 0.000 tNET RR 2 top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_data_fifo/next_cnt_2_s/CIN
4.312 0.040 tINS RR 1 top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_data_fifo/next_cnt_2_s/COUT
4.312 0.000 tNET RR 2 top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_data_fifo/next_cnt_3_s/CIN
4.352 0.040 tINS RR 1 top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_data_fifo/next_cnt_3_s/COUT
4.352 0.000 tNET RR 2 top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_data_fifo/next_cnt_4_s/CIN
4.547 0.195 tINS RR 6 top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_data_fifo/next_cnt_4_s/SUM
4.847 0.300 tNET RR 1 top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_data_fifo/next_cnt_5_s7/I1
5.260 0.413 tINS RR 1 top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_data_fifo/next_cnt_5_s7/F
5.560 0.300 tNET RR 1 top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_data_fifo/next_cnt_5_s6/I0
5.981 0.421 tINS RR 8 top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_data_fifo/next_cnt_5_s6/F
6.281 0.300 tNET RR 1 top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_data_fifo/next_cnt_6_s6/I1
6.694 0.413 tINS RR 3 top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_data_fifo/next_cnt_6_s6/F
6.994 0.300 tNET RR 1 top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_data_fifo/n882_s0/I1
7.407 0.413 tINS RR 1 top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_data_fifo/n882_s0/F
7.707 0.300 tNET RR 1 top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_data_fifo/full_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk
10.000 0.000 tCL RR 1 clk_ibuf/I
10.000 0.000 tINS RR 9685 clk_ibuf/O
10.300 0.300 tNET RR 1 top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_data_fifo/full_s0/CLK
10.249 -0.051 tSu 1 top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_data_fifo/full_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 11
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.300, 100.000%
Arrival Data Path Delay: cell: 4.101, 55.367%; route: 3.000, 40.502%; tC2Q: 0.306, 4.131%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.300, 100.000%

Path 3

Path Summary:
Slack 2.586
Data Arrival Time 7.663
Data Required Time 10.249
From top/u_dma/u_c2h_all_engines/u_c2h_all_engines_tlp_tx_mux/c_state.S_TLP_TX_s2
To top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_data_fifo/cnt_9_s0
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.000 0.000 tINS RR 9685 clk_ibuf/O
0.300 0.300 tNET RR 1 top/u_dma/u_c2h_all_engines/u_c2h_all_engines_tlp_tx_mux/c_state.S_TLP_TX_s2/CLK
0.606 0.306 tC2Q RR 272 top/u_dma/u_c2h_all_engines/u_c2h_all_engines_tlp_tx_mux/c_state.S_TLP_TX_s2/Q
0.906 0.300 tNET RR 1 top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_c2h_engine_tlp_tx_mux/n362_s3/I0
1.327 0.421 tINS RR 43 top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_c2h_engine_tlp_tx_mux/n362_s3/F
1.627 0.300 tNET RR 1 top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_c2h_data/tlp_tx_eop_int_s5/I0
2.048 0.421 tINS RR 13 top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_c2h_data/tlp_tx_eop_int_s5/F
2.348 0.300 tNET RR 1 top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_data_fifo/n16_s1/I0
2.769 0.421 tINS RR 5 top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_data_fifo/n16_s1/F
3.069 0.300 tNET RR 1 top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_data_fifo/n16_s2/I1
3.482 0.413 tINS RR 17 top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_data_fifo/n16_s2/F
3.782 0.300 tNET RR 2 top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_data_fifo/next_cnt_0_s/I1
4.232 0.450 tINS RF 1 top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_data_fifo/next_cnt_0_s/COUT
4.232 0.000 tNET FF 2 top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_data_fifo/next_cnt_1_s/CIN
4.272 0.040 tINS FR 1 top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_data_fifo/next_cnt_1_s/COUT
4.272 0.000 tNET RR 2 top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_data_fifo/next_cnt_2_s/CIN
4.312 0.040 tINS RR 1 top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_data_fifo/next_cnt_2_s/COUT
4.312 0.000 tNET RR 2 top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_data_fifo/next_cnt_3_s/CIN
4.352 0.040 tINS RR 1 top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_data_fifo/next_cnt_3_s/COUT
4.352 0.000 tNET RR 2 top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_data_fifo/next_cnt_4_s/CIN
4.547 0.195 tINS RR 6 top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_data_fifo/next_cnt_4_s/SUM
4.847 0.300 tNET RR 1 top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_data_fifo/next_cnt_5_s7/I1
5.260 0.413 tINS RR 1 top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_data_fifo/next_cnt_5_s7/F
5.560 0.300 tNET RR 1 top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_data_fifo/next_cnt_5_s6/I0
5.981 0.421 tINS RR 8 top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_data_fifo/next_cnt_5_s6/F
6.281 0.300 tNET RR 1 top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_data_fifo/next_cnt_6_s6/I1
6.694 0.413 tINS RR 3 top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_data_fifo/next_cnt_6_s6/F
6.994 0.300 tNET RR 1 top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_data_fifo/next_cnt_9_s5/I2
7.363 0.369 tINS RR 1 top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_data_fifo/next_cnt_9_s5/F
7.663 0.300 tNET RR 1 top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_data_fifo/cnt_9_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk
10.000 0.000 tCL RR 1 clk_ibuf/I
10.000 0.000 tINS RR 9685 clk_ibuf/O
10.300 0.300 tNET RR 1 top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_data_fifo/cnt_9_s0/CLK
10.249 -0.051 tSu 1 top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_data_fifo/cnt_9_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 11
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.300, 100.000%
Arrival Data Path Delay: cell: 4.057, 55.100%; route: 3.000, 40.744%; tC2Q: 0.306, 4.156%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.300, 100.000%

Path 4

Path Summary:
Slack 3.255
Data Arrival Time 6.994
Data Required Time 10.249
From top/u_dma/u_c2h_all_engines/u_c2h_all_engines_tlp_tx_mux/c_state.S_TLP_TX_s2
To top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_data_fifo/cnt_6_s0
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.000 0.000 tINS RR 9685 clk_ibuf/O
0.300 0.300 tNET RR 1 top/u_dma/u_c2h_all_engines/u_c2h_all_engines_tlp_tx_mux/c_state.S_TLP_TX_s2/CLK
0.606 0.306 tC2Q RR 272 top/u_dma/u_c2h_all_engines/u_c2h_all_engines_tlp_tx_mux/c_state.S_TLP_TX_s2/Q
0.906 0.300 tNET RR 1 top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_c2h_engine_tlp_tx_mux/n362_s3/I0
1.327 0.421 tINS RR 43 top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_c2h_engine_tlp_tx_mux/n362_s3/F
1.627 0.300 tNET RR 1 top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_c2h_data/tlp_tx_eop_int_s5/I0
2.048 0.421 tINS RR 13 top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_c2h_data/tlp_tx_eop_int_s5/F
2.348 0.300 tNET RR 1 top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_data_fifo/n16_s1/I0
2.769 0.421 tINS RR 5 top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_data_fifo/n16_s1/F
3.069 0.300 tNET RR 1 top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_data_fifo/n16_s2/I1
3.482 0.413 tINS RR 17 top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_data_fifo/n16_s2/F
3.782 0.300 tNET RR 2 top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_data_fifo/next_cnt_0_s/I1
4.232 0.450 tINS RF 1 top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_data_fifo/next_cnt_0_s/COUT
4.232 0.000 tNET FF 2 top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_data_fifo/next_cnt_1_s/CIN
4.272 0.040 tINS FR 1 top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_data_fifo/next_cnt_1_s/COUT
4.272 0.000 tNET RR 2 top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_data_fifo/next_cnt_2_s/CIN
4.312 0.040 tINS RR 1 top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_data_fifo/next_cnt_2_s/COUT
4.312 0.000 tNET RR 2 top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_data_fifo/next_cnt_3_s/CIN
4.352 0.040 tINS RR 1 top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_data_fifo/next_cnt_3_s/COUT
4.352 0.000 tNET RR 2 top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_data_fifo/next_cnt_4_s/CIN
4.547 0.195 tINS RR 6 top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_data_fifo/next_cnt_4_s/SUM
4.847 0.300 tNET RR 1 top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_data_fifo/next_cnt_5_s7/I1
5.260 0.413 tINS RR 1 top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_data_fifo/next_cnt_5_s7/F
5.560 0.300 tNET RR 1 top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_data_fifo/next_cnt_5_s6/I0
5.981 0.421 tINS RR 8 top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_data_fifo/next_cnt_5_s6/F
6.281 0.300 tNET RR 1 top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_data_fifo/next_cnt_6_s5/I1
6.694 0.413 tINS RR 1 top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_data_fifo/next_cnt_6_s5/F
6.994 0.300 tNET RR 1 top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_data_fifo/cnt_6_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk
10.000 0.000 tCL RR 1 clk_ibuf/I
10.000 0.000 tINS RR 9685 clk_ibuf/O
10.300 0.300 tNET RR 1 top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_data_fifo/cnt_6_s0/CLK
10.249 -0.051 tSu 1 top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_data_fifo/cnt_6_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 10
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.300, 100.000%
Arrival Data Path Delay: cell: 3.688, 55.094%; route: 2.700, 40.335%; tC2Q: 0.306, 4.571%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.300, 100.000%

Path 5

Path Summary:
Slack 3.299
Data Arrival Time 6.950
Data Required Time 10.249
From top/u_dma/u_c2h_all_engines/u_c2h_all_engines_tlp_tx_mux/c_state.S_TLP_TX_s2
To top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_data_fifo/cnt_7_s0
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.000 0.000 tINS RR 9685 clk_ibuf/O
0.300 0.300 tNET RR 1 top/u_dma/u_c2h_all_engines/u_c2h_all_engines_tlp_tx_mux/c_state.S_TLP_TX_s2/CLK
0.606 0.306 tC2Q RR 272 top/u_dma/u_c2h_all_engines/u_c2h_all_engines_tlp_tx_mux/c_state.S_TLP_TX_s2/Q
0.906 0.300 tNET RR 1 top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_c2h_engine_tlp_tx_mux/n362_s3/I0
1.327 0.421 tINS RR 43 top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_c2h_engine_tlp_tx_mux/n362_s3/F
1.627 0.300 tNET RR 1 top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_c2h_data/tlp_tx_eop_int_s5/I0
2.048 0.421 tINS RR 13 top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_c2h_data/tlp_tx_eop_int_s5/F
2.348 0.300 tNET RR 1 top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_data_fifo/n16_s1/I0
2.769 0.421 tINS RR 5 top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_data_fifo/n16_s1/F
3.069 0.300 tNET RR 1 top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_data_fifo/n16_s2/I1
3.482 0.413 tINS RR 17 top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_data_fifo/n16_s2/F
3.782 0.300 tNET RR 2 top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_data_fifo/next_cnt_0_s/I1
4.232 0.450 tINS RF 1 top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_data_fifo/next_cnt_0_s/COUT
4.232 0.000 tNET FF 2 top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_data_fifo/next_cnt_1_s/CIN
4.272 0.040 tINS FR 1 top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_data_fifo/next_cnt_1_s/COUT
4.272 0.000 tNET RR 2 top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_data_fifo/next_cnt_2_s/CIN
4.312 0.040 tINS RR 1 top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_data_fifo/next_cnt_2_s/COUT
4.312 0.000 tNET RR 2 top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_data_fifo/next_cnt_3_s/CIN
4.352 0.040 tINS RR 1 top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_data_fifo/next_cnt_3_s/COUT
4.352 0.000 tNET RR 2 top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_data_fifo/next_cnt_4_s/CIN
4.547 0.195 tINS RR 6 top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_data_fifo/next_cnt_4_s/SUM
4.847 0.300 tNET RR 1 top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_data_fifo/next_cnt_5_s7/I1
5.260 0.413 tINS RR 1 top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_data_fifo/next_cnt_5_s7/F
5.560 0.300 tNET RR 1 top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_data_fifo/next_cnt_5_s6/I0
5.981 0.421 tINS RR 8 top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_data_fifo/next_cnt_5_s6/F
6.281 0.300 tNET RR 1 top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_data_fifo/next_cnt_7_s8/I2
6.650 0.369 tINS RR 1 top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_data_fifo/next_cnt_7_s8/F
6.950 0.300 tNET RR 1 top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_data_fifo/cnt_7_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk
10.000 0.000 tCL RR 1 clk_ibuf/I
10.000 0.000 tINS RR 9685 clk_ibuf/O
10.300 0.300 tNET RR 1 top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_data_fifo/cnt_7_s0/CLK
10.249 -0.051 tSu 1 top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_data_fifo/cnt_7_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 10
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.300, 100.000%
Arrival Data Path Delay: cell: 3.644, 54.796%; route: 2.700, 40.602%; tC2Q: 0.306, 4.602%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.300, 100.000%