Timing Messages

Report Title	Timing Analysis Report
Design File	E:\myWork\IP\releaseVerify\version\1.9.12.01\Gowin_PCIe_SGDMA\Gowin_PCIe_SGDMA_RefDesign\project\impl\gwsynthesis\fpga_project.vg
Physical Constraints File	E:\myWork\IP\releaseVerify\version\1.9.12.01\Gowin_PCIe_SGDMA\Gowin_PCIe_SGDMA_RefDesign\project\src\fpga_project.cst
Timing Constraint File	E:\myWork\IP\releaseVerify\version\1.9.12.01\Gowin_PCIe_SGDMA\Gowin_PCIe_SGDMA_RefDesign\project\src\fpga_project.sdc
Tool Version	V1.9.12.01 (64-bit)
Part Number	GW5AT-LV60UG225C2/I1
Device	GW5AT-60
Device Version	B
Created Time	Wed Jan 7 17:12:55 2026
Legal Announcement	Copyright (C)2014-2025 Gowin Semiconductor Corporation. All rights reserved.

Timing Summaries

STA Tool Run Summary:

Setup Delay Model	Slow 0.855V 0C C2/I1
Hold Delay Model	Fast 0.945V 85C C2/I1
Numbers of Paths Analyzed	40380
Numbers of Endpoints Analyzed	48814
Numbers of Falling Endpoints	3
Numbers of Setup Violated Endpoints	0
Numbers of Hold Violated Endpoints	0

Clock Summary:

NO.	Clock Name	Type	Period	Frequency(MHz)	Rise	Fall	Source	Master	Objects
1	sysclk	Base	10.000	100.000	0.000	5.000			u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
2	tck_pad_i	Base	50.000	20.000	0.000	25.000			tck_pad_i
3	clk_50m	Base	20.000	50.000	0.000	10.000			clk_50m
4	clk_200m_p	Base	5.000	200.000	0.000	2.500			u_TLVDS_IBUF/I

Max Frequency Summary:

NO.	Clock Name	Constraint	Actual Fmax	Logic Level	Entity
1	sysclk	100.000(MHz)	101.076(MHz)	16	TOP
2	tck_pad_i	20.000(MHz)	91.395(MHz)	5	TOP
3	clk_50m	50.000(MHz)	229.095(MHz)	8	TOP

No timing paths to get frequency of clk_200m_p!

Total Negative Slack Summary:

Clock Name	Analysis Type	Endpoints TNS	Number of Endpoints
sysclk	Setup	0.000	0
sysclk	Hold	0.000	0
tck_pad_i	Setup	0.000	0
tck_pad_i	Hold	0.000	0
clk_50m	Setup	0.000	0
clk_50m	Hold	0.000	0
clk_200m_p	Setup	0.000	0
clk_200m_p	Hold	0.000	0

Timing Details

Path Slacks Table:

Setup Paths Table

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	0.107	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_h2c_engine/u_h2c_stream_if/m_axis_h2c_tkeep_tmp_13_s1/Q	u_user_stream_if_monitor/h2c_one_packet_byte_cnt_27_s1/D	sysclk:[R]	sysclk:[R]	10.000	-0.007	9.850
2	0.173	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_h2c_engine/u_h2c_stream_if/m_axis_h2c_tkeep_tmp_23_s1/Q	u_user_stream_if_monitor/h2c_one_packet_byte_cnt_29_s1/D	sysclk:[R]	sysclk:[R]	10.000	0.000	9.776
3	0.290	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_dma_target_regs/addr_int_5_s0/Q	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_dma_target_regs/cfg_interrupt_enable_23_s0/CE	sysclk:[R]	sysclk:[R]	10.000	0.007	9.454
4	0.305	u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_addr_9_s0/Q	u_user_stream_if_monitor/local_rddata_17_s0/D	sysclk:[R]	sysclk:[R]	10.000	0.015	9.629
5	0.313	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_h2c_engine/u_h2c_stream_if/m_axis_h2c_tkeep_tmp_23_s1/Q	u_user_stream_if_monitor/h2c_one_packet_byte_cnt_31_s1/D	sysclk:[R]	sysclk:[R]	10.000	0.000	9.636
6	0.321	u_dut/top/u_dma/u_c2h_all_engines/u_vld_rdy_pipe/s_ready_s0/Q	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_data_fifo/empty_s0/D	sysclk:[R]	sysclk:[R]	10.000	0.015	9.613
7	0.330	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_h2c_engine/u_h2c_stream_if/m_axis_h2c_tkeep_tmp_13_s1/Q	u_user_stream_if_monitor/h2c_one_packet_byte_cnt_13_s1/D	sysclk:[R]	sysclk:[R]	10.000	0.000	9.619
8	0.354	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_dma_target_regs/addr_int_6_s0/Q	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_dma_target_regs/target_op_resp_data_4_s0/D	sysclk:[R]	sysclk:[R]	10.000	0.000	9.595
9	0.377	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_dma_target_regs/addr_int_5_s0/Q	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_dma_target_regs/cfg_interrupt_enable_20_s0/CE	sysclk:[R]	sysclk:[R]	10.000	0.000	9.374
10	0.384	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_h2c_engine/u_data_fifo/full_s0/Q	u_dut/top/u_tlp_rx_demux/u_cpld_rx_pipe/data_pri_60_s1/D	sysclk:[R]	sysclk:[R]	10.000	0.000	9.565
11	0.384	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_h2c_engine/u_data_fifo/full_s0/Q	u_dut/top/u_tlp_rx_demux/u_cpld_rx_pipe/data_pri_61_s1/D	sysclk:[R]	sysclk:[R]	10.000	0.000	9.565
12	0.392	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_h2c_engine/u_data_fifo/full_s0/Q	u_dut/top/u_tlp_rx_demux/u_cpld_rx_pipe/data_pri_56_s1/D	sysclk:[R]	sysclk:[R]	10.000	0.000	9.557
13	0.392	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_h2c_engine/u_data_fifo/full_s0/Q	u_dut/top/u_tlp_rx_demux/u_cpld_rx_pipe/data_pri_57_s1/D	sysclk:[R]	sysclk:[R]	10.000	0.000	9.557
14	0.392	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_h2c_engine/u_data_fifo/full_s0/Q	u_dut/top/u_tlp_rx_demux/u_cpld_rx_pipe/data_pri_58_s1/D	sysclk:[R]	sysclk:[R]	10.000	0.000	9.557
15	0.392	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_h2c_engine/u_data_fifo/full_s0/Q	u_dut/top/u_tlp_rx_demux/u_cpld_rx_pipe/data_pri_59_s1/D	sysclk:[R]	sysclk:[R]	10.000	0.000	9.557
16	0.403	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_dma_target_regs/addr_int_5_s0/Q	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_dma_target_regs/cfg_interrupt_enable_22_s0/CE	sysclk:[R]	sysclk:[R]	10.000	0.000	9.348
17	0.407	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_h2c_engine/u_data_fifo/full_s0/Q	u_dut/top/u_tlp_rx_demux/u_cpld_rx_pipe/data_pri_62_s1/D	sysclk:[R]	sysclk:[R]	10.000	0.000	9.542
18	0.423	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_h2c_engine/u_data_fifo/mem_mem_0_4_s/DO[8]	u_user_stream_if_monitor/h2c_data_byte_error_14_s0/CE	sysclk:[R]	sysclk:[R]	10.000	0.000	9.328
19	0.431	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_h2c_engine/u_h2c_stream_if/m_axis_h2c_tkeep_tmp_23_s1/Q	u_user_stream_if_monitor/h2c_one_packet_byte_cnt_30_s1/D	sysclk:[R]	sysclk:[R]	10.000	-0.008	9.526
20	0.441	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_h2c_engine/u_h2c_stream_if/m_axis_h2c_tkeep_tmp_13_s1/Q	u_user_stream_if_monitor/h2c_one_packet_byte_cnt_24_s1/D	sysclk:[R]	sysclk:[R]	10.000	-0.007	9.516
21	0.447	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_h2c_engine/u_h2c_stream_if/m_axis_h2c_tkeep_tmp_13_s1/Q	u_user_stream_if_monitor/h2c_one_packet_byte_cnt_19_s1/D	sysclk:[R]	sysclk:[R]	10.000	-0.007	9.510
22	0.494	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_h2c_engine/u_h2c_stream_if/m_axis_h2c_tkeep_tmp_13_s1/Q	u_user_stream_if_monitor/h2c_one_packet_byte_cnt_26_s1/D	sysclk:[R]	sysclk:[R]	10.000	-0.007	9.463
23	0.541	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_h2c_engine/u_h2c_stream_if/m_axis_h2c_tkeep_tmp_23_s1/Q	u_user_stream_if_monitor/h2c_one_packet_byte_cnt_28_s1/D	sysclk:[R]	sysclk:[R]	10.000	0.000	9.413
24	0.545	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_h2c_engine/u_h2c_stream_if/m_axis_h2c_tkeep_tmp_13_s1/Q	u_user_stream_if_monitor/h2c_one_packet_byte_cnt_16_s1/D	sysclk:[R]	sysclk:[R]	10.000	-0.015	9.419
25	0.547	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_h2c_engine/u_h2c_stream_if/m_axis_h2c_tkeep_tmp_13_s1/Q	u_user_stream_if_monitor/h2c_one_packet_byte_cnt_18_s1/D	sysclk:[R]	sysclk:[R]	10.000	-0.015	9.417

Hold Paths Table

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	0.044	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_c2h_descriptor/descriptor_fifo_wrdata_reg_239_s0/Q	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_descriptor_fifo/mem_mem_0_0_s/DI[15]	sysclk:[R]	sysclk:[R]	0.000	-0.201	0.282
2	0.044	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_c2h_descriptor/descriptor_fifo_wrdata_reg_237_s0/Q	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_descriptor_fifo/mem_mem_0_0_s/DI[13]	sysclk:[R]	sysclk:[R]	0.000	-0.201	0.282
3	0.044	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_c2h_descriptor/descriptor_fifo_wrdata_reg_236_s0/Q	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_descriptor_fifo/mem_mem_0_0_s/DI[12]	sysclk:[R]	sysclk:[R]	0.000	-0.201	0.282
4	0.044	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_46_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[10]	sysclk:[R]	sysclk:[R]	0.000	-0.201	0.282
5	0.048	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_38_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[2]	sysclk:[R]	sysclk:[R]	0.000	-0.197	0.282
6	0.119	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_c2h_descriptor/descriptor_fifo_wrdata_reg_234_s0/Q	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_descriptor_fifo/mem_mem_0_0_s/DI[10]	sysclk:[R]	sysclk:[R]	0.000	-0.201	0.357
7	0.133	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/gowin_add_SDPX9B_mem_mem_0_8_s/ADA[10]	sysclk:[R]	sysclk:[R]	0.000	-0.197	0.367
8	0.134	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_162_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/gowin_add_SDPX9B_mem_mem_0_4_s/DI[0]	sysclk:[R]	sysclk:[R]	0.000	-0.201	0.372
9	0.134	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_c2h_descriptor/descriptor_fifo_wrdata_reg_238_s0/Q	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_descriptor_fifo/mem_mem_0_0_s/DI[14]	sysclk:[R]	sysclk:[R]	0.000	-0.201	0.372
10	0.134	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_c2h_descriptor/descriptor_fifo_wrdata_reg_235_s0/Q	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_descriptor_fifo/mem_mem_0_0_s/DI[11]	sysclk:[R]	sysclk:[R]	0.000	-0.201	0.372
11	0.134	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_39_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[3]	sysclk:[R]	sysclk:[R]	0.000	-0.201	0.372
12	0.142	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/gowin_add_SDPX9B_mem_mem_0_10_s/ADA[8]	sysclk:[R]	sysclk:[R]	0.000	-0.205	0.384
13	0.144	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_c2h_descriptor/descriptor_fifo_wrdata_reg_226_s0/Q	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_descriptor_fifo/mem_mem_0_0_s/DI[2]	sysclk:[R]	sysclk:[R]	0.000	-0.197	0.378
14	0.144	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_c2h_descriptor/descriptor_fifo_wrdata_reg_225_s0/Q	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_descriptor_fifo/mem_mem_0_0_s/DI[1]	sysclk:[R]	sysclk:[R]	0.000	-0.197	0.378
15	0.144	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_c2h_descriptor/descriptor_fifo_wrdata_reg_224_s0/Q	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_descriptor_fifo/mem_mem_0_0_s/DI[0]	sysclk:[R]	sysclk:[R]	0.000	-0.197	0.378
16	0.144	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_42_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[6]	sysclk:[R]	sysclk:[R]	0.000	-0.197	0.378
17	0.147	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/gowin_add_SDPX9B_mem_mem_0_8_s/ADA[9]	sysclk:[R]	sysclk:[R]	0.000	-0.201	0.385
18	0.148	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/gowin_add_SDPX9B_mem_mem_0_10_s/ADA[11]	sysclk:[R]	sysclk:[R]	0.000	-0.205	0.390
19	0.148	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/gowin_add_SDPX9B_mem_mem_0_8_s/ADA[8]	sysclk:[R]	sysclk:[R]	0.000	-0.201	0.386
20	0.148	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_140_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/gowin_add_SDPX9B_mem_mem_0_3_s/DI[14]	sysclk:[R]	sysclk:[R]	0.000	-0.193	0.378
21	0.148	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_139_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/gowin_add_SDPX9B_mem_mem_0_3_s/DI[13]	sysclk:[R]	sysclk:[R]	0.000	-0.193	0.378
22	0.148	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_138_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/gowin_add_SDPX9B_mem_mem_0_3_s/DI[12]	sysclk:[R]	sysclk:[R]	0.000	-0.193	0.378
23	0.151	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/gowin_add_SDPX9B_mem_mem_0_8_s/ADA[11]	sysclk:[R]	sysclk:[R]	0.000	-0.201	0.389
24	0.151	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/gowin_add_SDPX9B_mem_mem_0_8_s/ADA[6]	sysclk:[R]	sysclk:[R]	0.000	-0.193	0.381
25	0.158	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s5/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/gowin_add_SDPX9B_mem_mem_0_6_s/ADA[5]	sysclk:[R]	sysclk:[R]	0.000	-0.189	0.384

Recovery Paths Table

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	5.514	u_PCIe_IP/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/rstn_s0/Q	u_PCIe_IP/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/drp_addr_serdes_2_s0/CLEAR	sysclk:[R]	sysclk:[R]	10.000	-0.015	4.223
2	5.514	u_PCIe_IP/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/rstn_s0/Q	u_PCIe_IP/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/drp_addr_serdes_3_s0/CLEAR	sysclk:[R]	sysclk:[R]	10.000	-0.015	4.223
3	2.815	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s5/CLEAR	sysclk:[F]	sysclk:[R]	5.000	-0.011	1.918
4	2.815	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLEAR	sysclk:[F]	sysclk:[R]	5.000	-0.011	1.918
5	5.719	u_PCIe_IP/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/rstn_s0/Q	u_PCIe_IP/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wrdata_o_6_s1/CLEAR	sysclk:[R]	sysclk:[R]	10.000	-0.007	4.010
6	5.719	u_PCIe_IP/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/rstn_s0/Q	u_PCIe_IP/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wrdata_o_14_s1/CLEAR	sysclk:[R]	sysclk:[R]	10.000	-0.007	4.010
7	5.719	u_PCIe_IP/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/rstn_s0/Q	u_PCIe_IP/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wrdata_o_15_s1/CLEAR	sysclk:[R]	sysclk:[R]	10.000	-0.007	4.010
8	5.719	u_PCIe_IP/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/rstn_s0/Q	u_PCIe_IP/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wrdata_o_16_s1/CLEAR	sysclk:[R]	sysclk:[R]	10.000	-0.007	4.010
9	5.719	u_PCIe_IP/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/rstn_s0/Q	u_PCIe_IP/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/drp_wrdata_serdes_15_s0/CLEAR	sysclk:[R]	sysclk:[R]	10.000	-0.007	4.010
10	5.719	u_PCIe_IP/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/rstn_s0/Q	u_PCIe_IP/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/drp_wrdata_serdes_16_s0/CLEAR	sysclk:[R]	sysclk:[R]	10.000	-0.007	4.010
11	2.886	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/CLEAR	sysclk:[F]	sysclk:[R]	5.000	-0.406	2.243
12	2.886	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1/CLEAR	sysclk:[F]	sysclk:[R]	5.000	-0.003	1.839
13	2.886	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/CLEAR	sysclk:[F]	sysclk:[R]	5.000	-0.003	1.839
14	2.886	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1/CLEAR	sysclk:[F]	sysclk:[R]	5.000	-0.003	1.839
15	2.886	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/CLEAR	sysclk:[F]	sysclk:[R]	5.000	-0.003	1.839
16	2.893	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CLEAR	sysclk:[F]	sysclk:[R]	5.000	-0.003	1.832
17	2.893	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1/CLEAR	sysclk:[F]	sysclk:[R]	5.000	-0.003	1.832
18	2.893	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1/CLEAR	sysclk:[F]	sysclk:[R]	5.000	-0.003	1.832
19	5.887	u_PCIe_IP/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/rstn_s0/Q	u_PCIe_IP/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wrdata_o_22_s1/CLEAR	sysclk:[R]	sysclk:[R]	10.000	-0.007	3.842
20	5.887	u_PCIe_IP/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/rstn_s0/Q	u_PCIe_IP/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wrdata_o_23_s1/CLEAR	sysclk:[R]	sysclk:[R]	10.000	-0.007	3.842
21	5.887	u_PCIe_IP/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/rstn_s0/Q	u_PCIe_IP/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wrdata_o_24_s1/CLEAR	sysclk:[R]	sysclk:[R]	10.000	-0.007	3.842
22	5.887	u_PCIe_IP/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/rstn_s0/Q	u_PCIe_IP/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/drp_wrdata_serdes_14_s0/CLEAR	sysclk:[R]	sysclk:[R]	10.000	-0.007	3.842
23	5.887	u_PCIe_IP/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/rstn_s0/Q	u_PCIe_IP/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/drp_wrdata_serdes_22_s0/CLEAR	sysclk:[R]	sysclk:[R]	10.000	-0.007	3.842
24	2.947	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/CLEAR	sysclk:[F]	sysclk:[R]	5.000	0.005	1.771
25	2.947	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLEAR	sysclk:[F]	sysclk:[R]	5.000	0.005	1.771

Removal Paths Table

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	0.397	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_h2c_engine/u_descriptor_fifo/rstn_d1_s0/Q	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_h2c_engine/u_data_fifo/remaining_num_3_s0/CLEAR	sysclk:[R]	sysclk:[R]	0.000	0.000	0.344
2	0.397	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_h2c_engine/u_descriptor_fifo/rstn_d1_s0/Q	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_h2c_engine/u_data_fifo/remaining_num_4_s0/CLEAR	sysclk:[R]	sysclk:[R]	0.000	0.000	0.344
3	0.397	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_h2c_engine/u_descriptor_fifo/rstn_d1_s0/Q	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_h2c_engine/u_data_fifo/remaining_num_5_s0/CLEAR	sysclk:[R]	sysclk:[R]	0.000	0.000	0.344
4	0.484	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_descriptor_fifo/rstn_d1_s0/Q	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_descriptor_fifo/rdaddr_0_s3/CLEAR	sysclk:[R]	sysclk:[R]	0.000	0.000	0.431
5	0.484	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_descriptor_fifo/rstn_d1_s0/Q	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_descriptor_fifo/remaining_num_2_s0/CLEAR	sysclk:[R]	sysclk:[R]	0.000	0.000	0.431
6	0.484	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_descriptor_fifo/rstn_d1_s0/Q	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_descriptor_fifo/remaining_num_3_s0/CLEAR	sysclk:[R]	sysclk:[R]	0.000	0.000	0.431
7	0.484	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_descriptor_fifo/rstn_d1_s0/Q	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_descriptor_fifo/remaining_num_4_s0/PRESET	sysclk:[R]	sysclk:[R]	0.000	0.000	0.431
8	0.484	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_descriptor_fifo/rstn_d1_s0/Q	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_descriptor_fifo/full_s0/CLEAR	sysclk:[R]	sysclk:[R]	0.000	0.000	0.431
9	0.484	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_descriptor_fifo/rstn_d1_s0/Q	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_descriptor_fifo/cnt_2_s0/CLEAR	sysclk:[R]	sysclk:[R]	0.000	0.000	0.431
10	0.484	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_descriptor_fifo/rstn_d1_s0/Q	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_descriptor_fifo/cnt_4_s0/CLEAR	sysclk:[R]	sysclk:[R]	0.000	0.000	0.431
11	0.484	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_descriptor_fifo/rstn_d1_s0/Q	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_descriptor_fifo/rdaddr_1_s0/CLEAR	sysclk:[R]	sysclk:[R]	0.000	0.000	0.431
12	0.484	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_descriptor_fifo/rstn_d1_s0/Q	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_descriptor_fifo/rdaddr_2_s0/CLEAR	sysclk:[R]	sysclk:[R]	0.000	0.000	0.431
13	0.484	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_descriptor_fifo/rstn_d1_s0/Q	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_descriptor_fifo/rdaddr_3_s0/CLEAR	sysclk:[R]	sysclk:[R]	0.000	0.000	0.431
14	0.491	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_h2c_engine/u_reset_fifo/fifo_rstn_s0/Q	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_h2c_engine/u_descriptor_fifo/rstn_d0_s0/CLEAR	sysclk:[R]	sysclk:[R]	0.000	0.008	0.430
15	0.491	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_h2c_engine/u_reset_fifo/fifo_rstn_s0/Q	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_h2c_engine/u_descriptor_fifo/rstn_d1_s0/CLEAR	sysclk:[R]	sysclk:[R]	0.000	0.008	0.430
16	0.495	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_h2c_engine/u_descriptor_fifo/rstn_d1_s0/Q	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_h2c_engine/u_data_fifo/remaining_num_6_s0/CLEAR	sysclk:[R]	sysclk:[R]	0.000	-0.004	0.446
17	0.495	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_h2c_engine/u_descriptor_fifo/rstn_d1_s0/Q	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_h2c_engine/u_data_fifo/remaining_num_7_s0/CLEAR	sysclk:[R]	sysclk:[R]	0.000	-0.004	0.446
18	0.495	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_h2c_engine/u_descriptor_fifo/rstn_d1_s0/Q	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_h2c_engine/u_data_fifo/remaining_num_8_s0/CLEAR	sysclk:[R]	sysclk:[R]	0.000	-0.004	0.446
19	0.495	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_h2c_engine/u_descriptor_fifo/rstn_d1_s0/Q	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_h2c_engine/u_data_fifo/remaining_num_9_s0/PRESET	sysclk:[R]	sysclk:[R]	0.000	-0.004	0.446
20	0.495	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_h2c_engine/u_descriptor_fifo/rstn_d1_s0/Q	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_h2c_engine/u_data_fifo/cnt_2_s0/CLEAR	sysclk:[R]	sysclk:[R]	0.000	0.000	0.442
21	0.495	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_h2c_engine/u_descriptor_fifo/rstn_d1_s0/Q	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_h2c_engine/u_data_fifo/cnt_4_s0/CLEAR	sysclk:[R]	sysclk:[R]	0.000	0.000	0.442
22	0.495	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_h2c_engine/u_descriptor_fifo/rstn_d1_s0/Q	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_h2c_engine/u_data_fifo/cnt_8_s0/CLEAR	sysclk:[R]	sysclk:[R]	0.000	-0.004	0.446
23	0.516	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_descriptor_fifo/rstn_d1_s0/Q	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_info_fifo/wraddr_2_s0/CLEAR	sysclk:[R]	sysclk:[R]	0.000	0.008	0.455
24	0.516	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_descriptor_fifo/rstn_d1_s0/Q	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_info_fifo/wraddr_3_s0/CLEAR	sysclk:[R]	sysclk:[R]	0.000	0.008	0.455
25	0.517	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_descriptor_fifo/rstn_d1_s0/Q	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_data_fifo/empty_s0/PRESET	sysclk:[R]	sysclk:[R]	0.000	0.012	0.453

Minimum Pulse Width Table:

Report Command:report_min_pulse_width -nworst 10 -detail

Number	Slack	Actual Width	Required Width	Type	Clock	Objects
1	2.932	3.794	0.862	Low Pulse Width	sysclk	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_info_fifo/mem_mem_0_2_s
2	2.932	3.794	0.862	Low Pulse Width	sysclk	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/gowin_add_SDPX9B_mem_mem_0_0_s
3	2.932	3.794	0.862	Low Pulse Width	sysclk	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/gowin_add_SDPX9B_mem_mem_0_4_s
4	2.932	3.794	0.862	Low Pulse Width	sysclk	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/gowin_add_SDPX9B_mem_mem_0_10_s
5	2.932	3.794	0.862	Low Pulse Width	sysclk	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/gowin_add_SDPX9B_mem_mem_0_13_s
6	2.932	3.794	0.862	Low Pulse Width	sysclk	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_info_fifo/gowin_add_SDPB_mem_mem_0_1_s
7	2.934	3.796	0.862	High Pulse Width	sysclk	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/gowin_add_SDPX9B_mem_mem_0_0_s
8	2.934	3.796	0.862	High Pulse Width	sysclk	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/gowin_add_SDPX9B_mem_mem_0_4_s
9	2.934	3.796	0.862	High Pulse Width	sysclk	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_info_fifo/gowin_add_SDPB_mem_mem_0_1_s
10	2.934	3.796	0.862	High Pulse Width	sysclk	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/gowin_add_SDPX9B_mem_mem_0_10_s

Timing Report By Analysis Type:

Setup Analysis Report

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	0.107
Data Arrival Time	11.522
Data Required Time	11.628
From	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_h2c_engine/u_h2c_stream_if/m_axis_h2c_tkeep_tmp_13_s1
To	u_user_stream_if_monitor/h2c_one_packet_byte_cnt_27_s1
Launch Clk	sysclk:[R]
Latch Clk	sysclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sysclk
0.000	0.000	tCL	RR	13078	PLL_R[0]	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
1.672	1.672	tNET	RR	1	R39C111[2][A]	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_h2c_engine/u_h2c_stream_if/m_axis_h2c_tkeep_tmp_13_s1/CLK
1.966	0.294	tC2Q	RF	5	R39C111[2][A]	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_h2c_engine/u_h2c_stream_if/m_axis_h2c_tkeep_tmp_13_s1/Q
4.371	2.405	tNET	FF	1	R4C93[3][B]	u_user_stream_if_monitor/n2653_s61/I0
4.703	0.332	tINS	FR	3	R4C93[3][B]	u_user_stream_if_monitor/n2653_s61/F
4.983	0.280	tNET	RR	1	R2C92[3][A]	u_user_stream_if_monitor/n2652_s36/I1
5.215	0.232	tINS	RF	1	R2C92[3][A]	u_user_stream_if_monitor/n2652_s36/F
5.329	0.114	tNET	FF	1	R3C92[3][A]	u_user_stream_if_monitor/n2652_s33/I2
5.746	0.417	tINS	FR	1	R3C92[3][A]	u_user_stream_if_monitor/n2652_s33/F
5.748	0.002	tNET	RR	1	R3C92[3][B]	u_user_stream_if_monitor/n2652_s39/I3
6.080	0.332	tINS	RR	2	R3C92[3][B]	u_user_stream_if_monitor/n2652_s39/F
6.208	0.128	tNET	RR	1	R4C92[3][B]	u_user_stream_if_monitor/n2651_s16/I1
6.625	0.417	tINS	RR	1	R4C92[3][B]	u_user_stream_if_monitor/n2651_s16/F
6.933	0.308	tNET	RR	2	R3C90[1][A]	u_user_stream_if_monitor/n2651_s11/I0
7.383	0.450	tINS	RF	1	R3C90[1][A]	u_user_stream_if_monitor/n2651_s11/COUT
7.869	0.486	tNET	FF	2	R3C91[1][B]	u_user_stream_if_monitor/n2650_s12/I1
8.263	0.394	tINS	FR	1	R3C91[1][B]	u_user_stream_if_monitor/n2650_s12/COUT
8.263	0.000	tNET	RR	2	R3C91[2][A]	u_user_stream_if_monitor/n2649_s12/CIN
8.303	0.040	tINS	RR	1	R3C91[2][A]	u_user_stream_if_monitor/n2649_s12/COUT
8.303	0.000	tNET	RR	2	R3C91[2][B]	u_user_stream_if_monitor/n2648_s12/CIN
8.343	0.040	tINS	RR	1	R3C91[2][B]	u_user_stream_if_monitor/n2648_s12/COUT
8.343	0.000	tNET	RR	2	R3C92[0][A]	u_user_stream_if_monitor/n2647_s12/CIN
8.383	0.040	tINS	RR	1	R3C92[0][A]	u_user_stream_if_monitor/n2647_s12/COUT
8.383	0.000	tNET	RR	2	R3C92[0][B]	u_user_stream_if_monitor/n2646_s12/CIN
8.423	0.040	tINS	RR	1	R3C92[0][B]	u_user_stream_if_monitor/n2646_s12/COUT
8.423	0.000	tNET	RR	2	R3C92[1][A]	u_user_stream_if_monitor/n2645_s12/CIN
8.463	0.040	tINS	RR	1	R3C92[1][A]	u_user_stream_if_monitor/n2645_s12/COUT
8.463	0.000	tNET	RR	2	R3C92[1][B]	u_user_stream_if_monitor/n2644_s12/CIN
8.700	0.237	tINS	RR	1	R3C92[1][B]	u_user_stream_if_monitor/n2644_s12/SUM
9.116	0.416	tNET	RR	2	R2C92[1][B]	u_user_stream_if_monitor/n2644_s14/I1
9.510	0.394	tINS	RR	1	R2C92[1][B]	u_user_stream_if_monitor/n2644_s14/COUT
9.510	0.000	tNET	RR	2	R2C92[2][A]	u_user_stream_if_monitor/n2643_s14/CIN
9.550	0.040	tINS	RR	1	R2C92[2][A]	u_user_stream_if_monitor/n2643_s14/COUT
9.550	0.000	tNET	RR	2	R2C92[2][B]	u_user_stream_if_monitor/n2642_s14/CIN
9.590	0.040	tINS	RR	1	R2C92[2][B]	u_user_stream_if_monitor/n2642_s14/COUT
9.590	0.000	tNET	RR	2	R2C93[0][A]	u_user_stream_if_monitor/n2641_s14/CIN
9.630	0.040	tINS	RR	1	R2C93[0][A]	u_user_stream_if_monitor/n2641_s14/COUT
9.630	0.000	tNET	RR	2	R2C93[0][B]	u_user_stream_if_monitor/n2640_s14/CIN
9.670	0.040	tINS	RR	1	R2C93[0][B]	u_user_stream_if_monitor/n2640_s14/COUT
9.670	0.000	tNET	RR	2	R2C93[1][A]	u_user_stream_if_monitor/n2639_s14/CIN
9.710	0.040	tINS	RR	1	R2C93[1][A]	u_user_stream_if_monitor/n2639_s14/COUT
9.710	0.000	tNET	RR	2	R2C93[1][B]	u_user_stream_if_monitor/n2638_s14/CIN
9.750	0.040	tINS	RR	1	R2C93[1][B]	u_user_stream_if_monitor/n2638_s14/COUT
9.750	0.000	tNET	RR	2	R2C93[2][A]	u_user_stream_if_monitor/n2637_s14/CIN
9.790	0.040	tINS	RR	1	R2C93[2][A]	u_user_stream_if_monitor/n2637_s14/COUT
9.790	0.000	tNET	RR	2	R2C93[2][B]	u_user_stream_if_monitor/n2636_s14/CIN
9.830	0.040	tINS	RR	1	R2C93[2][B]	u_user_stream_if_monitor/n2636_s14/COUT
9.830	0.000	tNET	RR	2	R2C94[0][A]	u_user_stream_if_monitor/n2635_s14/CIN
9.870	0.040	tINS	RR	1	R2C94[0][A]	u_user_stream_if_monitor/n2635_s14/COUT
9.870	0.000	tNET	RR	2	R2C94[0][B]	u_user_stream_if_monitor/n2634_s14/CIN
9.910	0.040	tINS	RR	1	R2C94[0][B]	u_user_stream_if_monitor/n2634_s14/COUT
9.910	0.000	tNET	RR	2	R2C94[1][A]	u_user_stream_if_monitor/n2633_s14/CIN
9.950	0.040	tINS	RR	1	R2C94[1][A]	u_user_stream_if_monitor/n2633_s14/COUT
9.950	0.000	tNET	RR	2	R2C94[1][B]	u_user_stream_if_monitor/n2632_s14/CIN
9.990	0.040	tINS	RR	1	R2C94[1][B]	u_user_stream_if_monitor/n2632_s14/COUT
9.990	0.000	tNET	RR	2	R2C94[2][A]	u_user_stream_if_monitor/n2631_s14/CIN
10.030	0.040	tINS	RR	1	R2C94[2][A]	u_user_stream_if_monitor/n2631_s14/COUT
10.030	0.000	tNET	RR	2	R2C94[2][B]	u_user_stream_if_monitor/n2630_s14/CIN
10.070	0.040	tINS	RR	1	R2C94[2][B]	u_user_stream_if_monitor/n2630_s14/COUT
10.070	0.000	tNET	RR	2	R2C95[0][A]	u_user_stream_if_monitor/n2629_s14/CIN
10.110	0.040	tINS	RR	1	R2C95[0][A]	u_user_stream_if_monitor/n2629_s14/COUT
10.110	0.000	tNET	RR	2	R2C95[0][B]	u_user_stream_if_monitor/n2628_s14/CIN
10.150	0.040	tINS	RR	1	R2C95[0][B]	u_user_stream_if_monitor/n2628_s14/COUT
10.150	0.000	tNET	RR	2	R2C95[1][A]	u_user_stream_if_monitor/n2627_s14/CIN
10.190	0.040	tINS	RR	1	R2C95[1][A]	u_user_stream_if_monitor/n2627_s14/COUT
10.190	0.000	tNET	RR	2	R2C95[1][B]	u_user_stream_if_monitor/n2626_s14/CIN
10.427	0.237	tINS	RR	1	R2C95[1][B]	u_user_stream_if_monitor/n2626_s14/SUM
10.705	0.278	tNET	RR	1	R3C94[3][B]	u_user_stream_if_monitor/n2690_s3/I0
11.122	0.417	tINS	RR	1	R3C94[3][B]	u_user_stream_if_monitor/n2690_s3/F
11.124	0.002	tNET	RR	1	R3C94[3][A]	u_user_stream_if_monitor/n2690_s6/I0
11.522	0.398	tINS	RR	1	R3C94[3][A]	u_user_stream_if_monitor/n2690_s6/F
11.522	0.000	tNET	RR	1	R3C94[3][A]	u_user_stream_if_monitor/h2c_one_packet_byte_cnt_27_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					sysclk
10.000	0.000	tCL	RR	13078	PLL_R[0]	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
11.679	1.679	tNET	RR	1	R3C94[3][A]	u_user_stream_if_monitor/h2c_one_packet_byte_cnt_27_s1/CLK
11.628	-0.051	tSu		1	R3C94[3][A]	u_user_stream_if_monitor/h2c_one_packet_byte_cnt_27_s1

Path Statistics:

Clock Skew	0.007
Setup Relationship	10.000
Logic Level	16
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.672, 100.000%
Arrival Data Path Delay	cell: 5.137, 52.152%; route: 4.419, 44.863%; tC2Q: 0.294, 2.985%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.679, 100.000%

Path2

Path Summary:

Slack	0.173
Data Arrival Time	11.455
Data Required Time	11.628
From	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_h2c_engine/u_h2c_stream_if/m_axis_h2c_tkeep_tmp_23_s1
To	u_user_stream_if_monitor/h2c_one_packet_byte_cnt_29_s1
Launch Clk	sysclk:[R]
Latch Clk	sysclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sysclk
0.000	0.000	tCL	RR	13078	PLL_R[0]	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
1.679	1.679	tNET	RR	1	R36C110[1][B]	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_h2c_engine/u_h2c_stream_if/m_axis_h2c_tkeep_tmp_23_s1/CLK
1.973	0.294	tC2Q	RF	5	R36C110[1][B]	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_h2c_engine/u_h2c_stream_if/m_axis_h2c_tkeep_tmp_23_s1/Q
4.536	2.563	tNET	FF	1	R4C87[3][B]	u_user_stream_if_monitor/n2653_s63/I0
4.868	0.332	tINS	FR	2	R4C87[3][B]	u_user_stream_if_monitor/n2653_s63/F
5.273	0.404	tNET	RR	1	R2C91[3][B]	u_user_stream_if_monitor/n2652_s31/I0
5.689	0.417	tINS	RR	1	R2C91[3][B]	u_user_stream_if_monitor/n2652_s31/F
5.815	0.126	tNET	RR	1	R3C91[3][B]	u_user_stream_if_monitor/n2652_s38/I3
6.232	0.417	tINS	RR	2	R3C91[3][B]	u_user_stream_if_monitor/n2652_s38/F
6.360	0.128	tNET	RR	1	R4C91[3][B]	u_user_stream_if_monitor/n2651_s15/I1
6.777	0.417	tINS	RR	1	R4C91[3][B]	u_user_stream_if_monitor/n2651_s15/F
6.887	0.110	tNET	RR	2	R4C91[1][A]	u_user_stream_if_monitor/n2651_s10/I1
7.281	0.394	tINS	RR	1	R4C91[1][A]	u_user_stream_if_monitor/n2651_s10/COUT
7.281	0.000	tNET	RR	2	R4C91[1][B]	u_user_stream_if_monitor/n2650_s10/CIN
7.321	0.040	tINS	RR	1	R4C91[1][B]	u_user_stream_if_monitor/n2650_s10/COUT
7.321	0.000	tNET	RR	2	R4C91[2][A]	u_user_stream_if_monitor/n2649_s10/CIN
7.361	0.040	tINS	RR	1	R4C91[2][A]	u_user_stream_if_monitor/n2649_s10/COUT
7.361	0.000	tNET	RR	2	R4C91[2][B]	u_user_stream_if_monitor/n2648_s10/CIN
7.401	0.040	tINS	RR	1	R4C91[2][B]	u_user_stream_if_monitor/n2648_s10/COUT
7.401	0.000	tNET	RR	2	R4C92[0][A]	u_user_stream_if_monitor/n2647_s10/CIN
7.441	0.040	tINS	RR	1	R4C92[0][A]	u_user_stream_if_monitor/n2647_s10/COUT
7.441	0.000	tNET	RR	2	R4C92[0][B]	u_user_stream_if_monitor/n2646_s10/CIN
7.481	0.040	tINS	RR	1	R4C92[0][B]	u_user_stream_if_monitor/n2646_s10/COUT
7.481	0.000	tNET	RR	2	R4C92[1][A]	u_user_stream_if_monitor/n2645_s10/CIN
7.521	0.040	tINS	RR	1	R4C92[1][A]	u_user_stream_if_monitor/n2645_s10/COUT
7.521	0.000	tNET	RR	2	R4C92[1][B]	u_user_stream_if_monitor/n2644_s10/CIN
7.561	0.040	tINS	RR	1	R4C92[1][B]	u_user_stream_if_monitor/n2644_s10/COUT
7.561	0.000	tNET	RR	2	R4C92[2][A]	u_user_stream_if_monitor/n2643_s10/CIN
7.601	0.040	tINS	RR	1	R4C92[2][A]	u_user_stream_if_monitor/n2643_s10/COUT
7.601	0.000	tNET	RR	2	R4C92[2][B]	u_user_stream_if_monitor/n2642_s10/CIN
7.641	0.040	tINS	RR	1	R4C92[2][B]	u_user_stream_if_monitor/n2642_s10/COUT
7.641	0.000	tNET	RR	2	R4C93[0][A]	u_user_stream_if_monitor/n2641_s10/CIN
7.681	0.040	tINS	RR	1	R4C93[0][A]	u_user_stream_if_monitor/n2641_s10/COUT
7.681	0.000	tNET	RR	2	R4C93[0][B]	u_user_stream_if_monitor/n2640_s10/CIN
7.721	0.040	tINS	RR	1	R4C93[0][B]	u_user_stream_if_monitor/n2640_s10/COUT
7.721	0.000	tNET	RR	2	R4C93[1][A]	u_user_stream_if_monitor/n2639_s10/CIN
7.761	0.040	tINS	RR	1	R4C93[1][A]	u_user_stream_if_monitor/n2639_s10/COUT
7.761	0.000	tNET	RR	2	R4C93[1][B]	u_user_stream_if_monitor/n2638_s10/CIN
7.801	0.040	tINS	RR	1	R4C93[1][B]	u_user_stream_if_monitor/n2638_s10/COUT
7.801	0.000	tNET	RR	2	R4C93[2][A]	u_user_stream_if_monitor/n2637_s10/CIN
7.841	0.040	tINS	RR	1	R4C93[2][A]	u_user_stream_if_monitor/n2637_s10/COUT
7.841	0.000	tNET	RR	2	R4C93[2][B]	u_user_stream_if_monitor/n2636_s10/CIN
7.881	0.040	tINS	RR	1	R4C93[2][B]	u_user_stream_if_monitor/n2636_s10/COUT
7.881	0.000	tNET	RR	2	R4C94[0][A]	u_user_stream_if_monitor/n2635_s10/CIN
7.921	0.040	tINS	RR	1	R4C94[0][A]	u_user_stream_if_monitor/n2635_s10/COUT
7.921	0.000	tNET	RR	2	R4C94[0][B]	u_user_stream_if_monitor/n2634_s10/CIN
7.961	0.040	tINS	RR	1	R4C94[0][B]	u_user_stream_if_monitor/n2634_s10/COUT
7.961	0.000	tNET	RR	2	R4C94[1][A]	u_user_stream_if_monitor/n2633_s10/CIN
8.001	0.040	tINS	RR	1	R4C94[1][A]	u_user_stream_if_monitor/n2633_s10/COUT
8.001	0.000	tNET	RR	2	R4C94[1][B]	u_user_stream_if_monitor/n2632_s10/CIN
8.238	0.237	tINS	RR	1	R4C94[1][B]	u_user_stream_if_monitor/n2632_s10/SUM
8.624	0.386	tNET	RR	2	R3C94[1][B]	u_user_stream_if_monitor/n2632_s12/I1
9.018	0.394	tINS	RR	1	R3C94[1][B]	u_user_stream_if_monitor/n2632_s12/COUT
9.018	0.000	tNET	RR	2	R3C94[2][A]	u_user_stream_if_monitor/n2631_s12/CIN
9.058	0.040	tINS	RR	1	R3C94[2][A]	u_user_stream_if_monitor/n2631_s12/COUT
9.058	0.000	tNET	RR	2	R3C94[2][B]	u_user_stream_if_monitor/n2630_s12/CIN
9.098	0.040	tINS	RR	1	R3C94[2][B]	u_user_stream_if_monitor/n2630_s12/COUT
9.098	0.000	tNET	RR	2	R3C95[0][A]	u_user_stream_if_monitor/n2629_s12/CIN
9.138	0.040	tINS	RR	1	R3C95[0][A]	u_user_stream_if_monitor/n2629_s12/COUT
9.138	0.000	tNET	RR	2	R3C95[0][B]	u_user_stream_if_monitor/n2628_s12/CIN
9.178	0.040	tINS	RR	1	R3C95[0][B]	u_user_stream_if_monitor/n2628_s12/COUT
9.178	0.000	tNET	RR	2	R3C95[1][A]	u_user_stream_if_monitor/n2627_s12/CIN
9.218	0.040	tINS	RR	1	R3C95[1][A]	u_user_stream_if_monitor/n2627_s12/COUT
9.218	0.000	tNET	RR	2	R3C95[1][B]	u_user_stream_if_monitor/n2626_s12/CIN
9.455	0.237	tINS	RR	1	R3C95[1][B]	u_user_stream_if_monitor/n2626_s12/SUM
9.841	0.386	tNET	RR	2	R2C95[1][B]	u_user_stream_if_monitor/n2626_s14/I1
10.235	0.394	tINS	RR	1	R2C95[1][B]	u_user_stream_if_monitor/n2626_s14/COUT
10.235	0.000	tNET	RR	2	R2C95[2][A]	u_user_stream_if_monitor/n2625_s14/CIN
10.275	0.040	tINS	RR	1	R2C95[2][A]	u_user_stream_if_monitor/n2625_s14/COUT
10.275	0.000	tNET	RR	2	R2C95[2][B]	u_user_stream_if_monitor/n2624_s14/CIN
10.512	0.237	tINS	RR	1	R2C95[2][B]	u_user_stream_if_monitor/n2624_s14/SUM
10.639	0.126	tNET	RR	1	R2C94[3][B]	u_user_stream_if_monitor/n2688_s3/I0
11.056	0.417	tINS	RR	1	R2C94[3][B]	u_user_stream_if_monitor/n2688_s3/F
11.057	0.002	tNET	RR	1	R2C94[3][A]	u_user_stream_if_monitor/n2688_s7/I0
11.455	0.398	tINS	RR	1	R2C94[3][A]	u_user_stream_if_monitor/n2688_s7/F
11.455	0.000	tNET	RR	1	R2C94[3][A]	u_user_stream_if_monitor/h2c_one_packet_byte_cnt_29_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					sysclk
10.000	0.000	tCL	RR	13078	PLL_R[0]	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
11.679	1.679	tNET	RR	1	R2C94[3][A]	u_user_stream_if_monitor/h2c_one_packet_byte_cnt_29_s1/CLK
11.628	-0.051	tSu		1	R2C94[3][A]	u_user_stream_if_monitor/h2c_one_packet_byte_cnt_29_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	15
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.679, 100.000%
Arrival Data Path Delay	cell: 5.251, 53.713%; route: 4.231, 43.279%; tC2Q: 0.294, 3.007%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.679, 100.000%

Path3

Path Summary:

Slack	0.290
Data Arrival Time	11.133
Data Required Time	11.423
From	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_dma_target_regs/addr_int_5_s0
To	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_dma_target_regs/cfg_interrupt_enable_23_s0
Launch Clk	sysclk:[R]
Latch Clk	sysclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sysclk
0.000	0.000	tCL	RR	13078	PLL_R[0]	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
1.679	1.679	tNET	RR	1	R52C57[2][B]	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_dma_target_regs/addr_int_5_s0/CLK
1.985	0.306	tC2Q	RR	6	R52C57[2][B]	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_dma_target_regs/addr_int_5_s0/Q
4.307	2.322	tNET	RR	1	R68C93[3][A]	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_dma_target_regs/n2152_s2/I1
4.639	0.332	tINS	RR	42	R68C93[3][A]	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_dma_target_regs/n2152_s2/F
8.042	3.402	tNET	RR	1	R34C90[1][B]	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_dma_target_regs/cfg_interrupt_enable_23_s3/I3
8.462	0.421	tINS	RR	16	R34C90[1][B]	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_dma_target_regs/cfg_interrupt_enable_23_s3/F
10.610	2.148	tNET	RR	1	R66C95[2][B]	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_dma_target_regs/cfg_interrupt_enable_23_s2/I0
11.023	0.413	tINS	RR	1	R66C95[2][B]	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_dma_target_regs/cfg_interrupt_enable_23_s2/F
11.133	0.110	tNET	RR	1	R66C95[2][A]	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_dma_target_regs/cfg_interrupt_enable_23_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					sysclk
10.000	0.000	tCL	RR	13078	PLL_R[0]	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
11.672	1.672	tNET	RR	1	R66C95[2][A]	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_dma_target_regs/cfg_interrupt_enable_23_s0/CLK
11.423	-0.249	tSu		1	R66C95[2][A]	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_dma_target_regs/cfg_interrupt_enable_23_s0

Path Statistics:

Clock Skew	-0.007
Setup Relationship	10.000
Logic Level	4
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.679, 100.000%
Arrival Data Path Delay	cell: 1.166, 12.333%; route: 7.982, 84.430%; tC2Q: 0.306, 3.237%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.672, 100.000%

Path4

Path Summary:

Slack	0.305
Data Arrival Time	11.316
Data Required Time	11.621
From	u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_addr_9_s0
To	u_user_stream_if_monitor/local_rddata_17_s0
Launch Clk	sysclk:[R]
Latch Clk	sysclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sysclk
0.000	0.000	tCL	RR	13078	PLL_R[0]	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
1.687	1.687	tNET	RR	1	R13C105[0][A]	u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_addr_9_s0/CLK
1.993	0.306	tC2Q	RR	3	R13C105[0][A]	u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_addr_9_s0/Q
2.815	0.822	tNET	RR	1	R18C95[0][A]	u_Uart_to_Bus_Top/uart_bus_core/local0_rden_o_d_s4/I1
3.228	0.413	tINS	RR	1	R18C95[0][A]	u_Uart_to_Bus_Top/uart_bus_core/local0_rden_o_d_s4/F
3.555	0.327	tNET	RR	1	R20C95[0][A]	u_Uart_to_Bus_Top/uart_bus_core/local0_rden_o_d_s1/I2
3.924	0.369	tINS	RR	54	R20C95[0][A]	u_Uart_to_Bus_Top/uart_bus_core/local0_rden_o_d_s1/F
4.358	0.434	tNET	RR	1	R24C95[2][B]	u_Uart_to_Bus_Top/uart_bus_core/local0_addr_o_d_12_s0/I1
4.779	0.421	tINS	RR	1	R24C95[2][B]	u_Uart_to_Bus_Top/uart_bus_core/local0_addr_o_d_12_s0/F
4.781	0.002	tNET	RR	1	R24C95[0][A]	u_user_stream_if_monitor/n7577_s6/I0
5.202	0.421	tINS	RR	1	R24C95[0][A]	u_user_stream_if_monitor/n7577_s6/F
5.543	0.341	tNET	RR	1	R16C95[0][B]	u_user_stream_if_monitor/n7577_s4/I2
5.964	0.421	tINS	RR	4	R16C95[0][B]	u_user_stream_if_monitor/n7577_s4/F
6.960	0.996	tNET	RR	1	R3C89[3][B]	u_user_stream_if_monitor/n307_s11/I2
7.292	0.332	tINS	RR	4	R3C89[3][B]	u_user_stream_if_monitor/n307_s11/F
7.946	0.654	tNET	RR	1	R16C89[2][A]	u_user_stream_if_monitor/n255_s9/I1
8.367	0.421	tINS	RR	31	R16C89[2][A]	u_user_stream_if_monitor/n255_s9/F
9.822	1.455	tNET	RR	1	R22C88[3][B]	u_user_stream_if_monitor/n283_s7/I3
10.239	0.417	tINS	RR	1	R22C88[3][B]	u_user_stream_if_monitor/n283_s7/F
10.899	0.660	tNET	RR	1	R30C91[3][A]	u_user_stream_if_monitor/n283_s6/I0
11.316	0.417	tINS	RR	1	R30C91[3][A]	u_user_stream_if_monitor/n283_s6/F
11.316	0.000	tNET	RR	1	R30C91[3][A]	u_user_stream_if_monitor/local_rddata_17_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					sysclk
10.000	0.000	tCL	RR	13078	PLL_R[0]	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
11.672	1.672	tNET	RR	1	R30C91[3][A]	u_user_stream_if_monitor/local_rddata_17_s0/CLK
11.621	-0.051	tSu		1	R30C91[3][A]	u_user_stream_if_monitor/local_rddata_17_s0

Path Statistics:

Clock Skew	-0.015
Setup Relationship	10.000
Logic Level	10
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.687, 100.000%
Arrival Data Path Delay	cell: 3.632, 37.719%; route: 5.691, 59.103%; tC2Q: 0.306, 3.178%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.672, 100.000%

Path5

Path Summary:

Slack	0.313
Data Arrival Time	11.315
Data Required Time	11.628
From	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_h2c_engine/u_h2c_stream_if/m_axis_h2c_tkeep_tmp_23_s1
To	u_user_stream_if_monitor/h2c_one_packet_byte_cnt_31_s1
Launch Clk	sysclk:[R]
Latch Clk	sysclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sysclk
0.000	0.000	tCL	RR	13078	PLL_R[0]	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
1.679	1.679	tNET	RR	1	R36C110[1][B]	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_h2c_engine/u_h2c_stream_if/m_axis_h2c_tkeep_tmp_23_s1/CLK
1.973	0.294	tC2Q	RF	5	R36C110[1][B]	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_h2c_engine/u_h2c_stream_if/m_axis_h2c_tkeep_tmp_23_s1/Q
4.536	2.563	tNET	FF	1	R4C87[3][B]	u_user_stream_if_monitor/n2653_s63/I0
4.868	0.332	tINS	FR	2	R4C87[3][B]	u_user_stream_if_monitor/n2653_s63/F
5.273	0.404	tNET	RR	1	R2C91[3][B]	u_user_stream_if_monitor/n2652_s31/I0
5.689	0.417	tINS	RR	1	R2C91[3][B]	u_user_stream_if_monitor/n2652_s31/F
5.815	0.126	tNET	RR	1	R3C91[3][B]	u_user_stream_if_monitor/n2652_s38/I3
6.232	0.417	tINS	RR	2	R3C91[3][B]	u_user_stream_if_monitor/n2652_s38/F
6.360	0.128	tNET	RR	1	R4C91[3][B]	u_user_stream_if_monitor/n2651_s15/I1
6.777	0.417	tINS	RR	1	R4C91[3][B]	u_user_stream_if_monitor/n2651_s15/F
6.887	0.110	tNET	RR	2	R4C91[1][A]	u_user_stream_if_monitor/n2651_s10/I1
7.281	0.394	tINS	RR	1	R4C91[1][A]	u_user_stream_if_monitor/n2651_s10/COUT
7.281	0.000	tNET	RR	2	R4C91[1][B]	u_user_stream_if_monitor/n2650_s10/CIN
7.321	0.040	tINS	RR	1	R4C91[1][B]	u_user_stream_if_monitor/n2650_s10/COUT
7.321	0.000	tNET	RR	2	R4C91[2][A]	u_user_stream_if_monitor/n2649_s10/CIN
7.361	0.040	tINS	RR	1	R4C91[2][A]	u_user_stream_if_monitor/n2649_s10/COUT
7.361	0.000	tNET	RR	2	R4C91[2][B]	u_user_stream_if_monitor/n2648_s10/CIN
7.401	0.040	tINS	RR	1	R4C91[2][B]	u_user_stream_if_monitor/n2648_s10/COUT
7.401	0.000	tNET	RR	2	R4C92[0][A]	u_user_stream_if_monitor/n2647_s10/CIN
7.441	0.040	tINS	RR	1	R4C92[0][A]	u_user_stream_if_monitor/n2647_s10/COUT
7.441	0.000	tNET	RR	2	R4C92[0][B]	u_user_stream_if_monitor/n2646_s10/CIN
7.481	0.040	tINS	RR	1	R4C92[0][B]	u_user_stream_if_monitor/n2646_s10/COUT
7.481	0.000	tNET	RR	2	R4C92[1][A]	u_user_stream_if_monitor/n2645_s10/CIN
7.521	0.040	tINS	RR	1	R4C92[1][A]	u_user_stream_if_monitor/n2645_s10/COUT
7.521	0.000	tNET	RR	2	R4C92[1][B]	u_user_stream_if_monitor/n2644_s10/CIN
7.561	0.040	tINS	RR	1	R4C92[1][B]	u_user_stream_if_monitor/n2644_s10/COUT
7.561	0.000	tNET	RR	2	R4C92[2][A]	u_user_stream_if_monitor/n2643_s10/CIN
7.601	0.040	tINS	RR	1	R4C92[2][A]	u_user_stream_if_monitor/n2643_s10/COUT
7.601	0.000	tNET	RR	2	R4C92[2][B]	u_user_stream_if_monitor/n2642_s10/CIN
7.641	0.040	tINS	RR	1	R4C92[2][B]	u_user_stream_if_monitor/n2642_s10/COUT
7.641	0.000	tNET	RR	2	R4C93[0][A]	u_user_stream_if_monitor/n2641_s10/CIN
7.681	0.040	tINS	RR	1	R4C93[0][A]	u_user_stream_if_monitor/n2641_s10/COUT
7.681	0.000	tNET	RR	2	R4C93[0][B]	u_user_stream_if_monitor/n2640_s10/CIN
7.721	0.040	tINS	RR	1	R4C93[0][B]	u_user_stream_if_monitor/n2640_s10/COUT
7.721	0.000	tNET	RR	2	R4C93[1][A]	u_user_stream_if_monitor/n2639_s10/CIN
7.761	0.040	tINS	RR	1	R4C93[1][A]	u_user_stream_if_monitor/n2639_s10/COUT
7.761	0.000	tNET	RR	2	R4C93[1][B]	u_user_stream_if_monitor/n2638_s10/CIN
7.801	0.040	tINS	RR	1	R4C93[1][B]	u_user_stream_if_monitor/n2638_s10/COUT
7.801	0.000	tNET	RR	2	R4C93[2][A]	u_user_stream_if_monitor/n2637_s10/CIN
7.841	0.040	tINS	RR	1	R4C93[2][A]	u_user_stream_if_monitor/n2637_s10/COUT
7.841	0.000	tNET	RR	2	R4C93[2][B]	u_user_stream_if_monitor/n2636_s10/CIN
7.881	0.040	tINS	RR	1	R4C93[2][B]	u_user_stream_if_monitor/n2636_s10/COUT
7.881	0.000	tNET	RR	2	R4C94[0][A]	u_user_stream_if_monitor/n2635_s10/CIN
7.921	0.040	tINS	RR	1	R4C94[0][A]	u_user_stream_if_monitor/n2635_s10/COUT
7.921	0.000	tNET	RR	2	R4C94[0][B]	u_user_stream_if_monitor/n2634_s10/CIN
7.961	0.040	tINS	RR	1	R4C94[0][B]	u_user_stream_if_monitor/n2634_s10/COUT
7.961	0.000	tNET	RR	2	R4C94[1][A]	u_user_stream_if_monitor/n2633_s10/CIN
8.001	0.040	tINS	RR	1	R4C94[1][A]	u_user_stream_if_monitor/n2633_s10/COUT
8.001	0.000	tNET	RR	2	R4C94[1][B]	u_user_stream_if_monitor/n2632_s10/CIN
8.238	0.237	tINS	RR	1	R4C94[1][B]	u_user_stream_if_monitor/n2632_s10/SUM
8.624	0.386	tNET	RR	2	R3C94[1][B]	u_user_stream_if_monitor/n2632_s12/I1
9.018	0.394	tINS	RR	1	R3C94[1][B]	u_user_stream_if_monitor/n2632_s12/COUT
9.018	0.000	tNET	RR	2	R3C94[2][A]	u_user_stream_if_monitor/n2631_s12/CIN
9.058	0.040	tINS	RR	1	R3C94[2][A]	u_user_stream_if_monitor/n2631_s12/COUT
9.058	0.000	tNET	RR	2	R3C94[2][B]	u_user_stream_if_monitor/n2630_s12/CIN
9.098	0.040	tINS	RR	1	R3C94[2][B]	u_user_stream_if_monitor/n2630_s12/COUT
9.098	0.000	tNET	RR	2	R3C95[0][A]	u_user_stream_if_monitor/n2629_s12/CIN
9.138	0.040	tINS	RR	1	R3C95[0][A]	u_user_stream_if_monitor/n2629_s12/COUT
9.138	0.000	tNET	RR	2	R3C95[0][B]	u_user_stream_if_monitor/n2628_s12/CIN
9.178	0.040	tINS	RR	1	R3C95[0][B]	u_user_stream_if_monitor/n2628_s12/COUT
9.178	0.000	tNET	RR	2	R3C95[1][A]	u_user_stream_if_monitor/n2627_s12/CIN
9.218	0.040	tINS	RR	1	R3C95[1][A]	u_user_stream_if_monitor/n2627_s12/COUT
9.218	0.000	tNET	RR	2	R3C95[1][B]	u_user_stream_if_monitor/n2626_s12/CIN
9.455	0.237	tINS	RR	1	R3C95[1][B]	u_user_stream_if_monitor/n2626_s12/SUM
9.841	0.386	tNET	RR	2	R2C95[1][B]	u_user_stream_if_monitor/n2626_s14/I1
10.235	0.394	tINS	RR	1	R2C95[1][B]	u_user_stream_if_monitor/n2626_s14/COUT
10.235	0.000	tNET	RR	2	R2C95[2][A]	u_user_stream_if_monitor/n2625_s14/CIN
10.275	0.040	tINS	RR	1	R2C95[2][A]	u_user_stream_if_monitor/n2625_s14/COUT
10.275	0.000	tNET	RR	2	R2C95[2][B]	u_user_stream_if_monitor/n2624_s14/CIN
10.315	0.040	tINS	RR	1	R2C95[2][B]	u_user_stream_if_monitor/n2624_s14/COUT
10.315	0.000	tNET	RR	2	R2C96[0][A]	u_user_stream_if_monitor/n2623_s14/CIN
10.355	0.040	tINS	RR	1	R2C96[0][A]	u_user_stream_if_monitor/n2623_s14/COUT
10.355	0.000	tNET	RR	2	R2C96[0][B]	u_user_stream_if_monitor/n2622_s14/CIN
10.592	0.237	tINS	RR	1	R2C96[0][B]	u_user_stream_if_monitor/n2622_s14/SUM
10.898	0.306	tNET	RR	1	R4C94[3][A]	u_user_stream_if_monitor/n2686_s2/I1
11.315	0.417	tINS	RR	1	R4C94[3][A]	u_user_stream_if_monitor/n2686_s2/F
11.315	0.000	tNET	RR	1	R4C94[3][A]	u_user_stream_if_monitor/h2c_one_packet_byte_cnt_31_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					sysclk
10.000	0.000	tCL	RR	13078	PLL_R[0]	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
11.679	1.679	tNET	RR	1	R4C94[3][A]	u_user_stream_if_monitor/h2c_one_packet_byte_cnt_31_s1/CLK
11.628	-0.051	tSu		1	R4C94[3][A]	u_user_stream_if_monitor/h2c_one_packet_byte_cnt_31_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	15
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.679, 100.000%
Arrival Data Path Delay	cell: 4.933, 51.193%; route: 4.409, 45.756%; tC2Q: 0.294, 3.051%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.679, 100.000%

Path6

Path Summary:

Slack	0.321
Data Arrival Time	11.300
Data Required Time	11.621
From	u_dut/top/u_dma/u_c2h_all_engines/u_vld_rdy_pipe/s_ready_s0
To	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_data_fifo/empty_s0
Launch Clk	sysclk:[R]
Latch Clk	sysclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sysclk
0.000	0.000	tCL	RR	13078	PLL_R[0]	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
1.687	1.687	tNET	RR	1	R70C72[0][B]	u_dut/top/u_dma/u_c2h_all_engines/u_vld_rdy_pipe/s_ready_s0/CLK
1.993	0.306	tC2Q	RR	7	R70C72[0][B]	u_dut/top/u_dma/u_c2h_all_engines/u_vld_rdy_pipe/s_ready_s0/Q
2.894	0.901	tNET	RR	1	R61C85[1][A]	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_c2h_engine_tlp_tx_mux/n362_s3/I2
3.307	0.413	tINS	RR	43	R61C85[1][A]	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_c2h_engine_tlp_tx_mux/n362_s3/F
4.709	1.402	tNET	RR	1	R35C73[0][A]	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_c2h_data/tlp_tx_eop_int_s5/I0
5.078	0.369	tINS	RR	13	R35C73[0][A]	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_c2h_data/tlp_tx_eop_int_s5/F
5.673	0.595	tNET	RR	1	R35C85[2][B]	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_data_fifo/n16_s1/I0
6.086	0.413	tINS	RR	5	R35C85[2][B]	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_data_fifo/n16_s1/F
6.601	0.515	tNET	RR	1	R51C85[1][A]	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_data_fifo/n16_s2/I1
7.022	0.421	tINS	RR	25	R51C85[1][A]	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_data_fifo/n16_s2/F
7.324	0.302	tNET	RR	2	R51C82[0][A]	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_data_fifo/next_cnt_0_s/I1
7.718	0.394	tINS	RR	1	R51C82[0][A]	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_data_fifo/next_cnt_0_s/COUT
7.718	0.000	tNET	RR	2	R51C82[0][B]	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_data_fifo/next_cnt_1_s/CIN
7.758	0.040	tINS	RR	1	R51C82[0][B]	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_data_fifo/next_cnt_1_s/COUT
7.758	0.000	tNET	RR	2	R51C82[1][A]	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_data_fifo/next_cnt_2_s/CIN
7.953	0.195	tINS	RF	4	R51C82[1][A]	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_data_fifo/next_cnt_2_s/SUM
8.272	0.319	tNET	FF	1	R51C79[3][A]	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_data_fifo/next_cnt_2_s8/I1
8.689	0.417	tINS	FR	4	R51C79[3][A]	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_data_fifo/next_cnt_2_s8/F
8.971	0.282	tNET	RR	1	R51C82[3][A]	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_data_fifo/next_cnt_5_s6/I3
9.303	0.332	tINS	RR	8	R51C82[3][A]	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_data_fifo/next_cnt_5_s6/F
9.437	0.134	tNET	RR	1	R51C81[2][B]	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_data_fifo/next_cnt_6_s6/I1
9.850	0.413	tINS	RR	3	R51C81[2][B]	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_data_fifo/next_cnt_6_s6/F
9.964	0.114	tNET	RR	2	R51C81[0][B]	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_data_fifo/next_cnt_7_s4/I1
10.414	0.450	tINS	RF	1	R51C81[0][B]	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_data_fifo/next_cnt_7_s4/COUT
10.414	0.000	tNET	FF	2	R51C81[1][A]	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_data_fifo/next_cnt_8_s4/CIN
10.454	0.040	tINS	FR	1	R51C81[1][A]	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_data_fifo/next_cnt_8_s4/COUT
10.931	0.477	tNET	RR	1	R51C83[2][A]	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_data_fifo/n883_s1/I0
11.300	0.369	tINS	RR	1	R51C83[2][A]	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_data_fifo/n883_s1/F
11.300	0.000	tNET	RR	1	R51C83[2][A]	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_data_fifo/empty_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					sysclk
10.000	0.000	tCL	RR	13078	PLL_R[0]	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
11.672	1.672	tNET	RR	1	R51C83[2][A]	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_data_fifo/empty_s0/CLK
11.621	-0.051	tSu		1	R51C83[2][A]	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_data_fifo/empty_s0

Path Statistics:

Clock Skew	-0.015
Setup Relationship	10.000
Logic Level	13
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.687, 100.000%
Arrival Data Path Delay	cell: 4.266, 44.377%; route: 5.041, 52.439%; tC2Q: 0.306, 3.183%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.672, 100.000%

Path7

Path Summary:

Slack	0.330
Data Arrival Time	11.291
Data Required Time	11.621
From	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_h2c_engine/u_h2c_stream_if/m_axis_h2c_tkeep_tmp_13_s1
To	u_user_stream_if_monitor/h2c_one_packet_byte_cnt_13_s1
Launch Clk	sysclk:[R]
Latch Clk	sysclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sysclk
0.000	0.000	tCL	RR	13078	PLL_R[0]	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
1.672	1.672	tNET	RR	1	R39C111[2][A]	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_h2c_engine/u_h2c_stream_if/m_axis_h2c_tkeep_tmp_13_s1/CLK
1.966	0.294	tC2Q	RF	5	R39C111[2][A]	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_h2c_engine/u_h2c_stream_if/m_axis_h2c_tkeep_tmp_13_s1/Q
4.371	2.405	tNET	FF	1	R4C93[3][B]	u_user_stream_if_monitor/n2653_s61/I0
4.703	0.332	tINS	FR	3	R4C93[3][B]	u_user_stream_if_monitor/n2653_s61/F
4.983	0.280	tNET	RR	1	R2C92[3][A]	u_user_stream_if_monitor/n2652_s36/I1
5.215	0.232	tINS	RF	1	R2C92[3][A]	u_user_stream_if_monitor/n2652_s36/F
5.329	0.114	tNET	FF	1	R3C92[3][A]	u_user_stream_if_monitor/n2652_s33/I2
5.746	0.417	tINS	FR	1	R3C92[3][A]	u_user_stream_if_monitor/n2652_s33/F
5.748	0.002	tNET	RR	1	R3C92[3][B]	u_user_stream_if_monitor/n2652_s39/I3
6.080	0.332	tINS	RR	2	R3C92[3][B]	u_user_stream_if_monitor/n2652_s39/F
6.208	0.128	tNET	RR	1	R4C92[3][B]	u_user_stream_if_monitor/n2651_s16/I1
6.625	0.417	tINS	RR	1	R4C92[3][B]	u_user_stream_if_monitor/n2651_s16/F
6.933	0.308	tNET	RR	2	R3C90[1][A]	u_user_stream_if_monitor/n2651_s11/I0
7.383	0.450	tINS	RF	1	R3C90[1][A]	u_user_stream_if_monitor/n2651_s11/COUT
7.869	0.486	tNET	FF	2	R3C91[1][B]	u_user_stream_if_monitor/n2650_s12/I1
8.263	0.394	tINS	FR	1	R3C91[1][B]	u_user_stream_if_monitor/n2650_s12/COUT
8.263	0.000	tNET	RR	2	R3C91[2][A]	u_user_stream_if_monitor/n2649_s12/CIN
8.303	0.040	tINS	RR	1	R3C91[2][A]	u_user_stream_if_monitor/n2649_s12/COUT
8.303	0.000	tNET	RR	2	R3C91[2][B]	u_user_stream_if_monitor/n2648_s12/CIN
8.343	0.040	tINS	RR	1	R3C91[2][B]	u_user_stream_if_monitor/n2648_s12/COUT
8.343	0.000	tNET	RR	2	R3C92[0][A]	u_user_stream_if_monitor/n2647_s12/CIN
8.383	0.040	tINS	RR	1	R3C92[0][A]	u_user_stream_if_monitor/n2647_s12/COUT
8.383	0.000	tNET	RR	2	R3C92[0][B]	u_user_stream_if_monitor/n2646_s12/CIN
8.423	0.040	tINS	RR	1	R3C92[0][B]	u_user_stream_if_monitor/n2646_s12/COUT
8.423	0.000	tNET	RR	2	R3C92[1][A]	u_user_stream_if_monitor/n2645_s12/CIN
8.463	0.040	tINS	RR	1	R3C92[1][A]	u_user_stream_if_monitor/n2645_s12/COUT
8.463	0.000	tNET	RR	2	R3C92[1][B]	u_user_stream_if_monitor/n2644_s12/CIN
8.700	0.237	tINS	RR	1	R3C92[1][B]	u_user_stream_if_monitor/n2644_s12/SUM
9.116	0.416	tNET	RR	2	R2C92[1][B]	u_user_stream_if_monitor/n2644_s14/I1
9.510	0.394	tINS	RR	1	R2C92[1][B]	u_user_stream_if_monitor/n2644_s14/COUT
9.510	0.000	tNET	RR	2	R2C92[2][A]	u_user_stream_if_monitor/n2643_s14/CIN
9.550	0.040	tINS	RR	1	R2C92[2][A]	u_user_stream_if_monitor/n2643_s14/COUT
9.550	0.000	tNET	RR	2	R2C92[2][B]	u_user_stream_if_monitor/n2642_s14/CIN
9.590	0.040	tINS	RR	1	R2C92[2][B]	u_user_stream_if_monitor/n2642_s14/COUT
9.590	0.000	tNET	RR	2	R2C93[0][A]	u_user_stream_if_monitor/n2641_s14/CIN
9.630	0.040	tINS	RR	1	R2C93[0][A]	u_user_stream_if_monitor/n2641_s14/COUT
9.630	0.000	tNET	RR	2	R2C93[0][B]	u_user_stream_if_monitor/n2640_s14/CIN
9.867	0.237	tINS	RR	1	R2C93[0][B]	u_user_stream_if_monitor/n2640_s14/SUM
10.355	0.488	tNET	RR	1	R3C89[0][B]	u_user_stream_if_monitor/n2704_s3/I0
10.724	0.369	tINS	RR	1	R3C89[0][B]	u_user_stream_if_monitor/n2704_s3/F
10.878	0.154	tNET	RR	1	R3C87[0][A]	u_user_stream_if_monitor/n2704_s5/I0
11.291	0.413	tINS	RR	1	R3C87[0][A]	u_user_stream_if_monitor/n2704_s5/F
11.291	0.000	tNET	RR	1	R3C87[0][A]	u_user_stream_if_monitor/h2c_one_packet_byte_cnt_13_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					sysclk
10.000	0.000	tCL	RR	13078	PLL_R[0]	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
11.672	1.672	tNET	RR	1	R3C87[0][A]	u_user_stream_if_monitor/h2c_one_packet_byte_cnt_13_s1/CLK
11.621	-0.051	tSu		1	R3C87[0][A]	u_user_stream_if_monitor/h2c_one_packet_byte_cnt_13_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	15
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.672, 100.000%
Arrival Data Path Delay	cell: 4.544, 47.240%; route: 4.781, 49.704%; tC2Q: 0.294, 3.056%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.672, 100.000%

Path8

Path Summary:

Slack	0.354
Data Arrival Time	11.275
Data Required Time	11.628
From	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_dma_target_regs/addr_int_6_s0
To	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_dma_target_regs/target_op_resp_data_4_s0
Launch Clk	sysclk:[R]
Latch Clk	sysclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sysclk
0.000	0.000	tCL	RR	13078	PLL_R[0]	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
1.679	1.679	tNET	RR	1	R52C57[2][A]	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_dma_target_regs/addr_int_6_s0/CLK
1.985	0.306	tC2Q	RR	4	R52C57[2][A]	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_dma_target_regs/addr_int_6_s0/Q
4.168	2.182	tNET	RR	1	R68C93[2][B]	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_dma_target_regs/n4300_s3/I1
4.581	0.413	tINS	RR	54	R68C93[2][B]	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_dma_target_regs/n4300_s3/F
6.538	1.957	tNET	RR	1	R34C90[3][A]	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_dma_target_regs/n4403_s1/I2
6.750	0.212	tINS	RR	49	R34C90[3][A]	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_dma_target_regs/n4403_s1/F
9.712	2.962	tNET	RR	1	R67C95[0][A]	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_dma_target_regs/n443_s6/I1
10.081	0.369	tINS	RR	1	R67C95[0][A]	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_dma_target_regs/n443_s6/F
10.359	0.278	tNET	RR	1	R69C94[1][B]	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_dma_target_regs/n443_s3/I2
10.780	0.421	tINS	RR	1	R69C94[1][B]	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_dma_target_regs/n443_s3/F
10.906	0.126	tNET	RR	1	R68C94[0][A]	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_dma_target_regs/n443_s2/I0
11.275	0.369	tINS	RR	1	R68C94[0][A]	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_dma_target_regs/n443_s2/F
11.275	0.000	tNET	RR	1	R68C94[0][A]	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_dma_target_regs/target_op_resp_data_4_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					sysclk
10.000	0.000	tCL	RR	13078	PLL_R[0]	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
11.679	1.679	tNET	RR	1	R68C94[0][A]	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_dma_target_regs/target_op_resp_data_4_s0/CLK
11.628	-0.051	tSu		1	R68C94[0][A]	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_dma_target_regs/target_op_resp_data_4_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	6
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.679, 100.000%
Arrival Data Path Delay	cell: 1.784, 18.593%; route: 7.505, 78.218%; tC2Q: 0.306, 3.189%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.679, 100.000%

Path9

Path Summary:

Slack	0.377
Data Arrival Time	11.053
Data Required Time	11.431
From	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_dma_target_regs/addr_int_5_s0
To	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_dma_target_regs/cfg_interrupt_enable_20_s0
Launch Clk	sysclk:[R]
Latch Clk	sysclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sysclk
0.000	0.000	tCL	RR	13078	PLL_R[0]	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
1.679	1.679	tNET	RR	1	R52C57[2][B]	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_dma_target_regs/addr_int_5_s0/CLK
1.985	0.306	tC2Q	RR	6	R52C57[2][B]	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_dma_target_regs/addr_int_5_s0/Q
4.307	2.322	tNET	RR	1	R68C93[3][A]	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_dma_target_regs/n2152_s2/I1
4.639	0.332	tINS	RR	42	R68C93[3][A]	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_dma_target_regs/n2152_s2/F
8.042	3.402	tNET	RR	1	R34C90[1][B]	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_dma_target_regs/cfg_interrupt_enable_23_s3/I3
8.462	0.421	tINS	RR	16	R34C90[1][B]	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_dma_target_regs/cfg_interrupt_enable_23_s3/F
10.545	2.083	tNET	RR	1	R63C94[3][B]	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_dma_target_regs/cfg_interrupt_enable_20_s2/I0
10.943	0.398	tINS	RR	1	R63C94[3][B]	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_dma_target_regs/cfg_interrupt_enable_20_s2/F
11.053	0.110	tNET	RR	1	R63C94[1][A]	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_dma_target_regs/cfg_interrupt_enable_20_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					sysclk
10.000	0.000	tCL	RR	13078	PLL_R[0]	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
11.679	1.679	tNET	RR	1	R63C94[1][A]	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_dma_target_regs/cfg_interrupt_enable_20_s0/CLK
11.431	-0.249	tSu		1	R63C94[1][A]	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_dma_target_regs/cfg_interrupt_enable_20_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	4
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.679, 100.000%
Arrival Data Path Delay	cell: 1.151, 12.279%; route: 7.917, 84.457%; tC2Q: 0.306, 3.264%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.679, 100.000%

Path10

Path Summary:

Slack	0.384
Data Arrival Time	11.245
Data Required Time	11.628
From	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_h2c_engine/u_data_fifo/full_s0
To	u_dut/top/u_tlp_rx_demux/u_cpld_rx_pipe/data_pri_60_s1
Launch Clk	sysclk:[R]
Latch Clk	sysclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sysclk
0.000	0.000	tCL	RR	13078	PLL_R[0]	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
1.679	1.679	tNET	RR	1	R50C112[2][A]	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_h2c_engine/u_data_fifo/full_s0/CLK
1.985	0.306	tC2Q	RR	430	R50C112[2][A]	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_h2c_engine/u_data_fifo/full_s0/Q
2.513	0.528	tNET	RR	1	R51C103[2][B]	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_h2c_engine/u_h2c_engine_tlp_rx_demux/cpld_tlp_rx_ready_int_0_s/I0
2.926	0.413	tINS	RR	263	R51C103[2][B]	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_h2c_engine/u_h2c_engine_tlp_rx_demux/cpld_tlp_rx_ready_int_0_s/F
3.620	0.694	tNET	RR	1	R43C96[0][B]	u_dut/top/u_dma/u_h2c_all_engines/u_c2h_all_engine_tlp_rx_demux/h2c_cpld_tlp_rx_ready_s/I1
4.042	0.421	tINS	RR	264	R43C96[0][B]	u_dut/top/u_dma/u_h2c_all_engines/u_c2h_all_engine_tlp_rx_demux/h2c_cpld_tlp_rx_ready_s/F
6.184	2.142	tNET	RR	1	R34C47[2][B]	u_dut/top/u_cpld_rx_demux/cpld_rx_ready_s/I2
6.597	0.413	tINS	RR	267	R34C47[2][B]	u_dut/top/u_cpld_rx_demux/cpld_rx_ready_s/F
6.759	0.162	tNET	RR	1	R34C49[3][B]	u_dut/top/u_tlp_rx_demux/u_cpld_rx_pipe/n612_s4/I1
7.157	0.398	tINS	RR	1	R34C49[3][B]	u_dut/top/u_tlp_rx_demux/u_cpld_rx_pipe/n612_s4/F
7.159	0.002	tNET	RR	1	R34C49[3][A]	u_dut/top/u_tlp_rx_demux/u_cpld_rx_pipe/n612_s2/I1
7.496	0.337	tINS	RF	260	R34C49[3][A]	u_dut/top/u_tlp_rx_demux/u_cpld_rx_pipe/n612_s2/F
10.824	3.328	tNET	FF	1	R44C55[2][A]	u_dut/top/u_tlp_rx_demux/u_cpld_rx_pipe/n831_s1/I1
11.245	0.421	tINS	FR	1	R44C55[2][A]	u_dut/top/u_tlp_rx_demux/u_cpld_rx_pipe/n831_s1/F
11.245	0.000	tNET	RR	1	R44C55[2][A]	u_dut/top/u_tlp_rx_demux/u_cpld_rx_pipe/data_pri_60_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					sysclk
10.000	0.000	tCL	RR	13078	PLL_R[0]	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
11.679	1.679	tNET	RR	1	R44C55[2][A]	u_dut/top/u_tlp_rx_demux/u_cpld_rx_pipe/data_pri_60_s1/CLK
11.628	-0.051	tSu		1	R44C55[2][A]	u_dut/top/u_tlp_rx_demux/u_cpld_rx_pipe/data_pri_60_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.679, 100.000%
Arrival Data Path Delay	cell: 2.403, 25.123%; route: 6.856, 71.678%; tC2Q: 0.306, 3.199%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.679, 100.000%

Path11

Path Summary:

Slack	0.384
Data Arrival Time	11.245
Data Required Time	11.628
From	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_h2c_engine/u_data_fifo/full_s0
To	u_dut/top/u_tlp_rx_demux/u_cpld_rx_pipe/data_pri_61_s1
Launch Clk	sysclk:[R]
Latch Clk	sysclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sysclk
0.000	0.000	tCL	RR	13078	PLL_R[0]	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
1.679	1.679	tNET	RR	1	R50C112[2][A]	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_h2c_engine/u_data_fifo/full_s0/CLK
1.985	0.306	tC2Q	RR	430	R50C112[2][A]	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_h2c_engine/u_data_fifo/full_s0/Q
2.513	0.528	tNET	RR	1	R51C103[2][B]	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_h2c_engine/u_h2c_engine_tlp_rx_demux/cpld_tlp_rx_ready_int_0_s/I0
2.926	0.413	tINS	RR	263	R51C103[2][B]	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_h2c_engine/u_h2c_engine_tlp_rx_demux/cpld_tlp_rx_ready_int_0_s/F
3.620	0.694	tNET	RR	1	R43C96[0][B]	u_dut/top/u_dma/u_h2c_all_engines/u_c2h_all_engine_tlp_rx_demux/h2c_cpld_tlp_rx_ready_s/I1
4.042	0.421	tINS	RR	264	R43C96[0][B]	u_dut/top/u_dma/u_h2c_all_engines/u_c2h_all_engine_tlp_rx_demux/h2c_cpld_tlp_rx_ready_s/F
6.184	2.142	tNET	RR	1	R34C47[2][B]	u_dut/top/u_cpld_rx_demux/cpld_rx_ready_s/I2
6.597	0.413	tINS	RR	267	R34C47[2][B]	u_dut/top/u_cpld_rx_demux/cpld_rx_ready_s/F
6.759	0.162	tNET	RR	1	R34C49[3][B]	u_dut/top/u_tlp_rx_demux/u_cpld_rx_pipe/n612_s4/I1
7.157	0.398	tINS	RR	1	R34C49[3][B]	u_dut/top/u_tlp_rx_demux/u_cpld_rx_pipe/n612_s4/F
7.159	0.002	tNET	RR	1	R34C49[3][A]	u_dut/top/u_tlp_rx_demux/u_cpld_rx_pipe/n612_s2/I1
7.496	0.337	tINS	RF	260	R34C49[3][A]	u_dut/top/u_tlp_rx_demux/u_cpld_rx_pipe/n612_s2/F
10.824	3.328	tNET	FF	1	R44C55[2][B]	u_dut/top/u_tlp_rx_demux/u_cpld_rx_pipe/n830_s1/I1
11.245	0.421	tINS	FR	1	R44C55[2][B]	u_dut/top/u_tlp_rx_demux/u_cpld_rx_pipe/n830_s1/F
11.245	0.000	tNET	RR	1	R44C55[2][B]	u_dut/top/u_tlp_rx_demux/u_cpld_rx_pipe/data_pri_61_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					sysclk
10.000	0.000	tCL	RR	13078	PLL_R[0]	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
11.679	1.679	tNET	RR	1	R44C55[2][B]	u_dut/top/u_tlp_rx_demux/u_cpld_rx_pipe/data_pri_61_s1/CLK
11.628	-0.051	tSu		1	R44C55[2][B]	u_dut/top/u_tlp_rx_demux/u_cpld_rx_pipe/data_pri_61_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.679, 100.000%
Arrival Data Path Delay	cell: 2.403, 25.123%; route: 6.856, 71.678%; tC2Q: 0.306, 3.199%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.679, 100.000%

Path12

Path Summary:

Slack	0.392
Data Arrival Time	11.237
Data Required Time	11.628
From	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_h2c_engine/u_data_fifo/full_s0
To	u_dut/top/u_tlp_rx_demux/u_cpld_rx_pipe/data_pri_56_s1
Launch Clk	sysclk:[R]
Latch Clk	sysclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sysclk
0.000	0.000	tCL	RR	13078	PLL_R[0]	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
1.679	1.679	tNET	RR	1	R50C112[2][A]	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_h2c_engine/u_data_fifo/full_s0/CLK
1.985	0.306	tC2Q	RR	430	R50C112[2][A]	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_h2c_engine/u_data_fifo/full_s0/Q
2.513	0.528	tNET	RR	1	R51C103[2][B]	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_h2c_engine/u_h2c_engine_tlp_rx_demux/cpld_tlp_rx_ready_int_0_s/I0
2.926	0.413	tINS	RR	263	R51C103[2][B]	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_h2c_engine/u_h2c_engine_tlp_rx_demux/cpld_tlp_rx_ready_int_0_s/F
3.620	0.694	tNET	RR	1	R43C96[0][B]	u_dut/top/u_dma/u_h2c_all_engines/u_c2h_all_engine_tlp_rx_demux/h2c_cpld_tlp_rx_ready_s/I1
4.042	0.421	tINS	RR	264	R43C96[0][B]	u_dut/top/u_dma/u_h2c_all_engines/u_c2h_all_engine_tlp_rx_demux/h2c_cpld_tlp_rx_ready_s/F
6.184	2.142	tNET	RR	1	R34C47[2][B]	u_dut/top/u_cpld_rx_demux/cpld_rx_ready_s/I2
6.597	0.413	tINS	RR	267	R34C47[2][B]	u_dut/top/u_cpld_rx_demux/cpld_rx_ready_s/F
6.759	0.162	tNET	RR	1	R34C49[3][B]	u_dut/top/u_tlp_rx_demux/u_cpld_rx_pipe/n612_s4/I1
7.157	0.398	tINS	RR	1	R34C49[3][B]	u_dut/top/u_tlp_rx_demux/u_cpld_rx_pipe/n612_s4/F
7.159	0.002	tNET	RR	1	R34C49[3][A]	u_dut/top/u_tlp_rx_demux/u_cpld_rx_pipe/n612_s2/I1
7.496	0.337	tINS	RF	260	R34C49[3][A]	u_dut/top/u_tlp_rx_demux/u_cpld_rx_pipe/n612_s2/F
10.824	3.328	tNET	FF	1	R44C55[0][A]	u_dut/top/u_tlp_rx_demux/u_cpld_rx_pipe/n835_s1/I1
11.237	0.413	tINS	FR	1	R44C55[0][A]	u_dut/top/u_tlp_rx_demux/u_cpld_rx_pipe/n835_s1/F
11.237	0.000	tNET	RR	1	R44C55[0][A]	u_dut/top/u_tlp_rx_demux/u_cpld_rx_pipe/data_pri_56_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					sysclk
10.000	0.000	tCL	RR	13078	PLL_R[0]	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
11.679	1.679	tNET	RR	1	R44C55[0][A]	u_dut/top/u_tlp_rx_demux/u_cpld_rx_pipe/data_pri_56_s1/CLK
11.628	-0.051	tSu		1	R44C55[0][A]	u_dut/top/u_tlp_rx_demux/u_cpld_rx_pipe/data_pri_56_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.679, 100.000%
Arrival Data Path Delay	cell: 2.395, 25.060%; route: 6.856, 71.738%; tC2Q: 0.306, 3.202%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.679, 100.000%

Path13

Path Summary:

Slack	0.392
Data Arrival Time	11.237
Data Required Time	11.628
From	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_h2c_engine/u_data_fifo/full_s0
To	u_dut/top/u_tlp_rx_demux/u_cpld_rx_pipe/data_pri_57_s1
Launch Clk	sysclk:[R]
Latch Clk	sysclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sysclk
0.000	0.000	tCL	RR	13078	PLL_R[0]	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
1.679	1.679	tNET	RR	1	R50C112[2][A]	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_h2c_engine/u_data_fifo/full_s0/CLK
1.985	0.306	tC2Q	RR	430	R50C112[2][A]	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_h2c_engine/u_data_fifo/full_s0/Q
2.513	0.528	tNET	RR	1	R51C103[2][B]	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_h2c_engine/u_h2c_engine_tlp_rx_demux/cpld_tlp_rx_ready_int_0_s/I0
2.926	0.413	tINS	RR	263	R51C103[2][B]	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_h2c_engine/u_h2c_engine_tlp_rx_demux/cpld_tlp_rx_ready_int_0_s/F
3.620	0.694	tNET	RR	1	R43C96[0][B]	u_dut/top/u_dma/u_h2c_all_engines/u_c2h_all_engine_tlp_rx_demux/h2c_cpld_tlp_rx_ready_s/I1
4.042	0.421	tINS	RR	264	R43C96[0][B]	u_dut/top/u_dma/u_h2c_all_engines/u_c2h_all_engine_tlp_rx_demux/h2c_cpld_tlp_rx_ready_s/F
6.184	2.142	tNET	RR	1	R34C47[2][B]	u_dut/top/u_cpld_rx_demux/cpld_rx_ready_s/I2
6.597	0.413	tINS	RR	267	R34C47[2][B]	u_dut/top/u_cpld_rx_demux/cpld_rx_ready_s/F
6.759	0.162	tNET	RR	1	R34C49[3][B]	u_dut/top/u_tlp_rx_demux/u_cpld_rx_pipe/n612_s4/I1
7.157	0.398	tINS	RR	1	R34C49[3][B]	u_dut/top/u_tlp_rx_demux/u_cpld_rx_pipe/n612_s4/F
7.159	0.002	tNET	RR	1	R34C49[3][A]	u_dut/top/u_tlp_rx_demux/u_cpld_rx_pipe/n612_s2/I1
7.496	0.337	tINS	RF	260	R34C49[3][A]	u_dut/top/u_tlp_rx_demux/u_cpld_rx_pipe/n612_s2/F
10.824	3.328	tNET	FF	1	R44C55[0][B]	u_dut/top/u_tlp_rx_demux/u_cpld_rx_pipe/n834_s1/I1
11.237	0.413	tINS	FR	1	R44C55[0][B]	u_dut/top/u_tlp_rx_demux/u_cpld_rx_pipe/n834_s1/F
11.237	0.000	tNET	RR	1	R44C55[0][B]	u_dut/top/u_tlp_rx_demux/u_cpld_rx_pipe/data_pri_57_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					sysclk
10.000	0.000	tCL	RR	13078	PLL_R[0]	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
11.679	1.679	tNET	RR	1	R44C55[0][B]	u_dut/top/u_tlp_rx_demux/u_cpld_rx_pipe/data_pri_57_s1/CLK
11.628	-0.051	tSu		1	R44C55[0][B]	u_dut/top/u_tlp_rx_demux/u_cpld_rx_pipe/data_pri_57_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.679, 100.000%
Arrival Data Path Delay	cell: 2.395, 25.060%; route: 6.856, 71.738%; tC2Q: 0.306, 3.202%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.679, 100.000%

Path14

Path Summary:

Slack	0.392
Data Arrival Time	11.237
Data Required Time	11.628
From	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_h2c_engine/u_data_fifo/full_s0
To	u_dut/top/u_tlp_rx_demux/u_cpld_rx_pipe/data_pri_58_s1
Launch Clk	sysclk:[R]
Latch Clk	sysclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sysclk
0.000	0.000	tCL	RR	13078	PLL_R[0]	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
1.679	1.679	tNET	RR	1	R50C112[2][A]	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_h2c_engine/u_data_fifo/full_s0/CLK
1.985	0.306	tC2Q	RR	430	R50C112[2][A]	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_h2c_engine/u_data_fifo/full_s0/Q
2.513	0.528	tNET	RR	1	R51C103[2][B]	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_h2c_engine/u_h2c_engine_tlp_rx_demux/cpld_tlp_rx_ready_int_0_s/I0
2.926	0.413	tINS	RR	263	R51C103[2][B]	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_h2c_engine/u_h2c_engine_tlp_rx_demux/cpld_tlp_rx_ready_int_0_s/F
3.620	0.694	tNET	RR	1	R43C96[0][B]	u_dut/top/u_dma/u_h2c_all_engines/u_c2h_all_engine_tlp_rx_demux/h2c_cpld_tlp_rx_ready_s/I1
4.042	0.421	tINS	RR	264	R43C96[0][B]	u_dut/top/u_dma/u_h2c_all_engines/u_c2h_all_engine_tlp_rx_demux/h2c_cpld_tlp_rx_ready_s/F
6.184	2.142	tNET	RR	1	R34C47[2][B]	u_dut/top/u_cpld_rx_demux/cpld_rx_ready_s/I2
6.597	0.413	tINS	RR	267	R34C47[2][B]	u_dut/top/u_cpld_rx_demux/cpld_rx_ready_s/F
6.759	0.162	tNET	RR	1	R34C49[3][B]	u_dut/top/u_tlp_rx_demux/u_cpld_rx_pipe/n612_s4/I1
7.157	0.398	tINS	RR	1	R34C49[3][B]	u_dut/top/u_tlp_rx_demux/u_cpld_rx_pipe/n612_s4/F
7.159	0.002	tNET	RR	1	R34C49[3][A]	u_dut/top/u_tlp_rx_demux/u_cpld_rx_pipe/n612_s2/I1
7.496	0.337	tINS	RF	260	R34C49[3][A]	u_dut/top/u_tlp_rx_demux/u_cpld_rx_pipe/n612_s2/F
10.824	3.328	tNET	FF	1	R44C55[1][A]	u_dut/top/u_tlp_rx_demux/u_cpld_rx_pipe/n833_s1/I1
11.237	0.413	tINS	FR	1	R44C55[1][A]	u_dut/top/u_tlp_rx_demux/u_cpld_rx_pipe/n833_s1/F
11.237	0.000	tNET	RR	1	R44C55[1][A]	u_dut/top/u_tlp_rx_demux/u_cpld_rx_pipe/data_pri_58_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					sysclk
10.000	0.000	tCL	RR	13078	PLL_R[0]	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
11.679	1.679	tNET	RR	1	R44C55[1][A]	u_dut/top/u_tlp_rx_demux/u_cpld_rx_pipe/data_pri_58_s1/CLK
11.628	-0.051	tSu		1	R44C55[1][A]	u_dut/top/u_tlp_rx_demux/u_cpld_rx_pipe/data_pri_58_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.679, 100.000%
Arrival Data Path Delay	cell: 2.395, 25.060%; route: 6.856, 71.738%; tC2Q: 0.306, 3.202%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.679, 100.000%

Path15

Path Summary:

Slack	0.392
Data Arrival Time	11.237
Data Required Time	11.628
From	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_h2c_engine/u_data_fifo/full_s0
To	u_dut/top/u_tlp_rx_demux/u_cpld_rx_pipe/data_pri_59_s1
Launch Clk	sysclk:[R]
Latch Clk	sysclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sysclk
0.000	0.000	tCL	RR	13078	PLL_R[0]	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
1.679	1.679	tNET	RR	1	R50C112[2][A]	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_h2c_engine/u_data_fifo/full_s0/CLK
1.985	0.306	tC2Q	RR	430	R50C112[2][A]	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_h2c_engine/u_data_fifo/full_s0/Q
2.513	0.528	tNET	RR	1	R51C103[2][B]	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_h2c_engine/u_h2c_engine_tlp_rx_demux/cpld_tlp_rx_ready_int_0_s/I0
2.926	0.413	tINS	RR	263	R51C103[2][B]	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_h2c_engine/u_h2c_engine_tlp_rx_demux/cpld_tlp_rx_ready_int_0_s/F
3.620	0.694	tNET	RR	1	R43C96[0][B]	u_dut/top/u_dma/u_h2c_all_engines/u_c2h_all_engine_tlp_rx_demux/h2c_cpld_tlp_rx_ready_s/I1
4.042	0.421	tINS	RR	264	R43C96[0][B]	u_dut/top/u_dma/u_h2c_all_engines/u_c2h_all_engine_tlp_rx_demux/h2c_cpld_tlp_rx_ready_s/F
6.184	2.142	tNET	RR	1	R34C47[2][B]	u_dut/top/u_cpld_rx_demux/cpld_rx_ready_s/I2
6.597	0.413	tINS	RR	267	R34C47[2][B]	u_dut/top/u_cpld_rx_demux/cpld_rx_ready_s/F
6.759	0.162	tNET	RR	1	R34C49[3][B]	u_dut/top/u_tlp_rx_demux/u_cpld_rx_pipe/n612_s4/I1
7.157	0.398	tINS	RR	1	R34C49[3][B]	u_dut/top/u_tlp_rx_demux/u_cpld_rx_pipe/n612_s4/F
7.159	0.002	tNET	RR	1	R34C49[3][A]	u_dut/top/u_tlp_rx_demux/u_cpld_rx_pipe/n612_s2/I1
7.496	0.337	tINS	RF	260	R34C49[3][A]	u_dut/top/u_tlp_rx_demux/u_cpld_rx_pipe/n612_s2/F
10.824	3.328	tNET	FF	1	R44C55[1][B]	u_dut/top/u_tlp_rx_demux/u_cpld_rx_pipe/n832_s1/I1
11.237	0.413	tINS	FR	1	R44C55[1][B]	u_dut/top/u_tlp_rx_demux/u_cpld_rx_pipe/n832_s1/F
11.237	0.000	tNET	RR	1	R44C55[1][B]	u_dut/top/u_tlp_rx_demux/u_cpld_rx_pipe/data_pri_59_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					sysclk
10.000	0.000	tCL	RR	13078	PLL_R[0]	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
11.679	1.679	tNET	RR	1	R44C55[1][B]	u_dut/top/u_tlp_rx_demux/u_cpld_rx_pipe/data_pri_59_s1/CLK
11.628	-0.051	tSu		1	R44C55[1][B]	u_dut/top/u_tlp_rx_demux/u_cpld_rx_pipe/data_pri_59_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.679, 100.000%
Arrival Data Path Delay	cell: 2.395, 25.060%; route: 6.856, 71.738%; tC2Q: 0.306, 3.202%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.679, 100.000%

Path16

Path Summary:

Slack	0.403
Data Arrival Time	11.028
Data Required Time	11.431
From	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_dma_target_regs/addr_int_5_s0
To	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_dma_target_regs/cfg_interrupt_enable_22_s0
Launch Clk	sysclk:[R]
Latch Clk	sysclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sysclk
0.000	0.000	tCL	RR	13078	PLL_R[0]	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
1.679	1.679	tNET	RR	1	R52C57[2][B]	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_dma_target_regs/addr_int_5_s0/CLK
1.985	0.306	tC2Q	RR	6	R52C57[2][B]	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_dma_target_regs/addr_int_5_s0/Q
4.307	2.322	tNET	RR	1	R68C93[3][A]	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_dma_target_regs/n2152_s2/I1
4.639	0.332	tINS	RR	42	R68C93[3][A]	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_dma_target_regs/n2152_s2/F
8.042	3.402	tNET	RR	1	R34C90[1][B]	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_dma_target_regs/cfg_interrupt_enable_23_s3/I3
8.462	0.421	tINS	RR	16	R34C90[1][B]	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_dma_target_regs/cfg_interrupt_enable_23_s3/F
10.549	2.086	tNET	RR	1	R72C94[1][B]	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_dma_target_regs/cfg_interrupt_enable_22_s2/I0
10.918	0.369	tINS	RR	1	R72C94[1][B]	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_dma_target_regs/cfg_interrupt_enable_22_s2/F
11.028	0.110	tNET	RR	1	R72C94[0][A]	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_dma_target_regs/cfg_interrupt_enable_22_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					sysclk
10.000	0.000	tCL	RR	13078	PLL_R[0]	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
11.679	1.679	tNET	RR	1	R72C94[0][A]	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_dma_target_regs/cfg_interrupt_enable_22_s0/CLK
11.431	-0.249	tSu		1	R72C94[0][A]	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_dma_target_regs/cfg_interrupt_enable_22_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	4
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.679, 100.000%
Arrival Data Path Delay	cell: 1.122, 12.003%; route: 7.920, 84.724%; tC2Q: 0.306, 3.273%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.679, 100.000%

Path17

Path Summary:

Slack	0.407
Data Arrival Time	11.222
Data Required Time	11.628
From	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_h2c_engine/u_data_fifo/full_s0
To	u_dut/top/u_tlp_rx_demux/u_cpld_rx_pipe/data_pri_62_s1
Launch Clk	sysclk:[R]
Latch Clk	sysclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sysclk
0.000	0.000	tCL	RR	13078	PLL_R[0]	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
1.679	1.679	tNET	RR	1	R50C112[2][A]	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_h2c_engine/u_data_fifo/full_s0/CLK
1.985	0.306	tC2Q	RR	430	R50C112[2][A]	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_h2c_engine/u_data_fifo/full_s0/Q
2.513	0.528	tNET	RR	1	R51C103[2][B]	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_h2c_engine/u_h2c_engine_tlp_rx_demux/cpld_tlp_rx_ready_int_0_s/I0
2.926	0.413	tINS	RR	263	R51C103[2][B]	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_h2c_engine/u_h2c_engine_tlp_rx_demux/cpld_tlp_rx_ready_int_0_s/F
3.620	0.694	tNET	RR	1	R43C96[0][B]	u_dut/top/u_dma/u_h2c_all_engines/u_c2h_all_engine_tlp_rx_demux/h2c_cpld_tlp_rx_ready_s/I1
4.042	0.421	tINS	RR	264	R43C96[0][B]	u_dut/top/u_dma/u_h2c_all_engines/u_c2h_all_engine_tlp_rx_demux/h2c_cpld_tlp_rx_ready_s/F
6.184	2.142	tNET	RR	1	R34C47[2][B]	u_dut/top/u_cpld_rx_demux/cpld_rx_ready_s/I2
6.597	0.413	tINS	RR	267	R34C47[2][B]	u_dut/top/u_cpld_rx_demux/cpld_rx_ready_s/F
6.759	0.162	tNET	RR	1	R34C49[3][B]	u_dut/top/u_tlp_rx_demux/u_cpld_rx_pipe/n612_s4/I1
7.157	0.398	tINS	RR	1	R34C49[3][B]	u_dut/top/u_tlp_rx_demux/u_cpld_rx_pipe/n612_s4/F
7.159	0.002	tNET	RR	1	R34C49[3][A]	u_dut/top/u_tlp_rx_demux/u_cpld_rx_pipe/n612_s2/I1
7.496	0.337	tINS	RF	260	R34C49[3][A]	u_dut/top/u_tlp_rx_demux/u_cpld_rx_pipe/n612_s2/F
10.824	3.328	tNET	FF	1	R44C55[3][A]	u_dut/top/u_tlp_rx_demux/u_cpld_rx_pipe/n829_s1/I1
11.222	0.398	tINS	FR	1	R44C55[3][A]	u_dut/top/u_tlp_rx_demux/u_cpld_rx_pipe/n829_s1/F
11.222	0.000	tNET	RR	1	R44C55[3][A]	u_dut/top/u_tlp_rx_demux/u_cpld_rx_pipe/data_pri_62_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					sysclk
10.000	0.000	tCL	RR	13078	PLL_R[0]	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
11.679	1.679	tNET	RR	1	R44C55[3][A]	u_dut/top/u_tlp_rx_demux/u_cpld_rx_pipe/data_pri_62_s1/CLK
11.628	-0.051	tSu		1	R44C55[3][A]	u_dut/top/u_tlp_rx_demux/u_cpld_rx_pipe/data_pri_62_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.679, 100.000%
Arrival Data Path Delay	cell: 2.380, 24.942%; route: 6.856, 71.851%; tC2Q: 0.306, 3.207%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.679, 100.000%

Path18

Path Summary:

Slack	0.423
Data Arrival Time	11.007
Data Required Time	11.431
From	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_h2c_engine/u_data_fifo/mem_mem_0_4_s
To	u_user_stream_if_monitor/h2c_data_byte_error_14_s0
Launch Clk	sysclk:[R]
Latch Clk	sysclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sysclk
0.000	0.000	tCL	RR	13078	PLL_R[0]	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
1.679	1.679	tNET	RR	16	BSRAM_R38[27]	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_h2c_engine/u_data_fifo/mem_mem_0_4_s/CLKB
3.287	1.608	tC2Q	RR	2	BSRAM_R38[27]	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_h2c_engine/u_data_fifo/mem_mem_0_4_s/DO[8]
7.227	3.940	tNET	RR	2	R30C33[0][A]	u_user_stream_if_monitor/n2127_s0/I1
7.677	0.450	tINS	RF	1	R30C33[0][A]	u_user_stream_if_monitor/n2127_s0/COUT
7.677	0.000	tNET	FF	2	R30C33[0][B]	u_user_stream_if_monitor/n2128_s0/CIN
7.717	0.040	tINS	FR	1	R30C33[0][B]	u_user_stream_if_monitor/n2128_s0/COUT
7.717	0.000	tNET	RR	2	R30C33[1][A]	u_user_stream_if_monitor/n2129_s0/CIN
7.757	0.040	tINS	RR	1	R30C33[1][A]	u_user_stream_if_monitor/n2129_s0/COUT
7.757	0.000	tNET	RR	2	R30C33[1][B]	u_user_stream_if_monitor/n2130_s0/CIN
7.797	0.040	tINS	RR	1	R30C33[1][B]	u_user_stream_if_monitor/n2130_s0/COUT
7.797	0.000	tNET	RR	2	R30C33[2][A]	u_user_stream_if_monitor/n2131_s0/CIN
7.837	0.040	tINS	RR	1	R30C33[2][A]	u_user_stream_if_monitor/n2131_s0/COUT
7.837	0.000	tNET	RR	2	R30C33[2][B]	u_user_stream_if_monitor/n2132_s0/CIN
7.877	0.040	tINS	RR	1	R30C33[2][B]	u_user_stream_if_monitor/n2132_s0/COUT
7.877	0.000	tNET	RR	2	R30C34[0][A]	u_user_stream_if_monitor/n2133_s0/CIN
7.917	0.040	tINS	RR	1	R30C34[0][A]	u_user_stream_if_monitor/n2133_s0/COUT
7.917	0.000	tNET	RR	2	R30C34[0][B]	u_user_stream_if_monitor/n2134_s0/CIN
7.957	0.040	tINS	RR	1	R30C34[0][B]	u_user_stream_if_monitor/n2134_s0/COUT
10.312	2.355	tNET	RR	1	R22C87[3][A]	u_user_stream_if_monitor/h2c_data_byte_error_14_s2/I1
10.729	0.417	tINS	RR	1	R22C87[3][A]	u_user_stream_if_monitor/h2c_data_byte_error_14_s2/F
11.007	0.278	tNET	RR	1	R22C88[0][A]	u_user_stream_if_monitor/h2c_data_byte_error_14_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					sysclk
10.000	0.000	tCL	RR	13078	PLL_R[0]	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
11.679	1.679	tNET	RR	1	R22C88[0][A]	u_user_stream_if_monitor/h2c_data_byte_error_14_s0/CLK
11.431	-0.249	tSu		1	R22C88[0][A]	u_user_stream_if_monitor/h2c_data_byte_error_14_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.679, 100.000%
Arrival Data Path Delay	cell: 1.147, 12.296%; route: 6.573, 70.465%; tC2Q: 1.608, 17.238%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.679, 100.000%

Path19

Path Summary:

Slack	0.431
Data Arrival Time	11.205
Data Required Time	11.636
From	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_h2c_engine/u_h2c_stream_if/m_axis_h2c_tkeep_tmp_23_s1
To	u_user_stream_if_monitor/h2c_one_packet_byte_cnt_30_s1
Launch Clk	sysclk:[R]
Latch Clk	sysclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sysclk
0.000	0.000	tCL	RR	13078	PLL_R[0]	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
1.679	1.679	tNET	RR	1	R36C110[1][B]	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_h2c_engine/u_h2c_stream_if/m_axis_h2c_tkeep_tmp_23_s1/CLK
1.973	0.294	tC2Q	RF	5	R36C110[1][B]	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_h2c_engine/u_h2c_stream_if/m_axis_h2c_tkeep_tmp_23_s1/Q
4.536	2.563	tNET	FF	1	R4C87[3][B]	u_user_stream_if_monitor/n2653_s63/I0
4.868	0.332	tINS	FR	2	R4C87[3][B]	u_user_stream_if_monitor/n2653_s63/F
5.273	0.404	tNET	RR	1	R2C91[3][B]	u_user_stream_if_monitor/n2652_s31/I0
5.689	0.417	tINS	RR	1	R2C91[3][B]	u_user_stream_if_monitor/n2652_s31/F
5.815	0.126	tNET	RR	1	R3C91[3][B]	u_user_stream_if_monitor/n2652_s38/I3
6.232	0.417	tINS	RR	2	R3C91[3][B]	u_user_stream_if_monitor/n2652_s38/F
6.360	0.128	tNET	RR	1	R4C91[3][B]	u_user_stream_if_monitor/n2651_s15/I1
6.777	0.417	tINS	RR	1	R4C91[3][B]	u_user_stream_if_monitor/n2651_s15/F
6.887	0.110	tNET	RR	2	R4C91[1][A]	u_user_stream_if_monitor/n2651_s10/I1
7.281	0.394	tINS	RR	1	R4C91[1][A]	u_user_stream_if_monitor/n2651_s10/COUT
7.281	0.000	tNET	RR	2	R4C91[1][B]	u_user_stream_if_monitor/n2650_s10/CIN
7.321	0.040	tINS	RR	1	R4C91[1][B]	u_user_stream_if_monitor/n2650_s10/COUT
7.321	0.000	tNET	RR	2	R4C91[2][A]	u_user_stream_if_monitor/n2649_s10/CIN
7.361	0.040	tINS	RR	1	R4C91[2][A]	u_user_stream_if_monitor/n2649_s10/COUT
7.361	0.000	tNET	RR	2	R4C91[2][B]	u_user_stream_if_monitor/n2648_s10/CIN
7.401	0.040	tINS	RR	1	R4C91[2][B]	u_user_stream_if_monitor/n2648_s10/COUT
7.401	0.000	tNET	RR	2	R4C92[0][A]	u_user_stream_if_monitor/n2647_s10/CIN
7.441	0.040	tINS	RR	1	R4C92[0][A]	u_user_stream_if_monitor/n2647_s10/COUT
7.441	0.000	tNET	RR	2	R4C92[0][B]	u_user_stream_if_monitor/n2646_s10/CIN
7.481	0.040	tINS	RR	1	R4C92[0][B]	u_user_stream_if_monitor/n2646_s10/COUT
7.481	0.000	tNET	RR	2	R4C92[1][A]	u_user_stream_if_monitor/n2645_s10/CIN
7.521	0.040	tINS	RR	1	R4C92[1][A]	u_user_stream_if_monitor/n2645_s10/COUT
7.521	0.000	tNET	RR	2	R4C92[1][B]	u_user_stream_if_monitor/n2644_s10/CIN
7.561	0.040	tINS	RR	1	R4C92[1][B]	u_user_stream_if_monitor/n2644_s10/COUT
7.561	0.000	tNET	RR	2	R4C92[2][A]	u_user_stream_if_monitor/n2643_s10/CIN
7.601	0.040	tINS	RR	1	R4C92[2][A]	u_user_stream_if_monitor/n2643_s10/COUT
7.601	0.000	tNET	RR	2	R4C92[2][B]	u_user_stream_if_monitor/n2642_s10/CIN
7.641	0.040	tINS	RR	1	R4C92[2][B]	u_user_stream_if_monitor/n2642_s10/COUT
7.641	0.000	tNET	RR	2	R4C93[0][A]	u_user_stream_if_monitor/n2641_s10/CIN
7.681	0.040	tINS	RR	1	R4C93[0][A]	u_user_stream_if_monitor/n2641_s10/COUT
7.681	0.000	tNET	RR	2	R4C93[0][B]	u_user_stream_if_monitor/n2640_s10/CIN
7.721	0.040	tINS	RR	1	R4C93[0][B]	u_user_stream_if_monitor/n2640_s10/COUT
7.721	0.000	tNET	RR	2	R4C93[1][A]	u_user_stream_if_monitor/n2639_s10/CIN
7.761	0.040	tINS	RR	1	R4C93[1][A]	u_user_stream_if_monitor/n2639_s10/COUT
7.761	0.000	tNET	RR	2	R4C93[1][B]	u_user_stream_if_monitor/n2638_s10/CIN
7.801	0.040	tINS	RR	1	R4C93[1][B]	u_user_stream_if_monitor/n2638_s10/COUT
7.801	0.000	tNET	RR	2	R4C93[2][A]	u_user_stream_if_monitor/n2637_s10/CIN
7.841	0.040	tINS	RR	1	R4C93[2][A]	u_user_stream_if_monitor/n2637_s10/COUT
7.841	0.000	tNET	RR	2	R4C93[2][B]	u_user_stream_if_monitor/n2636_s10/CIN
7.881	0.040	tINS	RR	1	R4C93[2][B]	u_user_stream_if_monitor/n2636_s10/COUT
7.881	0.000	tNET	RR	2	R4C94[0][A]	u_user_stream_if_monitor/n2635_s10/CIN
7.921	0.040	tINS	RR	1	R4C94[0][A]	u_user_stream_if_monitor/n2635_s10/COUT
7.921	0.000	tNET	RR	2	R4C94[0][B]	u_user_stream_if_monitor/n2634_s10/CIN
7.961	0.040	tINS	RR	1	R4C94[0][B]	u_user_stream_if_monitor/n2634_s10/COUT
7.961	0.000	tNET	RR	2	R4C94[1][A]	u_user_stream_if_monitor/n2633_s10/CIN
8.001	0.040	tINS	RR	1	R4C94[1][A]	u_user_stream_if_monitor/n2633_s10/COUT
8.001	0.000	tNET	RR	2	R4C94[1][B]	u_user_stream_if_monitor/n2632_s10/CIN
8.238	0.237	tINS	RR	1	R4C94[1][B]	u_user_stream_if_monitor/n2632_s10/SUM
8.624	0.386	tNET	RR	2	R3C94[1][B]	u_user_stream_if_monitor/n2632_s12/I1
9.018	0.394	tINS	RR	1	R3C94[1][B]	u_user_stream_if_monitor/n2632_s12/COUT
9.018	0.000	tNET	RR	2	R3C94[2][A]	u_user_stream_if_monitor/n2631_s12/CIN
9.058	0.040	tINS	RR	1	R3C94[2][A]	u_user_stream_if_monitor/n2631_s12/COUT
9.058	0.000	tNET	RR	2	R3C94[2][B]	u_user_stream_if_monitor/n2630_s12/CIN
9.098	0.040	tINS	RR	1	R3C94[2][B]	u_user_stream_if_monitor/n2630_s12/COUT
9.098	0.000	tNET	RR	2	R3C95[0][A]	u_user_stream_if_monitor/n2629_s12/CIN
9.138	0.040	tINS	RR	1	R3C95[0][A]	u_user_stream_if_monitor/n2629_s12/COUT
9.138	0.000	tNET	RR	2	R3C95[0][B]	u_user_stream_if_monitor/n2628_s12/CIN
9.178	0.040	tINS	RR	1	R3C95[0][B]	u_user_stream_if_monitor/n2628_s12/COUT
9.178	0.000	tNET	RR	2	R3C95[1][A]	u_user_stream_if_monitor/n2627_s12/CIN
9.218	0.040	tINS	RR	1	R3C95[1][A]	u_user_stream_if_monitor/n2627_s12/COUT
9.218	0.000	tNET	RR	2	R3C95[1][B]	u_user_stream_if_monitor/n2626_s12/CIN
9.455	0.237	tINS	RR	1	R3C95[1][B]	u_user_stream_if_monitor/n2626_s12/SUM
9.841	0.386	tNET	RR	2	R2C95[1][B]	u_user_stream_if_monitor/n2626_s14/I1
10.235	0.394	tINS	RR	1	R2C95[1][B]	u_user_stream_if_monitor/n2626_s14/COUT
10.235	0.000	tNET	RR	2	R2C95[2][A]	u_user_stream_if_monitor/n2625_s14/CIN
10.275	0.040	tINS	RR	1	R2C95[2][A]	u_user_stream_if_monitor/n2625_s14/COUT
10.275	0.000	tNET	RR	2	R2C95[2][B]	u_user_stream_if_monitor/n2624_s14/CIN
10.315	0.040	tINS	RR	1	R2C95[2][B]	u_user_stream_if_monitor/n2624_s14/COUT
10.315	0.000	tNET	RR	2	R2C96[0][A]	u_user_stream_if_monitor/n2623_s14/CIN
10.510	0.195	tINS	RR	1	R2C96[0][A]	u_user_stream_if_monitor/n2623_s14/SUM
10.788	0.278	tNET	RR	1	R2C93[3][A]	u_user_stream_if_monitor/n2687_s2/I1
11.205	0.417	tINS	RR	1	R2C93[3][A]	u_user_stream_if_monitor/n2687_s2/F
11.205	0.000	tNET	RR	1	R2C93[3][A]	u_user_stream_if_monitor/h2c_one_packet_byte_cnt_30_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					sysclk
10.000	0.000	tCL	RR	13078	PLL_R[0]	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
11.687	1.687	tNET	RR	1	R2C93[3][A]	u_user_stream_if_monitor/h2c_one_packet_byte_cnt_30_s1/CLK
11.636	-0.051	tSu		1	R2C93[3][A]	u_user_stream_if_monitor/h2c_one_packet_byte_cnt_30_s1

Path Statistics:

Clock Skew	0.008
Setup Relationship	10.000
Logic Level	15
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.679, 100.000%
Arrival Data Path Delay	cell: 4.851, 50.924%; route: 4.381, 45.990%; tC2Q: 0.294, 3.086%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.687, 100.000%

Path20

Path Summary:

Slack	0.441
Data Arrival Time	11.188
Data Required Time	11.628
From	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_h2c_engine/u_h2c_stream_if/m_axis_h2c_tkeep_tmp_13_s1
To	u_user_stream_if_monitor/h2c_one_packet_byte_cnt_24_s1
Launch Clk	sysclk:[R]
Latch Clk	sysclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sysclk
0.000	0.000	tCL	RR	13078	PLL_R[0]	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
1.672	1.672	tNET	RR	1	R39C111[2][A]	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_h2c_engine/u_h2c_stream_if/m_axis_h2c_tkeep_tmp_13_s1/CLK
1.966	0.294	tC2Q	RF	5	R39C111[2][A]	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_h2c_engine/u_h2c_stream_if/m_axis_h2c_tkeep_tmp_13_s1/Q
4.371	2.405	tNET	FF	1	R4C93[3][B]	u_user_stream_if_monitor/n2653_s61/I0
4.703	0.332	tINS	FR	3	R4C93[3][B]	u_user_stream_if_monitor/n2653_s61/F
4.983	0.280	tNET	RR	1	R2C92[3][A]	u_user_stream_if_monitor/n2652_s36/I1
5.215	0.232	tINS	RF	1	R2C92[3][A]	u_user_stream_if_monitor/n2652_s36/F
5.329	0.114	tNET	FF	1	R3C92[3][A]	u_user_stream_if_monitor/n2652_s33/I2
5.746	0.417	tINS	FR	1	R3C92[3][A]	u_user_stream_if_monitor/n2652_s33/F
5.748	0.002	tNET	RR	1	R3C92[3][B]	u_user_stream_if_monitor/n2652_s39/I3
6.080	0.332	tINS	RR	2	R3C92[3][B]	u_user_stream_if_monitor/n2652_s39/F
6.208	0.128	tNET	RR	1	R4C92[3][B]	u_user_stream_if_monitor/n2651_s16/I1
6.625	0.417	tINS	RR	1	R4C92[3][B]	u_user_stream_if_monitor/n2651_s16/F
6.933	0.308	tNET	RR	2	R3C90[1][A]	u_user_stream_if_monitor/n2651_s11/I0
7.383	0.450	tINS	RF	1	R3C90[1][A]	u_user_stream_if_monitor/n2651_s11/COUT
7.869	0.486	tNET	FF	2	R3C91[1][B]	u_user_stream_if_monitor/n2650_s12/I1
8.263	0.394	tINS	FR	1	R3C91[1][B]	u_user_stream_if_monitor/n2650_s12/COUT
8.263	0.000	tNET	RR	2	R3C91[2][A]	u_user_stream_if_monitor/n2649_s12/CIN
8.303	0.040	tINS	RR	1	R3C91[2][A]	u_user_stream_if_monitor/n2649_s12/COUT
8.303	0.000	tNET	RR	2	R3C91[2][B]	u_user_stream_if_monitor/n2648_s12/CIN
8.343	0.040	tINS	RR	1	R3C91[2][B]	u_user_stream_if_monitor/n2648_s12/COUT
8.343	0.000	tNET	RR	2	R3C92[0][A]	u_user_stream_if_monitor/n2647_s12/CIN
8.383	0.040	tINS	RR	1	R3C92[0][A]	u_user_stream_if_monitor/n2647_s12/COUT
8.383	0.000	tNET	RR	2	R3C92[0][B]	u_user_stream_if_monitor/n2646_s12/CIN
8.423	0.040	tINS	RR	1	R3C92[0][B]	u_user_stream_if_monitor/n2646_s12/COUT
8.423	0.000	tNET	RR	2	R3C92[1][A]	u_user_stream_if_monitor/n2645_s12/CIN
8.463	0.040	tINS	RR	1	R3C92[1][A]	u_user_stream_if_monitor/n2645_s12/COUT
8.463	0.000	tNET	RR	2	R3C92[1][B]	u_user_stream_if_monitor/n2644_s12/CIN
8.700	0.237	tINS	RR	1	R3C92[1][B]	u_user_stream_if_monitor/n2644_s12/SUM
9.116	0.416	tNET	RR	2	R2C92[1][B]	u_user_stream_if_monitor/n2644_s14/I1
9.510	0.394	tINS	RR	1	R2C92[1][B]	u_user_stream_if_monitor/n2644_s14/COUT
9.510	0.000	tNET	RR	2	R2C92[2][A]	u_user_stream_if_monitor/n2643_s14/CIN
9.550	0.040	tINS	RR	1	R2C92[2][A]	u_user_stream_if_monitor/n2643_s14/COUT
9.550	0.000	tNET	RR	2	R2C92[2][B]	u_user_stream_if_monitor/n2642_s14/CIN
9.590	0.040	tINS	RR	1	R2C92[2][B]	u_user_stream_if_monitor/n2642_s14/COUT
9.590	0.000	tNET	RR	2	R2C93[0][A]	u_user_stream_if_monitor/n2641_s14/CIN
9.630	0.040	tINS	RR	1	R2C93[0][A]	u_user_stream_if_monitor/n2641_s14/COUT
9.630	0.000	tNET	RR	2	R2C93[0][B]	u_user_stream_if_monitor/n2640_s14/CIN
9.670	0.040	tINS	RR	1	R2C93[0][B]	u_user_stream_if_monitor/n2640_s14/COUT
9.670	0.000	tNET	RR	2	R2C93[1][A]	u_user_stream_if_monitor/n2639_s14/CIN
9.710	0.040	tINS	RR	1	R2C93[1][A]	u_user_stream_if_monitor/n2639_s14/COUT
9.710	0.000	tNET	RR	2	R2C93[1][B]	u_user_stream_if_monitor/n2638_s14/CIN
9.750	0.040	tINS	RR	1	R2C93[1][B]	u_user_stream_if_monitor/n2638_s14/COUT
9.750	0.000	tNET	RR	2	R2C93[2][A]	u_user_stream_if_monitor/n2637_s14/CIN
9.790	0.040	tINS	RR	1	R2C93[2][A]	u_user_stream_if_monitor/n2637_s14/COUT
9.790	0.000	tNET	RR	2	R2C93[2][B]	u_user_stream_if_monitor/n2636_s14/CIN
9.830	0.040	tINS	RR	1	R2C93[2][B]	u_user_stream_if_monitor/n2636_s14/COUT
9.830	0.000	tNET	RR	2	R2C94[0][A]	u_user_stream_if_monitor/n2635_s14/CIN
9.870	0.040	tINS	RR	1	R2C94[0][A]	u_user_stream_if_monitor/n2635_s14/COUT
9.870	0.000	tNET	RR	2	R2C94[0][B]	u_user_stream_if_monitor/n2634_s14/CIN
9.910	0.040	tINS	RR	1	R2C94[0][B]	u_user_stream_if_monitor/n2634_s14/COUT
9.910	0.000	tNET	RR	2	R2C94[1][A]	u_user_stream_if_monitor/n2633_s14/CIN
9.950	0.040	tINS	RR	1	R2C94[1][A]	u_user_stream_if_monitor/n2633_s14/COUT
9.950	0.000	tNET	RR	2	R2C94[1][B]	u_user_stream_if_monitor/n2632_s14/CIN
9.990	0.040	tINS	RR	1	R2C94[1][B]	u_user_stream_if_monitor/n2632_s14/COUT
9.990	0.000	tNET	RR	2	R2C94[2][A]	u_user_stream_if_monitor/n2631_s14/CIN
10.030	0.040	tINS	RR	1	R2C94[2][A]	u_user_stream_if_monitor/n2631_s14/COUT
10.030	0.000	tNET	RR	2	R2C94[2][B]	u_user_stream_if_monitor/n2630_s14/CIN
10.070	0.040	tINS	RR	1	R2C94[2][B]	u_user_stream_if_monitor/n2630_s14/COUT
10.070	0.000	tNET	RR	2	R2C95[0][A]	u_user_stream_if_monitor/n2629_s14/CIN
10.265	0.195	tINS	RR	1	R2C95[0][A]	u_user_stream_if_monitor/n2629_s14/SUM
10.819	0.554	tNET	RR	1	R2C90[1][B]	u_user_stream_if_monitor/n2693_s2/I1
11.188	0.369	tINS	RR	1	R2C90[1][B]	u_user_stream_if_monitor/n2693_s2/F
11.188	0.000	tNET	RR	1	R2C90[1][B]	u_user_stream_if_monitor/h2c_one_packet_byte_cnt_24_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					sysclk
10.000	0.000	tCL	RR	13078	PLL_R[0]	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
11.679	1.679	tNET	RR	1	R2C90[1][B]	u_user_stream_if_monitor/h2c_one_packet_byte_cnt_24_s1/CLK
11.628	-0.051	tSu		1	R2C90[1][B]	u_user_stream_if_monitor/h2c_one_packet_byte_cnt_24_s1

Path Statistics:

Clock Skew	0.007
Setup Relationship	10.000
Logic Level	15
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.672, 100.000%
Arrival Data Path Delay	cell: 4.529, 47.594%; route: 4.693, 49.317%; tC2Q: 0.294, 3.090%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.679, 100.000%

Path21

Path Summary:

Slack	0.447
Data Arrival Time	11.182
Data Required Time	11.628
From	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_h2c_engine/u_h2c_stream_if/m_axis_h2c_tkeep_tmp_13_s1
To	u_user_stream_if_monitor/h2c_one_packet_byte_cnt_19_s1
Launch Clk	sysclk:[R]
Latch Clk	sysclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sysclk
0.000	0.000	tCL	RR	13078	PLL_R[0]	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
1.672	1.672	tNET	RR	1	R39C111[2][A]	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_h2c_engine/u_h2c_stream_if/m_axis_h2c_tkeep_tmp_13_s1/CLK
1.966	0.294	tC2Q	RF	5	R39C111[2][A]	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_h2c_engine/u_h2c_stream_if/m_axis_h2c_tkeep_tmp_13_s1/Q
4.371	2.405	tNET	FF	1	R4C93[3][B]	u_user_stream_if_monitor/n2653_s61/I0
4.703	0.332	tINS	FR	3	R4C93[3][B]	u_user_stream_if_monitor/n2653_s61/F
4.983	0.280	tNET	RR	1	R2C92[3][A]	u_user_stream_if_monitor/n2652_s36/I1
5.215	0.232	tINS	RF	1	R2C92[3][A]	u_user_stream_if_monitor/n2652_s36/F
5.329	0.114	tNET	FF	1	R3C92[3][A]	u_user_stream_if_monitor/n2652_s33/I2
5.746	0.417	tINS	FR	1	R3C92[3][A]	u_user_stream_if_monitor/n2652_s33/F
5.748	0.002	tNET	RR	1	R3C92[3][B]	u_user_stream_if_monitor/n2652_s39/I3
6.080	0.332	tINS	RR	2	R3C92[3][B]	u_user_stream_if_monitor/n2652_s39/F
6.208	0.128	tNET	RR	1	R4C92[3][B]	u_user_stream_if_monitor/n2651_s16/I1
6.625	0.417	tINS	RR	1	R4C92[3][B]	u_user_stream_if_monitor/n2651_s16/F
6.933	0.308	tNET	RR	2	R3C90[1][A]	u_user_stream_if_monitor/n2651_s11/I0
7.383	0.450	tINS	RF	1	R3C90[1][A]	u_user_stream_if_monitor/n2651_s11/COUT
7.869	0.486	tNET	FF	2	R3C91[1][B]	u_user_stream_if_monitor/n2650_s12/I1
8.263	0.394	tINS	FR	1	R3C91[1][B]	u_user_stream_if_monitor/n2650_s12/COUT
8.263	0.000	tNET	RR	2	R3C91[2][A]	u_user_stream_if_monitor/n2649_s12/CIN
8.303	0.040	tINS	RR	1	R3C91[2][A]	u_user_stream_if_monitor/n2649_s12/COUT
8.303	0.000	tNET	RR	2	R3C91[2][B]	u_user_stream_if_monitor/n2648_s12/CIN
8.343	0.040	tINS	RR	1	R3C91[2][B]	u_user_stream_if_monitor/n2648_s12/COUT
8.343	0.000	tNET	RR	2	R3C92[0][A]	u_user_stream_if_monitor/n2647_s12/CIN
8.383	0.040	tINS	RR	1	R3C92[0][A]	u_user_stream_if_monitor/n2647_s12/COUT
8.383	0.000	tNET	RR	2	R3C92[0][B]	u_user_stream_if_monitor/n2646_s12/CIN
8.423	0.040	tINS	RR	1	R3C92[0][B]	u_user_stream_if_monitor/n2646_s12/COUT
8.423	0.000	tNET	RR	2	R3C92[1][A]	u_user_stream_if_monitor/n2645_s12/CIN
8.463	0.040	tINS	RR	1	R3C92[1][A]	u_user_stream_if_monitor/n2645_s12/COUT
8.463	0.000	tNET	RR	2	R3C92[1][B]	u_user_stream_if_monitor/n2644_s12/CIN
8.700	0.237	tINS	RR	1	R3C92[1][B]	u_user_stream_if_monitor/n2644_s12/SUM
9.116	0.416	tNET	RR	2	R2C92[1][B]	u_user_stream_if_monitor/n2644_s14/I1
9.510	0.394	tINS	RR	1	R2C92[1][B]	u_user_stream_if_monitor/n2644_s14/COUT
9.510	0.000	tNET	RR	2	R2C92[2][A]	u_user_stream_if_monitor/n2643_s14/CIN
9.550	0.040	tINS	RR	1	R2C92[2][A]	u_user_stream_if_monitor/n2643_s14/COUT
9.550	0.000	tNET	RR	2	R2C92[2][B]	u_user_stream_if_monitor/n2642_s14/CIN
9.590	0.040	tINS	RR	1	R2C92[2][B]	u_user_stream_if_monitor/n2642_s14/COUT
9.590	0.000	tNET	RR	2	R2C93[0][A]	u_user_stream_if_monitor/n2641_s14/CIN
9.630	0.040	tINS	RR	1	R2C93[0][A]	u_user_stream_if_monitor/n2641_s14/COUT
9.630	0.000	tNET	RR	2	R2C93[0][B]	u_user_stream_if_monitor/n2640_s14/CIN
9.670	0.040	tINS	RR	1	R2C93[0][B]	u_user_stream_if_monitor/n2640_s14/COUT
9.670	0.000	tNET	RR	2	R2C93[1][A]	u_user_stream_if_monitor/n2639_s14/CIN
9.710	0.040	tINS	RR	1	R2C93[1][A]	u_user_stream_if_monitor/n2639_s14/COUT
9.710	0.000	tNET	RR	2	R2C93[1][B]	u_user_stream_if_monitor/n2638_s14/CIN
9.750	0.040	tINS	RR	1	R2C93[1][B]	u_user_stream_if_monitor/n2638_s14/COUT
9.750	0.000	tNET	RR	2	R2C93[2][A]	u_user_stream_if_monitor/n2637_s14/CIN
9.790	0.040	tINS	RR	1	R2C93[2][A]	u_user_stream_if_monitor/n2637_s14/COUT
9.790	0.000	tNET	RR	2	R2C93[2][B]	u_user_stream_if_monitor/n2636_s14/CIN
9.830	0.040	tINS	RR	1	R2C93[2][B]	u_user_stream_if_monitor/n2636_s14/COUT
9.830	0.000	tNET	RR	2	R2C94[0][A]	u_user_stream_if_monitor/n2635_s14/CIN
9.870	0.040	tINS	RR	1	R2C94[0][A]	u_user_stream_if_monitor/n2635_s14/COUT
9.870	0.000	tNET	RR	2	R2C94[0][B]	u_user_stream_if_monitor/n2634_s14/CIN
10.107	0.237	tINS	RR	1	R2C94[0][B]	u_user_stream_if_monitor/n2634_s14/SUM
10.813	0.706	tNET	RR	1	R6C88[2][A]	u_user_stream_if_monitor/n2698_s2/I1
11.182	0.369	tINS	RR	1	R6C88[2][A]	u_user_stream_if_monitor/n2698_s2/F
11.182	0.000	tNET	RR	1	R6C88[2][A]	u_user_stream_if_monitor/h2c_one_packet_byte_cnt_19_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					sysclk
10.000	0.000	tCL	RR	13078	PLL_R[0]	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
11.679	1.679	tNET	RR	1	R6C88[2][A]	u_user_stream_if_monitor/h2c_one_packet_byte_cnt_19_s1/CLK
11.628	-0.051	tSu		1	R6C88[2][A]	u_user_stream_if_monitor/h2c_one_packet_byte_cnt_19_s1

Path Statistics:

Clock Skew	0.007
Setup Relationship	10.000
Logic Level	14
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.672, 100.000%
Arrival Data Path Delay	cell: 4.371, 45.962%; route: 4.845, 50.946%; tC2Q: 0.294, 3.091%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.679, 100.000%

Path22

Path Summary:

Slack	0.494
Data Arrival Time	11.135
Data Required Time	11.628
From	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_h2c_engine/u_h2c_stream_if/m_axis_h2c_tkeep_tmp_13_s1
To	u_user_stream_if_monitor/h2c_one_packet_byte_cnt_26_s1
Launch Clk	sysclk:[R]
Latch Clk	sysclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sysclk
0.000	0.000	tCL	RR	13078	PLL_R[0]	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
1.672	1.672	tNET	RR	1	R39C111[2][A]	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_h2c_engine/u_h2c_stream_if/m_axis_h2c_tkeep_tmp_13_s1/CLK
1.966	0.294	tC2Q	RF	5	R39C111[2][A]	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_h2c_engine/u_h2c_stream_if/m_axis_h2c_tkeep_tmp_13_s1/Q
4.371	2.405	tNET	FF	1	R4C93[3][B]	u_user_stream_if_monitor/n2653_s61/I0
4.703	0.332	tINS	FR	3	R4C93[3][B]	u_user_stream_if_monitor/n2653_s61/F
4.983	0.280	tNET	RR	1	R2C92[3][A]	u_user_stream_if_monitor/n2652_s36/I1
5.215	0.232	tINS	RF	1	R2C92[3][A]	u_user_stream_if_monitor/n2652_s36/F
5.329	0.114	tNET	FF	1	R3C92[3][A]	u_user_stream_if_monitor/n2652_s33/I2
5.746	0.417	tINS	FR	1	R3C92[3][A]	u_user_stream_if_monitor/n2652_s33/F
5.748	0.002	tNET	RR	1	R3C92[3][B]	u_user_stream_if_monitor/n2652_s39/I3
6.080	0.332	tINS	RR	2	R3C92[3][B]	u_user_stream_if_monitor/n2652_s39/F
6.208	0.128	tNET	RR	1	R4C92[3][B]	u_user_stream_if_monitor/n2651_s16/I1
6.625	0.417	tINS	RR	1	R4C92[3][B]	u_user_stream_if_monitor/n2651_s16/F
6.933	0.308	tNET	RR	2	R3C90[1][A]	u_user_stream_if_monitor/n2651_s11/I0
7.383	0.450	tINS	RF	1	R3C90[1][A]	u_user_stream_if_monitor/n2651_s11/COUT
7.869	0.486	tNET	FF	2	R3C91[1][B]	u_user_stream_if_monitor/n2650_s12/I1
8.263	0.394	tINS	FR	1	R3C91[1][B]	u_user_stream_if_monitor/n2650_s12/COUT
8.263	0.000	tNET	RR	2	R3C91[2][A]	u_user_stream_if_monitor/n2649_s12/CIN
8.303	0.040	tINS	RR	1	R3C91[2][A]	u_user_stream_if_monitor/n2649_s12/COUT
8.303	0.000	tNET	RR	2	R3C91[2][B]	u_user_stream_if_monitor/n2648_s12/CIN
8.343	0.040	tINS	RR	1	R3C91[2][B]	u_user_stream_if_monitor/n2648_s12/COUT
8.343	0.000	tNET	RR	2	R3C92[0][A]	u_user_stream_if_monitor/n2647_s12/CIN
8.383	0.040	tINS	RR	1	R3C92[0][A]	u_user_stream_if_monitor/n2647_s12/COUT
8.383	0.000	tNET	RR	2	R3C92[0][B]	u_user_stream_if_monitor/n2646_s12/CIN
8.423	0.040	tINS	RR	1	R3C92[0][B]	u_user_stream_if_monitor/n2646_s12/COUT
8.423	0.000	tNET	RR	2	R3C92[1][A]	u_user_stream_if_monitor/n2645_s12/CIN
8.463	0.040	tINS	RR	1	R3C92[1][A]	u_user_stream_if_monitor/n2645_s12/COUT
8.463	0.000	tNET	RR	2	R3C92[1][B]	u_user_stream_if_monitor/n2644_s12/CIN
8.700	0.237	tINS	RR	1	R3C92[1][B]	u_user_stream_if_monitor/n2644_s12/SUM
9.116	0.416	tNET	RR	2	R2C92[1][B]	u_user_stream_if_monitor/n2644_s14/I1
9.510	0.394	tINS	RR	1	R2C92[1][B]	u_user_stream_if_monitor/n2644_s14/COUT
9.510	0.000	tNET	RR	2	R2C92[2][A]	u_user_stream_if_monitor/n2643_s14/CIN
9.550	0.040	tINS	RR	1	R2C92[2][A]	u_user_stream_if_monitor/n2643_s14/COUT
9.550	0.000	tNET	RR	2	R2C92[2][B]	u_user_stream_if_monitor/n2642_s14/CIN
9.590	0.040	tINS	RR	1	R2C92[2][B]	u_user_stream_if_monitor/n2642_s14/COUT
9.590	0.000	tNET	RR	2	R2C93[0][A]	u_user_stream_if_monitor/n2641_s14/CIN
9.630	0.040	tINS	RR	1	R2C93[0][A]	u_user_stream_if_monitor/n2641_s14/COUT
9.630	0.000	tNET	RR	2	R2C93[0][B]	u_user_stream_if_monitor/n2640_s14/CIN
9.670	0.040	tINS	RR	1	R2C93[0][B]	u_user_stream_if_monitor/n2640_s14/COUT
9.670	0.000	tNET	RR	2	R2C93[1][A]	u_user_stream_if_monitor/n2639_s14/CIN
9.710	0.040	tINS	RR	1	R2C93[1][A]	u_user_stream_if_monitor/n2639_s14/COUT
9.710	0.000	tNET	RR	2	R2C93[1][B]	u_user_stream_if_monitor/n2638_s14/CIN
9.750	0.040	tINS	RR	1	R2C93[1][B]	u_user_stream_if_monitor/n2638_s14/COUT
9.750	0.000	tNET	RR	2	R2C93[2][A]	u_user_stream_if_monitor/n2637_s14/CIN
9.790	0.040	tINS	RR	1	R2C93[2][A]	u_user_stream_if_monitor/n2637_s14/COUT
9.790	0.000	tNET	RR	2	R2C93[2][B]	u_user_stream_if_monitor/n2636_s14/CIN
9.830	0.040	tINS	RR	1	R2C93[2][B]	u_user_stream_if_monitor/n2636_s14/COUT
9.830	0.000	tNET	RR	2	R2C94[0][A]	u_user_stream_if_monitor/n2635_s14/CIN
9.870	0.040	tINS	RR	1	R2C94[0][A]	u_user_stream_if_monitor/n2635_s14/COUT
9.870	0.000	tNET	RR	2	R2C94[0][B]	u_user_stream_if_monitor/n2634_s14/CIN
9.910	0.040	tINS	RR	1	R2C94[0][B]	u_user_stream_if_monitor/n2634_s14/COUT
9.910	0.000	tNET	RR	2	R2C94[1][A]	u_user_stream_if_monitor/n2633_s14/CIN
9.950	0.040	tINS	RR	1	R2C94[1][A]	u_user_stream_if_monitor/n2633_s14/COUT
9.950	0.000	tNET	RR	2	R2C94[1][B]	u_user_stream_if_monitor/n2632_s14/CIN
9.990	0.040	tINS	RR	1	R2C94[1][B]	u_user_stream_if_monitor/n2632_s14/COUT
9.990	0.000	tNET	RR	2	R2C94[2][A]	u_user_stream_if_monitor/n2631_s14/CIN
10.030	0.040	tINS	RR	1	R2C94[2][A]	u_user_stream_if_monitor/n2631_s14/COUT
10.030	0.000	tNET	RR	2	R2C94[2][B]	u_user_stream_if_monitor/n2630_s14/CIN
10.070	0.040	tINS	RR	1	R2C94[2][B]	u_user_stream_if_monitor/n2630_s14/COUT
10.070	0.000	tNET	RR	2	R2C95[0][A]	u_user_stream_if_monitor/n2629_s14/CIN
10.110	0.040	tINS	RR	1	R2C95[0][A]	u_user_stream_if_monitor/n2629_s14/COUT
10.110	0.000	tNET	RR	2	R2C95[0][B]	u_user_stream_if_monitor/n2628_s14/CIN
10.150	0.040	tINS	RR	1	R2C95[0][B]	u_user_stream_if_monitor/n2628_s14/COUT
10.150	0.000	tNET	RR	2	R2C95[1][A]	u_user_stream_if_monitor/n2627_s14/CIN
10.345	0.195	tINS	RR	1	R2C95[1][A]	u_user_stream_if_monitor/n2627_s14/SUM
10.803	0.458	tNET	RR	1	R6C94[3][A]	u_user_stream_if_monitor/n2691_s2/I1
11.135	0.332	tINS	RR	1	R6C94[3][A]	u_user_stream_if_monitor/n2691_s2/F
11.135	0.000	tNET	RR	1	R6C94[3][A]	u_user_stream_if_monitor/h2c_one_packet_byte_cnt_26_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					sysclk
10.000	0.000	tCL	RR	13078	PLL_R[0]	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
11.679	1.679	tNET	RR	1	R6C94[3][A]	u_user_stream_if_monitor/h2c_one_packet_byte_cnt_26_s1/CLK
11.628	-0.051	tSu		1	R6C94[3][A]	u_user_stream_if_monitor/h2c_one_packet_byte_cnt_26_s1

Path Statistics:

Clock Skew	0.007
Setup Relationship	10.000
Logic Level	15
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.672, 100.000%
Arrival Data Path Delay	cell: 4.572, 48.314%; route: 4.597, 48.579%; tC2Q: 0.294, 3.107%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.679, 100.000%

Path23

Path Summary:

Slack	0.541
Data Arrival Time	11.092
Data Required Time	11.634
From	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_h2c_engine/u_h2c_stream_if/m_axis_h2c_tkeep_tmp_23_s1
To	u_user_stream_if_monitor/h2c_one_packet_byte_cnt_28_s1
Launch Clk	sysclk:[R]
Latch Clk	sysclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sysclk
0.000	0.000	tCL	RR	13078	PLL_R[0]	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
1.679	1.679	tNET	RR	1	R36C110[1][B]	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_h2c_engine/u_h2c_stream_if/m_axis_h2c_tkeep_tmp_23_s1/CLK
1.973	0.294	tC2Q	RF	5	R36C110[1][B]	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_h2c_engine/u_h2c_stream_if/m_axis_h2c_tkeep_tmp_23_s1/Q
4.536	2.563	tNET	FF	1	R4C87[3][B]	u_user_stream_if_monitor/n2653_s63/I0
4.868	0.332	tINS	FR	2	R4C87[3][B]	u_user_stream_if_monitor/n2653_s63/F
5.273	0.404	tNET	RR	1	R2C91[3][B]	u_user_stream_if_monitor/n2652_s31/I0
5.689	0.417	tINS	RR	1	R2C91[3][B]	u_user_stream_if_monitor/n2652_s31/F
5.815	0.126	tNET	RR	1	R3C91[3][B]	u_user_stream_if_monitor/n2652_s38/I3
6.232	0.417	tINS	RR	2	R3C91[3][B]	u_user_stream_if_monitor/n2652_s38/F
6.360	0.128	tNET	RR	1	R4C91[3][B]	u_user_stream_if_monitor/n2651_s15/I1
6.777	0.417	tINS	RR	1	R4C91[3][B]	u_user_stream_if_monitor/n2651_s15/F
6.887	0.110	tNET	RR	2	R4C91[1][A]	u_user_stream_if_monitor/n2651_s10/I1
7.281	0.394	tINS	RR	1	R4C91[1][A]	u_user_stream_if_monitor/n2651_s10/COUT
7.281	0.000	tNET	RR	2	R4C91[1][B]	u_user_stream_if_monitor/n2650_s10/CIN
7.321	0.040	tINS	RR	1	R4C91[1][B]	u_user_stream_if_monitor/n2650_s10/COUT
7.321	0.000	tNET	RR	2	R4C91[2][A]	u_user_stream_if_monitor/n2649_s10/CIN
7.361	0.040	tINS	RR	1	R4C91[2][A]	u_user_stream_if_monitor/n2649_s10/COUT
7.361	0.000	tNET	RR	2	R4C91[2][B]	u_user_stream_if_monitor/n2648_s10/CIN
7.401	0.040	tINS	RR	1	R4C91[2][B]	u_user_stream_if_monitor/n2648_s10/COUT
7.401	0.000	tNET	RR	2	R4C92[0][A]	u_user_stream_if_monitor/n2647_s10/CIN
7.441	0.040	tINS	RR	1	R4C92[0][A]	u_user_stream_if_monitor/n2647_s10/COUT
7.441	0.000	tNET	RR	2	R4C92[0][B]	u_user_stream_if_monitor/n2646_s10/CIN
7.481	0.040	tINS	RR	1	R4C92[0][B]	u_user_stream_if_monitor/n2646_s10/COUT
7.481	0.000	tNET	RR	2	R4C92[1][A]	u_user_stream_if_monitor/n2645_s10/CIN
7.521	0.040	tINS	RR	1	R4C92[1][A]	u_user_stream_if_monitor/n2645_s10/COUT
7.521	0.000	tNET	RR	2	R4C92[1][B]	u_user_stream_if_monitor/n2644_s10/CIN
7.561	0.040	tINS	RR	1	R4C92[1][B]	u_user_stream_if_monitor/n2644_s10/COUT
7.561	0.000	tNET	RR	2	R4C92[2][A]	u_user_stream_if_monitor/n2643_s10/CIN
7.601	0.040	tINS	RR	1	R4C92[2][A]	u_user_stream_if_monitor/n2643_s10/COUT
7.601	0.000	tNET	RR	2	R4C92[2][B]	u_user_stream_if_monitor/n2642_s10/CIN
7.641	0.040	tINS	RR	1	R4C92[2][B]	u_user_stream_if_monitor/n2642_s10/COUT
7.641	0.000	tNET	RR	2	R4C93[0][A]	u_user_stream_if_monitor/n2641_s10/CIN
7.681	0.040	tINS	RR	1	R4C93[0][A]	u_user_stream_if_monitor/n2641_s10/COUT
7.681	0.000	tNET	RR	2	R4C93[0][B]	u_user_stream_if_monitor/n2640_s10/CIN
7.721	0.040	tINS	RR	1	R4C93[0][B]	u_user_stream_if_monitor/n2640_s10/COUT
7.721	0.000	tNET	RR	2	R4C93[1][A]	u_user_stream_if_monitor/n2639_s10/CIN
7.761	0.040	tINS	RR	1	R4C93[1][A]	u_user_stream_if_monitor/n2639_s10/COUT
7.761	0.000	tNET	RR	2	R4C93[1][B]	u_user_stream_if_monitor/n2638_s10/CIN
7.801	0.040	tINS	RR	1	R4C93[1][B]	u_user_stream_if_monitor/n2638_s10/COUT
7.801	0.000	tNET	RR	2	R4C93[2][A]	u_user_stream_if_monitor/n2637_s10/CIN
7.841	0.040	tINS	RR	1	R4C93[2][A]	u_user_stream_if_monitor/n2637_s10/COUT
7.841	0.000	tNET	RR	2	R4C93[2][B]	u_user_stream_if_monitor/n2636_s10/CIN
7.881	0.040	tINS	RR	1	R4C93[2][B]	u_user_stream_if_monitor/n2636_s10/COUT
7.881	0.000	tNET	RR	2	R4C94[0][A]	u_user_stream_if_monitor/n2635_s10/CIN
7.921	0.040	tINS	RR	1	R4C94[0][A]	u_user_stream_if_monitor/n2635_s10/COUT
7.921	0.000	tNET	RR	2	R4C94[0][B]	u_user_stream_if_monitor/n2634_s10/CIN
7.961	0.040	tINS	RR	1	R4C94[0][B]	u_user_stream_if_monitor/n2634_s10/COUT
7.961	0.000	tNET	RR	2	R4C94[1][A]	u_user_stream_if_monitor/n2633_s10/CIN
8.001	0.040	tINS	RR	1	R4C94[1][A]	u_user_stream_if_monitor/n2633_s10/COUT
8.001	0.000	tNET	RR	2	R4C94[1][B]	u_user_stream_if_monitor/n2632_s10/CIN
8.238	0.237	tINS	RR	1	R4C94[1][B]	u_user_stream_if_monitor/n2632_s10/SUM
8.624	0.386	tNET	RR	2	R3C94[1][B]	u_user_stream_if_monitor/n2632_s12/I1
9.018	0.394	tINS	RR	1	R3C94[1][B]	u_user_stream_if_monitor/n2632_s12/COUT
9.018	0.000	tNET	RR	2	R3C94[2][A]	u_user_stream_if_monitor/n2631_s12/CIN
9.058	0.040	tINS	RR	1	R3C94[2][A]	u_user_stream_if_monitor/n2631_s12/COUT
9.058	0.000	tNET	RR	2	R3C94[2][B]	u_user_stream_if_monitor/n2630_s12/CIN
9.098	0.040	tINS	RR	1	R3C94[2][B]	u_user_stream_if_monitor/n2630_s12/COUT
9.098	0.000	tNET	RR	2	R3C95[0][A]	u_user_stream_if_monitor/n2629_s12/CIN
9.138	0.040	tINS	RR	1	R3C95[0][A]	u_user_stream_if_monitor/n2629_s12/COUT
9.138	0.000	tNET	RR	2	R3C95[0][B]	u_user_stream_if_monitor/n2628_s12/CIN
9.178	0.040	tINS	RR	1	R3C95[0][B]	u_user_stream_if_monitor/n2628_s12/COUT
9.178	0.000	tNET	RR	2	R3C95[1][A]	u_user_stream_if_monitor/n2627_s12/CIN
9.218	0.040	tINS	RR	1	R3C95[1][A]	u_user_stream_if_monitor/n2627_s12/COUT
9.218	0.000	tNET	RR	2	R3C95[1][B]	u_user_stream_if_monitor/n2626_s12/CIN
9.455	0.237	tINS	RR	1	R3C95[1][B]	u_user_stream_if_monitor/n2626_s12/SUM
9.841	0.386	tNET	RR	2	R2C95[1][B]	u_user_stream_if_monitor/n2626_s14/I1
10.235	0.394	tINS	RR	1	R2C95[1][B]	u_user_stream_if_monitor/n2626_s14/COUT
10.235	0.000	tNET	RR	2	R2C95[2][A]	u_user_stream_if_monitor/n2625_s14/CIN
10.430	0.195	tINS	RR	1	R2C95[2][A]	u_user_stream_if_monitor/n2625_s14/SUM
10.860	0.430	tNET	RR	1	R5C94[3][A]	u_user_stream_if_monitor/n2689_s2/I1
11.092	0.232	tINS	RF	1	R5C94[3][A]	u_user_stream_if_monitor/n2689_s2/F
11.092	0.000	tNET	FF	1	R5C94[3][A]	u_user_stream_if_monitor/h2c_one_packet_byte_cnt_28_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					sysclk
10.000	0.000	tCL	RR	13078	PLL_R[0]	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
11.679	1.679	tNET	RR	1	R5C94[3][A]	u_user_stream_if_monitor/h2c_one_packet_byte_cnt_28_s1/CLK
11.634	-0.046	tSu		1	R5C94[3][A]	u_user_stream_if_monitor/h2c_one_packet_byte_cnt_28_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	14
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.679, 100.000%
Arrival Data Path Delay	cell: 4.586, 48.720%; route: 4.533, 48.157%; tC2Q: 0.294, 3.123%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.679, 100.000%

Path24

Path Summary:

Slack	0.545
Data Arrival Time	11.091
Data Required Time	11.636
From	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_h2c_engine/u_h2c_stream_if/m_axis_h2c_tkeep_tmp_13_s1
To	u_user_stream_if_monitor/h2c_one_packet_byte_cnt_16_s1
Launch Clk	sysclk:[R]
Latch Clk	sysclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sysclk
0.000	0.000	tCL	RR	13078	PLL_R[0]	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
1.672	1.672	tNET	RR	1	R39C111[2][A]	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_h2c_engine/u_h2c_stream_if/m_axis_h2c_tkeep_tmp_13_s1/CLK
1.966	0.294	tC2Q	RF	5	R39C111[2][A]	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_h2c_engine/u_h2c_stream_if/m_axis_h2c_tkeep_tmp_13_s1/Q
4.371	2.405	tNET	FF	1	R4C93[3][B]	u_user_stream_if_monitor/n2653_s61/I0
4.703	0.332	tINS	FR	3	R4C93[3][B]	u_user_stream_if_monitor/n2653_s61/F
4.983	0.280	tNET	RR	1	R2C92[3][A]	u_user_stream_if_monitor/n2652_s36/I1
5.215	0.232	tINS	RF	1	R2C92[3][A]	u_user_stream_if_monitor/n2652_s36/F
5.329	0.114	tNET	FF	1	R3C92[3][A]	u_user_stream_if_monitor/n2652_s33/I2
5.746	0.417	tINS	FR	1	R3C92[3][A]	u_user_stream_if_monitor/n2652_s33/F
5.748	0.002	tNET	RR	1	R3C92[3][B]	u_user_stream_if_monitor/n2652_s39/I3
6.080	0.332	tINS	RR	2	R3C92[3][B]	u_user_stream_if_monitor/n2652_s39/F
6.208	0.128	tNET	RR	1	R4C92[3][B]	u_user_stream_if_monitor/n2651_s16/I1
6.625	0.417	tINS	RR	1	R4C92[3][B]	u_user_stream_if_monitor/n2651_s16/F
6.933	0.308	tNET	RR	2	R3C90[1][A]	u_user_stream_if_monitor/n2651_s11/I0
7.383	0.450	tINS	RF	1	R3C90[1][A]	u_user_stream_if_monitor/n2651_s11/COUT
7.869	0.486	tNET	FF	2	R3C91[1][B]	u_user_stream_if_monitor/n2650_s12/I1
8.263	0.394	tINS	FR	1	R3C91[1][B]	u_user_stream_if_monitor/n2650_s12/COUT
8.263	0.000	tNET	RR	2	R3C91[2][A]	u_user_stream_if_monitor/n2649_s12/CIN
8.303	0.040	tINS	RR	1	R3C91[2][A]	u_user_stream_if_monitor/n2649_s12/COUT
8.303	0.000	tNET	RR	2	R3C91[2][B]	u_user_stream_if_monitor/n2648_s12/CIN
8.343	0.040	tINS	RR	1	R3C91[2][B]	u_user_stream_if_monitor/n2648_s12/COUT
8.343	0.000	tNET	RR	2	R3C92[0][A]	u_user_stream_if_monitor/n2647_s12/CIN
8.383	0.040	tINS	RR	1	R3C92[0][A]	u_user_stream_if_monitor/n2647_s12/COUT
8.383	0.000	tNET	RR	2	R3C92[0][B]	u_user_stream_if_monitor/n2646_s12/CIN
8.423	0.040	tINS	RR	1	R3C92[0][B]	u_user_stream_if_monitor/n2646_s12/COUT
8.423	0.000	tNET	RR	2	R3C92[1][A]	u_user_stream_if_monitor/n2645_s12/CIN
8.463	0.040	tINS	RR	1	R3C92[1][A]	u_user_stream_if_monitor/n2645_s12/COUT
8.463	0.000	tNET	RR	2	R3C92[1][B]	u_user_stream_if_monitor/n2644_s12/CIN
8.700	0.237	tINS	RR	1	R3C92[1][B]	u_user_stream_if_monitor/n2644_s12/SUM
9.116	0.416	tNET	RR	2	R2C92[1][B]	u_user_stream_if_monitor/n2644_s14/I1
9.510	0.394	tINS	RR	1	R2C92[1][B]	u_user_stream_if_monitor/n2644_s14/COUT
9.510	0.000	tNET	RR	2	R2C92[2][A]	u_user_stream_if_monitor/n2643_s14/CIN
9.550	0.040	tINS	RR	1	R2C92[2][A]	u_user_stream_if_monitor/n2643_s14/COUT
9.550	0.000	tNET	RR	2	R2C92[2][B]	u_user_stream_if_monitor/n2642_s14/CIN
9.590	0.040	tINS	RR	1	R2C92[2][B]	u_user_stream_if_monitor/n2642_s14/COUT
9.590	0.000	tNET	RR	2	R2C93[0][A]	u_user_stream_if_monitor/n2641_s14/CIN
9.630	0.040	tINS	RR	1	R2C93[0][A]	u_user_stream_if_monitor/n2641_s14/COUT
9.630	0.000	tNET	RR	2	R2C93[0][B]	u_user_stream_if_monitor/n2640_s14/CIN
9.670	0.040	tINS	RR	1	R2C93[0][B]	u_user_stream_if_monitor/n2640_s14/COUT
9.670	0.000	tNET	RR	2	R2C93[1][A]	u_user_stream_if_monitor/n2639_s14/CIN
9.710	0.040	tINS	RR	1	R2C93[1][A]	u_user_stream_if_monitor/n2639_s14/COUT
9.710	0.000	tNET	RR	2	R2C93[1][B]	u_user_stream_if_monitor/n2638_s14/CIN
9.750	0.040	tINS	RR	1	R2C93[1][B]	u_user_stream_if_monitor/n2638_s14/COUT
9.750	0.000	tNET	RR	2	R2C93[2][A]	u_user_stream_if_monitor/n2637_s14/CIN
9.945	0.195	tINS	RR	1	R2C93[2][A]	u_user_stream_if_monitor/n2637_s14/SUM
10.359	0.414	tNET	RR	1	R6C93[3][B]	u_user_stream_if_monitor/n2701_s3/I0
10.691	0.332	tINS	RR	1	R6C93[3][B]	u_user_stream_if_monitor/n2701_s3/F
10.693	0.002	tNET	RR	1	R6C93[3][A]	u_user_stream_if_monitor/n2701_s5/I0
11.091	0.398	tINS	RR	1	R6C93[3][A]	u_user_stream_if_monitor/n2701_s5/F
11.091	0.000	tNET	RR	1	R6C93[3][A]	u_user_stream_if_monitor/h2c_one_packet_byte_cnt_16_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					sysclk
10.000	0.000	tCL	RR	13078	PLL_R[0]	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
11.687	1.687	tNET	RR	1	R6C93[3][A]	u_user_stream_if_monitor/h2c_one_packet_byte_cnt_16_s1/CLK
11.636	-0.051	tSu		1	R6C93[3][A]	u_user_stream_if_monitor/h2c_one_packet_byte_cnt_16_s1

Path Statistics:

Clock Skew	0.015
Setup Relationship	10.000
Logic Level	15
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.672, 100.000%
Arrival Data Path Delay	cell: 4.570, 48.519%; route: 4.555, 48.360%; tC2Q: 0.294, 3.121%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.687, 100.000%

Path25

Path Summary:

Slack	0.547
Data Arrival Time	11.089
Data Required Time	11.636
From	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_h2c_engine/u_h2c_stream_if/m_axis_h2c_tkeep_tmp_13_s1
To	u_user_stream_if_monitor/h2c_one_packet_byte_cnt_18_s1
Launch Clk	sysclk:[R]
Latch Clk	sysclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sysclk
0.000	0.000	tCL	RR	13078	PLL_R[0]	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
1.672	1.672	tNET	RR	1	R39C111[2][A]	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_h2c_engine/u_h2c_stream_if/m_axis_h2c_tkeep_tmp_13_s1/CLK
1.966	0.294	tC2Q	RF	5	R39C111[2][A]	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_h2c_engine/u_h2c_stream_if/m_axis_h2c_tkeep_tmp_13_s1/Q
4.371	2.405	tNET	FF	1	R4C93[3][B]	u_user_stream_if_monitor/n2653_s61/I0
4.703	0.332	tINS	FR	3	R4C93[3][B]	u_user_stream_if_monitor/n2653_s61/F
4.983	0.280	tNET	RR	1	R2C92[3][A]	u_user_stream_if_monitor/n2652_s36/I1
5.215	0.232	tINS	RF	1	R2C92[3][A]	u_user_stream_if_monitor/n2652_s36/F
5.329	0.114	tNET	FF	1	R3C92[3][A]	u_user_stream_if_monitor/n2652_s33/I2
5.746	0.417	tINS	FR	1	R3C92[3][A]	u_user_stream_if_monitor/n2652_s33/F
5.748	0.002	tNET	RR	1	R3C92[3][B]	u_user_stream_if_monitor/n2652_s39/I3
6.080	0.332	tINS	RR	2	R3C92[3][B]	u_user_stream_if_monitor/n2652_s39/F
6.208	0.128	tNET	RR	1	R4C92[3][B]	u_user_stream_if_monitor/n2651_s16/I1
6.625	0.417	tINS	RR	1	R4C92[3][B]	u_user_stream_if_monitor/n2651_s16/F
6.933	0.308	tNET	RR	2	R3C90[1][A]	u_user_stream_if_monitor/n2651_s11/I0
7.383	0.450	tINS	RF	1	R3C90[1][A]	u_user_stream_if_monitor/n2651_s11/COUT
7.869	0.486	tNET	FF	2	R3C91[1][B]	u_user_stream_if_monitor/n2650_s12/I1
8.263	0.394	tINS	FR	1	R3C91[1][B]	u_user_stream_if_monitor/n2650_s12/COUT
8.263	0.000	tNET	RR	2	R3C91[2][A]	u_user_stream_if_monitor/n2649_s12/CIN
8.303	0.040	tINS	RR	1	R3C91[2][A]	u_user_stream_if_monitor/n2649_s12/COUT
8.303	0.000	tNET	RR	2	R3C91[2][B]	u_user_stream_if_monitor/n2648_s12/CIN
8.343	0.040	tINS	RR	1	R3C91[2][B]	u_user_stream_if_monitor/n2648_s12/COUT
8.343	0.000	tNET	RR	2	R3C92[0][A]	u_user_stream_if_monitor/n2647_s12/CIN
8.383	0.040	tINS	RR	1	R3C92[0][A]	u_user_stream_if_monitor/n2647_s12/COUT
8.383	0.000	tNET	RR	2	R3C92[0][B]	u_user_stream_if_monitor/n2646_s12/CIN
8.423	0.040	tINS	RR	1	R3C92[0][B]	u_user_stream_if_monitor/n2646_s12/COUT
8.423	0.000	tNET	RR	2	R3C92[1][A]	u_user_stream_if_monitor/n2645_s12/CIN
8.463	0.040	tINS	RR	1	R3C92[1][A]	u_user_stream_if_monitor/n2645_s12/COUT
8.463	0.000	tNET	RR	2	R3C92[1][B]	u_user_stream_if_monitor/n2644_s12/CIN
8.700	0.237	tINS	RR	1	R3C92[1][B]	u_user_stream_if_monitor/n2644_s12/SUM
9.116	0.416	tNET	RR	2	R2C92[1][B]	u_user_stream_if_monitor/n2644_s14/I1
9.510	0.394	tINS	RR	1	R2C92[1][B]	u_user_stream_if_monitor/n2644_s14/COUT
9.510	0.000	tNET	RR	2	R2C92[2][A]	u_user_stream_if_monitor/n2643_s14/CIN
9.550	0.040	tINS	RR	1	R2C92[2][A]	u_user_stream_if_monitor/n2643_s14/COUT
9.550	0.000	tNET	RR	2	R2C92[2][B]	u_user_stream_if_monitor/n2642_s14/CIN
9.590	0.040	tINS	RR	1	R2C92[2][B]	u_user_stream_if_monitor/n2642_s14/COUT
9.590	0.000	tNET	RR	2	R2C93[0][A]	u_user_stream_if_monitor/n2641_s14/CIN
9.630	0.040	tINS	RR	1	R2C93[0][A]	u_user_stream_if_monitor/n2641_s14/COUT
9.630	0.000	tNET	RR	2	R2C93[0][B]	u_user_stream_if_monitor/n2640_s14/CIN
9.670	0.040	tINS	RR	1	R2C93[0][B]	u_user_stream_if_monitor/n2640_s14/COUT
9.670	0.000	tNET	RR	2	R2C93[1][A]	u_user_stream_if_monitor/n2639_s14/CIN
9.710	0.040	tINS	RR	1	R2C93[1][A]	u_user_stream_if_monitor/n2639_s14/COUT
9.710	0.000	tNET	RR	2	R2C93[1][B]	u_user_stream_if_monitor/n2638_s14/CIN
9.750	0.040	tINS	RR	1	R2C93[1][B]	u_user_stream_if_monitor/n2638_s14/COUT
9.750	0.000	tNET	RR	2	R2C93[2][A]	u_user_stream_if_monitor/n2637_s14/CIN
9.790	0.040	tINS	RR	1	R2C93[2][A]	u_user_stream_if_monitor/n2637_s14/COUT
9.790	0.000	tNET	RR	2	R2C93[2][B]	u_user_stream_if_monitor/n2636_s14/CIN
9.830	0.040	tINS	RR	1	R2C93[2][B]	u_user_stream_if_monitor/n2636_s14/COUT
9.830	0.000	tNET	RR	2	R2C94[0][A]	u_user_stream_if_monitor/n2635_s14/CIN
10.025	0.195	tINS	RR	1	R2C94[0][A]	u_user_stream_if_monitor/n2635_s14/SUM
10.455	0.430	tNET	RR	1	R5C93[3][B]	u_user_stream_if_monitor/n2699_s3/I0
10.687	0.232	tINS	RF	1	R5C93[3][B]	u_user_stream_if_monitor/n2699_s3/F
10.691	0.004	tNET	FF	1	R5C93[3][A]	u_user_stream_if_monitor/n2699_s7/I0
11.089	0.398	tINS	FR	1	R5C93[3][A]	u_user_stream_if_monitor/n2699_s7/F
11.089	0.000	tNET	RR	1	R5C93[3][A]	u_user_stream_if_monitor/h2c_one_packet_byte_cnt_18_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					sysclk
10.000	0.000	tCL	RR	13078	PLL_R[0]	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
11.687	1.687	tNET	RR	1	R5C93[3][A]	u_user_stream_if_monitor/h2c_one_packet_byte_cnt_18_s1/CLK
11.636	-0.051	tSu		1	R5C93[3][A]	u_user_stream_if_monitor/h2c_one_packet_byte_cnt_18_s1

Path Statistics:

Clock Skew	0.015
Setup Relationship	10.000
Logic Level	15
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.672, 100.000%
Arrival Data Path Delay	cell: 4.550, 48.317%; route: 4.573, 48.561%; tC2Q: 0.294, 3.122%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.687, 100.000%

Hold Analysis Report

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	0.044
Data Arrival Time	0.951
Data Required Time	0.907
From	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_c2h_descriptor/descriptor_fifo_wrdata_reg_239_s0
To	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_descriptor_fifo/mem_mem_0_0_s
Launch Clk	sysclk:[R]
Latch Clk	sysclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sysclk
0.000	0.000	tCL	RR	13078	PLL_R[0]	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
0.669	0.669	tNET	RR	1	R40C66[0][B]	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_c2h_descriptor/descriptor_fifo_wrdata_reg_239_s0/CLK
0.813	0.144	tC2Q	RR	1	R40C66[0][B]	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_c2h_descriptor/descriptor_fifo_wrdata_reg_239_s0/Q
0.951	0.138	tNET	RR	1	BSRAM_R38[13]	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_descriptor_fifo/mem_mem_0_0_s/DI[15]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sysclk
0.000	0.000	tCL	RR	13078	PLL_R[0]	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
0.870	0.870	tNET	RR	1	BSRAM_R38[13]	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_descriptor_fifo/mem_mem_0_0_s/CLKA
0.907	0.037	tHld		1	BSRAM_R38[13]	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_descriptor_fifo/mem_mem_0_0_s

Path Statistics:

Clock Skew	0.201
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.669, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.138, 48.936%; tC2Q: 0.144, 51.064%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.870, 100.000%

Path2

Path Summary:

Slack	0.044
Data Arrival Time	0.951
Data Required Time	0.907
From	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_c2h_descriptor/descriptor_fifo_wrdata_reg_237_s0
To	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_descriptor_fifo/mem_mem_0_0_s
Launch Clk	sysclk:[R]
Latch Clk	sysclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sysclk
0.000	0.000	tCL	RR	13078	PLL_R[0]	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
0.669	0.669	tNET	RR	1	R39C66[1][A]	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_c2h_descriptor/descriptor_fifo_wrdata_reg_237_s0/CLK
0.813	0.144	tC2Q	RR	1	R39C66[1][A]	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_c2h_descriptor/descriptor_fifo_wrdata_reg_237_s0/Q
0.951	0.138	tNET	RR	1	BSRAM_R38[13]	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_descriptor_fifo/mem_mem_0_0_s/DI[13]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sysclk
0.000	0.000	tCL	RR	13078	PLL_R[0]	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
0.870	0.870	tNET	RR	1	BSRAM_R38[13]	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_descriptor_fifo/mem_mem_0_0_s/CLKA
0.907	0.037	tHld		1	BSRAM_R38[13]	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_descriptor_fifo/mem_mem_0_0_s

Path Statistics:

Clock Skew	0.201
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.669, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.138, 48.936%; tC2Q: 0.144, 51.064%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.870, 100.000%

Path3

Path Summary:

Slack	0.044
Data Arrival Time	0.951
Data Required Time	0.907
From	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_c2h_descriptor/descriptor_fifo_wrdata_reg_236_s0
To	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_descriptor_fifo/mem_mem_0_0_s
Launch Clk	sysclk:[R]
Latch Clk	sysclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sysclk
0.000	0.000	tCL	RR	13078	PLL_R[0]	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
0.669	0.669	tNET	RR	1	R39C66[1][B]	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_c2h_descriptor/descriptor_fifo_wrdata_reg_236_s0/CLK
0.813	0.144	tC2Q	RR	1	R39C66[1][B]	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_c2h_descriptor/descriptor_fifo_wrdata_reg_236_s0/Q
0.951	0.138	tNET	RR	1	BSRAM_R38[13]	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_descriptor_fifo/mem_mem_0_0_s/DI[12]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sysclk
0.000	0.000	tCL	RR	13078	PLL_R[0]	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
0.870	0.870	tNET	RR	1	BSRAM_R38[13]	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_descriptor_fifo/mem_mem_0_0_s/CLKA
0.907	0.037	tHld		1	BSRAM_R38[13]	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_descriptor_fifo/mem_mem_0_0_s

Path Statistics:

Clock Skew	0.201
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.669, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.138, 48.936%; tC2Q: 0.144, 51.064%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.870, 100.000%

Path4

Path Summary:

Slack	0.044
Data Arrival Time	0.951
Data Required Time	0.907
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_46_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s
Launch Clk	sysclk:[R]
Latch Clk	sysclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sysclk
0.000	0.000	tCL	RR	13078	PLL_R[0]	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
0.669	0.669	tNET	RR	1	R39C18[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_46_s0/CLK
0.813	0.144	tC2Q	RR	1	R39C18[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_46_s0/Q
0.951	0.138	tNET	RR	1	BSRAM_R38[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[10]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sysclk
0.000	0.000	tCL	RR	13078	PLL_R[0]	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
0.870	0.870	tNET	RR	1	BSRAM_R38[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CLKA
0.907	0.037	tHld		1	BSRAM_R38[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s

Path Statistics:

Clock Skew	0.201
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.669, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.138, 48.936%; tC2Q: 0.144, 51.064%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.870, 100.000%

Path5

Path Summary:

Slack	0.048
Data Arrival Time	0.955
Data Required Time	0.907
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_38_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s
Launch Clk	sysclk:[R]
Latch Clk	sysclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sysclk
0.000	0.000	tCL	RR	13078	PLL_R[0]	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
0.673	0.673	tNET	RR	1	R39C17[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_38_s0/CLK
0.817	0.144	tC2Q	RR	1	R39C17[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_38_s0/Q
0.955	0.138	tNET	RR	1	BSRAM_R38[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[2]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sysclk
0.000	0.000	tCL	RR	13078	PLL_R[0]	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
0.870	0.870	tNET	RR	1	BSRAM_R38[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CLKA
0.907	0.037	tHld		1	BSRAM_R38[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s

Path Statistics:

Clock Skew	0.197
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.673, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.138, 48.936%; tC2Q: 0.144, 51.064%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.870, 100.000%

Path6

Path Summary:

Slack	0.119
Data Arrival Time	1.026
Data Required Time	0.907
From	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_c2h_descriptor/descriptor_fifo_wrdata_reg_234_s0
To	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_descriptor_fifo/mem_mem_0_0_s
Launch Clk	sysclk:[R]
Latch Clk	sysclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sysclk
0.000	0.000	tCL	RR	13078	PLL_R[0]	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
0.669	0.669	tNET	RR	1	R40C66[3][A]	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_c2h_descriptor/descriptor_fifo_wrdata_reg_234_s0/CLK
0.813	0.144	tC2Q	RR	1	R40C66[3][A]	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_c2h_descriptor/descriptor_fifo_wrdata_reg_234_s0/Q
1.026	0.213	tNET	RR	1	BSRAM_R38[13]	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_descriptor_fifo/mem_mem_0_0_s/DI[10]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sysclk
0.000	0.000	tCL	RR	13078	PLL_R[0]	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
0.870	0.870	tNET	RR	1	BSRAM_R38[13]	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_descriptor_fifo/mem_mem_0_0_s/CLKA
0.907	0.037	tHld		1	BSRAM_R38[13]	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_descriptor_fifo/mem_mem_0_0_s

Path Statistics:

Clock Skew	0.201
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.669, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.213, 59.664%; tC2Q: 0.144, 40.336%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.870, 100.000%

Path7

Path Summary:

Slack	0.133
Data Arrival Time	1.040
Data Required Time	0.907
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/gowin_add_SDPX9B_mem_mem_0_8_s
Launch Clk	sysclk:[R]
Latch Clk	sysclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sysclk
0.000	0.000	tCL	RR	13078	PLL_R[0]	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
0.673	0.673	tNET	RR	1	R40C41[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLK
0.817	0.144	tC2Q	RR	34	R40C41[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/Q
1.040	0.223	tNET	RR	1	BSRAM_R38[8][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/gowin_add_SDPX9B_mem_mem_0_8_s/ADA[10]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sysclk
0.000	0.000	tCL	RR	13078	PLL_R[0]	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
0.870	0.870	tNET	RR	1	BSRAM_R38[8][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/gowin_add_SDPX9B_mem_mem_0_8_s/CLKA
0.907	0.037	tHld		1	BSRAM_R38[8][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/gowin_add_SDPX9B_mem_mem_0_8_s

Path Statistics:

Clock Skew	0.197
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.673, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.223, 60.763%; tC2Q: 0.144, 39.237%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.870, 100.000%

Path8

Path Summary:

Slack	0.134
Data Arrival Time	1.045
Data Required Time	0.911
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_162_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/gowin_add_SDPX9B_mem_mem_0_4_s
Launch Clk	sysclk:[R]
Latch Clk	sysclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sysclk
0.000	0.000	tCL	RR	13078	PLL_R[0]	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
0.673	0.673	tNET	RR	1	R40C33[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_162_s0/CLK
0.817	0.144	tC2Q	RR	1	R40C33[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_162_s0/Q
1.045	0.228	tNET	RR	1	BSRAM_R38[6][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/gowin_add_SDPX9B_mem_mem_0_4_s/DI[0]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sysclk
0.000	0.000	tCL	RR	13078	PLL_R[0]	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
0.874	0.874	tNET	RR	1	BSRAM_R38[6][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/gowin_add_SDPX9B_mem_mem_0_4_s/CLKA
0.911	0.037	tHld		1	BSRAM_R38[6][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/gowin_add_SDPX9B_mem_mem_0_4_s

Path Statistics:

Clock Skew	0.201
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.673, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.228, 61.290%; tC2Q: 0.144, 38.710%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.874, 100.000%

Path9

Path Summary:

Slack	0.134
Data Arrival Time	1.041
Data Required Time	0.907
From	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_c2h_descriptor/descriptor_fifo_wrdata_reg_238_s0
To	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_descriptor_fifo/mem_mem_0_0_s
Launch Clk	sysclk:[R]
Latch Clk	sysclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sysclk
0.000	0.000	tCL	RR	13078	PLL_R[0]	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
0.669	0.669	tNET	RR	1	R40C66[2][A]	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_c2h_descriptor/descriptor_fifo_wrdata_reg_238_s0/CLK
0.813	0.144	tC2Q	RR	1	R40C66[2][A]	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_c2h_descriptor/descriptor_fifo_wrdata_reg_238_s0/Q
1.041	0.228	tNET	RR	1	BSRAM_R38[13]	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_descriptor_fifo/mem_mem_0_0_s/DI[14]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sysclk
0.000	0.000	tCL	RR	13078	PLL_R[0]	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
0.870	0.870	tNET	RR	1	BSRAM_R38[13]	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_descriptor_fifo/mem_mem_0_0_s/CLKA
0.907	0.037	tHld		1	BSRAM_R38[13]	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_descriptor_fifo/mem_mem_0_0_s

Path Statistics:

Clock Skew	0.201
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.669, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.228, 61.290%; tC2Q: 0.144, 38.710%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.870, 100.000%

Path10

Path Summary:

Slack	0.134
Data Arrival Time	1.041
Data Required Time	0.907
From	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_c2h_descriptor/descriptor_fifo_wrdata_reg_235_s0
To	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_descriptor_fifo/mem_mem_0_0_s
Launch Clk	sysclk:[R]
Latch Clk	sysclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sysclk
0.000	0.000	tCL	RR	13078	PLL_R[0]	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
0.669	0.669	tNET	RR	1	R40C66[2][B]	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_c2h_descriptor/descriptor_fifo_wrdata_reg_235_s0/CLK
0.813	0.144	tC2Q	RR	1	R40C66[2][B]	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_c2h_descriptor/descriptor_fifo_wrdata_reg_235_s0/Q
1.041	0.228	tNET	RR	1	BSRAM_R38[13]	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_descriptor_fifo/mem_mem_0_0_s/DI[11]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sysclk
0.000	0.000	tCL	RR	13078	PLL_R[0]	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
0.870	0.870	tNET	RR	1	BSRAM_R38[13]	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_descriptor_fifo/mem_mem_0_0_s/CLKA
0.907	0.037	tHld		1	BSRAM_R38[13]	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_descriptor_fifo/mem_mem_0_0_s

Path Statistics:

Clock Skew	0.201
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.669, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.228, 61.290%; tC2Q: 0.144, 38.710%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.870, 100.000%

Path11

Path Summary:

Slack	0.134
Data Arrival Time	1.041
Data Required Time	0.907
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_39_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s
Launch Clk	sysclk:[R]
Latch Clk	sysclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sysclk
0.000	0.000	tCL	RR	13078	PLL_R[0]	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
0.669	0.669	tNET	RR	1	R39C18[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_39_s0/CLK
0.813	0.144	tC2Q	RR	1	R39C18[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_39_s0/Q
1.041	0.228	tNET	RR	1	BSRAM_R38[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[3]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sysclk
0.000	0.000	tCL	RR	13078	PLL_R[0]	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
0.870	0.870	tNET	RR	1	BSRAM_R38[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CLKA
0.907	0.037	tHld		1	BSRAM_R38[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s

Path Statistics:

Clock Skew	0.201
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.669, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.228, 61.290%; tC2Q: 0.144, 38.710%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.870, 100.000%

Path12

Path Summary:

Slack	0.142
Data Arrival Time	1.053
Data Required Time	0.911
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/gowin_add_SDPX9B_mem_mem_0_10_s
Launch Clk	sysclk:[R]
Latch Clk	sysclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sysclk
0.000	0.000	tCL	RR	13078	PLL_R[0]	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
0.669	0.669	tNET	RR	1	R40C42[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLK
0.813	0.144	tC2Q	RR	33	R40C42[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/Q
1.053	0.240	tNET	RR	1	BSRAM_R38[8][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/gowin_add_SDPX9B_mem_mem_0_10_s/ADA[8]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sysclk
0.000	0.000	tCL	RR	13078	PLL_R[0]	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
0.874	0.874	tNET	RR	1	BSRAM_R38[8][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/gowin_add_SDPX9B_mem_mem_0_10_s/CLKA
0.911	0.037	tHld		1	BSRAM_R38[8][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/gowin_add_SDPX9B_mem_mem_0_10_s

Path Statistics:

Clock Skew	0.205
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.669, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.240, 62.500%; tC2Q: 0.144, 37.500%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.874, 100.000%

Path13

Path Summary:

Slack	0.144
Data Arrival Time	1.051
Data Required Time	0.907
From	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_c2h_descriptor/descriptor_fifo_wrdata_reg_226_s0
To	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_descriptor_fifo/mem_mem_0_0_s
Launch Clk	sysclk:[R]
Latch Clk	sysclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sysclk
0.000	0.000	tCL	RR	13078	PLL_R[0]	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
0.673	0.673	tNET	RR	1	R39C67[0][B]	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_c2h_descriptor/descriptor_fifo_wrdata_reg_226_s0/CLK
0.817	0.144	tC2Q	RR	1	R39C67[0][B]	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_c2h_descriptor/descriptor_fifo_wrdata_reg_226_s0/Q
1.051	0.234	tNET	RR	1	BSRAM_R38[13]	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_descriptor_fifo/mem_mem_0_0_s/DI[2]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sysclk
0.000	0.000	tCL	RR	13078	PLL_R[0]	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
0.870	0.870	tNET	RR	1	BSRAM_R38[13]	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_descriptor_fifo/mem_mem_0_0_s/CLKA
0.907	0.037	tHld		1	BSRAM_R38[13]	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_descriptor_fifo/mem_mem_0_0_s

Path Statistics:

Clock Skew	0.197
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.673, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.234, 61.905%; tC2Q: 0.144, 38.095%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.870, 100.000%

Path14

Path Summary:

Slack	0.144
Data Arrival Time	1.051
Data Required Time	0.907
From	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_c2h_descriptor/descriptor_fifo_wrdata_reg_225_s0
To	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_descriptor_fifo/mem_mem_0_0_s
Launch Clk	sysclk:[R]
Latch Clk	sysclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sysclk
0.000	0.000	tCL	RR	13078	PLL_R[0]	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
0.673	0.673	tNET	RR	1	R40C67[0][A]	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_c2h_descriptor/descriptor_fifo_wrdata_reg_225_s0/CLK
0.817	0.144	tC2Q	RR	1	R40C67[0][A]	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_c2h_descriptor/descriptor_fifo_wrdata_reg_225_s0/Q
1.051	0.234	tNET	RR	1	BSRAM_R38[13]	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_descriptor_fifo/mem_mem_0_0_s/DI[1]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sysclk
0.000	0.000	tCL	RR	13078	PLL_R[0]	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
0.870	0.870	tNET	RR	1	BSRAM_R38[13]	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_descriptor_fifo/mem_mem_0_0_s/CLKA
0.907	0.037	tHld		1	BSRAM_R38[13]	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_descriptor_fifo/mem_mem_0_0_s

Path Statistics:

Clock Skew	0.197
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.673, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.234, 61.905%; tC2Q: 0.144, 38.095%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.870, 100.000%

Path15

Path Summary:

Slack	0.144
Data Arrival Time	1.051
Data Required Time	0.907
From	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_c2h_descriptor/descriptor_fifo_wrdata_reg_224_s0
To	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_descriptor_fifo/mem_mem_0_0_s
Launch Clk	sysclk:[R]
Latch Clk	sysclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sysclk
0.000	0.000	tCL	RR	13078	PLL_R[0]	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
0.673	0.673	tNET	RR	1	R39C67[2][A]	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_c2h_descriptor/descriptor_fifo_wrdata_reg_224_s0/CLK
0.817	0.144	tC2Q	RR	1	R39C67[2][A]	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_c2h_descriptor/descriptor_fifo_wrdata_reg_224_s0/Q
1.051	0.234	tNET	RR	1	BSRAM_R38[13]	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_descriptor_fifo/mem_mem_0_0_s/DI[0]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sysclk
0.000	0.000	tCL	RR	13078	PLL_R[0]	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
0.870	0.870	tNET	RR	1	BSRAM_R38[13]	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_descriptor_fifo/mem_mem_0_0_s/CLKA
0.907	0.037	tHld		1	BSRAM_R38[13]	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_descriptor_fifo/mem_mem_0_0_s

Path Statistics:

Clock Skew	0.197
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.673, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.234, 61.905%; tC2Q: 0.144, 38.095%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.870, 100.000%

Path16

Path Summary:

Slack	0.144
Data Arrival Time	1.051
Data Required Time	0.907
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_42_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s
Launch Clk	sysclk:[R]
Latch Clk	sysclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sysclk
0.000	0.000	tCL	RR	13078	PLL_R[0]	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
0.673	0.673	tNET	RR	1	R39C19[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_42_s0/CLK
0.817	0.144	tC2Q	RR	1	R39C19[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_42_s0/Q
1.051	0.234	tNET	RR	1	BSRAM_R38[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[6]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sysclk
0.000	0.000	tCL	RR	13078	PLL_R[0]	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
0.870	0.870	tNET	RR	1	BSRAM_R38[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CLKA
0.907	0.037	tHld		1	BSRAM_R38[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s

Path Statistics:

Clock Skew	0.197
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.673, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.234, 61.905%; tC2Q: 0.144, 38.095%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.870, 100.000%

Path17

Path Summary:

Slack	0.147
Data Arrival Time	1.054
Data Required Time	0.907
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/gowin_add_SDPX9B_mem_mem_0_8_s
Launch Clk	sysclk:[R]
Latch Clk	sysclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sysclk
0.000	0.000	tCL	RR	13078	PLL_R[0]	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
0.669	0.669	tNET	RR	1	R39C42[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLK
0.813	0.144	tC2Q	RR	35	R39C42[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/Q
1.054	0.241	tNET	RR	1	BSRAM_R38[8][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/gowin_add_SDPX9B_mem_mem_0_8_s/ADA[9]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sysclk
0.000	0.000	tCL	RR	13078	PLL_R[0]	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
0.870	0.870	tNET	RR	1	BSRAM_R38[8][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/gowin_add_SDPX9B_mem_mem_0_8_s/CLKA
0.907	0.037	tHld		1	BSRAM_R38[8][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/gowin_add_SDPX9B_mem_mem_0_8_s

Path Statistics:

Clock Skew	0.201
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.669, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.241, 62.597%; tC2Q: 0.144, 37.403%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.870, 100.000%

Path18

Path Summary:

Slack	0.148
Data Arrival Time	1.059
Data Required Time	0.911
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/gowin_add_SDPX9B_mem_mem_0_10_s
Launch Clk	sysclk:[R]
Latch Clk	sysclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sysclk
0.000	0.000	tCL	RR	13078	PLL_R[0]	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
0.669	0.669	tNET	RR	1	R39C42[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/CLK
0.813	0.144	tC2Q	RR	33	R39C42[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/Q
1.059	0.246	tNET	RR	1	BSRAM_R38[8][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/gowin_add_SDPX9B_mem_mem_0_10_s/ADA[11]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sysclk
0.000	0.000	tCL	RR	13078	PLL_R[0]	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
0.874	0.874	tNET	RR	1	BSRAM_R38[8][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/gowin_add_SDPX9B_mem_mem_0_10_s/CLKA
0.911	0.037	tHld		1	BSRAM_R38[8][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/gowin_add_SDPX9B_mem_mem_0_10_s

Path Statistics:

Clock Skew	0.205
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.669, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.246, 63.077%; tC2Q: 0.144, 36.923%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.874, 100.000%

Path19

Path Summary:

Slack	0.148
Data Arrival Time	1.055
Data Required Time	0.907
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/gowin_add_SDPX9B_mem_mem_0_8_s
Launch Clk	sysclk:[R]
Latch Clk	sysclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sysclk
0.000	0.000	tCL	RR	13078	PLL_R[0]	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
0.669	0.669	tNET	RR	1	R40C42[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLK
0.813	0.144	tC2Q	RR	33	R40C42[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/Q
1.055	0.242	tNET	RR	1	BSRAM_R38[8][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/gowin_add_SDPX9B_mem_mem_0_8_s/ADA[8]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sysclk
0.000	0.000	tCL	RR	13078	PLL_R[0]	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
0.870	0.870	tNET	RR	1	BSRAM_R38[8][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/gowin_add_SDPX9B_mem_mem_0_8_s/CLKA
0.907	0.037	tHld		1	BSRAM_R38[8][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/gowin_add_SDPX9B_mem_mem_0_8_s

Path Statistics:

Clock Skew	0.201
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.669, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.242, 62.694%; tC2Q: 0.144, 37.306%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.870, 100.000%

Path20

Path Summary:

Slack	0.148
Data Arrival Time	1.055
Data Required Time	0.907
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_140_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/gowin_add_SDPX9B_mem_mem_0_3_s
Launch Clk	sysclk:[R]
Latch Clk	sysclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sysclk
0.000	0.000	tCL	RR	13078	PLL_R[0]	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
0.677	0.677	tNET	RR	1	R39C32[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_140_s0/CLK
0.821	0.144	tC2Q	RR	1	R39C32[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_140_s0/Q
1.055	0.234	tNET	RR	1	BSRAM_R38[5]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/gowin_add_SDPX9B_mem_mem_0_3_s/DI[14]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sysclk
0.000	0.000	tCL	RR	13078	PLL_R[0]	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
0.870	0.870	tNET	RR	1	BSRAM_R38[5]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/gowin_add_SDPX9B_mem_mem_0_3_s/CLKA
0.907	0.037	tHld		1	BSRAM_R38[5]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/gowin_add_SDPX9B_mem_mem_0_3_s

Path Statistics:

Clock Skew	0.193
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.677, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.234, 61.905%; tC2Q: 0.144, 38.095%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.870, 100.000%

Path21

Path Summary:

Slack	0.148
Data Arrival Time	1.055
Data Required Time	0.907
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_139_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/gowin_add_SDPX9B_mem_mem_0_3_s
Launch Clk	sysclk:[R]
Latch Clk	sysclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sysclk
0.000	0.000	tCL	RR	13078	PLL_R[0]	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
0.677	0.677	tNET	RR	1	R39C32[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_139_s0/CLK
0.821	0.144	tC2Q	RR	1	R39C32[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_139_s0/Q
1.055	0.234	tNET	RR	1	BSRAM_R38[5]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/gowin_add_SDPX9B_mem_mem_0_3_s/DI[13]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sysclk
0.000	0.000	tCL	RR	13078	PLL_R[0]	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
0.870	0.870	tNET	RR	1	BSRAM_R38[5]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/gowin_add_SDPX9B_mem_mem_0_3_s/CLKA
0.907	0.037	tHld		1	BSRAM_R38[5]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/gowin_add_SDPX9B_mem_mem_0_3_s

Path Statistics:

Clock Skew	0.193
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.677, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.234, 61.905%; tC2Q: 0.144, 38.095%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.870, 100.000%

Path22

Path Summary:

Slack	0.148
Data Arrival Time	1.055
Data Required Time	0.907
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_138_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/gowin_add_SDPX9B_mem_mem_0_3_s
Launch Clk	sysclk:[R]
Latch Clk	sysclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sysclk
0.000	0.000	tCL	RR	13078	PLL_R[0]	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
0.677	0.677	tNET	RR	1	R39C32[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_138_s0/CLK
0.821	0.144	tC2Q	RR	1	R39C32[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_138_s0/Q
1.055	0.234	tNET	RR	1	BSRAM_R38[5]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/gowin_add_SDPX9B_mem_mem_0_3_s/DI[12]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sysclk
0.000	0.000	tCL	RR	13078	PLL_R[0]	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
0.870	0.870	tNET	RR	1	BSRAM_R38[5]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/gowin_add_SDPX9B_mem_mem_0_3_s/CLKA
0.907	0.037	tHld		1	BSRAM_R38[5]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/gowin_add_SDPX9B_mem_mem_0_3_s

Path Statistics:

Clock Skew	0.193
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.677, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.234, 61.905%; tC2Q: 0.144, 38.095%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.870, 100.000%

Path23

Path Summary:

Slack	0.151
Data Arrival Time	1.058
Data Required Time	0.907
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/gowin_add_SDPX9B_mem_mem_0_8_s
Launch Clk	sysclk:[R]
Latch Clk	sysclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sysclk
0.000	0.000	tCL	RR	13078	PLL_R[0]	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
0.669	0.669	tNET	RR	1	R39C42[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/CLK
0.813	0.144	tC2Q	RR	33	R39C42[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/Q
1.058	0.245	tNET	RR	1	BSRAM_R38[8][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/gowin_add_SDPX9B_mem_mem_0_8_s/ADA[11]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sysclk
0.000	0.000	tCL	RR	13078	PLL_R[0]	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
0.870	0.870	tNET	RR	1	BSRAM_R38[8][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/gowin_add_SDPX9B_mem_mem_0_8_s/CLKA
0.907	0.037	tHld		1	BSRAM_R38[8][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/gowin_add_SDPX9B_mem_mem_0_8_s

Path Statistics:

Clock Skew	0.201
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.669, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.245, 62.982%; tC2Q: 0.144, 37.018%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.870, 100.000%

Path24

Path Summary:

Slack	0.151
Data Arrival Time	1.058
Data Required Time	0.907
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/gowin_add_SDPX9B_mem_mem_0_8_s
Launch Clk	sysclk:[R]
Latch Clk	sysclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sysclk
0.000	0.000	tCL	RR	13078	PLL_R[0]	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
0.677	0.677	tNET	RR	1	R40C40[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLK
0.821	0.144	tC2Q	RR	35	R40C40[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/Q
1.058	0.237	tNET	RR	1	BSRAM_R38[8][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/gowin_add_SDPX9B_mem_mem_0_8_s/ADA[6]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sysclk
0.000	0.000	tCL	RR	13078	PLL_R[0]	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
0.870	0.870	tNET	RR	1	BSRAM_R38[8][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/gowin_add_SDPX9B_mem_mem_0_8_s/CLKA
0.907	0.037	tHld		1	BSRAM_R38[8][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/gowin_add_SDPX9B_mem_mem_0_8_s

Path Statistics:

Clock Skew	0.193
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.677, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.237, 62.205%; tC2Q: 0.144, 37.795%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.870, 100.000%

Path25

Path Summary:

Slack	0.158
Data Arrival Time	1.061
Data Required Time	0.903
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s5
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/gowin_add_SDPX9B_mem_mem_0_6_s
Launch Clk	sysclk:[R]
Latch Clk	sysclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sysclk
0.000	0.000	tCL	RR	13078	PLL_R[0]	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
0.677	0.677	tNET	RR	1	R40C40[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s5/CLK
0.821	0.144	tC2Q	RR	36	R40C40[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s5/Q
1.061	0.240	tNET	RR	1	BSRAM_R38[7]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/gowin_add_SDPX9B_mem_mem_0_6_s/ADA[5]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sysclk
0.000	0.000	tCL	RR	13078	PLL_R[0]	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
0.866	0.866	tNET	RR	1	BSRAM_R38[7]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/gowin_add_SDPX9B_mem_mem_0_6_s/CLKA
0.903	0.037	tHld		1	BSRAM_R38[7]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/gowin_add_SDPX9B_mem_mem_0_6_s

Path Statistics:

Clock Skew	0.189
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.677, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.240, 62.500%; tC2Q: 0.144, 37.500%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.866, 100.000%

Recovery Analysis Report

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	5.514
Data Arrival Time	5.895
Data Required Time	11.409
From	u_PCIe_IP/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/rstn_s0
To	u_PCIe_IP/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/drp_addr_serdes_2_s0
Launch Clk	sysclk:[R]
Latch Clk	sysclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sysclk
0.000	0.000	tCL	RR	13078	PLL_R[0]	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
1.672	1.672	tNET	RR	1	R37C146[2][A]	u_PCIe_IP/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/rstn_s0/CLK
1.966	0.294	tC2Q	RF	174	R37C146[2][A]	u_PCIe_IP/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/rstn_s0/Q
5.895	3.929	tNET	FF	1	R53C48[1][A]	u_PCIe_IP/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/drp_addr_serdes_2_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					sysclk
10.000	0.000	tCL	RR	13078	PLL_R[0]	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
11.687	1.687	tNET	RR	1	R53C48[1][A]	u_PCIe_IP/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/drp_addr_serdes_2_s0/CLK
11.409	-0.278	tSu		1	R53C48[1][A]	u_PCIe_IP/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/drp_addr_serdes_2_s0

Path Statistics:

Clock Skew	0.015
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.672, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 3.929, 93.038%; tC2Q: 0.294, 6.962%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.687, 100.000%

Path2

Path Summary:

Slack	5.514
Data Arrival Time	5.895
Data Required Time	11.409
From	u_PCIe_IP/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/rstn_s0
To	u_PCIe_IP/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/drp_addr_serdes_3_s0
Launch Clk	sysclk:[R]
Latch Clk	sysclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sysclk
0.000	0.000	tCL	RR	13078	PLL_R[0]	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
1.672	1.672	tNET	RR	1	R37C146[2][A]	u_PCIe_IP/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/rstn_s0/CLK
1.966	0.294	tC2Q	RF	174	R37C146[2][A]	u_PCIe_IP/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/rstn_s0/Q
5.895	3.929	tNET	FF	1	R53C48[2][A]	u_PCIe_IP/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/drp_addr_serdes_3_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					sysclk
10.000	0.000	tCL	RR	13078	PLL_R[0]	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
11.687	1.687	tNET	RR	1	R53C48[2][A]	u_PCIe_IP/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/drp_addr_serdes_3_s0/CLK
11.409	-0.278	tSu		1	R53C48[2][A]	u_PCIe_IP/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/drp_addr_serdes_3_s0

Path Statistics:

Clock Skew	0.015
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.672, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 3.929, 93.038%; tC2Q: 0.294, 6.962%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.687, 100.000%

Path3

Path Summary:

Slack	2.815
Data Arrival Time	8.594
Data Required Time	11.409
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s5
Launch Clk	sysclk:[F]
Latch Clk	sysclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					sysclk
5.000	0.000	tCL	FF	13078	PLL_R[0]	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
6.676	1.676	tNET	FF	1	R50C43[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
7.030	0.354	tC2Q	FF	60	R50C43[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
8.594	1.564	tNET	FF	1	R40C40[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s5/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					sysclk
10.000	0.000	tCL	RR	13078	PLL_R[0]	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
11.687	1.687	tNET	RR	1	R40C40[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s5/CLK
11.409	-0.278	tSu		1	R40C40[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s5

Path Statistics:

Clock Skew	0.011
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.676, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.564, 81.543%; tC2Q: 0.354, 18.457%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.687, 100.000%

Path4

Path Summary:

Slack	2.815
Data Arrival Time	8.594
Data Required Time	11.409
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1
Launch Clk	sysclk:[F]
Latch Clk	sysclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					sysclk
5.000	0.000	tCL	FF	13078	PLL_R[0]	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
6.676	1.676	tNET	FF	1	R50C43[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
7.030	0.354	tC2Q	FF	60	R50C43[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
8.594	1.564	tNET	FF	1	R40C40[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					sysclk
10.000	0.000	tCL	RR	13078	PLL_R[0]	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
11.687	1.687	tNET	RR	1	R40C40[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLK
11.409	-0.278	tSu		1	R40C40[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1

Path Statistics:

Clock Skew	0.011
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.676, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.564, 81.543%; tC2Q: 0.354, 18.457%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.687, 100.000%

Path5

Path Summary:

Slack	5.719
Data Arrival Time	5.682
Data Required Time	11.401
From	u_PCIe_IP/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/rstn_s0
To	u_PCIe_IP/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wrdata_o_6_s1
Launch Clk	sysclk:[R]
Latch Clk	sysclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sysclk
0.000	0.000	tCL	RR	13078	PLL_R[0]	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
1.672	1.672	tNET	RR	1	R37C146[2][A]	u_PCIe_IP/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/rstn_s0/CLK
1.966	0.294	tC2Q	RF	174	R37C146[2][A]	u_PCIe_IP/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/rstn_s0/Q
5.682	3.716	tNET	FF	1	R30C78[1][B]	u_PCIe_IP/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wrdata_o_6_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					sysclk
10.000	0.000	tCL	RR	13078	PLL_R[0]	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
11.679	1.679	tNET	RR	1	R30C78[1][B]	u_PCIe_IP/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wrdata_o_6_s1/CLK
11.401	-0.278	tSu		1	R30C78[1][B]	u_PCIe_IP/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wrdata_o_6_s1

Path Statistics:

Clock Skew	0.007
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.672, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 3.716, 92.668%; tC2Q: 0.294, 7.332%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.679, 100.000%

Path6

Path Summary:

Slack	5.719
Data Arrival Time	5.682
Data Required Time	11.401
From	u_PCIe_IP/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/rstn_s0
To	u_PCIe_IP/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wrdata_o_14_s1
Launch Clk	sysclk:[R]
Latch Clk	sysclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sysclk
0.000	0.000	tCL	RR	13078	PLL_R[0]	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
1.672	1.672	tNET	RR	1	R37C146[2][A]	u_PCIe_IP/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/rstn_s0/CLK
1.966	0.294	tC2Q	RF	174	R37C146[2][A]	u_PCIe_IP/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/rstn_s0/Q
5.682	3.716	tNET	FF	1	R31C78[3][A]	u_PCIe_IP/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wrdata_o_14_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					sysclk
10.000	0.000	tCL	RR	13078	PLL_R[0]	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
11.679	1.679	tNET	RR	1	R31C78[3][A]	u_PCIe_IP/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wrdata_o_14_s1/CLK
11.401	-0.278	tSu		1	R31C78[3][A]	u_PCIe_IP/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wrdata_o_14_s1

Path Statistics:

Clock Skew	0.007
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.672, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 3.716, 92.668%; tC2Q: 0.294, 7.332%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.679, 100.000%

Path7

Path Summary:

Slack	5.719
Data Arrival Time	5.682
Data Required Time	11.401
From	u_PCIe_IP/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/rstn_s0
To	u_PCIe_IP/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wrdata_o_15_s1
Launch Clk	sysclk:[R]
Latch Clk	sysclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sysclk
0.000	0.000	tCL	RR	13078	PLL_R[0]	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
1.672	1.672	tNET	RR	1	R37C146[2][A]	u_PCIe_IP/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/rstn_s0/CLK
1.966	0.294	tC2Q	RF	174	R37C146[2][A]	u_PCIe_IP/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/rstn_s0/Q
5.682	3.716	tNET	FF	1	R31C78[2][B]	u_PCIe_IP/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wrdata_o_15_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					sysclk
10.000	0.000	tCL	RR	13078	PLL_R[0]	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
11.679	1.679	tNET	RR	1	R31C78[2][B]	u_PCIe_IP/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wrdata_o_15_s1/CLK
11.401	-0.278	tSu		1	R31C78[2][B]	u_PCIe_IP/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wrdata_o_15_s1

Path Statistics:

Clock Skew	0.007
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.672, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 3.716, 92.668%; tC2Q: 0.294, 7.332%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.679, 100.000%

Path8

Path Summary:

Slack	5.719
Data Arrival Time	5.682
Data Required Time	11.401
From	u_PCIe_IP/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/rstn_s0
To	u_PCIe_IP/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wrdata_o_16_s1
Launch Clk	sysclk:[R]
Latch Clk	sysclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sysclk
0.000	0.000	tCL	RR	13078	PLL_R[0]	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
1.672	1.672	tNET	RR	1	R37C146[2][A]	u_PCIe_IP/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/rstn_s0/CLK
1.966	0.294	tC2Q	RF	174	R37C146[2][A]	u_PCIe_IP/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/rstn_s0/Q
5.682	3.716	tNET	FF	1	R31C78[2][A]	u_PCIe_IP/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wrdata_o_16_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					sysclk
10.000	0.000	tCL	RR	13078	PLL_R[0]	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
11.679	1.679	tNET	RR	1	R31C78[2][A]	u_PCIe_IP/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wrdata_o_16_s1/CLK
11.401	-0.278	tSu		1	R31C78[2][A]	u_PCIe_IP/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wrdata_o_16_s1

Path Statistics:

Clock Skew	0.007
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.672, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 3.716, 92.668%; tC2Q: 0.294, 7.332%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.679, 100.000%

Path9

Path Summary:

Slack	5.719
Data Arrival Time	5.682
Data Required Time	11.401
From	u_PCIe_IP/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/rstn_s0
To	u_PCIe_IP/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/drp_wrdata_serdes_15_s0
Launch Clk	sysclk:[R]
Latch Clk	sysclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sysclk
0.000	0.000	tCL	RR	13078	PLL_R[0]	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
1.672	1.672	tNET	RR	1	R37C146[2][A]	u_PCIe_IP/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/rstn_s0/CLK
1.966	0.294	tC2Q	RF	174	R37C146[2][A]	u_PCIe_IP/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/rstn_s0/Q
5.682	3.716	tNET	FF	1	R31C78[0][A]	u_PCIe_IP/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/drp_wrdata_serdes_15_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					sysclk
10.000	0.000	tCL	RR	13078	PLL_R[0]	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
11.679	1.679	tNET	RR	1	R31C78[0][A]	u_PCIe_IP/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/drp_wrdata_serdes_15_s0/CLK
11.401	-0.278	tSu		1	R31C78[0][A]	u_PCIe_IP/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/drp_wrdata_serdes_15_s0

Path Statistics:

Clock Skew	0.007
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.672, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 3.716, 92.668%; tC2Q: 0.294, 7.332%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.679, 100.000%

Path10

Path Summary:

Slack	5.719
Data Arrival Time	5.682
Data Required Time	11.401
From	u_PCIe_IP/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/rstn_s0
To	u_PCIe_IP/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/drp_wrdata_serdes_16_s0
Launch Clk	sysclk:[R]
Latch Clk	sysclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sysclk
0.000	0.000	tCL	RR	13078	PLL_R[0]	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
1.672	1.672	tNET	RR	1	R37C146[2][A]	u_PCIe_IP/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/rstn_s0/CLK
1.966	0.294	tC2Q	RF	174	R37C146[2][A]	u_PCIe_IP/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/rstn_s0/Q
5.682	3.716	tNET	FF	1	R31C78[1][A]	u_PCIe_IP/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/drp_wrdata_serdes_16_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					sysclk
10.000	0.000	tCL	RR	13078	PLL_R[0]	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
11.679	1.679	tNET	RR	1	R31C78[1][A]	u_PCIe_IP/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/drp_wrdata_serdes_16_s0/CLK
11.401	-0.278	tSu		1	R31C78[1][A]	u_PCIe_IP/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/drp_wrdata_serdes_16_s0

Path Statistics:

Clock Skew	0.007
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.672, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 3.716, 92.668%; tC2Q: 0.294, 7.332%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.679, 100.000%

Path11

Path Summary:

Slack	2.886
Data Arrival Time	8.920
Data Required Time	11.805
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1
Launch Clk	sysclk:[F]
Latch Clk	sysclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					sysclk
5.000	0.000	tCL	FF	13078	PLL_R[0]	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
6.676	1.676	tNET	FF	1	R50C43[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
7.030	0.354	tC2Q	FF	60	R50C43[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
8.920	1.889	tNET	FF	1	R36C40[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					sysclk
10.000	0.000	tCL	RR	13078	PLL_R[0]	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
12.083	2.083	tNET	RR	1	R36C40[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/CLK
11.805	-0.278	tSu		1	R36C40[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1

Path Statistics:

Clock Skew	0.406
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.676, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.889, 84.218%; tC2Q: 0.354, 15.782%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.083, 100.000%

Path12

Path Summary:

Slack	2.886
Data Arrival Time	8.515
Data Required Time	11.401
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1
Launch Clk	sysclk:[F]
Latch Clk	sysclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					sysclk
5.000	0.000	tCL	FF	13078	PLL_R[0]	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
6.676	1.676	tNET	FF	1	R50C43[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
7.030	0.354	tC2Q	FF	60	R50C43[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
8.516	1.485	tNET	FF	1	R39C35[3][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					sysclk
10.000	0.000	tCL	RR	13078	PLL_R[0]	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
11.679	1.679	tNET	RR	1	R39C35[3][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1/CLK
11.401	-0.278	tSu		1	R39C35[3][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1

Path Statistics:

Clock Skew	0.003
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.676, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.485, 80.750%; tC2Q: 0.354, 19.250%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.679, 100.000%

Path13

Path Summary:

Slack	2.886
Data Arrival Time	8.515
Data Required Time	11.401
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1
Launch Clk	sysclk:[F]
Latch Clk	sysclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					sysclk
5.000	0.000	tCL	FF	13078	PLL_R[0]	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
6.676	1.676	tNET	FF	1	R50C43[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
7.030	0.354	tC2Q	FF	60	R50C43[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
8.516	1.485	tNET	FF	1	R39C35[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					sysclk
10.000	0.000	tCL	RR	13078	PLL_R[0]	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
11.679	1.679	tNET	RR	1	R39C35[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/CLK
11.401	-0.278	tSu		1	R39C35[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1

Path Statistics:

Clock Skew	0.003
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.676, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.485, 80.750%; tC2Q: 0.354, 19.250%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.679, 100.000%

Path14

Path Summary:

Slack	2.886
Data Arrival Time	8.515
Data Required Time	11.401
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1
Launch Clk	sysclk:[F]
Latch Clk	sysclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					sysclk
5.000	0.000	tCL	FF	13078	PLL_R[0]	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
6.676	1.676	tNET	FF	1	R50C43[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
7.030	0.354	tC2Q	FF	60	R50C43[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
8.516	1.485	tNET	FF	1	R39C35[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					sysclk
10.000	0.000	tCL	RR	13078	PLL_R[0]	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
11.679	1.679	tNET	RR	1	R39C35[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1/CLK
11.401	-0.278	tSu		1	R39C35[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1

Path Statistics:

Clock Skew	0.003
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.676, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.485, 80.750%; tC2Q: 0.354, 19.250%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.679, 100.000%

Path15

Path Summary:

Slack	2.886
Data Arrival Time	8.515
Data Required Time	11.401
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1
Launch Clk	sysclk:[F]
Latch Clk	sysclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					sysclk
5.000	0.000	tCL	FF	13078	PLL_R[0]	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
6.676	1.676	tNET	FF	1	R50C43[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
7.030	0.354	tC2Q	FF	60	R50C43[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
8.516	1.485	tNET	FF	1	R39C35[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					sysclk
10.000	0.000	tCL	RR	13078	PLL_R[0]	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
11.679	1.679	tNET	RR	1	R39C35[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/CLK
11.401	-0.278	tSu		1	R39C35[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1

Path Statistics:

Clock Skew	0.003
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.676, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.485, 80.750%; tC2Q: 0.354, 19.250%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.679, 100.000%

Path16

Path Summary:

Slack	2.893
Data Arrival Time	8.508
Data Required Time	11.401
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1
Launch Clk	sysclk:[F]
Latch Clk	sysclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					sysclk
5.000	0.000	tCL	FF	13078	PLL_R[0]	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
6.676	1.676	tNET	FF	1	R50C43[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
7.030	0.354	tC2Q	FF	60	R50C43[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
8.509	1.478	tNET	FF	1	R40C35[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					sysclk
10.000	0.000	tCL	RR	13078	PLL_R[0]	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
11.679	1.679	tNET	RR	1	R40C35[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CLK
11.401	-0.278	tSu		1	R40C35[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1

Path Statistics:

Clock Skew	0.003
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.676, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.478, 80.677%; tC2Q: 0.354, 19.323%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.679, 100.000%

Path17

Path Summary:

Slack	2.893
Data Arrival Time	8.508
Data Required Time	11.401
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1
Launch Clk	sysclk:[F]
Latch Clk	sysclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					sysclk
5.000	0.000	tCL	FF	13078	PLL_R[0]	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
6.676	1.676	tNET	FF	1	R50C43[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
7.030	0.354	tC2Q	FF	60	R50C43[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
8.509	1.478	tNET	FF	1	R40C35[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					sysclk
10.000	0.000	tCL	RR	13078	PLL_R[0]	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
11.679	1.679	tNET	RR	1	R40C35[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1/CLK
11.401	-0.278	tSu		1	R40C35[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1

Path Statistics:

Clock Skew	0.003
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.676, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.478, 80.677%; tC2Q: 0.354, 19.323%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.679, 100.000%

Path18

Path Summary:

Slack	2.893
Data Arrival Time	8.508
Data Required Time	11.401
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1
Launch Clk	sysclk:[F]
Latch Clk	sysclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					sysclk
5.000	0.000	tCL	FF	13078	PLL_R[0]	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
6.676	1.676	tNET	FF	1	R50C43[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
7.030	0.354	tC2Q	FF	60	R50C43[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
8.509	1.478	tNET	FF	1	R40C35[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					sysclk
10.000	0.000	tCL	RR	13078	PLL_R[0]	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
11.679	1.679	tNET	RR	1	R40C35[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1/CLK
11.401	-0.278	tSu		1	R40C35[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1

Path Statistics:

Clock Skew	0.003
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.676, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.478, 80.677%; tC2Q: 0.354, 19.323%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.679, 100.000%

Path19

Path Summary:

Slack	5.887
Data Arrival Time	5.514
Data Required Time	11.401
From	u_PCIe_IP/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/rstn_s0
To	u_PCIe_IP/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wrdata_o_22_s1
Launch Clk	sysclk:[R]
Latch Clk	sysclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sysclk
0.000	0.000	tCL	RR	13078	PLL_R[0]	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
1.672	1.672	tNET	RR	1	R37C146[2][A]	u_PCIe_IP/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/rstn_s0/CLK
1.966	0.294	tC2Q	RF	174	R37C146[2][A]	u_PCIe_IP/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/rstn_s0/Q
5.514	3.548	tNET	FF	1	R32C78[3][A]	u_PCIe_IP/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wrdata_o_22_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					sysclk
10.000	0.000	tCL	RR	13078	PLL_R[0]	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
11.679	1.679	tNET	RR	1	R32C78[3][A]	u_PCIe_IP/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wrdata_o_22_s1/CLK
11.401	-0.278	tSu		1	R32C78[3][A]	u_PCIe_IP/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wrdata_o_22_s1

Path Statistics:

Clock Skew	0.007
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.672, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 3.548, 92.348%; tC2Q: 0.294, 7.652%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.679, 100.000%

Path20

Path Summary:

Slack	5.887
Data Arrival Time	5.514
Data Required Time	11.401
From	u_PCIe_IP/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/rstn_s0
To	u_PCIe_IP/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wrdata_o_23_s1
Launch Clk	sysclk:[R]
Latch Clk	sysclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sysclk
0.000	0.000	tCL	RR	13078	PLL_R[0]	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
1.672	1.672	tNET	RR	1	R37C146[2][A]	u_PCIe_IP/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/rstn_s0/CLK
1.966	0.294	tC2Q	RF	174	R37C146[2][A]	u_PCIe_IP/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/rstn_s0/Q
5.514	3.548	tNET	FF	1	R32C78[2][B]	u_PCIe_IP/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wrdata_o_23_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					sysclk
10.000	0.000	tCL	RR	13078	PLL_R[0]	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
11.679	1.679	tNET	RR	1	R32C78[2][B]	u_PCIe_IP/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wrdata_o_23_s1/CLK
11.401	-0.278	tSu		1	R32C78[2][B]	u_PCIe_IP/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wrdata_o_23_s1

Path Statistics:

Clock Skew	0.007
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.672, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 3.548, 92.348%; tC2Q: 0.294, 7.652%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.679, 100.000%

Path21

Path Summary:

Slack	5.887
Data Arrival Time	5.514
Data Required Time	11.401
From	u_PCIe_IP/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/rstn_s0
To	u_PCIe_IP/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wrdata_o_24_s1
Launch Clk	sysclk:[R]
Latch Clk	sysclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sysclk
0.000	0.000	tCL	RR	13078	PLL_R[0]	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
1.672	1.672	tNET	RR	1	R37C146[2][A]	u_PCIe_IP/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/rstn_s0/CLK
1.966	0.294	tC2Q	RF	174	R37C146[2][A]	u_PCIe_IP/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/rstn_s0/Q
5.514	3.548	tNET	FF	1	R32C78[2][A]	u_PCIe_IP/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wrdata_o_24_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					sysclk
10.000	0.000	tCL	RR	13078	PLL_R[0]	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
11.679	1.679	tNET	RR	1	R32C78[2][A]	u_PCIe_IP/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wrdata_o_24_s1/CLK
11.401	-0.278	tSu		1	R32C78[2][A]	u_PCIe_IP/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wrdata_o_24_s1

Path Statistics:

Clock Skew	0.007
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.672, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 3.548, 92.348%; tC2Q: 0.294, 7.652%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.679, 100.000%

Path22

Path Summary:

Slack	5.887
Data Arrival Time	5.514
Data Required Time	11.401
From	u_PCIe_IP/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/rstn_s0
To	u_PCIe_IP/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/drp_wrdata_serdes_14_s0
Launch Clk	sysclk:[R]
Latch Clk	sysclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sysclk
0.000	0.000	tCL	RR	13078	PLL_R[0]	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
1.672	1.672	tNET	RR	1	R37C146[2][A]	u_PCIe_IP/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/rstn_s0/CLK
1.966	0.294	tC2Q	RF	174	R37C146[2][A]	u_PCIe_IP/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/rstn_s0/Q
5.514	3.548	tNET	FF	1	R32C78[1][A]	u_PCIe_IP/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/drp_wrdata_serdes_14_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					sysclk
10.000	0.000	tCL	RR	13078	PLL_R[0]	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
11.679	1.679	tNET	RR	1	R32C78[1][A]	u_PCIe_IP/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/drp_wrdata_serdes_14_s0/CLK
11.401	-0.278	tSu		1	R32C78[1][A]	u_PCIe_IP/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/drp_wrdata_serdes_14_s0

Path Statistics:

Clock Skew	0.007
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.672, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 3.548, 92.348%; tC2Q: 0.294, 7.652%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.679, 100.000%

Path23

Path Summary:

Slack	5.887
Data Arrival Time	5.514
Data Required Time	11.401
From	u_PCIe_IP/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/rstn_s0
To	u_PCIe_IP/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/drp_wrdata_serdes_22_s0
Launch Clk	sysclk:[R]
Latch Clk	sysclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sysclk
0.000	0.000	tCL	RR	13078	PLL_R[0]	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
1.672	1.672	tNET	RR	1	R37C146[2][A]	u_PCIe_IP/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/rstn_s0/CLK
1.966	0.294	tC2Q	RF	174	R37C146[2][A]	u_PCIe_IP/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/rstn_s0/Q
5.514	3.548	tNET	FF	1	R32C78[0][A]	u_PCIe_IP/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/drp_wrdata_serdes_22_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					sysclk
10.000	0.000	tCL	RR	13078	PLL_R[0]	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
11.679	1.679	tNET	RR	1	R32C78[0][A]	u_PCIe_IP/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/drp_wrdata_serdes_22_s0/CLK
11.401	-0.278	tSu		1	R32C78[0][A]	u_PCIe_IP/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/drp_wrdata_serdes_22_s0

Path Statistics:

Clock Skew	0.007
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.672, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 3.548, 92.348%; tC2Q: 0.294, 7.652%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.679, 100.000%

Path24

Path Summary:

Slack	2.947
Data Arrival Time	8.448
Data Required Time	11.394
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1
Launch Clk	sysclk:[F]
Latch Clk	sysclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					sysclk
5.000	0.000	tCL	FF	13078	PLL_R[0]	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
6.676	1.676	tNET	FF	1	R50C43[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
7.030	0.354	tC2Q	FF	60	R50C43[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
8.448	1.417	tNET	FF	1	R40C42[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					sysclk
10.000	0.000	tCL	RR	13078	PLL_R[0]	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
11.672	1.672	tNET	RR	1	R40C42[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/CLK
11.394	-0.278	tSu		1	R40C42[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1

Path Statistics:

Clock Skew	-0.005
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.676, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.417, 80.011%; tC2Q: 0.354, 19.989%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.672, 100.000%

Path25

Path Summary:

Slack	2.947
Data Arrival Time	8.448
Data Required Time	11.394
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1
Launch Clk	sysclk:[F]
Latch Clk	sysclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					sysclk
5.000	0.000	tCL	FF	13078	PLL_R[0]	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
6.676	1.676	tNET	FF	1	R50C43[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
7.030	0.354	tC2Q	FF	60	R50C43[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
8.448	1.417	tNET	FF	1	R40C42[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					sysclk
10.000	0.000	tCL	RR	13078	PLL_R[0]	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
11.672	1.672	tNET	RR	1	R40C42[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLK
11.394	-0.278	tSu		1	R40C42[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1

Path Statistics:

Clock Skew	-0.005
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.676, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.417, 80.011%; tC2Q: 0.354, 19.989%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.672, 100.000%

Removal Analysis Report

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	0.397
Data Arrival Time	1.013
Data Required Time	0.616
From	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_h2c_engine/u_descriptor_fifo/rstn_d1_s0
To	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_h2c_engine/u_data_fifo/remaining_num_3_s0
Launch Clk	sysclk:[R]
Latch Clk	sysclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sysclk
0.000	0.000	tCL	RR	13078	PLL_R[0]	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
0.669	0.669	tNET	RR	1	R54C111[2][A]	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_h2c_engine/u_descriptor_fifo/rstn_d1_s0/CLK
0.813	0.144	tC2Q	RR	73	R54C111[2][A]	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_h2c_engine/u_descriptor_fifo/rstn_d1_s0/Q
1.013	0.200	tNET	RR	1	R51C111[1][A]	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_h2c_engine/u_data_fifo/remaining_num_3_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sysclk
0.000	0.000	tCL	RR	13078	PLL_R[0]	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
0.669	0.669	tNET	RR	1	R51C111[1][A]	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_h2c_engine/u_data_fifo/remaining_num_3_s0/CLK
0.616	-0.053	tHld		1	R51C111[1][A]	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_h2c_engine/u_data_fifo/remaining_num_3_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.669, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.200, 58.140%; tC2Q: 0.144, 41.860%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.669, 100.000%

Path2

Path Summary:

Slack	0.397
Data Arrival Time	1.013
Data Required Time	0.616
From	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_h2c_engine/u_descriptor_fifo/rstn_d1_s0
To	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_h2c_engine/u_data_fifo/remaining_num_4_s0
Launch Clk	sysclk:[R]
Latch Clk	sysclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sysclk
0.000	0.000	tCL	RR	13078	PLL_R[0]	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
0.669	0.669	tNET	RR	1	R54C111[2][A]	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_h2c_engine/u_descriptor_fifo/rstn_d1_s0/CLK
0.813	0.144	tC2Q	RR	73	R54C111[2][A]	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_h2c_engine/u_descriptor_fifo/rstn_d1_s0/Q
1.013	0.200	tNET	RR	1	R51C111[2][A]	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_h2c_engine/u_data_fifo/remaining_num_4_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sysclk
0.000	0.000	tCL	RR	13078	PLL_R[0]	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
0.669	0.669	tNET	RR	1	R51C111[2][A]	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_h2c_engine/u_data_fifo/remaining_num_4_s0/CLK
0.616	-0.053	tHld		1	R51C111[2][A]	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_h2c_engine/u_data_fifo/remaining_num_4_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.669, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.200, 58.140%; tC2Q: 0.144, 41.860%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.669, 100.000%

Path3

Path Summary:

Slack	0.397
Data Arrival Time	1.013
Data Required Time	0.616
From	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_h2c_engine/u_descriptor_fifo/rstn_d1_s0
To	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_h2c_engine/u_data_fifo/remaining_num_5_s0
Launch Clk	sysclk:[R]
Latch Clk	sysclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sysclk
0.000	0.000	tCL	RR	13078	PLL_R[0]	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
0.669	0.669	tNET	RR	1	R54C111[2][A]	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_h2c_engine/u_descriptor_fifo/rstn_d1_s0/CLK
0.813	0.144	tC2Q	RR	73	R54C111[2][A]	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_h2c_engine/u_descriptor_fifo/rstn_d1_s0/Q
1.013	0.200	tNET	RR	1	R51C111[0][B]	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_h2c_engine/u_data_fifo/remaining_num_5_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sysclk
0.000	0.000	tCL	RR	13078	PLL_R[0]	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
0.669	0.669	tNET	RR	1	R51C111[0][B]	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_h2c_engine/u_data_fifo/remaining_num_5_s0/CLK
0.616	-0.053	tHld		1	R51C111[0][B]	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_h2c_engine/u_data_fifo/remaining_num_5_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.669, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.200, 58.140%; tC2Q: 0.144, 41.860%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.669, 100.000%

Path4

Path Summary:

Slack	0.484
Data Arrival Time	1.112
Data Required Time	0.628
From	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_descriptor_fifo/rstn_d1_s0
To	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_descriptor_fifo/rdaddr_0_s3
Launch Clk	sysclk:[R]
Latch Clk	sysclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sysclk
0.000	0.000	tCL	RR	13078	PLL_R[0]	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
0.681	0.681	tNET	RR	1	R60C73[3][A]	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_descriptor_fifo/rstn_d1_s0/CLK
0.825	0.144	tC2Q	RR	64	R60C73[3][A]	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_descriptor_fifo/rstn_d1_s0/Q
1.112	0.287	tNET	RR	1	R59C73[0][A]	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_descriptor_fifo/rdaddr_0_s3/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sysclk
0.000	0.000	tCL	RR	13078	PLL_R[0]	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
0.681	0.681	tNET	RR	1	R59C73[0][A]	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_descriptor_fifo/rdaddr_0_s3/CLK
0.628	-0.053	tHld		1	R59C73[0][A]	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_descriptor_fifo/rdaddr_0_s3

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.681, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.287, 66.589%; tC2Q: 0.144, 33.411%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.681, 100.000%

Path5

Path Summary:

Slack	0.484
Data Arrival Time	1.112
Data Required Time	0.628
From	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_descriptor_fifo/rstn_d1_s0
To	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_descriptor_fifo/remaining_num_2_s0
Launch Clk	sysclk:[R]
Latch Clk	sysclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sysclk
0.000	0.000	tCL	RR	13078	PLL_R[0]	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
0.681	0.681	tNET	RR	1	R60C73[3][A]	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_descriptor_fifo/rstn_d1_s0/CLK
0.825	0.144	tC2Q	RR	64	R60C73[3][A]	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_descriptor_fifo/rstn_d1_s0/Q
1.112	0.287	tNET	RR	1	R58C73[1][A]	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_descriptor_fifo/remaining_num_2_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sysclk
0.000	0.000	tCL	RR	13078	PLL_R[0]	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
0.681	0.681	tNET	RR	1	R58C73[1][A]	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_descriptor_fifo/remaining_num_2_s0/CLK
0.628	-0.053	tHld		1	R58C73[1][A]	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_descriptor_fifo/remaining_num_2_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.681, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.287, 66.589%; tC2Q: 0.144, 33.411%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.681, 100.000%

Path6

Path Summary:

Slack	0.484
Data Arrival Time	1.112
Data Required Time	0.628
From	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_descriptor_fifo/rstn_d1_s0
To	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_descriptor_fifo/remaining_num_3_s0
Launch Clk	sysclk:[R]
Latch Clk	sysclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sysclk
0.000	0.000	tCL	RR	13078	PLL_R[0]	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
0.681	0.681	tNET	RR	1	R60C73[3][A]	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_descriptor_fifo/rstn_d1_s0/CLK
0.825	0.144	tC2Q	RR	64	R60C73[3][A]	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_descriptor_fifo/rstn_d1_s0/Q
1.112	0.287	tNET	RR	1	R58C73[0][B]	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_descriptor_fifo/remaining_num_3_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sysclk
0.000	0.000	tCL	RR	13078	PLL_R[0]	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
0.681	0.681	tNET	RR	1	R58C73[0][B]	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_descriptor_fifo/remaining_num_3_s0/CLK
0.628	-0.053	tHld		1	R58C73[0][B]	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_descriptor_fifo/remaining_num_3_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.681, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.287, 66.589%; tC2Q: 0.144, 33.411%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.681, 100.000%

Path7

Path Summary:

Slack	0.484
Data Arrival Time	1.112
Data Required Time	0.628
From	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_descriptor_fifo/rstn_d1_s0
To	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_descriptor_fifo/remaining_num_4_s0
Launch Clk	sysclk:[R]
Latch Clk	sysclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sysclk
0.000	0.000	tCL	RR	13078	PLL_R[0]	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
0.681	0.681	tNET	RR	1	R60C73[3][A]	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_descriptor_fifo/rstn_d1_s0/CLK
0.825	0.144	tC2Q	RR	64	R60C73[3][A]	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_descriptor_fifo/rstn_d1_s0/Q
1.112	0.287	tNET	RR	1	R59C73[0][B]	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_descriptor_fifo/remaining_num_4_s0/PRESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sysclk
0.000	0.000	tCL	RR	13078	PLL_R[0]	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
0.681	0.681	tNET	RR	1	R59C73[0][B]	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_descriptor_fifo/remaining_num_4_s0/CLK
0.628	-0.053	tHld		1	R59C73[0][B]	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_descriptor_fifo/remaining_num_4_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.681, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.287, 66.589%; tC2Q: 0.144, 33.411%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.681, 100.000%

Path8

Path Summary:

Slack	0.484
Data Arrival Time	1.112
Data Required Time	0.628
From	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_descriptor_fifo/rstn_d1_s0
To	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_descriptor_fifo/full_s0
Launch Clk	sysclk:[R]
Latch Clk	sysclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sysclk
0.000	0.000	tCL	RR	13078	PLL_R[0]	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
0.681	0.681	tNET	RR	1	R60C73[3][A]	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_descriptor_fifo/rstn_d1_s0/CLK
0.825	0.144	tC2Q	RR	64	R60C73[3][A]	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_descriptor_fifo/rstn_d1_s0/Q
1.112	0.287	tNET	RR	1	R58C73[2][A]	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_descriptor_fifo/full_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sysclk
0.000	0.000	tCL	RR	13078	PLL_R[0]	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
0.681	0.681	tNET	RR	1	R58C73[2][A]	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_descriptor_fifo/full_s0/CLK
0.628	-0.053	tHld		1	R58C73[2][A]	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_descriptor_fifo/full_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.681, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.287, 66.589%; tC2Q: 0.144, 33.411%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.681, 100.000%

Path9

Path Summary:

Slack	0.484
Data Arrival Time	1.112
Data Required Time	0.628
From	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_descriptor_fifo/rstn_d1_s0
To	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_descriptor_fifo/cnt_2_s0
Launch Clk	sysclk:[R]
Latch Clk	sysclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sysclk
0.000	0.000	tCL	RR	13078	PLL_R[0]	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
0.681	0.681	tNET	RR	1	R60C73[3][A]	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_descriptor_fifo/rstn_d1_s0/CLK
0.825	0.144	tC2Q	RR	64	R60C73[3][A]	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_descriptor_fifo/rstn_d1_s0/Q
1.112	0.287	tNET	RR	1	R58C73[1][B]	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_descriptor_fifo/cnt_2_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sysclk
0.000	0.000	tCL	RR	13078	PLL_R[0]	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
0.681	0.681	tNET	RR	1	R58C73[1][B]	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_descriptor_fifo/cnt_2_s0/CLK
0.628	-0.053	tHld		1	R58C73[1][B]	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_descriptor_fifo/cnt_2_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.681, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.287, 66.589%; tC2Q: 0.144, 33.411%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.681, 100.000%

Path10

Path Summary:

Slack	0.484
Data Arrival Time	1.112
Data Required Time	0.628
From	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_descriptor_fifo/rstn_d1_s0
To	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_descriptor_fifo/cnt_4_s0
Launch Clk	sysclk:[R]
Latch Clk	sysclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sysclk
0.000	0.000	tCL	RR	13078	PLL_R[0]	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
0.681	0.681	tNET	RR	1	R60C73[3][A]	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_descriptor_fifo/rstn_d1_s0/CLK
0.825	0.144	tC2Q	RR	64	R60C73[3][A]	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_descriptor_fifo/rstn_d1_s0/Q
1.112	0.287	tNET	RR	1	R58C73[0][A]	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_descriptor_fifo/cnt_4_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sysclk
0.000	0.000	tCL	RR	13078	PLL_R[0]	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
0.681	0.681	tNET	RR	1	R58C73[0][A]	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_descriptor_fifo/cnt_4_s0/CLK
0.628	-0.053	tHld		1	R58C73[0][A]	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_descriptor_fifo/cnt_4_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.681, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.287, 66.589%; tC2Q: 0.144, 33.411%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.681, 100.000%

Path11

Path Summary:

Slack	0.484
Data Arrival Time	1.112
Data Required Time	0.628
From	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_descriptor_fifo/rstn_d1_s0
To	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_descriptor_fifo/rdaddr_1_s0
Launch Clk	sysclk:[R]
Latch Clk	sysclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sysclk
0.000	0.000	tCL	RR	13078	PLL_R[0]	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
0.681	0.681	tNET	RR	1	R60C73[3][A]	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_descriptor_fifo/rstn_d1_s0/CLK
0.825	0.144	tC2Q	RR	64	R60C73[3][A]	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_descriptor_fifo/rstn_d1_s0/Q
1.112	0.287	tNET	RR	1	R59C73[2][A]	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_descriptor_fifo/rdaddr_1_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sysclk
0.000	0.000	tCL	RR	13078	PLL_R[0]	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
0.681	0.681	tNET	RR	1	R59C73[2][A]	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_descriptor_fifo/rdaddr_1_s0/CLK
0.628	-0.053	tHld		1	R59C73[2][A]	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_descriptor_fifo/rdaddr_1_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.681, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.287, 66.589%; tC2Q: 0.144, 33.411%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.681, 100.000%

Path12

Path Summary:

Slack	0.484
Data Arrival Time	1.112
Data Required Time	0.628
From	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_descriptor_fifo/rstn_d1_s0
To	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_descriptor_fifo/rdaddr_2_s0
Launch Clk	sysclk:[R]
Latch Clk	sysclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sysclk
0.000	0.000	tCL	RR	13078	PLL_R[0]	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
0.681	0.681	tNET	RR	1	R60C73[3][A]	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_descriptor_fifo/rstn_d1_s0/CLK
0.825	0.144	tC2Q	RR	64	R60C73[3][A]	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_descriptor_fifo/rstn_d1_s0/Q
1.112	0.287	tNET	RR	1	R59C73[1][B]	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_descriptor_fifo/rdaddr_2_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sysclk
0.000	0.000	tCL	RR	13078	PLL_R[0]	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
0.681	0.681	tNET	RR	1	R59C73[1][B]	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_descriptor_fifo/rdaddr_2_s0/CLK
0.628	-0.053	tHld		1	R59C73[1][B]	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_descriptor_fifo/rdaddr_2_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.681, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.287, 66.589%; tC2Q: 0.144, 33.411%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.681, 100.000%

Path13

Path Summary:

Slack	0.484
Data Arrival Time	1.112
Data Required Time	0.628
From	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_descriptor_fifo/rstn_d1_s0
To	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_descriptor_fifo/rdaddr_3_s0
Launch Clk	sysclk:[R]
Latch Clk	sysclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sysclk
0.000	0.000	tCL	RR	13078	PLL_R[0]	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
0.681	0.681	tNET	RR	1	R60C73[3][A]	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_descriptor_fifo/rstn_d1_s0/CLK
0.825	0.144	tC2Q	RR	64	R60C73[3][A]	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_descriptor_fifo/rstn_d1_s0/Q
1.112	0.287	tNET	RR	1	R59C73[1][A]	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_descriptor_fifo/rdaddr_3_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sysclk
0.000	0.000	tCL	RR	13078	PLL_R[0]	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
0.681	0.681	tNET	RR	1	R59C73[1][A]	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_descriptor_fifo/rdaddr_3_s0/CLK
0.628	-0.053	tHld		1	R59C73[1][A]	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_descriptor_fifo/rdaddr_3_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.681, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.287, 66.589%; tC2Q: 0.144, 33.411%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.681, 100.000%

Path14

Path Summary:

Slack	0.491
Data Arrival Time	1.107
Data Required Time	0.616
From	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_h2c_engine/u_reset_fifo/fifo_rstn_s0
To	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_h2c_engine/u_descriptor_fifo/rstn_d0_s0
Launch Clk	sysclk:[R]
Latch Clk	sysclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sysclk
0.000	0.000	tCL	RR	13078	PLL_R[0]	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
0.677	0.677	tNET	RR	1	R37C109[0][A]	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_h2c_engine/u_reset_fifo/fifo_rstn_s0/CLK
0.821	0.144	tC2Q	RR	2	R37C109[0][A]	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_h2c_engine/u_reset_fifo/fifo_rstn_s0/Q
1.107	0.286	tNET	RR	1	R54C111[2][B]	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_h2c_engine/u_descriptor_fifo/rstn_d0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sysclk
0.000	0.000	tCL	RR	13078	PLL_R[0]	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
0.669	0.669	tNET	RR	1	R54C111[2][B]	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_h2c_engine/u_descriptor_fifo/rstn_d0_s0/CLK
0.616	-0.053	tHld		1	R54C111[2][B]	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_h2c_engine/u_descriptor_fifo/rstn_d0_s0

Path Statistics:

Clock Skew	-0.008
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.677, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.286, 66.512%; tC2Q: 0.144, 33.488%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.669, 100.000%

Path15

Path Summary:

Slack	0.491
Data Arrival Time	1.107
Data Required Time	0.616
From	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_h2c_engine/u_reset_fifo/fifo_rstn_s0
To	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_h2c_engine/u_descriptor_fifo/rstn_d1_s0
Launch Clk	sysclk:[R]
Latch Clk	sysclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sysclk
0.000	0.000	tCL	RR	13078	PLL_R[0]	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
0.677	0.677	tNET	RR	1	R37C109[0][A]	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_h2c_engine/u_reset_fifo/fifo_rstn_s0/CLK
0.821	0.144	tC2Q	RR	2	R37C109[0][A]	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_h2c_engine/u_reset_fifo/fifo_rstn_s0/Q
1.107	0.286	tNET	RR	1	R54C111[2][A]	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_h2c_engine/u_descriptor_fifo/rstn_d1_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sysclk
0.000	0.000	tCL	RR	13078	PLL_R[0]	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
0.669	0.669	tNET	RR	1	R54C111[2][A]	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_h2c_engine/u_descriptor_fifo/rstn_d1_s0/CLK
0.616	-0.053	tHld		1	R54C111[2][A]	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_h2c_engine/u_descriptor_fifo/rstn_d1_s0

Path Statistics:

Clock Skew	-0.008
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.677, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.286, 66.512%; tC2Q: 0.144, 33.488%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.669, 100.000%

Path16

Path Summary:

Slack	0.495
Data Arrival Time	1.115
Data Required Time	0.620
From	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_h2c_engine/u_descriptor_fifo/rstn_d1_s0
To	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_h2c_engine/u_data_fifo/remaining_num_6_s0
Launch Clk	sysclk:[R]
Latch Clk	sysclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sysclk
0.000	0.000	tCL	RR	13078	PLL_R[0]	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
0.669	0.669	tNET	RR	1	R54C111[2][A]	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_h2c_engine/u_descriptor_fifo/rstn_d1_s0/CLK
0.813	0.144	tC2Q	RR	73	R54C111[2][A]	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_h2c_engine/u_descriptor_fifo/rstn_d1_s0/Q
1.115	0.302	tNET	RR	1	R51C112[0][B]	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_h2c_engine/u_data_fifo/remaining_num_6_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sysclk
0.000	0.000	tCL	RR	13078	PLL_R[0]	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
0.673	0.673	tNET	RR	1	R51C112[0][B]	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_h2c_engine/u_data_fifo/remaining_num_6_s0/CLK
0.620	-0.053	tHld		1	R51C112[0][B]	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_h2c_engine/u_data_fifo/remaining_num_6_s0

Path Statistics:

Clock Skew	0.004
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.669, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.302, 67.713%; tC2Q: 0.144, 32.287%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.673, 100.000%

Path17

Path Summary:

Slack	0.495
Data Arrival Time	1.115
Data Required Time	0.620
From	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_h2c_engine/u_descriptor_fifo/rstn_d1_s0
To	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_h2c_engine/u_data_fifo/remaining_num_7_s0
Launch Clk	sysclk:[R]
Latch Clk	sysclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sysclk
0.000	0.000	tCL	RR	13078	PLL_R[0]	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
0.669	0.669	tNET	RR	1	R54C111[2][A]	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_h2c_engine/u_descriptor_fifo/rstn_d1_s0/CLK
0.813	0.144	tC2Q	RR	73	R54C111[2][A]	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_h2c_engine/u_descriptor_fifo/rstn_d1_s0/Q
1.115	0.302	tNET	RR	1	R51C112[3][A]	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_h2c_engine/u_data_fifo/remaining_num_7_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sysclk
0.000	0.000	tCL	RR	13078	PLL_R[0]	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
0.673	0.673	tNET	RR	1	R51C112[3][A]	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_h2c_engine/u_data_fifo/remaining_num_7_s0/CLK
0.620	-0.053	tHld		1	R51C112[3][A]	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_h2c_engine/u_data_fifo/remaining_num_7_s0

Path Statistics:

Clock Skew	0.004
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.669, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.302, 67.713%; tC2Q: 0.144, 32.287%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.673, 100.000%

Path18

Path Summary:

Slack	0.495
Data Arrival Time	1.115
Data Required Time	0.620
From	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_h2c_engine/u_descriptor_fifo/rstn_d1_s0
To	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_h2c_engine/u_data_fifo/remaining_num_8_s0
Launch Clk	sysclk:[R]
Latch Clk	sysclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sysclk
0.000	0.000	tCL	RR	13078	PLL_R[0]	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
0.669	0.669	tNET	RR	1	R54C111[2][A]	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_h2c_engine/u_descriptor_fifo/rstn_d1_s0/CLK
0.813	0.144	tC2Q	RR	73	R54C111[2][A]	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_h2c_engine/u_descriptor_fifo/rstn_d1_s0/Q
1.115	0.302	tNET	RR	1	R51C112[2][B]	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_h2c_engine/u_data_fifo/remaining_num_8_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sysclk
0.000	0.000	tCL	RR	13078	PLL_R[0]	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
0.673	0.673	tNET	RR	1	R51C112[2][B]	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_h2c_engine/u_data_fifo/remaining_num_8_s0/CLK
0.620	-0.053	tHld		1	R51C112[2][B]	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_h2c_engine/u_data_fifo/remaining_num_8_s0

Path Statistics:

Clock Skew	0.004
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.669, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.302, 67.713%; tC2Q: 0.144, 32.287%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.673, 100.000%

Path19

Path Summary:

Slack	0.495
Data Arrival Time	1.115
Data Required Time	0.620
From	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_h2c_engine/u_descriptor_fifo/rstn_d1_s0
To	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_h2c_engine/u_data_fifo/remaining_num_9_s0
Launch Clk	sysclk:[R]
Latch Clk	sysclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sysclk
0.000	0.000	tCL	RR	13078	PLL_R[0]	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
0.669	0.669	tNET	RR	1	R54C111[2][A]	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_h2c_engine/u_descriptor_fifo/rstn_d1_s0/CLK
0.813	0.144	tC2Q	RR	73	R54C111[2][A]	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_h2c_engine/u_descriptor_fifo/rstn_d1_s0/Q
1.115	0.302	tNET	RR	1	R51C112[1][A]	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_h2c_engine/u_data_fifo/remaining_num_9_s0/PRESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sysclk
0.000	0.000	tCL	RR	13078	PLL_R[0]	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
0.673	0.673	tNET	RR	1	R51C112[1][A]	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_h2c_engine/u_data_fifo/remaining_num_9_s0/CLK
0.620	-0.053	tHld		1	R51C112[1][A]	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_h2c_engine/u_data_fifo/remaining_num_9_s0

Path Statistics:

Clock Skew	0.004
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.669, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.302, 67.713%; tC2Q: 0.144, 32.287%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.673, 100.000%

Path20

Path Summary:

Slack	0.495
Data Arrival Time	1.111
Data Required Time	0.616
From	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_h2c_engine/u_descriptor_fifo/rstn_d1_s0
To	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_h2c_engine/u_data_fifo/cnt_2_s0
Launch Clk	sysclk:[R]
Latch Clk	sysclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sysclk
0.000	0.000	tCL	RR	13078	PLL_R[0]	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
0.669	0.669	tNET	RR	1	R54C111[2][A]	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_h2c_engine/u_descriptor_fifo/rstn_d1_s0/CLK
0.813	0.144	tC2Q	RR	73	R54C111[2][A]	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_h2c_engine/u_descriptor_fifo/rstn_d1_s0/Q
1.111	0.298	tNET	RR	1	R49C111[3][A]	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_h2c_engine/u_data_fifo/cnt_2_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sysclk
0.000	0.000	tCL	RR	13078	PLL_R[0]	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
0.669	0.669	tNET	RR	1	R49C111[3][A]	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_h2c_engine/u_data_fifo/cnt_2_s0/CLK
0.616	-0.053	tHld		1	R49C111[3][A]	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_h2c_engine/u_data_fifo/cnt_2_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.669, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.298, 67.421%; tC2Q: 0.144, 32.579%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.669, 100.000%

Path21

Path Summary:

Slack	0.495
Data Arrival Time	1.111
Data Required Time	0.616
From	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_h2c_engine/u_descriptor_fifo/rstn_d1_s0
To	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_h2c_engine/u_data_fifo/cnt_4_s0
Launch Clk	sysclk:[R]
Latch Clk	sysclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sysclk
0.000	0.000	tCL	RR	13078	PLL_R[0]	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
0.669	0.669	tNET	RR	1	R54C111[2][A]	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_h2c_engine/u_descriptor_fifo/rstn_d1_s0/CLK
0.813	0.144	tC2Q	RR	73	R54C111[2][A]	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_h2c_engine/u_descriptor_fifo/rstn_d1_s0/Q
1.111	0.298	tNET	RR	1	R50C111[3][A]	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_h2c_engine/u_data_fifo/cnt_4_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sysclk
0.000	0.000	tCL	RR	13078	PLL_R[0]	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
0.669	0.669	tNET	RR	1	R50C111[3][A]	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_h2c_engine/u_data_fifo/cnt_4_s0/CLK
0.616	-0.053	tHld		1	R50C111[3][A]	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_h2c_engine/u_data_fifo/cnt_4_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.669, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.298, 67.421%; tC2Q: 0.144, 32.579%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.669, 100.000%

Path22

Path Summary:

Slack	0.495
Data Arrival Time	1.115
Data Required Time	0.620
From	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_h2c_engine/u_descriptor_fifo/rstn_d1_s0
To	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_h2c_engine/u_data_fifo/cnt_8_s0
Launch Clk	sysclk:[R]
Latch Clk	sysclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sysclk
0.000	0.000	tCL	RR	13078	PLL_R[0]	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
0.669	0.669	tNET	RR	1	R54C111[2][A]	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_h2c_engine/u_descriptor_fifo/rstn_d1_s0/CLK
0.813	0.144	tC2Q	RR	73	R54C111[2][A]	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_h2c_engine/u_descriptor_fifo/rstn_d1_s0/Q
1.115	0.302	tNET	RR	1	R51C112[2][A]	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_h2c_engine/u_data_fifo/cnt_8_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sysclk
0.000	0.000	tCL	RR	13078	PLL_R[0]	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
0.673	0.673	tNET	RR	1	R51C112[2][A]	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_h2c_engine/u_data_fifo/cnt_8_s0/CLK
0.620	-0.053	tHld		1	R51C112[2][A]	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_h2c_engine/u_data_fifo/cnt_8_s0

Path Statistics:

Clock Skew	0.004
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.669, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.302, 67.713%; tC2Q: 0.144, 32.287%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.673, 100.000%

Path23

Path Summary:

Slack	0.516
Data Arrival Time	1.135
Data Required Time	0.620
From	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_descriptor_fifo/rstn_d1_s0
To	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_info_fifo/wraddr_2_s0
Launch Clk	sysclk:[R]
Latch Clk	sysclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sysclk
0.000	0.000	tCL	RR	13078	PLL_R[0]	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
0.681	0.681	tNET	RR	1	R60C73[3][A]	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_descriptor_fifo/rstn_d1_s0/CLK
0.825	0.144	tC2Q	RR	64	R60C73[3][A]	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_descriptor_fifo/rstn_d1_s0/Q
1.135	0.311	tNET	RR	1	R52C84[0][B]	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_info_fifo/wraddr_2_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sysclk
0.000	0.000	tCL	RR	13078	PLL_R[0]	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
0.673	0.673	tNET	RR	1	R52C84[0][B]	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_info_fifo/wraddr_2_s0/CLK
0.620	-0.053	tHld		1	R52C84[0][B]	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_info_fifo/wraddr_2_s0

Path Statistics:

Clock Skew	-0.008
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.681, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.311, 68.352%; tC2Q: 0.144, 31.648%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.673, 100.000%

Path24

Path Summary:

Slack	0.516
Data Arrival Time	1.135
Data Required Time	0.620
From	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_descriptor_fifo/rstn_d1_s0
To	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_info_fifo/wraddr_3_s0
Launch Clk	sysclk:[R]
Latch Clk	sysclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sysclk
0.000	0.000	tCL	RR	13078	PLL_R[0]	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
0.681	0.681	tNET	RR	1	R60C73[3][A]	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_descriptor_fifo/rstn_d1_s0/CLK
0.825	0.144	tC2Q	RR	64	R60C73[3][A]	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_descriptor_fifo/rstn_d1_s0/Q
1.135	0.311	tNET	RR	1	R52C84[0][A]	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_info_fifo/wraddr_3_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sysclk
0.000	0.000	tCL	RR	13078	PLL_R[0]	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
0.673	0.673	tNET	RR	1	R52C84[0][A]	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_info_fifo/wraddr_3_s0/CLK
0.620	-0.053	tHld		1	R52C84[0][A]	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_info_fifo/wraddr_3_s0

Path Statistics:

Clock Skew	-0.008
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.681, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.311, 68.352%; tC2Q: 0.144, 31.648%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.673, 100.000%

Path25

Path Summary:

Slack	0.517
Data Arrival Time	1.133
Data Required Time	0.616
From	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_descriptor_fifo/rstn_d1_s0
To	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_data_fifo/empty_s0
Launch Clk	sysclk:[R]
Latch Clk	sysclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sysclk
0.000	0.000	tCL	RR	13078	PLL_R[0]	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
0.681	0.681	tNET	RR	1	R60C73[3][A]	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_descriptor_fifo/rstn_d1_s0/CLK
0.825	0.144	tC2Q	RR	64	R60C73[3][A]	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_descriptor_fifo/rstn_d1_s0/Q
1.133	0.309	tNET	RR	1	R51C83[2][A]	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_data_fifo/empty_s0/PRESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sysclk
0.000	0.000	tCL	RR	13078	PLL_R[0]	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
0.669	0.669	tNET	RR	1	R51C83[2][A]	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_data_fifo/empty_s0/CLK
0.616	-0.053	tHld		1	R51C83[2][A]	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_data_fifo/empty_s0

Path Statistics:

Clock Skew	-0.012
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.681, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.309, 68.212%; tC2Q: 0.144, 31.788%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.669, 100.000%

Minimum Pulse Width Report:

Report Command:report_min_pulse_width -nworst 10 -detail

MPW1

MPW Summary:

Slack:	2.932
Actual Width:	3.794
Required Width:	0.862
Type:	Low Pulse Width
Clock:	sysclk
Objects:	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_info_fifo/mem_mem_0_2_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			sysclk
5.000	0.000	tCL	FF	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
7.080	2.080	tNET	FF	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_info_fifo/mem_mem_0_2_s/CLKB

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			sysclk
10.000	0.000	tCL	RR	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
10.874	0.874	tNET	RR	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_info_fifo/mem_mem_0_2_s/CLKB

MPW2

MPW Summary:

Slack:	2.932
Actual Width:	3.794
Required Width:	0.862
Type:	Low Pulse Width
Clock:	sysclk
Objects:	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/gowin_add_SDPX9B_mem_mem_0_0_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			sysclk
5.000	0.000	tCL	FF	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
7.080	2.080	tNET	FF	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/gowin_add_SDPX9B_mem_mem_0_0_s/CLKA

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			sysclk
10.000	0.000	tCL	RR	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
10.874	0.874	tNET	RR	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/gowin_add_SDPX9B_mem_mem_0_0_s/CLKA

MPW3

MPW Summary:

Slack:	2.932
Actual Width:	3.794
Required Width:	0.862
Type:	Low Pulse Width
Clock:	sysclk
Objects:	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/gowin_add_SDPX9B_mem_mem_0_4_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			sysclk
5.000	0.000	tCL	FF	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
7.080	2.080	tNET	FF	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/gowin_add_SDPX9B_mem_mem_0_4_s/CLKA

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			sysclk
10.000	0.000	tCL	RR	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
10.874	0.874	tNET	RR	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/gowin_add_SDPX9B_mem_mem_0_4_s/CLKA

MPW4

MPW Summary:

Slack:	2.932
Actual Width:	3.794
Required Width:	0.862
Type:	Low Pulse Width
Clock:	sysclk
Objects:	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/gowin_add_SDPX9B_mem_mem_0_10_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			sysclk
5.000	0.000	tCL	FF	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
7.080	2.080	tNET	FF	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/gowin_add_SDPX9B_mem_mem_0_10_s/CLKA

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			sysclk
10.000	0.000	tCL	RR	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
10.874	0.874	tNET	RR	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/gowin_add_SDPX9B_mem_mem_0_10_s/CLKA

MPW5

MPW Summary:

Slack:	2.932
Actual Width:	3.794
Required Width:	0.862
Type:	Low Pulse Width
Clock:	sysclk
Objects:	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/gowin_add_SDPX9B_mem_mem_0_13_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			sysclk
5.000	0.000	tCL	FF	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
7.080	2.080	tNET	FF	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/gowin_add_SDPX9B_mem_mem_0_13_s/CLKA

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			sysclk
10.000	0.000	tCL	RR	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
10.874	0.874	tNET	RR	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/gowin_add_SDPX9B_mem_mem_0_13_s/CLKA

MPW6

MPW Summary:

Slack:	2.932
Actual Width:	3.794
Required Width:	0.862
Type:	Low Pulse Width
Clock:	sysclk
Objects:	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_info_fifo/gowin_add_SDPB_mem_mem_0_1_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			sysclk
5.000	0.000	tCL	FF	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
7.080	2.080	tNET	FF	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_info_fifo/gowin_add_SDPB_mem_mem_0_1_s/CLKA

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			sysclk
10.000	0.000	tCL	RR	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
10.874	0.874	tNET	RR	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_info_fifo/gowin_add_SDPB_mem_mem_0_1_s/CLKA

MPW7

MPW Summary:

Slack:	2.934
Actual Width:	3.796
Required Width:	0.862
Type:	High Pulse Width
Clock:	sysclk
Objects:	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/gowin_add_SDPX9B_mem_mem_0_0_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			sysclk
0.000	0.000	tCL	RR	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
2.083	2.083	tNET	RR	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/gowin_add_SDPX9B_mem_mem_0_0_s/CLKA

Early clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			sysclk
5.000	0.000	tCL	FF	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
5.879	0.879	tNET	FF	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/gowin_add_SDPX9B_mem_mem_0_0_s/CLKA

MPW8

MPW Summary:

Slack:	2.934
Actual Width:	3.796
Required Width:	0.862
Type:	High Pulse Width
Clock:	sysclk
Objects:	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/gowin_add_SDPX9B_mem_mem_0_4_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			sysclk
0.000	0.000	tCL	RR	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
2.083	2.083	tNET	RR	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/gowin_add_SDPX9B_mem_mem_0_4_s/CLKA

Early clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			sysclk
5.000	0.000	tCL	FF	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
5.879	0.879	tNET	FF	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/gowin_add_SDPX9B_mem_mem_0_4_s/CLKA

MPW9

MPW Summary:

Slack:	2.934
Actual Width:	3.796
Required Width:	0.862
Type:	High Pulse Width
Clock:	sysclk
Objects:	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_info_fifo/gowin_add_SDPB_mem_mem_0_1_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			sysclk
0.000	0.000	tCL	RR	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
2.083	2.083	tNET	RR	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_info_fifo/gowin_add_SDPB_mem_mem_0_1_s/CLKA

Early clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			sysclk
5.000	0.000	tCL	FF	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
5.879	0.879	tNET	FF	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_info_fifo/gowin_add_SDPB_mem_mem_0_1_s/CLKA

MPW10

MPW Summary:

Slack:	2.934
Actual Width:	3.796
Required Width:	0.862
Type:	High Pulse Width
Clock:	sysclk
Objects:	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/gowin_add_SDPX9B_mem_mem_0_10_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			sysclk
0.000	0.000	tCL	RR	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
2.083	2.083	tNET	RR	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/gowin_add_SDPX9B_mem_mem_0_10_s/CLKA

Early clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			sysclk
5.000	0.000	tCL	FF	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
5.879	0.879	tNET	FF	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/gowin_add_SDPX9B_mem_mem_0_10_s/CLKA

High Fanout Nets Report:

Report Command:report_high_fanout_nets -max_nets 10

FANOUT	NET NAME	WORST SLACK	MAX DELAY
13078	pcie_tl_drp_clk	0.107	2.090
3332	u_dut/top/rstn	6.603	2.378
1289	gw_gao_inst_0/control0[0]	39.059	2.772
1150	pcie_rstn	4.313	2.210
557	gw_gao_inst_0/u_la0_top/n20_3	44.959	3.406
541	gw_gao_inst_0/u_la0_top/n3214_5	39.058	4.646
535	gw_gao_inst_0/u_la0_top/n3214_12	44.266	3.368
535	gw_gao_inst_0/u_la0_top/data_out_shift_reg_534_9	39.058	3.367
430	u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_h2c_engine/data_fifo_full	0.384	2.919
384	u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_c2h_data/tlp_tx_data_int_383_6	1.414	3.213

Route Congestions Report:

Report Command:report_route_congestion -max_grids 10

GRID LOC	ROUTE CONGESTIONS
R2C75	100.00%
R2C76	100.00%
R2C79	100.00%
R2C112	100.00%
R2C113	100.00%
R2C114	100.00%
R5C88	100.00%
R8C125	100.00%
R8C126	100.00%
R16C90	100.00%

Timing Exceptions Report:

Setup Analysis Report

Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Hold Analysis Report

Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Recovery Analysis Report

Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Removal Analysis Report

Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Timing Constraints Report:

SDC Command Type	State	Detail Command
TC_CLOCK	Actived	create_clock -name sysclk -period 10 -waveform {0 5} [get_pins {u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0}]
TC_CLOCK	Actived	create_clock -name tck_pad_i -period 50 -waveform {0 25} [get_ports {tck_pad_i}]
TC_CLOCK	Actived	create_clock -name clk_50m -period 20 -waveform {0 10} [get_ports {clk_50m}]
TC_CLOCK_GROUP	Actived	set_clock_groups -asynchronous -group [get_clocks {tck_pad_i}] -group [get_clocks {sysclk}]