Synthesis Messages
| Report Title | GowinSynthesis Report |
| Design File | D:\Gowin\Gowin_V1.9.12_x64\IDE\ipcore\UARTTOBUS\data\uart_bus_core_encryption.v D:\Gowin\Gowin_V1.9.12_x64\IDE\ipcore\UARTTOBUS\data\uart_to_bus_top.v |
| GowinSynthesis Constraints File | --- |
| Tool Version | V1.9.12 (64-bit) |
| Part Number | GW5AT-LV60UG225C2/I1 |
| Device | GW5AT-60 |
| Device Version | B |
| Created Time | Mon Nov 3 16:39:51 2025 |
| Legal Announcement | Copyright (C)2014-2025 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
| Top Level Module | Uart_to_Bus_Top |
| Synthesis Process | Running parser: CPU time = 0h 0m 0.218s, Elapsed time = 0h 0m 0.247s, Peak memory usage = 89.230MB Running netlist conversion: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.01s, Peak memory usage = 89.230MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.043s, Peak memory usage = 89.230MB Optimizing Phase 1: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.019s, Peak memory usage = 89.230MB Optimizing Phase 2: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.043s, Peak memory usage = 89.230MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.027s, Peak memory usage = 89.230MB Inferring Phase 1: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.033s, Peak memory usage = 89.230MB Inferring Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.01s, Peak memory usage = 89.230MB Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 89.230MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0.109s, Elapsed time = 0h 0m 0.099s, Peak memory usage = 89.230MB Tech-Mapping Phase 1: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.031s, Peak memory usage = 89.230MB Tech-Mapping Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.022s, Peak memory usage = 89.230MB Tech-Mapping Phase 3: CPU time = 0h 0m 0.937s, Elapsed time = 0h 0m 0.976s, Peak memory usage = 114.613MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.11s, Peak memory usage = 114.613MB Generate output files: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.106s, Peak memory usage = 114.613MB |
| Total Time and Memory Usage | CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 114.613MB |
Resource
Resource Usage Summary
| Resource | Usage |
| I/O Port | 90 |
| I/O Buf | 90 |
| IBUF | 37 |
| OBUF | 53 |
| Register | 1438 |
| DFFRE | 839 |
| DFFPE | 9 |
| DFFCE | 590 |
| LUT | 960 |
| LUT2 | 99 |
| LUT3 | 633 |
| LUT4 | 228 |
| ALU | 40 |
| ALU | 40 |
| INV | 11 |
| INV | 11 |
Resource Utilization Summary
| Resource | Usage | Utilization |
| Logic | 1011(971 LUT, 40 ALU) / 59904 | 2% |
| Register | 1438 / 60228 | 3% |
| --Register as Latch | 0 / 60228 | 0% |
| --Register as FF | 1438 / 60228 | 3% |
| BSRAM | 0 / 118 | 0% |
Timing
Clock Summary:
| NO. | Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
|---|---|---|---|---|---|---|---|---|---|
| 1 | clk_i | Base | 10.000 | 100.000 | 0.000 | 5.000 | clk_i_ibuf/I |
Max Frequency Summary:
| NO. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
|---|---|---|---|---|---|
| 1 | clk_i | 100.000(MHz) | 180.440(MHz) | 7 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:| Slack | 4.458 |
| Data Arrival Time | 5.791 |
| Data Required Time | 10.249 |
| From | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_fifo_rdata_reg_25_s0 |
| To | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_4_s1 |
| Launch Clk | clk_i[R] |
| Latch Clk | clk_i[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | clk_i | |||
| 0.000 | 0.000 | tCL | RR | 1 | clk_i_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 1438 | clk_i_ibuf/O |
| 0.300 | 0.300 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_fifo_rdata_reg_25_s0/CLK |
| 0.606 | 0.306 | tC2Q | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_fifo_rdata_reg_25_s0/Q |
| 0.906 | 0.300 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n194_s6/I0 |
| 1.327 | 0.421 | tINS | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n194_s6/F |
| 1.627 | 0.300 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n194_s2/I1 |
| 1.736 | 0.109 | tINS | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n194_s2/O |
| 2.036 | 0.300 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n194_s0/I1 |
| 2.105 | 0.069 | tINS | RR | 3 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n194_s0/O |
| 2.405 | 0.300 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n741_s47/I1 |
| 2.818 | 0.413 | tINS | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n741_s47/F |
| 3.118 | 0.300 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n741_s43/I0 |
| 3.539 | 0.421 | tINS | RR | 3 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n741_s43/F |
| 3.839 | 0.300 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n738_s44/I3 |
| 4.049 | 0.210 | tINS | RR | 5 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n738_s44/F |
| 4.349 | 0.300 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n740_s51/I0 |
| 4.770 | 0.421 | tINS | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n740_s51/F |
| 5.070 | 0.300 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n740_s54/I0 |
| 5.491 | 0.421 | tINS | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n740_s54/F |
| 5.791 | 0.300 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_4_s1/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | clk_i | |||
| 10.000 | 0.000 | tCL | RR | 1 | clk_i_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 1438 | clk_i_ibuf/O |
| 10.300 | 0.300 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_4_s1/CLK |
| 10.249 | -0.051 | tSu | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_4_s1 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 7 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.300, 100.000% |
| Arrival Data Path Delay: | cell: 2.485, 45.256%; route: 2.700, 49.171%; tC2Q: 0.306, 5.573% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.300, 100.000% |
Path 2
Path Summary:| Slack | 4.466 |
| Data Arrival Time | 5.783 |
| Data Required Time | 10.249 |
| From | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_fifo_rdata_reg_25_s0 |
| To | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_5_s1 |
| Launch Clk | clk_i[R] |
| Latch Clk | clk_i[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | clk_i | |||
| 0.000 | 0.000 | tCL | RR | 1 | clk_i_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 1438 | clk_i_ibuf/O |
| 0.300 | 0.300 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_fifo_rdata_reg_25_s0/CLK |
| 0.606 | 0.306 | tC2Q | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_fifo_rdata_reg_25_s0/Q |
| 0.906 | 0.300 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n194_s6/I0 |
| 1.327 | 0.421 | tINS | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n194_s6/F |
| 1.627 | 0.300 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n194_s2/I1 |
| 1.736 | 0.109 | tINS | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n194_s2/O |
| 2.036 | 0.300 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n194_s0/I1 |
| 2.105 | 0.069 | tINS | RR | 3 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n194_s0/O |
| 2.405 | 0.300 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n741_s47/I1 |
| 2.818 | 0.413 | tINS | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n741_s47/F |
| 3.118 | 0.300 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n741_s43/I0 |
| 3.539 | 0.421 | tINS | RR | 3 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n741_s43/F |
| 3.839 | 0.300 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n738_s44/I3 |
| 4.049 | 0.210 | tINS | RR | 5 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n738_s44/F |
| 4.349 | 0.300 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n739_s60/I0 |
| 4.770 | 0.421 | tINS | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n739_s60/F |
| 5.070 | 0.300 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n739_s58/I1 |
| 5.483 | 0.413 | tINS | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n739_s58/F |
| 5.783 | 0.300 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_5_s1/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | clk_i | |||
| 10.000 | 0.000 | tCL | RR | 1 | clk_i_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 1438 | clk_i_ibuf/O |
| 10.300 | 0.300 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_5_s1/CLK |
| 10.249 | -0.051 | tSu | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_5_s1 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 7 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.300, 100.000% |
| Arrival Data Path Delay: | cell: 2.477, 45.176%; route: 2.700, 49.243%; tC2Q: 0.306, 5.581% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.300, 100.000% |
Path 3
Path Summary:| Slack | 4.466 |
| Data Arrival Time | 5.783 |
| Data Required Time | 10.249 |
| From | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_fifo_rdata_reg_25_s0 |
| To | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_0_s0 |
| Launch Clk | clk_i[R] |
| Latch Clk | clk_i[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | clk_i | |||
| 0.000 | 0.000 | tCL | RR | 1 | clk_i_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 1438 | clk_i_ibuf/O |
| 0.300 | 0.300 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_fifo_rdata_reg_25_s0/CLK |
| 0.606 | 0.306 | tC2Q | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_fifo_rdata_reg_25_s0/Q |
| 0.906 | 0.300 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n194_s6/I0 |
| 1.327 | 0.421 | tINS | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n194_s6/F |
| 1.627 | 0.300 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n194_s2/I1 |
| 1.736 | 0.109 | tINS | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n194_s2/O |
| 2.036 | 0.300 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n194_s0/I1 |
| 2.105 | 0.069 | tINS | RR | 3 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n194_s0/O |
| 2.405 | 0.300 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n741_s47/I1 |
| 2.818 | 0.413 | tINS | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n741_s47/F |
| 3.118 | 0.300 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n741_s43/I0 |
| 3.539 | 0.421 | tINS | RR | 3 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n741_s43/F |
| 3.839 | 0.300 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n738_s44/I3 |
| 4.049 | 0.210 | tINS | RR | 5 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n738_s44/F |
| 4.349 | 0.300 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n744_s40/I1 |
| 4.762 | 0.413 | tINS | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n744_s40/F |
| 5.062 | 0.300 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n744_s39/I0 |
| 5.483 | 0.421 | tINS | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n744_s39/F |
| 5.783 | 0.300 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_0_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | clk_i | |||
| 10.000 | 0.000 | tCL | RR | 1 | clk_i_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 1438 | clk_i_ibuf/O |
| 10.300 | 0.300 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_0_s0/CLK |
| 10.249 | -0.051 | tSu | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_0_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 7 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.300, 100.000% |
| Arrival Data Path Delay: | cell: 2.477, 45.176%; route: 2.700, 49.243%; tC2Q: 0.306, 5.581% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.300, 100.000% |
Path 4
Path Summary:| Slack | 4.466 |
| Data Arrival Time | 5.783 |
| Data Required Time | 10.249 |
| From | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_fifo_rdata_reg_25_s0 |
| To | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_6_s0 |
| Launch Clk | clk_i[R] |
| Latch Clk | clk_i[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | clk_i | |||
| 0.000 | 0.000 | tCL | RR | 1 | clk_i_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 1438 | clk_i_ibuf/O |
| 0.300 | 0.300 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_fifo_rdata_reg_25_s0/CLK |
| 0.606 | 0.306 | tC2Q | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_fifo_rdata_reg_25_s0/Q |
| 0.906 | 0.300 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n194_s6/I0 |
| 1.327 | 0.421 | tINS | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n194_s6/F |
| 1.627 | 0.300 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n194_s2/I1 |
| 1.736 | 0.109 | tINS | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n194_s2/O |
| 2.036 | 0.300 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n194_s0/I1 |
| 2.105 | 0.069 | tINS | RR | 3 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n194_s0/O |
| 2.405 | 0.300 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n741_s47/I1 |
| 2.818 | 0.413 | tINS | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n741_s47/F |
| 3.118 | 0.300 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n741_s43/I0 |
| 3.539 | 0.421 | tINS | RR | 3 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n741_s43/F |
| 3.839 | 0.300 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n738_s44/I3 |
| 4.049 | 0.210 | tINS | RR | 5 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n738_s44/F |
| 4.349 | 0.300 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n738_s40/I1 |
| 4.762 | 0.413 | tINS | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n738_s40/F |
| 5.062 | 0.300 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n738_s39/I0 |
| 5.483 | 0.421 | tINS | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n738_s39/F |
| 5.783 | 0.300 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_6_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | clk_i | |||
| 10.000 | 0.000 | tCL | RR | 1 | clk_i_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 1438 | clk_i_ibuf/O |
| 10.300 | 0.300 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_6_s0/CLK |
| 10.249 | -0.051 | tSu | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_6_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 7 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.300, 100.000% |
| Arrival Data Path Delay: | cell: 2.477, 45.176%; route: 2.700, 49.243%; tC2Q: 0.306, 5.581% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.300, 100.000% |
Path 5
Path Summary:| Slack | 5.020 |
| Data Arrival Time | 5.229 |
| Data Required Time | 10.249 |
| From | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_fifo_rdata_reg_25_s0 |
| To | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_3_s0 |
| Launch Clk | clk_i[R] |
| Latch Clk | clk_i[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | clk_i | |||
| 0.000 | 0.000 | tCL | RR | 1 | clk_i_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 1438 | clk_i_ibuf/O |
| 0.300 | 0.300 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_fifo_rdata_reg_25_s0/CLK |
| 0.606 | 0.306 | tC2Q | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_fifo_rdata_reg_25_s0/Q |
| 0.906 | 0.300 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n194_s6/I0 |
| 1.327 | 0.421 | tINS | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n194_s6/F |
| 1.627 | 0.300 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n194_s2/I1 |
| 1.736 | 0.109 | tINS | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n194_s2/O |
| 2.036 | 0.300 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n194_s0/I1 |
| 2.105 | 0.069 | tINS | RR | 3 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n194_s0/O |
| 2.405 | 0.300 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n741_s47/I1 |
| 2.818 | 0.413 | tINS | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n741_s47/F |
| 3.118 | 0.300 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n741_s43/I0 |
| 3.539 | 0.421 | tINS | RR | 3 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n741_s43/F |
| 3.839 | 0.300 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n741_s41/I0 |
| 4.260 | 0.421 | tINS | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n741_s41/F |
| 4.560 | 0.300 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n741_s39/I2 |
| 4.929 | 0.369 | tINS | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n741_s39/F |
| 5.229 | 0.300 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_3_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | clk_i | |||
| 10.000 | 0.000 | tCL | RR | 1 | clk_i_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 1438 | clk_i_ibuf/O |
| 10.300 | 0.300 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_3_s0/CLK |
| 10.249 | -0.051 | tSu | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_3_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 6 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.300, 100.000% |
| Arrival Data Path Delay: | cell: 2.223, 45.100%; route: 2.400, 48.692%; tC2Q: 0.306, 6.208% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.300, 100.000% |