Power Messages

Report Title	Power Analysis Report
Design File	E:\myWork\IP\releaseVerify\version\1.9.12.01\Gowin_PCIe_SGDMA\Gowin_PCIe_SGDMA_RefDesign\project\impl\gwsynthesis\fpga_project.vg
Physical Constraints File	E:\myWork\IP\releaseVerify\version\1.9.12.01\Gowin_PCIe_SGDMA\Gowin_PCIe_SGDMA_RefDesign\project\src\fpga_project.cst
Timing Constraints File	E:\myWork\IP\releaseVerify\version\1.9.12.01\Gowin_PCIe_SGDMA\Gowin_PCIe_SGDMA_RefDesign\project\src\fpga_project.sdc
Tool Version	V1.9.12.01 (64-bit)
Part Number	GW5AT-LV60UG225C2/I1
Device	GW5AT-60
Device Version	B
Created Time	Wed Jan 7 17:12:54 2026
Legal Announcement	Copyright (C)2014-2025 Gowin Semiconductor Corporation. All rights reserved.

Configure Information:

Grade	Commercial
Process	Typical
Ambient Temperature	25.000
Use Custom Theta JA	false
Heat Sink	None
Air Flow	LFM_0
Use Custom Theta SA	false
Board Thermal Model	None
Use Custom Theta JB	false
Related Vcd File
Related Saif File
Filter Glitches	false
Default IO Toggle Rate	0.125
Default Remain Toggle Rate	0.125

Power Summary

Power Information:

Total Power (mW)	525.691
Quiescent Power (mW)	91.683
Dynamic Power (mW)	434.007

Thermal Information:

Junction Temperature	34.909
Theta JA	18.850
Max Allowed Ambient Temperature	75.091

Supply Information:

Voltage Source	Voltage	Dynamic Current(mA)	Quiescent Current(mA)	Power(mW)
VCC	0.900	479.041	80.005	503.141
VCCX	3.300	0.450	5.000	17.984
VCCIO18	1.800	0.061	0.100	0.290
VCCIO33	3.300	0.387	0.909	4.275

Power Details

Power By Block Type:

Block Type	Total Power(mW)	Static Power(mW)	Average Toggle Rate(millions of transitions/sec)
Logic	9.536	NA	11.650
IO	7.402	4.137	33.250
BSRAM	411.546	NA	NA
PLL	9.648	NA	NA

Power By Hierarchy:

Hierarchy Entity	Total Power(mW)	Block Dynamic Power(mW)
test_top	430.731	430.731(430.684)
test_top/gw_gao_inst_0/	98.924	98.924(98.924)
test_top/gw_gao_inst_0/u_icon_top/	0.002	0.002(0.000)
test_top/gw_gao_inst_0/u_la0_top/	98.922	98.922(98.799)
test_top/gw_gao_inst_0/u_la0_top/u_ao_crc32/	0.004	0.004(0.000)
test_top/gw_gao_inst_0/u_la0_top/u_ao_match_0/	0.006	0.006(0.000)
test_top/gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/	98.789	98.789(0.000)
test_top/u_Gowin_PLL/	9.968	9.968(9.968)
test_top/u_Gowin_PLL/u_pll/	9.648	9.648(0.000)
test_top/u_Gowin_PLL/u_pll_init/	0.320	0.320(0.000)
test_top/u_PCIe_IP/	0.171	0.171(0.171)
test_top/u_PCIe_IP/PCIE_Controller_Top_inst/	0.043	0.043(0.043)
test_top/u_PCIe_IP/PCIE_Controller_Top_inst/u_pcie_controller/	0.043	0.043(0.042)
test_top/u_PCIe_IP/PCIE_Controller_Top_inst/u_pcie_controller/u_pcie_st/	0.021	0.021(0.000)
test_top/u_PCIe_IP/PCIE_Controller_Top_inst/u_pcie_controller/u_rstn/	0.021	0.021(0.000)
test_top/u_PCIe_IP/upar_arbiter_wrap_SerDes_Top_inst/	0.127	0.127(0.127)
test_top/u_PCIe_IP/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/	0.127	0.127(0.000)
test_top/u_Uart_to_Bus_Top/	0.709	0.709(0.709)
test_top/u_Uart_to_Bus_Top/uart_bus_core/	0.709	0.709(0.654)
test_top/u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/	0.654	0.654(0.654)
test_top/u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/	0.025	0.025(0.000)
test_top/u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_rx_md/	0.311	0.311(0.311)
test_top/u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_parser_rx_md/	0.285	0.285(0.221)
test_top/u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_parser_rx_md/u_uart_rx_async_fifo/	0.221	0.221(0.000)
test_top/u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_serial_rx_md/	0.026	0.026(0.000)
test_top/u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_tx_md/	0.318	0.318(0.318)
test_top/u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/	0.286	0.286(0.228)
test_top/u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/u_uart_tx_async_fifo/	0.228	0.228(0.000)
test_top/u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_serial_tx_md/	0.032	0.032(0.000)
test_top/u_dut/	318.493	318.493(318.493)
test_top/u_dut/top/	318.493	318.493(318.493)
test_top/u_dut/top/u_common_control/	0.003	0.003(0.000)
test_top/u_dut/top/u_cpld_rx_demux/	0.053	0.053(0.000)
test_top/u_dut/top/u_dma/	317.248	317.248(317.248)
test_top/u_dut/top/u_dma/u_c2h_all_engines/	174.748	174.748(174.748)
test_top/u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/	174.184	174.184(174.184)
test_top/u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_c2h_data/	1.118	1.118(0.000)
test_top/u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_c2h_descriptor/	0.418	0.418(0.000)
test_top/u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_c2h_engine_tlp_tx_mux/	0.152	0.152(0.000)
test_top/u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_c2h_stream_if/	0.226	0.226(0.000)
test_top/u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_data_fifo/	86.153	86.153(0.000)
test_top/u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_descriptor_fifo/	53.816	53.816(0.000)
test_top/u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_info_fifo/	32.299	32.299(0.000)
test_top/u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_c2h_engine/u_reset_fifo/	0.001	0.001(0.000)
test_top/u_dut/top/u_dma/u_c2h_all_engines/multi_engines_gen[0].u_dma_target_regs/	0.166	0.166(0.000)
test_top/u_dut/top/u_dma/u_c2h_all_engines/u_c2h_all_engine_tlp_rx_demux/	0.047	0.047(0.000)
test_top/u_dut/top/u_dma/u_c2h_all_engines/u_c2h_all_engines_tlp_tx_mux/	0.150	0.150(0.001)
test_top/u_dut/top/u_dma/u_c2h_all_engines/u_c2h_all_engines_tlp_tx_mux/u_round_robin_arbiter/	0.001	0.001(0.000)
test_top/u_dut/top/u_dma/u_c2h_all_engines/u_vld_rdy_pipe/	0.201	0.201(0.000)
test_top/u_dut/top/u_dma/u_control_regs/	0.011	0.011(0.000)
test_top/u_dut/top/u_dma/u_h2c_all_engines/	142.327	142.327(142.327)
test_top/u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_dma_target_regs/	0.172	0.172(0.000)
test_top/u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_h2c_engine/	141.970	141.970(141.970)
test_top/u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_h2c_engine/u_data_fifo/	86.158	86.158(0.000)
test_top/u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_h2c_engine/u_descriptor_fifo/	43.836	43.836(0.000)
test_top/u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_h2c_engine/u_h2c_data/	0.576	0.576(0.000)
test_top/u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_h2c_engine/u_h2c_descriptor/	0.412	0.412(0.000)
test_top/u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_h2c_engine/u_h2c_engine_tlp_rx_demux/	0.054	0.054(0.000)
test_top/u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_h2c_engine/u_h2c_engine_tlp_tx_mux/	0.056	0.056(0.000)
test_top/u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_h2c_engine/u_h2c_stream_if/	0.090	0.090(0.000)
test_top/u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_h2c_engine/u_info_fifo/	10.786	10.786(0.000)
test_top/u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_h2c_engine/u_reset_fifo/	0.001	0.001(0.000)
test_top/u_dut/top/u_dma/u_h2c_all_engines/u_c2h_all_engine_tlp_rx_demux/	0.052	0.052(0.000)
test_top/u_dut/top/u_dma/u_h2c_all_engines/u_c2h_all_engines_tlp_tx_mux/	0.056	0.056(0.001)
test_top/u_dut/top/u_dma/u_h2c_all_engines/u_c2h_all_engines_tlp_tx_mux/u_round_robin_arbiter/	0.001	0.001(0.000)
test_top/u_dut/top/u_dma/u_h2c_all_engines/u_vld_rdy_pipe/	0.077	0.077(0.000)
test_top/u_dut/top/u_dma/u_irq_regs/	0.043	0.043(0.000)
test_top/u_dut/top/u_dma/u_poll_mode_tlp_tx/	0.080	0.080(0.001)
test_top/u_dut/top/u_dma/u_poll_mode_tlp_tx/u_round_robin_arbiter/	0.001	0.001(0.000)
test_top/u_dut/top/u_dma/u_target_rx_bar0_cs_gen/	0.021	0.021(0.000)
test_top/u_dut/top/u_dma/u_target_tx_mux/	0.018	0.018(0.000)
test_top/u_dut/top/u_irq_gen/	0.003	0.003(0.001)
test_top/u_dut/top/u_irq_gen/u_round_robin_arbiter/	0.001	0.001(0.000)
test_top/u_dut/top/u_pcie_cfg_space_rd/	0.032	0.032(0.000)
test_top/u_dut/top/u_target_op2tx/	0.049	0.049(0.000)
test_top/u_dut/top/u_target_rx2op/	0.116	0.116(0.000)
test_top/u_dut/top/u_target_user_if/	0.008	0.008(0.000)
test_top/u_dut/top/u_tlp_rx_demux/	0.553	0.553(0.498)
test_top/u_dut/top/u_tlp_rx_demux/u_cpld_rx_pipe/	0.197	0.197(0.000)
test_top/u_dut/top/u_tlp_rx_demux/u_pcie_tl_rx_pipe/	0.198	0.198(0.000)
test_top/u_dut/top/u_tlp_rx_demux/u_target_rx_pipe/	0.103	0.103(0.000)
test_top/u_dut/top/u_tlp_tx_mux/	0.426	0.426(0.207)
test_top/u_dut/top/u_tlp_tx_mux/u_round_robin_arbiter/	0.005	0.005(0.000)
test_top/u_dut/top/u_tlp_tx_mux/u_vld_rdy_pipe/	0.201	0.201(0.000)
test_top/u_user_stream_if_monitor/	2.418	2.418(0.000)

Power By Clock Domain:

Clock Domain	Clock Frequency(Mhz)	Total Dynamic Power(mW)
clk_50m	50.000	0.321
tck_pad_i	20.000	16.539
sysclk	100.000	404.235
NO CLOCK DOMAIN	0.000	0.000
clk_200m_p	200.000	9.648