Synthesis Messages
| Report Title | GowinSynthesis Report |
| Design File | E:\myWork\IP\releaseVerify\version\1.9.12.01\Gowin_PCIe_SGDMA\Gowin_PCIe_SGDMA_RefDesign\project\src\Pcie_Sgdma\Pcie_Sgdma.v E:\myWork\IP\releaseVerify\version\1.9.12.01\Gowin_PCIe_SGDMA\Gowin_PCIe_SGDMA_RefDesign\project\src\gowin_pll\gowin_pll.v E:\myWork\IP\releaseVerify\version\1.9.12.01\Gowin_PCIe_SGDMA\Gowin_PCIe_SGDMA_RefDesign\project\src\gowin_pll\gowin_pll_mod.v E:\myWork\IP\releaseVerify\version\1.9.12.01\Gowin_PCIe_SGDMA\Gowin_PCIe_SGDMA_RefDesign\project\src\pll_init.v E:\myWork\IP\releaseVerify\version\1.9.12.01\Gowin_PCIe_SGDMA\Gowin_PCIe_SGDMA_RefDesign\project\src\serdes\pcie_controller\pcie_controller.v E:\myWork\IP\releaseVerify\version\1.9.12.01\Gowin_PCIe_SGDMA\Gowin_PCIe_SGDMA_RefDesign\project\src\serdes\serdes.v E:\myWork\IP\releaseVerify\version\1.9.12.01\Gowin_PCIe_SGDMA\Gowin_PCIe_SGDMA_RefDesign\project\src\serdes\upar_arbiter\upar_arbiter.v E:\myWork\IP\releaseVerify\version\1.9.12.01\Gowin_PCIe_SGDMA\Gowin_PCIe_SGDMA_RefDesign\project\src\test_top.v E:\myWork\IP\releaseVerify\version\1.9.12.01\Gowin_PCIe_SGDMA\Gowin_PCIe_SGDMA_RefDesign\project\src\uart_to_bus\uart_to_bus.v E:\myWork\IP\releaseVerify\version\1.9.12.01\Gowin_PCIe_SGDMA\Gowin_PCIe_SGDMA_RefDesign\project\src\user_stream_if_monitor.v C:\Gowin\Gowin_V1.9.12.01_x64_internal\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_crc32.v C:\Gowin\Gowin_V1.9.12.01_x64_internal\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_match.v C:\Gowin\Gowin_V1.9.12.01_x64_internal\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_mem_ctrl.v C:\Gowin\Gowin_V1.9.12.01_x64_internal\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_top.v C:\Gowin\Gowin_V1.9.12.01_x64_internal\IDE\data\ipcores\GAO\GW_CON\gw_con_top.v C:\Gowin\Gowin_V1.9.12.01_x64_internal\IDE\data\ipcores\gw_jtag.v E:\myWork\IP\releaseVerify\version\1.9.12.01\Gowin_PCIe_SGDMA\Gowin_PCIe_SGDMA_RefDesign\project\impl\gwsynthesis\RTL_GAO\gw_gao_top.v |
| GowinSynthesis Constraints File | --- |
| Tool Version | V1.9.12.01 (64-bit) |
| Part Number | GW5AT-LV60UG225C2/I1 |
| Device | GW5AT-60 |
| Device Version | B |
| Created Time | Wed Jan 7 17:10:40 2026 |
| Legal Announcement | Copyright (C)2014-2025 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
| Top Level Module | test_top |
| Synthesis Process | Running parser: CPU time = 0h 0m 4s, Elapsed time = 0h 0m 4s, Peak memory usage = 426.637MB Running netlist conversion: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s, Peak memory usage = 426.637MB Optimizing Phase 1: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 426.637MB Optimizing Phase 2: CPU time = 0h 0m 4s, Elapsed time = 0h 0m 3s, Peak memory usage = 426.637MB Running inference: Inferring Phase 0: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 426.637MB Inferring Phase 1: CPU time = 0h 0m 0.234s, Elapsed time = 0h 0m 0.239s, Peak memory usage = 426.637MB Inferring Phase 2: CPU time = 0h 0m 0.203s, Elapsed time = 0h 0m 0.208s, Peak memory usage = 426.637MB Inferring Phase 3: CPU time = 0h 0m 0.14s, Elapsed time = 0h 0m 0.145s, Peak memory usage = 426.637MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 2s, Elapsed time = 0h 0m 1s, Peak memory usage = 426.637MB Tech-Mapping Phase 1: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 426.637MB Tech-Mapping Phase 2: CPU time = 0h 0m 0.296s, Elapsed time = 0h 0m 0.27s, Peak memory usage = 426.637MB Tech-Mapping Phase 3: CPU time = 0h 0m 12s, Elapsed time = 0h 0m 12s, Peak memory usage = 426.637MB Tech-Mapping Phase 4: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 426.637MB Generate output files: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 493.148MB |
| Total Time and Memory Usage | CPU time = 0h 0m 29s, Elapsed time = 0h 0m 27s, Peak memory usage = 493.148MB |
Resource
Resource Usage Summary
| Resource | Usage |
| I/O Port | 11 |
| I/O Buf | 10 |
| IBUF | 6 |
| OBUF | 2 |
| TBUF | 1 |
| TLVDS_IBUF | 1 |
| Register | 14287 |
| DFFSE | 26 |
| DFFRE | 1112 |
| DFFPE | 86 |
| DFFCE | 13063 |
| LUT | 11007 |
| LUT2 | 1532 |
| LUT3 | 2695 |
| LUT4 | 6780 |
| MUX | 1 |
| MUX16 | 1 |
| ALU | 1423 |
| ALU | 1423 |
| INV | 35 |
| INV | 35 |
| BSRAM | 45 |
| SDPB | 25 |
| SDPX9B | 19 |
| pROM | 1 |
| CLOCK | 1 |
| PLLA | 1 |
| Black Box | 4 |
| GW_JTAG | 1 |
| GTR12_QUADA | 1 |
| GTR12_UPARA | 1 |
| GTR12_PMACA | 1 |
Resource Utilization Summary
| Resource | Usage | Utilization |
| Logic | 12473(11050 LUT, 1423 ALU) / 59904 | 21% |
| Register | 14287 / 60228 | 24% |
| --Register as Latch | 0 / 60228 | 0% |
| --Register as FF | 14287 / 60228 | 24% |
| BSRAM | 45 / 118 | 39% |
Timing
Clock Summary:
| NO. | Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
|---|---|---|---|---|---|---|---|---|---|
| 1 | clk_200m_p | Base | 5.000 | 200.000 | 0.000 | 2.500 | u_TLVDS_IBUF/I | ||
| 2 | clk_50m | Base | 10.000 | 100.000 | 0.000 | 5.000 | clk_50m_ibuf/I | ||
| 3 | gw_gao_inst_0/u_icon_top/n19_6 | Base | 10.000 | 100.000 | 0.000 | 5.000 | gw_gao_inst_0/u_icon_top/n19_s2/F | ||
| 4 | u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0.default_gen_clk | Generated | 10.000 | 100.000 | 0.000 | 5.000 | u_TLVDS_IBUF/I | clk_200m_p | u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0 |
Max Frequency Summary:
| NO. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
|---|---|---|---|---|---|
| 1 | clk_50m | 100.000(MHz) | 191.791(MHz) | 8 | TOP |
| 2 | gw_gao_inst_0/u_icon_top/n19_6 | 100.000(MHz) | 1522.071(MHz) | 1 | TOP |
| 3 | u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0.default_gen_clk | 100.000(MHz) | 108.578(MHz) | 16 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:| Slack | 0.790 |
| Data Arrival Time | 9.703 |
| Data Required Time | 10.493 |
| From | u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_h2c_engine/u_h2c_stream_if/m_axis_h2c_tkeep_tmp_23_s1 |
| To | u_user_stream_if_monitor/h2c_one_packet_byte_cnt_29_s1 |
| Launch Clk | u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0.default_gen_clk[R] |
| Latch Clk | u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0.default_gen_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0.default_gen_clk | |||
| 0.244 | 0.244 | tCL | RR | 13001 | u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0 |
| 0.544 | 0.300 | tNET | RR | 1 | u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_h2c_engine/u_h2c_stream_if/m_axis_h2c_tkeep_tmp_23_s1/CLK |
| 0.850 | 0.306 | tC2Q | RR | 5 | u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_h2c_engine/u_h2c_stream_if/m_axis_h2c_tkeep_tmp_23_s1/Q |
| 1.150 | 0.300 | tNET | RR | 1 | u_user_stream_if_monitor/n2653_s59/I0 |
| 1.571 | 0.421 | tINS | RR | 3 | u_user_stream_if_monitor/n2653_s59/F |
| 1.871 | 0.300 | tNET | RR | 1 | u_user_stream_if_monitor/n2652_s34/I1 |
| 2.284 | 0.413 | tINS | RR | 1 | u_user_stream_if_monitor/n2652_s34/F |
| 2.584 | 0.300 | tNET | RR | 1 | u_user_stream_if_monitor/n2652_s31/I2 |
| 2.953 | 0.369 | tINS | RR | 1 | u_user_stream_if_monitor/n2652_s31/F |
| 3.253 | 0.300 | tNET | RR | 1 | u_user_stream_if_monitor/n2652_s38/I3 |
| 3.463 | 0.210 | tINS | RR | 2 | u_user_stream_if_monitor/n2652_s38/F |
| 3.763 | 0.300 | tNET | RR | 1 | u_user_stream_if_monitor/n2651_s15/I1 |
| 4.176 | 0.413 | tINS | RR | 1 | u_user_stream_if_monitor/n2651_s15/F |
| 4.476 | 0.300 | tNET | RR | 2 | u_user_stream_if_monitor/n2651_s10/I1 |
| 4.926 | 0.450 | tINS | RF | 1 | u_user_stream_if_monitor/n2651_s10/COUT |
| 4.926 | 0.000 | tNET | FF | 2 | u_user_stream_if_monitor/n2650_s10/CIN |
| 5.121 | 0.195 | tINS | FR | 1 | u_user_stream_if_monitor/n2650_s10/SUM |
| 5.421 | 0.300 | tNET | RR | 2 | u_user_stream_if_monitor/n2650_s12/I0 |
| 5.866 | 0.445 | tINS | RF | 1 | u_user_stream_if_monitor/n2650_s12/COUT |
| 5.866 | 0.000 | tNET | FF | 2 | u_user_stream_if_monitor/n2649_s12/CIN |
| 6.061 | 0.195 | tINS | FR | 1 | u_user_stream_if_monitor/n2649_s12/SUM |
| 6.361 | 0.300 | tNET | RR | 2 | u_user_stream_if_monitor/n2649_s14/I0 |
| 6.806 | 0.445 | tINS | RF | 1 | u_user_stream_if_monitor/n2649_s14/COUT |
| 6.806 | 0.000 | tNET | FF | 2 | u_user_stream_if_monitor/n2648_s14/CIN |
| 6.846 | 0.040 | tINS | FR | 1 | u_user_stream_if_monitor/n2648_s14/COUT |
| 6.846 | 0.000 | tNET | RR | 2 | u_user_stream_if_monitor/n2647_s14/CIN |
| 6.886 | 0.040 | tINS | RR | 1 | u_user_stream_if_monitor/n2647_s14/COUT |
| 6.886 | 0.000 | tNET | RR | 2 | u_user_stream_if_monitor/n2646_s14/CIN |
| 6.926 | 0.040 | tINS | RR | 1 | u_user_stream_if_monitor/n2646_s14/COUT |
| 6.926 | 0.000 | tNET | RR | 2 | u_user_stream_if_monitor/n2645_s14/CIN |
| 6.966 | 0.040 | tINS | RR | 1 | u_user_stream_if_monitor/n2645_s14/COUT |
| 6.966 | 0.000 | tNET | RR | 2 | u_user_stream_if_monitor/n2644_s14/CIN |
| 7.006 | 0.040 | tINS | RR | 1 | u_user_stream_if_monitor/n2644_s14/COUT |
| 7.006 | 0.000 | tNET | RR | 2 | u_user_stream_if_monitor/n2643_s14/CIN |
| 7.046 | 0.040 | tINS | RR | 1 | u_user_stream_if_monitor/n2643_s14/COUT |
| 7.046 | 0.000 | tNET | RR | 2 | u_user_stream_if_monitor/n2642_s14/CIN |
| 7.086 | 0.040 | tINS | RR | 1 | u_user_stream_if_monitor/n2642_s14/COUT |
| 7.086 | 0.000 | tNET | RR | 2 | u_user_stream_if_monitor/n2641_s14/CIN |
| 7.126 | 0.040 | tINS | RR | 1 | u_user_stream_if_monitor/n2641_s14/COUT |
| 7.126 | 0.000 | tNET | RR | 2 | u_user_stream_if_monitor/n2640_s14/CIN |
| 7.166 | 0.040 | tINS | RR | 1 | u_user_stream_if_monitor/n2640_s14/COUT |
| 7.166 | 0.000 | tNET | RR | 2 | u_user_stream_if_monitor/n2639_s14/CIN |
| 7.206 | 0.040 | tINS | RR | 1 | u_user_stream_if_monitor/n2639_s14/COUT |
| 7.206 | 0.000 | tNET | RR | 2 | u_user_stream_if_monitor/n2638_s14/CIN |
| 7.246 | 0.040 | tINS | RR | 1 | u_user_stream_if_monitor/n2638_s14/COUT |
| 7.246 | 0.000 | tNET | RR | 2 | u_user_stream_if_monitor/n2637_s14/CIN |
| 7.286 | 0.040 | tINS | RR | 1 | u_user_stream_if_monitor/n2637_s14/COUT |
| 7.286 | 0.000 | tNET | RR | 2 | u_user_stream_if_monitor/n2636_s14/CIN |
| 7.326 | 0.040 | tINS | RR | 1 | u_user_stream_if_monitor/n2636_s14/COUT |
| 7.326 | 0.000 | tNET | RR | 2 | u_user_stream_if_monitor/n2635_s14/CIN |
| 7.366 | 0.040 | tINS | RR | 1 | u_user_stream_if_monitor/n2635_s14/COUT |
| 7.366 | 0.000 | tNET | RR | 2 | u_user_stream_if_monitor/n2634_s14/CIN |
| 7.406 | 0.040 | tINS | RR | 1 | u_user_stream_if_monitor/n2634_s14/COUT |
| 7.406 | 0.000 | tNET | RR | 2 | u_user_stream_if_monitor/n2633_s14/CIN |
| 7.446 | 0.040 | tINS | RR | 1 | u_user_stream_if_monitor/n2633_s14/COUT |
| 7.446 | 0.000 | tNET | RR | 2 | u_user_stream_if_monitor/n2632_s14/CIN |
| 7.486 | 0.040 | tINS | RR | 1 | u_user_stream_if_monitor/n2632_s14/COUT |
| 7.486 | 0.000 | tNET | RR | 2 | u_user_stream_if_monitor/n2631_s14/CIN |
| 7.526 | 0.040 | tINS | RR | 1 | u_user_stream_if_monitor/n2631_s14/COUT |
| 7.526 | 0.000 | tNET | RR | 2 | u_user_stream_if_monitor/n2630_s14/CIN |
| 7.566 | 0.040 | tINS | RR | 1 | u_user_stream_if_monitor/n2630_s14/COUT |
| 7.566 | 0.000 | tNET | RR | 2 | u_user_stream_if_monitor/n2629_s14/CIN |
| 7.606 | 0.040 | tINS | RR | 1 | u_user_stream_if_monitor/n2629_s14/COUT |
| 7.606 | 0.000 | tNET | RR | 2 | u_user_stream_if_monitor/n2628_s14/CIN |
| 7.646 | 0.040 | tINS | RR | 1 | u_user_stream_if_monitor/n2628_s14/COUT |
| 7.646 | 0.000 | tNET | RR | 2 | u_user_stream_if_monitor/n2627_s14/CIN |
| 7.686 | 0.040 | tINS | RR | 1 | u_user_stream_if_monitor/n2627_s14/COUT |
| 7.686 | 0.000 | tNET | RR | 2 | u_user_stream_if_monitor/n2626_s14/CIN |
| 7.726 | 0.040 | tINS | RR | 1 | u_user_stream_if_monitor/n2626_s14/COUT |
| 7.726 | 0.000 | tNET | RR | 2 | u_user_stream_if_monitor/n2625_s14/CIN |
| 7.766 | 0.040 | tINS | RR | 1 | u_user_stream_if_monitor/n2625_s14/COUT |
| 7.766 | 0.000 | tNET | RR | 2 | u_user_stream_if_monitor/n2624_s14/CIN |
| 7.961 | 0.195 | tINS | RR | 1 | u_user_stream_if_monitor/n2624_s14/SUM |
| 8.261 | 0.300 | tNET | RR | 1 | u_user_stream_if_monitor/n2688_s3/I0 |
| 8.682 | 0.421 | tINS | RR | 1 | u_user_stream_if_monitor/n2688_s3/F |
| 8.982 | 0.300 | tNET | RR | 1 | u_user_stream_if_monitor/n2688_s7/I0 |
| 9.403 | 0.421 | tINS | RR | 1 | u_user_stream_if_monitor/n2688_s7/F |
| 9.703 | 0.300 | tNET | RR | 1 | u_user_stream_if_monitor/h2c_one_packet_byte_cnt_29_s1/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0.default_gen_clk | |||
| 10.244 | 0.244 | tCL | RR | 13001 | u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0 |
| 10.544 | 0.300 | tNET | RR | 1 | u_user_stream_if_monitor/h2c_one_packet_byte_cnt_29_s1/CLK |
| 10.493 | -0.051 | tSu | 1 | u_user_stream_if_monitor/h2c_one_packet_byte_cnt_29_s1 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 16 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.300, 100.000% |
| Arrival Data Path Delay: | cell: 5.553, 60.629%; route: 3.300, 36.030%; tC2Q: 0.306, 3.341% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.300, 100.000% |
Path 2
Path Summary:| Slack | 0.870 |
| Data Arrival Time | 9.623 |
| Data Required Time | 10.493 |
| From | u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_h2c_engine/u_h2c_stream_if/m_axis_h2c_tkeep_tmp_23_s1 |
| To | u_user_stream_if_monitor/h2c_one_packet_byte_cnt_27_s1 |
| Launch Clk | u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0.default_gen_clk[R] |
| Latch Clk | u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0.default_gen_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0.default_gen_clk | |||
| 0.244 | 0.244 | tCL | RR | 13001 | u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0 |
| 0.544 | 0.300 | tNET | RR | 1 | u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_h2c_engine/u_h2c_stream_if/m_axis_h2c_tkeep_tmp_23_s1/CLK |
| 0.850 | 0.306 | tC2Q | RR | 5 | u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_h2c_engine/u_h2c_stream_if/m_axis_h2c_tkeep_tmp_23_s1/Q |
| 1.150 | 0.300 | tNET | RR | 1 | u_user_stream_if_monitor/n2653_s59/I0 |
| 1.571 | 0.421 | tINS | RR | 3 | u_user_stream_if_monitor/n2653_s59/F |
| 1.871 | 0.300 | tNET | RR | 1 | u_user_stream_if_monitor/n2652_s34/I1 |
| 2.284 | 0.413 | tINS | RR | 1 | u_user_stream_if_monitor/n2652_s34/F |
| 2.584 | 0.300 | tNET | RR | 1 | u_user_stream_if_monitor/n2652_s31/I2 |
| 2.953 | 0.369 | tINS | RR | 1 | u_user_stream_if_monitor/n2652_s31/F |
| 3.253 | 0.300 | tNET | RR | 1 | u_user_stream_if_monitor/n2652_s38/I3 |
| 3.463 | 0.210 | tINS | RR | 2 | u_user_stream_if_monitor/n2652_s38/F |
| 3.763 | 0.300 | tNET | RR | 1 | u_user_stream_if_monitor/n2651_s15/I1 |
| 4.176 | 0.413 | tINS | RR | 1 | u_user_stream_if_monitor/n2651_s15/F |
| 4.476 | 0.300 | tNET | RR | 2 | u_user_stream_if_monitor/n2651_s10/I1 |
| 4.926 | 0.450 | tINS | RF | 1 | u_user_stream_if_monitor/n2651_s10/COUT |
| 4.926 | 0.000 | tNET | FF | 2 | u_user_stream_if_monitor/n2650_s10/CIN |
| 5.121 | 0.195 | tINS | FR | 1 | u_user_stream_if_monitor/n2650_s10/SUM |
| 5.421 | 0.300 | tNET | RR | 2 | u_user_stream_if_monitor/n2650_s12/I0 |
| 5.866 | 0.445 | tINS | RF | 1 | u_user_stream_if_monitor/n2650_s12/COUT |
| 5.866 | 0.000 | tNET | FF | 2 | u_user_stream_if_monitor/n2649_s12/CIN |
| 6.061 | 0.195 | tINS | FR | 1 | u_user_stream_if_monitor/n2649_s12/SUM |
| 6.361 | 0.300 | tNET | RR | 2 | u_user_stream_if_monitor/n2649_s14/I0 |
| 6.806 | 0.445 | tINS | RF | 1 | u_user_stream_if_monitor/n2649_s14/COUT |
| 6.806 | 0.000 | tNET | FF | 2 | u_user_stream_if_monitor/n2648_s14/CIN |
| 6.846 | 0.040 | tINS | FR | 1 | u_user_stream_if_monitor/n2648_s14/COUT |
| 6.846 | 0.000 | tNET | RR | 2 | u_user_stream_if_monitor/n2647_s14/CIN |
| 6.886 | 0.040 | tINS | RR | 1 | u_user_stream_if_monitor/n2647_s14/COUT |
| 6.886 | 0.000 | tNET | RR | 2 | u_user_stream_if_monitor/n2646_s14/CIN |
| 6.926 | 0.040 | tINS | RR | 1 | u_user_stream_if_monitor/n2646_s14/COUT |
| 6.926 | 0.000 | tNET | RR | 2 | u_user_stream_if_monitor/n2645_s14/CIN |
| 6.966 | 0.040 | tINS | RR | 1 | u_user_stream_if_monitor/n2645_s14/COUT |
| 6.966 | 0.000 | tNET | RR | 2 | u_user_stream_if_monitor/n2644_s14/CIN |
| 7.006 | 0.040 | tINS | RR | 1 | u_user_stream_if_monitor/n2644_s14/COUT |
| 7.006 | 0.000 | tNET | RR | 2 | u_user_stream_if_monitor/n2643_s14/CIN |
| 7.046 | 0.040 | tINS | RR | 1 | u_user_stream_if_monitor/n2643_s14/COUT |
| 7.046 | 0.000 | tNET | RR | 2 | u_user_stream_if_monitor/n2642_s14/CIN |
| 7.086 | 0.040 | tINS | RR | 1 | u_user_stream_if_monitor/n2642_s14/COUT |
| 7.086 | 0.000 | tNET | RR | 2 | u_user_stream_if_monitor/n2641_s14/CIN |
| 7.126 | 0.040 | tINS | RR | 1 | u_user_stream_if_monitor/n2641_s14/COUT |
| 7.126 | 0.000 | tNET | RR | 2 | u_user_stream_if_monitor/n2640_s14/CIN |
| 7.166 | 0.040 | tINS | RR | 1 | u_user_stream_if_monitor/n2640_s14/COUT |
| 7.166 | 0.000 | tNET | RR | 2 | u_user_stream_if_monitor/n2639_s14/CIN |
| 7.206 | 0.040 | tINS | RR | 1 | u_user_stream_if_monitor/n2639_s14/COUT |
| 7.206 | 0.000 | tNET | RR | 2 | u_user_stream_if_monitor/n2638_s14/CIN |
| 7.246 | 0.040 | tINS | RR | 1 | u_user_stream_if_monitor/n2638_s14/COUT |
| 7.246 | 0.000 | tNET | RR | 2 | u_user_stream_if_monitor/n2637_s14/CIN |
| 7.286 | 0.040 | tINS | RR | 1 | u_user_stream_if_monitor/n2637_s14/COUT |
| 7.286 | 0.000 | tNET | RR | 2 | u_user_stream_if_monitor/n2636_s14/CIN |
| 7.326 | 0.040 | tINS | RR | 1 | u_user_stream_if_monitor/n2636_s14/COUT |
| 7.326 | 0.000 | tNET | RR | 2 | u_user_stream_if_monitor/n2635_s14/CIN |
| 7.366 | 0.040 | tINS | RR | 1 | u_user_stream_if_monitor/n2635_s14/COUT |
| 7.366 | 0.000 | tNET | RR | 2 | u_user_stream_if_monitor/n2634_s14/CIN |
| 7.406 | 0.040 | tINS | RR | 1 | u_user_stream_if_monitor/n2634_s14/COUT |
| 7.406 | 0.000 | tNET | RR | 2 | u_user_stream_if_monitor/n2633_s14/CIN |
| 7.446 | 0.040 | tINS | RR | 1 | u_user_stream_if_monitor/n2633_s14/COUT |
| 7.446 | 0.000 | tNET | RR | 2 | u_user_stream_if_monitor/n2632_s14/CIN |
| 7.486 | 0.040 | tINS | RR | 1 | u_user_stream_if_monitor/n2632_s14/COUT |
| 7.486 | 0.000 | tNET | RR | 2 | u_user_stream_if_monitor/n2631_s14/CIN |
| 7.526 | 0.040 | tINS | RR | 1 | u_user_stream_if_monitor/n2631_s14/COUT |
| 7.526 | 0.000 | tNET | RR | 2 | u_user_stream_if_monitor/n2630_s14/CIN |
| 7.566 | 0.040 | tINS | RR | 1 | u_user_stream_if_monitor/n2630_s14/COUT |
| 7.566 | 0.000 | tNET | RR | 2 | u_user_stream_if_monitor/n2629_s14/CIN |
| 7.606 | 0.040 | tINS | RR | 1 | u_user_stream_if_monitor/n2629_s14/COUT |
| 7.606 | 0.000 | tNET | RR | 2 | u_user_stream_if_monitor/n2628_s14/CIN |
| 7.646 | 0.040 | tINS | RR | 1 | u_user_stream_if_monitor/n2628_s14/COUT |
| 7.646 | 0.000 | tNET | RR | 2 | u_user_stream_if_monitor/n2627_s14/CIN |
| 7.686 | 0.040 | tINS | RR | 1 | u_user_stream_if_monitor/n2627_s14/COUT |
| 7.686 | 0.000 | tNET | RR | 2 | u_user_stream_if_monitor/n2626_s14/CIN |
| 7.881 | 0.195 | tINS | RR | 1 | u_user_stream_if_monitor/n2626_s14/SUM |
| 8.181 | 0.300 | tNET | RR | 1 | u_user_stream_if_monitor/n2690_s3/I0 |
| 8.602 | 0.421 | tINS | RR | 1 | u_user_stream_if_monitor/n2690_s3/F |
| 8.902 | 0.300 | tNET | RR | 1 | u_user_stream_if_monitor/n2690_s6/I0 |
| 9.323 | 0.421 | tINS | RR | 1 | u_user_stream_if_monitor/n2690_s6/F |
| 9.623 | 0.300 | tNET | RR | 1 | u_user_stream_if_monitor/h2c_one_packet_byte_cnt_27_s1/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0.default_gen_clk | |||
| 10.244 | 0.244 | tCL | RR | 13001 | u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0 |
| 10.544 | 0.300 | tNET | RR | 1 | u_user_stream_if_monitor/h2c_one_packet_byte_cnt_27_s1/CLK |
| 10.493 | -0.051 | tSu | 1 | u_user_stream_if_monitor/h2c_one_packet_byte_cnt_27_s1 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 16 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.300, 100.000% |
| Arrival Data Path Delay: | cell: 5.473, 60.282%; route: 3.300, 36.348%; tC2Q: 0.306, 3.370% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.300, 100.000% |
Path 3
Path Summary:| Slack | 1.230 |
| Data Arrival Time | 9.263 |
| Data Required Time | 10.493 |
| From | u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_h2c_engine/u_h2c_stream_if/m_axis_h2c_tkeep_tmp_23_s1 |
| To | u_user_stream_if_monitor/h2c_one_packet_byte_cnt_18_s1 |
| Launch Clk | u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0.default_gen_clk[R] |
| Latch Clk | u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0.default_gen_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0.default_gen_clk | |||
| 0.244 | 0.244 | tCL | RR | 13001 | u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0 |
| 0.544 | 0.300 | tNET | RR | 1 | u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_h2c_engine/u_h2c_stream_if/m_axis_h2c_tkeep_tmp_23_s1/CLK |
| 0.850 | 0.306 | tC2Q | RR | 5 | u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_h2c_engine/u_h2c_stream_if/m_axis_h2c_tkeep_tmp_23_s1/Q |
| 1.150 | 0.300 | tNET | RR | 1 | u_user_stream_if_monitor/n2653_s59/I0 |
| 1.571 | 0.421 | tINS | RR | 3 | u_user_stream_if_monitor/n2653_s59/F |
| 1.871 | 0.300 | tNET | RR | 1 | u_user_stream_if_monitor/n2652_s34/I1 |
| 2.284 | 0.413 | tINS | RR | 1 | u_user_stream_if_monitor/n2652_s34/F |
| 2.584 | 0.300 | tNET | RR | 1 | u_user_stream_if_monitor/n2652_s31/I2 |
| 2.953 | 0.369 | tINS | RR | 1 | u_user_stream_if_monitor/n2652_s31/F |
| 3.253 | 0.300 | tNET | RR | 1 | u_user_stream_if_monitor/n2652_s38/I3 |
| 3.463 | 0.210 | tINS | RR | 2 | u_user_stream_if_monitor/n2652_s38/F |
| 3.763 | 0.300 | tNET | RR | 1 | u_user_stream_if_monitor/n2651_s15/I1 |
| 4.176 | 0.413 | tINS | RR | 1 | u_user_stream_if_monitor/n2651_s15/F |
| 4.476 | 0.300 | tNET | RR | 2 | u_user_stream_if_monitor/n2651_s10/I1 |
| 4.926 | 0.450 | tINS | RF | 1 | u_user_stream_if_monitor/n2651_s10/COUT |
| 4.926 | 0.000 | tNET | FF | 2 | u_user_stream_if_monitor/n2650_s10/CIN |
| 5.121 | 0.195 | tINS | FR | 1 | u_user_stream_if_monitor/n2650_s10/SUM |
| 5.421 | 0.300 | tNET | RR | 2 | u_user_stream_if_monitor/n2650_s12/I0 |
| 5.866 | 0.445 | tINS | RF | 1 | u_user_stream_if_monitor/n2650_s12/COUT |
| 5.866 | 0.000 | tNET | FF | 2 | u_user_stream_if_monitor/n2649_s12/CIN |
| 6.061 | 0.195 | tINS | FR | 1 | u_user_stream_if_monitor/n2649_s12/SUM |
| 6.361 | 0.300 | tNET | RR | 2 | u_user_stream_if_monitor/n2649_s14/I0 |
| 6.806 | 0.445 | tINS | RF | 1 | u_user_stream_if_monitor/n2649_s14/COUT |
| 6.806 | 0.000 | tNET | FF | 2 | u_user_stream_if_monitor/n2648_s14/CIN |
| 6.846 | 0.040 | tINS | FR | 1 | u_user_stream_if_monitor/n2648_s14/COUT |
| 6.846 | 0.000 | tNET | RR | 2 | u_user_stream_if_monitor/n2647_s14/CIN |
| 6.886 | 0.040 | tINS | RR | 1 | u_user_stream_if_monitor/n2647_s14/COUT |
| 6.886 | 0.000 | tNET | RR | 2 | u_user_stream_if_monitor/n2646_s14/CIN |
| 6.926 | 0.040 | tINS | RR | 1 | u_user_stream_if_monitor/n2646_s14/COUT |
| 6.926 | 0.000 | tNET | RR | 2 | u_user_stream_if_monitor/n2645_s14/CIN |
| 6.966 | 0.040 | tINS | RR | 1 | u_user_stream_if_monitor/n2645_s14/COUT |
| 6.966 | 0.000 | tNET | RR | 2 | u_user_stream_if_monitor/n2644_s14/CIN |
| 7.006 | 0.040 | tINS | RR | 1 | u_user_stream_if_monitor/n2644_s14/COUT |
| 7.006 | 0.000 | tNET | RR | 2 | u_user_stream_if_monitor/n2643_s14/CIN |
| 7.046 | 0.040 | tINS | RR | 1 | u_user_stream_if_monitor/n2643_s14/COUT |
| 7.046 | 0.000 | tNET | RR | 2 | u_user_stream_if_monitor/n2642_s14/CIN |
| 7.086 | 0.040 | tINS | RR | 1 | u_user_stream_if_monitor/n2642_s14/COUT |
| 7.086 | 0.000 | tNET | RR | 2 | u_user_stream_if_monitor/n2641_s14/CIN |
| 7.126 | 0.040 | tINS | RR | 1 | u_user_stream_if_monitor/n2641_s14/COUT |
| 7.126 | 0.000 | tNET | RR | 2 | u_user_stream_if_monitor/n2640_s14/CIN |
| 7.166 | 0.040 | tINS | RR | 1 | u_user_stream_if_monitor/n2640_s14/COUT |
| 7.166 | 0.000 | tNET | RR | 2 | u_user_stream_if_monitor/n2639_s14/CIN |
| 7.206 | 0.040 | tINS | RR | 1 | u_user_stream_if_monitor/n2639_s14/COUT |
| 7.206 | 0.000 | tNET | RR | 2 | u_user_stream_if_monitor/n2638_s14/CIN |
| 7.246 | 0.040 | tINS | RR | 1 | u_user_stream_if_monitor/n2638_s14/COUT |
| 7.246 | 0.000 | tNET | RR | 2 | u_user_stream_if_monitor/n2637_s14/CIN |
| 7.286 | 0.040 | tINS | RR | 1 | u_user_stream_if_monitor/n2637_s14/COUT |
| 7.286 | 0.000 | tNET | RR | 2 | u_user_stream_if_monitor/n2636_s14/CIN |
| 7.326 | 0.040 | tINS | RR | 1 | u_user_stream_if_monitor/n2636_s14/COUT |
| 7.326 | 0.000 | tNET | RR | 2 | u_user_stream_if_monitor/n2635_s14/CIN |
| 7.521 | 0.195 | tINS | RR | 1 | u_user_stream_if_monitor/n2635_s14/SUM |
| 7.821 | 0.300 | tNET | RR | 1 | u_user_stream_if_monitor/n2699_s3/I0 |
| 8.242 | 0.421 | tINS | RR | 1 | u_user_stream_if_monitor/n2699_s3/F |
| 8.542 | 0.300 | tNET | RR | 1 | u_user_stream_if_monitor/n2699_s7/I0 |
| 8.963 | 0.421 | tINS | RR | 1 | u_user_stream_if_monitor/n2699_s7/F |
| 9.263 | 0.300 | tNET | RR | 1 | u_user_stream_if_monitor/h2c_one_packet_byte_cnt_18_s1/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0.default_gen_clk | |||
| 10.244 | 0.244 | tCL | RR | 13001 | u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0 |
| 10.544 | 0.300 | tNET | RR | 1 | u_user_stream_if_monitor/h2c_one_packet_byte_cnt_18_s1/CLK |
| 10.493 | -0.051 | tSu | 1 | u_user_stream_if_monitor/h2c_one_packet_byte_cnt_18_s1 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 15 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.300, 100.000% |
| Arrival Data Path Delay: | cell: 5.113, 58.642%; route: 3.300, 37.848%; tC2Q: 0.306, 3.510% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.300, 100.000% |
Path 4
Path Summary:| Slack | 1.310 |
| Data Arrival Time | 9.183 |
| Data Required Time | 10.493 |
| From | u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_h2c_engine/u_h2c_stream_if/m_axis_h2c_tkeep_tmp_23_s1 |
| To | u_user_stream_if_monitor/h2c_one_packet_byte_cnt_16_s1 |
| Launch Clk | u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0.default_gen_clk[R] |
| Latch Clk | u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0.default_gen_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0.default_gen_clk | |||
| 0.244 | 0.244 | tCL | RR | 13001 | u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0 |
| 0.544 | 0.300 | tNET | RR | 1 | u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_h2c_engine/u_h2c_stream_if/m_axis_h2c_tkeep_tmp_23_s1/CLK |
| 0.850 | 0.306 | tC2Q | RR | 5 | u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_h2c_engine/u_h2c_stream_if/m_axis_h2c_tkeep_tmp_23_s1/Q |
| 1.150 | 0.300 | tNET | RR | 1 | u_user_stream_if_monitor/n2653_s59/I0 |
| 1.571 | 0.421 | tINS | RR | 3 | u_user_stream_if_monitor/n2653_s59/F |
| 1.871 | 0.300 | tNET | RR | 1 | u_user_stream_if_monitor/n2652_s34/I1 |
| 2.284 | 0.413 | tINS | RR | 1 | u_user_stream_if_monitor/n2652_s34/F |
| 2.584 | 0.300 | tNET | RR | 1 | u_user_stream_if_monitor/n2652_s31/I2 |
| 2.953 | 0.369 | tINS | RR | 1 | u_user_stream_if_monitor/n2652_s31/F |
| 3.253 | 0.300 | tNET | RR | 1 | u_user_stream_if_monitor/n2652_s38/I3 |
| 3.463 | 0.210 | tINS | RR | 2 | u_user_stream_if_monitor/n2652_s38/F |
| 3.763 | 0.300 | tNET | RR | 1 | u_user_stream_if_monitor/n2651_s15/I1 |
| 4.176 | 0.413 | tINS | RR | 1 | u_user_stream_if_monitor/n2651_s15/F |
| 4.476 | 0.300 | tNET | RR | 2 | u_user_stream_if_monitor/n2651_s10/I1 |
| 4.926 | 0.450 | tINS | RF | 1 | u_user_stream_if_monitor/n2651_s10/COUT |
| 4.926 | 0.000 | tNET | FF | 2 | u_user_stream_if_monitor/n2650_s10/CIN |
| 5.121 | 0.195 | tINS | FR | 1 | u_user_stream_if_monitor/n2650_s10/SUM |
| 5.421 | 0.300 | tNET | RR | 2 | u_user_stream_if_monitor/n2650_s12/I0 |
| 5.866 | 0.445 | tINS | RF | 1 | u_user_stream_if_monitor/n2650_s12/COUT |
| 5.866 | 0.000 | tNET | FF | 2 | u_user_stream_if_monitor/n2649_s12/CIN |
| 6.061 | 0.195 | tINS | FR | 1 | u_user_stream_if_monitor/n2649_s12/SUM |
| 6.361 | 0.300 | tNET | RR | 2 | u_user_stream_if_monitor/n2649_s14/I0 |
| 6.806 | 0.445 | tINS | RF | 1 | u_user_stream_if_monitor/n2649_s14/COUT |
| 6.806 | 0.000 | tNET | FF | 2 | u_user_stream_if_monitor/n2648_s14/CIN |
| 6.846 | 0.040 | tINS | FR | 1 | u_user_stream_if_monitor/n2648_s14/COUT |
| 6.846 | 0.000 | tNET | RR | 2 | u_user_stream_if_monitor/n2647_s14/CIN |
| 6.886 | 0.040 | tINS | RR | 1 | u_user_stream_if_monitor/n2647_s14/COUT |
| 6.886 | 0.000 | tNET | RR | 2 | u_user_stream_if_monitor/n2646_s14/CIN |
| 6.926 | 0.040 | tINS | RR | 1 | u_user_stream_if_monitor/n2646_s14/COUT |
| 6.926 | 0.000 | tNET | RR | 2 | u_user_stream_if_monitor/n2645_s14/CIN |
| 6.966 | 0.040 | tINS | RR | 1 | u_user_stream_if_monitor/n2645_s14/COUT |
| 6.966 | 0.000 | tNET | RR | 2 | u_user_stream_if_monitor/n2644_s14/CIN |
| 7.006 | 0.040 | tINS | RR | 1 | u_user_stream_if_monitor/n2644_s14/COUT |
| 7.006 | 0.000 | tNET | RR | 2 | u_user_stream_if_monitor/n2643_s14/CIN |
| 7.046 | 0.040 | tINS | RR | 1 | u_user_stream_if_monitor/n2643_s14/COUT |
| 7.046 | 0.000 | tNET | RR | 2 | u_user_stream_if_monitor/n2642_s14/CIN |
| 7.086 | 0.040 | tINS | RR | 1 | u_user_stream_if_monitor/n2642_s14/COUT |
| 7.086 | 0.000 | tNET | RR | 2 | u_user_stream_if_monitor/n2641_s14/CIN |
| 7.126 | 0.040 | tINS | RR | 1 | u_user_stream_if_monitor/n2641_s14/COUT |
| 7.126 | 0.000 | tNET | RR | 2 | u_user_stream_if_monitor/n2640_s14/CIN |
| 7.166 | 0.040 | tINS | RR | 1 | u_user_stream_if_monitor/n2640_s14/COUT |
| 7.166 | 0.000 | tNET | RR | 2 | u_user_stream_if_monitor/n2639_s14/CIN |
| 7.206 | 0.040 | tINS | RR | 1 | u_user_stream_if_monitor/n2639_s14/COUT |
| 7.206 | 0.000 | tNET | RR | 2 | u_user_stream_if_monitor/n2638_s14/CIN |
| 7.246 | 0.040 | tINS | RR | 1 | u_user_stream_if_monitor/n2638_s14/COUT |
| 7.246 | 0.000 | tNET | RR | 2 | u_user_stream_if_monitor/n2637_s14/CIN |
| 7.441 | 0.195 | tINS | RR | 1 | u_user_stream_if_monitor/n2637_s14/SUM |
| 7.741 | 0.300 | tNET | RR | 1 | u_user_stream_if_monitor/n2701_s3/I0 |
| 8.162 | 0.421 | tINS | RR | 1 | u_user_stream_if_monitor/n2701_s3/F |
| 8.462 | 0.300 | tNET | RR | 1 | u_user_stream_if_monitor/n2701_s5/I0 |
| 8.883 | 0.421 | tINS | RR | 1 | u_user_stream_if_monitor/n2701_s5/F |
| 9.183 | 0.300 | tNET | RR | 1 | u_user_stream_if_monitor/h2c_one_packet_byte_cnt_16_s1/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0.default_gen_clk | |||
| 10.244 | 0.244 | tCL | RR | 13001 | u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0 |
| 10.544 | 0.300 | tNET | RR | 1 | u_user_stream_if_monitor/h2c_one_packet_byte_cnt_16_s1/CLK |
| 10.493 | -0.051 | tSu | 1 | u_user_stream_if_monitor/h2c_one_packet_byte_cnt_16_s1 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 15 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.300, 100.000% |
| Arrival Data Path Delay: | cell: 5.033, 58.259%; route: 3.300, 38.199%; tC2Q: 0.306, 3.542% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.300, 100.000% |
Path 5
Path Summary:| Slack | 1.430 |
| Data Arrival Time | 9.063 |
| Data Required Time | 10.493 |
| From | u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_h2c_engine/u_h2c_stream_if/m_axis_h2c_tkeep_tmp_23_s1 |
| To | u_user_stream_if_monitor/h2c_one_packet_byte_cnt_13_s1 |
| Launch Clk | u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0.default_gen_clk[R] |
| Latch Clk | u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0.default_gen_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0.default_gen_clk | |||
| 0.244 | 0.244 | tCL | RR | 13001 | u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0 |
| 0.544 | 0.300 | tNET | RR | 1 | u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_h2c_engine/u_h2c_stream_if/m_axis_h2c_tkeep_tmp_23_s1/CLK |
| 0.850 | 0.306 | tC2Q | RR | 5 | u_dut/top/u_dma/u_h2c_all_engines/multi_engines_gen[0].u_h2c_engine/u_h2c_stream_if/m_axis_h2c_tkeep_tmp_23_s1/Q |
| 1.150 | 0.300 | tNET | RR | 1 | u_user_stream_if_monitor/n2653_s59/I0 |
| 1.571 | 0.421 | tINS | RR | 3 | u_user_stream_if_monitor/n2653_s59/F |
| 1.871 | 0.300 | tNET | RR | 1 | u_user_stream_if_monitor/n2652_s34/I1 |
| 2.284 | 0.413 | tINS | RR | 1 | u_user_stream_if_monitor/n2652_s34/F |
| 2.584 | 0.300 | tNET | RR | 1 | u_user_stream_if_monitor/n2652_s31/I2 |
| 2.953 | 0.369 | tINS | RR | 1 | u_user_stream_if_monitor/n2652_s31/F |
| 3.253 | 0.300 | tNET | RR | 1 | u_user_stream_if_monitor/n2652_s38/I3 |
| 3.463 | 0.210 | tINS | RR | 2 | u_user_stream_if_monitor/n2652_s38/F |
| 3.763 | 0.300 | tNET | RR | 1 | u_user_stream_if_monitor/n2651_s15/I1 |
| 4.176 | 0.413 | tINS | RR | 1 | u_user_stream_if_monitor/n2651_s15/F |
| 4.476 | 0.300 | tNET | RR | 2 | u_user_stream_if_monitor/n2651_s10/I1 |
| 4.926 | 0.450 | tINS | RF | 1 | u_user_stream_if_monitor/n2651_s10/COUT |
| 4.926 | 0.000 | tNET | FF | 2 | u_user_stream_if_monitor/n2650_s10/CIN |
| 5.121 | 0.195 | tINS | FR | 1 | u_user_stream_if_monitor/n2650_s10/SUM |
| 5.421 | 0.300 | tNET | RR | 2 | u_user_stream_if_monitor/n2650_s12/I0 |
| 5.866 | 0.445 | tINS | RF | 1 | u_user_stream_if_monitor/n2650_s12/COUT |
| 5.866 | 0.000 | tNET | FF | 2 | u_user_stream_if_monitor/n2649_s12/CIN |
| 6.061 | 0.195 | tINS | FR | 1 | u_user_stream_if_monitor/n2649_s12/SUM |
| 6.361 | 0.300 | tNET | RR | 2 | u_user_stream_if_monitor/n2649_s14/I0 |
| 6.806 | 0.445 | tINS | RF | 1 | u_user_stream_if_monitor/n2649_s14/COUT |
| 6.806 | 0.000 | tNET | FF | 2 | u_user_stream_if_monitor/n2648_s14/CIN |
| 6.846 | 0.040 | tINS | FR | 1 | u_user_stream_if_monitor/n2648_s14/COUT |
| 6.846 | 0.000 | tNET | RR | 2 | u_user_stream_if_monitor/n2647_s14/CIN |
| 6.886 | 0.040 | tINS | RR | 1 | u_user_stream_if_monitor/n2647_s14/COUT |
| 6.886 | 0.000 | tNET | RR | 2 | u_user_stream_if_monitor/n2646_s14/CIN |
| 6.926 | 0.040 | tINS | RR | 1 | u_user_stream_if_monitor/n2646_s14/COUT |
| 6.926 | 0.000 | tNET | RR | 2 | u_user_stream_if_monitor/n2645_s14/CIN |
| 6.966 | 0.040 | tINS | RR | 1 | u_user_stream_if_monitor/n2645_s14/COUT |
| 6.966 | 0.000 | tNET | RR | 2 | u_user_stream_if_monitor/n2644_s14/CIN |
| 7.006 | 0.040 | tINS | RR | 1 | u_user_stream_if_monitor/n2644_s14/COUT |
| 7.006 | 0.000 | tNET | RR | 2 | u_user_stream_if_monitor/n2643_s14/CIN |
| 7.046 | 0.040 | tINS | RR | 1 | u_user_stream_if_monitor/n2643_s14/COUT |
| 7.046 | 0.000 | tNET | RR | 2 | u_user_stream_if_monitor/n2642_s14/CIN |
| 7.086 | 0.040 | tINS | RR | 1 | u_user_stream_if_monitor/n2642_s14/COUT |
| 7.086 | 0.000 | tNET | RR | 2 | u_user_stream_if_monitor/n2641_s14/CIN |
| 7.126 | 0.040 | tINS | RR | 1 | u_user_stream_if_monitor/n2641_s14/COUT |
| 7.126 | 0.000 | tNET | RR | 2 | u_user_stream_if_monitor/n2640_s14/CIN |
| 7.321 | 0.195 | tINS | RR | 1 | u_user_stream_if_monitor/n2640_s14/SUM |
| 7.621 | 0.300 | tNET | RR | 1 | u_user_stream_if_monitor/n2704_s3/I0 |
| 8.042 | 0.421 | tINS | RR | 1 | u_user_stream_if_monitor/n2704_s3/F |
| 8.342 | 0.300 | tNET | RR | 1 | u_user_stream_if_monitor/n2704_s5/I0 |
| 8.763 | 0.421 | tINS | RR | 1 | u_user_stream_if_monitor/n2704_s5/F |
| 9.063 | 0.300 | tNET | RR | 1 | u_user_stream_if_monitor/h2c_one_packet_byte_cnt_13_s1/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0.default_gen_clk | |||
| 10.244 | 0.244 | tCL | RR | 13001 | u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0 |
| 10.544 | 0.300 | tNET | RR | 1 | u_user_stream_if_monitor/h2c_one_packet_byte_cnt_13_s1/CLK |
| 10.493 | -0.051 | tSu | 1 | u_user_stream_if_monitor/h2c_one_packet_byte_cnt_13_s1 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 15 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.300, 100.000% |
| Arrival Data Path Delay: | cell: 4.913, 57.671%; route: 3.300, 38.737%; tC2Q: 0.306, 3.592% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.300, 100.000% |