____________________________________________________________________________________________________________________________
                                     ISP Design Read Me
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Object device:
GW2A-LV55PG484C8/I7
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File List:
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.
|-- ISP_Demo
|   `-- ReadMe.txt                          -->  Read me file (this file)
| 	|-- FPGA_Design                         -->  Gowin Project for Example Design
|       `-- isp_proj.gprj                   -->  Gowin Project for Example Design
|       |-- bootload                        -->  Boot load file for Gowin_EMPU_M1 configuration
|       |-- src
|           |-- bayer_to_rgb				--> Beyer image to RGB image module (optional)
|	        |-- ddr3_memory_interface		--> Ddr3_memory_interface
|			|-- ddr3_rpll					--> PLL for ddr3
|			|-- frame_buffer				--> Frame buffer
|           |-- gowin_empu_m1				--> Cortext M1 
|           |-- ILM_ISP_M1  				--> Cortext M1 ILM file ILM_ISP_M1
|           |-- gowin_rpll					--> PLL for LCD display
|           |-- mipi_csi					--> MIPI CSI module
|           |-- ov5647_init					--> ov5647 initial & driver 
|           |-- pll_8bit_2lane				--> PLL for CSI module
|           |-- scaler						--> Sclaer Module
|           |-- syn_code					--> Display timming signal
|           |-- ISP
|            	|-- AEAWB					--> ISP's AEAWB module
|				|-- CCM						--> ISP's CCM module
|				|-- CFA						--> ISP's CFA module
|				|-- GAMMA					--> ISP's GAMMA module
|				`-- isp_top.v 				--> ISP top module	
|           `-- video_top.v					--> Top module
|           `-- ahb_isp.v					--> Ahb decoder module
|           `-- video_clip_sl.v				--> Video clip module
|           `-- testpattern.v				--> Testpattern module
|           `-- isp_proj.cst      			--> Constraint file for Gowin Project
|           `-- isp_proj.sdc      	 		--> SDC file for Gowin Project
|   |-- MCU_Design                          --> Keil Project for Example Design
|       |-- CORE                        		
|       |-- PERIPHERAL                        	
|       |-- PROJECT                        		
|       |-- SCT                        			
|       |-- STARTUP                        		
|       |-- SYSTEM                        		
|		|-- USER							--> MCU user C code design file
|			`-- main.c						-->	Main function file
|			`-- main.h						-->	Main header file
|			`-- gw_ahb.c					-->	AHB function file
|			`-- gw_ahb.h					-->	AHB function header file
|			`-- gw_isp.c					-->	ISP function file
|			`-- gw_isp.h					-->	ISP function header file
|			`-- gw_isp_param.h				-->	ISP parameters file
|			`-- retarget.c					-->	UART printf and scanf retarget function.
|			`-- GOWIN_M1_conf.h				-->	Library configuration file.
|			`-- GOWIN_M1_it.c				-->	Main Interrupt Service Routines.
|			`-- GOWIN_M1_it.h				-->	Interrupt handlers header file
|   |-- Download_file                       --> Download file
|	    `-- isp_proj.fs						--> FPGA fs file


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HOW TO OPEN A PROJECT IN Gowin:
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1. Unzip the respective design files.
2. Launch Gowin and select "File -> Open -> Project"
3. In the Open Project dialog, enter the Project location -- "FPGA_Design",select the project"isp_proj.gprj".
4. Click Finish. Now the project is successfully loaded.

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HOW TO OPEN A PROJECT IN ARM Keil MDK:
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1. Unzip the respective design files.
2. Launch ARM Keil MDK and select "Project -> Open Projects".
3. In the Open Project dialog, enter the Project location -- "PROJECT", select the project "isp_proj.uvprojx".
4. Click Open. Now the project is successfully loaded. 
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HOW TO CHANGE THE C BIN:
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1. Write C program and modify the starting address of IROM1 to 0.
2.Build the project.
3.Get the bin file and use makehex software to generate the ITCM initialization file.
4. Regenerate M1 IP core, select Internal Instruction Memory and add the file generated in the previous step to the initialization path.
5.Add new M1 core to project.
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HOW TO RUN SYNTHESIZE, PLACE AND ROUTE, IP CORE GENERATION, AND TIMING ANALYSIS IN Gowin:
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1. Click the Process tab in the process panel of the Gowin dashboard. 
   Double click on Synthsize(GowinSynthesis or Synplify Pro). This will bring the design through synthesis.
2. Click the Process tab in the process panel of the Gowin dashboard. 
   Double click on Place & Route. This will bring the design through mapping, place and route.
3. Once Place & Route is done, user can double click on Timing Analysis Report to get 
   the timing analysis result.

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HOW TO DOWNLOAD:
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1. Launch Programmer.
2. "SRAM Program" to download FPGA fs file.

