Synthesis Messages

Report Title GowinSynthesis Report
Design File D:\Gowin\Gowin_V1.9.7Beta\IDE\ipcore\MIPI_RX_Advance\data\DPHY_RX.v
D:\Gowin\Gowin_V1.9.7Beta\IDE\ipcore\MIPI_RX_Advance\data\DPHY_RX_TOP.v
GowinSynthesis Constraints File ---
GowinSynthesis Verision GowinSynthesis V1.9.7Beta
Created Time Fri Nov 06 16:41:09 2020
Legal Announcement Copyright (C)2014-2020 Gowin Semiconductor Corporation. ALL rights reserved.

Design Settings

Top Level Module: MIPI_RX_Advance_Top
Part Number: GW2A-LV55PG484C8/I7
Device: GW2A-55C

Resource

Resource Usage Summary

I/O Port 48
I/O Buf 45
    IBUF 12
    OBUF 24
    IOBUF 6
    TLVDS_IBUF 3
Register 259
    DFFE 16
    DFFPE 1
    DFFC 205
    DFFCE 37
LUT 195
    LUT2 34
    LUT3 78
    LUT4 83
ALU 20
    ALU 20
SSRAM 4
    RAM16SDP4 4
INV 3
    INV 3
IOLOGIC 4
    IDES8 2
    IODELAY 2
CLOCK 2
    CLKDIV 1
    DHCEN 1

Resource Utilization Summary

Logic 242(198 LUTs, 20 ALUs, 4 SSRAMs) / 54720 1%
Register 259 / 42000 1%
BSRAM 0 / 140 0%


Timing

Clock Summary:

Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
HS_CLK_P Base 10.000 100.0 0.000 5.000 DPHY_RX_INST/U0_IB/I
DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT.default_gen_clk Generated 40.000 25.0 0.000 20.000 DPHY_RX_INST/U0_IB/I HS_CLK_P DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT

Max Frequency Summary:

No. Clock Name Constraint Actual Fmax Logic Level Entity
1 HS_CLK_P 100.0 MHz 379.4 MHz 2 TOP
2 DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT.default_gen_clk 25.0 MHz 203.6 MHz 7 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack 4
Data Arrival Time 2
Data Required Time 6
From DPHY_RX_INST/u_idesx8/opensync_1_s0
To DPHY_RX_INST/u_idesx8/u_DHCEN
Launch Clk HS_CLK_P[F]
Latch Clk HS_CLK_P[R]

Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0 0 tCL RR 1 DPHY_RX_INST/U0_IB/I
0.682 0.682 tINS RR 5 DPHY_RX_INST/U0_IB/O
0.862 0.18 tNET RR 1 DPHY_RX_INST/u_idesx8/opensync_1_s0/CLK
1.094 0.232 tC2Q RF 2 DPHY_RX_INST/u_idesx8/opensync_1_s0/Q
1.331 0.237 tNET FF 1 DPHY_RX_INST/u_idesx8/LUT4_0/I2
1.784 0.453 tINS FF 1 DPHY_RX_INST/u_idesx8/LUT4_0/F
2.021 0.237 tNET FF 1 DPHY_RX_INST/u_idesx8/u_DHCEN/CE

Data Required Path:
AT DELAY TYPE RF FANOUT NODE
5 0 tCL FF 1 DPHY_RX_INST/U0_IB/I
5.687 0.687 tINS FF 5 DPHY_RX_INST/U0_IB/O
5.924 0.237 tNET FF 3 DPHY_RX_INST/u_idesx8/u_DHCEN/CLKIN

Path Statistic:
Clock Skew: 0
Hold Relationship: 5
Logic Level: 2
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 0.453, 39.085%; route: 0.474, 40.897%; tC2Q: 0.232, 20.017%
Required Clock Path Delay: cell: 0.688, 74.365%; route: 0.237, 25.635%

Path 2

Path Summary:
Slack 8.819
Data Arrival Time 1.974
Data Required Time 10.793
From DPHY_RX_INST/u_idesx8/opensync_3_s0
To DPHY_RX_INST/u_idesx8/opensync_0_s0
Launch Clk HS_CLK_P[R]
Latch Clk HS_CLK_P[R]

Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0 0 tCL RR 1 DPHY_RX_INST/U0_IB/I
0.682 0.682 tINS RR 5 DPHY_RX_INST/U0_IB/O
0.862 0.18 tNET RR 1 DPHY_RX_INST/u_idesx8/opensync_3_s0/CLK
1.094 0.232 tC2Q RF 2 DPHY_RX_INST/u_idesx8/opensync_3_s0/Q
1.331 0.237 tNET FF 1 DPHY_RX_INST/u_idesx8/LUT4_1/I2
1.793 0.462 tINS FR 4 DPHY_RX_INST/u_idesx8/LUT4_1/F
1.973 0.18 tNET RR 1 DPHY_RX_INST/u_idesx8/opensync_0_s0/CE

Data Required Path:
AT DELAY TYPE RF FANOUT NODE
0 0 tCL RR 1 DPHY_RX_INST/U0_IB/I
0.682 0.682 tINS RR 5 DPHY_RX_INST/U0_IB/O
0.862 0.18 tNET RR 1 DPHY_RX_INST/u_idesx8/opensync_0_s0/CLK

Path Statistic:
Clock Skew: 0.062
Hold Relationship: 10.000
Logic Level: 2
Arrival Clock Path Delay: cell: 1.365, 79.130%; route: 0.360, 20.870%
Arrival Data Path Delay: cell: 0.915, 44.897%; route: 0.891, 43.719%; tC2Q: 0.232, 11.384%
Required Clock Path Delay: cell: 1.370, 76.665%; route: 0.417, 23.335%

Path 3

Path Summary:
Slack 8.819
Data Arrival Time 1.974
Data Required Time 10.793
From DPHY_RX_INST/u_idesx8/opensync_3_s0
To DPHY_RX_INST/u_idesx8/opensync_3_s0
Launch Clk HS_CLK_P[R]
Latch Clk HS_CLK_P[R]

Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0 0 tCL RR 1 DPHY_RX_INST/U0_IB/I
0.682 0.682 tINS RR 5 DPHY_RX_INST/U0_IB/O
0.862 0.18 tNET RR 1 DPHY_RX_INST/u_idesx8/opensync_3_s0/CLK
1.094 0.232 tC2Q RF 2 DPHY_RX_INST/u_idesx8/opensync_3_s0/Q
1.331 0.237 tNET FF 1 DPHY_RX_INST/u_idesx8/LUT4_1/I2
1.793 0.462 tINS FR 4 DPHY_RX_INST/u_idesx8/LUT4_1/F
1.973 0.18 tNET RR 1 DPHY_RX_INST/u_idesx8/opensync_3_s0/CE

Data Required Path:
AT DELAY TYPE RF FANOUT NODE
0 0 tCL RR 1 DPHY_RX_INST/U0_IB/I
0.682 0.682 tINS RR 5 DPHY_RX_INST/U0_IB/O
0.862 0.18 tNET RR 1 DPHY_RX_INST/u_idesx8/opensync_3_s0/CLK

Path Statistic:
Clock Skew: 0.062
Hold Relationship: 10.000
Logic Level: 2
Arrival Clock Path Delay: cell: 2.048, 79.130%; route: 0.540, 20.870%
Arrival Data Path Delay: cell: 1.377, 47.206%; route: 1.308, 44.841%; tC2Q: 0.232, 7.953%
Required Clock Path Delay: cell: 2.053, 77.467%; route: 0.597, 22.533%

Path 4

Path Summary:
Slack 8.819
Data Arrival Time 1.974
Data Required Time 10.793
From DPHY_RX_INST/u_idesx8/opensync_3_s0
To DPHY_RX_INST/u_idesx8/opensync_1_s0
Launch Clk HS_CLK_P[R]
Latch Clk HS_CLK_P[R]

Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0 0 tCL RR 1 DPHY_RX_INST/U0_IB/I
0.682 0.682 tINS RR 5 DPHY_RX_INST/U0_IB/O
0.862 0.18 tNET RR 1 DPHY_RX_INST/u_idesx8/opensync_3_s0/CLK
1.094 0.232 tC2Q RF 2 DPHY_RX_INST/u_idesx8/opensync_3_s0/Q
1.331 0.237 tNET FF 1 DPHY_RX_INST/u_idesx8/LUT4_1/I2
1.793 0.462 tINS FR 4 DPHY_RX_INST/u_idesx8/LUT4_1/F
1.973 0.18 tNET RR 1 DPHY_RX_INST/u_idesx8/opensync_1_s0/CE

Data Required Path:
AT DELAY TYPE RF FANOUT NODE
0 0 tCL RR 1 DPHY_RX_INST/U0_IB/I
0.682 0.682 tINS RR 5 DPHY_RX_INST/U0_IB/O
0.862 0.18 tNET RR 1 DPHY_RX_INST/u_idesx8/opensync_1_s0/CLK

Path Statistic:
Clock Skew: 0.062
Hold Relationship: 10.000
Logic Level: 2
Arrival Clock Path Delay: cell: 2.730, 79.130%; route: 0.720, 20.870%
Arrival Data Path Delay: cell: 1.839, 48.446%; route: 1.725, 45.443%; tC2Q: 0.232, 6.112%
Required Clock Path Delay: cell: 2.735, 77.876%; route: 0.777, 22.124%

Path 5

Path Summary:
Slack 8.819
Data Arrival Time 1.974
Data Required Time 10.793
From DPHY_RX_INST/u_idesx8/opensync_3_s0
To DPHY_RX_INST/u_idesx8/opensync_2_s0
Launch Clk HS_CLK_P[R]
Latch Clk HS_CLK_P[R]

Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0 0 tCL RR 1 DPHY_RX_INST/U0_IB/I
0.682 0.682 tINS RR 5 DPHY_RX_INST/U0_IB/O
0.862 0.18 tNET RR 1 DPHY_RX_INST/u_idesx8/opensync_3_s0/CLK
1.094 0.232 tC2Q RF 2 DPHY_RX_INST/u_idesx8/opensync_3_s0/Q
1.331 0.237 tNET FF 1 DPHY_RX_INST/u_idesx8/LUT4_1/I2
1.793 0.462 tINS FR 4 DPHY_RX_INST/u_idesx8/LUT4_1/F
1.973 0.18 tNET RR 1 DPHY_RX_INST/u_idesx8/opensync_2_s0/CE

Data Required Path:
AT DELAY TYPE RF FANOUT NODE
0 0 tCL RR 1 DPHY_RX_INST/U0_IB/I
0.682 0.682 tINS RR 5 DPHY_RX_INST/U0_IB/O
0.862 0.18 tNET RR 1 DPHY_RX_INST/u_idesx8/opensync_2_s0/CLK

Path Statistic:
Clock Skew: 0.062
Hold Relationship: 10.000
Logic Level: 2
Arrival Clock Path Delay: cell: 3.412, 79.130%; route: 0.900, 20.870%
Arrival Data Path Delay: cell: 2.301, 49.219%; route: 2.142, 45.818%; tC2Q: 0.232, 4.963%
Required Clock Path Delay: cell: 3.418, 78.123%; route: 0.957, 21.877%

Synthesis completed successfully!
Process took 0h:0m:2s realtime, 0h:0m:2s cputime
Memory peak: 49.4MB