Project Settings
Project Name ao_0 Device Name rev_1: GOWIN-GW2A : GW2A_18
Implementation Name rev_1 Top Module [auto]
Pipelining 1 Retiming 0
Resource Sharing 1 Fanout Guide 10000
Disable I/O Insertion 0 Disable Sequential Optimizations 0
Clock Conversion 1 FSM Compiler 1

Run Status
Job Name Status CPU Time Real Time Memory Date/Time
(compiler)Complete 6 28 0 - 00m:03s - 2020/9/29
16:33:29
(premap)Complete 6 0 0 0m:02s 0m:02s 224MB 2020/9/29
16:33:34
(fpga_mapper)Complete 9 2 0 0m:08s 0m:09s 251MB 2020/9/29
16:33:44
Multi-srs Generator Complete00m:01s2020/9/29
16:33:31

Area Summary
I/O ports (io_port) 31 Non I/O Register bits (non_io_reg) 298 (1%)
I/O Register bits (total_io_reg) 0 Ultra Rams 0
Block Rams (v_ram) 2 (46) Block Multipliers (dsp_used) 0 (24)
LUTs (total_luts) 396 (1%)

Timing Summary
Clock NameReq FreqEst FreqSlack
ao_top_0|clk_i231.0 MHz196.3 MHz-0.764
ao_top_0|control[0]182.4 MHz155.0 MHz-0.968
System150.0 MHz223.2 MHz2.187

Optimizations Summary
Combined Clock Conversion 2 / 0