#Build: Synplify Pro (R) Q-2020.03G-Beta1, Build 136R, May 11 2020 #install: /share/gwsw/gowin_new/Gowin/Gowin_YunYuan_V1.9.xBeta/SynplifyPro #OS: Linux #Hostname: jinan9110.sdgowin.com # Fri Dec 18 11:22:58 2020 #Implementation: rev_1 Copyright (C) 1994-2020 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: Q-2020.03G-Beta1 Install: /share/gwsw/gowin_new/Gowin/Gowin_YunYuan_V1.9.xBeta/SynplifyPro OS: CentOS release 6.8 (Final) Hostname: jinan9110.sdgowin.com max virtual memory: unlimited (bytes) max user processes: 1024 max stack size: 10485760 (bytes) Implementation : rev_1 Synopsys HDL Compiler, Version comp202003syn, Build 137R, Built May 11 2020 09:27:04, @998475 @N: : | Running in 64-bit mode ###########################################################[ Copyright (C) 1994-2020 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: Q-2020.03G-Beta1 Install: /share/gwsw/gowin_new/Gowin/Gowin_YunYuan_V1.9.xBeta/SynplifyPro OS: CentOS release 6.8 (Final) Hostname: jinan9110.sdgowin.com max virtual memory: unlimited (bytes) max user processes: 1024 max stack size: 10485760 (bytes) Implementation : rev_1 Synopsys Verilog Compiler, Version comp202003syn, Build 137R, Built May 11 2020 09:27:04, @998475 @N: : | Running in 64-bit mode @N:CG1349 : | Running Verilog Compiler in System Verilog mode @N:CG1350 : | Running Verilog Compiler in Multiple File Compilation Unit mode @I::"/share/gwsw/gowin_new/Gowin/Gowin_YunYuan_V1.9.xBeta/SynplifyPro/lib/generic/gw2a.v" (library work) @I::"/share/gwsw/gowin_new/Gowin/Gowin_YunYuan_V1.9.xBeta/SynplifyPro/lib/vlog/hypermods.v" (library __hyper__lib__) @I::"/share/gwsw/gowin_new/Gowin/Gowin_YunYuan_V1.9.xBeta/SynplifyPro/lib/vlog/umr_capim.v" (library snps_haps) @I::"/share/gwsw/gowin_new/Gowin/Gowin_YunYuan_V1.9.xBeta/SynplifyPro/lib/vlog/scemi_objects.v" (library snps_haps) @I::"/share/gwsw/gowin_new/Gowin/Gowin_YunYuan_V1.9.xBeta/SynplifyPro/lib/vlog/scemi_pipes.svh" (library snps_haps) @I::"/share/gwsw/gowin_new/Gowin/Gowin_YunYuan_V1.9.xBeta/IDE/ipcore/IIR_Filter/data/iir_top.v" (library work) @I:"/share/gwsw/gowin_new/Gowin/Gowin_YunYuan_V1.9.xBeta/IDE/ipcore/IIR_Filter/data/iir_top.v":"/iscsi/share/farm/wenxuan/IIR/Ref_Design_1218/Gowin_IIR_Filter_RefDesign/Ref_Design/src/iir_filter/temp/IIR_Filter/define.v" (library work) @I:"/share/gwsw/gowin_new/Gowin/Gowin_YunYuan_V1.9.xBeta/IDE/ipcore/IIR_Filter/data/iir_top.v":"/iscsi/share/farm/wenxuan/IIR/Ref_Design_1218/Gowin_IIR_Filter_RefDesign/Ref_Design/src/iir_filter/temp/IIR_Filter/parameter.v" (library work) @I::"/share/gwsw/gowin_new/Gowin/Gowin_YunYuan_V1.9.xBeta/IDE/ipcore/IIR_Filter/data/iir_top_wrap.v" (library work) @I::"/share/gwsw/gowin_new/Gowin/Gowin_YunYuan_V1.9.xBeta/IDE/ipcore/IIR_Filter/data/static_macro_define.v" (library work) Verilog syntax check successful! Selecting top level module IIR_Filter_Top Running optimization stage 1 on delay_3s_18s ....... Running optimization stage 1 on delay_1s_1s ....... Running optimization stage 1 on delay_4s_18s ....... Opening data file coeff_a_in.dat from directory /iscsi/share/farm/wenxuan/IIR/Ref_Design_1218/Gowin_IIR_Filter_RefDesign/Ref_Design/src/iir_filter/temp/IIR_Filter Running optimization stage 1 on singlerate_coeff_rom_coeff_a_in.dat_12s_18s ....... Opening data file coeff_b_in.dat from directory /iscsi/share/farm/wenxuan/IIR/Ref_Design_1218/Gowin_IIR_Filter_RefDesign/Ref_Design/src/iir_filter/temp/IIR_Filter Running optimization stage 1 on singlerate_coeff_rom_coeff_b_in.dat_12s_18s ....... Running optimization stage 1 on delay_2s_1s ....... Running optimization stage 1 on delay_1s_4s ....... Running optimization stage 1 on syn_signal ....... Running optimization stage 1 on delay_8s_1s ....... Running optimization stage 1 on delay_3s_1s ....... Running optimization stage 1 on delay_4s_1s ....... Running optimization stage 1 on data_round_36s_18s_2s_17s_21s_16s ....... Running optimization stage 1 on shift_reg_6s_18s ....... Running optimization stage 1 on delay_1s_18s ....... Running optimization stage 1 on delay_1s_3s ....... Running optimization stage 1 on dsp_Multiplier_18s_18s_36s ....... Running optimization stage 1 on delay_1s_36s ....... Running optimization stage 1 on delay_3s_3s ....... Running optimization stage 1 on iir_direct_form_ii ....... Running optimization stage 1 on IIR ....... @N:CG364 : iir_top_wrap.v(13) | Synthesizing module IIR_Filter_Top in library work. @W:CS263 : iir_top_wrap.v(64) | Port-width mismatch for port coeff_a. The port definition is 18 bits, but the actual port connection bit width is 32. Adjust either the definition or the instantiation of this port. @W:CS263 : iir_top_wrap.v(65) | Port-width mismatch for port coeff_b. The port definition is 18 bits, but the actual port connection bit width is 32. Adjust either the definition or the instantiation of this port. Running optimization stage 1 on IIR_Filter_Top ....... Running optimization stage 2 on IIR_Filter_Top ....... @W:CL246 : iir_top_wrap.v(44) | Input port bits 31 to 18 of coeff_a[31:0] are unused. Assign logic for all port bits or change the input port size. @W:CL246 : iir_top_wrap.v(45) | Input port bits 31 to 18 of coeff_b[31:0] are unused. Assign logic for all port bits or change the input port size. Running optimization stage 2 on IIR ....... Running optimization stage 2 on delay_3s_3s ....... Running optimization stage 2 on delay_1s_36s ....... Running optimization stage 2 on dsp_Multiplier_18s_18s_36s ....... Running optimization stage 2 on delay_1s_3s ....... Running optimization stage 2 on delay_1s_18s ....... Running optimization stage 2 on shift_reg_6s_18s ....... Running optimization stage 2 on iir_direct_form_ii ....... Running optimization stage 2 on data_round_36s_18s_2s_17s_21s_16s ....... Running optimization stage 2 on delay_4s_1s ....... Running optimization stage 2 on delay_3s_1s ....... Running optimization stage 2 on delay_8s_1s ....... Running optimization stage 2 on syn_signal ....... Running optimization stage 2 on delay_1s_4s ....... Running optimization stage 2 on delay_2s_1s ....... Running optimization stage 2 on singlerate_coeff_rom_coeff_b_in.dat_12s_18s ....... Running optimization stage 2 on singlerate_coeff_rom_coeff_a_in.dat_12s_18s ....... Running optimization stage 2 on delay_4s_18s ....... Running optimization stage 2 on delay_1s_1s ....... Running optimization stage 2 on delay_3s_18s ....... For a summary of runtime and memory usage per design unit, please see file: ========================================================== Linked File: layer0.rt.csv At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 155MB peak: 157MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. # Fri Dec 18 11:23:00 2020 ###########################################################] ###########################################################[ Copyright (C) 1994-2020 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: Q-2020.03G-Beta1 Install: /share/gwsw/gowin_new/Gowin/Gowin_YunYuan_V1.9.xBeta/SynplifyPro OS: CentOS release 6.8 (Final) Hostname: jinan9110.sdgowin.com max virtual memory: unlimited (bytes) max user processes: 1024 max stack size: 10485760 (bytes) Implementation : rev_1 Synopsys Synopsys Netlist Linker, Version comp202003syn, Build 137R, Built May 11 2020 09:27:04, @998475 @N: : | Running in 64-bit mode @N:NF107 : iir_top_wrap.v(13) | Selected library: work cell: IIR_Filter_Top view verilog as top level @N:NF107 : iir_top_wrap.v(13) | Selected library: work cell: IIR_Filter_Top view verilog as top level At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 144MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. # Fri Dec 18 11:23:00 2020 ###########################################################] For a summary of runtime and memory usage for all design units, please see file: ========================================================== Linked File: iir_filter_comp.rt.csv @END At c_hdl Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 56MB peak: 58MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. # Fri Dec 18 11:23:00 2020 ###########################################################] ###########################################################[ Copyright (C) 1994-2020 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: Q-2020.03G-Beta1 Install: /share/gwsw/gowin_new/Gowin/Gowin_YunYuan_V1.9.xBeta/SynplifyPro OS: CentOS release 6.8 (Final) Hostname: jinan9110.sdgowin.com max virtual memory: unlimited (bytes) max user processes: 1024 max stack size: 10485760 (bytes) Implementation : rev_1 Synopsys Synopsys Netlist Linker, Version comp202003syn, Build 137R, Built May 11 2020 09:27:04, @998475 @N: : | Running in 64-bit mode @N:NF107 : iir_top_wrap.v(13) | Selected library: work cell: IIR_Filter_Top view verilog as top level @N:NF107 : iir_top_wrap.v(13) | Selected library: work cell: IIR_Filter_Top view verilog as top level At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 144MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. # Fri Dec 18 11:23:02 2020 ###########################################################] Premap Report # Fri Dec 18 11:23:02 2020 Copyright (C) 1994-2020 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: Q-2020.03G-Beta1 Install: /share/gwsw/gowin_new/Gowin/Gowin_YunYuan_V1.9.xBeta/SynplifyPro OS: CentOS release 6.8 (Final) Hostname: jinan9110.sdgowin.com max virtual memory: unlimited (bytes) max user processes: 1024 max stack size: 10485760 (bytes) Implementation : rev_1 Synopsys Generic Technology Pre-mapping, Version mapgw2020q1p1, Build 004R, Built Jun 18 2020 09:32:57, @1003843 Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 223MB peak: 224MB) @A:MF827 : | No constraint file specified. Linked File: iir_filter_scck.rpt See clock summary report "/iscsi/share/farm/wenxuan/IIR/Ref_Design_1218/Gowin_IIR_Filter_RefDesign/Ref_Design/src/iir_filter/temp/IIR_Filter/rev_1/iir_filter_scck.rpt" @N:MF916 : | Option synthesis_strategy=base is enabled. @N:MF248 : | Running in 64-bit mode. @N:MF666 : | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 238MB peak: 238MB) Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 238MB peak: 239MB) Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 238MB peak: 239MB) Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 251MB peak: 252MB) Starting clock optimization phase (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 334MB peak: 335MB) Finished clock optimization phase (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 334MB peak: 335MB) Starting clock optimization report phase (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 334MB peak: 335MB) @W:BN117 : iir_top_wrap.v(57) | Instance IIR of partition view:work.IIR(verilog) has no references to its outputs; instance not removed. @W:BN117 : iir_top_wrap.v(57) | Instance IIR of partition view:work.IIR(verilog) has no references to its outputs; instance not removed. Finished clock optimization report phase (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 335MB peak: 336MB) Finished netlist restructuring (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 335MB peak: 336MB) Clock Summary ****************** Start Requested Requested Clock Clock Clock Level Clock Frequency Period Type Group Load --------------------------------------------------------------------------------------------------------- 0 - IIR_Filter_Top|clk 150.0 MHz 6.667 inferred Autoconstr_clkgroup_0 1184 ========================================================================================================= Clock Load Summary *********************** Clock Source Clock Pin Non-clock Pin Non-clock Pin Clock Load Pin Seq Example Seq Example Comb Example ----------------------------------------------------------------------------------------------------------------------------- IIR_Filter_Top|clk 1184 clk(port) IIR.iir_direct_form_ii.rmem_addr_wr[3:0].C - - ============================================================================================================================= ICG Latch Removal Summary: Number of ICG latches removed: 0 Number of ICG latches not removed: 0 @S |Clock Optimization Summary #### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[ 1 non-gated/non-generated clock tree(s) driving 993 clock pin(s) of sequential element(s) 0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s) 0 instances converted, 0 sequential instances remain driven by gated/generated clocks =========================== Non-Gated/Non-Generated Clocks ============================ Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance --------------------------------------------------------------------------------------- ClockId_0_0 clk port 993 ENCRYPTED ======================================================================================= ##### END OF CLOCK OPTIMIZATION REPORT ###### @N:FX1143 : | Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized. Finished Pre Mapping Phase. @N:BN225 : | Writing default property annotation file /iscsi/share/farm/wenxuan/IIR/Ref_Design_1218/Gowin_IIR_Filter_RefDesign/Ref_Design/src/iir_filter/temp/IIR_Filter/rev_1/iir_filter.sap. Starting constraint checker (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 335MB peak: 337MB) Finished constraint checker preprocessing (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 335MB peak: 337MB) Finished constraint checker (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 335MB peak: 337MB) Pre-mapping successful! At Mapper Exit (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 335MB peak: 337MB) Process took 0h:00m:03s realtime, 0h:00m:02s cputime # Fri Dec 18 11:23:06 2020 ###########################################################] Map & Optimize Report # Fri Dec 18 11:23:06 2020 Copyright (C) 1994-2020 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: Q-2020.03G-Beta1 Install: /share/gwsw/gowin_new/Gowin/Gowin_YunYuan_V1.9.xBeta/SynplifyPro OS: CentOS release 6.8 (Final) Hostname: jinan9110.sdgowin.com max virtual memory: unlimited (bytes) max user processes: 1024 max stack size: 10485760 (bytes) Implementation : rev_1 Synopsys Generic Technology Mapper, Version mapgw2020q1p1, Build 004R, Built Jun 18 2020 09:32:57, @1003843 Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 223MB peak: 224MB) @N:MF916 : | Option synthesis_strategy=base is enabled. @N:MF248 : | Running in 64-bit mode. @N:MF666 : | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 234MB peak: 234MB) Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 234MB peak: 235MB) Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 234MB peak: 235MB) Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 249MB peak: 250MB) Starting Optimization and Mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 331MB peak: 332MB) Available hyper_sources - for debug and ip models None Found @N:MT206 : | Auto Constrain mode is enabled Finished RTL optimizations (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 331MB peak: 332MB) @N:MF794 : | RAM mem[17:0] required 20 registers during mapping @N:MF794 : | RAM mem[17:0] required 20 registers during mapping @N:MF794 : | RAM rmem_b_1[17:0] required 20 registers during mapping @N:MF794 : | RAM dsp_acc_coeff_b_x\[1\]\.delay_cnt_tdm_x.dReg_CR2[2:0] required 6 registers during mapping @N:MF794 : | RAM dsp_acc_coeff_b_x\[1\]\.delay_a0_i.dReg_CR17[17:0] required 69 registers during mapping @N:MF794 : | RAM mc_data_shift_y\[0\]\.data_shift_y\[0\]\.shift_reg.data_shift\[5\]\.genblk1\.data_r_CR17[17:0] required 79 registers during mapping @N:MF794 : | RAM delay_coeff_b_in.dReg_CR17[17:0] required 43 registers during mapping Starting factoring (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 349MB peak: 349MB) Finished factoring (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:03s; Memory used current: 355MB peak: 355MB) Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:04s; Memory used current: 358MB peak: 358MB) Starting Early Timing Optimization (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:04s; Memory used current: 358MB peak: 359MB) Finished Early Timing Optimization (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:05s; Memory used current: 358MB peak: 359MB) Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:05s; Memory used current: 358MB peak: 359MB) @N:MF794 : | RAM mem[17:0] required 20 registers during mapping @N:MF794 : | RAM mem[17:0] required 18 registers during mapping @N:MF794 : | RAM rmem_b_1[17:0] required 12 registers during mapping @N:MF794 : | RAM dsp_acc_coeff_b_x\[1\]\.delay_cnt_tdm_x.dReg_CR2[2:0] required 6 registers during mapping @N:MF794 : | RAM dsp_acc_coeff_b_x\[1\]\.delay_a0_i.dReg_CR17[17:0] required 69 registers during mapping @N:MF794 : | RAM mc_data_shift_y\[0\]\.data_shift_y\[0\]\.shift_reg.data_shift\[5\]\.genblk1\.data_r_CR17[17:0] required 79 registers during mapping @N:MF794 : | RAM delay_coeff_b_in.dReg_CR17[17:0] required 43 registers during mapping Finished preparing to map (Real Time elapsed 0h:00m:07s; CPU Time elapsed 0h:00m:06s; Memory used current: 358MB peak: 359MB) Finished technology mapping (Real Time elapsed 0h:00m:07s; CPU Time elapsed 0h:00m:06s; Memory used current: 358MB peak: 359MB) Pass CPU time Worst Slack Luts / Registers ------------------------------------------------------------ 1 0h:00m:06s -2.41ns 1250 / 1289 2 0h:00m:06s -2.41ns 1247 / 1289 3 0h:00m:06s -2.41ns 1247 / 1289 4 0h:00m:06s -2.41ns 1247 / 1289 5 0h:00m:06s -2.41ns 1247 / 1289 6 0h:00m:06s -2.41ns 1247 / 1289 Timing driven replication report Added 9 Registers via timing driven replication Added 17 LUTs via timing driven replication 7 0h:00m:07s -2.48ns 1264 / 1298 8 0h:00m:07s -2.45ns 1273 / 1298 9 0h:00m:07s -2.47ns 1275 / 1298 10 0h:00m:07s -2.33ns 1276 / 1298 11 0h:00m:07s -2.46ns 1279 / 1298 12 0h:00m:07s -2.40ns 1281 / 1298 13 0h:00m:07s -2.15ns 1283 / 1298 14 0h:00m:08s -2.29ns 1283 / 1298 15 0h:00m:08s -2.15ns 1283 / 1298 16 0h:00m:08s -2.29ns 1283 / 1298 17 0h:00m:08s -2.15ns 1283 / 1298 18 0h:00m:08s -2.15ns 1283 / 1298 19 0h:00m:08s -2.29ns 1283 / 1298 20 0h:00m:08s -2.29ns 1283 / 1298 @N:MF322 : | Retiming summary: 0 registers retimed to 2 ##### BEGIN RETIMING REPORT ##### Retiming summary : 0 registers retimed to 2 Original and Pipelined registers replaced by retiming : None New registers created by retiming : IIR.iir_direct_form_ii.delay_coeff_a_in.dReg_CF1_ret[0] IIR.iir_direct_form_ii.delay_coeff_a_in.dReg_CF1_ret[1] ##### END RETIMING REPORT ##### Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:09s; CPU Time elapsed 0h:00m:08s; Memory used current: 358MB peak: 359MB) @N:FX164 : | The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute. Finished restoring hierarchy (Real Time elapsed 0h:00m:10s; CPU Time elapsed 0h:00m:09s; Memory used current: 358MB peak: 359MB) Start Writing Netlists (Real Time elapsed 0h:00m:11s; CPU Time elapsed 0h:00m:09s; Memory used current: 358MB peak: 359MB) Writing Analyst data base /iscsi/share/farm/wenxuan/IIR/Ref_Design_1218/Gowin_IIR_Filter_RefDesign/Ref_Design/src/iir_filter/temp/IIR_Filter/rev_1/synwork/iir_filter_m.srm Finished Writing Netlist Databases (Real Time elapsed 0h:00m:12s; CPU Time elapsed 0h:00m:11s; Memory used current: 359MB peak: 359MB) Writing Verilog Simulation files Writing scf file... (Real Time elapsed 0h:00m:15s; CPU Time elapsed 0h:00m:13s; Memory used current: 359MB peak: 360MB) @N:BW103 : | The default time unit for the Synopsys Constraint File (SDC or FDC) is 1ns. @N:BW107 : | Synopsys Constraint File capacitance units using default value of 1pF Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:15s; CPU Time elapsed 0h:00m:13s; Memory used current: 359MB peak: 361MB) Start final timing analysis (Real Time elapsed 0h:00m:16s; CPU Time elapsed 0h:00m:14s; Memory used current: 359MB peak: 361MB) @W:MT246 : iir_top.v(46) | Blackbox MULT18X18 is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) @W:MT246 : iir_top.v(46) | Blackbox MULT18X18 is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) @W:MT246 : iir_top.v(46) | Blackbox MULT18X18 is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) @W:MT246 : iir_top.v(46) | Blackbox MULT18X18 is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) @W:MT420 : | Found inferred clock IIR_Filter_Top|clk with period 6.16ns. Please declare a user-defined clock on port clk. ##### START OF TIMING REPORT #####[ # Timing report written on Fri Dec 18 11:23:23 2020 # Top view: IIR_Filter_Top Requested Frequency: 162.3 MHz Wire load mode: top Paths requested: 5 Constraint File(s): @N:MT320 : | This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report. @N:MT322 : | Clock constraints include only register-to-register paths associated with each individual clock. Performance Summary ******************* Worst slack in design: -1.087 Requested Estimated Requested Estimated Clock Clock Starting Clock Frequency Frequency Period Period Slack Type Group ---------------------------------------------------------------------------------------------------------------------------- IIR_Filter_Top|clk 162.3 MHz 138.0 MHz 6.161 7.248 -1.087 inferred Autoconstr_clkgroup_0 System 150.0 MHz 260.0 MHz 6.667 3.846 2.821 system system_clkgroup ============================================================================================================================ Clock Relationships ******************* Clocks | rise to rise | fall to fall | rise to fall | fall to rise ------------------------------------------------------------------------------------------------------------------------------- Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack ------------------------------------------------------------------------------------------------------------------------------- System IIR_Filter_Top|clk | 6.161 2.821 | No paths - | No paths - | No paths - IIR_Filter_Top|clk System | 6.161 2.007 | No paths - | No paths - | No paths - IIR_Filter_Top|clk IIR_Filter_Top|clk | 6.161 -1.087 | No paths - | No paths - | No paths - =============================================================================================================================== Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups. Interface Information ********************* No IO constraint found ==================================== Detailed Report for Clock: IIR_Filter_Top|clk ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock -------------------------------------------------------------------------------------------------------------------------- IIR.iir_direct_form_ii.dout_r[33] IIR_Filter_Top|clk DFFCE Q dout_r[33] 0.243 -1.087 IIR.iir_direct_form_ii.dout_r_fast[17] IIR_Filter_Top|clk DFFCE Q dout_r_fast[17] 0.243 -1.044 IIR.iir_direct_form_ii.dout_r_fast[16] IIR_Filter_Top|clk DFFCE Q dout_r_fast[16] 0.243 -1.023 IIR.iir_direct_form_ii.dout_r_fast[21] IIR_Filter_Top|clk DFFCE Q dout_r_fast[21] 0.243 -1.009 IIR.iir_direct_form_ii.dout_r_fast[20] IIR_Filter_Top|clk DFFCE Q dout_r_fast[20] 0.243 -0.988 IIR.iir_direct_form_ii.dout_r[25] IIR_Filter_Top|clk DFFCE Q dout_r[25] 0.243 -0.974 IIR.iir_direct_form_ii.dout_r[24] IIR_Filter_Top|clk DFFCE Q dout_r[24] 0.243 -0.953 IIR.iir_direct_form_ii.dout_r[29] IIR_Filter_Top|clk DFFCE Q dout_r[29] 0.243 -0.939 IIR.iir_direct_form_ii.dout_r_fast[18] IIR_Filter_Top|clk DFFCE Q dout_r_fast[18] 0.243 -0.936 IIR.iir_direct_form_ii.dout_r[28] IIR_Filter_Top|clk DFFCE Q dout_r[28] 0.243 -0.918 ========================================================================================================================== Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- IIR.iir_direct_form_ii.mc_data_shift_y\[0\]\.data_shift_y\[0\]\.shift_reg.data_shift\[5\]\.genblk1\.data_r_CR17_data_shift\[5\]\.genblk1\.data_r_CR17_0_3 IIR_Filter_Top|clk RAM16S4 DI[3] dout[15] 6.028 -1.087 IIR.iir_direct_form_ii.mc_data_shift_y\[0\]\.data_shift_y\[0\]\.shift_reg.data_shift\[5\]\.genblk1\.data_r_CR17_data_shift\[5\]\.genblk1\.data_r_CR17_0_4 IIR_Filter_Top|clk RAM16S4 DI[0] dout[16] 6.028 -1.087 IIR.iir_direct_form_ii.mc_data_shift_y\[0\]\.data_shift_y\[0\]\.shift_reg.data_shift\[5\]\.genblk1\.data_r_CR17_data_shift\[5\]\.genblk1\.data_r_CR17_0_3 IIR_Filter_Top|clk RAM16S4 DI[2] dout[14] 6.028 -0.966 IIR.iir_direct_form_ii.mc_data_shift_y\[0\]\.data_shift_y\[0\]\.shift_reg.data_shift\[5\]\.genblk1\.data_r_CR17_data_shift\[5\]\.genblk1\.data_r_CR17_0_3 IIR_Filter_Top|clk RAM16S4 DI[1] dout[13] 6.028 -0.931 IIR.iir_direct_form_ii.mc_data_shift_y\[0\]\.data_shift_y\[0\]\.shift_reg.data_shift\[5\]\.genblk1\.data_r_CR17_data_shift\[5\]\.genblk1\.data_r_CR17_0_3 IIR_Filter_Top|clk RAM16S4 DI[0] dout[12] 6.028 -0.896 IIR.iir_direct_form_ii.mc_data_shift_y\[0\]\.data_shift_y\[0\]\.shift_reg.data_shift\[5\]\.genblk1\.data_r_CR17_data_shift\[5\]\.genblk1\.data_r_CR17_0_2 IIR_Filter_Top|clk RAM16S4 DI[3] dout[11] 6.028 -0.861 IIR.iir_direct_form_ii.mc_data_shift_y\[0\]\.data_shift_y\[0\]\.shift_reg.data_shift\[5\]\.genblk1\.data_r_CR17_data_shift\[5\]\.genblk1\.data_r_CR17_0_2 IIR_Filter_Top|clk RAM16S4 DI[2] dout[10] 6.028 -0.826 IIR.iir_direct_form_ii.mc_data_shift_y\[0\]\.data_shift_y\[0\]\.shift_reg.data_shift\[5\]\.genblk1\.data_r_CR17_data_shift\[5\]\.genblk1\.data_r_CR17_0_2 IIR_Filter_Top|clk RAM16S4 DI[1] dout[9] 6.028 -0.791 IIR.iir_direct_form_ii.mc_data_shift_y\[0\]\.data_shift_y\[0\]\.shift_reg.data_shift\[5\]\.genblk1\.data_r_CR17_data_shift\[5\]\.genblk1\.data_r_CR17_0_0 IIR_Filter_Top|clk RAM16S4 DI[0] dout[0] 6.028 -0.789 IIR.iir_direct_form_ii.mc_data_shift_y\[0\]\.data_shift_y\[0\]\.shift_reg.data_shift\[5\]\.genblk1\.data_r_CR17_data_shift\[5\]\.genblk1\.data_r_CR17_0_0 IIR_Filter_Top|clk RAM16S4 DI[1] dout[1] 6.028 -0.789 =========================================================================================================================================================================================================================================== Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 6.161 - Setup time: 0.133 + Clock delay at ending point: 0.000 (ideal) = Required time: 6.028 - Propagation time: 7.115 - Clock delay at starting point: 0.000 (ideal) = Slack (critical) : -1.087 Number of logic level(s): 7 Starting point: IIR.iir_direct_form_ii.dout_r[33] / Q Ending point: IIR.iir_direct_form_ii.mc_data_shift_y\[0\]\.data_shift_y\[0\]\.shift_reg.data_shift\[5\]\.genblk1\.data_r_CR17_data_shift\[5\]\.genblk1\.data_r_CR17_0_3 / DI[3] The start point is clocked by IIR_Filter_Top|clk [rising] (rise=0.000 fall=3.080 period=6.161) on pin CLK The end point is clocked by IIR_Filter_Top|clk [rising] (rise=0.000 fall=3.080 period=6.161) on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ IIR.iir_direct_form_ii.dout_r[33] DFFCE Q Out 0.243 0.243 r - dout_r[33] Net - - 0.718 - 37 IIR.iir_direct_form_ii.data_round.temp_data_1_axb_16_par_0_lofx LUT3 I1 In - 0.961 r - IIR.iir_direct_form_ii.data_round.temp_data_1_axb_16_par_0_lofx LUT3 F Out 0.570 1.531 r - temp_data_1_axb_16_par_0_lofx Net - - 0.535 - 1 IIR.iir_direct_form_ii.data_round.temp_data_1_axb_16_par_1 ALU I0 In - 2.066 r - IIR.iir_direct_form_ii.data_round.temp_data_1_axb_16_par_1 ALU COUT Out 0.549 2.615 r - temp_data_1_axb_16_par_1_COUT Net - - 0.000 - 1 IIR.iir_direct_form_ii.data_round.temp_data_1_cry_19_0 ALU CIN In - 2.615 r - IIR.iir_direct_form_ii.data_round.temp_data_1_cry_19_0 ALU SUM Out 0.470 3.085 f - temp_data1[19] Net - - 0.535 - 1 IIR.iir_direct_form_ii.data_round.temp_data_m[19] LUT3 I1 In - 3.620 f - IIR.iir_direct_form_ii.data_round.temp_data_m[19] LUT3 F Out 0.570 4.190 r - temp_data[19] Net - - 0.718 - 32 IIR.iir_direct_form_ii.data_round.dout_1_1_0_0[15] LUT4 I2 In - 4.908 r - IIR.iir_direct_form_ii.data_round.dout_1_1_0_0[15] LUT4 F Out 0.462 5.370 r - dout_1_1_0_0[15] Net - - 0.000 - 1 IIR.iir_direct_form_ii.data_round.dout_1_1_0[15] MUX2_LUT5 I0 In - 5.370 r - IIR.iir_direct_form_ii.data_round.dout_1_1_0[15] MUX2_LUT5 O Out 0.105 5.475 r - dout_1_1_0[15] Net - - 0.535 - 1 IIR.iir_direct_form_ii.data_round.dout_1[15] LUT4 I1 In - 6.010 r - IIR.iir_direct_form_ii.data_round.dout_1[15] LUT4 F Out 0.570 6.580 r - dout[15] Net - - 0.535 - 2 IIR.iir_direct_form_ii.mc_data_shift_y\[0\]\.data_shift_y\[0\]\.shift_reg.data_shift\[5\]\.genblk1\.data_r_CR17_data_shift\[5\]\.genblk1\.data_r_CR17_0_3 RAM16S4 DI[3] In - 7.115 r - ============================================================================================================================================================================================================================== Total path delay (propagation time + setup) of 7.248 is 3.672(50.7%) logic and 3.576(49.3%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 2: Requested Period: 6.161 - Setup time: 0.133 + Clock delay at ending point: 0.000 (ideal) = Required time: 6.028 - Propagation time: 7.115 - Clock delay at starting point: 0.000 (ideal) = Slack (critical) : -1.087 Number of logic level(s): 7 Starting point: IIR.iir_direct_form_ii.dout_r[33] / Q Ending point: IIR.iir_direct_form_ii.mc_data_shift_y\[0\]\.data_shift_y\[0\]\.shift_reg.data_shift\[5\]\.genblk1\.data_r_CR17_data_shift\[5\]\.genblk1\.data_r_CR17_0_3 / DI[3] The start point is clocked by IIR_Filter_Top|clk [rising] (rise=0.000 fall=3.080 period=6.161) on pin CLK The end point is clocked by IIR_Filter_Top|clk [rising] (rise=0.000 fall=3.080 period=6.161) on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ IIR.iir_direct_form_ii.dout_r[33] DFFCE Q Out 0.243 0.243 r - dout_r[33] Net - - 0.718 - 37 IIR.iir_direct_form_ii.data_round.temp_data_1_axb_16_par_0_lofx LUT3 I1 In - 0.961 r - IIR.iir_direct_form_ii.data_round.temp_data_1_axb_16_par_0_lofx LUT3 F Out 0.570 1.531 r - temp_data_1_axb_16_par_0_lofx Net - - 0.535 - 1 IIR.iir_direct_form_ii.data_round.temp_data_1_axb_16_par_1 ALU I0 In - 2.066 r - IIR.iir_direct_form_ii.data_round.temp_data_1_axb_16_par_1 ALU COUT Out 0.549 2.615 r - temp_data_1_axb_16_par_1_COUT Net - - 0.000 - 1 IIR.iir_direct_form_ii.data_round.temp_data_1_cry_19_0 ALU CIN In - 2.615 r - IIR.iir_direct_form_ii.data_round.temp_data_1_cry_19_0 ALU SUM Out 0.470 3.085 f - temp_data1[19] Net - - 0.535 - 1 IIR.iir_direct_form_ii.data_round.temp_data_m[19] LUT3 I1 In - 3.620 f - IIR.iir_direct_form_ii.data_round.temp_data_m[19] LUT3 F Out 0.570 4.190 r - temp_data[19] Net - - 0.718 - 32 IIR.iir_direct_form_ii.data_round.dout_1_1_0_1[15] LUT4 I2 In - 4.908 r - IIR.iir_direct_form_ii.data_round.dout_1_1_0_1[15] LUT4 F Out 0.462 5.370 r - dout_1_1_0_1[15] Net - - 0.000 - 1 IIR.iir_direct_form_ii.data_round.dout_1_1_0[15] MUX2_LUT5 I1 In - 5.370 r - IIR.iir_direct_form_ii.data_round.dout_1_1_0[15] MUX2_LUT5 O Out 0.105 5.475 r - dout_1_1_0[15] Net - - 0.535 - 1 IIR.iir_direct_form_ii.data_round.dout_1[15] LUT4 I1 In - 6.010 r - IIR.iir_direct_form_ii.data_round.dout_1[15] LUT4 F Out 0.570 6.580 r - dout[15] Net - - 0.535 - 2 IIR.iir_direct_form_ii.mc_data_shift_y\[0\]\.data_shift_y\[0\]\.shift_reg.data_shift\[5\]\.genblk1\.data_r_CR17_data_shift\[5\]\.genblk1\.data_r_CR17_0_3 RAM16S4 DI[3] In - 7.115 r - ============================================================================================================================================================================================================================== Total path delay (propagation time + setup) of 7.248 is 3.672(50.7%) logic and 3.576(49.3%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 3: Requested Period: 6.161 - Setup time: 0.133 + Clock delay at ending point: 0.000 (ideal) = Required time: 6.028 - Propagation time: 7.115 - Clock delay at starting point: 0.000 (ideal) = Slack (critical) : -1.087 Number of logic level(s): 7 Starting point: IIR.iir_direct_form_ii.dout_r[33] / Q Ending point: IIR.iir_direct_form_ii.mc_data_shift_y\[0\]\.data_shift_y\[0\]\.shift_reg.data_shift\[5\]\.genblk1\.data_r_CR17_data_shift\[5\]\.genblk1\.data_r_CR17_0_4 / DI[0] The start point is clocked by IIR_Filter_Top|clk [rising] (rise=0.000 fall=3.080 period=6.161) on pin CLK The end point is clocked by IIR_Filter_Top|clk [rising] (rise=0.000 fall=3.080 period=6.161) on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ IIR.iir_direct_form_ii.dout_r[33] DFFCE Q Out 0.243 0.243 r - dout_r[33] Net - - 0.718 - 37 IIR.iir_direct_form_ii.data_round.temp_data_1_axb_16_par_0_lofx LUT3 I1 In - 0.961 r - IIR.iir_direct_form_ii.data_round.temp_data_1_axb_16_par_0_lofx LUT3 F Out 0.570 1.531 r - temp_data_1_axb_16_par_0_lofx Net - - 0.535 - 1 IIR.iir_direct_form_ii.data_round.temp_data_1_axb_16_par_1 ALU I0 In - 2.066 r - IIR.iir_direct_form_ii.data_round.temp_data_1_axb_16_par_1 ALU COUT Out 0.549 2.615 r - temp_data_1_axb_16_par_1_COUT Net - - 0.000 - 1 IIR.iir_direct_form_ii.data_round.temp_data_1_cry_19_0 ALU CIN In - 2.615 r - IIR.iir_direct_form_ii.data_round.temp_data_1_cry_19_0 ALU SUM Out 0.470 3.085 f - temp_data1[19] Net - - 0.535 - 1 IIR.iir_direct_form_ii.data_round.temp_data_m[19] LUT3 I1 In - 3.620 f - IIR.iir_direct_form_ii.data_round.temp_data_m[19] LUT3 F Out 0.570 4.190 r - temp_data[19] Net - - 0.718 - 32 IIR.iir_direct_form_ii.data_round.dout_1_1_0_1[16] LUT4 I2 In - 4.908 r - IIR.iir_direct_form_ii.data_round.dout_1_1_0_1[16] LUT4 F Out 0.462 5.370 r - dout_1_1_0_1[16] Net - - 0.000 - 1 IIR.iir_direct_form_ii.data_round.dout_1_1_0[16] MUX2_LUT5 I1 In - 5.370 r - IIR.iir_direct_form_ii.data_round.dout_1_1_0[16] MUX2_LUT5 O Out 0.105 5.475 r - dout_1_1_0[16] Net - - 0.535 - 1 IIR.iir_direct_form_ii.data_round.dout_1[16] LUT4 I1 In - 6.010 r - IIR.iir_direct_form_ii.data_round.dout_1[16] LUT4 F Out 0.570 6.580 r - dout[16] Net - - 0.535 - 2 IIR.iir_direct_form_ii.mc_data_shift_y\[0\]\.data_shift_y\[0\]\.shift_reg.data_shift\[5\]\.genblk1\.data_r_CR17_data_shift\[5\]\.genblk1\.data_r_CR17_0_4 RAM16S4 DI[0] In - 7.115 r - ============================================================================================================================================================================================================================== Total path delay (propagation time + setup) of 7.248 is 3.672(50.7%) logic and 3.576(49.3%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 4: Requested Period: 6.161 - Setup time: 0.133 + Clock delay at ending point: 0.000 (ideal) = Required time: 6.028 - Propagation time: 7.115 - Clock delay at starting point: 0.000 (ideal) = Slack (critical) : -1.087 Number of logic level(s): 7 Starting point: IIR.iir_direct_form_ii.dout_r[33] / Q Ending point: IIR.iir_direct_form_ii.mc_data_shift_y\[0\]\.data_shift_y\[0\]\.shift_reg.data_shift\[5\]\.genblk1\.data_r_CR17_data_shift\[5\]\.genblk1\.data_r_CR17_0_4 / DI[0] The start point is clocked by IIR_Filter_Top|clk [rising] (rise=0.000 fall=3.080 period=6.161) on pin CLK The end point is clocked by IIR_Filter_Top|clk [rising] (rise=0.000 fall=3.080 period=6.161) on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ IIR.iir_direct_form_ii.dout_r[33] DFFCE Q Out 0.243 0.243 r - dout_r[33] Net - - 0.718 - 37 IIR.iir_direct_form_ii.data_round.temp_data_1_axb_16_par_0_lofx LUT3 I1 In - 0.961 r - IIR.iir_direct_form_ii.data_round.temp_data_1_axb_16_par_0_lofx LUT3 F Out 0.570 1.531 r - temp_data_1_axb_16_par_0_lofx Net - - 0.535 - 1 IIR.iir_direct_form_ii.data_round.temp_data_1_axb_16_par_1 ALU I0 In - 2.066 r - IIR.iir_direct_form_ii.data_round.temp_data_1_axb_16_par_1 ALU COUT Out 0.549 2.615 r - temp_data_1_axb_16_par_1_COUT Net - - 0.000 - 1 IIR.iir_direct_form_ii.data_round.temp_data_1_cry_19_0 ALU CIN In - 2.615 r - IIR.iir_direct_form_ii.data_round.temp_data_1_cry_19_0 ALU SUM Out 0.470 3.085 f - temp_data1[19] Net - - 0.535 - 1 IIR.iir_direct_form_ii.data_round.temp_data_m[19] LUT3 I1 In - 3.620 f - IIR.iir_direct_form_ii.data_round.temp_data_m[19] LUT3 F Out 0.570 4.190 r - temp_data[19] Net - - 0.718 - 32 IIR.iir_direct_form_ii.data_round.dout_1_1_0_0[16] LUT4 I2 In - 4.908 r - IIR.iir_direct_form_ii.data_round.dout_1_1_0_0[16] LUT4 F Out 0.462 5.370 r - dout_1_1_0_0[16] Net - - 0.000 - 1 IIR.iir_direct_form_ii.data_round.dout_1_1_0[16] MUX2_LUT5 I0 In - 5.370 r - IIR.iir_direct_form_ii.data_round.dout_1_1_0[16] MUX2_LUT5 O Out 0.105 5.475 r - dout_1_1_0[16] Net - - 0.535 - 1 IIR.iir_direct_form_ii.data_round.dout_1[16] LUT4 I1 In - 6.010 r - IIR.iir_direct_form_ii.data_round.dout_1[16] LUT4 F Out 0.570 6.580 r - dout[16] Net - - 0.535 - 2 IIR.iir_direct_form_ii.mc_data_shift_y\[0\]\.data_shift_y\[0\]\.shift_reg.data_shift\[5\]\.genblk1\.data_r_CR17_data_shift\[5\]\.genblk1\.data_r_CR17_0_4 RAM16S4 DI[0] In - 7.115 r - ============================================================================================================================================================================================================================== Total path delay (propagation time + setup) of 7.248 is 3.672(50.7%) logic and 3.576(49.3%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 5: Requested Period: 6.161 - Setup time: 0.133 + Clock delay at ending point: 0.000 (ideal) = Required time: 6.028 - Propagation time: 7.072 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -1.044 Number of logic level(s): 11 Starting point: IIR.iir_direct_form_ii.dout_r_fast[17] / Q Ending point: IIR.iir_direct_form_ii.mc_data_shift_y\[0\]\.data_shift_y\[0\]\.shift_reg.data_shift\[5\]\.genblk1\.data_r_CR17_data_shift\[5\]\.genblk1\.data_r_CR17_0_3 / DI[3] The start point is clocked by IIR_Filter_Top|clk [rising] (rise=0.000 fall=3.080 period=6.161) on pin CLK The end point is clocked by IIR_Filter_Top|clk [rising] (rise=0.000 fall=3.080 period=6.161) on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ IIR.iir_direct_form_ii.dout_r_fast[17] DFFCE Q Out 0.243 0.243 r - dout_r_fast[17] Net - - 0.535 - 2 IIR.iir_direct_form_ii.data_round.temp_data_1_axb_0_par_0_cp LUT4 I1 In - 0.778 r - IIR.iir_direct_form_ii.data_round.temp_data_1_axb_0_par_0_cp LUT4 F Out 0.570 1.348 r - temp_data_1_axb_0_par_0_cp Net - - 0.535 - 1 IIR.iir_direct_form_ii.data_round.temp_data_1_axb_0_par_cp_0 ALU I0 In - 1.883 r - IIR.iir_direct_form_ii.data_round.temp_data_1_axb_0_par_cp_0 ALU COUT Out 0.549 2.432 r - temp_data_1_axb_0_par_cp_0_COUT Net - - 0.000 - 1 IIR.iir_direct_form_ii.data_round.temp_data_1_axb_4_par_cp_0 ALU CIN In - 2.432 r - IIR.iir_direct_form_ii.data_round.temp_data_1_axb_4_par_cp_0 ALU COUT Out 0.035 2.467 r - temp_data_1_axb_4_par_cp_0_COUT Net - - 0.000 - 1 IIR.iir_direct_form_ii.data_round.temp_data_1_axb_8_par_1 ALU CIN In - 2.467 r - IIR.iir_direct_form_ii.data_round.temp_data_1_axb_8_par_1 ALU COUT Out 0.035 2.502 r - temp_data_1_axb_8_par_1_COUT Net - - 0.000 - 1 IIR.iir_direct_form_ii.data_round.temp_data_1_axb_12_par_1 ALU CIN In - 2.502 r - IIR.iir_direct_form_ii.data_round.temp_data_1_axb_12_par_1 ALU COUT Out 0.035 2.537 r - temp_data_1_axb_12_par_1_COUT Net - - 0.000 - 1 IIR.iir_direct_form_ii.data_round.temp_data_1_axb_16_par_1 ALU CIN In - 2.537 r - IIR.iir_direct_form_ii.data_round.temp_data_1_axb_16_par_1 ALU COUT Out 0.035 2.572 r - temp_data_1_axb_16_par_1_COUT Net - - 0.000 - 1 IIR.iir_direct_form_ii.data_round.temp_data_1_cry_19_0 ALU CIN In - 2.572 r - IIR.iir_direct_form_ii.data_round.temp_data_1_cry_19_0 ALU SUM Out 0.470 3.042 f - temp_data1[19] Net - - 0.535 - 1 IIR.iir_direct_form_ii.data_round.temp_data_m[19] LUT3 I1 In - 3.577 f - IIR.iir_direct_form_ii.data_round.temp_data_m[19] LUT3 F Out 0.570 4.147 r - temp_data[19] Net - - 0.718 - 32 IIR.iir_direct_form_ii.data_round.dout_1_1_0_0[15] LUT4 I2 In - 4.865 r - IIR.iir_direct_form_ii.data_round.dout_1_1_0_0[15] LUT4 F Out 0.462 5.327 r - dout_1_1_0_0[15] Net - - 0.000 - 1 IIR.iir_direct_form_ii.data_round.dout_1_1_0[15] MUX2_LUT5 I0 In - 5.327 r - IIR.iir_direct_form_ii.data_round.dout_1_1_0[15] MUX2_LUT5 O Out 0.105 5.432 r - dout_1_1_0[15] Net - - 0.535 - 1 IIR.iir_direct_form_ii.data_round.dout_1[15] LUT4 I1 In - 5.967 r - IIR.iir_direct_form_ii.data_round.dout_1[15] LUT4 F Out 0.570 6.537 r - dout[15] Net - - 0.535 - 2 IIR.iir_direct_form_ii.mc_data_shift_y\[0\]\.data_shift_y\[0\]\.shift_reg.data_shift\[5\]\.genblk1\.data_r_CR17_data_shift\[5\]\.genblk1\.data_r_CR17_0_3 RAM16S4 DI[3] In - 7.072 r - ============================================================================================================================================================================================================================== Total path delay (propagation time + setup) of 7.205 is 3.812(52.9%) logic and 3.393(47.1%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ==================================== Detailed Report for Clock: System ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock -------------------------------------------------------------------------------------------------------------------------------------------------------------------------- IIR.iir_direct_form_ii.dsp_acc_coeff_b_x\[1\]\.dsp_Multiplier_b.un3_dout_r_mulonly_0[35:0] System MULT18X18 DOUT[0] un3_dout_r[0] 0.000 2.821 IIR.iir_direct_form_ii.dsp_acc_coeff_a_y\[1\]\.dsp_Multiplier_a.un3_dout_r_mulonly_0[35:0] System MULT18X18 DOUT[0] un3_dout_r[0] 0.000 2.821 IIR.iir_direct_form_ii.dsp_acc_coeff_b_x\[1\]\.dsp_Multiplier_b.un3_dout_r_mulonly_0[35:0] System MULT18X18 DOUT[1] un3_dout_r[1] 0.000 2.856 IIR.iir_direct_form_ii.dsp_acc_coeff_a_y\[1\]\.dsp_Multiplier_a.un3_dout_r_mulonly_0[35:0] System MULT18X18 DOUT[1] un3_dout_r[1] 0.000 2.856 IIR.iir_direct_form_ii.dsp_acc_coeff_a_y\[1\]\.dsp_Multiplier_a.un3_dout_r_mulonly_0[35:0] System MULT18X18 DOUT[2] un3_dout_r[2] 0.000 2.891 IIR.iir_direct_form_ii.dsp_acc_coeff_b_x\[1\]\.dsp_Multiplier_b.un3_dout_r_mulonly_0[35:0] System MULT18X18 DOUT[2] un3_dout_r[2] 0.000 2.891 IIR.iir_direct_form_ii.dsp_acc_coeff_a_y\[1\]\.dsp_Multiplier_a.un3_dout_r_mulonly_0[35:0] System MULT18X18 DOUT[3] un3_dout_r[3] 0.000 2.926 IIR.iir_direct_form_ii.dsp_acc_coeff_b_x\[1\]\.dsp_Multiplier_b.un3_dout_r_mulonly_0[35:0] System MULT18X18 DOUT[3] un3_dout_r[3] 0.000 2.926 IIR.iir_direct_form_ii.dsp_acc_coeff_b_x\[1\]\.dsp_Multiplier_b.un3_dout_r_mulonly_0[35:0] System MULT18X18 DOUT[4] un3_dout_r[4] 0.000 2.961 IIR.iir_direct_form_ii.dsp_acc_coeff_a_y\[1\]\.dsp_Multiplier_a.un3_dout_r_mulonly_0[35:0] System MULT18X18 DOUT[4] un3_dout_r[4] 0.000 2.961 ========================================================================================================================================================================== Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock --------------------------------------------------------------------------------------------------------------------------------------------------- IIR.iir_direct_form_ii.dsp_acc_coeff_b_x\[1\]\.dsp_Multiplier_b.dout_r[35] System DFFC D un2_dout_r[35] 6.100 2.821 IIR.iir_direct_form_ii.dsp_acc_coeff_a_y\[1\]\.dsp_Multiplier_a.dout_r[35] System DFFC D un2_dout_r[35] 6.100 2.821 IIR.iir_direct_form_ii.dsp_acc_coeff_b_x\[1\]\.dsp_Multiplier_b.dout_r[34] System DFFC D un2_dout_r[34] 6.100 2.856 IIR.iir_direct_form_ii.dsp_acc_coeff_a_y\[1\]\.dsp_Multiplier_a.dout_r[34] System DFFC D un2_dout_r[34] 6.100 2.856 IIR.iir_direct_form_ii.dsp_acc_coeff_b_x\[1\]\.dsp_Multiplier_b.dout_r[33] System DFFC D un2_dout_r[33] 6.100 2.891 IIR.iir_direct_form_ii.dsp_acc_coeff_a_y\[1\]\.dsp_Multiplier_a.dout_r[33] System DFFC D un2_dout_r[33] 6.100 2.891 IIR.iir_direct_form_ii.dsp_acc_coeff_a_y\[1\]\.dsp_Multiplier_a.dout_r[32] System DFFC D un2_dout_r[32] 6.100 2.926 IIR.iir_direct_form_ii.dsp_acc_coeff_b_x\[1\]\.dsp_Multiplier_b.dout_r[32] System DFFC D un2_dout_r[32] 6.100 2.926 IIR.iir_direct_form_ii.dsp_acc_coeff_b_x\[1\]\.dsp_Multiplier_b.dout_r[31] System DFFC D un2_dout_r[31] 6.100 2.961 IIR.iir_direct_form_ii.dsp_acc_coeff_a_y\[1\]\.dsp_Multiplier_a.dout_r[31] System DFFC D un2_dout_r[31] 6.100 2.961 =================================================================================================================================================== Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 6.161 - Setup time: 0.061 + Clock delay at ending point: 0.000 (ideal) = Required time: 6.100 - Propagation time: 3.279 - Clock delay at starting point: 0.000 (ideal) - Estimated clock delay at start point: -0.000 = Slack (non-critical) : 2.821 Number of logic level(s): 36 Starting point: IIR.iir_direct_form_ii.dsp_acc_coeff_b_x\[1\]\.dsp_Multiplier_b.un3_dout_r_mulonly_0[35:0] / DOUT[0] Ending point: IIR.iir_direct_form_ii.dsp_acc_coeff_b_x\[1\]\.dsp_Multiplier_b.dout_r[35] / D The start point is clocked by System [rising] The end point is clocked by IIR_Filter_Top|clk [rising] (rise=0.000 fall=3.080 period=6.161) on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ----------------------------------------------------------------------------------------------------------------------------------------------------------------- IIR.iir_direct_form_ii.dsp_acc_coeff_b_x\[1\]\.dsp_Multiplier_b.un3_dout_r_mulonly_0[35:0] MULT18X18 DOUT[0] Out 0.000 0.000 r - un3_dout_r[0] Net - - 0.535 - 1 IIR.iir_direct_form_ii.dsp_acc_coeff_b_x\[1\]\.dsp_Multiplier_b.un2_dout_r_cry_0_0 ALU I0 In - 0.535 r - IIR.iir_direct_form_ii.dsp_acc_coeff_b_x\[1\]\.dsp_Multiplier_b.un2_dout_r_cry_0_0 ALU COUT Out 0.549 1.084 r - un2_dout_r_cry_0 Net - - 0.000 - 1 IIR.iir_direct_form_ii.dsp_acc_coeff_b_x\[1\]\.dsp_Multiplier_b.un2_dout_r_cry_1_0 ALU CIN In - 1.084 r - IIR.iir_direct_form_ii.dsp_acc_coeff_b_x\[1\]\.dsp_Multiplier_b.un2_dout_r_cry_1_0 ALU COUT Out 0.035 1.119 r - un2_dout_r_cry_1 Net - - 0.000 - 1 IIR.iir_direct_form_ii.dsp_acc_coeff_b_x\[1\]\.dsp_Multiplier_b.un2_dout_r_cry_2_0 ALU CIN In - 1.119 r - IIR.iir_direct_form_ii.dsp_acc_coeff_b_x\[1\]\.dsp_Multiplier_b.un2_dout_r_cry_2_0 ALU COUT Out 0.035 1.154 r - un2_dout_r_cry_2 Net - - 0.000 - 1 IIR.iir_direct_form_ii.dsp_acc_coeff_b_x\[1\]\.dsp_Multiplier_b.un2_dout_r_cry_3_0 ALU CIN In - 1.154 r - IIR.iir_direct_form_ii.dsp_acc_coeff_b_x\[1\]\.dsp_Multiplier_b.un2_dout_r_cry_3_0 ALU COUT Out 0.035 1.189 r - un2_dout_r_cry_3 Net - - 0.000 - 1 IIR.iir_direct_form_ii.dsp_acc_coeff_b_x\[1\]\.dsp_Multiplier_b.un2_dout_r_cry_4_0 ALU CIN In - 1.189 r - IIR.iir_direct_form_ii.dsp_acc_coeff_b_x\[1\]\.dsp_Multiplier_b.un2_dout_r_cry_4_0 ALU COUT Out 0.035 1.224 r - un2_dout_r_cry_4 Net - - 0.000 - 1 IIR.iir_direct_form_ii.dsp_acc_coeff_b_x\[1\]\.dsp_Multiplier_b.un2_dout_r_cry_5_0 ALU CIN In - 1.224 r - IIR.iir_direct_form_ii.dsp_acc_coeff_b_x\[1\]\.dsp_Multiplier_b.un2_dout_r_cry_5_0 ALU COUT Out 0.035 1.259 r - un2_dout_r_cry_5 Net - - 0.000 - 1 IIR.iir_direct_form_ii.dsp_acc_coeff_b_x\[1\]\.dsp_Multiplier_b.un2_dout_r_cry_6_0 ALU CIN In - 1.259 r - IIR.iir_direct_form_ii.dsp_acc_coeff_b_x\[1\]\.dsp_Multiplier_b.un2_dout_r_cry_6_0 ALU COUT Out 0.035 1.294 r - un2_dout_r_cry_6 Net - - 0.000 - 1 IIR.iir_direct_form_ii.dsp_acc_coeff_b_x\[1\]\.dsp_Multiplier_b.un2_dout_r_cry_7_0 ALU CIN In - 1.294 r - IIR.iir_direct_form_ii.dsp_acc_coeff_b_x\[1\]\.dsp_Multiplier_b.un2_dout_r_cry_7_0 ALU COUT Out 0.035 1.329 r - un2_dout_r_cry_7 Net - - 0.000 - 1 IIR.iir_direct_form_ii.dsp_acc_coeff_b_x\[1\]\.dsp_Multiplier_b.un2_dout_r_cry_8_0 ALU CIN In - 1.329 r - IIR.iir_direct_form_ii.dsp_acc_coeff_b_x\[1\]\.dsp_Multiplier_b.un2_dout_r_cry_8_0 ALU COUT Out 0.035 1.364 r - un2_dout_r_cry_8 Net - - 0.000 - 1 IIR.iir_direct_form_ii.dsp_acc_coeff_b_x\[1\]\.dsp_Multiplier_b.un2_dout_r_cry_9_0 ALU CIN In - 1.364 r - IIR.iir_direct_form_ii.dsp_acc_coeff_b_x\[1\]\.dsp_Multiplier_b.un2_dout_r_cry_9_0 ALU COUT Out 0.035 1.399 r - un2_dout_r_cry_9 Net - - 0.000 - 1 IIR.iir_direct_form_ii.dsp_acc_coeff_b_x\[1\]\.dsp_Multiplier_b.un2_dout_r_cry_10_0 ALU CIN In - 1.399 r - IIR.iir_direct_form_ii.dsp_acc_coeff_b_x\[1\]\.dsp_Multiplier_b.un2_dout_r_cry_10_0 ALU COUT Out 0.035 1.434 r - un2_dout_r_cry_10 Net - - 0.000 - 1 IIR.iir_direct_form_ii.dsp_acc_coeff_b_x\[1\]\.dsp_Multiplier_b.un2_dout_r_cry_11_0 ALU CIN In - 1.434 r - IIR.iir_direct_form_ii.dsp_acc_coeff_b_x\[1\]\.dsp_Multiplier_b.un2_dout_r_cry_11_0 ALU COUT Out 0.035 1.469 r - un2_dout_r_cry_11 Net - - 0.000 - 1 IIR.iir_direct_form_ii.dsp_acc_coeff_b_x\[1\]\.dsp_Multiplier_b.un2_dout_r_cry_12_0 ALU CIN In - 1.469 r - IIR.iir_direct_form_ii.dsp_acc_coeff_b_x\[1\]\.dsp_Multiplier_b.un2_dout_r_cry_12_0 ALU COUT Out 0.035 1.504 r - un2_dout_r_cry_12 Net - - 0.000 - 1 IIR.iir_direct_form_ii.dsp_acc_coeff_b_x\[1\]\.dsp_Multiplier_b.un2_dout_r_cry_13_0 ALU CIN In - 1.504 r - IIR.iir_direct_form_ii.dsp_acc_coeff_b_x\[1\]\.dsp_Multiplier_b.un2_dout_r_cry_13_0 ALU COUT Out 0.035 1.539 r - un2_dout_r_cry_13 Net - - 0.000 - 1 IIR.iir_direct_form_ii.dsp_acc_coeff_b_x\[1\]\.dsp_Multiplier_b.un2_dout_r_cry_14_0 ALU CIN In - 1.539 r - IIR.iir_direct_form_ii.dsp_acc_coeff_b_x\[1\]\.dsp_Multiplier_b.un2_dout_r_cry_14_0 ALU COUT Out 0.035 1.574 r - un2_dout_r_cry_14 Net - - 0.000 - 1 IIR.iir_direct_form_ii.dsp_acc_coeff_b_x\[1\]\.dsp_Multiplier_b.un2_dout_r_cry_15_0 ALU CIN In - 1.574 r - IIR.iir_direct_form_ii.dsp_acc_coeff_b_x\[1\]\.dsp_Multiplier_b.un2_dout_r_cry_15_0 ALU COUT Out 0.035 1.609 r - un2_dout_r_cry_15 Net - - 0.000 - 1 IIR.iir_direct_form_ii.dsp_acc_coeff_b_x\[1\]\.dsp_Multiplier_b.un2_dout_r_cry_16_0 ALU CIN In - 1.609 r - IIR.iir_direct_form_ii.dsp_acc_coeff_b_x\[1\]\.dsp_Multiplier_b.un2_dout_r_cry_16_0 ALU COUT Out 0.035 1.644 r - un2_dout_r_cry_16 Net - - 0.000 - 1 IIR.iir_direct_form_ii.dsp_acc_coeff_b_x\[1\]\.dsp_Multiplier_b.un2_dout_r_cry_17_0 ALU CIN In - 1.644 r - IIR.iir_direct_form_ii.dsp_acc_coeff_b_x\[1\]\.dsp_Multiplier_b.un2_dout_r_cry_17_0 ALU COUT Out 0.035 1.679 r - un2_dout_r_cry_17 Net - - 0.000 - 1 IIR.iir_direct_form_ii.dsp_acc_coeff_b_x\[1\]\.dsp_Multiplier_b.un2_dout_r_cry_18_0 ALU CIN In - 1.679 r - IIR.iir_direct_form_ii.dsp_acc_coeff_b_x\[1\]\.dsp_Multiplier_b.un2_dout_r_cry_18_0 ALU COUT Out 0.035 1.714 r - un2_dout_r_cry_18 Net - - 0.000 - 1 IIR.iir_direct_form_ii.dsp_acc_coeff_b_x\[1\]\.dsp_Multiplier_b.un2_dout_r_cry_19_0 ALU CIN In - 1.714 r - IIR.iir_direct_form_ii.dsp_acc_coeff_b_x\[1\]\.dsp_Multiplier_b.un2_dout_r_cry_19_0 ALU COUT Out 0.035 1.749 r - un2_dout_r_cry_19 Net - - 0.000 - 1 IIR.iir_direct_form_ii.dsp_acc_coeff_b_x\[1\]\.dsp_Multiplier_b.un2_dout_r_cry_20_0 ALU CIN In - 1.749 r - IIR.iir_direct_form_ii.dsp_acc_coeff_b_x\[1\]\.dsp_Multiplier_b.un2_dout_r_cry_20_0 ALU COUT Out 0.035 1.784 r - un2_dout_r_cry_20 Net - - 0.000 - 1 IIR.iir_direct_form_ii.dsp_acc_coeff_b_x\[1\]\.dsp_Multiplier_b.un2_dout_r_cry_21_0 ALU CIN In - 1.784 r - IIR.iir_direct_form_ii.dsp_acc_coeff_b_x\[1\]\.dsp_Multiplier_b.un2_dout_r_cry_21_0 ALU COUT Out 0.035 1.819 r - un2_dout_r_cry_21 Net - - 0.000 - 1 IIR.iir_direct_form_ii.dsp_acc_coeff_b_x\[1\]\.dsp_Multiplier_b.un2_dout_r_cry_22_0 ALU CIN In - 1.819 r - IIR.iir_direct_form_ii.dsp_acc_coeff_b_x\[1\]\.dsp_Multiplier_b.un2_dout_r_cry_22_0 ALU COUT Out 0.035 1.854 r - un2_dout_r_cry_22 Net - - 0.000 - 1 IIR.iir_direct_form_ii.dsp_acc_coeff_b_x\[1\]\.dsp_Multiplier_b.un2_dout_r_cry_23_0 ALU CIN In - 1.854 r - IIR.iir_direct_form_ii.dsp_acc_coeff_b_x\[1\]\.dsp_Multiplier_b.un2_dout_r_cry_23_0 ALU COUT Out 0.035 1.889 r - un2_dout_r_cry_23 Net - - 0.000 - 1 IIR.iir_direct_form_ii.dsp_acc_coeff_b_x\[1\]\.dsp_Multiplier_b.un2_dout_r_cry_24_0 ALU CIN In - 1.889 r - IIR.iir_direct_form_ii.dsp_acc_coeff_b_x\[1\]\.dsp_Multiplier_b.un2_dout_r_cry_24_0 ALU COUT Out 0.035 1.924 r - un2_dout_r_cry_24 Net - - 0.000 - 1 IIR.iir_direct_form_ii.dsp_acc_coeff_b_x\[1\]\.dsp_Multiplier_b.un2_dout_r_cry_25_0 ALU CIN In - 1.924 r - IIR.iir_direct_form_ii.dsp_acc_coeff_b_x\[1\]\.dsp_Multiplier_b.un2_dout_r_cry_25_0 ALU COUT Out 0.035 1.959 r - un2_dout_r_cry_25 Net - - 0.000 - 1 IIR.iir_direct_form_ii.dsp_acc_coeff_b_x\[1\]\.dsp_Multiplier_b.un2_dout_r_cry_26_0 ALU CIN In - 1.959 r - IIR.iir_direct_form_ii.dsp_acc_coeff_b_x\[1\]\.dsp_Multiplier_b.un2_dout_r_cry_26_0 ALU COUT Out 0.035 1.994 r - un2_dout_r_cry_26 Net - - 0.000 - 1 IIR.iir_direct_form_ii.dsp_acc_coeff_b_x\[1\]\.dsp_Multiplier_b.un2_dout_r_cry_27_0 ALU CIN In - 1.994 r - IIR.iir_direct_form_ii.dsp_acc_coeff_b_x\[1\]\.dsp_Multiplier_b.un2_dout_r_cry_27_0 ALU COUT Out 0.035 2.029 r - un2_dout_r_cry_27 Net - - 0.000 - 1 IIR.iir_direct_form_ii.dsp_acc_coeff_b_x\[1\]\.dsp_Multiplier_b.un2_dout_r_cry_28_0 ALU CIN In - 2.029 r - IIR.iir_direct_form_ii.dsp_acc_coeff_b_x\[1\]\.dsp_Multiplier_b.un2_dout_r_cry_28_0 ALU COUT Out 0.035 2.064 r - un2_dout_r_cry_28 Net - - 0.000 - 1 IIR.iir_direct_form_ii.dsp_acc_coeff_b_x\[1\]\.dsp_Multiplier_b.un2_dout_r_cry_29_0 ALU CIN In - 2.064 r - IIR.iir_direct_form_ii.dsp_acc_coeff_b_x\[1\]\.dsp_Multiplier_b.un2_dout_r_cry_29_0 ALU COUT Out 0.035 2.099 r - un2_dout_r_cry_29 Net - - 0.000 - 1 IIR.iir_direct_form_ii.dsp_acc_coeff_b_x\[1\]\.dsp_Multiplier_b.un2_dout_r_cry_30_0 ALU CIN In - 2.099 r - IIR.iir_direct_form_ii.dsp_acc_coeff_b_x\[1\]\.dsp_Multiplier_b.un2_dout_r_cry_30_0 ALU COUT Out 0.035 2.134 r - un2_dout_r_cry_30 Net - - 0.000 - 1 IIR.iir_direct_form_ii.dsp_acc_coeff_b_x\[1\]\.dsp_Multiplier_b.un2_dout_r_cry_31_0 ALU CIN In - 2.134 r - IIR.iir_direct_form_ii.dsp_acc_coeff_b_x\[1\]\.dsp_Multiplier_b.un2_dout_r_cry_31_0 ALU COUT Out 0.035 2.169 r - un2_dout_r_cry_31 Net - - 0.000 - 1 IIR.iir_direct_form_ii.dsp_acc_coeff_b_x\[1\]\.dsp_Multiplier_b.un2_dout_r_cry_32_0 ALU CIN In - 2.169 r - IIR.iir_direct_form_ii.dsp_acc_coeff_b_x\[1\]\.dsp_Multiplier_b.un2_dout_r_cry_32_0 ALU COUT Out 0.035 2.204 r - un2_dout_r_cry_32 Net - - 0.000 - 1 IIR.iir_direct_form_ii.dsp_acc_coeff_b_x\[1\]\.dsp_Multiplier_b.un2_dout_r_cry_33_0 ALU CIN In - 2.204 r - IIR.iir_direct_form_ii.dsp_acc_coeff_b_x\[1\]\.dsp_Multiplier_b.un2_dout_r_cry_33_0 ALU COUT Out 0.035 2.239 r - un2_dout_r_cry_33 Net - - 0.000 - 1 IIR.iir_direct_form_ii.dsp_acc_coeff_b_x\[1\]\.dsp_Multiplier_b.un2_dout_r_cry_34_0 ALU CIN In - 2.239 r - IIR.iir_direct_form_ii.dsp_acc_coeff_b_x\[1\]\.dsp_Multiplier_b.un2_dout_r_cry_34_0 ALU COUT Out 0.035 2.274 r - un2_dout_r_cry_34 Net - - 0.000 - 1 IIR.iir_direct_form_ii.dsp_acc_coeff_b_x\[1\]\.dsp_Multiplier_b.un2_dout_r_s_35_0 ALU CIN In - 2.274 r - IIR.iir_direct_form_ii.dsp_acc_coeff_b_x\[1\]\.dsp_Multiplier_b.un2_dout_r_s_35_0 ALU SUM Out 0.470 2.744 f - un2_dout_r[35] Net - - 0.535 - 1 IIR.iir_direct_form_ii.dsp_acc_coeff_b_x\[1\]\.dsp_Multiplier_b.dout_r[35] DFFC D In - 3.279 f - ================================================================================================================================================================= Total path delay (propagation time + setup) of 3.340 is 2.270(68.0%) logic and 1.070(32.0%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ##### END OF TIMING REPORT #####] Timing exceptions that could not be applied Finished final timing analysis (Real Time elapsed 0h:00m:16s; CPU Time elapsed 0h:00m:14s; Memory used current: 361MB peak: 362MB) Finished timing report (Real Time elapsed 0h:00m:16s; CPU Time elapsed 0h:00m:14s; Memory used current: 361MB peak: 362MB) --------------------------------------- Resource Usage Report for IIR_Filter_Top Mapping to part: gw2a_18pbga256-8 Cell usage: ALU 224 uses DFFC 73 uses DFFCE 1038 uses DFFE 169 uses DFFP 9 uses DFFPE 7 uses DFFR 1 use DFFS 1 use GSR 1 use INV 6 uses MUX2_LUT5 143 uses MUX2_LUT6 18 uses RAM16S4 25 uses RAM16SDP4 20 uses SPX9 2 uses LUT2 199 uses LUT3 646 uses LUT4 238 uses MULT18X18 4 uses I/O Register bits: 0 Register bits not including I/Os: 1298 of 15552 (8%) RAM/ROM usage summary Block Rams : 2 of 46 (4%) Block Multipliers: 2 of 24 (8%) Total load per clock: IIR_Filter_Top|clk: 1347 @S |Mapping Summary: Total LUTs: 1083 Mapper successful! At Mapper Exit (Real Time elapsed 0h:00m:16s; CPU Time elapsed 0h:00m:14s; Memory used current: 361MB peak: 363MB) Process took 0h:00m:16s realtime, 0h:00m:14s cputime # Fri Dec 18 11:23:23 2020 ###########################################################]