@N: MF916 |Option synthesis_strategy=base is enabled. 
@N: MF248 |Running in 64-bit mode.
@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
@N: MT206 |Auto Constrain mode is enabled
@N: MF794 |RAM mem[17:0] required 20 registers during mapping 
@N: MF794 |RAM mem[17:0] required 20 registers during mapping 
@N: MF794 |RAM rmem_b_1[17:0] required 20 registers during mapping 
@N: MF794 |RAM dsp_acc_coeff_b_x\[1\]\.delay_cnt_tdm_x.dReg_CR2[2:0] required 6 registers during mapping 
@N: MF794 |RAM dsp_acc_coeff_b_x\[1\]\.delay_a0_i.dReg_CR17[17:0] required 69 registers during mapping 
@N: MF794 |RAM mc_data_shift_y\[0\]\.data_shift_y\[0\]\.shift_reg.data_shift\[5\]\.genblk1\.data_r_CR17[17:0] required 79 registers during mapping 
@N: MF794 |RAM delay_coeff_b_in.dReg_CR17[17:0] required 43 registers during mapping 
@N: MF794 |RAM mem[17:0] required 20 registers during mapping 
@N: MF794 |RAM mem[17:0] required 18 registers during mapping 
@N: MF794 |RAM rmem_b_1[17:0] required 12 registers during mapping 
@N: MF794 |RAM dsp_acc_coeff_b_x\[1\]\.delay_cnt_tdm_x.dReg_CR2[2:0] required 6 registers during mapping 
@N: MF794 |RAM dsp_acc_coeff_b_x\[1\]\.delay_a0_i.dReg_CR17[17:0] required 69 registers during mapping 
@N: MF794 |RAM mc_data_shift_y\[0\]\.data_shift_y\[0\]\.shift_reg.data_shift\[5\]\.genblk1\.data_r_CR17[17:0] required 79 registers during mapping 
@N: MF794 |RAM delay_coeff_b_in.dReg_CR17[17:0] required 43 registers during mapping 
@N: MF322 |Retiming summary: 0 registers retimed to 2 
@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.  
@N: BW103 |The default time unit for the Synopsys Constraint File (SDC or FDC) is 1ns.
@N: BW107 |Synopsys Constraint File capacitance units using default value of 1pF 
@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.
@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock.
