| Project Settings |
|---|
| Project Name | Ref_Design | Device Name | rev_1: GOWIN-GW2A : GW2A_18 |
| Implementation Name | rev_1 | Top Module | [auto] |
| Pipelining | 1 | Retiming | 0 |
| Resource Sharing | 1 | Fanout Guide | 10000 |
| Disable I/O Insertion | 0 | Disable Sequential Optimizations | 0 |
| Clock Conversion | 1 | FSM Compiler | 1 |
| Run Status |
|---|
| Job Name |
Status |
|
|
|
CPU Time |
Real Time |
Memory |
Date/Time |
| (compiler) | Complete |
12 |
105 |
0 |
- |
00m:04s |
- |
2020/11/20
15:47:51 |
| (premap) | Complete |
5 |
0 |
0 |
0m:03s |
0m:03s |
234MB |
2020/11/20
15:47:57 |
| (fpga_mapper) | Complete |
73 |
18 |
0 |
0m:10s |
0m:10s |
242MB |
2020/11/20
15:48:08 |
| Multi-srs Generator |
Complete | | | | 00m:01s | | | 2020/11/20
15:47:53 |
| Area Summary |
|---|
|
| I/O ports
(io_port) | 23 |
Non I/O Register bits
(non_io_reg) | 1331 (8%) |
| I/O Register bits
(total_io_reg) | 0 |
Ultra Rams | 0 |
| Block Rams
(v_ram) | 3 (46) |
Block Multipliers
(dsp_used) | 2 (24) |
| LUTs
(total_luts) | 1138 (5%) |
| |
| Timing Summary |
|---|
|
| Clock Name | Req Freq | Est Freq | Slack |
|---|
| exp_iir|SYM_CLK | 150.0 MHz | 126.0 MHz | -1.272 |
| Optimizations Summary |
|---|
| Combined Clock Conversion | 1 / 0 |
| |
|