@N|Running in 64-bit mode
@N|Running in 64-bit mode
@N: CG1349 :	| Running Verilog Compiler in System Verilog mode
@N: CG1350 :	| Running Verilog Compiler in Multiple File Compilation Unit mode
@N: CG364 :"C:\Gowin\Gowin_V1.9.7.01Beta\SynplifyPro\lib\generic\gw2a.v":2406:7:2406:9|Synthesizing module GSR in library work.
@N: CG364 :"E:\myWork\IP\releaseVerify\V1.9.7.01\Gowin_IIR_Filter_RefDesign\Ref_Design\src\iir_filter\iir_filter.v":27029:7:27029:20|Synthesizing module IIR_Filter_Top in library work.
@N: CG364 :"E:\myWork\IP\releaseVerify\V1.9.7.01\Gowin_IIR_Filter_RefDesign\Ref_Design\src\exp_iir.v":2:7:2:13|Synthesizing module exp_iir in library work.
@N: CG179 :"E:\myWork\IP\releaseVerify\V1.9.7.01\Gowin_IIR_Filter_RefDesign\Ref_Design\src\exp_iir.v":73:59:73:67|Removing redundant assignment.
@N: CL159 :"E:\myWork\IP\releaseVerify\V1.9.7.01\Gowin_IIR_Filter_RefDesign\Ref_Design\src\iir_filter\iir_filter.v":27062:6:27062:14|Input coeff_set is unused.
@N|Running in 64-bit mode
@N: NF107 :"e:\mywork\ip\releaseverify\v1.9.7.01\gowin_iir_filter_refdesign\ref_design\src\exp_iir.v":2:7:2:13|Selected library: work cell: exp_iir view verilog as top level
@N: NF107 :"e:\mywork\ip\releaseverify\v1.9.7.01\gowin_iir_filter_refdesign\ref_design\src\exp_iir.v":2:7:2:13|Selected library: work cell: exp_iir view verilog as top level

