Timing Messages
| Report Title | Timing Analysis Report |
| Design File | E:\Gowin_haogang\project\Gowin_USB3_0_Ref\Gowin_USB30_UVC_BULK\release\Gowin_USB3_2_GEN1_UVC_BULK_Ref_DK_USB_GW5AT_LV60UG225_V1.0\prj\impl\gwsynthesis\prj.vg |
| Physical Constraints File | E:\Gowin_haogang\project\Gowin_USB3_0_Ref\Gowin_USB30_UVC_BULK\release\Gowin_USB3_2_GEN1_UVC_BULK_Ref_DK_USB_GW5AT_LV60UG225_V1.0\prj\src\top.cst |
| Timing Constraint File | E:\Gowin_haogang\project\Gowin_USB3_0_Ref\Gowin_USB30_UVC_BULK\release\Gowin_USB3_2_GEN1_UVC_BULK_Ref_DK_USB_GW5AT_LV60UG225_V1.0\prj\src\top.sdc |
| Tool Version | V1.9.12.03 (64-bit) |
| Part Number | GW5AT-LV60UG225C2/I1 |
| Device | GW5AT-60 |
| Device Version | B |
| Created Time | Thu Jul 16 15:02:09 2026 |
| Legal Announcement | Copyright (C)2014-2026 Gowin Semiconductor Corporation. All rights reserved. |
Timing Summaries
STA Tool Run Summary:
| Setup Delay Model | Slow 0.93V 0C C2/I1 |
| Hold Delay Model | Fast 0.975V 85C C2/I1 |
| Numbers of Paths Analyzed | 37862 |
| Numbers of Endpoints Analyzed | 52804 |
| Numbers of Falling Endpoints | 12 |
| Numbers of Setup Violated Endpoints | 0 |
| Numbers of Hold Violated Endpoints | 0 |
Clock Summary:
| NO. | Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Objects |
|---|---|---|---|---|---|---|---|---|---|
| 1 | pclk | Base | 6.250 | 160.000 | 0.000 | 3.200 | pclk | ||
| 2 | q0_lane1_fabric_rx_clk | Base | 6.250 | 160.000 | 0.000 | 3.200 | SerDes_Top_inst/q0_lane1_fabric_rx_clk | ||
| 3 | drp_clk | Base | 10.000 | 100.000 | 0.000 | 5.000 | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst_drp_clk_o[1] | ||
| 4 | clk_24m | Base | 41.667 | 24.000 | 0.000 | 20.834 | clk_24m | ||
| 5 | sys_clk | Base | 5.000 | 200.000 | 0.000 | 2.500 | sys_clk | ||
| 6 | rgb_clk | Base | 6.250 | 160.000 | 0.000 | 3.125 | rgb_clk | ||
| 7 | dma_clk | Base | 7.273 | 137.495 | 0.000 | 3.636 | dma_clk | ||
| 8 | memory_clk | Base | 1.818 | 550.055 | 0.000 | 0.909 | memory_clk | ||
| 9 | sys_clk_p | Base | 5.000 | 200.000 | 0.000 | 2.500 | Inst_sys_clk_in/I | ||
| 10 | cnt4_clr | Base | 10.000 | 100.000 | 0.000 | 5.000 | cnt4_clr_s0/Q | ||
| 11 | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk | Generated | 6.723 | 148.750 | 0.000 | 3.361 | Inst_sys_clk_in/O | sys_clk | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1 |
Max Frequency Summary:
| NO. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
|---|---|---|---|---|---|
| 1 | pclk | 160.000(MHz) | 161.217(MHz) | 8 | TOP |
| 2 | q0_lane1_fabric_rx_clk | 160.000(MHz) | 167.499(MHz) | 9 | TOP |
| 3 | drp_clk | 100.000(MHz) | 210.021(MHz) | 3 | TOP |
| 4 | clk_24m | 24.000(MHz) | 206.814(MHz) | 2 | TOP |
| 5 | sys_clk | 200.000(MHz) | 572.737(MHz) | 3 | TOP |
| 6 | rgb_clk | 160.000(MHz) | 203.322(MHz) | 7 | TOP |
| 7 | dma_clk | 137.495(MHz) | 156.953(MHz) | 4 | TOP |
| 8 | cnt4_clr | 100.000(MHz) | 1945.904(MHz) | 2 | TOP |
| 9 | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk | 148.750(MHz) | 210.298(MHz) | 10 | TOP |
No timing paths to get frequency of memory_clk!
No timing paths to get frequency of sys_clk_p!
Total Negative Slack Summary:
| Clock Name | Analysis Type | Endpoints TNS | Number of Endpoints |
|---|---|---|---|
| pclk | Setup | 0.000 | 0 |
| pclk | Hold | 0.000 | 0 |
| q0_lane1_fabric_rx_clk | Setup | 0.000 | 0 |
| q0_lane1_fabric_rx_clk | Hold | 0.000 | 0 |
| drp_clk | Setup | 0.000 | 0 |
| drp_clk | Hold | 0.000 | 0 |
| clk_24m | Setup | 0.000 | 0 |
| clk_24m | Hold | 0.000 | 0 |
| sys_clk | Setup | 0.000 | 0 |
| sys_clk | Hold | 0.000 | 0 |
| rgb_clk | Setup | 0.000 | 0 |
| rgb_clk | Hold | 0.000 | 0 |
| dma_clk | Setup | 0.000 | 0 |
| dma_clk | Hold | 0.000 | 0 |
| memory_clk | Setup | 0.000 | 0 |
| memory_clk | Hold | 0.000 | 0 |
| sys_clk_p | Setup | 0.000 | 0 |
| sys_clk_p | Hold | 0.000 | 0 |
| cnt4_clr | Setup | 0.000 | 0 |
| cnt4_clr | Hold | 0.000 | 0 |
| Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk | Setup | 0.000 | 0 |
| Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk | Hold | 0.000 | 0 |
Timing Details
Path Slacks Table:
Setup Paths Table
Report Command:report_timing -setup -max_paths 100 -max_common_paths 1
| Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
|---|---|---|---|---|---|---|---|---|
| 1 | 0.047 | UserLayer_top_inst/ControlTransfer_inst/bmRequestType_latch_1_s0/Q | UserLayer_top_inst/ControlTransfer_inst/transfer_in_data_mux_0_s0/D | pclk:[R] | pclk:[R] | 6.250 | 0.000 | 6.157 |
| 2 | 0.067 | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/Q | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_12_s2/D | pclk:[R] | pclk:[R] | 6.250 | 0.007 | 6.130 |
| 3 | 0.137 | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/Q | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_19_s1/D | pclk:[R] | pclk:[R] | 6.250 | 0.007 | 5.943 |
| 4 | 0.211 | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/Q | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_12_s1/D | pclk:[R] | pclk:[R] | 6.250 | 0.000 | 5.993 |
| 5 | 0.220 | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/Q | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_19_s2/D | pclk:[R] | pclk:[R] | 6.250 | 0.007 | 5.977 |
| 6 | 0.230 | UserLayer_top_inst/ControlTransfer_inst/bmRequestType_latch_1_s0/Q | UserLayer_top_inst/ControlTransfer_inst/transfer_in_data_mux_3_s0/D | pclk:[R] | pclk:[R] | 6.250 | 0.000 | 5.974 |
| 7 | 0.274 | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/Q | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_6_s2/D | pclk:[R] | pclk:[R] | 6.250 | 0.007 | 5.924 |
| 8 | 0.280 | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_word_alignment/data_in_r0_10_s0/Q | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_word_alignment/cnt0_1_s1/D | q0_lane1_fabric_rx_clk:[R] | q0_lane1_fabric_rx_clk:[R] | 6.250 | -0.007 | 5.936 |
| 9 | 0.290 | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/Q | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_9_s2/D | pclk:[R] | pclk:[R] | 6.250 | 0.007 | 5.790 |
| 10 | 0.290 | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/Q | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_9_s1/D | pclk:[R] | pclk:[R] | 6.250 | 0.007 | 5.790 |
| 11 | 0.327 | UserLayer_top_inst/ControlTransfer_inst/bmRequestType_latch_1_s0/Q | UserLayer_top_inst/ControlTransfer_inst/transfer_in_data_mux_2_s0/D | pclk:[R] | pclk:[R] | 6.250 | 0.000 | 5.877 |
| 12 | 0.347 | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/reset_n_d_s0/Q | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_25_s2/D | pclk:[R] | pclk:[R] | 6.250 | 0.350 | 5.389 |
| 13 | 0.379 | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/Q | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_28_s1/D | pclk:[R] | pclk:[R] | 6.250 | 0.014 | 5.694 |
| 14 | 0.432 | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/Q | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_28_s2/D | pclk:[R] | pclk:[R] | 6.250 | 0.000 | 5.654 |
| 15 | 0.464 | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/Q | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_20_s1/D | pclk:[R] | pclk:[R] | 6.250 | 0.007 | 5.616 |
| 16 | 0.485 | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/Q | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_20_s2/D | pclk:[R] | pclk:[R] | 6.250 | 0.000 | 5.601 |
| 17 | 0.489 | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/reset_n_d_s0/Q | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_25_s1/D | pclk:[R] | pclk:[R] | 6.250 | 0.363 | 5.234 |
| 18 | 0.511 | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/Q | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_17_s1/D | pclk:[R] | pclk:[R] | 6.250 | 0.007 | 5.686 |
| 19 | 0.513 | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/Q | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_17_s2/D | pclk:[R] | pclk:[R] | 6.250 | 0.007 | 5.684 |
| 20 | 0.550 | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/Q | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_4_s1/D | pclk:[R] | pclk:[R] | 6.250 | 0.014 | 5.523 |
| 21 | 0.554 | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/Q | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_14_s2/D | pclk:[R] | pclk:[R] | 6.250 | 0.007 | 5.643 |
| 22 | 0.556 | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/Q | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_22_s2/D | pclk:[R] | pclk:[R] | 6.250 | 0.007 | 5.523 |
| 23 | 0.557 | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/Q | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_4_s2/D | pclk:[R] | pclk:[R] | 6.250 | 0.007 | 5.523 |
| 24 | 0.563 | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/Q | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_30_s1/D | pclk:[R] | pclk:[R] | 6.250 | 0.007 | 5.516 |
| 25 | 0.570 | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/Q | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_30_s2/D | pclk:[R] | pclk:[R] | 6.250 | 0.000 | 5.516 |
| 26 | 0.577 | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/Q | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_22_s1/D | pclk:[R] | pclk:[R] | 6.250 | 0.000 | 5.509 |
| 27 | 0.581 | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/Q | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_1_s2/D | pclk:[R] | pclk:[R] | 6.250 | 0.007 | 5.498 |
| 28 | 0.610 | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/Q | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_11_s2/D | pclk:[R] | pclk:[R] | 6.250 | 0.007 | 5.469 |
| 29 | 0.610 | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/Q | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_11_s1/D | pclk:[R] | pclk:[R] | 6.250 | 0.007 | 5.469 |
| 30 | 0.618 | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/Q | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_3_s2/D | pclk:[R] | pclk:[R] | 6.250 | 0.014 | 5.455 |
| 31 | 0.618 | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/Q | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_3_s1/D | pclk:[R] | pclk:[R] | 6.250 | 0.014 | 5.455 |
| 32 | 0.632 | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/Q | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_14_s1/D | pclk:[R] | pclk:[R] | 6.250 | 0.000 | 5.454 |
| 33 | 0.652 | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/Q | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_6_s1/D | pclk:[R] | pclk:[R] | 6.250 | 0.000 | 5.552 |
| 34 | 0.659 | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_word_alignment/data_in_r0_3_s0/Q | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_word_alignment/lock_s0/D | q0_lane1_fabric_rx_clk:[R] | q0_lane1_fabric_rx_clk:[R] | 6.250 | -0.007 | 5.552 |
| 35 | 0.679 | UserLayer_top_inst/ControlTransfer_inst/wValue_latch_9_s0/Q | UserLayer_top_inst/ControlTransfer_inst/bmHint_2_s0/CE | pclk:[R] | pclk:[R] | 6.250 | -0.007 | 5.353 |
| 36 | 0.679 | UserLayer_top_inst/ControlTransfer_inst/wValue_latch_9_s0/Q | UserLayer_top_inst/ControlTransfer_inst/bmHint_6_s0/CE | pclk:[R] | pclk:[R] | 6.250 | -0.007 | 5.353 |
| 37 | 0.693 | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/Q | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_1_s1/D | pclk:[R] | pclk:[R] | 6.250 | 0.007 | 5.387 |
| 38 | 0.752 | UserLayer_top_inst/ControlTransfer_inst/wValue_latch_9_s0/Q | UserLayer_top_inst/ControlTransfer_inst/dwMaxVideoFrameSize_10_s0/CE | pclk:[R] | pclk:[R] | 6.250 | 0.000 | 5.274 |
| 39 | 0.752 | UserLayer_top_inst/ControlTransfer_inst/wValue_latch_9_s0/Q | UserLayer_top_inst/ControlTransfer_inst/dwMaxVideoFrameSize_11_s0/CE | pclk:[R] | pclk:[R] | 6.250 | 0.000 | 5.274 |
| 40 | 0.752 | UserLayer_top_inst/ControlTransfer_inst/wValue_latch_9_s0/Q | UserLayer_top_inst/ControlTransfer_inst/dwMaxVideoFrameSize_12_s0/CE | pclk:[R] | pclk:[R] | 6.250 | 0.000 | 5.274 |
| 41 | 0.752 | UserLayer_top_inst/ControlTransfer_inst/wValue_latch_9_s0/Q | UserLayer_top_inst/ControlTransfer_inst/dwFrameInterval_25_s0/CE | pclk:[R] | pclk:[R] | 6.250 | -0.007 | 5.280 |
| 42 | 0.752 | UserLayer_top_inst/ControlTransfer_inst/wValue_latch_9_s0/Q | UserLayer_top_inst/ControlTransfer_inst/dwFrameInterval_29_s0/CE | pclk:[R] | pclk:[R] | 6.250 | -0.007 | 5.280 |
| 43 | 0.759 | UserLayer_top_inst/ControlTransfer_inst/wValue_latch_9_s0/Q | UserLayer_top_inst/ControlTransfer_inst/dwMaxVideoFrameSize_9_s0/CE | pclk:[R] | pclk:[R] | 6.250 | -0.007 | 5.274 |
| 44 | 0.759 | UserLayer_top_inst/ControlTransfer_inst/wValue_latch_9_s0/Q | UserLayer_top_inst/ControlTransfer_inst/dwMaxVideoFrameSize_13_s0/CE | pclk:[R] | pclk:[R] | 6.250 | -0.007 | 5.274 |
| 45 | 0.759 | UserLayer_top_inst/ControlTransfer_inst/wValue_latch_9_s0/Q | UserLayer_top_inst/ControlTransfer_inst/dwMaxVideoFrameSize_27_s0/CE | pclk:[R] | pclk:[R] | 6.250 | -0.007 | 5.274 |
| 46 | 0.773 | UserLayer_top_inst/ControlTransfer_inst/wValue_latch_9_s0/Q | UserLayer_top_inst/ControlTransfer_inst/wDelay_4_s0/CE | pclk:[R] | pclk:[R] | 6.250 | -0.007 | 5.260 |
| 47 | 0.792 | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_word_alignment/data_in_r0_3_s0/Q | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_word_alignment/cnt0_1_s1/CE | q0_lane1_fabric_rx_clk:[R] | q0_lane1_fabric_rx_clk:[R] | 6.250 | -0.007 | 5.241 |
| 48 | 0.792 | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_word_alignment/data_in_r0_3_s0/Q | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_word_alignment/cnt0_2_s1/CE | q0_lane1_fabric_rx_clk:[R] | q0_lane1_fabric_rx_clk:[R] | 6.250 | -0.007 | 5.241 |
| 49 | 0.796 | UserLayer_top_inst/ControlTransfer_inst/bmRequestType_latch_1_s0/Q | UserLayer_top_inst/ControlTransfer_inst/transfer_in_data_mux_59_s0/D | pclk:[R] | pclk:[R] | 6.250 | 0.007 | 5.402 |
| 50 | 0.798 | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/GEN1_DPP_buff/mem_mem_0_1_s/DO[5] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_dpp_9_s1/D | pclk:[R] | pclk:[R] | 6.250 | 0.007 | 5.399 |
| 51 | 0.798 | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/GEN1_DPP_buff/mem_mem_0_1_s/DO[5] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_dpp_9_s0/D | pclk:[R] | pclk:[R] | 6.250 | 0.007 | 5.399 |
| 52 | 0.800 | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_word_alignment/data_in_r0_3_s0/Q | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_word_alignment/cnt0_0_s1/CE | q0_lane1_fabric_rx_clk:[R] | q0_lane1_fabric_rx_clk:[R] | 6.250 | 0.000 | 5.226 |
| 53 | 0.805 | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb_pipe_interface/RxData_6_s1/Q | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_encode_8b10b_4ch/enc3/dout_3_s0/D | pclk:[R] | pclk:[R] | 6.250 | -0.007 | 5.405 |
| 54 | 0.805 | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_word_alignment/data_in_r0_3_s0/Q | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_word_alignment/cnt0_3_s1/D | q0_lane1_fabric_rx_clk:[R] | q0_lane1_fabric_rx_clk:[R] | 6.250 | 0.007 | 5.392 |
| 55 | 0.838 | UserLayer_top_inst/ControlTransfer_inst/bmRequestType_latch_1_s0/Q | UserLayer_top_inst/ControlTransfer_inst/transfer_in_data_mux_5_s0/D | pclk:[R] | pclk:[R] | 6.250 | 0.000 | 5.366 |
| 56 | 0.848 | UserLayer_top_inst/ControlTransfer_inst/wValue_latch_9_s0/Q | UserLayer_top_inst/ControlTransfer_inst/dwFrameInterval_3_s0/CE | pclk:[R] | pclk:[R] | 6.250 | 0.000 | 5.178 |
| 57 | 0.857 | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/state_2_s0/Q | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/tsc_1_s0/D | pclk:[R] | pclk:[R] | 6.250 | -0.007 | 5.354 |
| 58 | 0.857 | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_header_pkt_66_s0/Q | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_hp_4_s1/D | pclk:[R] | pclk:[R] | 6.250 | 0.000 | 5.229 |
| 59 | 0.860 | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/Q | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_27_s1/D | pclk:[R] | pclk:[R] | 6.250 | 0.007 | 5.219 |
| 60 | 0.871 | UserLayer_top_inst/ControlTransfer_inst/wValue_latch_9_s0/Q | UserLayer_top_inst/ControlTransfer_inst/bFrameIndex_2_s0/CE | pclk:[R] | pclk:[R] | 6.250 | -0.007 | 5.161 |
| 61 | 0.871 | UserLayer_top_inst/ControlTransfer_inst/wValue_latch_9_s0/Q | UserLayer_top_inst/ControlTransfer_inst/bmHint_8_s0/CE | pclk:[R] | pclk:[R] | 6.250 | -0.007 | 5.161 |
| 62 | 0.882 | UserLayer_top_inst/ControlTransfer_inst/wValue_latch_9_s0/Q | UserLayer_top_inst/ControlTransfer_inst/dwFrameInterval_22_s0/CE | pclk:[R] | pclk:[R] | 6.250 | 0.000 | 5.143 |
| 63 | 0.882 | UserLayer_top_inst/ControlTransfer_inst/wValue_latch_9_s0/Q | UserLayer_top_inst/ControlTransfer_inst/dwFrameInterval_31_s0/CE | pclk:[R] | pclk:[R] | 6.250 | 0.000 | 5.143 |
| 64 | 0.883 | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_header_pkt_66_s0/Q | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_hp_4_s0/D | pclk:[R] | pclk:[R] | 6.250 | 0.000 | 5.321 |
| 65 | 0.884 | UserLayer_top_inst/ControlTransfer_inst/wValue_latch_9_s0/Q | UserLayer_top_inst/ControlTransfer_inst/dwFrameInterval_2_s0/CE | pclk:[R] | pclk:[R] | 6.250 | 0.000 | 5.142 |
| 66 | 0.884 | UserLayer_top_inst/ControlTransfer_inst/wValue_latch_9_s0/Q | UserLayer_top_inst/ControlTransfer_inst/dwFrameInterval_4_s0/CE | pclk:[R] | pclk:[R] | 6.250 | 0.000 | 5.142 |
| 67 | 0.897 | UserLayer_top_inst/ControlTransfer_inst/wValue_latch_9_s0/Q | UserLayer_top_inst/ControlTransfer_inst/dwMaxVideoFrameSize_0_s0/CE | pclk:[R] | pclk:[R] | 6.250 | -0.007 | 5.135 |
| 68 | 0.897 | UserLayer_top_inst/ControlTransfer_inst/wValue_latch_9_s0/Q | UserLayer_top_inst/ControlTransfer_inst/dwMaxVideoFrameSize_3_s0/CE | pclk:[R] | pclk:[R] | 6.250 | -0.007 | 5.135 |
| 69 | 0.902 | DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_3_s0/Q | DDR3_Memory_Interface_Top_inst/gw3_top/u_gwmc_top/gw_wr_data0/wr_buf_din_8_s0/D | dma_clk:[R] | dma_clk:[R] | 7.273 | 0.007 | 6.319 |
| 70 | 0.914 | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/recv_u0_adv_GEN2_s0/Q | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/hp_rd_s0/CE | pclk:[R] | pclk:[R] | 6.250 | 0.014 | 5.098 |
| 71 | 0.921 | UserLayer_top_inst/ControlTransfer_inst/wValue_latch_9_s0/Q | UserLayer_top_inst/ControlTransfer_inst/wDelay_3_s0/CE | pclk:[R] | pclk:[R] | 6.250 | 0.000 | 5.105 |
| 72 | 0.921 | UserLayer_top_inst/ControlTransfer_inst/wValue_latch_9_s0/Q | UserLayer_top_inst/ControlTransfer_inst/wDelay_5_s0/CE | pclk:[R] | pclk:[R] | 6.250 | 0.000 | 5.105 |
| 73 | 0.924 | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/in_dpp_length_expect_4_s0/Q | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/in_dpp_length_9_s1/D | pclk:[R] | pclk:[R] | 6.250 | -0.007 | 5.287 |
| 74 | 0.931 | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_word_alignment/data_in_r0_3_s0/Q | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_word_alignment/cnt0_3_s1/CE | q0_lane1_fabric_rx_clk:[R] | q0_lane1_fabric_rx_clk:[R] | 6.250 | 0.007 | 5.088 |
| 75 | 0.934 | UserLayer_top_inst/ControlTransfer_inst/bmRequestType_latch_1_s0/Q | UserLayer_top_inst/ControlTransfer_inst/transfer_in_data_mux_7_s0/D | pclk:[R] | pclk:[R] | 6.250 | 0.000 | 5.270 |
| 76 | 0.934 | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_header_pkt_69_s0/Q | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_hp_7_s1/D | pclk:[R] | pclk:[R] | 6.250 | 0.007 | 5.263 |
| 77 | 0.941 | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/ack_tx_hdr_seq_num_3_s0/Q | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/resend_hp_act_s1/CE | pclk:[R] | pclk:[R] | 6.250 | 0.000 | 5.085 |
| 78 | 0.950 | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/Q | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/tx_hp_word_1_2_s0/CE | pclk:[R] | pclk:[R] | 6.250 | -0.343 | 5.419 |
| 79 | 0.953 | DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_3_s0/Q | DDR3_Memory_Interface_Top_inst/gw3_top/u_gwmc_top/gw_wr_data0/wr_buf_din_103_s0/D | dma_clk:[R] | dma_clk:[R] | 7.273 | 0.000 | 6.274 |
| 80 | 0.969 | UserLayer_top_inst/ControlTransfer_inst/wValue_latch_9_s0/Q | UserLayer_top_inst/ControlTransfer_inst/wCompQuality_12_s0/CE | pclk:[R] | pclk:[R] | 6.250 | 0.007 | 5.050 |
| 81 | 0.976 | UserLayer_top_inst/ControlTransfer_inst/wValue_latch_9_s0/Q | UserLayer_top_inst/ControlTransfer_inst/dwMaxVideoFrameSize_19_s0/CE | pclk:[R] | pclk:[R] | 6.250 | 0.007 | 5.044 |
| 82 | 0.976 | UserLayer_top_inst/ControlTransfer_inst/wValue_latch_9_s0/Q | UserLayer_top_inst/ControlTransfer_inst/dwMaxVideoFrameSize_21_s0/CE | pclk:[R] | pclk:[R] | 6.250 | 0.007 | 5.044 |
| 83 | 0.981 | UserLayer_top_inst/ControlTransfer_inst/wValue_latch_9_s0/Q | UserLayer_top_inst/ControlTransfer_inst/dwMaxVideoFrameSize_23_s0/CE | pclk:[R] | pclk:[R] | 6.250 | 0.000 | 5.045 |
| 84 | 0.981 | UserLayer_top_inst/ControlTransfer_inst/wValue_latch_9_s0/Q | UserLayer_top_inst/ControlTransfer_inst/wDelay_6_s0/CE | pclk:[R] | pclk:[R] | 6.250 | 0.000 | 5.045 |
| 85 | 0.981 | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_5g/state_3_s0/Q | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_5g/train_count_17_s2/CE | pclk:[R] | pclk:[R] | 6.250 | 0.000 | 5.044 |
| 86 | 0.981 | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_5g/state_3_s0/Q | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_5g/train_count_18_s2/CE | pclk:[R] | pclk:[R] | 6.250 | 0.000 | 5.044 |
| 87 | 0.984 | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_word_alignment/data_in_r0_3_s0/Q | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_word_alignment/cnt0_0_s1/D | q0_lane1_fabric_rx_clk:[R] | q0_lane1_fabric_rx_clk:[R] | 6.250 | 0.000 | 5.220 |
| 88 | 0.994 | UserLayer_top_inst/ControlTransfer_inst/wValue_latch_9_s0/Q | UserLayer_top_inst/ControlTransfer_inst/bFormatIndex_0_s0/CE | pclk:[R] | pclk:[R] | 6.250 | 0.007 | 5.025 |
| 89 | 0.994 | UserLayer_top_inst/ControlTransfer_inst/wValue_latch_9_s0/Q | UserLayer_top_inst/ControlTransfer_inst/dwFrameInterval_8_s0/CE | pclk:[R] | pclk:[R] | 6.250 | 0.007 | 5.025 |
| 90 | 0.994 | UserLayer_top_inst/ControlTransfer_inst/wValue_latch_9_s0/Q | UserLayer_top_inst/ControlTransfer_inst/dwFrameInterval_10_s0/CE | pclk:[R] | pclk:[R] | 6.250 | 0.007 | 5.025 |
| 91 | 0.994 | UserLayer_top_inst/ControlTransfer_inst/wValue_latch_9_s0/Q | UserLayer_top_inst/ControlTransfer_inst/dwFrameInterval_14_s0/CE | pclk:[R] | pclk:[R] | 6.250 | 0.007 | 5.025 |
| 92 | 0.997 | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/dpp_crc_append/dpp_data_in_0_d0_30_s0/Q | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/dpp_crc_append/crc64_in[1]_9_s0/D | pclk:[R] | pclk:[R] | 6.250 | 0.000 | 5.089 |
| 93 | 1.003 | UserLayer_top_inst/ControlTransfer_inst/wValue_latch_9_s0/Q | UserLayer_top_inst/ControlTransfer_inst/bFormatIndex_3_s0/CE | pclk:[R] | pclk:[R] | 6.250 | 0.000 | 5.023 |
| 94 | 1.003 | UserLayer_top_inst/ControlTransfer_inst/wValue_latch_9_s0/Q | UserLayer_top_inst/ControlTransfer_inst/bFormatIndex_4_s0/CE | pclk:[R] | pclk:[R] | 6.250 | 0.000 | 5.023 |
| 95 | 1.003 | UserLayer_top_inst/ControlTransfer_inst/wValue_latch_9_s0/Q | UserLayer_top_inst/ControlTransfer_inst/bmHint_0_s0/CE | pclk:[R] | pclk:[R] | 6.250 | 0.000 | 5.023 |
| 96 | 1.005 | UserLayer_top_inst/ControlTransfer_inst/wValue_latch_9_s0/Q | UserLayer_top_inst/ControlTransfer_inst/dwFrameInterval_13_s0/CE | pclk:[R] | pclk:[R] | 6.250 | 0.000 | 5.021 |
| 97 | 1.005 | UserLayer_top_inst/ControlTransfer_inst/wValue_latch_9_s0/Q | UserLayer_top_inst/ControlTransfer_inst/dwFrameInterval_15_s0/CE | pclk:[R] | pclk:[R] | 6.250 | 0.000 | 5.021 |
| 98 | 1.005 | UserLayer_top_inst/ControlTransfer_inst/wValue_latch_9_s0/Q | UserLayer_top_inst/ControlTransfer_inst/bFormatIndex_5_s0/CE | pclk:[R] | pclk:[R] | 6.250 | 0.000 | 5.021 |
| 99 | 1.006 | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/ltssm_go_u_d0_2_s0/Q | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/state_2_s0/D | pclk:[R] | pclk:[R] | 6.250 | 0.007 | 5.073 |
| 100 | 1.007 | UserLayer_top_inst/ControlTransfer_inst/wValue_latch_9_s0/Q | UserLayer_top_inst/ControlTransfer_inst/dwFrameInterval_7_s0/CE | pclk:[R] | pclk:[R] | 6.250 | 0.000 | 5.019 |
Hold Paths Table
Report Command:report_timing -hold -max_paths 25 -max_common_paths 1
| Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
|---|---|---|---|---|---|---|---|---|
| 1 | 0.043 | u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_data_51_s0/Q | u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.mem_Big.mem_0_6_s/DI[3] | rgb_clk:[R] | rgb_clk:[R] | 0.000 | -0.177 | 0.254 |
| 2 | 0.043 | u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_data_48_s0/Q | u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.mem_Big.mem_0_6_s/DI[0] | rgb_clk:[R] | rgb_clk:[R] | 0.000 | -0.177 | 0.254 |
| 3 | 0.043 | u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_data_22_s0/Q | u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.mem_Big.mem_0_2_s/DI[6] | rgb_clk:[R] | rgb_clk:[R] | 0.000 | -0.177 | 0.254 |
| 4 | 0.043 | u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_data_21_s0/Q | u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.mem_Big.mem_0_2_s/DI[5] | rgb_clk:[R] | rgb_clk:[R] | 0.000 | -0.177 | 0.254 |
| 5 | 0.043 | u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_data_19_s0/Q | u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.mem_Big.mem_0_2_s/DI[3] | rgb_clk:[R] | rgb_clk:[R] | 0.000 | -0.177 | 0.254 |
| 6 | 0.043 | u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_data_47_s0/Q | u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.mem_Big.mem_0_5_s/DI[7] | rgb_clk:[R] | rgb_clk:[R] | 0.000 | -0.177 | 0.254 |
| 7 | 0.057 | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/gen_in_ep_ping_pong[2].transfer_in_mem_ping_pong_inst/GEN_TRANSFER_IN_MEM[1].transfer_in_mem_inst/transfer_in_pkt_rd_addr_6_s1/Q | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/gen_in_ep_ping_pong[2].transfer_in_mem_ping_pong_inst/GEN_TRANSFER_IN_MEM[1].transfer_in_mem_inst/mem0_mem0_0_2_s/ADB[10] | pclk:[R] | pclk:[R] | 0.000 | -0.177 | 0.265 |
| 8 | 0.059 | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/gen_in_ep_ping_pong[2].transfer_in_mem_ping_pong_inst/GEN_TRANSFER_IN_MEM[1].transfer_in_mem_inst/transfer_in_pkt_rd_addr_1_s1/Q | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/gen_in_ep_ping_pong[2].transfer_in_mem_ping_pong_inst/GEN_TRANSFER_IN_MEM[1].transfer_in_mem_inst/mem0_mem0_0_2_s/ADB[5] | pclk:[R] | pclk:[R] | 0.000 | -0.174 | 0.264 |
| 9 | 0.061 | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/gen_in_ep_ping_pong[2].transfer_in_mem_ping_pong_inst/GEN_TRANSFER_IN_MEM[1].transfer_in_mem_inst/transfer_in_pkt_rd_addr_2_s1/Q | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/gen_in_ep_ping_pong[2].transfer_in_mem_ping_pong_inst/GEN_TRANSFER_IN_MEM[1].transfer_in_mem_inst/mem0_mem0_0_2_s/ADB[6] | pclk:[R] | pclk:[R] | 0.000 | -0.174 | 0.266 |
| 10 | 0.062 | u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wbin_0_s0/Q | u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.mem_Big.mem_0_6_s/ADA[3] | rgb_clk:[R] | rgb_clk:[R] | 0.000 | -0.174 | 0.269 |
| 11 | 0.069 | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/gen_in_ep_ping_pong[2].transfer_in_mem_ping_pong_inst/GEN_TRANSFER_IN_MEM[1].transfer_in_mem_inst/transfer_in_pkt_rd_addr_6_s1/Q | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/gen_in_ep_ping_pong[2].transfer_in_mem_ping_pong_inst/GEN_TRANSFER_IN_MEM[1].transfer_in_mem_inst/mem0_mem0_0_0_s/ADB[10] | pclk:[R] | pclk:[R] | 0.000 | -0.174 | 0.274 |
| 12 | 0.086 | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/rx_dph_len_d[5]_8_s0/Q | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/rx_dph_len_d[6]_0_s9/DI[0] | pclk:[R] | pclk:[R] | 0.000 | 0.004 | 0.127 |
| 13 | 0.111 | u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_data_53_s0/Q | u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.mem_Big.mem_0_6_s/DI[5] | rgb_clk:[R] | rgb_clk:[R] | 0.000 | -0.177 | 0.321 |
| 14 | 0.111 | u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_data_52_s0/Q | u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.mem_Big.mem_0_6_s/DI[4] | rgb_clk:[R] | rgb_clk:[R] | 0.000 | -0.177 | 0.321 |
| 15 | 0.111 | u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_data_20_s0/Q | u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.mem_Big.mem_0_2_s/DI[4] | rgb_clk:[R] | rgb_clk:[R] | 0.000 | -0.177 | 0.321 |
| 16 | 0.111 | u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_data_18_s0/Q | u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.mem_Big.mem_0_2_s/DI[2] | rgb_clk:[R] | rgb_clk:[R] | 0.000 | -0.177 | 0.321 |
| 17 | 0.111 | u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_data_44_s0/Q | u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.mem_Big.mem_0_5_s/DI[4] | rgb_clk:[R] | rgb_clk:[R] | 0.000 | -0.177 | 0.321 |
| 18 | 0.120 | DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/VALUE_rrr_11_s0/Q | DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/dq_iobuf_gen[11].dq_iodelay/VALUE | dma_clk:[R] | dma_clk:[R] | 0.000 | -0.007 | 0.127 |
| 19 | 0.120 | DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/VALUE_rrr_10_s0/Q | DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/dq_iobuf_gen[10].dq_iodelay/VALUE | dma_clk:[R] | dma_clk:[R] | 0.000 | -0.007 | 0.127 |
| 20 | 0.120 | DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/VALUE_rrr_7_s0/Q | DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/dq_iobuf_gen[7].dq_iodelay/VALUE | dma_clk:[R] | dma_clk:[R] | 0.000 | -0.007 | 0.127 |
| 21 | 0.120 | DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/VALUE_rrr_0_s0/Q | DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/dq_iobuf_gen[0].dq_iodelay/VALUE | dma_clk:[R] | dma_clk:[R] | 0.000 | -0.007 | 0.127 |
| 22 | 0.122 | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/gen_in_ep_ping_pong[2].transfer_in_mem_ping_pong_inst/GEN_TRANSFER_IN_MEM[2].transfer_in_mem_inst/transfer_in_pkt_rd_addr_6_s1/Q | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/gen_in_ep_ping_pong[2].transfer_in_mem_ping_pong_inst/GEN_TRANSFER_IN_MEM[2].transfer_in_mem_inst/mem0_mem0_0_2_s/ADB[10] | pclk:[R] | pclk:[R] | 0.000 | -0.181 | 0.334 |
| 23 | 0.123 | DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/VALUE_rrr_15_s0/Q | DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/dq_iobuf_gen[15].dq_iodelay/VALUE | dma_clk:[R] | dma_clk:[R] | 0.000 | -0.004 | 0.127 |
| 24 | 0.123 | DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/VALUE_rrr_14_s0/Q | DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/dq_iobuf_gen[14].dq_iodelay/VALUE | dma_clk:[R] | dma_clk:[R] | 0.000 | -0.004 | 0.127 |
| 25 | 0.123 | DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/VALUE_rrr_1_s0/Q | DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/dq_iobuf_gen[1].dq_iodelay/VALUE | dma_clk:[R] | dma_clk:[R] | 0.000 | -0.004 | 0.127 |
Recovery Paths Table
Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1
| Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
|---|---|---|---|---|---|---|---|---|
| 1 | 0.310 | line_fifo_inst/fifo_inst/reset_w_1_s0/Q | line_fifo_inst/fifo_inst/Equal.wq2_rptr_3_s0/CLEAR | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk:[F] | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk:[R] | 3.361 | 0.004 | 2.797 |
| 2 | 0.310 | line_fifo_inst/fifo_inst/reset_w_1_s0/Q | line_fifo_inst/fifo_inst/Equal.wq2_rptr_4_s0/CLEAR | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk:[F] | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk:[R] | 3.361 | 0.004 | 2.797 |
| 3 | 0.310 | line_fifo_inst/fifo_inst/reset_w_1_s0/Q | line_fifo_inst/fifo_inst/Equal.wq2_rptr_8_s0/CLEAR | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk:[F] | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk:[R] | 3.361 | 0.004 | 2.797 |
| 4 | 0.310 | line_fifo_inst/fifo_inst/reset_w_1_s0/Q | line_fifo_inst/fifo_inst/Equal.wq2_rptr_11_s0/CLEAR | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk:[F] | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk:[R] | 3.361 | 0.004 | 2.797 |
| 5 | 0.310 | line_fifo_inst/fifo_inst/reset_w_1_s0/Q | line_fifo_inst/fifo_inst/Equal.wq1_rptr_3_s0/CLEAR | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk:[F] | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk:[R] | 3.361 | 0.004 | 2.797 |
| 6 | 0.310 | line_fifo_inst/fifo_inst/reset_w_1_s0/Q | line_fifo_inst/fifo_inst/Equal.wq1_rptr_4_s0/CLEAR | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk:[F] | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk:[R] | 3.361 | 0.004 | 2.797 |
| 7 | 0.310 | line_fifo_inst/fifo_inst/reset_w_1_s0/Q | line_fifo_inst/fifo_inst/Equal.wq1_rptr_8_s0/CLEAR | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk:[F] | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk:[R] | 3.361 | 0.004 | 2.797 |
| 8 | 0.310 | line_fifo_inst/fifo_inst/reset_w_1_s0/Q | line_fifo_inst/fifo_inst/Equal.wq1_rptr_11_s0/CLEAR | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk:[F] | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk:[R] | 3.361 | 0.004 | 2.797 |
| 9 | 0.318 | line_fifo_inst/fifo_inst/reset_r_1_s0/Q | line_fifo_inst/fifo_inst/Rnum_6_s0/CLEAR | pclk:[F] | pclk:[R] | 3.050 | -0.357 | 2.839 |
| 10 | 0.318 | line_fifo_inst/fifo_inst/reset_r_1_s0/Q | line_fifo_inst/fifo_inst/Rnum_7_s0/CLEAR | pclk:[F] | pclk:[R] | 3.050 | -0.357 | 2.839 |
| 11 | 0.318 | line_fifo_inst/fifo_inst/reset_r_1_s0/Q | line_fifo_inst/fifo_inst/Rnum_8_s0/CLEAR | pclk:[F] | pclk:[R] | 3.050 | -0.357 | 2.839 |
| 12 | 0.318 | line_fifo_inst/fifo_inst/reset_r_1_s0/Q | line_fifo_inst/fifo_inst/Rnum_9_s0/CLEAR | pclk:[F] | pclk:[R] | 3.050 | -0.357 | 2.839 |
| 13 | 0.318 | line_fifo_inst/fifo_inst/reset_r_1_s0/Q | line_fifo_inst/fifo_inst/Rnum_10_s0/CLEAR | pclk:[F] | pclk:[R] | 3.050 | -0.357 | 2.839 |
| 14 | 0.318 | line_fifo_inst/fifo_inst/reset_r_1_s0/Q | line_fifo_inst/fifo_inst/Rnum_11_s0/CLEAR | pclk:[F] | pclk:[R] | 3.050 | -0.357 | 2.839 |
| 15 | 0.324 | line_fifo_inst/fifo_inst/reset_r_1_s0/Q | line_fifo_inst/fifo_inst/Rnum_0_s0/CLEAR | pclk:[F] | pclk:[R] | 3.050 | -0.364 | 2.839 |
| 16 | 0.324 | line_fifo_inst/fifo_inst/reset_r_1_s0/Q | line_fifo_inst/fifo_inst/Rnum_1_s0/CLEAR | pclk:[F] | pclk:[R] | 3.050 | -0.364 | 2.839 |
| 17 | 0.324 | line_fifo_inst/fifo_inst/reset_r_1_s0/Q | line_fifo_inst/fifo_inst/Rnum_2_s0/CLEAR | pclk:[F] | pclk:[R] | 3.050 | -0.364 | 2.839 |
| 18 | 0.324 | line_fifo_inst/fifo_inst/reset_r_1_s0/Q | line_fifo_inst/fifo_inst/Rnum_3_s0/CLEAR | pclk:[F] | pclk:[R] | 3.050 | -0.364 | 2.839 |
| 19 | 0.324 | line_fifo_inst/fifo_inst/reset_r_1_s0/Q | line_fifo_inst/fifo_inst/Rnum_4_s0/CLEAR | pclk:[F] | pclk:[R] | 3.050 | -0.364 | 2.839 |
| 20 | 0.324 | line_fifo_inst/fifo_inst/reset_r_1_s0/Q | line_fifo_inst/fifo_inst/Rnum_5_s0/CLEAR | pclk:[F] | pclk:[R] | 3.050 | -0.364 | 2.839 |
| 21 | 0.328 | line_fifo_inst/fifo_inst/reset_w_1_s0/Q | line_fifo_inst/fifo_inst/Equal.wq2_rptr_0_s0/CLEAR | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk:[F] | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk:[R] | 3.361 | -0.003 | 2.786 |
| 22 | 0.328 | line_fifo_inst/fifo_inst/reset_w_1_s0/Q | line_fifo_inst/fifo_inst/Equal.wq2_rptr_2_s0/CLEAR | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk:[F] | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk:[R] | 3.361 | -0.003 | 2.786 |
| 23 | 0.328 | line_fifo_inst/fifo_inst/reset_w_1_s0/Q | line_fifo_inst/fifo_inst/Equal.wq2_rptr_6_s0/CLEAR | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk:[F] | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk:[R] | 3.361 | -0.003 | 2.786 |
| 24 | 0.328 | line_fifo_inst/fifo_inst/reset_w_1_s0/Q | line_fifo_inst/fifo_inst/Equal.wq2_rptr_9_s0/CLEAR | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk:[F] | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk:[R] | 3.361 | -0.003 | 2.786 |
| 25 | 0.328 | line_fifo_inst/fifo_inst/reset_w_1_s0/Q | line_fifo_inst/fifo_inst/Equal.wq1_rptr_6_s0/CLEAR | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk:[F] | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk:[R] | 3.361 | -0.003 | 2.786 |
Removal Paths Table
Report Command:report_timing -removal -max_paths 25 -max_common_paths 1
| Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
|---|---|---|---|---|---|---|---|---|
| 1 | 0.261 | frame_read_inst/rst_n_d_1_s0/Q | frame_read_inst/v_cnt_9_s1/CLEAR | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk:[R] | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk:[R] | 0.000 | 0.000 | 0.213 |
| 2 | 0.261 | frame_read_inst/rst_n_d_1_s0/Q | frame_read_inst/v_cnt_10_s0/CLEAR | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk:[R] | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk:[R] | 0.000 | 0.000 | 0.213 |
| 3 | 0.280 | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/reset_n_d_s0/Q | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_dpp_8_s1/CLEAR | pclk:[R] | pclk:[R] | 0.000 | 0.000 | 0.232 |
| 4 | 0.347 | frame_read_inst/rst_n_d_1_s0/Q | frame_read_inst/v_cnt_4_s1/CLEAR | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk:[R] | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk:[R] | 0.000 | 0.000 | 0.300 |
| 5 | 0.347 | frame_read_inst/rst_n_d_1_s0/Q | frame_read_inst/v_cnt_6_s1/CLEAR | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk:[R] | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk:[R] | 0.000 | 0.000 | 0.300 |
| 6 | 0.347 | frame_read_inst/rst_n_d_1_s0/Q | frame_read_inst/v_cnt_8_s0/CLEAR | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk:[R] | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk:[R] | 0.000 | 0.000 | 0.300 |
| 7 | 0.347 | frame_read_inst/rst_n_d_1_s0/Q | frame_read_inst/v_cnt_11_s0/CLEAR | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk:[R] | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk:[R] | 0.000 | 0.000 | 0.300 |
| 8 | 0.351 | frame_read_inst/rst_n_d_1_s0/Q | frame_read_inst/v_cnt_0_s1/CLEAR | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk:[R] | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk:[R] | 0.000 | 0.004 | 0.300 |
| 9 | 0.351 | frame_read_inst/rst_n_d_1_s0/Q | frame_read_inst/v_cnt_1_s1/CLEAR | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk:[R] | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk:[R] | 0.000 | 0.004 | 0.300 |
| 10 | 0.351 | frame_read_inst/rst_n_d_1_s0/Q | frame_read_inst/vfb_out_vs_s0/CLEAR | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk:[R] | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk:[R] | 0.000 | 0.004 | 0.300 |
| 11 | 0.360 | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/rstn_s0/Q | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_strb_o_3_s1/CLEAR | drp_clk:[R] | drp_clk:[R] | 0.000 | 0.000 | 0.312 |
| 12 | 0.360 | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/rstn_s0/Q | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wrdata_o_28_s1/CLEAR | drp_clk:[R] | drp_clk:[R] | 0.000 | 0.000 | 0.312 |
| 13 | 0.360 | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/rstn_s0/Q | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/drp_strb_serdes_3_s0/CLEAR | drp_clk:[R] | drp_clk:[R] | 0.000 | 0.000 | 0.312 |
| 14 | 0.360 | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/rstn_s0/Q | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/drp_wrdata_serdes_28_s0/CLEAR | drp_clk:[R] | drp_clk:[R] | 0.000 | 0.000 | 0.312 |
| 15 | 0.360 | frame_read_inst/rst_n_d_1_s0/Q | frame_read_inst/h_cnt_2_s1/CLEAR | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk:[R] | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk:[R] | 0.000 | -0.004 | 0.316 |
| 16 | 0.360 | frame_read_inst/rst_n_d_1_s0/Q | frame_read_inst/h_cnt_3_s1/CLEAR | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk:[R] | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk:[R] | 0.000 | -0.004 | 0.316 |
| 17 | 0.360 | frame_read_inst/rst_n_d_1_s0/Q | frame_read_inst/h_cnt_4_s1/CLEAR | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk:[R] | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk:[R] | 0.000 | -0.004 | 0.316 |
| 18 | 0.360 | frame_read_inst/rst_n_d_1_s0/Q | frame_read_inst/h_cnt_5_s1/CLEAR | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk:[R] | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk:[R] | 0.000 | -0.004 | 0.316 |
| 19 | 0.363 | testpattern_yuv_inst/rst_n_local_s0/Q | testpattern_yuv_inst/yuv_data_45_s0/CLEAR | rgb_clk:[R] | rgb_clk:[R] | 0.000 | -0.004 | 0.319 |
| 20 | 0.363 | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/upar_rstn_r1_s0/Q | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_upar_csr/csr_addr_12_s0/CLEAR | drp_clk:[R] | drp_clk:[R] | 0.000 | -0.170 | 0.485 |
| 21 | 0.365 | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/upar_rstn_r1_s0/Q | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_upar_csr/tx_detect_rx_en_d2_s0/CLEAR | drp_clk:[R] | drp_clk:[R] | 0.000 | -0.003 | 0.320 |
| 22 | 0.365 | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/upar_rstn_r1_s0/Q | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_upar_csr/tx_detect_rx_en_d1_s0/CLEAR | drp_clk:[R] | drp_clk:[R] | 0.000 | -0.003 | 0.320 |
| 23 | 0.365 | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/upar_rstn_r1_s0/Q | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_upar_csr/eidle_en_d2_s0/PRESET | drp_clk:[R] | drp_clk:[R] | 0.000 | -0.003 | 0.320 |
| 24 | 0.366 | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/reset_n_d_s0/Q | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_dpp_13_s1/CLEAR | pclk:[R] | pclk:[R] | 0.000 | 0.000 | 0.319 |
| 25 | 0.366 | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/rstn_s0/Q | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wrdata_o_6_s1/CLEAR | drp_clk:[R] | drp_clk:[R] | 0.000 | 0.004 | 0.315 |
Minimum Pulse Width Table:
| Number | Slack | Actual Width | Required Width | Type | Clock | Objects |
|---|---|---|---|---|---|---|
| 1 | 0.817 | 1.593 | 0.776 | Low Pulse Width | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk | u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.mem_Small.mem_0_4_s |
| 2 | 0.817 | 1.593 | 0.776 | Low Pulse Width | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk | line_fifo_inst/fifo_inst/Equal.mem_Equal.mem_0_4_s |
| 3 | 0.819 | 1.595 | 0.776 | High Pulse Width | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk | u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.mem_Small.mem_0_4_s |
| 4 | 0.819 | 1.595 | 0.776 | High Pulse Width | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk | line_fifo_inst/fifo_inst/Equal.mem_Equal.mem_0_4_s |
| 5 | 0.821 | 1.596 | 0.776 | Low Pulse Width | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk | u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.mem_Small.mem_0_0_s |
| 6 | 0.821 | 1.596 | 0.776 | Low Pulse Width | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk | u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.mem_Small.mem_0_6_s |
| 7 | 0.821 | 1.596 | 0.776 | Low Pulse Width | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk | line_fifo_inst/fifo_inst/Equal.mem_Equal.mem_0_1_s |
| 8 | 0.822 | 1.598 | 0.776 | High Pulse Width | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk | u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.mem_Small.mem_0_0_s |
| 9 | 0.822 | 1.598 | 0.776 | High Pulse Width | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk | u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.mem_Small.mem_0_6_s |
| 10 | 0.822 | 1.598 | 0.776 | High Pulse Width | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk | line_fifo_inst/fifo_inst/Equal.mem_Equal.mem_0_1_s |
Timing Report By Analysis Type:
Setup Analysis Report
Report Command:report_timing -setup -max_paths 100 -max_common_paths 1
Path1
Path Summary:
| Slack | 0.047 |
| Data Arrival Time | 7.670 |
| Data Required Time | 7.717 |
| From | UserLayer_top_inst/ControlTransfer_inst/bmRequestType_latch_1_s0 |
| To | UserLayer_top_inst/ControlTransfer_inst/transfer_in_data_mux_0_s0 |
| Launch Clk | pclk:[R] |
| Latch Clk | pclk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | pclk | ||||
| 0.000 | 0.000 | tCL | RR | 10163 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK |
| 1.513 | 1.513 | tNET | RR | 1 | R55C39[1][B] | UserLayer_top_inst/ControlTransfer_inst/bmRequestType_latch_1_s0/CLK |
| 1.789 | 0.275 | tC2Q | RR | 1 | R55C39[1][B] | UserLayer_top_inst/ControlTransfer_inst/bmRequestType_latch_1_s0/Q |
| 2.123 | 0.334 | tNET | RR | 1 | R57C41[3][A] | UserLayer_top_inst/ControlTransfer_inst/n4443_s20/I0 |
| 2.481 | 0.358 | tINS | RR | 2 | R57C41[3][A] | UserLayer_top_inst/ControlTransfer_inst/n4443_s20/F |
| 3.030 | 0.549 | tNET | RR | 1 | R72C42[3][A] | UserLayer_top_inst/ControlTransfer_inst/n4443_s18/I3 |
| 3.405 | 0.375 | tINS | RR | 5 | R72C42[3][A] | UserLayer_top_inst/ControlTransfer_inst/n4443_s18/F |
| 4.152 | 0.747 | tNET | RR | 1 | R66C47[3][B] | UserLayer_top_inst/ControlTransfer_inst/n4443_s17/I1 |
| 4.510 | 0.358 | tINS | RR | 48 | R66C47[3][B] | UserLayer_top_inst/ControlTransfer_inst/n4443_s17/F |
| 5.010 | 0.499 | tNET | RR | 1 | R68C42[0][B] | UserLayer_top_inst/ControlTransfer_inst/n4507_s21/I2 |
| 5.389 | 0.379 | tINS | RR | 15 | R68C42[0][B] | UserLayer_top_inst/ControlTransfer_inst/n4507_s21/F |
| 5.851 | 0.463 | tNET | RR | 1 | R64C45[3][A] | UserLayer_top_inst/ControlTransfer_inst/n4537_s13/I3 |
| 6.227 | 0.375 | tINS | RR | 1 | R64C45[3][A] | UserLayer_top_inst/ControlTransfer_inst/n4537_s13/F |
| 6.535 | 0.309 | tNET | RR | 1 | R66C44[3][B] | UserLayer_top_inst/ControlTransfer_inst/n4537_s12/I0 |
| 6.894 | 0.358 | tINS | RR | 1 | R66C44[3][B] | UserLayer_top_inst/ControlTransfer_inst/n4537_s12/F |
| 7.299 | 0.405 | tNET | RR | 1 | R68C47[2][A] | UserLayer_top_inst/ControlTransfer_inst/n4537_s10/I3 |
| 7.670 | 0.372 | tINS | RR | 1 | R68C47[2][A] | UserLayer_top_inst/ControlTransfer_inst/n4537_s10/F |
| 7.670 | 0.000 | tNET | RR | 1 | R68C47[2][A] | UserLayer_top_inst/ControlTransfer_inst/transfer_in_data_mux_0_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.250 | 6.250 | active clock edge time | ||||
| 6.250 | 0.000 | pclk | ||||
| 6.250 | 0.000 | tCL | RR | 10163 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK |
| 7.763 | 1.513 | tNET | RR | 1 | R68C47[2][A] | UserLayer_top_inst/ControlTransfer_inst/transfer_in_data_mux_0_s0/CLK |
| 7.717 | -0.046 | tSu | 1 | R68C47[2][A] | UserLayer_top_inst/ControlTransfer_inst/transfer_in_data_mux_0_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 6.250 |
| Logic Level | 8 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.513, 100.000% |
| Arrival Data Path Delay | cell: 2.576, 41.836%; route: 3.306, 53.691%; tC2Q: 0.275, 4.473% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.513, 100.000% |
Path2
Path Summary:
| Slack | 0.067 |
| Data Arrival Time | 7.650 |
| Data Required Time | 7.717 |
| From | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0 |
| To | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_12_s2 |
| Launch Clk | pclk:[R] |
| Latch Clk | pclk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | pclk | ||||
| 0.000 | 0.000 | tCL | RR | 10163 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK |
| 1.520 | 1.520 | tNET | RR | 1 | R44C83[1][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/CLK |
| 1.795 | 0.275 | tC2Q | RR | 2598 | R44C83[1][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/Q |
| 3.682 | 1.886 | tNET | RR | 1 | R45C82[3][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_lcmd_20_s8/I2 |
| 4.040 | 0.358 | tINS | RR | 1 | R45C82[3][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_lcmd_20_s8/F |
| 4.155 | 0.115 | tNET | RR | 1 | R45C82[2][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3099_s19/I2 |
| 4.487 | 0.332 | tINS | RR | 2 | R45C82[2][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3099_s19/F |
| 5.522 | 1.035 | tNET | RR | 1 | R18C78[3][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5590_s4/I2 |
| 5.881 | 0.358 | tINS | RR | 1 | R18C78[3][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5590_s4/F |
| 5.882 | 0.002 | tNET | RR | 1 | R18C78[3][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5590_s1/I1 |
| 6.241 | 0.358 | tINS | RR | 1 | R18C78[3][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5590_s1/F |
| 6.851 | 0.610 | tNET | RR | 1 | R30C79[3][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5590_s0/I0 |
| 7.209 | 0.358 | tINS | RR | 2 | R30C79[3][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5590_s0/F |
| 7.650 | 0.441 | tNET | RR | 1 | R31C78[1][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_12_s2/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.250 | 6.250 | active clock edge time | ||||
| 6.250 | 0.000 | pclk | ||||
| 6.250 | 0.000 | tCL | RR | 10163 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK |
| 7.763 | 1.513 | tNET | RR | 1 | R31C78[1][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_12_s2/CLK |
| 7.717 | -0.046 | tSu | 1 | R31C78[1][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_12_s2 |
Path Statistics:
| Clock Skew | -0.007 |
| Setup Relationship | 6.250 |
| Logic Level | 6 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.520, 100.000% |
| Arrival Data Path Delay | cell: 1.765, 28.792%; route: 4.090, 66.716%; tC2Q: 0.275, 4.493% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.513, 100.000% |
Path3
Path Summary:
| Slack | 0.137 |
| Data Arrival Time | 7.463 |
| Data Required Time | 7.600 |
| From | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0 |
| To | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_19_s1 |
| Launch Clk | pclk:[R] |
| Latch Clk | pclk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | pclk | ||||
| 0.000 | 0.000 | tCL | RR | 10163 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK |
| 1.520 | 1.520 | tNET | RR | 1 | R44C83[1][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/CLK |
| 1.795 | 0.275 | tC2Q | RR | 2598 | R44C83[1][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/Q |
| 3.668 | 1.873 | tNET | RR | 1 | R46C84[2][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_lcmd_11_s8/I2 |
| 4.047 | 0.379 | tINS | RR | 1 | R46C84[2][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_lcmd_11_s8/F |
| 4.148 | 0.101 | tNET | RR | 1 | R46C84[2][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3108_s19/I2 |
| 4.520 | 0.372 | tINS | RR | 2 | R46C84[2][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3108_s19/F |
| 5.555 | 1.035 | tNET | RR | 1 | R20C80[3][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5583_s4/I2 |
| 5.930 | 0.375 | tINS | RR | 1 | R20C80[3][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5583_s4/F |
| 6.069 | 0.139 | tNET | RR | 1 | R20C78[3][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5583_s1/I1 |
| 6.427 | 0.358 | tINS | RR | 1 | R20C78[3][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5583_s1/F |
| 6.677 | 0.250 | tNET | RR | 1 | R21C79[0][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5583_s0/I0 |
| 7.056 | 0.379 | tINS | RR | 2 | R21C79[0][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5583_s0/F |
| 7.463 | 0.407 | tNET | RR | 1 | R21C84[1][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_19_s1/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.250 | 6.250 | active clock edge time | ||||
| 6.250 | 0.000 | pclk | ||||
| 6.250 | 0.000 | tCL | RR | 10163 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK |
| 7.763 | 1.513 | tNET | RR | 1 | R21C84[1][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_19_s1/CLK |
| 7.600 | -0.164 | tSu | 1 | R21C84[1][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_19_s1 |
Path Statistics:
| Clock Skew | -0.007 |
| Setup Relationship | 6.250 |
| Logic Level | 6 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.520, 100.000% |
| Arrival Data Path Delay | cell: 1.863, 31.349%; route: 3.804, 64.016%; tC2Q: 0.275, 4.634% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.513, 100.000% |
Path4
Path Summary:
| Slack | 0.211 |
| Data Arrival Time | 7.513 |
| Data Required Time | 7.724 |
| From | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0 |
| To | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_12_s1 |
| Launch Clk | pclk:[R] |
| Latch Clk | pclk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | pclk | ||||
| 0.000 | 0.000 | tCL | RR | 10163 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK |
| 1.520 | 1.520 | tNET | RR | 1 | R44C83[1][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/CLK |
| 1.795 | 0.275 | tC2Q | RR | 2598 | R44C83[1][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/Q |
| 3.682 | 1.886 | tNET | RR | 1 | R45C82[3][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_lcmd_20_s8/I2 |
| 4.040 | 0.358 | tINS | RR | 1 | R45C82[3][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_lcmd_20_s8/F |
| 4.155 | 0.115 | tNET | RR | 1 | R45C82[2][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3099_s19/I2 |
| 4.487 | 0.332 | tINS | RR | 2 | R45C82[2][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3099_s19/F |
| 5.522 | 1.035 | tNET | RR | 1 | R18C78[3][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5590_s4/I2 |
| 5.881 | 0.358 | tINS | RR | 1 | R18C78[3][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5590_s4/F |
| 5.882 | 0.002 | tNET | RR | 1 | R18C78[3][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5590_s1/I1 |
| 6.241 | 0.358 | tINS | RR | 1 | R18C78[3][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5590_s1/F |
| 6.851 | 0.610 | tNET | RR | 1 | R30C79[3][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5590_s0/I0 |
| 7.209 | 0.358 | tINS | RR | 2 | R30C79[3][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5590_s0/F |
| 7.513 | 0.304 | tNET | RR | 1 | R31C79[0][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_12_s1/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.250 | 6.250 | active clock edge time | ||||
| 6.250 | 0.000 | pclk | ||||
| 6.250 | 0.000 | tCL | RR | 10163 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK |
| 7.770 | 1.520 | tNET | RR | 1 | R31C79[0][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_12_s1/CLK |
| 7.724 | -0.046 | tSu | 1 | R31C79[0][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_12_s1 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 6.250 |
| Logic Level | 6 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.520, 100.000% |
| Arrival Data Path Delay | cell: 1.765, 29.449%; route: 3.953, 65.956%; tC2Q: 0.275, 4.595% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.520, 100.000% |
Path5
Path Summary:
| Slack | 0.220 |
| Data Arrival Time | 7.497 |
| Data Required Time | 7.717 |
| From | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0 |
| To | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_19_s2 |
| Launch Clk | pclk:[R] |
| Latch Clk | pclk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | pclk | ||||
| 0.000 | 0.000 | tCL | RR | 10163 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK |
| 1.520 | 1.520 | tNET | RR | 1 | R44C83[1][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/CLK |
| 1.795 | 0.275 | tC2Q | RR | 2598 | R44C83[1][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/Q |
| 3.668 | 1.873 | tNET | RR | 1 | R46C84[2][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_lcmd_11_s8/I2 |
| 4.047 | 0.379 | tINS | RR | 1 | R46C84[2][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_lcmd_11_s8/F |
| 4.148 | 0.101 | tNET | RR | 1 | R46C84[2][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3108_s19/I2 |
| 4.520 | 0.372 | tINS | RR | 2 | R46C84[2][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3108_s19/F |
| 5.555 | 1.035 | tNET | RR | 1 | R20C80[3][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5583_s4/I2 |
| 5.930 | 0.375 | tINS | RR | 1 | R20C80[3][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5583_s4/F |
| 6.069 | 0.139 | tNET | RR | 1 | R20C78[3][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5583_s1/I1 |
| 6.427 | 0.358 | tINS | RR | 1 | R20C78[3][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5583_s1/F |
| 6.677 | 0.250 | tNET | RR | 1 | R21C79[0][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5583_s0/I0 |
| 7.056 | 0.379 | tINS | RR | 2 | R21C79[0][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5583_s0/F |
| 7.497 | 0.441 | tNET | RR | 1 | R21C82[2][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_19_s2/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.250 | 6.250 | active clock edge time | ||||
| 6.250 | 0.000 | pclk | ||||
| 6.250 | 0.000 | tCL | RR | 10163 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK |
| 7.763 | 1.513 | tNET | RR | 1 | R21C82[2][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_19_s2/CLK |
| 7.717 | -0.046 | tSu | 1 | R21C82[2][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_19_s2 |
Path Statistics:
| Clock Skew | -0.007 |
| Setup Relationship | 6.250 |
| Logic Level | 6 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.520, 100.000% |
| Arrival Data Path Delay | cell: 1.863, 31.170%; route: 3.839, 64.222%; tC2Q: 0.275, 4.608% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.513, 100.000% |
Path6
Path Summary:
| Slack | 0.230 |
| Data Arrival Time | 7.488 |
| Data Required Time | 7.717 |
| From | UserLayer_top_inst/ControlTransfer_inst/bmRequestType_latch_1_s0 |
| To | UserLayer_top_inst/ControlTransfer_inst/transfer_in_data_mux_3_s0 |
| Launch Clk | pclk:[R] |
| Latch Clk | pclk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | pclk | ||||
| 0.000 | 0.000 | tCL | RR | 10163 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK |
| 1.513 | 1.513 | tNET | RR | 1 | R55C39[1][B] | UserLayer_top_inst/ControlTransfer_inst/bmRequestType_latch_1_s0/CLK |
| 1.789 | 0.275 | tC2Q | RR | 1 | R55C39[1][B] | UserLayer_top_inst/ControlTransfer_inst/bmRequestType_latch_1_s0/Q |
| 2.123 | 0.334 | tNET | RR | 1 | R57C41[3][A] | UserLayer_top_inst/ControlTransfer_inst/n4443_s20/I0 |
| 2.481 | 0.358 | tINS | RR | 2 | R57C41[3][A] | UserLayer_top_inst/ControlTransfer_inst/n4443_s20/F |
| 3.030 | 0.549 | tNET | RR | 1 | R72C42[3][A] | UserLayer_top_inst/ControlTransfer_inst/n4443_s18/I3 |
| 3.405 | 0.375 | tINS | RR | 5 | R72C42[3][A] | UserLayer_top_inst/ControlTransfer_inst/n4443_s18/F |
| 4.152 | 0.747 | tNET | RR | 1 | R66C47[3][B] | UserLayer_top_inst/ControlTransfer_inst/n4443_s17/I1 |
| 4.510 | 0.358 | tINS | RR | 48 | R66C47[3][B] | UserLayer_top_inst/ControlTransfer_inst/n4443_s17/F |
| 5.010 | 0.499 | tNET | RR | 1 | R68C42[0][B] | UserLayer_top_inst/ControlTransfer_inst/n4507_s21/I2 |
| 5.389 | 0.379 | tINS | RR | 15 | R68C42[0][B] | UserLayer_top_inst/ControlTransfer_inst/n4507_s21/F |
| 5.795 | 0.406 | tNET | RR | 1 | R66C45[2][A] | UserLayer_top_inst/ControlTransfer_inst/n4531_s16/I1 |
| 5.984 | 0.189 | tINS | RR | 1 | R66C45[2][A] | UserLayer_top_inst/ControlTransfer_inst/n4531_s16/F |
| 6.396 | 0.412 | tNET | RR | 1 | R68C42[2][B] | UserLayer_top_inst/ControlTransfer_inst/n4531_s12/I3 |
| 6.585 | 0.189 | tINS | RR | 1 | R68C42[2][B] | UserLayer_top_inst/ControlTransfer_inst/n4531_s12/F |
| 7.109 | 0.524 | tNET | RR | 1 | R68C43[1][B] | UserLayer_top_inst/ControlTransfer_inst/n4531_s10/I2 |
| 7.488 | 0.379 | tINS | RR | 1 | R68C43[1][B] | UserLayer_top_inst/ControlTransfer_inst/n4531_s10/F |
| 7.488 | 0.000 | tNET | RR | 1 | R68C43[1][B] | UserLayer_top_inst/ControlTransfer_inst/transfer_in_data_mux_3_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.250 | 6.250 | active clock edge time | ||||
| 6.250 | 0.000 | pclk | ||||
| 6.250 | 0.000 | tCL | RR | 10163 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK |
| 7.763 | 1.513 | tNET | RR | 1 | R68C43[1][B] | UserLayer_top_inst/ControlTransfer_inst/transfer_in_data_mux_3_s0/CLK |
| 7.717 | -0.046 | tSu | 1 | R68C43[1][B] | UserLayer_top_inst/ControlTransfer_inst/transfer_in_data_mux_3_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 6.250 |
| Logic Level | 8 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.513, 100.000% |
| Arrival Data Path Delay | cell: 2.227, 37.285%; route: 3.471, 58.105%; tC2Q: 0.275, 4.610% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.513, 100.000% |
Path7
Path Summary:
| Slack | 0.274 |
| Data Arrival Time | 7.444 |
| Data Required Time | 7.717 |
| From | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0 |
| To | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_6_s2 |
| Launch Clk | pclk:[R] |
| Latch Clk | pclk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | pclk | ||||
| 0.000 | 0.000 | tCL | RR | 10163 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK |
| 1.520 | 1.520 | tNET | RR | 1 | R44C83[1][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/CLK |
| 1.795 | 0.275 | tC2Q | RR | 2598 | R44C83[1][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/Q |
| 3.686 | 1.891 | tNET | RR | 1 | R44C84[3][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_lcmd_62_s10/I2 |
| 4.045 | 0.358 | tINS | RR | 2 | R44C84[3][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_lcmd_62_s10/F |
| 4.162 | 0.117 | tNET | RR | 1 | R45C84[3][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5596_s7/I2 |
| 4.460 | 0.299 | tINS | RR | 1 | R45C84[3][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5596_s7/F |
| 5.297 | 0.836 | tNET | RR | 1 | R23C83[3][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5596_s5/I2 |
| 5.487 | 0.191 | tINS | RR | 1 | R23C83[3][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5596_s5/F |
| 5.586 | 0.099 | tNET | RR | 1 | R23C83[1][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5596_s2/I0 |
| 5.958 | 0.372 | tINS | RR | 1 | R23C83[1][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5596_s2/F |
| 6.407 | 0.449 | tNET | RR | 1 | R27C79[3][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5596_s0/I1 |
| 6.782 | 0.375 | tINS | RR | 2 | R27C79[3][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5596_s0/F |
| 7.444 | 0.662 | tNET | RR | 1 | R31C78[1][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_6_s2/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.250 | 6.250 | active clock edge time | ||||
| 6.250 | 0.000 | pclk | ||||
| 6.250 | 0.000 | tCL | RR | 10163 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK |
| 7.763 | 1.513 | tNET | RR | 1 | R31C78[1][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_6_s2/CLK |
| 7.717 | -0.046 | tSu | 1 | R31C78[1][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_6_s2 |
Path Statistics:
| Clock Skew | -0.007 |
| Setup Relationship | 6.250 |
| Logic Level | 6 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.520, 100.000% |
| Arrival Data Path Delay | cell: 1.595, 26.922%; route: 4.054, 68.429%; tC2Q: 0.275, 4.649% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.513, 100.000% |
Path8
Path Summary:
| Slack | 0.280 |
| Data Arrival Time | 7.449 |
| Data Required Time | 7.729 |
| From | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_word_alignment/data_in_r0_10_s0 |
| To | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_word_alignment/cnt0_1_s1 |
| Launch Clk | q0_lane1_fabric_rx_clk:[R] |
| Latch Clk | q0_lane1_fabric_rx_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | q0_lane1_fabric_rx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 518 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_RX_O_FABRIC_CLK |
| 1.513 | 1.513 | tNET | RR | 1 | R25C79[2][B] | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_word_alignment/data_in_r0_10_s0/CLK |
| 1.789 | 0.275 | tC2Q | RR | 12 | R25C79[2][B] | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_word_alignment/data_in_r0_10_s0/Q |
| 2.082 | 0.293 | tNET | RR | 1 | R26C81[2][A] | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_word_alignment/n730_s25/I1 |
| 2.461 | 0.379 | tINS | RR | 2 | R26C81[2][A] | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_word_alignment/n730_s25/F |
| 3.201 | 0.740 | tNET | RR | 1 | R25C81[0][A] | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_word_alignment/n730_s15/I3 |
| 3.390 | 0.189 | tINS | RR | 2 | R25C81[0][A] | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_word_alignment/n730_s15/F |
| 3.491 | 0.101 | tNET | RR | 1 | R25C81[2][B] | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_word_alignment/n730_s7/I3 |
| 3.823 | 0.332 | tINS | RR | 4 | R25C81[2][B] | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_word_alignment/n730_s7/F |
| 4.532 | 0.709 | tNET | RR | 1 | R25C82[1][A] | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_word_alignment/n762_s34/I2 |
| 4.911 | 0.379 | tINS | RR | 1 | R25C82[1][A] | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_word_alignment/n762_s34/F |
| 5.147 | 0.236 | tNET | RR | 1 | R26C82[0][B] | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_word_alignment/n762_s18/I1 |
| 5.526 | 0.379 | tINS | RR | 1 | R26C82[0][B] | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_word_alignment/n762_s18/F |
| 5.891 | 0.365 | tNET | RR | 1 | R26C85[3][B] | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_word_alignment/n762_s8/I0 |
| 6.249 | 0.358 | tINS | RR | 1 | R26C85[3][B] | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_word_alignment/n762_s8/F |
| 6.859 | 0.610 | tNET | RR | 1 | R25C86[0][A] | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_word_alignment/n762_s4/I0 |
| 7.238 | 0.379 | tINS | RR | 1 | R25C86[0][A] | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_word_alignment/n762_s4/F |
| 7.240 | 0.002 | tNET | RR | 1 | R25C86[3][A] | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_word_alignment/n762_s3/I0 |
| 7.449 | 0.209 | tINS | RF | 1 | R25C86[3][A] | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_word_alignment/n762_s3/F |
| 7.449 | 0.000 | tNET | FF | 1 | R25C86[3][A] | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_word_alignment/cnt0_1_s1/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.250 | 6.250 | active clock edge time | ||||
| 6.250 | 0.000 | q0_lane1_fabric_rx_clk | ||||
| 6.250 | 0.000 | tCL | RR | 518 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_RX_O_FABRIC_CLK |
| 7.770 | 1.520 | tNET | RR | 1 | R25C86[3][A] | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_word_alignment/cnt0_1_s1/CLK |
| 7.729 | -0.041 | tSu | 1 | R25C86[3][A] | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_word_alignment/cnt0_1_s1 |
Path Statistics:
| Clock Skew | 0.007 |
| Setup Relationship | 6.250 |
| Logic Level | 9 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.513, 100.000% |
| Arrival Data Path Delay | cell: 2.604, 43.867%; route: 3.056, 51.494%; tC2Q: 0.275, 4.640% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.520, 100.000% |
Path9
Path Summary:
| Slack | 0.290 |
| Data Arrival Time | 7.310 |
| Data Required Time | 7.600 |
| From | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0 |
| To | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_9_s2 |
| Launch Clk | pclk:[R] |
| Latch Clk | pclk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | pclk | ||||
| 0.000 | 0.000 | tCL | RR | 10163 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK |
| 1.520 | 1.520 | tNET | RR | 1 | R44C83[1][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/CLK |
| 1.795 | 0.275 | tC2Q | RR | 2598 | R44C83[1][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/Q |
| 3.668 | 1.873 | tNET | RR | 1 | R43C80[2][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_lcmd_49_s8/I2 |
| 4.047 | 0.379 | tINS | RR | 2 | R43C80[2][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_lcmd_49_s8/F |
| 4.164 | 0.117 | tNET | RR | 1 | R43C81[0][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5593_s7/I2 |
| 4.543 | 0.379 | tINS | RR | 1 | R43C81[0][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5593_s7/F |
| 5.291 | 0.748 | tNET | RR | 1 | R18C81[2][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5593_s5/I2 |
| 5.623 | 0.332 | tINS | RR | 1 | R18C81[2][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5593_s5/F |
| 6.010 | 0.387 | tNET | RR | 1 | R16C78[3][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5593_s2/I0 |
| 6.309 | 0.299 | tINS | RR | 1 | R16C78[3][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5593_s2/F |
| 6.740 | 0.431 | tNET | RR | 1 | R20C78[0][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5593_s0/I1 |
| 7.072 | 0.332 | tINS | RR | 2 | R20C78[0][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5593_s0/F |
| 7.310 | 0.238 | tNET | RR | 1 | R22C78[0][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_9_s2/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.250 | 6.250 | active clock edge time | ||||
| 6.250 | 0.000 | pclk | ||||
| 6.250 | 0.000 | tCL | RR | 10163 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK |
| 7.763 | 1.513 | tNET | RR | 1 | R22C78[0][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_9_s2/CLK |
| 7.600 | -0.164 | tSu | 1 | R22C78[0][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_9_s2 |
Path Statistics:
| Clock Skew | -0.007 |
| Setup Relationship | 6.250 |
| Logic Level | 6 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.520, 100.000% |
| Arrival Data Path Delay | cell: 1.721, 29.722%; route: 3.794, 65.522%; tC2Q: 0.275, 4.757% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.513, 100.000% |
Path10
Path Summary:
| Slack | 0.290 |
| Data Arrival Time | 7.310 |
| Data Required Time | 7.600 |
| From | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0 |
| To | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_9_s1 |
| Launch Clk | pclk:[R] |
| Latch Clk | pclk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | pclk | ||||
| 0.000 | 0.000 | tCL | RR | 10163 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK |
| 1.520 | 1.520 | tNET | RR | 1 | R44C83[1][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/CLK |
| 1.795 | 0.275 | tC2Q | RR | 2598 | R44C83[1][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/Q |
| 3.668 | 1.873 | tNET | RR | 1 | R43C80[2][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_lcmd_49_s8/I2 |
| 4.047 | 0.379 | tINS | RR | 2 | R43C80[2][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_lcmd_49_s8/F |
| 4.164 | 0.117 | tNET | RR | 1 | R43C81[0][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5593_s7/I2 |
| 4.543 | 0.379 | tINS | RR | 1 | R43C81[0][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5593_s7/F |
| 5.291 | 0.748 | tNET | RR | 1 | R18C81[2][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5593_s5/I2 |
| 5.623 | 0.332 | tINS | RR | 1 | R18C81[2][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5593_s5/F |
| 6.010 | 0.387 | tNET | RR | 1 | R16C78[3][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5593_s2/I0 |
| 6.309 | 0.299 | tINS | RR | 1 | R16C78[3][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5593_s2/F |
| 6.740 | 0.431 | tNET | RR | 1 | R20C78[0][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5593_s0/I1 |
| 7.072 | 0.332 | tINS | RR | 2 | R20C78[0][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5593_s0/F |
| 7.310 | 0.238 | tNET | RR | 1 | R21C78[0][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_9_s1/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.250 | 6.250 | active clock edge time | ||||
| 6.250 | 0.000 | pclk | ||||
| 6.250 | 0.000 | tCL | RR | 10163 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK |
| 7.763 | 1.513 | tNET | RR | 1 | R21C78[0][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_9_s1/CLK |
| 7.600 | -0.164 | tSu | 1 | R21C78[0][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_9_s1 |
Path Statistics:
| Clock Skew | -0.007 |
| Setup Relationship | 6.250 |
| Logic Level | 6 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.520, 100.000% |
| Arrival Data Path Delay | cell: 1.721, 29.722%; route: 3.794, 65.522%; tC2Q: 0.275, 4.757% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.513, 100.000% |
Path11
Path Summary:
| Slack | 0.327 |
| Data Arrival Time | 7.390 |
| Data Required Time | 7.717 |
| From | UserLayer_top_inst/ControlTransfer_inst/bmRequestType_latch_1_s0 |
| To | UserLayer_top_inst/ControlTransfer_inst/transfer_in_data_mux_2_s0 |
| Launch Clk | pclk:[R] |
| Latch Clk | pclk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | pclk | ||||
| 0.000 | 0.000 | tCL | RR | 10163 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK |
| 1.513 | 1.513 | tNET | RR | 1 | R55C39[1][B] | UserLayer_top_inst/ControlTransfer_inst/bmRequestType_latch_1_s0/CLK |
| 1.789 | 0.275 | tC2Q | RR | 1 | R55C39[1][B] | UserLayer_top_inst/ControlTransfer_inst/bmRequestType_latch_1_s0/Q |
| 2.123 | 0.334 | tNET | RR | 1 | R57C41[3][A] | UserLayer_top_inst/ControlTransfer_inst/n4443_s20/I0 |
| 2.481 | 0.358 | tINS | RR | 2 | R57C41[3][A] | UserLayer_top_inst/ControlTransfer_inst/n4443_s20/F |
| 3.030 | 0.549 | tNET | RR | 1 | R72C42[3][A] | UserLayer_top_inst/ControlTransfer_inst/n4443_s18/I3 |
| 3.405 | 0.375 | tINS | RR | 5 | R72C42[3][A] | UserLayer_top_inst/ControlTransfer_inst/n4443_s18/F |
| 4.152 | 0.747 | tNET | RR | 1 | R66C47[3][B] | UserLayer_top_inst/ControlTransfer_inst/n4443_s17/I1 |
| 4.510 | 0.358 | tINS | RR | 48 | R66C47[3][B] | UserLayer_top_inst/ControlTransfer_inst/n4443_s17/F |
| 5.010 | 0.499 | tNET | RR | 1 | R68C42[0][B] | UserLayer_top_inst/ControlTransfer_inst/n4507_s21/I2 |
| 5.389 | 0.379 | tINS | RR | 15 | R68C42[0][B] | UserLayer_top_inst/ControlTransfer_inst/n4507_s21/F |
| 5.685 | 0.296 | tNET | RR | 1 | R66C44[1][A] | UserLayer_top_inst/ControlTransfer_inst/n4533_s16/I1 |
| 6.057 | 0.372 | tINS | RR | 1 | R66C44[1][A] | UserLayer_top_inst/ControlTransfer_inst/n4533_s16/F |
| 6.292 | 0.236 | tNET | RR | 1 | R66C42[2][A] | UserLayer_top_inst/ControlTransfer_inst/n4533_s12/I3 |
| 6.664 | 0.372 | tINS | RR | 1 | R66C42[2][A] | UserLayer_top_inst/ControlTransfer_inst/n4533_s12/F |
| 7.011 | 0.347 | tNET | RR | 1 | R67C43[0][B] | UserLayer_top_inst/ControlTransfer_inst/n4533_s10/I2 |
| 7.390 | 0.379 | tINS | RR | 1 | R67C43[0][B] | UserLayer_top_inst/ControlTransfer_inst/n4533_s10/F |
| 7.390 | 0.000 | tNET | RR | 1 | R67C43[0][B] | UserLayer_top_inst/ControlTransfer_inst/transfer_in_data_mux_2_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.250 | 6.250 | active clock edge time | ||||
| 6.250 | 0.000 | pclk | ||||
| 6.250 | 0.000 | tCL | RR | 10163 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK |
| 7.763 | 1.513 | tNET | RR | 1 | R67C43[0][B] | UserLayer_top_inst/ControlTransfer_inst/transfer_in_data_mux_2_s0/CLK |
| 7.717 | -0.046 | tSu | 1 | R67C43[0][B] | UserLayer_top_inst/ControlTransfer_inst/transfer_in_data_mux_2_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 6.250 |
| Logic Level | 8 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.513, 100.000% |
| Arrival Data Path Delay | cell: 2.593, 44.119%; route: 3.009, 51.194%; tC2Q: 0.275, 4.686% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.513, 100.000% |
Path12
Path Summary:
| Slack | 0.347 |
| Data Arrival Time | 7.259 |
| Data Required Time | 7.606 |
| From | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/reset_n_d_s0 |
| To | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_25_s2 |
| Launch Clk | pclk:[R] |
| Latch Clk | pclk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | pclk | ||||
| 0.000 | 0.000 | tCL | RR | 10163 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK |
| 1.870 | 1.870 | tNET | RR | 1 | R30C63[1][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/reset_n_d_s0/CLK |
| 2.134 | 0.265 | tC2Q | RF | 159 | R30C63[1][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/reset_n_d_s0/Q |
| 3.215 | 1.081 | tNET | FF | 1 | R33C44[1][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_dpp_33_s8/I2 |
| 3.587 | 0.372 | tINS | FR | 1 | R33C44[1][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_dpp_33_s8/F |
| 3.688 | 0.101 | tNET | RR | 1 | R33C44[2][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5577_s6/I2 |
| 4.067 | 0.379 | tINS | RR | 3 | R33C44[2][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5577_s6/F |
| 4.670 | 0.603 | tNET | RR | 1 | R30C54[3][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5577_s3/I1 |
| 4.968 | 0.299 | tINS | RR | 1 | R30C54[3][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5577_s3/F |
| 6.645 | 1.677 | tNET | RR | 1 | R16C81[3][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5577_s0/I3 |
| 7.003 | 0.358 | tINS | RR | 2 | R16C81[3][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5577_s0/F |
| 7.259 | 0.256 | tNET | RR | 1 | R16C83[2][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_25_s2/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.250 | 6.250 | active clock edge time | ||||
| 6.250 | 0.000 | pclk | ||||
| 6.250 | 0.000 | tCL | RR | 10163 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK |
| 7.770 | 1.520 | tNET | RR | 1 | R16C83[2][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_25_s2/CLK |
| 7.606 | -0.164 | tSu | 1 | R16C83[2][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_25_s2 |
Path Statistics:
| Clock Skew | -0.350 |
| Setup Relationship | 6.250 |
| Logic Level | 5 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.870, 100.000% |
| Arrival Data Path Delay | cell: 1.408, 26.119%; route: 3.717, 68.971%; tC2Q: 0.265, 4.910% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.520, 100.000% |
Path13
Path Summary:
| Slack | 0.379 |
| Data Arrival Time | 7.214 |
| Data Required Time | 7.593 |
| From | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0 |
| To | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_28_s1 |
| Launch Clk | pclk:[R] |
| Latch Clk | pclk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | pclk | ||||
| 0.000 | 0.000 | tCL | RR | 10163 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK |
| 1.520 | 1.520 | tNET | RR | 1 | R44C83[1][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/CLK |
| 1.795 | 0.275 | tC2Q | RR | 2598 | R44C83[1][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/Q |
| 3.675 | 1.880 | tNET | RR | 1 | R46C81[3][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_lcmd_4_s8/I2 |
| 4.033 | 0.358 | tINS | RR | 1 | R46C81[3][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_lcmd_4_s8/F |
| 4.134 | 0.101 | tNET | RR | 1 | R46C81[3][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3115_s18/I2 |
| 4.433 | 0.299 | tINS | RR | 2 | R46C81[3][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3115_s18/F |
| 5.433 | 1.000 | tNET | RR | 1 | R18C81[1][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5574_s4/I2 |
| 5.812 | 0.379 | tINS | RR | 1 | R18C81[1][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5574_s4/F |
| 6.062 | 0.250 | tNET | RR | 1 | R16C82[1][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5574_s1/I1 |
| 6.441 | 0.379 | tINS | RR | 1 | R16C82[1][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5574_s1/F |
| 6.540 | 0.099 | tNET | RR | 1 | R16C82[1][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5574_s0/I0 |
| 6.919 | 0.379 | tINS | RR | 2 | R16C82[1][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5574_s0/F |
| 7.214 | 0.295 | tNET | RR | 1 | R16C85[2][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_28_s1/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.250 | 6.250 | active clock edge time | ||||
| 6.250 | 0.000 | pclk | ||||
| 6.250 | 0.000 | tCL | RR | 10163 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK |
| 7.757 | 1.507 | tNET | RR | 1 | R16C85[2][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_28_s1/CLK |
| 7.593 | -0.164 | tSu | 1 | R16C85[2][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_28_s1 |
Path Statistics:
| Clock Skew | -0.014 |
| Setup Relationship | 6.250 |
| Logic Level | 6 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.520, 100.000% |
| Arrival Data Path Delay | cell: 1.794, 31.502%; route: 3.625, 63.661%; tC2Q: 0.275, 4.837% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.507, 100.000% |
Path14
Path Summary:
| Slack | 0.432 |
| Data Arrival Time | 7.174 |
| Data Required Time | 7.606 |
| From | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0 |
| To | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_28_s2 |
| Launch Clk | pclk:[R] |
| Latch Clk | pclk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | pclk | ||||
| 0.000 | 0.000 | tCL | RR | 10163 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK |
| 1.520 | 1.520 | tNET | RR | 1 | R44C83[1][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/CLK |
| 1.795 | 0.275 | tC2Q | RR | 2598 | R44C83[1][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/Q |
| 3.675 | 1.880 | tNET | RR | 1 | R46C81[3][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_lcmd_4_s8/I2 |
| 4.033 | 0.358 | tINS | RR | 1 | R46C81[3][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_lcmd_4_s8/F |
| 4.134 | 0.101 | tNET | RR | 1 | R46C81[3][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3115_s18/I2 |
| 4.433 | 0.299 | tINS | RR | 2 | R46C81[3][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3115_s18/F |
| 5.433 | 1.000 | tNET | RR | 1 | R18C81[1][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5574_s4/I2 |
| 5.812 | 0.379 | tINS | RR | 1 | R18C81[1][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5574_s4/F |
| 6.062 | 0.250 | tNET | RR | 1 | R16C82[1][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5574_s1/I1 |
| 6.441 | 0.379 | tINS | RR | 1 | R16C82[1][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5574_s1/F |
| 6.540 | 0.099 | tNET | RR | 1 | R16C82[1][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5574_s0/I0 |
| 6.919 | 0.379 | tINS | RR | 2 | R16C82[1][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5574_s0/F |
| 7.174 | 0.256 | tNET | RR | 1 | R16C83[2][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_28_s2/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.250 | 6.250 | active clock edge time | ||||
| 6.250 | 0.000 | pclk | ||||
| 6.250 | 0.000 | tCL | RR | 10163 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK |
| 7.770 | 1.520 | tNET | RR | 1 | R16C83[2][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_28_s2/CLK |
| 7.606 | -0.164 | tSu | 1 | R16C83[2][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_28_s2 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 6.250 |
| Logic Level | 6 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.520, 100.000% |
| Arrival Data Path Delay | cell: 1.794, 31.723%; route: 3.585, 63.406%; tC2Q: 0.275, 4.871% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.520, 100.000% |
Path15
Path Summary:
| Slack | 0.464 |
| Data Arrival Time | 7.136 |
| Data Required Time | 7.600 |
| From | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0 |
| To | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_20_s1 |
| Launch Clk | pclk:[R] |
| Latch Clk | pclk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | pclk | ||||
| 0.000 | 0.000 | tCL | RR | 10163 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK |
| 1.520 | 1.520 | tNET | RR | 1 | R44C83[1][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/CLK |
| 1.795 | 0.275 | tC2Q | RR | 2598 | R44C83[1][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/Q |
| 3.675 | 1.880 | tNET | RR | 1 | R45C81[3][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_lcmd_44_s8/I2 |
| 4.033 | 0.358 | tINS | RR | 2 | R45C81[3][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_lcmd_44_s8/F |
| 4.150 | 0.117 | tNET | RR | 1 | R45C82[3][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5582_s7/I2 |
| 4.509 | 0.358 | tINS | RR | 1 | R45C82[3][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5582_s7/F |
| 5.314 | 0.805 | tNET | RR | 1 | R18C82[2][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5582_s5/I2 |
| 5.686 | 0.372 | tINS | RR | 1 | R18C82[2][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5582_s5/F |
| 6.073 | 0.387 | tNET | RR | 1 | R15C80[1][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5582_s2/I0 |
| 6.262 | 0.189 | tINS | RR | 1 | R15C80[1][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5582_s2/F |
| 6.512 | 0.250 | tNET | RR | 1 | R17C79[1][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5582_s0/I1 |
| 6.884 | 0.372 | tINS | RR | 2 | R17C79[1][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5582_s0/F |
| 7.136 | 0.252 | tNET | RR | 1 | R18C80[0][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_20_s1/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.250 | 6.250 | active clock edge time | ||||
| 6.250 | 0.000 | pclk | ||||
| 6.250 | 0.000 | tCL | RR | 10163 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK |
| 7.763 | 1.513 | tNET | RR | 1 | R18C80[0][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_20_s1/CLK |
| 7.600 | -0.164 | tSu | 1 | R18C80[0][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_20_s1 |
Path Statistics:
| Clock Skew | -0.007 |
| Setup Relationship | 6.250 |
| Logic Level | 6 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.520, 100.000% |
| Arrival Data Path Delay | cell: 1.649, 29.361%; route: 3.691, 65.734%; tC2Q: 0.275, 4.904% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.513, 100.000% |
Path16
Path Summary:
| Slack | 0.485 |
| Data Arrival Time | 7.121 |
| Data Required Time | 7.606 |
| From | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0 |
| To | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_20_s2 |
| Launch Clk | pclk:[R] |
| Latch Clk | pclk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | pclk | ||||
| 0.000 | 0.000 | tCL | RR | 10163 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK |
| 1.520 | 1.520 | tNET | RR | 1 | R44C83[1][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/CLK |
| 1.795 | 0.275 | tC2Q | RR | 2598 | R44C83[1][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/Q |
| 3.675 | 1.880 | tNET | RR | 1 | R45C81[3][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_lcmd_44_s8/I2 |
| 4.033 | 0.358 | tINS | RR | 2 | R45C81[3][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_lcmd_44_s8/F |
| 4.150 | 0.117 | tNET | RR | 1 | R45C82[3][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5582_s7/I2 |
| 4.509 | 0.358 | tINS | RR | 1 | R45C82[3][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5582_s7/F |
| 5.314 | 0.805 | tNET | RR | 1 | R18C82[2][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5582_s5/I2 |
| 5.686 | 0.372 | tINS | RR | 1 | R18C82[2][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5582_s5/F |
| 6.073 | 0.387 | tNET | RR | 1 | R15C80[1][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5582_s2/I0 |
| 6.262 | 0.189 | tINS | RR | 1 | R15C80[1][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5582_s2/F |
| 6.512 | 0.250 | tNET | RR | 1 | R17C79[1][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5582_s0/I1 |
| 6.884 | 0.372 | tINS | RR | 2 | R17C79[1][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5582_s0/F |
| 7.121 | 0.238 | tNET | RR | 1 | R18C79[2][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_20_s2/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.250 | 6.250 | active clock edge time | ||||
| 6.250 | 0.000 | pclk | ||||
| 6.250 | 0.000 | tCL | RR | 10163 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK |
| 7.770 | 1.520 | tNET | RR | 1 | R18C79[2][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_20_s2/CLK |
| 7.606 | -0.164 | tSu | 1 | R18C79[2][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_20_s2 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 6.250 |
| Logic Level | 6 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.520, 100.000% |
| Arrival Data Path Delay | cell: 1.649, 29.437%; route: 3.677, 65.646%; tC2Q: 0.275, 4.917% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.520, 100.000% |
Path17
Path Summary:
| Slack | 0.489 |
| Data Arrival Time | 7.104 |
| Data Required Time | 7.593 |
| From | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/reset_n_d_s0 |
| To | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_25_s1 |
| Launch Clk | pclk:[R] |
| Latch Clk | pclk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | pclk | ||||
| 0.000 | 0.000 | tCL | RR | 10163 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK |
| 1.870 | 1.870 | tNET | RR | 1 | R30C63[1][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/reset_n_d_s0/CLK |
| 2.134 | 0.265 | tC2Q | RF | 159 | R30C63[1][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/reset_n_d_s0/Q |
| 3.215 | 1.081 | tNET | FF | 1 | R33C44[1][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_dpp_33_s8/I2 |
| 3.587 | 0.372 | tINS | FR | 1 | R33C44[1][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_dpp_33_s8/F |
| 3.688 | 0.101 | tNET | RR | 1 | R33C44[2][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5577_s6/I2 |
| 4.067 | 0.379 | tINS | RR | 3 | R33C44[2][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5577_s6/F |
| 4.670 | 0.603 | tNET | RR | 1 | R30C54[3][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5577_s3/I1 |
| 4.968 | 0.299 | tINS | RR | 1 | R30C54[3][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5577_s3/F |
| 6.645 | 1.677 | tNET | RR | 1 | R16C81[3][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5577_s0/I3 |
| 7.003 | 0.358 | tINS | RR | 2 | R16C81[3][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5577_s0/F |
| 7.104 | 0.101 | tNET | RR | 1 | R16C81[1][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_25_s1/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.250 | 6.250 | active clock edge time | ||||
| 6.250 | 0.000 | pclk | ||||
| 6.250 | 0.000 | tCL | RR | 10163 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK |
| 7.757 | 1.507 | tNET | RR | 1 | R16C81[1][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_25_s1/CLK |
| 7.593 | -0.164 | tSu | 1 | R16C81[1][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_25_s1 |
Path Statistics:
| Clock Skew | -0.363 |
| Setup Relationship | 6.250 |
| Logic Level | 5 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.870, 100.000% |
| Arrival Data Path Delay | cell: 1.408, 26.891%; route: 3.562, 68.054%; tC2Q: 0.265, 5.055% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.507, 100.000% |
Path18
Path Summary:
| Slack | 0.511 |
| Data Arrival Time | 7.206 |
| Data Required Time | 7.717 |
| From | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0 |
| To | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_17_s1 |
| Launch Clk | pclk:[R] |
| Latch Clk | pclk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | pclk | ||||
| 0.000 | 0.000 | tCL | RR | 10163 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK |
| 1.520 | 1.520 | tNET | RR | 1 | R44C83[1][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/CLK |
| 1.795 | 0.275 | tC2Q | RR | 2598 | R44C83[1][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/Q |
| 3.694 | 1.898 | tNET | RR | 1 | R42C82[0][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_lcmd_9_s8/I2 |
| 3.883 | 0.189 | tINS | RR | 1 | R42C82[0][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_lcmd_9_s8/F |
| 3.998 | 0.115 | tNET | RR | 1 | R43C82[3][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3110_s18/I2 |
| 4.356 | 0.358 | tINS | RR | 2 | R43C82[3][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3110_s18/F |
| 5.340 | 0.984 | tNET | RR | 1 | R18C79[3][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5585_s4/I2 |
| 5.715 | 0.375 | tINS | RR | 1 | R18C79[3][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5585_s4/F |
| 6.088 | 0.373 | tNET | RR | 1 | R16C77[3][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5585_s1/I1 |
| 6.463 | 0.375 | tINS | RR | 1 | R16C77[3][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5585_s1/F |
| 6.465 | 0.002 | tNET | RR | 1 | R16C77[3][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5585_s0/I0 |
| 6.763 | 0.299 | tINS | RR | 2 | R16C77[3][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5585_s0/F |
| 7.206 | 0.443 | tNET | RR | 1 | R15C76[3][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_17_s1/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.250 | 6.250 | active clock edge time | ||||
| 6.250 | 0.000 | pclk | ||||
| 6.250 | 0.000 | tCL | RR | 10163 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK |
| 7.763 | 1.513 | tNET | RR | 1 | R15C76[3][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_17_s1/CLK |
| 7.717 | -0.046 | tSu | 1 | R15C76[3][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_17_s1 |
Path Statistics:
| Clock Skew | -0.007 |
| Setup Relationship | 6.250 |
| Logic Level | 6 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.520, 100.000% |
| Arrival Data Path Delay | cell: 1.597, 28.079%; route: 3.814, 67.078%; tC2Q: 0.275, 4.843% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.513, 100.000% |
Path19
Path Summary:
| Slack | 0.513 |
| Data Arrival Time | 7.204 |
| Data Required Time | 7.717 |
| From | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0 |
| To | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_17_s2 |
| Launch Clk | pclk:[R] |
| Latch Clk | pclk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | pclk | ||||
| 0.000 | 0.000 | tCL | RR | 10163 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK |
| 1.520 | 1.520 | tNET | RR | 1 | R44C83[1][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/CLK |
| 1.795 | 0.275 | tC2Q | RR | 2598 | R44C83[1][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/Q |
| 3.694 | 1.898 | tNET | RR | 1 | R42C82[0][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_lcmd_9_s8/I2 |
| 3.883 | 0.189 | tINS | RR | 1 | R42C82[0][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_lcmd_9_s8/F |
| 3.998 | 0.115 | tNET | RR | 1 | R43C82[3][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3110_s18/I2 |
| 4.356 | 0.358 | tINS | RR | 2 | R43C82[3][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3110_s18/F |
| 5.340 | 0.984 | tNET | RR | 1 | R18C79[3][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5585_s4/I2 |
| 5.715 | 0.375 | tINS | RR | 1 | R18C79[3][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5585_s4/F |
| 6.088 | 0.373 | tNET | RR | 1 | R16C77[3][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5585_s1/I1 |
| 6.463 | 0.375 | tINS | RR | 1 | R16C77[3][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5585_s1/F |
| 6.465 | 0.002 | tNET | RR | 1 | R16C77[3][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5585_s0/I0 |
| 6.763 | 0.299 | tINS | RR | 2 | R16C77[3][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5585_s0/F |
| 7.204 | 0.441 | tNET | RR | 1 | R15C76[0][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_17_s2/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.250 | 6.250 | active clock edge time | ||||
| 6.250 | 0.000 | pclk | ||||
| 6.250 | 0.000 | tCL | RR | 10163 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK |
| 7.763 | 1.513 | tNET | RR | 1 | R15C76[0][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_17_s2/CLK |
| 7.717 | -0.046 | tSu | 1 | R15C76[0][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_17_s2 |
Path Statistics:
| Clock Skew | -0.007 |
| Setup Relationship | 6.250 |
| Logic Level | 6 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.520, 100.000% |
| Arrival Data Path Delay | cell: 1.597, 28.087%; route: 3.812, 67.068%; tC2Q: 0.275, 4.845% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.513, 100.000% |
Path20
Path Summary:
| Slack | 0.550 |
| Data Arrival Time | 7.043 |
| Data Required Time | 7.593 |
| From | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0 |
| To | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_4_s1 |
| Launch Clk | pclk:[R] |
| Latch Clk | pclk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | pclk | ||||
| 0.000 | 0.000 | tCL | RR | 10163 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK |
| 1.520 | 1.520 | tNET | RR | 1 | R44C83[1][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/CLK |
| 1.795 | 0.275 | tC2Q | RR | 2598 | R44C83[1][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/Q |
| 3.675 | 1.880 | tNET | RR | 1 | R43C83[2][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_lcmd_28_s8/I2 |
| 4.054 | 0.379 | tINS | RR | 1 | R43C83[2][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_lcmd_28_s8/F |
| 4.058 | 0.004 | tNET | RR | 1 | R43C83[1][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3091_s21/I2 |
| 4.390 | 0.332 | tINS | RR | 2 | R43C83[1][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3091_s21/F |
| 5.391 | 1.002 | tNET | RR | 1 | R18C80[0][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5598_s4/I2 |
| 5.724 | 0.332 | tINS | RR | 1 | R18C80[0][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5598_s4/F |
| 5.999 | 0.275 | tNET | RR | 1 | R14C80[2][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5598_s1/I1 |
| 6.331 | 0.332 | tINS | RR | 1 | R14C80[2][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5598_s1/F |
| 6.430 | 0.099 | tNET | RR | 1 | R14C80[3][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5598_s0/I0 |
| 6.805 | 0.375 | tINS | RR | 2 | R14C80[3][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5598_s0/F |
| 7.043 | 0.238 | tNET | RR | 1 | R14C81[1][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_4_s1/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.250 | 6.250 | active clock edge time | ||||
| 6.250 | 0.000 | pclk | ||||
| 6.250 | 0.000 | tCL | RR | 10163 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK |
| 7.757 | 1.507 | tNET | RR | 1 | R14C81[1][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_4_s1/CLK |
| 7.593 | -0.164 | tSu | 1 | R14C81[1][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_4_s1 |
Path Statistics:
| Clock Skew | -0.014 |
| Setup Relationship | 6.250 |
| Logic Level | 6 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.520, 100.000% |
| Arrival Data Path Delay | cell: 1.750, 31.696%; route: 3.497, 63.318%; tC2Q: 0.275, 4.987% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.507, 100.000% |
Path21
Path Summary:
| Slack | 0.554 |
| Data Arrival Time | 7.163 |
| Data Required Time | 7.717 |
| From | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0 |
| To | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_14_s2 |
| Launch Clk | pclk:[R] |
| Latch Clk | pclk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | pclk | ||||
| 0.000 | 0.000 | tCL | RR | 10163 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK |
| 1.520 | 1.520 | tNET | RR | 1 | R44C83[1][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/CLK |
| 1.795 | 0.275 | tC2Q | RR | 2598 | R44C83[1][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/Q |
| 3.668 | 1.873 | tNET | RR | 1 | R41C80[0][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_lcmd_54_s8/I2 |
| 4.047 | 0.379 | tINS | RR | 2 | R41C80[0][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_lcmd_54_s8/F |
| 4.189 | 0.142 | tNET | RR | 1 | R41C82[2][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5588_s7/I2 |
| 4.378 | 0.189 | tINS | RR | 1 | R41C82[2][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5588_s7/F |
| 5.071 | 0.692 | tNET | RR | 1 | R18C82[3][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5588_s5/I2 |
| 5.446 | 0.375 | tINS | RR | 1 | R18C82[3][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5588_s5/F |
| 5.696 | 0.250 | tNET | RR | 1 | R15C82[1][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5588_s2/I0 |
| 6.075 | 0.379 | tINS | RR | 1 | R15C82[1][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5588_s2/F |
| 6.350 | 0.275 | tNET | RR | 1 | R15C78[2][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5588_s0/I1 |
| 6.722 | 0.372 | tINS | RR | 2 | R15C78[2][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5588_s0/F |
| 7.163 | 0.441 | tNET | RR | 1 | R14C80[0][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_14_s2/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.250 | 6.250 | active clock edge time | ||||
| 6.250 | 0.000 | pclk | ||||
| 6.250 | 0.000 | tCL | RR | 10163 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK |
| 7.763 | 1.513 | tNET | RR | 1 | R14C80[0][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_14_s2/CLK |
| 7.717 | -0.046 | tSu | 1 | R14C80[0][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_14_s2 |
Path Statistics:
| Clock Skew | -0.007 |
| Setup Relationship | 6.250 |
| Logic Level | 6 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.520, 100.000% |
| Arrival Data Path Delay | cell: 1.694, 30.016%; route: 3.674, 65.104%; tC2Q: 0.275, 4.880% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.513, 100.000% |
Path22
Path Summary:
| Slack | 0.556 |
| Data Arrival Time | 7.043 |
| Data Required Time | 7.600 |
| From | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0 |
| To | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_22_s2 |
| Launch Clk | pclk:[R] |
| Latch Clk | pclk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | pclk | ||||
| 0.000 | 0.000 | tCL | RR | 10163 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK |
| 1.520 | 1.520 | tNET | RR | 1 | R44C83[1][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/CLK |
| 1.795 | 0.275 | tC2Q | RR | 2598 | R44C83[1][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/Q |
| 3.670 | 1.875 | tNET | RR | 1 | R44C84[0][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_lcmd_14_s8/I2 |
| 3.859 | 0.189 | tINS | RR | 1 | R44C84[0][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_lcmd_14_s8/F |
| 3.974 | 0.115 | tNET | RR | 1 | R44C83[3][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3105_s20/I2 |
| 4.183 | 0.209 | tINS | RF | 2 | R44C83[3][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3105_s20/F |
| 5.312 | 1.129 | tNET | FF | 1 | R18C80[0][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5580_s4/I2 |
| 5.691 | 0.379 | tINS | FR | 1 | R18C80[0][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5580_s4/F |
| 5.693 | 0.002 | tNET | RR | 1 | R18C80[2][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5580_s1/I1 |
| 6.064 | 0.372 | tINS | RR | 1 | R18C80[2][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5580_s1/F |
| 6.398 | 0.334 | tNET | RR | 1 | R20C82[3][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5580_s0/I0 |
| 6.773 | 0.375 | tINS | RR | 2 | R20C82[3][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5580_s0/F |
| 7.043 | 0.270 | tNET | RR | 1 | R20C84[2][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_22_s2/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.250 | 6.250 | active clock edge time | ||||
| 6.250 | 0.000 | pclk | ||||
| 6.250 | 0.000 | tCL | RR | 10163 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK |
| 7.763 | 1.513 | tNET | RR | 1 | R20C84[2][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_22_s2/CLK |
| 7.600 | -0.164 | tSu | 1 | R20C84[2][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_22_s2 |
Path Statistics:
| Clock Skew | -0.007 |
| Setup Relationship | 6.250 |
| Logic Level | 6 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.520, 100.000% |
| Arrival Data Path Delay | cell: 1.524, 27.587%; route: 3.724, 67.427%; tC2Q: 0.275, 4.986% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.513, 100.000% |
Path23
Path Summary:
| Slack | 0.557 |
| Data Arrival Time | 7.043 |
| Data Required Time | 7.600 |
| From | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0 |
| To | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_4_s2 |
| Launch Clk | pclk:[R] |
| Latch Clk | pclk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | pclk | ||||
| 0.000 | 0.000 | tCL | RR | 10163 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK |
| 1.520 | 1.520 | tNET | RR | 1 | R44C83[1][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/CLK |
| 1.795 | 0.275 | tC2Q | RR | 2598 | R44C83[1][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/Q |
| 3.675 | 1.880 | tNET | RR | 1 | R43C83[2][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_lcmd_28_s8/I2 |
| 4.054 | 0.379 | tINS | RR | 1 | R43C83[2][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_lcmd_28_s8/F |
| 4.058 | 0.004 | tNET | RR | 1 | R43C83[1][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3091_s21/I2 |
| 4.390 | 0.332 | tINS | RR | 2 | R43C83[1][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3091_s21/F |
| 5.391 | 1.002 | tNET | RR | 1 | R18C80[0][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5598_s4/I2 |
| 5.724 | 0.332 | tINS | RR | 1 | R18C80[0][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5598_s4/F |
| 5.999 | 0.275 | tNET | RR | 1 | R14C80[2][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5598_s1/I1 |
| 6.331 | 0.332 | tINS | RR | 1 | R14C80[2][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5598_s1/F |
| 6.430 | 0.099 | tNET | RR | 1 | R14C80[3][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5598_s0/I0 |
| 6.805 | 0.375 | tINS | RR | 2 | R14C80[3][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5598_s0/F |
| 7.043 | 0.238 | tNET | RR | 1 | R14C82[2][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_4_s2/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.250 | 6.250 | active clock edge time | ||||
| 6.250 | 0.000 | pclk | ||||
| 6.250 | 0.000 | tCL | RR | 10163 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK |
| 7.763 | 1.513 | tNET | RR | 1 | R14C82[2][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_4_s2/CLK |
| 7.600 | -0.164 | tSu | 1 | R14C82[2][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_4_s2 |
Path Statistics:
| Clock Skew | -0.007 |
| Setup Relationship | 6.250 |
| Logic Level | 6 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.520, 100.000% |
| Arrival Data Path Delay | cell: 1.750, 31.696%; route: 3.497, 63.318%; tC2Q: 0.275, 4.987% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.513, 100.000% |
Path24
Path Summary:
| Slack | 0.563 |
| Data Arrival Time | 7.036 |
| Data Required Time | 7.600 |
| From | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0 |
| To | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_30_s1 |
| Launch Clk | pclk:[R] |
| Latch Clk | pclk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | pclk | ||||
| 0.000 | 0.000 | tCL | RR | 10163 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK |
| 1.520 | 1.520 | tNET | RR | 1 | R44C83[1][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/CLK |
| 1.795 | 0.275 | tC2Q | RR | 2598 | R44C83[1][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/Q |
| 3.686 | 1.891 | tNET | RR | 1 | R41C84[3][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_lcmd_38_s8/I2 |
| 4.045 | 0.358 | tINS | RR | 2 | R41C84[3][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_lcmd_38_s8/F |
| 4.048 | 0.004 | tNET | RR | 1 | R41C84[0][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5572_s7/I2 |
| 4.427 | 0.379 | tINS | RR | 1 | R41C84[0][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5572_s7/F |
| 5.301 | 0.874 | tNET | RR | 1 | R18C82[1][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5572_s5/I2 |
| 5.490 | 0.189 | tINS | RR | 1 | R18C82[1][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5572_s5/F |
| 5.765 | 0.275 | tNET | RR | 1 | R16C80[2][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5572_s2/I0 |
| 6.144 | 0.379 | tINS | RR | 1 | R16C80[2][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5572_s2/F |
| 6.420 | 0.275 | tNET | RR | 1 | R18C78[2][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5572_s0/I1 |
| 6.799 | 0.379 | tINS | RR | 2 | R18C78[2][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5572_s0/F |
| 7.036 | 0.238 | tNET | RR | 1 | R18C80[0][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_30_s1/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.250 | 6.250 | active clock edge time | ||||
| 6.250 | 0.000 | pclk | ||||
| 6.250 | 0.000 | tCL | RR | 10163 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK |
| 7.763 | 1.513 | tNET | RR | 1 | R18C80[0][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_30_s1/CLK |
| 7.600 | -0.164 | tSu | 1 | R18C80[0][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_30_s1 |
Path Statistics:
| Clock Skew | -0.007 |
| Setup Relationship | 6.250 |
| Logic Level | 6 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.520, 100.000% |
| Arrival Data Path Delay | cell: 1.684, 30.527%; route: 3.557, 64.480%; tC2Q: 0.275, 4.993% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.513, 100.000% |
Path25
Path Summary:
| Slack | 0.570 |
| Data Arrival Time | 7.036 |
| Data Required Time | 7.606 |
| From | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0 |
| To | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_30_s2 |
| Launch Clk | pclk:[R] |
| Latch Clk | pclk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | pclk | ||||
| 0.000 | 0.000 | tCL | RR | 10163 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK |
| 1.520 | 1.520 | tNET | RR | 1 | R44C83[1][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/CLK |
| 1.795 | 0.275 | tC2Q | RR | 2598 | R44C83[1][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/Q |
| 3.686 | 1.891 | tNET | RR | 1 | R41C84[3][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_lcmd_38_s8/I2 |
| 4.045 | 0.358 | tINS | RR | 2 | R41C84[3][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_lcmd_38_s8/F |
| 4.048 | 0.004 | tNET | RR | 1 | R41C84[0][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5572_s7/I2 |
| 4.427 | 0.379 | tINS | RR | 1 | R41C84[0][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5572_s7/F |
| 5.301 | 0.874 | tNET | RR | 1 | R18C82[1][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5572_s5/I2 |
| 5.490 | 0.189 | tINS | RR | 1 | R18C82[1][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5572_s5/F |
| 5.765 | 0.275 | tNET | RR | 1 | R16C80[2][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5572_s2/I0 |
| 6.144 | 0.379 | tINS | RR | 1 | R16C80[2][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5572_s2/F |
| 6.420 | 0.275 | tNET | RR | 1 | R18C78[2][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5572_s0/I1 |
| 6.799 | 0.379 | tINS | RR | 2 | R18C78[2][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5572_s0/F |
| 7.036 | 0.238 | tNET | RR | 1 | R18C79[2][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_30_s2/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.250 | 6.250 | active clock edge time | ||||
| 6.250 | 0.000 | pclk | ||||
| 6.250 | 0.000 | tCL | RR | 10163 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK |
| 7.770 | 1.520 | tNET | RR | 1 | R18C79[2][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_30_s2/CLK |
| 7.606 | -0.164 | tSu | 1 | R18C79[2][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_30_s2 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 6.250 |
| Logic Level | 6 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.520, 100.000% |
| Arrival Data Path Delay | cell: 1.684, 30.527%; route: 3.557, 64.480%; tC2Q: 0.275, 4.993% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.520, 100.000% |
Path26
Path Summary:
| Slack | 0.577 |
| Data Arrival Time | 7.029 |
| Data Required Time | 7.606 |
| From | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0 |
| To | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_22_s1 |
| Launch Clk | pclk:[R] |
| Latch Clk | pclk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | pclk | ||||
| 0.000 | 0.000 | tCL | RR | 10163 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK |
| 1.520 | 1.520 | tNET | RR | 1 | R44C83[1][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/CLK |
| 1.795 | 0.275 | tC2Q | RR | 2598 | R44C83[1][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/Q |
| 3.670 | 1.875 | tNET | RR | 1 | R44C84[0][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_lcmd_14_s8/I2 |
| 3.859 | 0.189 | tINS | RR | 1 | R44C84[0][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_lcmd_14_s8/F |
| 3.974 | 0.115 | tNET | RR | 1 | R44C83[3][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3105_s20/I2 |
| 4.183 | 0.209 | tINS | RF | 2 | R44C83[3][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3105_s20/F |
| 5.312 | 1.129 | tNET | FF | 1 | R18C80[0][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5580_s4/I2 |
| 5.691 | 0.379 | tINS | FR | 1 | R18C80[0][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5580_s4/F |
| 5.693 | 0.002 | tNET | RR | 1 | R18C80[2][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5580_s1/I1 |
| 6.064 | 0.372 | tINS | RR | 1 | R18C80[2][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5580_s1/F |
| 6.398 | 0.334 | tNET | RR | 1 | R20C82[3][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5580_s0/I0 |
| 6.773 | 0.375 | tINS | RR | 2 | R20C82[3][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5580_s0/F |
| 7.029 | 0.256 | tNET | RR | 1 | R20C83[1][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_22_s1/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.250 | 6.250 | active clock edge time | ||||
| 6.250 | 0.000 | pclk | ||||
| 6.250 | 0.000 | tCL | RR | 10163 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK |
| 7.770 | 1.520 | tNET | RR | 1 | R20C83[1][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_22_s1/CLK |
| 7.606 | -0.164 | tSu | 1 | R20C83[1][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_22_s1 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 6.250 |
| Logic Level | 6 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.520, 100.000% |
| Arrival Data Path Delay | cell: 1.524, 27.659%; route: 3.710, 67.342%; tC2Q: 0.275, 4.999% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.520, 100.000% |
Path27
Path Summary:
| Slack | 0.581 |
| Data Arrival Time | 7.018 |
| Data Required Time | 7.600 |
| From | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0 |
| To | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_1_s2 |
| Launch Clk | pclk:[R] |
| Latch Clk | pclk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | pclk | ||||
| 0.000 | 0.000 | tCL | RR | 10163 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK |
| 1.520 | 1.520 | tNET | RR | 1 | R44C83[1][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/CLK |
| 1.795 | 0.275 | tC2Q | RR | 2598 | R44C83[1][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/Q |
| 3.668 | 1.873 | tNET | RR | 1 | R43C80[1][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_lcmd_25_s8/I2 |
| 4.047 | 0.379 | tINS | RR | 1 | R43C80[1][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_lcmd_25_s8/F |
| 4.051 | 0.004 | tNET | RR | 1 | R43C80[3][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3094_s20/I2 |
| 4.260 | 0.209 | tINS | RF | 2 | R43C80[3][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3094_s20/F |
| 5.044 | 0.785 | tNET | FF | 1 | R18C79[3][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5601_s4/I2 |
| 5.420 | 0.375 | tINS | FR | 1 | R18C79[3][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5601_s4/F |
| 5.558 | 0.139 | tNET | RR | 1 | R18C77[2][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5601_s1/I1 |
| 5.937 | 0.379 | tINS | RR | 1 | R18C77[2][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5601_s1/F |
| 6.408 | 0.471 | tNET | RR | 1 | R23C77[3][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5601_s0/I0 |
| 6.766 | 0.358 | tINS | RR | 2 | R23C77[3][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5601_s0/F |
| 7.018 | 0.252 | tNET | RR | 1 | R24C78[2][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_1_s2/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.250 | 6.250 | active clock edge time | ||||
| 6.250 | 0.000 | pclk | ||||
| 6.250 | 0.000 | tCL | RR | 10163 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK |
| 7.763 | 1.513 | tNET | RR | 1 | R24C78[2][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_1_s2/CLK |
| 7.600 | -0.164 | tSu | 1 | R24C78[2][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_1_s2 |
Path Statistics:
| Clock Skew | -0.007 |
| Setup Relationship | 6.250 |
| Logic Level | 6 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.520, 100.000% |
| Arrival Data Path Delay | cell: 1.700, 30.922%; route: 3.523, 64.069%; tC2Q: 0.275, 5.009% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.513, 100.000% |
Path28
Path Summary:
| Slack | 0.610 |
| Data Arrival Time | 6.989 |
| Data Required Time | 7.600 |
| From | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0 |
| To | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_11_s2 |
| Launch Clk | pclk:[R] |
| Latch Clk | pclk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | pclk | ||||
| 0.000 | 0.000 | tCL | RR | 10163 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK |
| 1.520 | 1.520 | tNET | RR | 1 | R44C83[1][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/CLK |
| 1.795 | 0.275 | tC2Q | RR | 2598 | R44C83[1][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/Q |
| 3.690 | 1.895 | tNET | RR | 1 | R40C84[3][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_lcmd_51_s8/I2 |
| 4.048 | 0.358 | tINS | RR | 2 | R40C84[3][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_lcmd_51_s8/F |
| 4.165 | 0.117 | tNET | RR | 1 | R40C83[2][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5591_s7/I2 |
| 4.497 | 0.332 | tINS | RR | 1 | R40C83[2][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5591_s7/F |
| 5.099 | 0.601 | tNET | RR | 1 | R21C82[0][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5591_s5/I2 |
| 5.288 | 0.189 | tINS | RR | 1 | R21C82[0][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5591_s5/F |
| 5.733 | 0.446 | tNET | RR | 1 | R17C82[1][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5591_s2/I0 |
| 6.105 | 0.372 | tINS | RR | 1 | R17C82[1][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5591_s2/F |
| 6.380 | 0.275 | tNET | RR | 1 | R17C78[2][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5591_s0/I1 |
| 6.752 | 0.372 | tINS | RR | 2 | R17C78[2][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5591_s0/F |
| 6.989 | 0.238 | tNET | RR | 1 | R17C80[0][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_11_s2/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.250 | 6.250 | active clock edge time | ||||
| 6.250 | 0.000 | pclk | ||||
| 6.250 | 0.000 | tCL | RR | 10163 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK |
| 7.763 | 1.513 | tNET | RR | 1 | R17C80[0][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_11_s2/CLK |
| 7.600 | -0.164 | tSu | 1 | R17C80[0][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_11_s2 |
Path Statistics:
| Clock Skew | -0.007 |
| Setup Relationship | 6.250 |
| Logic Level | 6 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.520, 100.000% |
| Arrival Data Path Delay | cell: 1.623, 29.669%; route: 3.571, 65.295%; tC2Q: 0.275, 5.035% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.513, 100.000% |
Path29
Path Summary:
| Slack | 0.610 |
| Data Arrival Time | 6.989 |
| Data Required Time | 7.600 |
| From | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0 |
| To | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_11_s1 |
| Launch Clk | pclk:[R] |
| Latch Clk | pclk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | pclk | ||||
| 0.000 | 0.000 | tCL | RR | 10163 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK |
| 1.520 | 1.520 | tNET | RR | 1 | R44C83[1][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/CLK |
| 1.795 | 0.275 | tC2Q | RR | 2598 | R44C83[1][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/Q |
| 3.690 | 1.895 | tNET | RR | 1 | R40C84[3][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_lcmd_51_s8/I2 |
| 4.048 | 0.358 | tINS | RR | 2 | R40C84[3][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_lcmd_51_s8/F |
| 4.165 | 0.117 | tNET | RR | 1 | R40C83[2][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5591_s7/I2 |
| 4.497 | 0.332 | tINS | RR | 1 | R40C83[2][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5591_s7/F |
| 5.099 | 0.601 | tNET | RR | 1 | R21C82[0][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5591_s5/I2 |
| 5.288 | 0.189 | tINS | RR | 1 | R21C82[0][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5591_s5/F |
| 5.733 | 0.446 | tNET | RR | 1 | R17C82[1][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5591_s2/I0 |
| 6.105 | 0.372 | tINS | RR | 1 | R17C82[1][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5591_s2/F |
| 6.380 | 0.275 | tNET | RR | 1 | R17C78[2][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5591_s0/I1 |
| 6.752 | 0.372 | tINS | RR | 2 | R17C78[2][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5591_s0/F |
| 6.989 | 0.238 | tNET | RR | 1 | R17C80[2][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_11_s1/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.250 | 6.250 | active clock edge time | ||||
| 6.250 | 0.000 | pclk | ||||
| 6.250 | 0.000 | tCL | RR | 10163 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK |
| 7.763 | 1.513 | tNET | RR | 1 | R17C80[2][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_11_s1/CLK |
| 7.600 | -0.164 | tSu | 1 | R17C80[2][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_11_s1 |
Path Statistics:
| Clock Skew | -0.007 |
| Setup Relationship | 6.250 |
| Logic Level | 6 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.520, 100.000% |
| Arrival Data Path Delay | cell: 1.623, 29.669%; route: 3.571, 65.295%; tC2Q: 0.275, 5.035% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.513, 100.000% |
Path30
Path Summary:
| Slack | 0.618 |
| Data Arrival Time | 6.975 |
| Data Required Time | 7.593 |
| From | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0 |
| To | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_3_s2 |
| Launch Clk | pclk:[R] |
| Latch Clk | pclk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | pclk | ||||
| 0.000 | 0.000 | tCL | RR | 10163 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK |
| 1.520 | 1.520 | tNET | RR | 1 | R44C83[1][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/CLK |
| 1.795 | 0.275 | tC2Q | RR | 2598 | R44C83[1][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/Q |
| 3.682 | 1.886 | tNET | RR | 1 | R46C82[2][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_lcmd_59_s8/I2 |
| 4.061 | 0.379 | tINS | RR | 2 | R46C82[2][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_lcmd_59_s8/F |
| 4.163 | 0.103 | tNET | RR | 1 | R46C82[2][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5599_s7/I2 |
| 4.352 | 0.189 | tINS | RR | 1 | R46C82[2][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5599_s7/F |
| 5.303 | 0.950 | tNET | RR | 1 | R18C82[2][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5599_s5/I2 |
| 5.492 | 0.189 | tINS | RR | 1 | R18C82[2][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5599_s5/F |
| 5.494 | 0.002 | tNET | RR | 1 | R18C82[3][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5599_s2/I0 |
| 5.852 | 0.358 | tINS | RR | 1 | R18C82[3][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5599_s2/F |
| 6.323 | 0.471 | tNET | RR | 1 | R23C82[3][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5599_s0/I1 |
| 6.698 | 0.375 | tINS | RR | 2 | R23C82[3][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5599_s0/F |
| 6.975 | 0.277 | tNET | RR | 1 | R25C81[1][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_3_s2/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.250 | 6.250 | active clock edge time | ||||
| 6.250 | 0.000 | pclk | ||||
| 6.250 | 0.000 | tCL | RR | 10163 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK |
| 7.757 | 1.507 | tNET | RR | 1 | R25C81[1][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_3_s2/CLK |
| 7.593 | -0.164 | tSu | 1 | R25C81[1][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_3_s2 |
Path Statistics:
| Clock Skew | -0.014 |
| Setup Relationship | 6.250 |
| Logic Level | 6 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.520, 100.000% |
| Arrival Data Path Delay | cell: 1.490, 27.322%; route: 3.689, 67.629%; tC2Q: 0.275, 5.049% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.507, 100.000% |
Path31
Path Summary:
| Slack | 0.618 |
| Data Arrival Time | 6.975 |
| Data Required Time | 7.593 |
| From | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0 |
| To | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_3_s1 |
| Launch Clk | pclk:[R] |
| Latch Clk | pclk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | pclk | ||||
| 0.000 | 0.000 | tCL | RR | 10163 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK |
| 1.520 | 1.520 | tNET | RR | 1 | R44C83[1][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/CLK |
| 1.795 | 0.275 | tC2Q | RR | 2598 | R44C83[1][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/Q |
| 3.682 | 1.886 | tNET | RR | 1 | R46C82[2][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_lcmd_59_s8/I2 |
| 4.061 | 0.379 | tINS | RR | 2 | R46C82[2][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_lcmd_59_s8/F |
| 4.163 | 0.103 | tNET | RR | 1 | R46C82[2][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5599_s7/I2 |
| 4.352 | 0.189 | tINS | RR | 1 | R46C82[2][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5599_s7/F |
| 5.303 | 0.950 | tNET | RR | 1 | R18C82[2][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5599_s5/I2 |
| 5.492 | 0.189 | tINS | RR | 1 | R18C82[2][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5599_s5/F |
| 5.494 | 0.002 | tNET | RR | 1 | R18C82[3][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5599_s2/I0 |
| 5.852 | 0.358 | tINS | RR | 1 | R18C82[3][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5599_s2/F |
| 6.323 | 0.471 | tNET | RR | 1 | R23C82[3][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5599_s0/I1 |
| 6.698 | 0.375 | tINS | RR | 2 | R23C82[3][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5599_s0/F |
| 6.975 | 0.277 | tNET | RR | 1 | R25C81[0][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_3_s1/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.250 | 6.250 | active clock edge time | ||||
| 6.250 | 0.000 | pclk | ||||
| 6.250 | 0.000 | tCL | RR | 10163 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK |
| 7.757 | 1.507 | tNET | RR | 1 | R25C81[0][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_3_s1/CLK |
| 7.593 | -0.164 | tSu | 1 | R25C81[0][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_3_s1 |
Path Statistics:
| Clock Skew | -0.014 |
| Setup Relationship | 6.250 |
| Logic Level | 6 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.520, 100.000% |
| Arrival Data Path Delay | cell: 1.490, 27.322%; route: 3.689, 67.629%; tC2Q: 0.275, 5.049% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.507, 100.000% |
Path32
Path Summary:
| Slack | 0.632 |
| Data Arrival Time | 6.974 |
| Data Required Time | 7.606 |
| From | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0 |
| To | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_14_s1 |
| Launch Clk | pclk:[R] |
| Latch Clk | pclk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | pclk | ||||
| 0.000 | 0.000 | tCL | RR | 10163 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK |
| 1.520 | 1.520 | tNET | RR | 1 | R44C83[1][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/CLK |
| 1.795 | 0.275 | tC2Q | RR | 2598 | R44C83[1][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/Q |
| 3.668 | 1.873 | tNET | RR | 1 | R41C80[0][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_lcmd_54_s8/I2 |
| 4.047 | 0.379 | tINS | RR | 2 | R41C80[0][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_lcmd_54_s8/F |
| 4.189 | 0.142 | tNET | RR | 1 | R41C82[2][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5588_s7/I2 |
| 4.378 | 0.189 | tINS | RR | 1 | R41C82[2][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5588_s7/F |
| 5.071 | 0.692 | tNET | RR | 1 | R18C82[3][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5588_s5/I2 |
| 5.446 | 0.375 | tINS | RR | 1 | R18C82[3][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5588_s5/F |
| 5.696 | 0.250 | tNET | RR | 1 | R15C82[1][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5588_s2/I0 |
| 6.075 | 0.379 | tINS | RR | 1 | R15C82[1][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5588_s2/F |
| 6.350 | 0.275 | tNET | RR | 1 | R15C78[2][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5588_s0/I1 |
| 6.722 | 0.372 | tINS | RR | 2 | R15C78[2][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5588_s0/F |
| 6.974 | 0.252 | tNET | RR | 1 | R14C79[1][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_14_s1/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.250 | 6.250 | active clock edge time | ||||
| 6.250 | 0.000 | pclk | ||||
| 6.250 | 0.000 | tCL | RR | 10163 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK |
| 7.770 | 1.520 | tNET | RR | 1 | R14C79[1][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_14_s1/CLK |
| 7.606 | -0.164 | tSu | 1 | R14C79[1][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_14_s1 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 6.250 |
| Logic Level | 6 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.520, 100.000% |
| Arrival Data Path Delay | cell: 1.694, 31.056%; route: 3.485, 63.894%; tC2Q: 0.275, 5.050% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.520, 100.000% |
Path33
Path Summary:
| Slack | 0.652 |
| Data Arrival Time | 7.072 |
| Data Required Time | 7.724 |
| From | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0 |
| To | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_6_s1 |
| Launch Clk | pclk:[R] |
| Latch Clk | pclk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | pclk | ||||
| 0.000 | 0.000 | tCL | RR | 10163 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK |
| 1.520 | 1.520 | tNET | RR | 1 | R44C83[1][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/CLK |
| 1.795 | 0.275 | tC2Q | RR | 2598 | R44C83[1][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/Q |
| 3.686 | 1.891 | tNET | RR | 1 | R44C84[3][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_lcmd_62_s10/I2 |
| 4.045 | 0.358 | tINS | RR | 2 | R44C84[3][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_lcmd_62_s10/F |
| 4.162 | 0.117 | tNET | RR | 1 | R45C84[3][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5596_s7/I2 |
| 4.460 | 0.299 | tINS | RR | 1 | R45C84[3][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5596_s7/F |
| 5.297 | 0.836 | tNET | RR | 1 | R23C83[3][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5596_s5/I2 |
| 5.487 | 0.191 | tINS | RR | 1 | R23C83[3][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5596_s5/F |
| 5.586 | 0.099 | tNET | RR | 1 | R23C83[1][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5596_s2/I0 |
| 5.958 | 0.372 | tINS | RR | 1 | R23C83[1][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5596_s2/F |
| 6.407 | 0.449 | tNET | RR | 1 | R27C79[3][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5596_s0/I1 |
| 6.782 | 0.375 | tINS | RR | 2 | R27C79[3][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5596_s0/F |
| 7.072 | 0.290 | tNET | RR | 1 | R27C79[0][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_6_s1/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.250 | 6.250 | active clock edge time | ||||
| 6.250 | 0.000 | pclk | ||||
| 6.250 | 0.000 | tCL | RR | 10163 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK |
| 7.770 | 1.520 | tNET | RR | 1 | R27C79[0][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_6_s1/CLK |
| 7.724 | -0.046 | tSu | 1 | R27C79[0][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_6_s1 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 6.250 |
| Logic Level | 6 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.520, 100.000% |
| Arrival Data Path Delay | cell: 1.595, 28.724%; route: 3.682, 66.315%; tC2Q: 0.275, 4.960% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.520, 100.000% |
Path34
Path Summary:
| Slack | 0.659 |
| Data Arrival Time | 7.065 |
| Data Required Time | 7.724 |
| From | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_word_alignment/data_in_r0_3_s0 |
| To | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_word_alignment/lock_s0 |
| Launch Clk | q0_lane1_fabric_rx_clk:[R] |
| Latch Clk | q0_lane1_fabric_rx_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | q0_lane1_fabric_rx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 518 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_RX_O_FABRIC_CLK |
| 1.513 | 1.513 | tNET | RR | 1 | R25C81[3][A] | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_word_alignment/data_in_r0_3_s0/CLK |
| 1.789 | 0.275 | tC2Q | RR | 13 | R25C81[3][A] | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_word_alignment/data_in_r0_3_s0/Q |
| 2.392 | 0.603 | tNET | RR | 1 | R27C80[3][B] | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_word_alignment/cnt0_3_s61/I0 |
| 2.691 | 0.299 | tINS | RR | 2 | R27C80[3][B] | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_word_alignment/cnt0_3_s61/F |
| 2.806 | 0.115 | tNET | RR | 1 | R26C80[1][A] | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_word_alignment/cnt0_3_s58/I3 |
| 3.177 | 0.372 | tINS | RR | 2 | R26C80[1][A] | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_word_alignment/cnt0_3_s58/F |
| 3.728 | 0.551 | tNET | RR | 1 | R25C81[0][B] | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_word_alignment/cnt0_3_s27/I1 |
| 4.100 | 0.372 | tINS | RR | 2 | R25C81[0][B] | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_word_alignment/cnt0_3_s27/F |
| 4.798 | 0.698 | tNET | RR | 1 | R25C82[2][B] | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_word_alignment/cnt0_3_s10/I2 |
| 5.170 | 0.372 | tINS | RR | 2 | R25C82[2][B] | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_word_alignment/cnt0_3_s10/F |
| 5.732 | 0.562 | tNET | RR | 1 | R25C82[3][A] | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_word_alignment/cnt0_3_s4/I3 |
| 5.940 | 0.209 | tINS | RF | 2 | R25C82[3][A] | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_word_alignment/cnt0_3_s4/F |
| 6.200 | 0.259 | tNET | FF | 1 | R25C84[3][A] | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_word_alignment/cnt0_3_s3/I0 |
| 6.498 | 0.299 | tINS | FR | 5 | R25C84[3][A] | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_word_alignment/cnt0_3_s3/F |
| 7.065 | 0.567 | tNET | RR | 1 | R27C86[0][A] | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_word_alignment/lock_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.250 | 6.250 | active clock edge time | ||||
| 6.250 | 0.000 | q0_lane1_fabric_rx_clk | ||||
| 6.250 | 0.000 | tCL | RR | 518 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_RX_O_FABRIC_CLK |
| 7.770 | 1.520 | tNET | RR | 1 | R27C86[0][A] | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_word_alignment/lock_s0/CLK |
| 7.724 | -0.046 | tSu | 1 | R27C86[0][A] | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_word_alignment/lock_s0 |
Path Statistics:
| Clock Skew | 0.007 |
| Setup Relationship | 6.250 |
| Logic Level | 7 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.513, 100.000% |
| Arrival Data Path Delay | cell: 1.921, 34.609%; route: 3.355, 60.431%; tC2Q: 0.275, 4.960% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.520, 100.000% |
Path35
Path Summary:
| Slack | 0.679 |
| Data Arrival Time | 6.867 |
| Data Required Time | 7.546 |
| From | UserLayer_top_inst/ControlTransfer_inst/wValue_latch_9_s0 |
| To | UserLayer_top_inst/ControlTransfer_inst/bmHint_2_s0 |
| Launch Clk | pclk:[R] |
| Latch Clk | pclk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | pclk | ||||
| 0.000 | 0.000 | tCL | RR | 10163 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK |
| 1.513 | 1.513 | tNET | RR | 1 | R68C39[1][B] | UserLayer_top_inst/ControlTransfer_inst/wValue_latch_9_s0/CLK |
| 1.789 | 0.275 | tC2Q | RR | 7 | R68C39[1][B] | UserLayer_top_inst/ControlTransfer_inst/wValue_latch_9_s0/Q |
| 2.046 | 0.257 | tNET | RR | 1 | R69C41[2][A] | UserLayer_top_inst/ControlTransfer_inst/n4511_s21/I3 |
| 2.418 | 0.372 | tINS | RR | 10 | R69C41[2][A] | UserLayer_top_inst/ControlTransfer_inst/n4511_s21/F |
| 2.888 | 0.470 | tNET | RR | 1 | R70C47[3][B] | UserLayer_top_inst/ControlTransfer_inst/n4511_s17/I1 |
| 3.263 | 0.375 | tINS | RR | 11 | R70C47[3][B] | UserLayer_top_inst/ControlTransfer_inst/n4511_s17/F |
| 3.609 | 0.346 | tNET | RR | 1 | R70C40[3][B] | UserLayer_top_inst/ControlTransfer_inst/n688_s28/I3 |
| 3.985 | 0.375 | tINS | RR | 6 | R70C40[3][B] | UserLayer_top_inst/ControlTransfer_inst/n688_s28/F |
| 4.329 | 0.344 | tNET | RR | 1 | R64C40[3][B] | UserLayer_top_inst/ControlTransfer_inst/n6333_s3/I1 |
| 4.704 | 0.375 | tINS | RR | 5 | R64C40[3][B] | UserLayer_top_inst/ControlTransfer_inst/n6333_s3/F |
| 4.959 | 0.256 | tNET | RR | 1 | R63C38[3][B] | UserLayer_top_inst/ControlTransfer_inst/n6333_s5/I2 |
| 5.335 | 0.375 | tINS | RR | 64 | R63C38[3][B] | UserLayer_top_inst/ControlTransfer_inst/n6333_s5/F |
| 6.867 | 1.532 | tNET | RR | 1 | R66C46[2][B] | UserLayer_top_inst/ControlTransfer_inst/bmHint_2_s0/CE |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.250 | 6.250 | active clock edge time | ||||
| 6.250 | 0.000 | pclk | ||||
| 6.250 | 0.000 | tCL | RR | 10163 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK |
| 7.770 | 1.520 | tNET | RR | 1 | R66C46[2][B] | UserLayer_top_inst/ControlTransfer_inst/bmHint_2_s0/CLK |
| 7.546 | -0.224 | tSu | 1 | R66C46[2][B] | UserLayer_top_inst/ControlTransfer_inst/bmHint_2_s0 |
Path Statistics:
| Clock Skew | 0.007 |
| Setup Relationship | 6.250 |
| Logic Level | 6 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.513, 100.000% |
| Arrival Data Path Delay | cell: 1.873, 34.987%; route: 3.205, 59.869%; tC2Q: 0.275, 5.145% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.520, 100.000% |
Path36
Path Summary:
| Slack | 0.679 |
| Data Arrival Time | 6.867 |
| Data Required Time | 7.546 |
| From | UserLayer_top_inst/ControlTransfer_inst/wValue_latch_9_s0 |
| To | UserLayer_top_inst/ControlTransfer_inst/bmHint_6_s0 |
| Launch Clk | pclk:[R] |
| Latch Clk | pclk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | pclk | ||||
| 0.000 | 0.000 | tCL | RR | 10163 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK |
| 1.513 | 1.513 | tNET | RR | 1 | R68C39[1][B] | UserLayer_top_inst/ControlTransfer_inst/wValue_latch_9_s0/CLK |
| 1.789 | 0.275 | tC2Q | RR | 7 | R68C39[1][B] | UserLayer_top_inst/ControlTransfer_inst/wValue_latch_9_s0/Q |
| 2.046 | 0.257 | tNET | RR | 1 | R69C41[2][A] | UserLayer_top_inst/ControlTransfer_inst/n4511_s21/I3 |
| 2.418 | 0.372 | tINS | RR | 10 | R69C41[2][A] | UserLayer_top_inst/ControlTransfer_inst/n4511_s21/F |
| 2.888 | 0.470 | tNET | RR | 1 | R70C47[3][B] | UserLayer_top_inst/ControlTransfer_inst/n4511_s17/I1 |
| 3.263 | 0.375 | tINS | RR | 11 | R70C47[3][B] | UserLayer_top_inst/ControlTransfer_inst/n4511_s17/F |
| 3.609 | 0.346 | tNET | RR | 1 | R70C40[3][B] | UserLayer_top_inst/ControlTransfer_inst/n688_s28/I3 |
| 3.985 | 0.375 | tINS | RR | 6 | R70C40[3][B] | UserLayer_top_inst/ControlTransfer_inst/n688_s28/F |
| 4.329 | 0.344 | tNET | RR | 1 | R64C40[3][B] | UserLayer_top_inst/ControlTransfer_inst/n6333_s3/I1 |
| 4.704 | 0.375 | tINS | RR | 5 | R64C40[3][B] | UserLayer_top_inst/ControlTransfer_inst/n6333_s3/F |
| 4.959 | 0.256 | tNET | RR | 1 | R63C38[3][B] | UserLayer_top_inst/ControlTransfer_inst/n6333_s5/I2 |
| 5.335 | 0.375 | tINS | RR | 64 | R63C38[3][B] | UserLayer_top_inst/ControlTransfer_inst/n6333_s5/F |
| 6.867 | 1.532 | tNET | RR | 1 | R66C46[3][A] | UserLayer_top_inst/ControlTransfer_inst/bmHint_6_s0/CE |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.250 | 6.250 | active clock edge time | ||||
| 6.250 | 0.000 | pclk | ||||
| 6.250 | 0.000 | tCL | RR | 10163 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK |
| 7.770 | 1.520 | tNET | RR | 1 | R66C46[3][A] | UserLayer_top_inst/ControlTransfer_inst/bmHint_6_s0/CLK |
| 7.546 | -0.224 | tSu | 1 | R66C46[3][A] | UserLayer_top_inst/ControlTransfer_inst/bmHint_6_s0 |
Path Statistics:
| Clock Skew | 0.007 |
| Setup Relationship | 6.250 |
| Logic Level | 6 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.513, 100.000% |
| Arrival Data Path Delay | cell: 1.873, 34.987%; route: 3.205, 59.869%; tC2Q: 0.275, 5.145% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.520, 100.000% |
Path37
Path Summary:
| Slack | 0.693 |
| Data Arrival Time | 6.907 |
| Data Required Time | 7.600 |
| From | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0 |
| To | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_1_s1 |
| Launch Clk | pclk:[R] |
| Latch Clk | pclk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | pclk | ||||
| 0.000 | 0.000 | tCL | RR | 10163 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK |
| 1.520 | 1.520 | tNET | RR | 1 | R44C83[1][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/CLK |
| 1.795 | 0.275 | tC2Q | RR | 2598 | R44C83[1][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/Q |
| 3.668 | 1.873 | tNET | RR | 1 | R43C80[1][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_lcmd_25_s8/I2 |
| 4.047 | 0.379 | tINS | RR | 1 | R43C80[1][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_lcmd_25_s8/F |
| 4.051 | 0.004 | tNET | RR | 1 | R43C80[3][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3094_s20/I2 |
| 4.260 | 0.209 | tINS | RF | 2 | R43C80[3][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3094_s20/F |
| 5.044 | 0.785 | tNET | FF | 1 | R18C79[3][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5601_s4/I2 |
| 5.420 | 0.375 | tINS | FR | 1 | R18C79[3][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5601_s4/F |
| 5.558 | 0.139 | tNET | RR | 1 | R18C77[2][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5601_s1/I1 |
| 5.937 | 0.379 | tINS | RR | 1 | R18C77[2][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5601_s1/F |
| 6.408 | 0.471 | tNET | RR | 1 | R23C77[3][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5601_s0/I0 |
| 6.766 | 0.358 | tINS | RR | 2 | R23C77[3][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5601_s0/F |
| 6.907 | 0.140 | tNET | RR | 1 | R23C78[2][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_1_s1/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.250 | 6.250 | active clock edge time | ||||
| 6.250 | 0.000 | pclk | ||||
| 6.250 | 0.000 | tCL | RR | 10163 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK |
| 7.763 | 1.513 | tNET | RR | 1 | R23C78[2][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_1_s1/CLK |
| 7.600 | -0.164 | tSu | 1 | R23C78[2][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_1_s1 |
Path Statistics:
| Clock Skew | -0.007 |
| Setup Relationship | 6.250 |
| Logic Level | 6 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.520, 100.000% |
| Arrival Data Path Delay | cell: 1.700, 31.562%; route: 3.411, 63.325%; tC2Q: 0.275, 5.113% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.513, 100.000% |
Path38
Path Summary:
| Slack | 0.752 |
| Data Arrival Time | 6.787 |
| Data Required Time | 7.539 |
| From | UserLayer_top_inst/ControlTransfer_inst/wValue_latch_9_s0 |
| To | UserLayer_top_inst/ControlTransfer_inst/dwMaxVideoFrameSize_10_s0 |
| Launch Clk | pclk:[R] |
| Latch Clk | pclk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | pclk | ||||
| 0.000 | 0.000 | tCL | RR | 10163 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK |
| 1.513 | 1.513 | tNET | RR | 1 | R68C39[1][B] | UserLayer_top_inst/ControlTransfer_inst/wValue_latch_9_s0/CLK |
| 1.789 | 0.275 | tC2Q | RR | 7 | R68C39[1][B] | UserLayer_top_inst/ControlTransfer_inst/wValue_latch_9_s0/Q |
| 2.046 | 0.257 | tNET | RR | 1 | R69C41[2][A] | UserLayer_top_inst/ControlTransfer_inst/n4511_s21/I3 |
| 2.418 | 0.372 | tINS | RR | 10 | R69C41[2][A] | UserLayer_top_inst/ControlTransfer_inst/n4511_s21/F |
| 2.888 | 0.470 | tNET | RR | 1 | R70C47[3][B] | UserLayer_top_inst/ControlTransfer_inst/n4511_s17/I1 |
| 3.263 | 0.375 | tINS | RR | 11 | R70C47[3][B] | UserLayer_top_inst/ControlTransfer_inst/n4511_s17/F |
| 3.609 | 0.346 | tNET | RR | 1 | R70C40[3][B] | UserLayer_top_inst/ControlTransfer_inst/n688_s28/I3 |
| 3.985 | 0.375 | tINS | RR | 6 | R70C40[3][B] | UserLayer_top_inst/ControlTransfer_inst/n688_s28/F |
| 4.329 | 0.344 | tNET | RR | 1 | R64C40[3][B] | UserLayer_top_inst/ControlTransfer_inst/n6333_s3/I1 |
| 4.704 | 0.375 | tINS | RR | 5 | R64C40[3][B] | UserLayer_top_inst/ControlTransfer_inst/n6333_s3/F |
| 4.983 | 0.279 | tNET | RR | 1 | R62C38[3][B] | UserLayer_top_inst/ControlTransfer_inst/n6461_s1/I2 |
| 5.358 | 0.375 | tINS | RR | 48 | R62C38[3][B] | UserLayer_top_inst/ControlTransfer_inst/n6461_s1/F |
| 6.787 | 1.429 | tNET | RR | 1 | R62C51[2][B] | UserLayer_top_inst/ControlTransfer_inst/dwMaxVideoFrameSize_10_s0/CE |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.250 | 6.250 | active clock edge time | ||||
| 6.250 | 0.000 | pclk | ||||
| 6.250 | 0.000 | tCL | RR | 10163 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK |
| 7.763 | 1.513 | tNET | RR | 1 | R62C51[2][B] | UserLayer_top_inst/ControlTransfer_inst/dwMaxVideoFrameSize_10_s0/CLK |
| 7.539 | -0.224 | tSu | 1 | R62C51[2][B] | UserLayer_top_inst/ControlTransfer_inst/dwMaxVideoFrameSize_10_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 6.250 |
| Logic Level | 6 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.513, 100.000% |
| Arrival Data Path Delay | cell: 1.873, 35.512%; route: 3.126, 59.266%; tC2Q: 0.275, 5.222% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.513, 100.000% |
Path39
Path Summary:
| Slack | 0.752 |
| Data Arrival Time | 6.787 |
| Data Required Time | 7.539 |
| From | UserLayer_top_inst/ControlTransfer_inst/wValue_latch_9_s0 |
| To | UserLayer_top_inst/ControlTransfer_inst/dwMaxVideoFrameSize_11_s0 |
| Launch Clk | pclk:[R] |
| Latch Clk | pclk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | pclk | ||||
| 0.000 | 0.000 | tCL | RR | 10163 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK |
| 1.513 | 1.513 | tNET | RR | 1 | R68C39[1][B] | UserLayer_top_inst/ControlTransfer_inst/wValue_latch_9_s0/CLK |
| 1.789 | 0.275 | tC2Q | RR | 7 | R68C39[1][B] | UserLayer_top_inst/ControlTransfer_inst/wValue_latch_9_s0/Q |
| 2.046 | 0.257 | tNET | RR | 1 | R69C41[2][A] | UserLayer_top_inst/ControlTransfer_inst/n4511_s21/I3 |
| 2.418 | 0.372 | tINS | RR | 10 | R69C41[2][A] | UserLayer_top_inst/ControlTransfer_inst/n4511_s21/F |
| 2.888 | 0.470 | tNET | RR | 1 | R70C47[3][B] | UserLayer_top_inst/ControlTransfer_inst/n4511_s17/I1 |
| 3.263 | 0.375 | tINS | RR | 11 | R70C47[3][B] | UserLayer_top_inst/ControlTransfer_inst/n4511_s17/F |
| 3.609 | 0.346 | tNET | RR | 1 | R70C40[3][B] | UserLayer_top_inst/ControlTransfer_inst/n688_s28/I3 |
| 3.985 | 0.375 | tINS | RR | 6 | R70C40[3][B] | UserLayer_top_inst/ControlTransfer_inst/n688_s28/F |
| 4.329 | 0.344 | tNET | RR | 1 | R64C40[3][B] | UserLayer_top_inst/ControlTransfer_inst/n6333_s3/I1 |
| 4.704 | 0.375 | tINS | RR | 5 | R64C40[3][B] | UserLayer_top_inst/ControlTransfer_inst/n6333_s3/F |
| 4.983 | 0.279 | tNET | RR | 1 | R62C38[3][B] | UserLayer_top_inst/ControlTransfer_inst/n6461_s1/I2 |
| 5.358 | 0.375 | tINS | RR | 48 | R62C38[3][B] | UserLayer_top_inst/ControlTransfer_inst/n6461_s1/F |
| 6.787 | 1.429 | tNET | RR | 1 | R63C51[1][B] | UserLayer_top_inst/ControlTransfer_inst/dwMaxVideoFrameSize_11_s0/CE |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.250 | 6.250 | active clock edge time | ||||
| 6.250 | 0.000 | pclk | ||||
| 6.250 | 0.000 | tCL | RR | 10163 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK |
| 7.763 | 1.513 | tNET | RR | 1 | R63C51[1][B] | UserLayer_top_inst/ControlTransfer_inst/dwMaxVideoFrameSize_11_s0/CLK |
| 7.539 | -0.224 | tSu | 1 | R63C51[1][B] | UserLayer_top_inst/ControlTransfer_inst/dwMaxVideoFrameSize_11_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 6.250 |
| Logic Level | 6 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.513, 100.000% |
| Arrival Data Path Delay | cell: 1.873, 35.512%; route: 3.126, 59.266%; tC2Q: 0.275, 5.222% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.513, 100.000% |
Path40
Path Summary:
| Slack | 0.752 |
| Data Arrival Time | 6.787 |
| Data Required Time | 7.539 |
| From | UserLayer_top_inst/ControlTransfer_inst/wValue_latch_9_s0 |
| To | UserLayer_top_inst/ControlTransfer_inst/dwMaxVideoFrameSize_12_s0 |
| Launch Clk | pclk:[R] |
| Latch Clk | pclk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | pclk | ||||
| 0.000 | 0.000 | tCL | RR | 10163 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK |
| 1.513 | 1.513 | tNET | RR | 1 | R68C39[1][B] | UserLayer_top_inst/ControlTransfer_inst/wValue_latch_9_s0/CLK |
| 1.789 | 0.275 | tC2Q | RR | 7 | R68C39[1][B] | UserLayer_top_inst/ControlTransfer_inst/wValue_latch_9_s0/Q |
| 2.046 | 0.257 | tNET | RR | 1 | R69C41[2][A] | UserLayer_top_inst/ControlTransfer_inst/n4511_s21/I3 |
| 2.418 | 0.372 | tINS | RR | 10 | R69C41[2][A] | UserLayer_top_inst/ControlTransfer_inst/n4511_s21/F |
| 2.888 | 0.470 | tNET | RR | 1 | R70C47[3][B] | UserLayer_top_inst/ControlTransfer_inst/n4511_s17/I1 |
| 3.263 | 0.375 | tINS | RR | 11 | R70C47[3][B] | UserLayer_top_inst/ControlTransfer_inst/n4511_s17/F |
| 3.609 | 0.346 | tNET | RR | 1 | R70C40[3][B] | UserLayer_top_inst/ControlTransfer_inst/n688_s28/I3 |
| 3.985 | 0.375 | tINS | RR | 6 | R70C40[3][B] | UserLayer_top_inst/ControlTransfer_inst/n688_s28/F |
| 4.329 | 0.344 | tNET | RR | 1 | R64C40[3][B] | UserLayer_top_inst/ControlTransfer_inst/n6333_s3/I1 |
| 4.704 | 0.375 | tINS | RR | 5 | R64C40[3][B] | UserLayer_top_inst/ControlTransfer_inst/n6333_s3/F |
| 4.983 | 0.279 | tNET | RR | 1 | R62C38[3][B] | UserLayer_top_inst/ControlTransfer_inst/n6461_s1/I2 |
| 5.358 | 0.375 | tINS | RR | 48 | R62C38[3][B] | UserLayer_top_inst/ControlTransfer_inst/n6461_s1/F |
| 6.787 | 1.429 | tNET | RR | 1 | R63C51[1][A] | UserLayer_top_inst/ControlTransfer_inst/dwMaxVideoFrameSize_12_s0/CE |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.250 | 6.250 | active clock edge time | ||||
| 6.250 | 0.000 | pclk | ||||
| 6.250 | 0.000 | tCL | RR | 10163 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK |
| 7.763 | 1.513 | tNET | RR | 1 | R63C51[1][A] | UserLayer_top_inst/ControlTransfer_inst/dwMaxVideoFrameSize_12_s0/CLK |
| 7.539 | -0.224 | tSu | 1 | R63C51[1][A] | UserLayer_top_inst/ControlTransfer_inst/dwMaxVideoFrameSize_12_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 6.250 |
| Logic Level | 6 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.513, 100.000% |
| Arrival Data Path Delay | cell: 1.873, 35.512%; route: 3.126, 59.266%; tC2Q: 0.275, 5.222% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.513, 100.000% |
Path41
Path Summary:
| Slack | 0.752 |
| Data Arrival Time | 6.794 |
| Data Required Time | 7.546 |
| From | UserLayer_top_inst/ControlTransfer_inst/wValue_latch_9_s0 |
| To | UserLayer_top_inst/ControlTransfer_inst/dwFrameInterval_25_s0 |
| Launch Clk | pclk:[R] |
| Latch Clk | pclk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | pclk | ||||
| 0.000 | 0.000 | tCL | RR | 10163 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK |
| 1.513 | 1.513 | tNET | RR | 1 | R68C39[1][B] | UserLayer_top_inst/ControlTransfer_inst/wValue_latch_9_s0/CLK |
| 1.789 | 0.275 | tC2Q | RR | 7 | R68C39[1][B] | UserLayer_top_inst/ControlTransfer_inst/wValue_latch_9_s0/Q |
| 2.046 | 0.257 | tNET | RR | 1 | R69C41[2][A] | UserLayer_top_inst/ControlTransfer_inst/n4511_s21/I3 |
| 2.418 | 0.372 | tINS | RR | 10 | R69C41[2][A] | UserLayer_top_inst/ControlTransfer_inst/n4511_s21/F |
| 2.888 | 0.470 | tNET | RR | 1 | R70C47[3][B] | UserLayer_top_inst/ControlTransfer_inst/n4511_s17/I1 |
| 3.263 | 0.375 | tINS | RR | 11 | R70C47[3][B] | UserLayer_top_inst/ControlTransfer_inst/n4511_s17/F |
| 3.609 | 0.346 | tNET | RR | 1 | R70C40[3][B] | UserLayer_top_inst/ControlTransfer_inst/n688_s28/I3 |
| 3.985 | 0.375 | tINS | RR | 6 | R70C40[3][B] | UserLayer_top_inst/ControlTransfer_inst/n688_s28/F |
| 4.329 | 0.344 | tNET | RR | 1 | R64C40[3][B] | UserLayer_top_inst/ControlTransfer_inst/n6333_s3/I1 |
| 4.704 | 0.375 | tINS | RR | 5 | R64C40[3][B] | UserLayer_top_inst/ControlTransfer_inst/n6333_s3/F |
| 4.959 | 0.256 | tNET | RR | 1 | R63C38[3][B] | UserLayer_top_inst/ControlTransfer_inst/n6333_s5/I2 |
| 5.335 | 0.375 | tINS | RR | 64 | R63C38[3][B] | UserLayer_top_inst/ControlTransfer_inst/n6333_s5/F |
| 6.794 | 1.459 | tNET | RR | 1 | R59C42[3][A] | UserLayer_top_inst/ControlTransfer_inst/dwFrameInterval_25_s0/CE |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.250 | 6.250 | active clock edge time | ||||
| 6.250 | 0.000 | pclk | ||||
| 6.250 | 0.000 | tCL | RR | 10163 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK |
| 7.770 | 1.520 | tNET | RR | 1 | R59C42[3][A] | UserLayer_top_inst/ControlTransfer_inst/dwFrameInterval_25_s0/CLK |
| 7.546 | -0.224 | tSu | 1 | R59C42[3][A] | UserLayer_top_inst/ControlTransfer_inst/dwFrameInterval_25_s0 |
Path Statistics:
| Clock Skew | 0.007 |
| Setup Relationship | 6.250 |
| Logic Level | 6 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.513, 100.000% |
| Arrival Data Path Delay | cell: 1.873, 35.470%; route: 3.132, 59.315%; tC2Q: 0.275, 5.216% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.520, 100.000% |
Path42
Path Summary:
| Slack | 0.752 |
| Data Arrival Time | 6.794 |
| Data Required Time | 7.546 |
| From | UserLayer_top_inst/ControlTransfer_inst/wValue_latch_9_s0 |
| To | UserLayer_top_inst/ControlTransfer_inst/dwFrameInterval_29_s0 |
| Launch Clk | pclk:[R] |
| Latch Clk | pclk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | pclk | ||||
| 0.000 | 0.000 | tCL | RR | 10163 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK |
| 1.513 | 1.513 | tNET | RR | 1 | R68C39[1][B] | UserLayer_top_inst/ControlTransfer_inst/wValue_latch_9_s0/CLK |
| 1.789 | 0.275 | tC2Q | RR | 7 | R68C39[1][B] | UserLayer_top_inst/ControlTransfer_inst/wValue_latch_9_s0/Q |
| 2.046 | 0.257 | tNET | RR | 1 | R69C41[2][A] | UserLayer_top_inst/ControlTransfer_inst/n4511_s21/I3 |
| 2.418 | 0.372 | tINS | RR | 10 | R69C41[2][A] | UserLayer_top_inst/ControlTransfer_inst/n4511_s21/F |
| 2.888 | 0.470 | tNET | RR | 1 | R70C47[3][B] | UserLayer_top_inst/ControlTransfer_inst/n4511_s17/I1 |
| 3.263 | 0.375 | tINS | RR | 11 | R70C47[3][B] | UserLayer_top_inst/ControlTransfer_inst/n4511_s17/F |
| 3.609 | 0.346 | tNET | RR | 1 | R70C40[3][B] | UserLayer_top_inst/ControlTransfer_inst/n688_s28/I3 |
| 3.985 | 0.375 | tINS | RR | 6 | R70C40[3][B] | UserLayer_top_inst/ControlTransfer_inst/n688_s28/F |
| 4.329 | 0.344 | tNET | RR | 1 | R64C40[3][B] | UserLayer_top_inst/ControlTransfer_inst/n6333_s3/I1 |
| 4.704 | 0.375 | tINS | RR | 5 | R64C40[3][B] | UserLayer_top_inst/ControlTransfer_inst/n6333_s3/F |
| 4.959 | 0.256 | tNET | RR | 1 | R63C38[3][B] | UserLayer_top_inst/ControlTransfer_inst/n6333_s5/I2 |
| 5.335 | 0.375 | tINS | RR | 64 | R63C38[3][B] | UserLayer_top_inst/ControlTransfer_inst/n6333_s5/F |
| 6.794 | 1.459 | tNET | RR | 1 | R59C42[2][B] | UserLayer_top_inst/ControlTransfer_inst/dwFrameInterval_29_s0/CE |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.250 | 6.250 | active clock edge time | ||||
| 6.250 | 0.000 | pclk | ||||
| 6.250 | 0.000 | tCL | RR | 10163 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK |
| 7.770 | 1.520 | tNET | RR | 1 | R59C42[2][B] | UserLayer_top_inst/ControlTransfer_inst/dwFrameInterval_29_s0/CLK |
| 7.546 | -0.224 | tSu | 1 | R59C42[2][B] | UserLayer_top_inst/ControlTransfer_inst/dwFrameInterval_29_s0 |
Path Statistics:
| Clock Skew | 0.007 |
| Setup Relationship | 6.250 |
| Logic Level | 6 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.513, 100.000% |
| Arrival Data Path Delay | cell: 1.873, 35.470%; route: 3.132, 59.315%; tC2Q: 0.275, 5.216% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.520, 100.000% |
Path43
Path Summary:
| Slack | 0.759 |
| Data Arrival Time | 6.787 |
| Data Required Time | 7.546 |
| From | UserLayer_top_inst/ControlTransfer_inst/wValue_latch_9_s0 |
| To | UserLayer_top_inst/ControlTransfer_inst/dwMaxVideoFrameSize_9_s0 |
| Launch Clk | pclk:[R] |
| Latch Clk | pclk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | pclk | ||||
| 0.000 | 0.000 | tCL | RR | 10163 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK |
| 1.513 | 1.513 | tNET | RR | 1 | R68C39[1][B] | UserLayer_top_inst/ControlTransfer_inst/wValue_latch_9_s0/CLK |
| 1.789 | 0.275 | tC2Q | RR | 7 | R68C39[1][B] | UserLayer_top_inst/ControlTransfer_inst/wValue_latch_9_s0/Q |
| 2.046 | 0.257 | tNET | RR | 1 | R69C41[2][A] | UserLayer_top_inst/ControlTransfer_inst/n4511_s21/I3 |
| 2.418 | 0.372 | tINS | RR | 10 | R69C41[2][A] | UserLayer_top_inst/ControlTransfer_inst/n4511_s21/F |
| 2.888 | 0.470 | tNET | RR | 1 | R70C47[3][B] | UserLayer_top_inst/ControlTransfer_inst/n4511_s17/I1 |
| 3.263 | 0.375 | tINS | RR | 11 | R70C47[3][B] | UserLayer_top_inst/ControlTransfer_inst/n4511_s17/F |
| 3.609 | 0.346 | tNET | RR | 1 | R70C40[3][B] | UserLayer_top_inst/ControlTransfer_inst/n688_s28/I3 |
| 3.985 | 0.375 | tINS | RR | 6 | R70C40[3][B] | UserLayer_top_inst/ControlTransfer_inst/n688_s28/F |
| 4.329 | 0.344 | tNET | RR | 1 | R64C40[3][B] | UserLayer_top_inst/ControlTransfer_inst/n6333_s3/I1 |
| 4.704 | 0.375 | tINS | RR | 5 | R64C40[3][B] | UserLayer_top_inst/ControlTransfer_inst/n6333_s3/F |
| 4.983 | 0.279 | tNET | RR | 1 | R62C38[3][B] | UserLayer_top_inst/ControlTransfer_inst/n6461_s1/I2 |
| 5.358 | 0.375 | tINS | RR | 48 | R62C38[3][B] | UserLayer_top_inst/ControlTransfer_inst/n6461_s1/F |
| 6.787 | 1.429 | tNET | RR | 1 | R63C50[0][A] | UserLayer_top_inst/ControlTransfer_inst/dwMaxVideoFrameSize_9_s0/CE |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.250 | 6.250 | active clock edge time | ||||
| 6.250 | 0.000 | pclk | ||||
| 6.250 | 0.000 | tCL | RR | 10163 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK |
| 7.770 | 1.520 | tNET | RR | 1 | R63C50[0][A] | UserLayer_top_inst/ControlTransfer_inst/dwMaxVideoFrameSize_9_s0/CLK |
| 7.546 | -0.224 | tSu | 1 | R63C50[0][A] | UserLayer_top_inst/ControlTransfer_inst/dwMaxVideoFrameSize_9_s0 |
Path Statistics:
| Clock Skew | 0.007 |
| Setup Relationship | 6.250 |
| Logic Level | 6 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.513, 100.000% |
| Arrival Data Path Delay | cell: 1.873, 35.512%; route: 3.126, 59.266%; tC2Q: 0.275, 5.222% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.520, 100.000% |
Path44
Path Summary:
| Slack | 0.759 |
| Data Arrival Time | 6.787 |
| Data Required Time | 7.546 |
| From | UserLayer_top_inst/ControlTransfer_inst/wValue_latch_9_s0 |
| To | UserLayer_top_inst/ControlTransfer_inst/dwMaxVideoFrameSize_13_s0 |
| Launch Clk | pclk:[R] |
| Latch Clk | pclk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | pclk | ||||
| 0.000 | 0.000 | tCL | RR | 10163 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK |
| 1.513 | 1.513 | tNET | RR | 1 | R68C39[1][B] | UserLayer_top_inst/ControlTransfer_inst/wValue_latch_9_s0/CLK |
| 1.789 | 0.275 | tC2Q | RR | 7 | R68C39[1][B] | UserLayer_top_inst/ControlTransfer_inst/wValue_latch_9_s0/Q |
| 2.046 | 0.257 | tNET | RR | 1 | R69C41[2][A] | UserLayer_top_inst/ControlTransfer_inst/n4511_s21/I3 |
| 2.418 | 0.372 | tINS | RR | 10 | R69C41[2][A] | UserLayer_top_inst/ControlTransfer_inst/n4511_s21/F |
| 2.888 | 0.470 | tNET | RR | 1 | R70C47[3][B] | UserLayer_top_inst/ControlTransfer_inst/n4511_s17/I1 |
| 3.263 | 0.375 | tINS | RR | 11 | R70C47[3][B] | UserLayer_top_inst/ControlTransfer_inst/n4511_s17/F |
| 3.609 | 0.346 | tNET | RR | 1 | R70C40[3][B] | UserLayer_top_inst/ControlTransfer_inst/n688_s28/I3 |
| 3.985 | 0.375 | tINS | RR | 6 | R70C40[3][B] | UserLayer_top_inst/ControlTransfer_inst/n688_s28/F |
| 4.329 | 0.344 | tNET | RR | 1 | R64C40[3][B] | UserLayer_top_inst/ControlTransfer_inst/n6333_s3/I1 |
| 4.704 | 0.375 | tINS | RR | 5 | R64C40[3][B] | UserLayer_top_inst/ControlTransfer_inst/n6333_s3/F |
| 4.983 | 0.279 | tNET | RR | 1 | R62C38[3][B] | UserLayer_top_inst/ControlTransfer_inst/n6461_s1/I2 |
| 5.358 | 0.375 | tINS | RR | 48 | R62C38[3][B] | UserLayer_top_inst/ControlTransfer_inst/n6461_s1/F |
| 6.787 | 1.429 | tNET | RR | 1 | R63C50[1][B] | UserLayer_top_inst/ControlTransfer_inst/dwMaxVideoFrameSize_13_s0/CE |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.250 | 6.250 | active clock edge time | ||||
| 6.250 | 0.000 | pclk | ||||
| 6.250 | 0.000 | tCL | RR | 10163 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK |
| 7.770 | 1.520 | tNET | RR | 1 | R63C50[1][B] | UserLayer_top_inst/ControlTransfer_inst/dwMaxVideoFrameSize_13_s0/CLK |
| 7.546 | -0.224 | tSu | 1 | R63C50[1][B] | UserLayer_top_inst/ControlTransfer_inst/dwMaxVideoFrameSize_13_s0 |
Path Statistics:
| Clock Skew | 0.007 |
| Setup Relationship | 6.250 |
| Logic Level | 6 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.513, 100.000% |
| Arrival Data Path Delay | cell: 1.873, 35.512%; route: 3.126, 59.266%; tC2Q: 0.275, 5.222% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.520, 100.000% |
Path45
Path Summary:
| Slack | 0.759 |
| Data Arrival Time | 6.787 |
| Data Required Time | 7.546 |
| From | UserLayer_top_inst/ControlTransfer_inst/wValue_latch_9_s0 |
| To | UserLayer_top_inst/ControlTransfer_inst/dwMaxVideoFrameSize_27_s0 |
| Launch Clk | pclk:[R] |
| Latch Clk | pclk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | pclk | ||||
| 0.000 | 0.000 | tCL | RR | 10163 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK |
| 1.513 | 1.513 | tNET | RR | 1 | R68C39[1][B] | UserLayer_top_inst/ControlTransfer_inst/wValue_latch_9_s0/CLK |
| 1.789 | 0.275 | tC2Q | RR | 7 | R68C39[1][B] | UserLayer_top_inst/ControlTransfer_inst/wValue_latch_9_s0/Q |
| 2.046 | 0.257 | tNET | RR | 1 | R69C41[2][A] | UserLayer_top_inst/ControlTransfer_inst/n4511_s21/I3 |
| 2.418 | 0.372 | tINS | RR | 10 | R69C41[2][A] | UserLayer_top_inst/ControlTransfer_inst/n4511_s21/F |
| 2.888 | 0.470 | tNET | RR | 1 | R70C47[3][B] | UserLayer_top_inst/ControlTransfer_inst/n4511_s17/I1 |
| 3.263 | 0.375 | tINS | RR | 11 | R70C47[3][B] | UserLayer_top_inst/ControlTransfer_inst/n4511_s17/F |
| 3.609 | 0.346 | tNET | RR | 1 | R70C40[3][B] | UserLayer_top_inst/ControlTransfer_inst/n688_s28/I3 |
| 3.985 | 0.375 | tINS | RR | 6 | R70C40[3][B] | UserLayer_top_inst/ControlTransfer_inst/n688_s28/F |
| 4.329 | 0.344 | tNET | RR | 1 | R64C40[3][B] | UserLayer_top_inst/ControlTransfer_inst/n6333_s3/I1 |
| 4.704 | 0.375 | tINS | RR | 5 | R64C40[3][B] | UserLayer_top_inst/ControlTransfer_inst/n6333_s3/F |
| 4.983 | 0.279 | tNET | RR | 1 | R62C38[3][B] | UserLayer_top_inst/ControlTransfer_inst/n6461_s1/I2 |
| 5.358 | 0.375 | tINS | RR | 48 | R62C38[3][B] | UserLayer_top_inst/ControlTransfer_inst/n6461_s1/F |
| 6.787 | 1.429 | tNET | RR | 1 | R63C50[0][B] | UserLayer_top_inst/ControlTransfer_inst/dwMaxVideoFrameSize_27_s0/CE |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.250 | 6.250 | active clock edge time | ||||
| 6.250 | 0.000 | pclk | ||||
| 6.250 | 0.000 | tCL | RR | 10163 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK |
| 7.770 | 1.520 | tNET | RR | 1 | R63C50[0][B] | UserLayer_top_inst/ControlTransfer_inst/dwMaxVideoFrameSize_27_s0/CLK |
| 7.546 | -0.224 | tSu | 1 | R63C50[0][B] | UserLayer_top_inst/ControlTransfer_inst/dwMaxVideoFrameSize_27_s0 |
Path Statistics:
| Clock Skew | 0.007 |
| Setup Relationship | 6.250 |
| Logic Level | 6 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.513, 100.000% |
| Arrival Data Path Delay | cell: 1.873, 35.512%; route: 3.126, 59.266%; tC2Q: 0.275, 5.222% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.520, 100.000% |
Path46
Path Summary:
| Slack | 0.773 |
| Data Arrival Time | 6.773 |
| Data Required Time | 7.546 |
| From | UserLayer_top_inst/ControlTransfer_inst/wValue_latch_9_s0 |
| To | UserLayer_top_inst/ControlTransfer_inst/wDelay_4_s0 |
| Launch Clk | pclk:[R] |
| Latch Clk | pclk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | pclk | ||||
| 0.000 | 0.000 | tCL | RR | 10163 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK |
| 1.513 | 1.513 | tNET | RR | 1 | R68C39[1][B] | UserLayer_top_inst/ControlTransfer_inst/wValue_latch_9_s0/CLK |
| 1.789 | 0.275 | tC2Q | RR | 7 | R68C39[1][B] | UserLayer_top_inst/ControlTransfer_inst/wValue_latch_9_s0/Q |
| 2.046 | 0.257 | tNET | RR | 1 | R69C41[2][A] | UserLayer_top_inst/ControlTransfer_inst/n4511_s21/I3 |
| 2.418 | 0.372 | tINS | RR | 10 | R69C41[2][A] | UserLayer_top_inst/ControlTransfer_inst/n4511_s21/F |
| 2.888 | 0.470 | tNET | RR | 1 | R70C47[3][B] | UserLayer_top_inst/ControlTransfer_inst/n4511_s17/I1 |
| 3.263 | 0.375 | tINS | RR | 11 | R70C47[3][B] | UserLayer_top_inst/ControlTransfer_inst/n4511_s17/F |
| 3.609 | 0.346 | tNET | RR | 1 | R70C40[3][B] | UserLayer_top_inst/ControlTransfer_inst/n688_s28/I3 |
| 3.985 | 0.375 | tINS | RR | 6 | R70C40[3][B] | UserLayer_top_inst/ControlTransfer_inst/n688_s28/F |
| 4.329 | 0.344 | tNET | RR | 1 | R64C40[3][B] | UserLayer_top_inst/ControlTransfer_inst/n6333_s3/I1 |
| 4.704 | 0.375 | tINS | RR | 5 | R64C40[3][B] | UserLayer_top_inst/ControlTransfer_inst/n6333_s3/F |
| 4.983 | 0.279 | tNET | RR | 1 | R62C38[3][B] | UserLayer_top_inst/ControlTransfer_inst/n6461_s1/I2 |
| 5.358 | 0.375 | tINS | RR | 48 | R62C38[3][B] | UserLayer_top_inst/ControlTransfer_inst/n6461_s1/F |
| 6.773 | 1.415 | tNET | RR | 1 | R66C46[1][A] | UserLayer_top_inst/ControlTransfer_inst/wDelay_4_s0/CE |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.250 | 6.250 | active clock edge time | ||||
| 6.250 | 0.000 | pclk | ||||
| 6.250 | 0.000 | tCL | RR | 10163 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK |
| 7.770 | 1.520 | tNET | RR | 1 | R66C46[1][A] | UserLayer_top_inst/ControlTransfer_inst/wDelay_4_s0/CLK |
| 7.546 | -0.224 | tSu | 1 | R66C46[1][A] | UserLayer_top_inst/ControlTransfer_inst/wDelay_4_s0 |
Path Statistics:
| Clock Skew | 0.007 |
| Setup Relationship | 6.250 |
| Logic Level | 6 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.513, 100.000% |
| Arrival Data Path Delay | cell: 1.873, 35.609%; route: 3.111, 59.155%; tC2Q: 0.275, 5.236% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.520, 100.000% |
Path47
Path Summary:
| Slack | 0.792 |
| Data Arrival Time | 6.754 |
| Data Required Time | 7.546 |
| From | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_word_alignment/data_in_r0_3_s0 |
| To | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_word_alignment/cnt0_1_s1 |
| Launch Clk | q0_lane1_fabric_rx_clk:[R] |
| Latch Clk | q0_lane1_fabric_rx_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | q0_lane1_fabric_rx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 518 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_RX_O_FABRIC_CLK |
| 1.513 | 1.513 | tNET | RR | 1 | R25C81[3][A] | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_word_alignment/data_in_r0_3_s0/CLK |
| 1.789 | 0.275 | tC2Q | RR | 13 | R25C81[3][A] | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_word_alignment/data_in_r0_3_s0/Q |
| 2.392 | 0.603 | tNET | RR | 1 | R27C80[3][B] | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_word_alignment/cnt0_3_s61/I0 |
| 2.691 | 0.299 | tINS | RR | 2 | R27C80[3][B] | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_word_alignment/cnt0_3_s61/F |
| 2.806 | 0.115 | tNET | RR | 1 | R26C80[1][A] | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_word_alignment/cnt0_3_s58/I3 |
| 3.177 | 0.372 | tINS | RR | 2 | R26C80[1][A] | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_word_alignment/cnt0_3_s58/F |
| 3.728 | 0.551 | tNET | RR | 1 | R25C81[0][B] | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_word_alignment/cnt0_3_s27/I1 |
| 4.100 | 0.372 | tINS | RR | 2 | R25C81[0][B] | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_word_alignment/cnt0_3_s27/F |
| 4.798 | 0.698 | tNET | RR | 1 | R25C82[2][B] | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_word_alignment/cnt0_3_s10/I2 |
| 5.170 | 0.372 | tINS | RR | 2 | R25C82[2][B] | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_word_alignment/cnt0_3_s10/F |
| 5.732 | 0.562 | tNET | RR | 1 | R25C82[3][A] | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_word_alignment/cnt0_3_s4/I3 |
| 5.940 | 0.209 | tINS | RF | 2 | R25C82[3][A] | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_word_alignment/cnt0_3_s4/F |
| 6.200 | 0.259 | tNET | FF | 1 | R25C84[3][A] | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_word_alignment/cnt0_3_s3/I0 |
| 6.498 | 0.299 | tINS | FR | 5 | R25C84[3][A] | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_word_alignment/cnt0_3_s3/F |
| 6.754 | 0.256 | tNET | RR | 1 | R25C86[3][A] | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_word_alignment/cnt0_1_s1/CE |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.250 | 6.250 | active clock edge time | ||||
| 6.250 | 0.000 | q0_lane1_fabric_rx_clk | ||||
| 6.250 | 0.000 | tCL | RR | 518 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_RX_O_FABRIC_CLK |
| 7.770 | 1.520 | tNET | RR | 1 | R25C86[3][A] | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_word_alignment/cnt0_1_s1/CLK |
| 7.546 | -0.224 | tSu | 1 | R25C86[3][A] | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_word_alignment/cnt0_1_s1 |
Path Statistics:
| Clock Skew | 0.007 |
| Setup Relationship | 6.250 |
| Logic Level | 7 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.513, 100.000% |
| Arrival Data Path Delay | cell: 1.921, 36.665%; route: 3.044, 58.080%; tC2Q: 0.275, 5.255% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.520, 100.000% |
Path48
Path Summary:
| Slack | 0.792 |
| Data Arrival Time | 6.754 |
| Data Required Time | 7.546 |
| From | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_word_alignment/data_in_r0_3_s0 |
| To | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_word_alignment/cnt0_2_s1 |
| Launch Clk | q0_lane1_fabric_rx_clk:[R] |
| Latch Clk | q0_lane1_fabric_rx_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | q0_lane1_fabric_rx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 518 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_RX_O_FABRIC_CLK |
| 1.513 | 1.513 | tNET | RR | 1 | R25C81[3][A] | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_word_alignment/data_in_r0_3_s0/CLK |
| 1.789 | 0.275 | tC2Q | RR | 13 | R25C81[3][A] | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_word_alignment/data_in_r0_3_s0/Q |
| 2.392 | 0.603 | tNET | RR | 1 | R27C80[3][B] | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_word_alignment/cnt0_3_s61/I0 |
| 2.691 | 0.299 | tINS | RR | 2 | R27C80[3][B] | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_word_alignment/cnt0_3_s61/F |
| 2.806 | 0.115 | tNET | RR | 1 | R26C80[1][A] | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_word_alignment/cnt0_3_s58/I3 |
| 3.177 | 0.372 | tINS | RR | 2 | R26C80[1][A] | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_word_alignment/cnt0_3_s58/F |
| 3.728 | 0.551 | tNET | RR | 1 | R25C81[0][B] | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_word_alignment/cnt0_3_s27/I1 |
| 4.100 | 0.372 | tINS | RR | 2 | R25C81[0][B] | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_word_alignment/cnt0_3_s27/F |
| 4.798 | 0.698 | tNET | RR | 1 | R25C82[2][B] | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_word_alignment/cnt0_3_s10/I2 |
| 5.170 | 0.372 | tINS | RR | 2 | R25C82[2][B] | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_word_alignment/cnt0_3_s10/F |
| 5.732 | 0.562 | tNET | RR | 1 | R25C82[3][A] | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_word_alignment/cnt0_3_s4/I3 |
| 5.940 | 0.209 | tINS | RF | 2 | R25C82[3][A] | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_word_alignment/cnt0_3_s4/F |
| 6.200 | 0.259 | tNET | FF | 1 | R25C84[3][A] | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_word_alignment/cnt0_3_s3/I0 |
| 6.498 | 0.299 | tINS | FR | 5 | R25C84[3][A] | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_word_alignment/cnt0_3_s3/F |
| 6.754 | 0.256 | tNET | RR | 1 | R25C86[0][B] | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_word_alignment/cnt0_2_s1/CE |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.250 | 6.250 | active clock edge time | ||||
| 6.250 | 0.000 | q0_lane1_fabric_rx_clk | ||||
| 6.250 | 0.000 | tCL | RR | 518 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_RX_O_FABRIC_CLK |
| 7.770 | 1.520 | tNET | RR | 1 | R25C86[0][B] | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_word_alignment/cnt0_2_s1/CLK |
| 7.546 | -0.224 | tSu | 1 | R25C86[0][B] | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_word_alignment/cnt0_2_s1 |
Path Statistics:
| Clock Skew | 0.007 |
| Setup Relationship | 6.250 |
| Logic Level | 7 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.513, 100.000% |
| Arrival Data Path Delay | cell: 1.921, 36.665%; route: 3.044, 58.080%; tC2Q: 0.275, 5.255% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.520, 100.000% |
Path49
Path Summary:
| Slack | 0.796 |
| Data Arrival Time | 6.915 |
| Data Required Time | 7.711 |
| From | UserLayer_top_inst/ControlTransfer_inst/bmRequestType_latch_1_s0 |
| To | UserLayer_top_inst/ControlTransfer_inst/transfer_in_data_mux_59_s0 |
| Launch Clk | pclk:[R] |
| Latch Clk | pclk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | pclk | ||||
| 0.000 | 0.000 | tCL | RR | 10163 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK |
| 1.513 | 1.513 | tNET | RR | 1 | R55C39[1][B] | UserLayer_top_inst/ControlTransfer_inst/bmRequestType_latch_1_s0/CLK |
| 1.789 | 0.275 | tC2Q | RR | 1 | R55C39[1][B] | UserLayer_top_inst/ControlTransfer_inst/bmRequestType_latch_1_s0/Q |
| 2.123 | 0.334 | tNET | RR | 1 | R57C41[3][A] | UserLayer_top_inst/ControlTransfer_inst/n4443_s20/I0 |
| 2.481 | 0.358 | tINS | RR | 2 | R57C41[3][A] | UserLayer_top_inst/ControlTransfer_inst/n4443_s20/F |
| 3.030 | 0.549 | tNET | RR | 1 | R72C42[3][A] | UserLayer_top_inst/ControlTransfer_inst/n4443_s18/I3 |
| 3.405 | 0.375 | tINS | RR | 5 | R72C42[3][A] | UserLayer_top_inst/ControlTransfer_inst/n4443_s18/F |
| 4.152 | 0.747 | tNET | RR | 1 | R66C47[3][B] | UserLayer_top_inst/ControlTransfer_inst/n4443_s17/I1 |
| 4.510 | 0.358 | tINS | RR | 48 | R66C47[3][B] | UserLayer_top_inst/ControlTransfer_inst/n4443_s17/F |
| 5.036 | 0.526 | tNET | RR | 1 | R61C43[1][B] | UserLayer_top_inst/ControlTransfer_inst/n4419_s15/I3 |
| 5.415 | 0.379 | tINS | RR | 1 | R61C43[1][B] | UserLayer_top_inst/ControlTransfer_inst/n4419_s15/F |
| 5.733 | 0.319 | tNET | RR | 1 | R68C43[0][A] | UserLayer_top_inst/ControlTransfer_inst/n4419_s14/I3 |
| 5.922 | 0.189 | tINS | RR | 1 | R68C43[0][A] | UserLayer_top_inst/ControlTransfer_inst/n4419_s14/F |
| 6.061 | 0.139 | tNET | RR | 1 | R68C45[0][B] | UserLayer_top_inst/ControlTransfer_inst/n4419_s12/I3 |
| 6.250 | 0.189 | tINS | RR | 1 | R68C45[0][B] | UserLayer_top_inst/ControlTransfer_inst/n4419_s12/F |
| 6.543 | 0.293 | tNET | RR | 1 | R68C48[2][A] | UserLayer_top_inst/ControlTransfer_inst/n4419_s11/I2 |
| 6.915 | 0.372 | tINS | RR | 1 | R68C48[2][A] | UserLayer_top_inst/ControlTransfer_inst/n4419_s11/F |
| 6.915 | 0.000 | tNET | RR | 1 | R68C48[2][A] | UserLayer_top_inst/ControlTransfer_inst/transfer_in_data_mux_59_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.250 | 6.250 | active clock edge time | ||||
| 6.250 | 0.000 | pclk | ||||
| 6.250 | 0.000 | tCL | RR | 10163 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK |
| 7.757 | 1.507 | tNET | RR | 1 | R68C48[2][A] | UserLayer_top_inst/ControlTransfer_inst/transfer_in_data_mux_59_s0/CLK |
| 7.711 | -0.046 | tSu | 1 | R68C48[2][A] | UserLayer_top_inst/ControlTransfer_inst/transfer_in_data_mux_59_s0 |
Path Statistics:
| Clock Skew | -0.007 |
| Setup Relationship | 6.250 |
| Logic Level | 8 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.513, 100.000% |
| Arrival Data Path Delay | cell: 2.220, 41.103%; route: 2.906, 53.799%; tC2Q: 0.275, 5.098% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.507, 100.000% |
Path50
Path Summary:
| Slack | 0.798 |
| Data Arrival Time | 7.269 |
| Data Required Time | 8.067 |
| From | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/GEN1_DPP_buff/mem_mem_0_1_s |
| To | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_dpp_9_s1 |
| Launch Clk | pclk:[R] |
| Latch Clk | pclk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | pclk | ||||
| 0.000 | 0.000 | tCL | RR | 10163 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK |
| 1.870 | 1.870 | tNET | RR | 36 | BSRAM_R38[11] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/GEN1_DPP_buff/mem_mem_0_1_s/CLKB |
| 3.321 | 1.451 | tC2Q | RR | 1 | BSRAM_R38[11] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/GEN1_DPP_buff/mem_mem_0_1_s/DO[5] |
| 3.956 | 0.635 | tNET | RR | 1 | R37C53[0][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n4729_s13/I1 |
| 4.288 | 0.332 | tINS | RR | 2 | R37C53[0][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n4729_s13/F |
| 4.565 | 0.277 | tNET | RR | 1 | R33C53[3][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n4729_s17/I0 |
| 4.923 | 0.358 | tINS | RR | 1 | R33C53[3][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n4729_s17/F |
| 5.062 | 0.139 | tNET | RR | 1 | R33C54[3][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n4729_s16/I1 |
| 5.361 | 0.299 | tINS | RR | 1 | R33C54[3][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n4729_s16/F |
| 5.499 | 0.139 | tNET | RR | 1 | R31C54[2][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n4729_s18/I0 |
| 5.871 | 0.372 | tINS | RR | 1 | R31C54[2][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n4729_s18/F |
| 6.121 | 0.250 | tNET | RR | 1 | R32C52[2][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n4729_s12/I1 |
| 6.493 | 0.372 | tINS | RR | 1 | R32C52[2][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n4729_s12/F |
| 6.606 | 0.113 | tNET | RR | 1 | R31C52[3][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n4729_s10/I2 |
| 6.965 | 0.358 | tINS | RR | 2 | R31C52[3][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n4729_s10/F |
| 7.269 | 0.304 | tNET | RR | 1 | R30C52[2][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_dpp_9_s1/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.250 | 6.250 | active clock edge time | ||||
| 6.250 | 0.000 | pclk | ||||
| 6.250 | 0.000 | tCL | RR | 10163 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK |
| 8.113 | 1.863 | tNET | RR | 1 | R30C52[2][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_dpp_9_s1/CLK |
| 8.067 | -0.046 | tSu | 1 | R30C52[2][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_dpp_9_s1 |
Path Statistics:
| Clock Skew | -0.007 |
| Setup Relationship | 6.250 |
| Logic Level | 7 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.870, 100.000% |
| Arrival Data Path Delay | cell: 2.091, 38.723%; route: 1.858, 34.406%; tC2Q: 1.451, 26.871% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.863, 100.000% |
Path51
Path Summary:
| Slack | 0.798 |
| Data Arrival Time | 7.269 |
| Data Required Time | 8.067 |
| From | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/GEN1_DPP_buff/mem_mem_0_1_s |
| To | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_dpp_9_s0 |
| Launch Clk | pclk:[R] |
| Latch Clk | pclk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | pclk | ||||
| 0.000 | 0.000 | tCL | RR | 10163 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK |
| 1.870 | 1.870 | tNET | RR | 36 | BSRAM_R38[11] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/GEN1_DPP_buff/mem_mem_0_1_s/CLKB |
| 3.321 | 1.451 | tC2Q | RR | 1 | BSRAM_R38[11] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/GEN1_DPP_buff/mem_mem_0_1_s/DO[5] |
| 3.956 | 0.635 | tNET | RR | 1 | R37C53[0][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n4729_s13/I1 |
| 4.288 | 0.332 | tINS | RR | 2 | R37C53[0][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n4729_s13/F |
| 4.565 | 0.277 | tNET | RR | 1 | R33C53[3][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n4729_s17/I0 |
| 4.923 | 0.358 | tINS | RR | 1 | R33C53[3][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n4729_s17/F |
| 5.062 | 0.139 | tNET | RR | 1 | R33C54[3][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n4729_s16/I1 |
| 5.361 | 0.299 | tINS | RR | 1 | R33C54[3][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n4729_s16/F |
| 5.499 | 0.139 | tNET | RR | 1 | R31C54[2][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n4729_s18/I0 |
| 5.871 | 0.372 | tINS | RR | 1 | R31C54[2][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n4729_s18/F |
| 6.121 | 0.250 | tNET | RR | 1 | R32C52[2][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n4729_s12/I1 |
| 6.493 | 0.372 | tINS | RR | 1 | R32C52[2][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n4729_s12/F |
| 6.606 | 0.113 | tNET | RR | 1 | R31C52[3][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n4729_s10/I2 |
| 6.965 | 0.358 | tINS | RR | 2 | R31C52[3][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n4729_s10/F |
| 7.269 | 0.304 | tNET | RR | 1 | R31C52[1][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_dpp_9_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.250 | 6.250 | active clock edge time | ||||
| 6.250 | 0.000 | pclk | ||||
| 6.250 | 0.000 | tCL | RR | 10163 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK |
| 8.113 | 1.863 | tNET | RR | 1 | R31C52[1][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_dpp_9_s0/CLK |
| 8.067 | -0.046 | tSu | 1 | R31C52[1][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_dpp_9_s0 |
Path Statistics:
| Clock Skew | -0.007 |
| Setup Relationship | 6.250 |
| Logic Level | 7 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.870, 100.000% |
| Arrival Data Path Delay | cell: 2.091, 38.723%; route: 1.858, 34.406%; tC2Q: 1.451, 26.871% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.863, 100.000% |
Path52
Path Summary:
| Slack | 0.800 |
| Data Arrival Time | 6.740 |
| Data Required Time | 7.539 |
| From | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_word_alignment/data_in_r0_3_s0 |
| To | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_word_alignment/cnt0_0_s1 |
| Launch Clk | q0_lane1_fabric_rx_clk:[R] |
| Latch Clk | q0_lane1_fabric_rx_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | q0_lane1_fabric_rx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 518 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_RX_O_FABRIC_CLK |
| 1.513 | 1.513 | tNET | RR | 1 | R25C81[3][A] | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_word_alignment/data_in_r0_3_s0/CLK |
| 1.789 | 0.275 | tC2Q | RR | 13 | R25C81[3][A] | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_word_alignment/data_in_r0_3_s0/Q |
| 2.392 | 0.603 | tNET | RR | 1 | R27C80[3][B] | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_word_alignment/cnt0_3_s61/I0 |
| 2.691 | 0.299 | tINS | RR | 2 | R27C80[3][B] | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_word_alignment/cnt0_3_s61/F |
| 2.806 | 0.115 | tNET | RR | 1 | R26C80[1][A] | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_word_alignment/cnt0_3_s58/I3 |
| 3.177 | 0.372 | tINS | RR | 2 | R26C80[1][A] | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_word_alignment/cnt0_3_s58/F |
| 3.728 | 0.551 | tNET | RR | 1 | R25C81[0][B] | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_word_alignment/cnt0_3_s27/I1 |
| 4.100 | 0.372 | tINS | RR | 2 | R25C81[0][B] | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_word_alignment/cnt0_3_s27/F |
| 4.798 | 0.698 | tNET | RR | 1 | R25C82[2][B] | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_word_alignment/cnt0_3_s10/I2 |
| 5.170 | 0.372 | tINS | RR | 2 | R25C82[2][B] | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_word_alignment/cnt0_3_s10/F |
| 5.732 | 0.562 | tNET | RR | 1 | R25C82[3][A] | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_word_alignment/cnt0_3_s4/I3 |
| 5.940 | 0.209 | tINS | RF | 2 | R25C82[3][A] | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_word_alignment/cnt0_3_s4/F |
| 6.200 | 0.259 | tNET | FF | 1 | R25C84[3][A] | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_word_alignment/cnt0_3_s3/I0 |
| 6.498 | 0.299 | tINS | FR | 5 | R25C84[3][A] | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_word_alignment/cnt0_3_s3/F |
| 6.740 | 0.241 | tNET | RR | 1 | R25C85[0][A] | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_word_alignment/cnt0_0_s1/CE |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.250 | 6.250 | active clock edge time | ||||
| 6.250 | 0.000 | q0_lane1_fabric_rx_clk | ||||
| 6.250 | 0.000 | tCL | RR | 518 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_RX_O_FABRIC_CLK |
| 7.763 | 1.513 | tNET | RR | 1 | R25C85[0][A] | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_word_alignment/cnt0_0_s1/CLK |
| 7.539 | -0.224 | tSu | 1 | R25C85[0][A] | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_word_alignment/cnt0_0_s1 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 6.250 |
| Logic Level | 7 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.513, 100.000% |
| Arrival Data Path Delay | cell: 1.921, 36.766%; route: 3.029, 57.965%; tC2Q: 0.275, 5.270% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.513, 100.000% |
Path53
Path Summary:
| Slack | 0.805 |
| Data Arrival Time | 6.912 |
| Data Required Time | 7.717 |
| From | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb_pipe_interface/RxData_6_s1 |
| To | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_encode_8b10b_4ch/enc3/dout_3_s0 |
| Launch Clk | pclk:[R] |
| Latch Clk | pclk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | pclk | ||||
| 0.000 | 0.000 | tCL | RR | 10163 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK |
| 1.507 | 1.507 | tNET | RR | 1 | R21C89[0][A] | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb_pipe_interface/RxData_6_s1/CLK |
| 1.782 | 0.275 | tC2Q | RR | 9 | R21C89[0][A] | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb_pipe_interface/RxData_6_s1/Q |
| 2.260 | 0.478 | tNET | RR | 1 | R18C87[1][A] | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_encode_8b10b_4ch/enc2/b6_0_s15/I1 |
| 2.632 | 0.372 | tINS | RR | 1 | R18C87[1][A] | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_encode_8b10b_4ch/enc2/b6_0_s15/F |
| 2.867 | 0.236 | tNET | RR | 1 | R18C85[2][A] | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_encode_8b10b_4ch/enc2/b6_0_s12/I2 |
| 3.199 | 0.332 | tINS | RR | 1 | R18C85[2][A] | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_encode_8b10b_4ch/enc2/b6_0_s12/F |
| 3.494 | 0.294 | tNET | RR | 1 | R20C85[2][B] | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_encode_8b10b_4ch/enc2/b6_0_s16/I3 |
| 3.873 | 0.379 | tINS | RR | 6 | R20C85[2][B] | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_encode_8b10b_4ch/enc2/b6_0_s16/F |
| 4.505 | 0.633 | tNET | RR | 1 | R17C82[1][A] | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_encode_8b10b_4ch/enc3/b6_1_s3/I1 |
| 4.884 | 0.379 | tINS | RR | 15 | R17C82[1][A] | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_encode_8b10b_4ch/enc3/b6_1_s3/F |
| 5.318 | 0.434 | tNET | RR | 1 | R20C81[3][A] | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_encode_8b10b_4ch/enc3/b6_3_s5/I3 |
| 5.676 | 0.358 | tINS | RR | 2 | R20C81[3][A] | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_encode_8b10b_4ch/enc3/b6_3_s5/F |
| 5.680 | 0.004 | tNET | RR | 1 | R20C81[1][B] | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_encode_8b10b_4ch/enc3/b6_2_s3/I2 |
| 6.012 | 0.332 | tINS | RR | 1 | R20C81[1][B] | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_encode_8b10b_4ch/enc3/b6_2_s3/F |
| 6.580 | 0.568 | tNET | RR | 1 | R17C80[1][A] | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_encode_8b10b_4ch/enc3/b6_2_s1/I1 |
| 6.912 | 0.332 | tINS | RR | 1 | R17C80[1][A] | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_encode_8b10b_4ch/enc3/b6_2_s1/F |
| 6.912 | 0.000 | tNET | RR | 1 | R17C80[1][A] | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_encode_8b10b_4ch/enc3/dout_3_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.250 | 6.250 | active clock edge time | ||||
| 6.250 | 0.000 | pclk | ||||
| 6.250 | 0.000 | tCL | RR | 10163 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK |
| 7.763 | 1.513 | tNET | RR | 1 | R17C80[1][A] | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_encode_8b10b_4ch/enc3/dout_3_s0/CLK |
| 7.717 | -0.046 | tSu | 1 | R17C80[1][A] | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_encode_8b10b_4ch/enc3/dout_3_s0 |
Path Statistics:
| Clock Skew | 0.007 |
| Setup Relationship | 6.250 |
| Logic Level | 8 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.507, 100.000% |
| Arrival Data Path Delay | cell: 2.484, 45.954%; route: 2.646, 48.951%; tC2Q: 0.275, 5.095% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.513, 100.000% |
Path54
Path Summary:
| Slack | 0.805 |
| Data Arrival Time | 6.905 |
| Data Required Time | 7.711 |
| From | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_word_alignment/data_in_r0_3_s0 |
| To | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_word_alignment/cnt0_3_s1 |
| Launch Clk | q0_lane1_fabric_rx_clk:[R] |
| Latch Clk | q0_lane1_fabric_rx_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | q0_lane1_fabric_rx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 518 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_RX_O_FABRIC_CLK |
| 1.513 | 1.513 | tNET | RR | 1 | R25C81[3][A] | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_word_alignment/data_in_r0_3_s0/CLK |
| 1.789 | 0.275 | tC2Q | RR | 13 | R25C81[3][A] | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_word_alignment/data_in_r0_3_s0/Q |
| 2.392 | 0.603 | tNET | RR | 1 | R27C80[3][B] | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_word_alignment/cnt0_3_s61/I0 |
| 2.691 | 0.299 | tINS | RR | 2 | R27C80[3][B] | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_word_alignment/cnt0_3_s61/F |
| 2.806 | 0.115 | tNET | RR | 1 | R26C80[1][A] | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_word_alignment/cnt0_3_s58/I3 |
| 3.177 | 0.372 | tINS | RR | 2 | R26C80[1][A] | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_word_alignment/cnt0_3_s58/F |
| 3.728 | 0.551 | tNET | RR | 1 | R25C81[0][B] | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_word_alignment/cnt0_3_s27/I1 |
| 4.100 | 0.372 | tINS | RR | 2 | R25C81[0][B] | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_word_alignment/cnt0_3_s27/F |
| 4.798 | 0.698 | tNET | RR | 1 | R25C82[2][B] | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_word_alignment/cnt0_3_s10/I2 |
| 5.170 | 0.372 | tINS | RR | 2 | R25C82[2][B] | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_word_alignment/cnt0_3_s10/F |
| 5.732 | 0.562 | tNET | RR | 1 | R25C82[3][A] | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_word_alignment/cnt0_3_s4/I3 |
| 5.940 | 0.209 | tINS | RF | 2 | R25C82[3][A] | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_word_alignment/cnt0_3_s4/F |
| 6.200 | 0.259 | tNET | FF | 1 | R25C84[1][B] | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_word_alignment/n730_s4/I0 |
| 6.532 | 0.332 | tINS | FR | 1 | R25C84[1][B] | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_word_alignment/n730_s4/F |
| 6.534 | 0.002 | tNET | RR | 1 | R25C84[1][A] | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_word_alignment/n730_s3/I0 |
| 6.905 | 0.372 | tINS | RR | 1 | R25C84[1][A] | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_word_alignment/n730_s3/F |
| 6.905 | 0.000 | tNET | RR | 1 | R25C84[1][A] | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_word_alignment/cnt0_3_s1/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.250 | 6.250 | active clock edge time | ||||
| 6.250 | 0.000 | q0_lane1_fabric_rx_clk | ||||
| 6.250 | 0.000 | tCL | RR | 518 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_RX_O_FABRIC_CLK |
| 7.757 | 1.507 | tNET | RR | 1 | R25C84[1][A] | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_word_alignment/cnt0_3_s1/CLK |
| 7.711 | -0.046 | tSu | 1 | R25C84[1][A] | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_word_alignment/cnt0_3_s1 |
Path Statistics:
| Clock Skew | -0.007 |
| Setup Relationship | 6.250 |
| Logic Level | 8 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.513, 100.000% |
| Arrival Data Path Delay | cell: 2.326, 43.148%; route: 2.790, 51.744%; tC2Q: 0.275, 5.108% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.507, 100.000% |
Path55
Path Summary:
| Slack | 0.838 |
| Data Arrival Time | 6.879 |
| Data Required Time | 7.717 |
| From | UserLayer_top_inst/ControlTransfer_inst/bmRequestType_latch_1_s0 |
| To | UserLayer_top_inst/ControlTransfer_inst/transfer_in_data_mux_5_s0 |
| Launch Clk | pclk:[R] |
| Latch Clk | pclk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | pclk | ||||
| 0.000 | 0.000 | tCL | RR | 10163 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK |
| 1.513 | 1.513 | tNET | RR | 1 | R55C39[1][B] | UserLayer_top_inst/ControlTransfer_inst/bmRequestType_latch_1_s0/CLK |
| 1.789 | 0.275 | tC2Q | RR | 1 | R55C39[1][B] | UserLayer_top_inst/ControlTransfer_inst/bmRequestType_latch_1_s0/Q |
| 2.123 | 0.334 | tNET | RR | 1 | R57C41[3][A] | UserLayer_top_inst/ControlTransfer_inst/n4443_s20/I0 |
| 2.481 | 0.358 | tINS | RR | 2 | R57C41[3][A] | UserLayer_top_inst/ControlTransfer_inst/n4443_s20/F |
| 3.030 | 0.549 | tNET | RR | 1 | R72C42[3][A] | UserLayer_top_inst/ControlTransfer_inst/n4443_s18/I3 |
| 3.405 | 0.375 | tINS | RR | 5 | R72C42[3][A] | UserLayer_top_inst/ControlTransfer_inst/n4443_s18/F |
| 4.152 | 0.747 | tNET | RR | 1 | R66C47[3][B] | UserLayer_top_inst/ControlTransfer_inst/n4443_s17/I1 |
| 4.510 | 0.358 | tINS | RR | 48 | R66C47[3][B] | UserLayer_top_inst/ControlTransfer_inst/n4443_s17/F |
| 5.010 | 0.499 | tNET | RR | 1 | R68C42[0][B] | UserLayer_top_inst/ControlTransfer_inst/n4507_s21/I2 |
| 5.389 | 0.379 | tINS | RR | 15 | R68C42[0][B] | UserLayer_top_inst/ControlTransfer_inst/n4507_s21/F |
| 5.872 | 0.483 | tNET | RR | 1 | R66C47[0][A] | UserLayer_top_inst/ControlTransfer_inst/n4527_s14/I3 |
| 6.061 | 0.189 | tINS | RR | 1 | R66C47[0][A] | UserLayer_top_inst/ControlTransfer_inst/n4527_s14/F |
| 6.200 | 0.139 | tNET | RR | 1 | R68C47[3][B] | UserLayer_top_inst/ControlTransfer_inst/n4527_s12/I3 |
| 6.498 | 0.299 | tINS | RR | 1 | R68C47[3][B] | UserLayer_top_inst/ControlTransfer_inst/n4527_s12/F |
| 6.500 | 0.002 | tNET | RR | 1 | R68C47[2][B] | UserLayer_top_inst/ControlTransfer_inst/n4527_s10/I1 |
| 6.879 | 0.379 | tINS | RR | 1 | R68C47[2][B] | UserLayer_top_inst/ControlTransfer_inst/n4527_s10/F |
| 6.879 | 0.000 | tNET | RR | 1 | R68C47[2][B] | UserLayer_top_inst/ControlTransfer_inst/transfer_in_data_mux_5_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.250 | 6.250 | active clock edge time | ||||
| 6.250 | 0.000 | pclk | ||||
| 6.250 | 0.000 | tCL | RR | 10163 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK |
| 7.763 | 1.513 | tNET | RR | 1 | R68C47[2][B] | UserLayer_top_inst/ControlTransfer_inst/transfer_in_data_mux_5_s0/CLK |
| 7.717 | -0.046 | tSu | 1 | R68C47[2][B] | UserLayer_top_inst/ControlTransfer_inst/transfer_in_data_mux_5_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 6.250 |
| Logic Level | 8 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.513, 100.000% |
| Arrival Data Path Delay | cell: 2.337, 43.559%; route: 2.753, 51.308%; tC2Q: 0.275, 5.133% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.513, 100.000% |
Path56
Path Summary:
| Slack | 0.848 |
| Data Arrival Time | 6.691 |
| Data Required Time | 7.539 |
| From | UserLayer_top_inst/ControlTransfer_inst/wValue_latch_9_s0 |
| To | UserLayer_top_inst/ControlTransfer_inst/dwFrameInterval_3_s0 |
| Launch Clk | pclk:[R] |
| Latch Clk | pclk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | pclk | ||||
| 0.000 | 0.000 | tCL | RR | 10163 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK |
| 1.513 | 1.513 | tNET | RR | 1 | R68C39[1][B] | UserLayer_top_inst/ControlTransfer_inst/wValue_latch_9_s0/CLK |
| 1.789 | 0.275 | tC2Q | RR | 7 | R68C39[1][B] | UserLayer_top_inst/ControlTransfer_inst/wValue_latch_9_s0/Q |
| 2.046 | 0.257 | tNET | RR | 1 | R69C41[2][A] | UserLayer_top_inst/ControlTransfer_inst/n4511_s21/I3 |
| 2.418 | 0.372 | tINS | RR | 10 | R69C41[2][A] | UserLayer_top_inst/ControlTransfer_inst/n4511_s21/F |
| 2.888 | 0.470 | tNET | RR | 1 | R70C47[3][B] | UserLayer_top_inst/ControlTransfer_inst/n4511_s17/I1 |
| 3.263 | 0.375 | tINS | RR | 11 | R70C47[3][B] | UserLayer_top_inst/ControlTransfer_inst/n4511_s17/F |
| 3.609 | 0.346 | tNET | RR | 1 | R70C40[3][B] | UserLayer_top_inst/ControlTransfer_inst/n688_s28/I3 |
| 3.985 | 0.375 | tINS | RR | 6 | R70C40[3][B] | UserLayer_top_inst/ControlTransfer_inst/n688_s28/F |
| 4.329 | 0.344 | tNET | RR | 1 | R64C40[3][B] | UserLayer_top_inst/ControlTransfer_inst/n6333_s3/I1 |
| 4.704 | 0.375 | tINS | RR | 5 | R64C40[3][B] | UserLayer_top_inst/ControlTransfer_inst/n6333_s3/F |
| 4.959 | 0.256 | tNET | RR | 1 | R63C38[3][B] | UserLayer_top_inst/ControlTransfer_inst/n6333_s5/I2 |
| 5.335 | 0.375 | tINS | RR | 64 | R63C38[3][B] | UserLayer_top_inst/ControlTransfer_inst/n6333_s5/F |
| 6.691 | 1.356 | tNET | RR | 1 | R58C45[2][A] | UserLayer_top_inst/ControlTransfer_inst/dwFrameInterval_3_s0/CE |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.250 | 6.250 | active clock edge time | ||||
| 6.250 | 0.000 | pclk | ||||
| 6.250 | 0.000 | tCL | RR | 10163 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK |
| 7.763 | 1.513 | tNET | RR | 1 | R58C45[2][A] | UserLayer_top_inst/ControlTransfer_inst/dwFrameInterval_3_s0/CLK |
| 7.539 | -0.224 | tSu | 1 | R58C45[2][A] | UserLayer_top_inst/ControlTransfer_inst/dwFrameInterval_3_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 6.250 |
| Logic Level | 6 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.513, 100.000% |
| Arrival Data Path Delay | cell: 1.873, 36.172%; route: 3.029, 58.509%; tC2Q: 0.275, 5.319% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.513, 100.000% |
Path57
Path Summary:
| Slack | 0.857 |
| Data Arrival Time | 6.867 |
| Data Required Time | 7.724 |
| From | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/state_2_s0 |
| To | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/tsc_1_s0 |
| Launch Clk | pclk:[R] |
| Latch Clk | pclk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | pclk | ||||
| 0.000 | 0.000 | tCL | RR | 10163 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK |
| 1.513 | 1.513 | tNET | RR | 1 | R7C98[0][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/state_2_s0/CLK |
| 1.789 | 0.275 | tC2Q | RR | 103 | R7C98[0][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/state_2_s0/Q |
| 2.087 | 0.298 | tNET | RR | 1 | R6C96[3][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/n2380_s98/I1 |
| 2.445 | 0.358 | tINS | RR | 7 | R6C96[3][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/n2380_s98/F |
| 3.195 | 0.750 | tNET | RR | 1 | R11C106[2][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/n2389_s86/I3 |
| 3.527 | 0.332 | tINS | RR | 9 | R11C106[2][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/n2389_s86/F |
| 4.103 | 0.576 | tNET | RR | 1 | R9C97[3][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/n2398_s83/I2 |
| 4.478 | 0.375 | tINS | RR | 5 | R9C97[3][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/n2398_s83/F |
| 4.948 | 0.470 | tNET | RR | 1 | R8C104[2][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/n2404_s76/I3 |
| 5.327 | 0.379 | tINS | RR | 1 | R8C104[2][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/n2404_s76/F |
| 5.562 | 0.236 | tNET | RR | 1 | R6C104[2][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/n2404_s74/I1 |
| 5.934 | 0.372 | tINS | RR | 1 | R6C104[2][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/n2404_s74/F |
| 6.535 | 0.601 | tNET | RR | 1 | R9C99[0][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/n2404_s70/I3 |
| 6.867 | 0.332 | tINS | RR | 1 | R9C99[0][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/n2404_s70/F |
| 6.867 | 0.000 | tNET | RR | 1 | R9C99[0][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/tsc_1_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.250 | 6.250 | active clock edge time | ||||
| 6.250 | 0.000 | pclk | ||||
| 6.250 | 0.000 | tCL | RR | 10163 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK |
| 7.770 | 1.520 | tNET | RR | 1 | R9C99[0][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/tsc_1_s0/CLK |
| 7.724 | -0.046 | tSu | 1 | R9C99[0][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/tsc_1_s0 |
Path Statistics:
| Clock Skew | 0.007 |
| Setup Relationship | 6.250 |
| Logic Level | 7 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.513, 100.000% |
| Arrival Data Path Delay | cell: 2.148, 40.124%; route: 2.930, 54.732%; tC2Q: 0.275, 5.144% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.520, 100.000% |
Path58
Path Summary:
| Slack | 0.857 |
| Data Arrival Time | 6.742 |
| Data Required Time | 7.600 |
| From | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_header_pkt_66_s0 |
| To | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_hp_4_s1 |
| Launch Clk | pclk:[R] |
| Latch Clk | pclk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | pclk | ||||
| 0.000 | 0.000 | tCL | RR | 10163 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK |
| 1.513 | 1.513 | tNET | RR | 1 | R3C84[0][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_header_pkt_66_s0/CLK |
| 1.789 | 0.275 | tC2Q | RR | 10 | R3C84[0][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_header_pkt_66_s0/Q |
| 2.075 | 0.286 | tNET | RR | 1 | R4C83[3][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3759_s42/I1 |
| 2.450 | 0.375 | tINS | RR | 2 | R4C83[3][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3759_s42/F |
| 3.174 | 0.724 | tNET | RR | 1 | R4C83[0][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3759_s34/I3 |
| 3.553 | 0.379 | tINS | RR | 1 | R4C83[0][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3759_s34/F |
| 4.761 | 1.208 | tNET | RR | 1 | R6C81[3][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3759_s27/I3 |
| 5.119 | 0.358 | tINS | RR | 2 | R6C81[3][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3759_s27/F |
| 5.511 | 0.392 | tNET | RR | 1 | R8C82[1][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3759_s23/I1 |
| 5.883 | 0.372 | tINS | RR | 1 | R8C82[1][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3759_s23/F |
| 6.021 | 0.139 | tNET | RR | 1 | R8C80[0][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3759_s22/I0 |
| 6.393 | 0.372 | tINS | RR | 2 | R8C80[0][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3759_s22/F |
| 6.742 | 0.349 | tNET | RR | 1 | R7C78[3][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_hp_4_s1/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.250 | 6.250 | active clock edge time | ||||
| 6.250 | 0.000 | pclk | ||||
| 6.250 | 0.000 | tCL | RR | 10163 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK |
| 7.763 | 1.513 | tNET | RR | 1 | R7C78[3][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_hp_4_s1/CLK |
| 7.600 | -0.164 | tSu | 1 | R7C78[3][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_hp_4_s1 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 6.250 |
| Logic Level | 6 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.513, 100.000% |
| Arrival Data Path Delay | cell: 1.856, 35.491%; route: 3.098, 59.243%; tC2Q: 0.275, 5.267% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.513, 100.000% |
Path59
Path Summary:
| Slack | 0.860 |
| Data Arrival Time | 6.739 |
| Data Required Time | 7.600 |
| From | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0 |
| To | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_27_s1 |
| Launch Clk | pclk:[R] |
| Latch Clk | pclk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | pclk | ||||
| 0.000 | 0.000 | tCL | RR | 10163 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK |
| 1.520 | 1.520 | tNET | RR | 1 | R44C83[1][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/CLK |
| 1.795 | 0.275 | tC2Q | RR | 2598 | R44C83[1][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/Q |
| 3.694 | 1.898 | tNET | RR | 1 | R42C83[2][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_lcmd_3_s8/I2 |
| 3.883 | 0.189 | tINS | RR | 1 | R42C83[2][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_lcmd_3_s8/F |
| 3.886 | 0.004 | tNET | RR | 1 | R42C83[2][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3116_s18/I2 |
| 4.265 | 0.379 | tINS | RR | 2 | R42C83[2][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3116_s18/F |
| 5.192 | 0.927 | tNET | RR | 1 | R18C78[2][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5575_s4/I2 |
| 5.571 | 0.379 | tINS | RR | 1 | R18C78[2][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5575_s4/F |
| 5.821 | 0.250 | tNET | RR | 1 | R15C78[2][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5575_s1/I1 |
| 6.153 | 0.332 | tINS | RR | 1 | R15C78[2][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5575_s1/F |
| 6.155 | 0.002 | tNET | RR | 1 | R15C78[1][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5575_s0/I0 |
| 6.487 | 0.332 | tINS | RR | 2 | R15C78[1][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5575_s0/F |
| 6.739 | 0.252 | tNET | RR | 1 | R15C80[2][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_27_s1/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.250 | 6.250 | active clock edge time | ||||
| 6.250 | 0.000 | pclk | ||||
| 6.250 | 0.000 | tCL | RR | 10163 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK |
| 7.763 | 1.513 | tNET | RR | 1 | R15C80[2][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_27_s1/CLK |
| 7.600 | -0.164 | tSu | 1 | R15C80[2][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_27_s1 |
Path Statistics:
| Clock Skew | -0.007 |
| Setup Relationship | 6.250 |
| Logic Level | 6 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.520, 100.000% |
| Arrival Data Path Delay | cell: 1.611, 30.867%; route: 3.333, 63.856%; tC2Q: 0.275, 5.277% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.513, 100.000% |
Path60
Path Summary:
| Slack | 0.871 |
| Data Arrival Time | 6.675 |
| Data Required Time | 7.546 |
| From | UserLayer_top_inst/ControlTransfer_inst/wValue_latch_9_s0 |
| To | UserLayer_top_inst/ControlTransfer_inst/bFrameIndex_2_s0 |
| Launch Clk | pclk:[R] |
| Latch Clk | pclk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | pclk | ||||
| 0.000 | 0.000 | tCL | RR | 10163 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK |
| 1.513 | 1.513 | tNET | RR | 1 | R68C39[1][B] | UserLayer_top_inst/ControlTransfer_inst/wValue_latch_9_s0/CLK |
| 1.789 | 0.275 | tC2Q | RR | 7 | R68C39[1][B] | UserLayer_top_inst/ControlTransfer_inst/wValue_latch_9_s0/Q |
| 2.046 | 0.257 | tNET | RR | 1 | R69C41[2][A] | UserLayer_top_inst/ControlTransfer_inst/n4511_s21/I3 |
| 2.418 | 0.372 | tINS | RR | 10 | R69C41[2][A] | UserLayer_top_inst/ControlTransfer_inst/n4511_s21/F |
| 2.888 | 0.470 | tNET | RR | 1 | R70C47[3][B] | UserLayer_top_inst/ControlTransfer_inst/n4511_s17/I1 |
| 3.263 | 0.375 | tINS | RR | 11 | R70C47[3][B] | UserLayer_top_inst/ControlTransfer_inst/n4511_s17/F |
| 3.609 | 0.346 | tNET | RR | 1 | R70C40[3][B] | UserLayer_top_inst/ControlTransfer_inst/n688_s28/I3 |
| 3.985 | 0.375 | tINS | RR | 6 | R70C40[3][B] | UserLayer_top_inst/ControlTransfer_inst/n688_s28/F |
| 4.329 | 0.344 | tNET | RR | 1 | R64C40[3][B] | UserLayer_top_inst/ControlTransfer_inst/n6333_s3/I1 |
| 4.704 | 0.375 | tINS | RR | 5 | R64C40[3][B] | UserLayer_top_inst/ControlTransfer_inst/n6333_s3/F |
| 4.959 | 0.256 | tNET | RR | 1 | R63C38[3][B] | UserLayer_top_inst/ControlTransfer_inst/n6333_s5/I2 |
| 5.335 | 0.375 | tINS | RR | 64 | R63C38[3][B] | UserLayer_top_inst/ControlTransfer_inst/n6333_s5/F |
| 6.675 | 1.340 | tNET | RR | 1 | R61C50[2][A] | UserLayer_top_inst/ControlTransfer_inst/bFrameIndex_2_s0/CE |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.250 | 6.250 | active clock edge time | ||||
| 6.250 | 0.000 | pclk | ||||
| 6.250 | 0.000 | tCL | RR | 10163 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK |
| 7.770 | 1.520 | tNET | RR | 1 | R61C50[2][A] | UserLayer_top_inst/ControlTransfer_inst/bFrameIndex_2_s0/CLK |
| 7.546 | -0.224 | tSu | 1 | R61C50[2][A] | UserLayer_top_inst/ControlTransfer_inst/bFrameIndex_2_s0 |
Path Statistics:
| Clock Skew | 0.007 |
| Setup Relationship | 6.250 |
| Logic Level | 6 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.513, 100.000% |
| Arrival Data Path Delay | cell: 1.873, 36.286%; route: 3.013, 58.378%; tC2Q: 0.275, 5.336% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.520, 100.000% |
Path61
Path Summary:
| Slack | 0.871 |
| Data Arrival Time | 6.675 |
| Data Required Time | 7.546 |
| From | UserLayer_top_inst/ControlTransfer_inst/wValue_latch_9_s0 |
| To | UserLayer_top_inst/ControlTransfer_inst/bmHint_8_s0 |
| Launch Clk | pclk:[R] |
| Latch Clk | pclk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | pclk | ||||
| 0.000 | 0.000 | tCL | RR | 10163 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK |
| 1.513 | 1.513 | tNET | RR | 1 | R68C39[1][B] | UserLayer_top_inst/ControlTransfer_inst/wValue_latch_9_s0/CLK |
| 1.789 | 0.275 | tC2Q | RR | 7 | R68C39[1][B] | UserLayer_top_inst/ControlTransfer_inst/wValue_latch_9_s0/Q |
| 2.046 | 0.257 | tNET | RR | 1 | R69C41[2][A] | UserLayer_top_inst/ControlTransfer_inst/n4511_s21/I3 |
| 2.418 | 0.372 | tINS | RR | 10 | R69C41[2][A] | UserLayer_top_inst/ControlTransfer_inst/n4511_s21/F |
| 2.888 | 0.470 | tNET | RR | 1 | R70C47[3][B] | UserLayer_top_inst/ControlTransfer_inst/n4511_s17/I1 |
| 3.263 | 0.375 | tINS | RR | 11 | R70C47[3][B] | UserLayer_top_inst/ControlTransfer_inst/n4511_s17/F |
| 3.609 | 0.346 | tNET | RR | 1 | R70C40[3][B] | UserLayer_top_inst/ControlTransfer_inst/n688_s28/I3 |
| 3.985 | 0.375 | tINS | RR | 6 | R70C40[3][B] | UserLayer_top_inst/ControlTransfer_inst/n688_s28/F |
| 4.329 | 0.344 | tNET | RR | 1 | R64C40[3][B] | UserLayer_top_inst/ControlTransfer_inst/n6333_s3/I1 |
| 4.704 | 0.375 | tINS | RR | 5 | R64C40[3][B] | UserLayer_top_inst/ControlTransfer_inst/n6333_s3/F |
| 4.959 | 0.256 | tNET | RR | 1 | R63C38[3][B] | UserLayer_top_inst/ControlTransfer_inst/n6333_s5/I2 |
| 5.335 | 0.375 | tINS | RR | 64 | R63C38[3][B] | UserLayer_top_inst/ControlTransfer_inst/n6333_s5/F |
| 6.675 | 1.340 | tNET | RR | 1 | R61C50[2][B] | UserLayer_top_inst/ControlTransfer_inst/bmHint_8_s0/CE |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.250 | 6.250 | active clock edge time | ||||
| 6.250 | 0.000 | pclk | ||||
| 6.250 | 0.000 | tCL | RR | 10163 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK |
| 7.770 | 1.520 | tNET | RR | 1 | R61C50[2][B] | UserLayer_top_inst/ControlTransfer_inst/bmHint_8_s0/CLK |
| 7.546 | -0.224 | tSu | 1 | R61C50[2][B] | UserLayer_top_inst/ControlTransfer_inst/bmHint_8_s0 |
Path Statistics:
| Clock Skew | 0.007 |
| Setup Relationship | 6.250 |
| Logic Level | 6 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.513, 100.000% |
| Arrival Data Path Delay | cell: 1.873, 36.286%; route: 3.013, 58.378%; tC2Q: 0.275, 5.336% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.520, 100.000% |
Path62
Path Summary:
| Slack | 0.882 |
| Data Arrival Time | 6.657 |
| Data Required Time | 7.539 |
| From | UserLayer_top_inst/ControlTransfer_inst/wValue_latch_9_s0 |
| To | UserLayer_top_inst/ControlTransfer_inst/dwFrameInterval_22_s0 |
| Launch Clk | pclk:[R] |
| Latch Clk | pclk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | pclk | ||||
| 0.000 | 0.000 | tCL | RR | 10163 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK |
| 1.513 | 1.513 | tNET | RR | 1 | R68C39[1][B] | UserLayer_top_inst/ControlTransfer_inst/wValue_latch_9_s0/CLK |
| 1.789 | 0.275 | tC2Q | RR | 7 | R68C39[1][B] | UserLayer_top_inst/ControlTransfer_inst/wValue_latch_9_s0/Q |
| 2.046 | 0.257 | tNET | RR | 1 | R69C41[2][A] | UserLayer_top_inst/ControlTransfer_inst/n4511_s21/I3 |
| 2.418 | 0.372 | tINS | RR | 10 | R69C41[2][A] | UserLayer_top_inst/ControlTransfer_inst/n4511_s21/F |
| 2.888 | 0.470 | tNET | RR | 1 | R70C47[3][B] | UserLayer_top_inst/ControlTransfer_inst/n4511_s17/I1 |
| 3.263 | 0.375 | tINS | RR | 11 | R70C47[3][B] | UserLayer_top_inst/ControlTransfer_inst/n4511_s17/F |
| 3.609 | 0.346 | tNET | RR | 1 | R70C40[3][B] | UserLayer_top_inst/ControlTransfer_inst/n688_s28/I3 |
| 3.985 | 0.375 | tINS | RR | 6 | R70C40[3][B] | UserLayer_top_inst/ControlTransfer_inst/n688_s28/F |
| 4.329 | 0.344 | tNET | RR | 1 | R64C40[3][B] | UserLayer_top_inst/ControlTransfer_inst/n6333_s3/I1 |
| 4.704 | 0.375 | tINS | RR | 5 | R64C40[3][B] | UserLayer_top_inst/ControlTransfer_inst/n6333_s3/F |
| 4.959 | 0.256 | tNET | RR | 1 | R63C38[3][B] | UserLayer_top_inst/ControlTransfer_inst/n6333_s5/I2 |
| 5.335 | 0.375 | tINS | RR | 64 | R63C38[3][B] | UserLayer_top_inst/ControlTransfer_inst/n6333_s5/F |
| 6.657 | 1.322 | tNET | RR | 1 | R61C41[0][B] | UserLayer_top_inst/ControlTransfer_inst/dwFrameInterval_22_s0/CE |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.250 | 6.250 | active clock edge time | ||||
| 6.250 | 0.000 | pclk | ||||
| 6.250 | 0.000 | tCL | RR | 10163 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK |
| 7.763 | 1.513 | tNET | RR | 1 | R61C41[0][B] | UserLayer_top_inst/ControlTransfer_inst/dwFrameInterval_22_s0/CLK |
| 7.539 | -0.224 | tSu | 1 | R61C41[0][B] | UserLayer_top_inst/ControlTransfer_inst/dwFrameInterval_22_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 6.250 |
| Logic Level | 6 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.513, 100.000% |
| Arrival Data Path Delay | cell: 1.873, 36.413%; route: 2.995, 58.233%; tC2Q: 0.275, 5.354% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.513, 100.000% |
Path63
Path Summary:
| Slack | 0.882 |
| Data Arrival Time | 6.657 |
| Data Required Time | 7.539 |
| From | UserLayer_top_inst/ControlTransfer_inst/wValue_latch_9_s0 |
| To | UserLayer_top_inst/ControlTransfer_inst/dwFrameInterval_31_s0 |
| Launch Clk | pclk:[R] |
| Latch Clk | pclk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | pclk | ||||
| 0.000 | 0.000 | tCL | RR | 10163 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK |
| 1.513 | 1.513 | tNET | RR | 1 | R68C39[1][B] | UserLayer_top_inst/ControlTransfer_inst/wValue_latch_9_s0/CLK |
| 1.789 | 0.275 | tC2Q | RR | 7 | R68C39[1][B] | UserLayer_top_inst/ControlTransfer_inst/wValue_latch_9_s0/Q |
| 2.046 | 0.257 | tNET | RR | 1 | R69C41[2][A] | UserLayer_top_inst/ControlTransfer_inst/n4511_s21/I3 |
| 2.418 | 0.372 | tINS | RR | 10 | R69C41[2][A] | UserLayer_top_inst/ControlTransfer_inst/n4511_s21/F |
| 2.888 | 0.470 | tNET | RR | 1 | R70C47[3][B] | UserLayer_top_inst/ControlTransfer_inst/n4511_s17/I1 |
| 3.263 | 0.375 | tINS | RR | 11 | R70C47[3][B] | UserLayer_top_inst/ControlTransfer_inst/n4511_s17/F |
| 3.609 | 0.346 | tNET | RR | 1 | R70C40[3][B] | UserLayer_top_inst/ControlTransfer_inst/n688_s28/I3 |
| 3.985 | 0.375 | tINS | RR | 6 | R70C40[3][B] | UserLayer_top_inst/ControlTransfer_inst/n688_s28/F |
| 4.329 | 0.344 | tNET | RR | 1 | R64C40[3][B] | UserLayer_top_inst/ControlTransfer_inst/n6333_s3/I1 |
| 4.704 | 0.375 | tINS | RR | 5 | R64C40[3][B] | UserLayer_top_inst/ControlTransfer_inst/n6333_s3/F |
| 4.959 | 0.256 | tNET | RR | 1 | R63C38[3][B] | UserLayer_top_inst/ControlTransfer_inst/n6333_s5/I2 |
| 5.335 | 0.375 | tINS | RR | 64 | R63C38[3][B] | UserLayer_top_inst/ControlTransfer_inst/n6333_s5/F |
| 6.657 | 1.322 | tNET | RR | 1 | R61C41[0][A] | UserLayer_top_inst/ControlTransfer_inst/dwFrameInterval_31_s0/CE |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.250 | 6.250 | active clock edge time | ||||
| 6.250 | 0.000 | pclk | ||||
| 6.250 | 0.000 | tCL | RR | 10163 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK |
| 7.763 | 1.513 | tNET | RR | 1 | R61C41[0][A] | UserLayer_top_inst/ControlTransfer_inst/dwFrameInterval_31_s0/CLK |
| 7.539 | -0.224 | tSu | 1 | R61C41[0][A] | UserLayer_top_inst/ControlTransfer_inst/dwFrameInterval_31_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 6.250 |
| Logic Level | 6 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.513, 100.000% |
| Arrival Data Path Delay | cell: 1.873, 36.413%; route: 2.995, 58.233%; tC2Q: 0.275, 5.354% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.513, 100.000% |
Path64
Path Summary:
| Slack | 0.883 |
| Data Arrival Time | 6.834 |
| Data Required Time | 7.717 |
| From | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_header_pkt_66_s0 |
| To | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_hp_4_s0 |
| Launch Clk | pclk:[R] |
| Latch Clk | pclk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | pclk | ||||
| 0.000 | 0.000 | tCL | RR | 10163 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK |
| 1.513 | 1.513 | tNET | RR | 1 | R3C84[0][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_header_pkt_66_s0/CLK |
| 1.789 | 0.275 | tC2Q | RR | 10 | R3C84[0][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_header_pkt_66_s0/Q |
| 2.075 | 0.286 | tNET | RR | 1 | R4C83[3][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3759_s42/I1 |
| 2.450 | 0.375 | tINS | RR | 2 | R4C83[3][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3759_s42/F |
| 3.174 | 0.724 | tNET | RR | 1 | R4C83[0][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3759_s34/I3 |
| 3.553 | 0.379 | tINS | RR | 1 | R4C83[0][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3759_s34/F |
| 4.761 | 1.208 | tNET | RR | 1 | R6C81[3][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3759_s27/I3 |
| 5.119 | 0.358 | tINS | RR | 2 | R6C81[3][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3759_s27/F |
| 5.511 | 0.392 | tNET | RR | 1 | R8C82[1][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3759_s23/I1 |
| 5.883 | 0.372 | tINS | RR | 1 | R8C82[1][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3759_s23/F |
| 6.021 | 0.139 | tNET | RR | 1 | R8C80[0][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3759_s22/I0 |
| 6.393 | 0.372 | tINS | RR | 2 | R8C80[0][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3759_s22/F |
| 6.834 | 0.441 | tNET | RR | 1 | R7C78[1][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_hp_4_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.250 | 6.250 | active clock edge time | ||||
| 6.250 | 0.000 | pclk | ||||
| 6.250 | 0.000 | tCL | RR | 10163 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK |
| 7.763 | 1.513 | tNET | RR | 1 | R7C78[1][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_hp_4_s0/CLK |
| 7.717 | -0.046 | tSu | 1 | R7C78[1][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_hp_4_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 6.250 |
| Logic Level | 6 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.513, 100.000% |
| Arrival Data Path Delay | cell: 1.856, 34.878%; route: 3.190, 59.946%; tC2Q: 0.275, 5.176% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.513, 100.000% |
Path65
Path Summary:
| Slack | 0.884 |
| Data Arrival Time | 6.655 |
| Data Required Time | 7.539 |
| From | UserLayer_top_inst/ControlTransfer_inst/wValue_latch_9_s0 |
| To | UserLayer_top_inst/ControlTransfer_inst/dwFrameInterval_2_s0 |
| Launch Clk | pclk:[R] |
| Latch Clk | pclk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | pclk | ||||
| 0.000 | 0.000 | tCL | RR | 10163 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK |
| 1.513 | 1.513 | tNET | RR | 1 | R68C39[1][B] | UserLayer_top_inst/ControlTransfer_inst/wValue_latch_9_s0/CLK |
| 1.789 | 0.275 | tC2Q | RR | 7 | R68C39[1][B] | UserLayer_top_inst/ControlTransfer_inst/wValue_latch_9_s0/Q |
| 2.046 | 0.257 | tNET | RR | 1 | R69C41[2][A] | UserLayer_top_inst/ControlTransfer_inst/n4511_s21/I3 |
| 2.418 | 0.372 | tINS | RR | 10 | R69C41[2][A] | UserLayer_top_inst/ControlTransfer_inst/n4511_s21/F |
| 2.888 | 0.470 | tNET | RR | 1 | R70C47[3][B] | UserLayer_top_inst/ControlTransfer_inst/n4511_s17/I1 |
| 3.263 | 0.375 | tINS | RR | 11 | R70C47[3][B] | UserLayer_top_inst/ControlTransfer_inst/n4511_s17/F |
| 3.609 | 0.346 | tNET | RR | 1 | R70C40[3][B] | UserLayer_top_inst/ControlTransfer_inst/n688_s28/I3 |
| 3.985 | 0.375 | tINS | RR | 6 | R70C40[3][B] | UserLayer_top_inst/ControlTransfer_inst/n688_s28/F |
| 4.329 | 0.344 | tNET | RR | 1 | R64C40[3][B] | UserLayer_top_inst/ControlTransfer_inst/n6333_s3/I1 |
| 4.704 | 0.375 | tINS | RR | 5 | R64C40[3][B] | UserLayer_top_inst/ControlTransfer_inst/n6333_s3/F |
| 4.959 | 0.256 | tNET | RR | 1 | R63C38[3][B] | UserLayer_top_inst/ControlTransfer_inst/n6333_s5/I2 |
| 5.335 | 0.375 | tINS | RR | 64 | R63C38[3][B] | UserLayer_top_inst/ControlTransfer_inst/n6333_s5/F |
| 6.655 | 1.320 | tNET | RR | 1 | R62C43[0][A] | UserLayer_top_inst/ControlTransfer_inst/dwFrameInterval_2_s0/CE |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.250 | 6.250 | active clock edge time | ||||
| 6.250 | 0.000 | pclk | ||||
| 6.250 | 0.000 | tCL | RR | 10163 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK |
| 7.763 | 1.513 | tNET | RR | 1 | R62C43[0][A] | UserLayer_top_inst/ControlTransfer_inst/dwFrameInterval_2_s0/CLK |
| 7.539 | -0.224 | tSu | 1 | R62C43[0][A] | UserLayer_top_inst/ControlTransfer_inst/dwFrameInterval_2_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 6.250 |
| Logic Level | 6 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.513, 100.000% |
| Arrival Data Path Delay | cell: 1.873, 36.426%; route: 2.993, 58.218%; tC2Q: 0.275, 5.356% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.513, 100.000% |
Path66
Path Summary:
| Slack | 0.884 |
| Data Arrival Time | 6.655 |
| Data Required Time | 7.539 |
| From | UserLayer_top_inst/ControlTransfer_inst/wValue_latch_9_s0 |
| To | UserLayer_top_inst/ControlTransfer_inst/dwFrameInterval_4_s0 |
| Launch Clk | pclk:[R] |
| Latch Clk | pclk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | pclk | ||||
| 0.000 | 0.000 | tCL | RR | 10163 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK |
| 1.513 | 1.513 | tNET | RR | 1 | R68C39[1][B] | UserLayer_top_inst/ControlTransfer_inst/wValue_latch_9_s0/CLK |
| 1.789 | 0.275 | tC2Q | RR | 7 | R68C39[1][B] | UserLayer_top_inst/ControlTransfer_inst/wValue_latch_9_s0/Q |
| 2.046 | 0.257 | tNET | RR | 1 | R69C41[2][A] | UserLayer_top_inst/ControlTransfer_inst/n4511_s21/I3 |
| 2.418 | 0.372 | tINS | RR | 10 | R69C41[2][A] | UserLayer_top_inst/ControlTransfer_inst/n4511_s21/F |
| 2.888 | 0.470 | tNET | RR | 1 | R70C47[3][B] | UserLayer_top_inst/ControlTransfer_inst/n4511_s17/I1 |
| 3.263 | 0.375 | tINS | RR | 11 | R70C47[3][B] | UserLayer_top_inst/ControlTransfer_inst/n4511_s17/F |
| 3.609 | 0.346 | tNET | RR | 1 | R70C40[3][B] | UserLayer_top_inst/ControlTransfer_inst/n688_s28/I3 |
| 3.985 | 0.375 | tINS | RR | 6 | R70C40[3][B] | UserLayer_top_inst/ControlTransfer_inst/n688_s28/F |
| 4.329 | 0.344 | tNET | RR | 1 | R64C40[3][B] | UserLayer_top_inst/ControlTransfer_inst/n6333_s3/I1 |
| 4.704 | 0.375 | tINS | RR | 5 | R64C40[3][B] | UserLayer_top_inst/ControlTransfer_inst/n6333_s3/F |
| 4.959 | 0.256 | tNET | RR | 1 | R63C38[3][B] | UserLayer_top_inst/ControlTransfer_inst/n6333_s5/I2 |
| 5.335 | 0.375 | tINS | RR | 64 | R63C38[3][B] | UserLayer_top_inst/ControlTransfer_inst/n6333_s5/F |
| 6.655 | 1.320 | tNET | RR | 1 | R62C43[0][B] | UserLayer_top_inst/ControlTransfer_inst/dwFrameInterval_4_s0/CE |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.250 | 6.250 | active clock edge time | ||||
| 6.250 | 0.000 | pclk | ||||
| 6.250 | 0.000 | tCL | RR | 10163 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK |
| 7.763 | 1.513 | tNET | RR | 1 | R62C43[0][B] | UserLayer_top_inst/ControlTransfer_inst/dwFrameInterval_4_s0/CLK |
| 7.539 | -0.224 | tSu | 1 | R62C43[0][B] | UserLayer_top_inst/ControlTransfer_inst/dwFrameInterval_4_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 6.250 |
| Logic Level | 6 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.513, 100.000% |
| Arrival Data Path Delay | cell: 1.873, 36.426%; route: 2.993, 58.218%; tC2Q: 0.275, 5.356% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.513, 100.000% |
Path67
Path Summary:
| Slack | 0.897 |
| Data Arrival Time | 6.649 |
| Data Required Time | 7.546 |
| From | UserLayer_top_inst/ControlTransfer_inst/wValue_latch_9_s0 |
| To | UserLayer_top_inst/ControlTransfer_inst/dwMaxVideoFrameSize_0_s0 |
| Launch Clk | pclk:[R] |
| Latch Clk | pclk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | pclk | ||||
| 0.000 | 0.000 | tCL | RR | 10163 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK |
| 1.513 | 1.513 | tNET | RR | 1 | R68C39[1][B] | UserLayer_top_inst/ControlTransfer_inst/wValue_latch_9_s0/CLK |
| 1.789 | 0.275 | tC2Q | RR | 7 | R68C39[1][B] | UserLayer_top_inst/ControlTransfer_inst/wValue_latch_9_s0/Q |
| 2.046 | 0.257 | tNET | RR | 1 | R69C41[2][A] | UserLayer_top_inst/ControlTransfer_inst/n4511_s21/I3 |
| 2.418 | 0.372 | tINS | RR | 10 | R69C41[2][A] | UserLayer_top_inst/ControlTransfer_inst/n4511_s21/F |
| 2.888 | 0.470 | tNET | RR | 1 | R70C47[3][B] | UserLayer_top_inst/ControlTransfer_inst/n4511_s17/I1 |
| 3.263 | 0.375 | tINS | RR | 11 | R70C47[3][B] | UserLayer_top_inst/ControlTransfer_inst/n4511_s17/F |
| 3.609 | 0.346 | tNET | RR | 1 | R70C40[3][B] | UserLayer_top_inst/ControlTransfer_inst/n688_s28/I3 |
| 3.985 | 0.375 | tINS | RR | 6 | R70C40[3][B] | UserLayer_top_inst/ControlTransfer_inst/n688_s28/F |
| 4.329 | 0.344 | tNET | RR | 1 | R64C40[3][B] | UserLayer_top_inst/ControlTransfer_inst/n6333_s3/I1 |
| 4.704 | 0.375 | tINS | RR | 5 | R64C40[3][B] | UserLayer_top_inst/ControlTransfer_inst/n6333_s3/F |
| 4.983 | 0.279 | tNET | RR | 1 | R62C38[3][B] | UserLayer_top_inst/ControlTransfer_inst/n6461_s1/I2 |
| 5.358 | 0.375 | tINS | RR | 48 | R62C38[3][B] | UserLayer_top_inst/ControlTransfer_inst/n6461_s1/F |
| 6.649 | 1.291 | tNET | RR | 1 | R61C50[0][B] | UserLayer_top_inst/ControlTransfer_inst/dwMaxVideoFrameSize_0_s0/CE |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.250 | 6.250 | active clock edge time | ||||
| 6.250 | 0.000 | pclk | ||||
| 6.250 | 0.000 | tCL | RR | 10163 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK |
| 7.770 | 1.520 | tNET | RR | 1 | R61C50[0][B] | UserLayer_top_inst/ControlTransfer_inst/dwMaxVideoFrameSize_0_s0/CLK |
| 7.546 | -0.224 | tSu | 1 | R61C50[0][B] | UserLayer_top_inst/ControlTransfer_inst/dwMaxVideoFrameSize_0_s0 |
Path Statistics:
| Clock Skew | 0.007 |
| Setup Relationship | 6.250 |
| Logic Level | 6 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.513, 100.000% |
| Arrival Data Path Delay | cell: 1.873, 36.470%; route: 2.987, 58.167%; tC2Q: 0.275, 5.363% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.520, 100.000% |
Path68
Path Summary:
| Slack | 0.897 |
| Data Arrival Time | 6.649 |
| Data Required Time | 7.546 |
| From | UserLayer_top_inst/ControlTransfer_inst/wValue_latch_9_s0 |
| To | UserLayer_top_inst/ControlTransfer_inst/dwMaxVideoFrameSize_3_s0 |
| Launch Clk | pclk:[R] |
| Latch Clk | pclk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | pclk | ||||
| 0.000 | 0.000 | tCL | RR | 10163 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK |
| 1.513 | 1.513 | tNET | RR | 1 | R68C39[1][B] | UserLayer_top_inst/ControlTransfer_inst/wValue_latch_9_s0/CLK |
| 1.789 | 0.275 | tC2Q | RR | 7 | R68C39[1][B] | UserLayer_top_inst/ControlTransfer_inst/wValue_latch_9_s0/Q |
| 2.046 | 0.257 | tNET | RR | 1 | R69C41[2][A] | UserLayer_top_inst/ControlTransfer_inst/n4511_s21/I3 |
| 2.418 | 0.372 | tINS | RR | 10 | R69C41[2][A] | UserLayer_top_inst/ControlTransfer_inst/n4511_s21/F |
| 2.888 | 0.470 | tNET | RR | 1 | R70C47[3][B] | UserLayer_top_inst/ControlTransfer_inst/n4511_s17/I1 |
| 3.263 | 0.375 | tINS | RR | 11 | R70C47[3][B] | UserLayer_top_inst/ControlTransfer_inst/n4511_s17/F |
| 3.609 | 0.346 | tNET | RR | 1 | R70C40[3][B] | UserLayer_top_inst/ControlTransfer_inst/n688_s28/I3 |
| 3.985 | 0.375 | tINS | RR | 6 | R70C40[3][B] | UserLayer_top_inst/ControlTransfer_inst/n688_s28/F |
| 4.329 | 0.344 | tNET | RR | 1 | R64C40[3][B] | UserLayer_top_inst/ControlTransfer_inst/n6333_s3/I1 |
| 4.704 | 0.375 | tINS | RR | 5 | R64C40[3][B] | UserLayer_top_inst/ControlTransfer_inst/n6333_s3/F |
| 4.983 | 0.279 | tNET | RR | 1 | R62C38[3][B] | UserLayer_top_inst/ControlTransfer_inst/n6461_s1/I2 |
| 5.358 | 0.375 | tINS | RR | 48 | R62C38[3][B] | UserLayer_top_inst/ControlTransfer_inst/n6461_s1/F |
| 6.649 | 1.291 | tNET | RR | 1 | R61C50[0][A] | UserLayer_top_inst/ControlTransfer_inst/dwMaxVideoFrameSize_3_s0/CE |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.250 | 6.250 | active clock edge time | ||||
| 6.250 | 0.000 | pclk | ||||
| 6.250 | 0.000 | tCL | RR | 10163 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK |
| 7.770 | 1.520 | tNET | RR | 1 | R61C50[0][A] | UserLayer_top_inst/ControlTransfer_inst/dwMaxVideoFrameSize_3_s0/CLK |
| 7.546 | -0.224 | tSu | 1 | R61C50[0][A] | UserLayer_top_inst/ControlTransfer_inst/dwMaxVideoFrameSize_3_s0 |
Path Statistics:
| Clock Skew | 0.007 |
| Setup Relationship | 6.250 |
| Logic Level | 6 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.513, 100.000% |
| Arrival Data Path Delay | cell: 1.873, 36.470%; route: 2.987, 58.167%; tC2Q: 0.275, 5.363% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.520, 100.000% |
Path69
Path Summary:
| Slack | 0.902 |
| Data Arrival Time | 7.837 |
| Data Required Time | 8.739 |
| From | DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_3_s0 |
| To | DDR3_Memory_Interface_Top_inst/gw3_top/u_gwmc_top/gw_wr_data0/wr_buf_din_8_s0 |
| Launch Clk | dma_clk:[R] |
| Latch Clk | dma_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | dma_clk | ||||
| 0.000 | 0.000 | tCL | RR | 3995 | BOTTOMSIDE[0] | DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 1.518 | 1.518 | tNET | RR | 1 | R60C21[0][B] | DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_3_s0/CLK |
| 1.794 | 0.275 | tC2Q | RR | 326 | R60C21[0][B] | DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_3_s0/Q |
| 5.019 | 3.225 | tNET | RR | 1 | R39C19[1][A] | u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u_dma_bus_arbiter/next_state.ST_IFF0_WRITE_DDR_s1/I3 |
| 5.188 | 0.169 | tINS | RF | 155 | R39C19[1][A] | u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u_dma_bus_arbiter/next_state.ST_IFF0_WRITE_DDR_s1/F |
| 6.806 | 1.618 | tNET | FF | 1 | R54C9[2][B] | u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u_dma_bus_arbiter/O_wr_data_d_8_s/I1 |
| 7.138 | 0.332 | tINS | FR | 1 | R54C9[2][B] | u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u_dma_bus_arbiter/O_wr_data_d_8_s/F |
| 7.465 | 0.328 | tNET | RR | 1 | R54C18[0][A] | DDR3_Memory_Interface_Top_inst/gw3_top/u_gwmc_top/gw_wr_data0/n465_s0/I0 |
| 7.837 | 0.372 | tINS | RR | 1 | R54C18[0][A] | DDR3_Memory_Interface_Top_inst/gw3_top/u_gwmc_top/gw_wr_data0/n465_s0/F |
| 7.837 | 0.000 | tNET | RR | 1 | R54C18[0][A] | DDR3_Memory_Interface_Top_inst/gw3_top/u_gwmc_top/gw_wr_data0/wr_buf_din_8_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 7.273 | 7.273 | active clock edge time | ||||
| 7.273 | 0.000 | dma_clk | ||||
| 7.273 | 0.000 | tCL | RR | 3995 | BOTTOMSIDE[0] | DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 8.785 | 1.512 | tNET | RR | 1 | R54C18[0][A] | DDR3_Memory_Interface_Top_inst/gw3_top/u_gwmc_top/gw_wr_data0/wr_buf_din_8_s0/CLK |
| 8.739 | -0.046 | tSu | 1 | R54C18[0][A] | DDR3_Memory_Interface_Top_inst/gw3_top/u_gwmc_top/gw_wr_data0/wr_buf_din_8_s0 |
Path Statistics:
| Clock Skew | -0.007 |
| Setup Relationship | 7.273 |
| Logic Level | 4 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.518, 100.000% |
| Arrival Data Path Delay | cell: 0.873, 13.816%; route: 5.170, 81.825%; tC2Q: 0.275, 4.359% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.512, 100.000% |
Path70
Path Summary:
| Slack | 0.914 |
| Data Arrival Time | 6.619 |
| Data Required Time | 7.532 |
| From | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/recv_u0_adv_GEN2_s0 |
| To | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/hp_rd_s0 |
| Launch Clk | pclk:[R] |
| Latch Clk | pclk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | pclk | ||||
| 0.000 | 0.000 | tCL | RR | 10163 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK |
| 1.520 | 1.520 | tNET | RR | 1 | R39C103[1][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/recv_u0_adv_GEN2_s0/CLK |
| 1.795 | 0.275 | tC2Q | RR | 5 | R39C103[1][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/recv_u0_adv_GEN2_s0/Q |
| 2.078 | 0.283 | tNET | RR | 1 | R41C101[1][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n2005_s25/I0 |
| 2.450 | 0.372 | tINS | RR | 2 | R41C101[1][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n2005_s25/F |
| 2.968 | 0.518 | tNET | RR | 1 | R41C89[3][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n2005_s21/I3 |
| 3.343 | 0.375 | tINS | RR | 1 | R41C89[3][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n2005_s21/F |
| 3.457 | 0.113 | tNET | RR | 1 | R41C88[2][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n2005_s18/I2 |
| 3.789 | 0.332 | tINS | RR | 4 | R41C88[2][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n2005_s18/F |
| 4.747 | 0.958 | tNET | RR | 1 | R15C91[1][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/hp_rd_s4/I0 |
| 5.125 | 0.379 | tINS | RR | 1 | R15C91[1][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/hp_rd_s4/F |
| 5.872 | 0.747 | tNET | RR | 1 | R11C107[3][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/hp_rd_s9/I0 |
| 6.248 | 0.375 | tINS | RR | 1 | R11C107[3][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/hp_rd_s9/F |
| 6.619 | 0.371 | tNET | RR | 1 | R11C101[2][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/hp_rd_s0/CE |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.250 | 6.250 | active clock edge time | ||||
| 6.250 | 0.000 | pclk | ||||
| 6.250 | 0.000 | tCL | RR | 10163 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK |
| 7.757 | 1.507 | tNET | RR | 1 | R11C101[2][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/hp_rd_s0/CLK |
| 7.532 | -0.224 | tSu | 1 | R11C101[2][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/hp_rd_s0 |
Path Statistics:
| Clock Skew | -0.014 |
| Setup Relationship | 6.250 |
| Logic Level | 6 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.520, 100.000% |
| Arrival Data Path Delay | cell: 1.833, 35.958%; route: 2.990, 58.641%; tC2Q: 0.275, 5.402% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.507, 100.000% |
Path71
Path Summary:
| Slack | 0.921 |
| Data Arrival Time | 6.618 |
| Data Required Time | 7.539 |
| From | UserLayer_top_inst/ControlTransfer_inst/wValue_latch_9_s0 |
| To | UserLayer_top_inst/ControlTransfer_inst/wDelay_3_s0 |
| Launch Clk | pclk:[R] |
| Latch Clk | pclk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | pclk | ||||
| 0.000 | 0.000 | tCL | RR | 10163 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK |
| 1.513 | 1.513 | tNET | RR | 1 | R68C39[1][B] | UserLayer_top_inst/ControlTransfer_inst/wValue_latch_9_s0/CLK |
| 1.789 | 0.275 | tC2Q | RR | 7 | R68C39[1][B] | UserLayer_top_inst/ControlTransfer_inst/wValue_latch_9_s0/Q |
| 2.046 | 0.257 | tNET | RR | 1 | R69C41[2][A] | UserLayer_top_inst/ControlTransfer_inst/n4511_s21/I3 |
| 2.418 | 0.372 | tINS | RR | 10 | R69C41[2][A] | UserLayer_top_inst/ControlTransfer_inst/n4511_s21/F |
| 2.888 | 0.470 | tNET | RR | 1 | R70C47[3][B] | UserLayer_top_inst/ControlTransfer_inst/n4511_s17/I1 |
| 3.263 | 0.375 | tINS | RR | 11 | R70C47[3][B] | UserLayer_top_inst/ControlTransfer_inst/n4511_s17/F |
| 3.609 | 0.346 | tNET | RR | 1 | R70C40[3][B] | UserLayer_top_inst/ControlTransfer_inst/n688_s28/I3 |
| 3.985 | 0.375 | tINS | RR | 6 | R70C40[3][B] | UserLayer_top_inst/ControlTransfer_inst/n688_s28/F |
| 4.329 | 0.344 | tNET | RR | 1 | R64C40[3][B] | UserLayer_top_inst/ControlTransfer_inst/n6333_s3/I1 |
| 4.704 | 0.375 | tINS | RR | 5 | R64C40[3][B] | UserLayer_top_inst/ControlTransfer_inst/n6333_s3/F |
| 4.983 | 0.279 | tNET | RR | 1 | R62C38[3][B] | UserLayer_top_inst/ControlTransfer_inst/n6461_s1/I2 |
| 5.358 | 0.375 | tINS | RR | 48 | R62C38[3][B] | UserLayer_top_inst/ControlTransfer_inst/n6461_s1/F |
| 6.618 | 1.260 | tNET | RR | 1 | R66C45[0][A] | UserLayer_top_inst/ControlTransfer_inst/wDelay_3_s0/CE |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.250 | 6.250 | active clock edge time | ||||
| 6.250 | 0.000 | pclk | ||||
| 6.250 | 0.000 | tCL | RR | 10163 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK |
| 7.763 | 1.513 | tNET | RR | 1 | R66C45[0][A] | UserLayer_top_inst/ControlTransfer_inst/wDelay_3_s0/CLK |
| 7.539 | -0.224 | tSu | 1 | R66C45[0][A] | UserLayer_top_inst/ControlTransfer_inst/wDelay_3_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 6.250 |
| Logic Level | 6 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.513, 100.000% |
| Arrival Data Path Delay | cell: 1.873, 36.689%; route: 2.957, 57.916%; tC2Q: 0.275, 5.395% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.513, 100.000% |
Path72
Path Summary:
| Slack | 0.921 |
| Data Arrival Time | 6.618 |
| Data Required Time | 7.539 |
| From | UserLayer_top_inst/ControlTransfer_inst/wValue_latch_9_s0 |
| To | UserLayer_top_inst/ControlTransfer_inst/wDelay_5_s0 |
| Launch Clk | pclk:[R] |
| Latch Clk | pclk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | pclk | ||||
| 0.000 | 0.000 | tCL | RR | 10163 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK |
| 1.513 | 1.513 | tNET | RR | 1 | R68C39[1][B] | UserLayer_top_inst/ControlTransfer_inst/wValue_latch_9_s0/CLK |
| 1.789 | 0.275 | tC2Q | RR | 7 | R68C39[1][B] | UserLayer_top_inst/ControlTransfer_inst/wValue_latch_9_s0/Q |
| 2.046 | 0.257 | tNET | RR | 1 | R69C41[2][A] | UserLayer_top_inst/ControlTransfer_inst/n4511_s21/I3 |
| 2.418 | 0.372 | tINS | RR | 10 | R69C41[2][A] | UserLayer_top_inst/ControlTransfer_inst/n4511_s21/F |
| 2.888 | 0.470 | tNET | RR | 1 | R70C47[3][B] | UserLayer_top_inst/ControlTransfer_inst/n4511_s17/I1 |
| 3.263 | 0.375 | tINS | RR | 11 | R70C47[3][B] | UserLayer_top_inst/ControlTransfer_inst/n4511_s17/F |
| 3.609 | 0.346 | tNET | RR | 1 | R70C40[3][B] | UserLayer_top_inst/ControlTransfer_inst/n688_s28/I3 |
| 3.985 | 0.375 | tINS | RR | 6 | R70C40[3][B] | UserLayer_top_inst/ControlTransfer_inst/n688_s28/F |
| 4.329 | 0.344 | tNET | RR | 1 | R64C40[3][B] | UserLayer_top_inst/ControlTransfer_inst/n6333_s3/I1 |
| 4.704 | 0.375 | tINS | RR | 5 | R64C40[3][B] | UserLayer_top_inst/ControlTransfer_inst/n6333_s3/F |
| 4.983 | 0.279 | tNET | RR | 1 | R62C38[3][B] | UserLayer_top_inst/ControlTransfer_inst/n6461_s1/I2 |
| 5.358 | 0.375 | tINS | RR | 48 | R62C38[3][B] | UserLayer_top_inst/ControlTransfer_inst/n6461_s1/F |
| 6.618 | 1.260 | tNET | RR | 1 | R66C45[0][B] | UserLayer_top_inst/ControlTransfer_inst/wDelay_5_s0/CE |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.250 | 6.250 | active clock edge time | ||||
| 6.250 | 0.000 | pclk | ||||
| 6.250 | 0.000 | tCL | RR | 10163 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK |
| 7.763 | 1.513 | tNET | RR | 1 | R66C45[0][B] | UserLayer_top_inst/ControlTransfer_inst/wDelay_5_s0/CLK |
| 7.539 | -0.224 | tSu | 1 | R66C45[0][B] | UserLayer_top_inst/ControlTransfer_inst/wDelay_5_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 6.250 |
| Logic Level | 6 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.513, 100.000% |
| Arrival Data Path Delay | cell: 1.873, 36.689%; route: 2.957, 57.916%; tC2Q: 0.275, 5.395% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.513, 100.000% |
Path73
Path Summary:
| Slack | 0.924 |
| Data Arrival Time | 6.800 |
| Data Required Time | 7.724 |
| From | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/in_dpp_length_expect_4_s0 |
| To | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/in_dpp_length_9_s1 |
| Launch Clk | pclk:[R] |
| Latch Clk | pclk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | pclk | ||||
| 0.000 | 0.000 | tCL | RR | 10163 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK |
| 1.513 | 1.513 | tNET | RR | 1 | R24C100[2][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/in_dpp_length_expect_4_s0/CLK |
| 1.789 | 0.275 | tC2Q | RR | 9 | R24C100[2][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/in_dpp_length_expect_4_s0/Q |
| 2.264 | 0.475 | tNET | RR | 1 | R30C100[0][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n16661_s7/I2 |
| 2.643 | 0.379 | tINS | RR | 6 | R30C100[0][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n16661_s7/F |
| 2.813 | 0.170 | tNET | RR | 1 | R30C102[3][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n16659_s6/I2 |
| 3.022 | 0.209 | tINS | RF | 4 | R30C102[3][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n16659_s6/F |
| 3.036 | 0.014 | tNET | FF | 1 | R30C102[2][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n16737_s6/I0 |
| 3.368 | 0.332 | tINS | FR | 3 | R30C102[2][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n16737_s6/F |
| 3.919 | 0.551 | tNET | RR | 1 | R40C100[3][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n16652_s13/I3 |
| 4.294 | 0.375 | tINS | RR | 8 | R40C100[3][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n16652_s13/F |
| 4.972 | 0.678 | tNET | RR | 1 | R30C103[0][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n16658_s6/I3 |
| 5.304 | 0.332 | tINS | RR | 1 | R30C103[0][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n16658_s6/F |
| 5.971 | 0.667 | tNET | RR | 1 | R43C103[0][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n16658_s4/I3 |
| 6.343 | 0.372 | tINS | RR | 1 | R43C103[0][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n16658_s4/F |
| 6.442 | 0.099 | tNET | RR | 1 | R43C103[3][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n16658_s3/I0 |
| 6.800 | 0.358 | tINS | RR | 1 | R43C103[3][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n16658_s3/F |
| 6.800 | 0.000 | tNET | RR | 1 | R43C103[3][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/in_dpp_length_9_s1/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.250 | 6.250 | active clock edge time | ||||
| 6.250 | 0.000 | pclk | ||||
| 6.250 | 0.000 | tCL | RR | 10163 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK |
| 7.770 | 1.520 | tNET | RR | 1 | R43C103[3][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/in_dpp_length_9_s1/CLK |
| 7.724 | -0.046 | tSu | 1 | R43C103[3][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/in_dpp_length_9_s1 |
Path Statistics:
| Clock Skew | 0.007 |
| Setup Relationship | 6.250 |
| Logic Level | 8 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.513, 100.000% |
| Arrival Data Path Delay | cell: 2.357, 44.586%; route: 2.654, 50.204%; tC2Q: 0.275, 5.209% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.520, 100.000% |
Path74
Path Summary:
| Slack | 0.931 |
| Data Arrival Time | 6.601 |
| Data Required Time | 7.532 |
| From | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_word_alignment/data_in_r0_3_s0 |
| To | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_word_alignment/cnt0_3_s1 |
| Launch Clk | q0_lane1_fabric_rx_clk:[R] |
| Latch Clk | q0_lane1_fabric_rx_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | q0_lane1_fabric_rx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 518 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_RX_O_FABRIC_CLK |
| 1.513 | 1.513 | tNET | RR | 1 | R25C81[3][A] | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_word_alignment/data_in_r0_3_s0/CLK |
| 1.789 | 0.275 | tC2Q | RR | 13 | R25C81[3][A] | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_word_alignment/data_in_r0_3_s0/Q |
| 2.392 | 0.603 | tNET | RR | 1 | R27C80[3][B] | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_word_alignment/cnt0_3_s61/I0 |
| 2.691 | 0.299 | tINS | RR | 2 | R27C80[3][B] | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_word_alignment/cnt0_3_s61/F |
| 2.806 | 0.115 | tNET | RR | 1 | R26C80[1][A] | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_word_alignment/cnt0_3_s58/I3 |
| 3.177 | 0.372 | tINS | RR | 2 | R26C80[1][A] | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_word_alignment/cnt0_3_s58/F |
| 3.728 | 0.551 | tNET | RR | 1 | R25C81[0][B] | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_word_alignment/cnt0_3_s27/I1 |
| 4.100 | 0.372 | tINS | RR | 2 | R25C81[0][B] | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_word_alignment/cnt0_3_s27/F |
| 4.798 | 0.698 | tNET | RR | 1 | R25C82[2][B] | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_word_alignment/cnt0_3_s10/I2 |
| 5.170 | 0.372 | tINS | RR | 2 | R25C82[2][B] | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_word_alignment/cnt0_3_s10/F |
| 5.732 | 0.562 | tNET | RR | 1 | R25C82[3][A] | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_word_alignment/cnt0_3_s4/I3 |
| 5.940 | 0.209 | tINS | RF | 2 | R25C82[3][A] | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_word_alignment/cnt0_3_s4/F |
| 6.200 | 0.259 | tNET | FF | 1 | R25C84[3][A] | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_word_alignment/cnt0_3_s3/I0 |
| 6.498 | 0.299 | tINS | FR | 5 | R25C84[3][A] | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_word_alignment/cnt0_3_s3/F |
| 6.601 | 0.103 | tNET | RR | 1 | R25C84[1][A] | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_word_alignment/cnt0_3_s1/CE |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.250 | 6.250 | active clock edge time | ||||
| 6.250 | 0.000 | q0_lane1_fabric_rx_clk | ||||
| 6.250 | 0.000 | tCL | RR | 518 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_RX_O_FABRIC_CLK |
| 7.757 | 1.507 | tNET | RR | 1 | R25C84[1][A] | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_word_alignment/cnt0_3_s1/CLK |
| 7.532 | -0.224 | tSu | 1 | R25C84[1][A] | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_word_alignment/cnt0_3_s1 |
Path Statistics:
| Clock Skew | -0.007 |
| Setup Relationship | 6.250 |
| Logic Level | 7 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.513, 100.000% |
| Arrival Data Path Delay | cell: 1.921, 37.768%; route: 2.891, 56.819%; tC2Q: 0.275, 5.413% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.507, 100.000% |
Path75
Path Summary:
| Slack | 0.934 |
| Data Arrival Time | 6.784 |
| Data Required Time | 7.717 |
| From | UserLayer_top_inst/ControlTransfer_inst/bmRequestType_latch_1_s0 |
| To | UserLayer_top_inst/ControlTransfer_inst/transfer_in_data_mux_7_s0 |
| Launch Clk | pclk:[R] |
| Latch Clk | pclk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | pclk | ||||
| 0.000 | 0.000 | tCL | RR | 10163 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK |
| 1.513 | 1.513 | tNET | RR | 1 | R55C39[1][B] | UserLayer_top_inst/ControlTransfer_inst/bmRequestType_latch_1_s0/CLK |
| 1.789 | 0.275 | tC2Q | RR | 1 | R55C39[1][B] | UserLayer_top_inst/ControlTransfer_inst/bmRequestType_latch_1_s0/Q |
| 2.123 | 0.334 | tNET | RR | 1 | R57C41[3][A] | UserLayer_top_inst/ControlTransfer_inst/n4443_s20/I0 |
| 2.481 | 0.358 | tINS | RR | 2 | R57C41[3][A] | UserLayer_top_inst/ControlTransfer_inst/n4443_s20/F |
| 3.030 | 0.549 | tNET | RR | 1 | R72C42[3][A] | UserLayer_top_inst/ControlTransfer_inst/n4443_s18/I3 |
| 3.405 | 0.375 | tINS | RR | 5 | R72C42[3][A] | UserLayer_top_inst/ControlTransfer_inst/n4443_s18/F |
| 4.152 | 0.747 | tNET | RR | 1 | R66C47[3][B] | UserLayer_top_inst/ControlTransfer_inst/n4443_s17/I1 |
| 4.510 | 0.358 | tINS | RR | 48 | R66C47[3][B] | UserLayer_top_inst/ControlTransfer_inst/n4443_s17/F |
| 5.010 | 0.499 | tNET | RR | 1 | R68C42[0][B] | UserLayer_top_inst/ControlTransfer_inst/n4507_s21/I2 |
| 5.389 | 0.379 | tINS | RR | 15 | R68C42[0][B] | UserLayer_top_inst/ControlTransfer_inst/n4507_s21/F |
| 5.916 | 0.527 | tNET | RR | 1 | R66C48[3][A] | UserLayer_top_inst/ControlTransfer_inst/n4523_s11/I3 |
| 6.291 | 0.375 | tINS | RR | 1 | R66C48[3][A] | UserLayer_top_inst/ControlTransfer_inst/n4523_s11/F |
| 6.405 | 0.113 | tNET | RR | 1 | R66C47[2][B] | UserLayer_top_inst/ControlTransfer_inst/n4523_s10/I2 |
| 6.784 | 0.379 | tINS | RR | 1 | R66C47[2][B] | UserLayer_top_inst/ControlTransfer_inst/n4523_s10/F |
| 6.784 | 0.000 | tNET | RR | 1 | R66C47[2][B] | UserLayer_top_inst/ControlTransfer_inst/transfer_in_data_mux_7_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.250 | 6.250 | active clock edge time | ||||
| 6.250 | 0.000 | pclk | ||||
| 6.250 | 0.000 | tCL | RR | 10163 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK |
| 7.763 | 1.513 | tNET | RR | 1 | R66C47[2][B] | UserLayer_top_inst/ControlTransfer_inst/transfer_in_data_mux_7_s0/CLK |
| 7.717 | -0.046 | tSu | 1 | R66C47[2][B] | UserLayer_top_inst/ControlTransfer_inst/transfer_in_data_mux_7_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 6.250 |
| Logic Level | 7 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.513, 100.000% |
| Arrival Data Path Delay | cell: 2.225, 42.213%; route: 2.770, 52.561%; tC2Q: 0.275, 5.225% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.513, 100.000% |
Path76
Path Summary:
| Slack | 0.934 |
| Data Arrival Time | 6.783 |
| Data Required Time | 7.717 |
| From | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_header_pkt_69_s0 |
| To | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_hp_7_s1 |
| Launch Clk | pclk:[R] |
| Latch Clk | pclk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | pclk | ||||
| 0.000 | 0.000 | tCL | RR | 10163 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK |
| 1.520 | 1.520 | tNET | RR | 1 | R4C83[1][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_header_pkt_69_s0/CLK |
| 1.795 | 0.275 | tC2Q | RR | 9 | R4C83[1][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_header_pkt_69_s0/Q |
| 2.301 | 0.506 | tNET | RR | 1 | R3C81[2][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3748_s52/I0 |
| 2.680 | 0.379 | tINS | RR | 4 | R3C81[2][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3748_s52/F |
| 3.227 | 0.547 | tNET | RR | 1 | R3C82[3][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3756_s47/I1 |
| 3.586 | 0.358 | tINS | RR | 1 | R3C82[3][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3756_s47/F |
| 3.587 | 0.002 | tNET | RR | 1 | R3C82[2][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3756_s39/I0 |
| 3.919 | 0.332 | tINS | RR | 1 | R3C82[2][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3756_s39/F |
| 4.306 | 0.387 | tNET | RR | 1 | R3C81[1][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3756_s34/I3 |
| 4.639 | 0.332 | tINS | RR | 2 | R3C81[1][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3756_s34/F |
| 5.087 | 0.448 | tNET | RR | 1 | R6C82[3][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3756_s31/I1 |
| 5.445 | 0.358 | tINS | RR | 1 | R6C82[3][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3756_s31/F |
| 6.451 | 1.006 | tNET | RR | 1 | R7C82[1][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3756_s30/I0 |
| 6.783 | 0.332 | tINS | RR | 1 | R7C82[1][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3756_s30/F |
| 6.783 | 0.000 | tNET | RR | 1 | R7C82[1][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_hp_7_s1/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.250 | 6.250 | active clock edge time | ||||
| 6.250 | 0.000 | pclk | ||||
| 6.250 | 0.000 | tCL | RR | 10163 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK |
| 7.763 | 1.513 | tNET | RR | 1 | R7C82[1][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_hp_7_s1/CLK |
| 7.717 | -0.046 | tSu | 1 | R7C82[1][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_hp_7_s1 |
Path Statistics:
| Clock Skew | -0.007 |
| Setup Relationship | 6.250 |
| Logic Level | 7 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.520, 100.000% |
| Arrival Data Path Delay | cell: 2.092, 39.740%; route: 2.896, 55.027%; tC2Q: 0.275, 5.233% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.513, 100.000% |
Path77
Path Summary:
| Slack | 0.941 |
| Data Arrival Time | 6.598 |
| Data Required Time | 7.539 |
| From | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/ack_tx_hdr_seq_num_3_s0 |
| To | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/resend_hp_act_s1 |
| Launch Clk | pclk:[R] |
| Latch Clk | pclk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | pclk | ||||
| 0.000 | 0.000 | tCL | RR | 10163 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK |
| 1.513 | 1.513 | tNET | RR | 1 | R36C96[0][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/ack_tx_hdr_seq_num_3_s0/CLK |
| 1.778 | 0.265 | tC2Q | RF | 4 | R36C96[0][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/ack_tx_hdr_seq_num_3_s0/Q |
| 3.449 | 1.671 | tNET | FF | 2 | R2C75[1][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n23157_s2/I1 |
| 3.854 | 0.405 | tINS | FF | 1 | R2C75[1][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n23157_s2/COUT |
| 5.569 | 1.715 | tNET | FF | 1 | R51C87[3][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n40805_s0/I1 |
| 5.778 | 0.209 | tINS | FF | 2 | R51C87[3][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n40805_s0/F |
| 5.884 | 0.106 | tNET | FF | 1 | R51C86[3][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/resend_hp_act_s3/I3 |
| 6.183 | 0.299 | tINS | FR | 1 | R51C86[3][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/resend_hp_act_s3/F |
| 6.598 | 0.416 | tNET | RR | 1 | R41C86[0][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/resend_hp_act_s1/CE |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.250 | 6.250 | active clock edge time | ||||
| 6.250 | 0.000 | pclk | ||||
| 6.250 | 0.000 | tCL | RR | 10163 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK |
| 7.763 | 1.513 | tNET | RR | 1 | R41C86[0][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/resend_hp_act_s1/CLK |
| 7.539 | -0.224 | tSu | 1 | R41C86[0][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/resend_hp_act_s1 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 6.250 |
| Logic Level | 4 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.513, 100.000% |
| Arrival Data Path Delay | cell: 0.913, 17.947%; route: 3.908, 76.850%; tC2Q: 0.265, 5.204% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.513, 100.000% |
Path78
Path Summary:
| Slack | 0.950 |
| Data Arrival Time | 6.939 |
| Data Required Time | 7.889 |
| From | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0 |
| To | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/tx_hp_word_1_2_s0 |
| Launch Clk | pclk:[R] |
| Latch Clk | pclk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | pclk | ||||
| 0.000 | 0.000 | tCL | RR | 10163 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK |
| 1.520 | 1.520 | tNET | RR | 1 | R44C83[1][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/CLK |
| 1.795 | 0.275 | tC2Q | RR | 2598 | R44C83[1][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/Q |
| 3.675 | 1.880 | tNET | RR | 1 | R11C87[2][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/tx_hp_word_0_31_s3/I0 |
| 4.054 | 0.379 | tINS | RR | 90 | R11C87[2][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/tx_hp_word_0_31_s3/F |
| 5.022 | 0.968 | tNET | RR | 1 | R6C88[3][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/tx_hp_word_0_6_s5/I0 |
| 5.397 | 0.375 | tINS | RR | 7 | R6C88[3][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/tx_hp_word_0_6_s5/F |
| 6.939 | 1.542 | tNET | RR | 1 | R31C64[3][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/tx_hp_word_1_2_s0/CE |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.250 | 6.250 | active clock edge time | ||||
| 6.250 | 0.000 | pclk | ||||
| 6.250 | 0.000 | tCL | RR | 10163 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK |
| 8.113 | 1.863 | tNET | RR | 1 | R31C64[3][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/tx_hp_word_1_2_s0/CLK |
| 7.889 | -0.224 | tSu | 1 | R31C64[3][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/tx_hp_word_1_2_s0 |
Path Statistics:
| Clock Skew | 0.343 |
| Setup Relationship | 6.250 |
| Logic Level | 3 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.520, 100.000% |
| Arrival Data Path Delay | cell: 0.754, 13.918%; route: 4.389, 81.000%; tC2Q: 0.275, 5.082% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.863, 100.000% |
Path79
Path Summary:
| Slack | 0.953 |
| Data Arrival Time | 7.792 |
| Data Required Time | 8.745 |
| From | DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_3_s0 |
| To | DDR3_Memory_Interface_Top_inst/gw3_top/u_gwmc_top/gw_wr_data0/wr_buf_din_103_s0 |
| Launch Clk | dma_clk:[R] |
| Latch Clk | dma_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | dma_clk | ||||
| 0.000 | 0.000 | tCL | RR | 3995 | BOTTOMSIDE[0] | DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 1.518 | 1.518 | tNET | RR | 1 | R60C21[0][B] | DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_3_s0/CLK |
| 1.794 | 0.275 | tC2Q | RR | 326 | R60C21[0][B] | DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_3_s0/Q |
| 5.019 | 3.225 | tNET | RR | 1 | R39C19[1][A] | u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u_dma_bus_arbiter/next_state.ST_IFF0_WRITE_DDR_s1/I3 |
| 5.188 | 0.169 | tINS | RF | 155 | R39C19[1][A] | u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u_dma_bus_arbiter/next_state.ST_IFF0_WRITE_DDR_s1/F |
| 6.599 | 1.411 | tNET | FF | 1 | R52C16[1][B] | u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u_dma_bus_arbiter/O_wr_data_d_103_s/I1 |
| 6.978 | 0.379 | tINS | FR | 1 | R52C16[1][B] | u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u_dma_bus_arbiter/O_wr_data_d_103_s/F |
| 7.417 | 0.439 | tNET | RR | 1 | R52C21[3][A] | DDR3_Memory_Interface_Top_inst/gw3_top/u_gwmc_top/gw_wr_data0/n664_s0/I0 |
| 7.792 | 0.375 | tINS | RR | 1 | R52C21[3][A] | DDR3_Memory_Interface_Top_inst/gw3_top/u_gwmc_top/gw_wr_data0/n664_s0/F |
| 7.792 | 0.000 | tNET | RR | 1 | R52C21[3][A] | DDR3_Memory_Interface_Top_inst/gw3_top/u_gwmc_top/gw_wr_data0/wr_buf_din_103_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 7.273 | 7.273 | active clock edge time | ||||
| 7.273 | 0.000 | dma_clk | ||||
| 7.273 | 0.000 | tCL | RR | 3995 | BOTTOMSIDE[0] | DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 8.791 | 1.518 | tNET | RR | 1 | R52C21[3][A] | DDR3_Memory_Interface_Top_inst/gw3_top/u_gwmc_top/gw_wr_data0/wr_buf_din_103_s0/CLK |
| 8.745 | -0.046 | tSu | 1 | R52C21[3][A] | DDR3_Memory_Interface_Top_inst/gw3_top/u_gwmc_top/gw_wr_data0/wr_buf_din_103_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 7.273 |
| Logic Level | 4 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.518, 100.000% |
| Arrival Data Path Delay | cell: 0.923, 14.718%; route: 5.075, 80.893%; tC2Q: 0.275, 4.389% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.518, 100.000% |
Path80
Path Summary:
| Slack | 0.969 |
| Data Arrival Time | 6.563 |
| Data Required Time | 7.532 |
| From | UserLayer_top_inst/ControlTransfer_inst/wValue_latch_9_s0 |
| To | UserLayer_top_inst/ControlTransfer_inst/wCompQuality_12_s0 |
| Launch Clk | pclk:[R] |
| Latch Clk | pclk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | pclk | ||||
| 0.000 | 0.000 | tCL | RR | 10163 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK |
| 1.513 | 1.513 | tNET | RR | 1 | R68C39[1][B] | UserLayer_top_inst/ControlTransfer_inst/wValue_latch_9_s0/CLK |
| 1.789 | 0.275 | tC2Q | RR | 7 | R68C39[1][B] | UserLayer_top_inst/ControlTransfer_inst/wValue_latch_9_s0/Q |
| 2.046 | 0.257 | tNET | RR | 1 | R69C41[2][A] | UserLayer_top_inst/ControlTransfer_inst/n4511_s21/I3 |
| 2.418 | 0.372 | tINS | RR | 10 | R69C41[2][A] | UserLayer_top_inst/ControlTransfer_inst/n4511_s21/F |
| 2.888 | 0.470 | tNET | RR | 1 | R70C47[3][B] | UserLayer_top_inst/ControlTransfer_inst/n4511_s17/I1 |
| 3.263 | 0.375 | tINS | RR | 11 | R70C47[3][B] | UserLayer_top_inst/ControlTransfer_inst/n4511_s17/F |
| 3.609 | 0.346 | tNET | RR | 1 | R70C40[3][B] | UserLayer_top_inst/ControlTransfer_inst/n688_s28/I3 |
| 3.985 | 0.375 | tINS | RR | 6 | R70C40[3][B] | UserLayer_top_inst/ControlTransfer_inst/n688_s28/F |
| 4.329 | 0.344 | tNET | RR | 1 | R64C40[3][B] | UserLayer_top_inst/ControlTransfer_inst/n6333_s3/I1 |
| 4.704 | 0.375 | tINS | RR | 5 | R64C40[3][B] | UserLayer_top_inst/ControlTransfer_inst/n6333_s3/F |
| 4.959 | 0.256 | tNET | RR | 1 | R63C38[0][A] | UserLayer_top_inst/ControlTransfer_inst/n6397_s2/I2 |
| 5.331 | 0.372 | tINS | RR | 64 | R63C38[0][A] | UserLayer_top_inst/ControlTransfer_inst/n6397_s2/F |
| 6.563 | 1.232 | tNET | RR | 1 | R66C52[0][A] | UserLayer_top_inst/ControlTransfer_inst/wCompQuality_12_s0/CE |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.250 | 6.250 | active clock edge time | ||||
| 6.250 | 0.000 | pclk | ||||
| 6.250 | 0.000 | tCL | RR | 10163 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK |
| 7.757 | 1.507 | tNET | RR | 1 | R66C52[0][A] | UserLayer_top_inst/ControlTransfer_inst/wCompQuality_12_s0/CLK |
| 7.532 | -0.224 | tSu | 1 | R66C52[0][A] | UserLayer_top_inst/ControlTransfer_inst/wCompQuality_12_s0 |
Path Statistics:
| Clock Skew | -0.007 |
| Setup Relationship | 6.250 |
| Logic Level | 6 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.513, 100.000% |
| Arrival Data Path Delay | cell: 1.869, 37.017%; route: 2.905, 57.530%; tC2Q: 0.275, 5.454% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.507, 100.000% |
Path81
Path Summary:
| Slack | 0.976 |
| Data Arrival Time | 6.557 |
| Data Required Time | 7.532 |
| From | UserLayer_top_inst/ControlTransfer_inst/wValue_latch_9_s0 |
| To | UserLayer_top_inst/ControlTransfer_inst/dwMaxVideoFrameSize_19_s0 |
| Launch Clk | pclk:[R] |
| Latch Clk | pclk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | pclk | ||||
| 0.000 | 0.000 | tCL | RR | 10163 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK |
| 1.513 | 1.513 | tNET | RR | 1 | R68C39[1][B] | UserLayer_top_inst/ControlTransfer_inst/wValue_latch_9_s0/CLK |
| 1.789 | 0.275 | tC2Q | RR | 7 | R68C39[1][B] | UserLayer_top_inst/ControlTransfer_inst/wValue_latch_9_s0/Q |
| 2.046 | 0.257 | tNET | RR | 1 | R69C41[2][A] | UserLayer_top_inst/ControlTransfer_inst/n4511_s21/I3 |
| 2.418 | 0.372 | tINS | RR | 10 | R69C41[2][A] | UserLayer_top_inst/ControlTransfer_inst/n4511_s21/F |
| 2.888 | 0.470 | tNET | RR | 1 | R70C47[3][B] | UserLayer_top_inst/ControlTransfer_inst/n4511_s17/I1 |
| 3.263 | 0.375 | tINS | RR | 11 | R70C47[3][B] | UserLayer_top_inst/ControlTransfer_inst/n4511_s17/F |
| 3.609 | 0.346 | tNET | RR | 1 | R70C40[3][B] | UserLayer_top_inst/ControlTransfer_inst/n688_s28/I3 |
| 3.985 | 0.375 | tINS | RR | 6 | R70C40[3][B] | UserLayer_top_inst/ControlTransfer_inst/n688_s28/F |
| 4.329 | 0.344 | tNET | RR | 1 | R64C40[3][B] | UserLayer_top_inst/ControlTransfer_inst/n6333_s3/I1 |
| 4.704 | 0.375 | tINS | RR | 5 | R64C40[3][B] | UserLayer_top_inst/ControlTransfer_inst/n6333_s3/F |
| 4.983 | 0.279 | tNET | RR | 1 | R62C38[3][B] | UserLayer_top_inst/ControlTransfer_inst/n6461_s1/I2 |
| 5.358 | 0.375 | tINS | RR | 48 | R62C38[3][B] | UserLayer_top_inst/ControlTransfer_inst/n6461_s1/F |
| 6.557 | 1.199 | tNET | RR | 1 | R61C44[0][A] | UserLayer_top_inst/ControlTransfer_inst/dwMaxVideoFrameSize_19_s0/CE |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.250 | 6.250 | active clock edge time | ||||
| 6.250 | 0.000 | pclk | ||||
| 6.250 | 0.000 | tCL | RR | 10163 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK |
| 7.757 | 1.507 | tNET | RR | 1 | R61C44[0][A] | UserLayer_top_inst/ControlTransfer_inst/dwMaxVideoFrameSize_19_s0/CLK |
| 7.532 | -0.224 | tSu | 1 | R61C44[0][A] | UserLayer_top_inst/ControlTransfer_inst/dwMaxVideoFrameSize_19_s0 |
Path Statistics:
| Clock Skew | -0.007 |
| Setup Relationship | 6.250 |
| Logic Level | 6 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.513, 100.000% |
| Arrival Data Path Delay | cell: 1.873, 37.134%; route: 2.895, 57.405%; tC2Q: 0.275, 5.460% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.507, 100.000% |
Path82
Path Summary:
| Slack | 0.976 |
| Data Arrival Time | 6.557 |
| Data Required Time | 7.532 |
| From | UserLayer_top_inst/ControlTransfer_inst/wValue_latch_9_s0 |
| To | UserLayer_top_inst/ControlTransfer_inst/dwMaxVideoFrameSize_21_s0 |
| Launch Clk | pclk:[R] |
| Latch Clk | pclk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | pclk | ||||
| 0.000 | 0.000 | tCL | RR | 10163 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK |
| 1.513 | 1.513 | tNET | RR | 1 | R68C39[1][B] | UserLayer_top_inst/ControlTransfer_inst/wValue_latch_9_s0/CLK |
| 1.789 | 0.275 | tC2Q | RR | 7 | R68C39[1][B] | UserLayer_top_inst/ControlTransfer_inst/wValue_latch_9_s0/Q |
| 2.046 | 0.257 | tNET | RR | 1 | R69C41[2][A] | UserLayer_top_inst/ControlTransfer_inst/n4511_s21/I3 |
| 2.418 | 0.372 | tINS | RR | 10 | R69C41[2][A] | UserLayer_top_inst/ControlTransfer_inst/n4511_s21/F |
| 2.888 | 0.470 | tNET | RR | 1 | R70C47[3][B] | UserLayer_top_inst/ControlTransfer_inst/n4511_s17/I1 |
| 3.263 | 0.375 | tINS | RR | 11 | R70C47[3][B] | UserLayer_top_inst/ControlTransfer_inst/n4511_s17/F |
| 3.609 | 0.346 | tNET | RR | 1 | R70C40[3][B] | UserLayer_top_inst/ControlTransfer_inst/n688_s28/I3 |
| 3.985 | 0.375 | tINS | RR | 6 | R70C40[3][B] | UserLayer_top_inst/ControlTransfer_inst/n688_s28/F |
| 4.329 | 0.344 | tNET | RR | 1 | R64C40[3][B] | UserLayer_top_inst/ControlTransfer_inst/n6333_s3/I1 |
| 4.704 | 0.375 | tINS | RR | 5 | R64C40[3][B] | UserLayer_top_inst/ControlTransfer_inst/n6333_s3/F |
| 4.983 | 0.279 | tNET | RR | 1 | R62C38[3][B] | UserLayer_top_inst/ControlTransfer_inst/n6461_s1/I2 |
| 5.358 | 0.375 | tINS | RR | 48 | R62C38[3][B] | UserLayer_top_inst/ControlTransfer_inst/n6461_s1/F |
| 6.557 | 1.199 | tNET | RR | 1 | R61C44[0][B] | UserLayer_top_inst/ControlTransfer_inst/dwMaxVideoFrameSize_21_s0/CE |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.250 | 6.250 | active clock edge time | ||||
| 6.250 | 0.000 | pclk | ||||
| 6.250 | 0.000 | tCL | RR | 10163 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK |
| 7.757 | 1.507 | tNET | RR | 1 | R61C44[0][B] | UserLayer_top_inst/ControlTransfer_inst/dwMaxVideoFrameSize_21_s0/CLK |
| 7.532 | -0.224 | tSu | 1 | R61C44[0][B] | UserLayer_top_inst/ControlTransfer_inst/dwMaxVideoFrameSize_21_s0 |
Path Statistics:
| Clock Skew | -0.007 |
| Setup Relationship | 6.250 |
| Logic Level | 6 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.513, 100.000% |
| Arrival Data Path Delay | cell: 1.873, 37.134%; route: 2.895, 57.405%; tC2Q: 0.275, 5.460% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.507, 100.000% |
Path83
Path Summary:
| Slack | 0.981 |
| Data Arrival Time | 6.559 |
| Data Required Time | 7.539 |
| From | UserLayer_top_inst/ControlTransfer_inst/wValue_latch_9_s0 |
| To | UserLayer_top_inst/ControlTransfer_inst/dwMaxVideoFrameSize_23_s0 |
| Launch Clk | pclk:[R] |
| Latch Clk | pclk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | pclk | ||||
| 0.000 | 0.000 | tCL | RR | 10163 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK |
| 1.513 | 1.513 | tNET | RR | 1 | R68C39[1][B] | UserLayer_top_inst/ControlTransfer_inst/wValue_latch_9_s0/CLK |
| 1.789 | 0.275 | tC2Q | RR | 7 | R68C39[1][B] | UserLayer_top_inst/ControlTransfer_inst/wValue_latch_9_s0/Q |
| 2.046 | 0.257 | tNET | RR | 1 | R69C41[2][A] | UserLayer_top_inst/ControlTransfer_inst/n4511_s21/I3 |
| 2.418 | 0.372 | tINS | RR | 10 | R69C41[2][A] | UserLayer_top_inst/ControlTransfer_inst/n4511_s21/F |
| 2.888 | 0.470 | tNET | RR | 1 | R70C47[3][B] | UserLayer_top_inst/ControlTransfer_inst/n4511_s17/I1 |
| 3.263 | 0.375 | tINS | RR | 11 | R70C47[3][B] | UserLayer_top_inst/ControlTransfer_inst/n4511_s17/F |
| 3.609 | 0.346 | tNET | RR | 1 | R70C40[3][B] | UserLayer_top_inst/ControlTransfer_inst/n688_s28/I3 |
| 3.985 | 0.375 | tINS | RR | 6 | R70C40[3][B] | UserLayer_top_inst/ControlTransfer_inst/n688_s28/F |
| 4.329 | 0.344 | tNET | RR | 1 | R64C40[3][B] | UserLayer_top_inst/ControlTransfer_inst/n6333_s3/I1 |
| 4.704 | 0.375 | tINS | RR | 5 | R64C40[3][B] | UserLayer_top_inst/ControlTransfer_inst/n6333_s3/F |
| 4.983 | 0.279 | tNET | RR | 1 | R62C38[3][B] | UserLayer_top_inst/ControlTransfer_inst/n6461_s1/I2 |
| 5.358 | 0.375 | tINS | RR | 48 | R62C38[3][B] | UserLayer_top_inst/ControlTransfer_inst/n6461_s1/F |
| 6.559 | 1.201 | tNET | RR | 1 | R63C45[2][B] | UserLayer_top_inst/ControlTransfer_inst/dwMaxVideoFrameSize_23_s0/CE |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.250 | 6.250 | active clock edge time | ||||
| 6.250 | 0.000 | pclk | ||||
| 6.250 | 0.000 | tCL | RR | 10163 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK |
| 7.763 | 1.513 | tNET | RR | 1 | R63C45[2][B] | UserLayer_top_inst/ControlTransfer_inst/dwMaxVideoFrameSize_23_s0/CLK |
| 7.539 | -0.224 | tSu | 1 | R63C45[2][B] | UserLayer_top_inst/ControlTransfer_inst/dwMaxVideoFrameSize_23_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 6.250 |
| Logic Level | 6 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.513, 100.000% |
| Arrival Data Path Delay | cell: 1.873, 37.121%; route: 2.897, 57.421%; tC2Q: 0.275, 5.458% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.513, 100.000% |
Path84
Path Summary:
| Slack | 0.981 |
| Data Arrival Time | 6.559 |
| Data Required Time | 7.539 |
| From | UserLayer_top_inst/ControlTransfer_inst/wValue_latch_9_s0 |
| To | UserLayer_top_inst/ControlTransfer_inst/wDelay_6_s0 |
| Launch Clk | pclk:[R] |
| Latch Clk | pclk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | pclk | ||||
| 0.000 | 0.000 | tCL | RR | 10163 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK |
| 1.513 | 1.513 | tNET | RR | 1 | R68C39[1][B] | UserLayer_top_inst/ControlTransfer_inst/wValue_latch_9_s0/CLK |
| 1.789 | 0.275 | tC2Q | RR | 7 | R68C39[1][B] | UserLayer_top_inst/ControlTransfer_inst/wValue_latch_9_s0/Q |
| 2.046 | 0.257 | tNET | RR | 1 | R69C41[2][A] | UserLayer_top_inst/ControlTransfer_inst/n4511_s21/I3 |
| 2.418 | 0.372 | tINS | RR | 10 | R69C41[2][A] | UserLayer_top_inst/ControlTransfer_inst/n4511_s21/F |
| 2.888 | 0.470 | tNET | RR | 1 | R70C47[3][B] | UserLayer_top_inst/ControlTransfer_inst/n4511_s17/I1 |
| 3.263 | 0.375 | tINS | RR | 11 | R70C47[3][B] | UserLayer_top_inst/ControlTransfer_inst/n4511_s17/F |
| 3.609 | 0.346 | tNET | RR | 1 | R70C40[3][B] | UserLayer_top_inst/ControlTransfer_inst/n688_s28/I3 |
| 3.985 | 0.375 | tINS | RR | 6 | R70C40[3][B] | UserLayer_top_inst/ControlTransfer_inst/n688_s28/F |
| 4.329 | 0.344 | tNET | RR | 1 | R64C40[3][B] | UserLayer_top_inst/ControlTransfer_inst/n6333_s3/I1 |
| 4.704 | 0.375 | tINS | RR | 5 | R64C40[3][B] | UserLayer_top_inst/ControlTransfer_inst/n6333_s3/F |
| 4.983 | 0.279 | tNET | RR | 1 | R62C38[3][B] | UserLayer_top_inst/ControlTransfer_inst/n6461_s1/I2 |
| 5.358 | 0.375 | tINS | RR | 48 | R62C38[3][B] | UserLayer_top_inst/ControlTransfer_inst/n6461_s1/F |
| 6.559 | 1.201 | tNET | RR | 1 | R63C45[0][A] | UserLayer_top_inst/ControlTransfer_inst/wDelay_6_s0/CE |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.250 | 6.250 | active clock edge time | ||||
| 6.250 | 0.000 | pclk | ||||
| 6.250 | 0.000 | tCL | RR | 10163 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK |
| 7.763 | 1.513 | tNET | RR | 1 | R63C45[0][A] | UserLayer_top_inst/ControlTransfer_inst/wDelay_6_s0/CLK |
| 7.539 | -0.224 | tSu | 1 | R63C45[0][A] | UserLayer_top_inst/ControlTransfer_inst/wDelay_6_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 6.250 |
| Logic Level | 6 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.513, 100.000% |
| Arrival Data Path Delay | cell: 1.873, 37.121%; route: 2.897, 57.421%; tC2Q: 0.275, 5.458% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.513, 100.000% |
Path85
Path Summary:
| Slack | 0.981 |
| Data Arrival Time | 6.558 |
| Data Required Time | 7.539 |
| From | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_5g/state_3_s0 |
| To | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_5g/train_count_17_s2 |
| Launch Clk | pclk:[R] |
| Latch Clk | pclk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | pclk | ||||
| 0.000 | 0.000 | tCL | RR | 10163 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK |
| 1.513 | 1.513 | tNET | RR | 1 | R21C106[2][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_5g/state_3_s0/CLK |
| 1.789 | 0.275 | tC2Q | RR | 11 | R21C106[2][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_5g/state_3_s0/Q |
| 2.046 | 0.257 | tNET | RR | 1 | R20C105[0][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_5g/n1816_s6/I1 |
| 2.425 | 0.379 | tINS | RR | 3 | R20C105[0][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_5g/n1816_s6/F |
| 2.679 | 0.254 | tNET | RR | 1 | R21C103[3][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_5g/n1968_s8/I0 |
| 2.888 | 0.209 | tINS | RF | 12 | R21C103[3][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_5g/n1968_s8/F |
| 3.546 | 0.658 | tNET | FF | 1 | R26C97[1][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_5g/train_count_19_s8/I0 |
| 3.924 | 0.379 | tINS | FR | 20 | R26C97[1][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_5g/train_count_19_s8/F |
| 4.420 | 0.496 | tNET | RR | 1 | R22C101[2][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_5g/train_count_19_s4/I3 |
| 4.752 | 0.332 | tINS | RR | 20 | R22C101[2][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_5g/train_count_19_s4/F |
| 6.558 | 1.805 | tNET | RR | 1 | R30C100[2][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_5g/train_count_17_s2/CE |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.250 | 6.250 | active clock edge time | ||||
| 6.250 | 0.000 | pclk | ||||
| 6.250 | 0.000 | tCL | RR | 10163 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK |
| 7.763 | 1.513 | tNET | RR | 1 | R30C100[2][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_5g/train_count_17_s2/CLK |
| 7.539 | -0.224 | tSu | 1 | R30C100[2][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_5g/train_count_17_s2 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 6.250 |
| Logic Level | 5 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.513, 100.000% |
| Arrival Data Path Delay | cell: 1.299, 25.745%; route: 3.470, 68.796%; tC2Q: 0.275, 5.459% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.513, 100.000% |
Path86
Path Summary:
| Slack | 0.981 |
| Data Arrival Time | 6.558 |
| Data Required Time | 7.539 |
| From | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_5g/state_3_s0 |
| To | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_5g/train_count_18_s2 |
| Launch Clk | pclk:[R] |
| Latch Clk | pclk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | pclk | ||||
| 0.000 | 0.000 | tCL | RR | 10163 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK |
| 1.513 | 1.513 | tNET | RR | 1 | R21C106[2][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_5g/state_3_s0/CLK |
| 1.789 | 0.275 | tC2Q | RR | 11 | R21C106[2][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_5g/state_3_s0/Q |
| 2.046 | 0.257 | tNET | RR | 1 | R20C105[0][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_5g/n1816_s6/I1 |
| 2.425 | 0.379 | tINS | RR | 3 | R20C105[0][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_5g/n1816_s6/F |
| 2.679 | 0.254 | tNET | RR | 1 | R21C103[3][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_5g/n1968_s8/I0 |
| 2.888 | 0.209 | tINS | RF | 12 | R21C103[3][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_5g/n1968_s8/F |
| 3.546 | 0.658 | tNET | FF | 1 | R26C97[1][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_5g/train_count_19_s8/I0 |
| 3.924 | 0.379 | tINS | FR | 20 | R26C97[1][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_5g/train_count_19_s8/F |
| 4.420 | 0.496 | tNET | RR | 1 | R22C101[2][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_5g/train_count_19_s4/I3 |
| 4.752 | 0.332 | tINS | RR | 20 | R22C101[2][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_5g/train_count_19_s4/F |
| 6.558 | 1.805 | tNET | RR | 1 | R30C100[0][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_5g/train_count_18_s2/CE |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.250 | 6.250 | active clock edge time | ||||
| 6.250 | 0.000 | pclk | ||||
| 6.250 | 0.000 | tCL | RR | 10163 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK |
| 7.763 | 1.513 | tNET | RR | 1 | R30C100[0][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_5g/train_count_18_s2/CLK |
| 7.539 | -0.224 | tSu | 1 | R30C100[0][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_5g/train_count_18_s2 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 6.250 |
| Logic Level | 5 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.513, 100.000% |
| Arrival Data Path Delay | cell: 1.299, 25.745%; route: 3.470, 68.796%; tC2Q: 0.275, 5.459% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.513, 100.000% |
Path87
Path Summary:
| Slack | 0.984 |
| Data Arrival Time | 6.733 |
| Data Required Time | 7.717 |
| From | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_word_alignment/data_in_r0_3_s0 |
| To | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_word_alignment/cnt0_0_s1 |
| Launch Clk | q0_lane1_fabric_rx_clk:[R] |
| Latch Clk | q0_lane1_fabric_rx_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | q0_lane1_fabric_rx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 518 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_RX_O_FABRIC_CLK |
| 1.513 | 1.513 | tNET | RR | 1 | R25C81[3][A] | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_word_alignment/data_in_r0_3_s0/CLK |
| 1.778 | 0.265 | tC2Q | RF | 13 | R25C81[3][A] | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_word_alignment/data_in_r0_3_s0/Q |
| 2.413 | 0.635 | tNET | FF | 1 | R25C79[1][B] | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_word_alignment/cnt0_3_s56/I3 |
| 2.745 | 0.332 | tINS | FR | 2 | R25C79[1][B] | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_word_alignment/cnt0_3_s56/F |
| 2.749 | 0.004 | tNET | RR | 1 | R25C79[3][B] | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_word_alignment/cnt0_3_s26/I3 |
| 3.124 | 0.375 | tINS | RR | 2 | R25C79[3][B] | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_word_alignment/cnt0_3_s26/F |
| 3.747 | 0.623 | tNET | RR | 1 | R25C80[1][A] | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_word_alignment/n768_s63/I3 |
| 4.119 | 0.372 | tINS | RR | 1 | R25C80[1][A] | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_word_alignment/n768_s63/F |
| 4.232 | 0.113 | tNET | RR | 1 | R25C81[1][A] | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_word_alignment/n768_s47/I1 |
| 4.564 | 0.332 | tINS | RR | 1 | R25C81[1][A] | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_word_alignment/n768_s47/F |
| 4.678 | 0.113 | tNET | RR | 1 | R26C81[1][B] | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_word_alignment/n768_s27/I0 |
| 5.010 | 0.332 | tINS | RR | 1 | R26C81[1][B] | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_word_alignment/n768_s27/F |
| 5.264 | 0.254 | tNET | RR | 1 | R26C82[1][A] | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_word_alignment/n768_s12/I1 |
| 5.643 | 0.379 | tINS | RR | 1 | R26C82[1][A] | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_word_alignment/n768_s12/F |
| 5.911 | 0.268 | tNET | RR | 1 | R26C84[3][B] | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_word_alignment/n768_s5/I0 |
| 6.120 | 0.209 | tINS | RF | 1 | R26C84[3][B] | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_word_alignment/n768_s5/F |
| 6.354 | 0.235 | tNET | FF | 1 | R25C85[0][A] | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_word_alignment/n768_s3/I1 |
| 6.733 | 0.379 | tINS | FR | 1 | R25C85[0][A] | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_word_alignment/n768_s3/F |
| 6.733 | 0.000 | tNET | RR | 1 | R25C85[0][A] | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_word_alignment/cnt0_0_s1/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.250 | 6.250 | active clock edge time | ||||
| 6.250 | 0.000 | q0_lane1_fabric_rx_clk | ||||
| 6.250 | 0.000 | tCL | RR | 518 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_RX_O_FABRIC_CLK |
| 7.763 | 1.513 | tNET | RR | 1 | R25C85[0][A] | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_word_alignment/cnt0_0_s1/CLK |
| 7.717 | -0.046 | tSu | 1 | R25C85[0][A] | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_word_alignment/cnt0_0_s1 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 6.250 |
| Logic Level | 9 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.513, 100.000% |
| Arrival Data Path Delay | cell: 2.710, 51.914%; route: 2.246, 43.017%; tC2Q: 0.265, 5.069% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.513, 100.000% |
Path88
Path Summary:
| Slack | 0.994 |
| Data Arrival Time | 6.538 |
| Data Required Time | 7.532 |
| From | UserLayer_top_inst/ControlTransfer_inst/wValue_latch_9_s0 |
| To | UserLayer_top_inst/ControlTransfer_inst/bFormatIndex_0_s0 |
| Launch Clk | pclk:[R] |
| Latch Clk | pclk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | pclk | ||||
| 0.000 | 0.000 | tCL | RR | 10163 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK |
| 1.513 | 1.513 | tNET | RR | 1 | R68C39[1][B] | UserLayer_top_inst/ControlTransfer_inst/wValue_latch_9_s0/CLK |
| 1.789 | 0.275 | tC2Q | RR | 7 | R68C39[1][B] | UserLayer_top_inst/ControlTransfer_inst/wValue_latch_9_s0/Q |
| 2.046 | 0.257 | tNET | RR | 1 | R69C41[2][A] | UserLayer_top_inst/ControlTransfer_inst/n4511_s21/I3 |
| 2.418 | 0.372 | tINS | RR | 10 | R69C41[2][A] | UserLayer_top_inst/ControlTransfer_inst/n4511_s21/F |
| 2.888 | 0.470 | tNET | RR | 1 | R70C47[3][B] | UserLayer_top_inst/ControlTransfer_inst/n4511_s17/I1 |
| 3.263 | 0.375 | tINS | RR | 11 | R70C47[3][B] | UserLayer_top_inst/ControlTransfer_inst/n4511_s17/F |
| 3.609 | 0.346 | tNET | RR | 1 | R70C40[3][B] | UserLayer_top_inst/ControlTransfer_inst/n688_s28/I3 |
| 3.985 | 0.375 | tINS | RR | 6 | R70C40[3][B] | UserLayer_top_inst/ControlTransfer_inst/n688_s28/F |
| 4.329 | 0.344 | tNET | RR | 1 | R64C40[3][B] | UserLayer_top_inst/ControlTransfer_inst/n6333_s3/I1 |
| 4.704 | 0.375 | tINS | RR | 5 | R64C40[3][B] | UserLayer_top_inst/ControlTransfer_inst/n6333_s3/F |
| 4.959 | 0.256 | tNET | RR | 1 | R63C38[3][B] | UserLayer_top_inst/ControlTransfer_inst/n6333_s5/I2 |
| 5.335 | 0.375 | tINS | RR | 64 | R63C38[3][B] | UserLayer_top_inst/ControlTransfer_inst/n6333_s5/F |
| 6.538 | 1.203 | tNET | RR | 1 | R61C48[1][A] | UserLayer_top_inst/ControlTransfer_inst/bFormatIndex_0_s0/CE |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.250 | 6.250 | active clock edge time | ||||
| 6.250 | 0.000 | pclk | ||||
| 6.250 | 0.000 | tCL | RR | 10163 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK |
| 7.757 | 1.507 | tNET | RR | 1 | R61C48[1][A] | UserLayer_top_inst/ControlTransfer_inst/bFormatIndex_0_s0/CLK |
| 7.532 | -0.224 | tSu | 1 | R61C48[1][A] | UserLayer_top_inst/ControlTransfer_inst/bFormatIndex_0_s0 |
Path Statistics:
| Clock Skew | -0.007 |
| Setup Relationship | 6.250 |
| Logic Level | 6 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.513, 100.000% |
| Arrival Data Path Delay | cell: 1.873, 37.274%; route: 2.876, 57.245%; tC2Q: 0.275, 5.481% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.507, 100.000% |
Path89
Path Summary:
| Slack | 0.994 |
| Data Arrival Time | 6.538 |
| Data Required Time | 7.532 |
| From | UserLayer_top_inst/ControlTransfer_inst/wValue_latch_9_s0 |
| To | UserLayer_top_inst/ControlTransfer_inst/dwFrameInterval_8_s0 |
| Launch Clk | pclk:[R] |
| Latch Clk | pclk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | pclk | ||||
| 0.000 | 0.000 | tCL | RR | 10163 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK |
| 1.513 | 1.513 | tNET | RR | 1 | R68C39[1][B] | UserLayer_top_inst/ControlTransfer_inst/wValue_latch_9_s0/CLK |
| 1.789 | 0.275 | tC2Q | RR | 7 | R68C39[1][B] | UserLayer_top_inst/ControlTransfer_inst/wValue_latch_9_s0/Q |
| 2.046 | 0.257 | tNET | RR | 1 | R69C41[2][A] | UserLayer_top_inst/ControlTransfer_inst/n4511_s21/I3 |
| 2.418 | 0.372 | tINS | RR | 10 | R69C41[2][A] | UserLayer_top_inst/ControlTransfer_inst/n4511_s21/F |
| 2.888 | 0.470 | tNET | RR | 1 | R70C47[3][B] | UserLayer_top_inst/ControlTransfer_inst/n4511_s17/I1 |
| 3.263 | 0.375 | tINS | RR | 11 | R70C47[3][B] | UserLayer_top_inst/ControlTransfer_inst/n4511_s17/F |
| 3.609 | 0.346 | tNET | RR | 1 | R70C40[3][B] | UserLayer_top_inst/ControlTransfer_inst/n688_s28/I3 |
| 3.985 | 0.375 | tINS | RR | 6 | R70C40[3][B] | UserLayer_top_inst/ControlTransfer_inst/n688_s28/F |
| 4.329 | 0.344 | tNET | RR | 1 | R64C40[3][B] | UserLayer_top_inst/ControlTransfer_inst/n6333_s3/I1 |
| 4.704 | 0.375 | tINS | RR | 5 | R64C40[3][B] | UserLayer_top_inst/ControlTransfer_inst/n6333_s3/F |
| 4.959 | 0.256 | tNET | RR | 1 | R63C38[3][B] | UserLayer_top_inst/ControlTransfer_inst/n6333_s5/I2 |
| 5.335 | 0.375 | tINS | RR | 64 | R63C38[3][B] | UserLayer_top_inst/ControlTransfer_inst/n6333_s5/F |
| 6.538 | 1.203 | tNET | RR | 1 | R62C48[2][B] | UserLayer_top_inst/ControlTransfer_inst/dwFrameInterval_8_s0/CE |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.250 | 6.250 | active clock edge time | ||||
| 6.250 | 0.000 | pclk | ||||
| 6.250 | 0.000 | tCL | RR | 10163 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK |
| 7.757 | 1.507 | tNET | RR | 1 | R62C48[2][B] | UserLayer_top_inst/ControlTransfer_inst/dwFrameInterval_8_s0/CLK |
| 7.532 | -0.224 | tSu | 1 | R62C48[2][B] | UserLayer_top_inst/ControlTransfer_inst/dwFrameInterval_8_s0 |
Path Statistics:
| Clock Skew | -0.007 |
| Setup Relationship | 6.250 |
| Logic Level | 6 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.513, 100.000% |
| Arrival Data Path Delay | cell: 1.873, 37.274%; route: 2.876, 57.245%; tC2Q: 0.275, 5.481% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.507, 100.000% |
Path90
Path Summary:
| Slack | 0.994 |
| Data Arrival Time | 6.538 |
| Data Required Time | 7.532 |
| From | UserLayer_top_inst/ControlTransfer_inst/wValue_latch_9_s0 |
| To | UserLayer_top_inst/ControlTransfer_inst/dwFrameInterval_10_s0 |
| Launch Clk | pclk:[R] |
| Latch Clk | pclk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | pclk | ||||
| 0.000 | 0.000 | tCL | RR | 10163 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK |
| 1.513 | 1.513 | tNET | RR | 1 | R68C39[1][B] | UserLayer_top_inst/ControlTransfer_inst/wValue_latch_9_s0/CLK |
| 1.789 | 0.275 | tC2Q | RR | 7 | R68C39[1][B] | UserLayer_top_inst/ControlTransfer_inst/wValue_latch_9_s0/Q |
| 2.046 | 0.257 | tNET | RR | 1 | R69C41[2][A] | UserLayer_top_inst/ControlTransfer_inst/n4511_s21/I3 |
| 2.418 | 0.372 | tINS | RR | 10 | R69C41[2][A] | UserLayer_top_inst/ControlTransfer_inst/n4511_s21/F |
| 2.888 | 0.470 | tNET | RR | 1 | R70C47[3][B] | UserLayer_top_inst/ControlTransfer_inst/n4511_s17/I1 |
| 3.263 | 0.375 | tINS | RR | 11 | R70C47[3][B] | UserLayer_top_inst/ControlTransfer_inst/n4511_s17/F |
| 3.609 | 0.346 | tNET | RR | 1 | R70C40[3][B] | UserLayer_top_inst/ControlTransfer_inst/n688_s28/I3 |
| 3.985 | 0.375 | tINS | RR | 6 | R70C40[3][B] | UserLayer_top_inst/ControlTransfer_inst/n688_s28/F |
| 4.329 | 0.344 | tNET | RR | 1 | R64C40[3][B] | UserLayer_top_inst/ControlTransfer_inst/n6333_s3/I1 |
| 4.704 | 0.375 | tINS | RR | 5 | R64C40[3][B] | UserLayer_top_inst/ControlTransfer_inst/n6333_s3/F |
| 4.959 | 0.256 | tNET | RR | 1 | R63C38[3][B] | UserLayer_top_inst/ControlTransfer_inst/n6333_s5/I2 |
| 5.335 | 0.375 | tINS | RR | 64 | R63C38[3][B] | UserLayer_top_inst/ControlTransfer_inst/n6333_s5/F |
| 6.538 | 1.203 | tNET | RR | 1 | R61C48[3][A] | UserLayer_top_inst/ControlTransfer_inst/dwFrameInterval_10_s0/CE |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.250 | 6.250 | active clock edge time | ||||
| 6.250 | 0.000 | pclk | ||||
| 6.250 | 0.000 | tCL | RR | 10163 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK |
| 7.757 | 1.507 | tNET | RR | 1 | R61C48[3][A] | UserLayer_top_inst/ControlTransfer_inst/dwFrameInterval_10_s0/CLK |
| 7.532 | -0.224 | tSu | 1 | R61C48[3][A] | UserLayer_top_inst/ControlTransfer_inst/dwFrameInterval_10_s0 |
Path Statistics:
| Clock Skew | -0.007 |
| Setup Relationship | 6.250 |
| Logic Level | 6 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.513, 100.000% |
| Arrival Data Path Delay | cell: 1.873, 37.274%; route: 2.876, 57.245%; tC2Q: 0.275, 5.481% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.507, 100.000% |
Path91
Path Summary:
| Slack | 0.994 |
| Data Arrival Time | 6.538 |
| Data Required Time | 7.532 |
| From | UserLayer_top_inst/ControlTransfer_inst/wValue_latch_9_s0 |
| To | UserLayer_top_inst/ControlTransfer_inst/dwFrameInterval_14_s0 |
| Launch Clk | pclk:[R] |
| Latch Clk | pclk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | pclk | ||||
| 0.000 | 0.000 | tCL | RR | 10163 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK |
| 1.513 | 1.513 | tNET | RR | 1 | R68C39[1][B] | UserLayer_top_inst/ControlTransfer_inst/wValue_latch_9_s0/CLK |
| 1.789 | 0.275 | tC2Q | RR | 7 | R68C39[1][B] | UserLayer_top_inst/ControlTransfer_inst/wValue_latch_9_s0/Q |
| 2.046 | 0.257 | tNET | RR | 1 | R69C41[2][A] | UserLayer_top_inst/ControlTransfer_inst/n4511_s21/I3 |
| 2.418 | 0.372 | tINS | RR | 10 | R69C41[2][A] | UserLayer_top_inst/ControlTransfer_inst/n4511_s21/F |
| 2.888 | 0.470 | tNET | RR | 1 | R70C47[3][B] | UserLayer_top_inst/ControlTransfer_inst/n4511_s17/I1 |
| 3.263 | 0.375 | tINS | RR | 11 | R70C47[3][B] | UserLayer_top_inst/ControlTransfer_inst/n4511_s17/F |
| 3.609 | 0.346 | tNET | RR | 1 | R70C40[3][B] | UserLayer_top_inst/ControlTransfer_inst/n688_s28/I3 |
| 3.985 | 0.375 | tINS | RR | 6 | R70C40[3][B] | UserLayer_top_inst/ControlTransfer_inst/n688_s28/F |
| 4.329 | 0.344 | tNET | RR | 1 | R64C40[3][B] | UserLayer_top_inst/ControlTransfer_inst/n6333_s3/I1 |
| 4.704 | 0.375 | tINS | RR | 5 | R64C40[3][B] | UserLayer_top_inst/ControlTransfer_inst/n6333_s3/F |
| 4.959 | 0.256 | tNET | RR | 1 | R63C38[3][B] | UserLayer_top_inst/ControlTransfer_inst/n6333_s5/I2 |
| 5.335 | 0.375 | tINS | RR | 64 | R63C38[3][B] | UserLayer_top_inst/ControlTransfer_inst/n6333_s5/F |
| 6.538 | 1.203 | tNET | RR | 1 | R61C48[2][A] | UserLayer_top_inst/ControlTransfer_inst/dwFrameInterval_14_s0/CE |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.250 | 6.250 | active clock edge time | ||||
| 6.250 | 0.000 | pclk | ||||
| 6.250 | 0.000 | tCL | RR | 10163 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK |
| 7.757 | 1.507 | tNET | RR | 1 | R61C48[2][A] | UserLayer_top_inst/ControlTransfer_inst/dwFrameInterval_14_s0/CLK |
| 7.532 | -0.224 | tSu | 1 | R61C48[2][A] | UserLayer_top_inst/ControlTransfer_inst/dwFrameInterval_14_s0 |
Path Statistics:
| Clock Skew | -0.007 |
| Setup Relationship | 6.250 |
| Logic Level | 6 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.513, 100.000% |
| Arrival Data Path Delay | cell: 1.873, 37.274%; route: 2.876, 57.245%; tC2Q: 0.275, 5.481% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.507, 100.000% |
Path92
Path Summary:
| Slack | 0.997 |
| Data Arrival Time | 6.603 |
| Data Required Time | 7.600 |
| From | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/dpp_crc_append/dpp_data_in_0_d0_30_s0 |
| To | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/dpp_crc_append/crc64_in[1]_9_s0 |
| Launch Clk | pclk:[R] |
| Latch Clk | pclk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | pclk | ||||
| 0.000 | 0.000 | tCL | RR | 10163 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK |
| 1.513 | 1.513 | tNET | RR | 1 | R68C55[2][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/dpp_crc_append/dpp_data_in_0_d0_30_s0/CLK |
| 1.789 | 0.275 | tC2Q | RR | 14 | R68C55[2][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/dpp_crc_append/dpp_data_in_0_d0_30_s0/Q |
| 2.732 | 0.943 | tNET | RR | 1 | R69C57[0][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/dpp_crc_append/iu3cdptx64/crcOut_9_s21/I2 |
| 3.104 | 0.372 | tINS | RR | 1 | R69C57[0][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/dpp_crc_append/iu3cdptx64/crcOut_9_s21/F |
| 3.476 | 0.373 | tNET | RR | 1 | R69C61[0][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/dpp_crc_append/iu3cdptx64/crcOut_9_s12/I0 |
| 3.855 | 0.379 | tINS | RR | 1 | R69C61[0][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/dpp_crc_append/iu3cdptx64/crcOut_9_s12/F |
| 4.534 | 0.679 | tNET | RR | 1 | R69C60[3][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/dpp_crc_append/iu3cdptx64/crcOut_9_s4/I3 |
| 4.909 | 0.375 | tINS | RR | 1 | R69C60[3][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/dpp_crc_append/iu3cdptx64/crcOut_9_s4/F |
| 5.256 | 0.347 | tNET | RR | 1 | R69C59[1][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/dpp_crc_append/iu3cdptx64/crcOut_9_s1/I3 |
| 5.589 | 0.332 | tINS | RR | 9 | R69C59[1][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/dpp_crc_append/iu3cdptx64/crcOut_9_s1/F |
| 6.603 | 1.014 | tNET | RR | 1 | R53C61[0][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/dpp_crc_append/crc64_in[1]_9_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.250 | 6.250 | active clock edge time | ||||
| 6.250 | 0.000 | pclk | ||||
| 6.250 | 0.000 | tCL | RR | 10163 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK |
| 7.763 | 1.513 | tNET | RR | 1 | R53C61[0][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/dpp_crc_append/crc64_in[1]_9_s0/CLK |
| 7.600 | -0.164 | tSu | 1 | R53C61[0][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/dpp_crc_append/crc64_in[1]_9_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 6.250 |
| Logic Level | 5 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.513, 100.000% |
| Arrival Data Path Delay | cell: 1.458, 28.647%; route: 3.356, 65.942%; tC2Q: 0.275, 5.411% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.513, 100.000% |
Path93
Path Summary:
| Slack | 1.003 |
| Data Arrival Time | 6.536 |
| Data Required Time | 7.539 |
| From | UserLayer_top_inst/ControlTransfer_inst/wValue_latch_9_s0 |
| To | UserLayer_top_inst/ControlTransfer_inst/bFormatIndex_3_s0 |
| Launch Clk | pclk:[R] |
| Latch Clk | pclk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | pclk | ||||
| 0.000 | 0.000 | tCL | RR | 10163 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK |
| 1.513 | 1.513 | tNET | RR | 1 | R68C39[1][B] | UserLayer_top_inst/ControlTransfer_inst/wValue_latch_9_s0/CLK |
| 1.789 | 0.275 | tC2Q | RR | 7 | R68C39[1][B] | UserLayer_top_inst/ControlTransfer_inst/wValue_latch_9_s0/Q |
| 2.046 | 0.257 | tNET | RR | 1 | R69C41[2][A] | UserLayer_top_inst/ControlTransfer_inst/n4511_s21/I3 |
| 2.418 | 0.372 | tINS | RR | 10 | R69C41[2][A] | UserLayer_top_inst/ControlTransfer_inst/n4511_s21/F |
| 2.888 | 0.470 | tNET | RR | 1 | R70C47[3][B] | UserLayer_top_inst/ControlTransfer_inst/n4511_s17/I1 |
| 3.263 | 0.375 | tINS | RR | 11 | R70C47[3][B] | UserLayer_top_inst/ControlTransfer_inst/n4511_s17/F |
| 3.609 | 0.346 | tNET | RR | 1 | R70C40[3][B] | UserLayer_top_inst/ControlTransfer_inst/n688_s28/I3 |
| 3.985 | 0.375 | tINS | RR | 6 | R70C40[3][B] | UserLayer_top_inst/ControlTransfer_inst/n688_s28/F |
| 4.329 | 0.344 | tNET | RR | 1 | R64C40[3][B] | UserLayer_top_inst/ControlTransfer_inst/n6333_s3/I1 |
| 4.704 | 0.375 | tINS | RR | 5 | R64C40[3][B] | UserLayer_top_inst/ControlTransfer_inst/n6333_s3/F |
| 4.959 | 0.256 | tNET | RR | 1 | R63C38[3][B] | UserLayer_top_inst/ControlTransfer_inst/n6333_s5/I2 |
| 5.335 | 0.375 | tINS | RR | 64 | R63C38[3][B] | UserLayer_top_inst/ControlTransfer_inst/n6333_s5/F |
| 6.536 | 1.201 | tNET | RR | 1 | R59C47[0][B] | UserLayer_top_inst/ControlTransfer_inst/bFormatIndex_3_s0/CE |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.250 | 6.250 | active clock edge time | ||||
| 6.250 | 0.000 | pclk | ||||
| 6.250 | 0.000 | tCL | RR | 10163 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK |
| 7.763 | 1.513 | tNET | RR | 1 | R59C47[0][B] | UserLayer_top_inst/ControlTransfer_inst/bFormatIndex_3_s0/CLK |
| 7.539 | -0.224 | tSu | 1 | R59C47[0][B] | UserLayer_top_inst/ControlTransfer_inst/bFormatIndex_3_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 6.250 |
| Logic Level | 6 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.513, 100.000% |
| Arrival Data Path Delay | cell: 1.873, 37.287%; route: 2.875, 57.230%; tC2Q: 0.275, 5.483% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.513, 100.000% |
Path94
Path Summary:
| Slack | 1.003 |
| Data Arrival Time | 6.536 |
| Data Required Time | 7.539 |
| From | UserLayer_top_inst/ControlTransfer_inst/wValue_latch_9_s0 |
| To | UserLayer_top_inst/ControlTransfer_inst/bFormatIndex_4_s0 |
| Launch Clk | pclk:[R] |
| Latch Clk | pclk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | pclk | ||||
| 0.000 | 0.000 | tCL | RR | 10163 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK |
| 1.513 | 1.513 | tNET | RR | 1 | R68C39[1][B] | UserLayer_top_inst/ControlTransfer_inst/wValue_latch_9_s0/CLK |
| 1.789 | 0.275 | tC2Q | RR | 7 | R68C39[1][B] | UserLayer_top_inst/ControlTransfer_inst/wValue_latch_9_s0/Q |
| 2.046 | 0.257 | tNET | RR | 1 | R69C41[2][A] | UserLayer_top_inst/ControlTransfer_inst/n4511_s21/I3 |
| 2.418 | 0.372 | tINS | RR | 10 | R69C41[2][A] | UserLayer_top_inst/ControlTransfer_inst/n4511_s21/F |
| 2.888 | 0.470 | tNET | RR | 1 | R70C47[3][B] | UserLayer_top_inst/ControlTransfer_inst/n4511_s17/I1 |
| 3.263 | 0.375 | tINS | RR | 11 | R70C47[3][B] | UserLayer_top_inst/ControlTransfer_inst/n4511_s17/F |
| 3.609 | 0.346 | tNET | RR | 1 | R70C40[3][B] | UserLayer_top_inst/ControlTransfer_inst/n688_s28/I3 |
| 3.985 | 0.375 | tINS | RR | 6 | R70C40[3][B] | UserLayer_top_inst/ControlTransfer_inst/n688_s28/F |
| 4.329 | 0.344 | tNET | RR | 1 | R64C40[3][B] | UserLayer_top_inst/ControlTransfer_inst/n6333_s3/I1 |
| 4.704 | 0.375 | tINS | RR | 5 | R64C40[3][B] | UserLayer_top_inst/ControlTransfer_inst/n6333_s3/F |
| 4.959 | 0.256 | tNET | RR | 1 | R63C38[3][B] | UserLayer_top_inst/ControlTransfer_inst/n6333_s5/I2 |
| 5.335 | 0.375 | tINS | RR | 64 | R63C38[3][B] | UserLayer_top_inst/ControlTransfer_inst/n6333_s5/F |
| 6.536 | 1.201 | tNET | RR | 1 | R59C47[2][B] | UserLayer_top_inst/ControlTransfer_inst/bFormatIndex_4_s0/CE |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.250 | 6.250 | active clock edge time | ||||
| 6.250 | 0.000 | pclk | ||||
| 6.250 | 0.000 | tCL | RR | 10163 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK |
| 7.763 | 1.513 | tNET | RR | 1 | R59C47[2][B] | UserLayer_top_inst/ControlTransfer_inst/bFormatIndex_4_s0/CLK |
| 7.539 | -0.224 | tSu | 1 | R59C47[2][B] | UserLayer_top_inst/ControlTransfer_inst/bFormatIndex_4_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 6.250 |
| Logic Level | 6 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.513, 100.000% |
| Arrival Data Path Delay | cell: 1.873, 37.287%; route: 2.875, 57.230%; tC2Q: 0.275, 5.483% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.513, 100.000% |
Path95
Path Summary:
| Slack | 1.003 |
| Data Arrival Time | 6.536 |
| Data Required Time | 7.539 |
| From | UserLayer_top_inst/ControlTransfer_inst/wValue_latch_9_s0 |
| To | UserLayer_top_inst/ControlTransfer_inst/bmHint_0_s0 |
| Launch Clk | pclk:[R] |
| Latch Clk | pclk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | pclk | ||||
| 0.000 | 0.000 | tCL | RR | 10163 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK |
| 1.513 | 1.513 | tNET | RR | 1 | R68C39[1][B] | UserLayer_top_inst/ControlTransfer_inst/wValue_latch_9_s0/CLK |
| 1.789 | 0.275 | tC2Q | RR | 7 | R68C39[1][B] | UserLayer_top_inst/ControlTransfer_inst/wValue_latch_9_s0/Q |
| 2.046 | 0.257 | tNET | RR | 1 | R69C41[2][A] | UserLayer_top_inst/ControlTransfer_inst/n4511_s21/I3 |
| 2.418 | 0.372 | tINS | RR | 10 | R69C41[2][A] | UserLayer_top_inst/ControlTransfer_inst/n4511_s21/F |
| 2.888 | 0.470 | tNET | RR | 1 | R70C47[3][B] | UserLayer_top_inst/ControlTransfer_inst/n4511_s17/I1 |
| 3.263 | 0.375 | tINS | RR | 11 | R70C47[3][B] | UserLayer_top_inst/ControlTransfer_inst/n4511_s17/F |
| 3.609 | 0.346 | tNET | RR | 1 | R70C40[3][B] | UserLayer_top_inst/ControlTransfer_inst/n688_s28/I3 |
| 3.985 | 0.375 | tINS | RR | 6 | R70C40[3][B] | UserLayer_top_inst/ControlTransfer_inst/n688_s28/F |
| 4.329 | 0.344 | tNET | RR | 1 | R64C40[3][B] | UserLayer_top_inst/ControlTransfer_inst/n6333_s3/I1 |
| 4.704 | 0.375 | tINS | RR | 5 | R64C40[3][B] | UserLayer_top_inst/ControlTransfer_inst/n6333_s3/F |
| 4.959 | 0.256 | tNET | RR | 1 | R63C38[3][B] | UserLayer_top_inst/ControlTransfer_inst/n6333_s5/I2 |
| 5.335 | 0.375 | tINS | RR | 64 | R63C38[3][B] | UserLayer_top_inst/ControlTransfer_inst/n6333_s5/F |
| 6.536 | 1.201 | tNET | RR | 1 | R59C47[0][A] | UserLayer_top_inst/ControlTransfer_inst/bmHint_0_s0/CE |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.250 | 6.250 | active clock edge time | ||||
| 6.250 | 0.000 | pclk | ||||
| 6.250 | 0.000 | tCL | RR | 10163 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK |
| 7.763 | 1.513 | tNET | RR | 1 | R59C47[0][A] | UserLayer_top_inst/ControlTransfer_inst/bmHint_0_s0/CLK |
| 7.539 | -0.224 | tSu | 1 | R59C47[0][A] | UserLayer_top_inst/ControlTransfer_inst/bmHint_0_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 6.250 |
| Logic Level | 6 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.513, 100.000% |
| Arrival Data Path Delay | cell: 1.873, 37.287%; route: 2.875, 57.230%; tC2Q: 0.275, 5.483% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.513, 100.000% |
Path96
Path Summary:
| Slack | 1.005 |
| Data Arrival Time | 6.534 |
| Data Required Time | 7.539 |
| From | UserLayer_top_inst/ControlTransfer_inst/wValue_latch_9_s0 |
| To | UserLayer_top_inst/ControlTransfer_inst/dwFrameInterval_13_s0 |
| Launch Clk | pclk:[R] |
| Latch Clk | pclk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | pclk | ||||
| 0.000 | 0.000 | tCL | RR | 10163 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK |
| 1.513 | 1.513 | tNET | RR | 1 | R68C39[1][B] | UserLayer_top_inst/ControlTransfer_inst/wValue_latch_9_s0/CLK |
| 1.789 | 0.275 | tC2Q | RR | 7 | R68C39[1][B] | UserLayer_top_inst/ControlTransfer_inst/wValue_latch_9_s0/Q |
| 2.046 | 0.257 | tNET | RR | 1 | R69C41[2][A] | UserLayer_top_inst/ControlTransfer_inst/n4511_s21/I3 |
| 2.418 | 0.372 | tINS | RR | 10 | R69C41[2][A] | UserLayer_top_inst/ControlTransfer_inst/n4511_s21/F |
| 2.888 | 0.470 | tNET | RR | 1 | R70C47[3][B] | UserLayer_top_inst/ControlTransfer_inst/n4511_s17/I1 |
| 3.263 | 0.375 | tINS | RR | 11 | R70C47[3][B] | UserLayer_top_inst/ControlTransfer_inst/n4511_s17/F |
| 3.609 | 0.346 | tNET | RR | 1 | R70C40[3][B] | UserLayer_top_inst/ControlTransfer_inst/n688_s28/I3 |
| 3.985 | 0.375 | tINS | RR | 6 | R70C40[3][B] | UserLayer_top_inst/ControlTransfer_inst/n688_s28/F |
| 4.329 | 0.344 | tNET | RR | 1 | R64C40[3][B] | UserLayer_top_inst/ControlTransfer_inst/n6333_s3/I1 |
| 4.704 | 0.375 | tINS | RR | 5 | R64C40[3][B] | UserLayer_top_inst/ControlTransfer_inst/n6333_s3/F |
| 4.959 | 0.256 | tNET | RR | 1 | R63C38[3][B] | UserLayer_top_inst/ControlTransfer_inst/n6333_s5/I2 |
| 5.335 | 0.375 | tINS | RR | 64 | R63C38[3][B] | UserLayer_top_inst/ControlTransfer_inst/n6333_s5/F |
| 6.534 | 1.200 | tNET | RR | 1 | R62C47[1][A] | UserLayer_top_inst/ControlTransfer_inst/dwFrameInterval_13_s0/CE |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.250 | 6.250 | active clock edge time | ||||
| 6.250 | 0.000 | pclk | ||||
| 6.250 | 0.000 | tCL | RR | 10163 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK |
| 7.763 | 1.513 | tNET | RR | 1 | R62C47[1][A] | UserLayer_top_inst/ControlTransfer_inst/dwFrameInterval_13_s0/CLK |
| 7.539 | -0.224 | tSu | 1 | R62C47[1][A] | UserLayer_top_inst/ControlTransfer_inst/dwFrameInterval_13_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 6.250 |
| Logic Level | 6 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.513, 100.000% |
| Arrival Data Path Delay | cell: 1.873, 37.301%; route: 2.873, 57.215%; tC2Q: 0.275, 5.485% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.513, 100.000% |
Path97
Path Summary:
| Slack | 1.005 |
| Data Arrival Time | 6.534 |
| Data Required Time | 7.539 |
| From | UserLayer_top_inst/ControlTransfer_inst/wValue_latch_9_s0 |
| To | UserLayer_top_inst/ControlTransfer_inst/dwFrameInterval_15_s0 |
| Launch Clk | pclk:[R] |
| Latch Clk | pclk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | pclk | ||||
| 0.000 | 0.000 | tCL | RR | 10163 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK |
| 1.513 | 1.513 | tNET | RR | 1 | R68C39[1][B] | UserLayer_top_inst/ControlTransfer_inst/wValue_latch_9_s0/CLK |
| 1.789 | 0.275 | tC2Q | RR | 7 | R68C39[1][B] | UserLayer_top_inst/ControlTransfer_inst/wValue_latch_9_s0/Q |
| 2.046 | 0.257 | tNET | RR | 1 | R69C41[2][A] | UserLayer_top_inst/ControlTransfer_inst/n4511_s21/I3 |
| 2.418 | 0.372 | tINS | RR | 10 | R69C41[2][A] | UserLayer_top_inst/ControlTransfer_inst/n4511_s21/F |
| 2.888 | 0.470 | tNET | RR | 1 | R70C47[3][B] | UserLayer_top_inst/ControlTransfer_inst/n4511_s17/I1 |
| 3.263 | 0.375 | tINS | RR | 11 | R70C47[3][B] | UserLayer_top_inst/ControlTransfer_inst/n4511_s17/F |
| 3.609 | 0.346 | tNET | RR | 1 | R70C40[3][B] | UserLayer_top_inst/ControlTransfer_inst/n688_s28/I3 |
| 3.985 | 0.375 | tINS | RR | 6 | R70C40[3][B] | UserLayer_top_inst/ControlTransfer_inst/n688_s28/F |
| 4.329 | 0.344 | tNET | RR | 1 | R64C40[3][B] | UserLayer_top_inst/ControlTransfer_inst/n6333_s3/I1 |
| 4.704 | 0.375 | tINS | RR | 5 | R64C40[3][B] | UserLayer_top_inst/ControlTransfer_inst/n6333_s3/F |
| 4.959 | 0.256 | tNET | RR | 1 | R63C38[3][B] | UserLayer_top_inst/ControlTransfer_inst/n6333_s5/I2 |
| 5.335 | 0.375 | tINS | RR | 64 | R63C38[3][B] | UserLayer_top_inst/ControlTransfer_inst/n6333_s5/F |
| 6.534 | 1.200 | tNET | RR | 1 | R60C49[3][A] | UserLayer_top_inst/ControlTransfer_inst/dwFrameInterval_15_s0/CE |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.250 | 6.250 | active clock edge time | ||||
| 6.250 | 0.000 | pclk | ||||
| 6.250 | 0.000 | tCL | RR | 10163 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK |
| 7.763 | 1.513 | tNET | RR | 1 | R60C49[3][A] | UserLayer_top_inst/ControlTransfer_inst/dwFrameInterval_15_s0/CLK |
| 7.539 | -0.224 | tSu | 1 | R60C49[3][A] | UserLayer_top_inst/ControlTransfer_inst/dwFrameInterval_15_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 6.250 |
| Logic Level | 6 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.513, 100.000% |
| Arrival Data Path Delay | cell: 1.873, 37.301%; route: 2.873, 57.215%; tC2Q: 0.275, 5.485% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.513, 100.000% |
Path98
Path Summary:
| Slack | 1.005 |
| Data Arrival Time | 6.534 |
| Data Required Time | 7.539 |
| From | UserLayer_top_inst/ControlTransfer_inst/wValue_latch_9_s0 |
| To | UserLayer_top_inst/ControlTransfer_inst/bFormatIndex_5_s0 |
| Launch Clk | pclk:[R] |
| Latch Clk | pclk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | pclk | ||||
| 0.000 | 0.000 | tCL | RR | 10163 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK |
| 1.513 | 1.513 | tNET | RR | 1 | R68C39[1][B] | UserLayer_top_inst/ControlTransfer_inst/wValue_latch_9_s0/CLK |
| 1.789 | 0.275 | tC2Q | RR | 7 | R68C39[1][B] | UserLayer_top_inst/ControlTransfer_inst/wValue_latch_9_s0/Q |
| 2.046 | 0.257 | tNET | RR | 1 | R69C41[2][A] | UserLayer_top_inst/ControlTransfer_inst/n4511_s21/I3 |
| 2.418 | 0.372 | tINS | RR | 10 | R69C41[2][A] | UserLayer_top_inst/ControlTransfer_inst/n4511_s21/F |
| 2.888 | 0.470 | tNET | RR | 1 | R70C47[3][B] | UserLayer_top_inst/ControlTransfer_inst/n4511_s17/I1 |
| 3.263 | 0.375 | tINS | RR | 11 | R70C47[3][B] | UserLayer_top_inst/ControlTransfer_inst/n4511_s17/F |
| 3.609 | 0.346 | tNET | RR | 1 | R70C40[3][B] | UserLayer_top_inst/ControlTransfer_inst/n688_s28/I3 |
| 3.985 | 0.375 | tINS | RR | 6 | R70C40[3][B] | UserLayer_top_inst/ControlTransfer_inst/n688_s28/F |
| 4.329 | 0.344 | tNET | RR | 1 | R64C40[3][B] | UserLayer_top_inst/ControlTransfer_inst/n6333_s3/I1 |
| 4.704 | 0.375 | tINS | RR | 5 | R64C40[3][B] | UserLayer_top_inst/ControlTransfer_inst/n6333_s3/F |
| 4.959 | 0.256 | tNET | RR | 1 | R63C38[3][B] | UserLayer_top_inst/ControlTransfer_inst/n6333_s5/I2 |
| 5.335 | 0.375 | tINS | RR | 64 | R63C38[3][B] | UserLayer_top_inst/ControlTransfer_inst/n6333_s5/F |
| 6.534 | 1.200 | tNET | RR | 1 | R60C49[2][A] | UserLayer_top_inst/ControlTransfer_inst/bFormatIndex_5_s0/CE |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.250 | 6.250 | active clock edge time | ||||
| 6.250 | 0.000 | pclk | ||||
| 6.250 | 0.000 | tCL | RR | 10163 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK |
| 7.763 | 1.513 | tNET | RR | 1 | R60C49[2][A] | UserLayer_top_inst/ControlTransfer_inst/bFormatIndex_5_s0/CLK |
| 7.539 | -0.224 | tSu | 1 | R60C49[2][A] | UserLayer_top_inst/ControlTransfer_inst/bFormatIndex_5_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 6.250 |
| Logic Level | 6 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.513, 100.000% |
| Arrival Data Path Delay | cell: 1.873, 37.301%; route: 2.873, 57.215%; tC2Q: 0.275, 5.485% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.513, 100.000% |
Path99
Path Summary:
| Slack | 1.006 |
| Data Arrival Time | 6.593 |
| Data Required Time | 7.600 |
| From | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/ltssm_go_u_d0_2_s0 |
| To | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/state_2_s0 |
| Launch Clk | pclk:[R] |
| Latch Clk | pclk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | pclk | ||||
| 0.000 | 0.000 | tCL | RR | 10163 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK |
| 1.520 | 1.520 | tNET | RR | 1 | R9C99[1][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/ltssm_go_u_d0_2_s0/CLK |
| 1.795 | 0.275 | tC2Q | RR | 7 | R9C99[1][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/ltssm_go_u_d0_2_s0/Q |
| 2.051 | 0.256 | tNET | RR | 1 | R11C99[1][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/n2440_s82/I2 |
| 2.423 | 0.372 | tINS | RR | 3 | R11C99[1][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/n2440_s82/F |
| 2.540 | 0.117 | tNET | RR | 1 | R11C98[1][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/n2382_s128/I2 |
| 2.872 | 0.332 | tINS | RR | 1 | R11C98[1][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/n2382_s128/F |
| 2.874 | 0.002 | tNET | RR | 1 | R11C98[3][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/n2382_s122/I3 |
| 3.249 | 0.375 | tINS | RR | 1 | R11C98[3][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/n2382_s122/F |
| 3.654 | 0.405 | tNET | RR | 1 | R9C101[0][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/n2382_s113/I2 |
| 4.026 | 0.372 | tINS | RR | 1 | R9C101[0][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/n2382_s113/F |
| 4.609 | 0.583 | tNET | RR | 1 | R6C107[1][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/n2382_s149/I1 |
| 4.988 | 0.379 | tINS | RR | 1 | R6C107[1][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/n2382_s149/F |
| 4.988 | 0.000 | tNET | RR | 1 | R6C107[1][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/n2382_s143/I0 |
| 5.086 | 0.098 | tINS | RR | 1 | R6C107[1][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/n2382_s143/O |
| 5.086 | 0.000 | tNET | RR | 1 | R6C107[0][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/n2382_s140/I0 |
| 5.148 | 0.062 | tINS | RR | 1 | R6C107[0][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/n2382_s140/O |
| 5.148 | 0.000 | tNET | RR | 1 | R6C107[1][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/n2382_s93/I1 |
| 5.210 | 0.062 | tINS | RR | 1 | R6C107[1][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/n2382_s93/O |
| 5.811 | 0.601 | tNET | RR | 1 | R9C102[2][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/n6062_s1/I2 |
| 6.143 | 0.332 | tINS | RR | 1 | R9C102[2][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/n6062_s1/F |
| 6.593 | 0.450 | tNET | RR | 1 | R7C98[0][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/state_2_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.250 | 6.250 | active clock edge time | ||||
| 6.250 | 0.000 | pclk | ||||
| 6.250 | 0.000 | tCL | RR | 10163 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK |
| 7.763 | 1.513 | tNET | RR | 1 | R7C98[0][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/state_2_s0/CLK |
| 7.600 | -0.164 | tSu | 1 | R7C98[0][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/state_2_s0 |
Path Statistics:
| Clock Skew | -0.007 |
| Setup Relationship | 6.250 |
| Logic Level | 8 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.520, 100.000% |
| Arrival Data Path Delay | cell: 2.384, 46.993%; route: 2.414, 47.578%; tC2Q: 0.275, 5.428% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.513, 100.000% |
Path100
Path Summary:
| Slack | 1.007 |
| Data Arrival Time | 6.533 |
| Data Required Time | 7.539 |
| From | UserLayer_top_inst/ControlTransfer_inst/wValue_latch_9_s0 |
| To | UserLayer_top_inst/ControlTransfer_inst/dwFrameInterval_7_s0 |
| Launch Clk | pclk:[R] |
| Latch Clk | pclk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | pclk | ||||
| 0.000 | 0.000 | tCL | RR | 10163 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK |
| 1.513 | 1.513 | tNET | RR | 1 | R68C39[1][B] | UserLayer_top_inst/ControlTransfer_inst/wValue_latch_9_s0/CLK |
| 1.789 | 0.275 | tC2Q | RR | 7 | R68C39[1][B] | UserLayer_top_inst/ControlTransfer_inst/wValue_latch_9_s0/Q |
| 2.046 | 0.257 | tNET | RR | 1 | R69C41[2][A] | UserLayer_top_inst/ControlTransfer_inst/n4511_s21/I3 |
| 2.418 | 0.372 | tINS | RR | 10 | R69C41[2][A] | UserLayer_top_inst/ControlTransfer_inst/n4511_s21/F |
| 2.888 | 0.470 | tNET | RR | 1 | R70C47[3][B] | UserLayer_top_inst/ControlTransfer_inst/n4511_s17/I1 |
| 3.263 | 0.375 | tINS | RR | 11 | R70C47[3][B] | UserLayer_top_inst/ControlTransfer_inst/n4511_s17/F |
| 3.609 | 0.346 | tNET | RR | 1 | R70C40[3][B] | UserLayer_top_inst/ControlTransfer_inst/n688_s28/I3 |
| 3.985 | 0.375 | tINS | RR | 6 | R70C40[3][B] | UserLayer_top_inst/ControlTransfer_inst/n688_s28/F |
| 4.329 | 0.344 | tNET | RR | 1 | R64C40[3][B] | UserLayer_top_inst/ControlTransfer_inst/n6333_s3/I1 |
| 4.704 | 0.375 | tINS | RR | 5 | R64C40[3][B] | UserLayer_top_inst/ControlTransfer_inst/n6333_s3/F |
| 4.959 | 0.256 | tNET | RR | 1 | R63C38[3][B] | UserLayer_top_inst/ControlTransfer_inst/n6333_s5/I2 |
| 5.335 | 0.375 | tINS | RR | 64 | R63C38[3][B] | UserLayer_top_inst/ControlTransfer_inst/n6333_s5/F |
| 6.533 | 1.198 | tNET | RR | 1 | R61C47[1][B] | UserLayer_top_inst/ControlTransfer_inst/dwFrameInterval_7_s0/CE |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.250 | 6.250 | active clock edge time | ||||
| 6.250 | 0.000 | pclk | ||||
| 6.250 | 0.000 | tCL | RR | 10163 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK |
| 7.763 | 1.513 | tNET | RR | 1 | R61C47[1][B] | UserLayer_top_inst/ControlTransfer_inst/dwFrameInterval_7_s0/CLK |
| 7.539 | -0.224 | tSu | 1 | R61C47[1][B] | UserLayer_top_inst/ControlTransfer_inst/dwFrameInterval_7_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 6.250 |
| Logic Level | 6 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.513, 100.000% |
| Arrival Data Path Delay | cell: 1.873, 37.314%; route: 2.871, 57.199%; tC2Q: 0.275, 5.487% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.513, 100.000% |
Hold Analysis Report
Report Command:report_timing -hold -max_paths 25 -max_common_paths 1
Path1
Path Summary:
| Slack | 0.043 |
| Data Arrival Time | 1.174 |
| Data Required Time | 1.130 |
| From | u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_data_51_s0 |
| To | u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.mem_Big.mem_0_6_s |
| Launch Clk | rgb_clk:[R] |
| Latch Clk | rgb_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | rgb_clk | ||||
| 0.000 | 0.000 | tCL | RR | 431 | PLL_L[1] | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0 |
| 0.920 | 0.920 | tNET | RR | 1 | R39C14[1][B] | u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_data_51_s0/CLK |
| 1.049 | 0.130 | tC2Q | RR | 1 | R39C14[1][B] | u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_data_51_s0/Q |
| 1.174 | 0.124 | tNET | RR | 1 | BSRAM_R38[2][A] | u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.mem_Big.mem_0_6_s/DI[3] |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | rgb_clk | ||||
| 0.000 | 0.000 | tCL | RR | 431 | PLL_L[1] | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0 |
| 1.097 | 1.097 | tNET | RR | 1 | BSRAM_R38[2][A] | u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.mem_Big.mem_0_6_s/CLKA |
| 1.130 | 0.033 | tHld | 1 | BSRAM_R38[2][A] | u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.mem_Big.mem_0_6_s |
Path Statistics:
| Clock Skew | 0.177 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.920, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.124, 48.936%; tC2Q: 0.130, 51.064% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.097, 100.000% |
Path2
Path Summary:
| Slack | 0.043 |
| Data Arrival Time | 1.174 |
| Data Required Time | 1.130 |
| From | u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_data_48_s0 |
| To | u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.mem_Big.mem_0_6_s |
| Launch Clk | rgb_clk:[R] |
| Latch Clk | rgb_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | rgb_clk | ||||
| 0.000 | 0.000 | tCL | RR | 431 | PLL_L[1] | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0 |
| 0.920 | 0.920 | tNET | RR | 1 | R40C14[0][A] | u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_data_48_s0/CLK |
| 1.049 | 0.130 | tC2Q | RR | 1 | R40C14[0][A] | u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_data_48_s0/Q |
| 1.174 | 0.124 | tNET | RR | 1 | BSRAM_R38[2][A] | u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.mem_Big.mem_0_6_s/DI[0] |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | rgb_clk | ||||
| 0.000 | 0.000 | tCL | RR | 431 | PLL_L[1] | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0 |
| 1.097 | 1.097 | tNET | RR | 1 | BSRAM_R38[2][A] | u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.mem_Big.mem_0_6_s/CLKA |
| 1.130 | 0.033 | tHld | 1 | BSRAM_R38[2][A] | u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.mem_Big.mem_0_6_s |
Path Statistics:
| Clock Skew | 0.177 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.920, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.124, 48.936%; tC2Q: 0.130, 51.064% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.097, 100.000% |
Path3
Path Summary:
| Slack | 0.043 |
| Data Arrival Time | 1.181 |
| Data Required Time | 1.138 |
| From | u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_data_22_s0 |
| To | u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.mem_Big.mem_0_2_s |
| Launch Clk | rgb_clk:[R] |
| Latch Clk | rgb_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | rgb_clk | ||||
| 0.000 | 0.000 | tCL | RR | 431 | PLL_L[1] | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0 |
| 0.927 | 0.927 | tNET | RR | 1 | R39C20[3][A] | u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_data_22_s0/CLK |
| 1.057 | 0.130 | tC2Q | RR | 1 | R39C20[3][A] | u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_data_22_s0/Q |
| 1.181 | 0.124 | tNET | RR | 1 | BSRAM_R38[3] | u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.mem_Big.mem_0_2_s/DI[6] |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | rgb_clk | ||||
| 0.000 | 0.000 | tCL | RR | 431 | PLL_L[1] | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0 |
| 1.104 | 1.104 | tNET | RR | 1 | BSRAM_R38[3] | u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.mem_Big.mem_0_2_s/CLKA |
| 1.138 | 0.033 | tHld | 1 | BSRAM_R38[3] | u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.mem_Big.mem_0_2_s |
Path Statistics:
| Clock Skew | 0.177 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.927, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.124, 48.936%; tC2Q: 0.130, 51.064% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.104, 100.000% |
Path4
Path Summary:
| Slack | 0.043 |
| Data Arrival Time | 1.181 |
| Data Required Time | 1.138 |
| From | u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_data_21_s0 |
| To | u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.mem_Big.mem_0_2_s |
| Launch Clk | rgb_clk:[R] |
| Latch Clk | rgb_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | rgb_clk | ||||
| 0.000 | 0.000 | tCL | RR | 431 | PLL_L[1] | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0 |
| 0.927 | 0.927 | tNET | RR | 1 | R39C20[0][A] | u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_data_21_s0/CLK |
| 1.057 | 0.130 | tC2Q | RR | 1 | R39C20[0][A] | u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_data_21_s0/Q |
| 1.181 | 0.124 | tNET | RR | 1 | BSRAM_R38[3] | u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.mem_Big.mem_0_2_s/DI[5] |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | rgb_clk | ||||
| 0.000 | 0.000 | tCL | RR | 431 | PLL_L[1] | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0 |
| 1.104 | 1.104 | tNET | RR | 1 | BSRAM_R38[3] | u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.mem_Big.mem_0_2_s/CLKA |
| 1.138 | 0.033 | tHld | 1 | BSRAM_R38[3] | u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.mem_Big.mem_0_2_s |
Path Statistics:
| Clock Skew | 0.177 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.927, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.124, 48.936%; tC2Q: 0.130, 51.064% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.104, 100.000% |
Path5
Path Summary:
| Slack | 0.043 |
| Data Arrival Time | 1.181 |
| Data Required Time | 1.138 |
| From | u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_data_19_s0 |
| To | u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.mem_Big.mem_0_2_s |
| Launch Clk | rgb_clk:[R] |
| Latch Clk | rgb_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | rgb_clk | ||||
| 0.000 | 0.000 | tCL | RR | 431 | PLL_L[1] | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0 |
| 0.927 | 0.927 | tNET | RR | 1 | R39C20[2][B] | u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_data_19_s0/CLK |
| 1.057 | 0.130 | tC2Q | RR | 1 | R39C20[2][B] | u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_data_19_s0/Q |
| 1.181 | 0.124 | tNET | RR | 1 | BSRAM_R38[3] | u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.mem_Big.mem_0_2_s/DI[3] |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | rgb_clk | ||||
| 0.000 | 0.000 | tCL | RR | 431 | PLL_L[1] | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0 |
| 1.104 | 1.104 | tNET | RR | 1 | BSRAM_R38[3] | u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.mem_Big.mem_0_2_s/CLKA |
| 1.138 | 0.033 | tHld | 1 | BSRAM_R38[3] | u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.mem_Big.mem_0_2_s |
Path Statistics:
| Clock Skew | 0.177 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.927, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.124, 48.936%; tC2Q: 0.130, 51.064% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.104, 100.000% |
Path6
Path Summary:
| Slack | 0.043 |
| Data Arrival Time | 1.177 |
| Data Required Time | 1.134 |
| From | u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_data_47_s0 |
| To | u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.mem_Big.mem_0_5_s |
| Launch Clk | rgb_clk:[R] |
| Latch Clk | rgb_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | rgb_clk | ||||
| 0.000 | 0.000 | tCL | RR | 431 | PLL_L[1] | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0 |
| 0.923 | 0.923 | tNET | RR | 1 | R39C17[0][B] | u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_data_47_s0/CLK |
| 1.053 | 0.130 | tC2Q | RR | 1 | R39C17[0][B] | u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_data_47_s0/Q |
| 1.177 | 0.124 | tNET | RR | 1 | BSRAM_R38[2][B] | u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.mem_Big.mem_0_5_s/DI[7] |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | rgb_clk | ||||
| 0.000 | 0.000 | tCL | RR | 431 | PLL_L[1] | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0 |
| 1.101 | 1.101 | tNET | RR | 1 | BSRAM_R38[2][B] | u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.mem_Big.mem_0_5_s/CLKA |
| 1.134 | 0.033 | tHld | 1 | BSRAM_R38[2][B] | u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.mem_Big.mem_0_5_s |
Path Statistics:
| Clock Skew | 0.177 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.923, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.124, 48.936%; tC2Q: 0.130, 51.064% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.101, 100.000% |
Path7
Path Summary:
| Slack | 0.057 |
| Data Arrival Time | 0.874 |
| Data Required Time | 0.817 |
| From | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/gen_in_ep_ping_pong[2].transfer_in_mem_ping_pong_inst/GEN_TRANSFER_IN_MEM[1].transfer_in_mem_inst/transfer_in_pkt_rd_addr_6_s1 |
| To | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/gen_in_ep_ping_pong[2].transfer_in_mem_ping_pong_inst/GEN_TRANSFER_IN_MEM[1].transfer_in_mem_inst/mem0_mem0_0_2_s |
| Launch Clk | pclk:[R] |
| Latch Clk | pclk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | pclk | ||||
| 0.000 | 0.000 | tCL | RR | 10163 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK |
| 0.608 | 0.608 | tNET | RR | 1 | R42C45[2][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/gen_in_ep_ping_pong[2].transfer_in_mem_ping_pong_inst/GEN_TRANSFER_IN_MEM[1].transfer_in_mem_inst/transfer_in_pkt_rd_addr_6_s1/CLK |
| 0.738 | 0.130 | tC2Q | RR | 6 | R42C45[2][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/gen_in_ep_ping_pong[2].transfer_in_mem_ping_pong_inst/GEN_TRANSFER_IN_MEM[1].transfer_in_mem_inst/transfer_in_pkt_rd_addr_6_s1/Q |
| 0.874 | 0.136 | tNET | RR | 1 | BSRAM_R38[8][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/gen_in_ep_ping_pong[2].transfer_in_mem_ping_pong_inst/GEN_TRANSFER_IN_MEM[1].transfer_in_mem_inst/mem0_mem0_0_2_s/ADB[10] |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | pclk | ||||
| 0.000 | 0.000 | tCL | RR | 10163 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK |
| 0.786 | 0.786 | tNET | RR | 1 | BSRAM_R38[8][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/gen_in_ep_ping_pong[2].transfer_in_mem_ping_pong_inst/GEN_TRANSFER_IN_MEM[1].transfer_in_mem_inst/mem0_mem0_0_2_s/CLKB |
| 0.817 | 0.032 | tHld | 1 | BSRAM_R38[8][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/gen_in_ep_ping_pong[2].transfer_in_mem_ping_pong_inst/GEN_TRANSFER_IN_MEM[1].transfer_in_mem_inst/mem0_mem0_0_2_s |
Path Statistics:
| Clock Skew | 0.177 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.608, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.136, 51.186%; tC2Q: 0.130, 48.814% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.786, 100.000% |
Path8
Path Summary:
| Slack | 0.059 |
| Data Arrival Time | 0.876 |
| Data Required Time | 0.817 |
| From | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/gen_in_ep_ping_pong[2].transfer_in_mem_ping_pong_inst/GEN_TRANSFER_IN_MEM[1].transfer_in_mem_inst/transfer_in_pkt_rd_addr_1_s1 |
| To | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/gen_in_ep_ping_pong[2].transfer_in_mem_ping_pong_inst/GEN_TRANSFER_IN_MEM[1].transfer_in_mem_inst/mem0_mem0_0_2_s |
| Launch Clk | pclk:[R] |
| Latch Clk | pclk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | pclk | ||||
| 0.000 | 0.000 | tCL | RR | 10163 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK |
| 0.612 | 0.612 | tNET | RR | 1 | R42C46[2][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/gen_in_ep_ping_pong[2].transfer_in_mem_ping_pong_inst/GEN_TRANSFER_IN_MEM[1].transfer_in_mem_inst/transfer_in_pkt_rd_addr_1_s1/CLK |
| 0.742 | 0.130 | tC2Q | RR | 8 | R42C46[2][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/gen_in_ep_ping_pong[2].transfer_in_mem_ping_pong_inst/GEN_TRANSFER_IN_MEM[1].transfer_in_mem_inst/transfer_in_pkt_rd_addr_1_s1/Q |
| 0.876 | 0.134 | tNET | RR | 1 | BSRAM_R38[8][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/gen_in_ep_ping_pong[2].transfer_in_mem_ping_pong_inst/GEN_TRANSFER_IN_MEM[1].transfer_in_mem_inst/mem0_mem0_0_2_s/ADB[5] |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | pclk | ||||
| 0.000 | 0.000 | tCL | RR | 10163 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK |
| 0.786 | 0.786 | tNET | RR | 1 | BSRAM_R38[8][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/gen_in_ep_ping_pong[2].transfer_in_mem_ping_pong_inst/GEN_TRANSFER_IN_MEM[1].transfer_in_mem_inst/mem0_mem0_0_2_s/CLKB |
| 0.817 | 0.032 | tHld | 1 | BSRAM_R38[8][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/gen_in_ep_ping_pong[2].transfer_in_mem_ping_pong_inst/GEN_TRANSFER_IN_MEM[1].transfer_in_mem_inst/mem0_mem0_0_2_s |
Path Statistics:
| Clock Skew | 0.174 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.612, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.134, 50.853%; tC2Q: 0.130, 49.147% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.786, 100.000% |
Path9
Path Summary:
| Slack | 0.061 |
| Data Arrival Time | 0.878 |
| Data Required Time | 0.817 |
| From | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/gen_in_ep_ping_pong[2].transfer_in_mem_ping_pong_inst/GEN_TRANSFER_IN_MEM[1].transfer_in_mem_inst/transfer_in_pkt_rd_addr_2_s1 |
| To | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/gen_in_ep_ping_pong[2].transfer_in_mem_ping_pong_inst/GEN_TRANSFER_IN_MEM[1].transfer_in_mem_inst/mem0_mem0_0_2_s |
| Launch Clk | pclk:[R] |
| Latch Clk | pclk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | pclk | ||||
| 0.000 | 0.000 | tCL | RR | 10163 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK |
| 0.612 | 0.612 | tNET | RR | 1 | R42C46[2][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/gen_in_ep_ping_pong[2].transfer_in_mem_ping_pong_inst/GEN_TRANSFER_IN_MEM[1].transfer_in_mem_inst/transfer_in_pkt_rd_addr_2_s1/CLK |
| 0.742 | 0.130 | tC2Q | RR | 7 | R42C46[2][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/gen_in_ep_ping_pong[2].transfer_in_mem_ping_pong_inst/GEN_TRANSFER_IN_MEM[1].transfer_in_mem_inst/transfer_in_pkt_rd_addr_2_s1/Q |
| 0.878 | 0.137 | tNET | RR | 1 | BSRAM_R38[8][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/gen_in_ep_ping_pong[2].transfer_in_mem_ping_pong_inst/GEN_TRANSFER_IN_MEM[1].transfer_in_mem_inst/mem0_mem0_0_2_s/ADB[6] |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | pclk | ||||
| 0.000 | 0.000 | tCL | RR | 10163 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK |
| 0.786 | 0.786 | tNET | RR | 1 | BSRAM_R38[8][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/gen_in_ep_ping_pong[2].transfer_in_mem_ping_pong_inst/GEN_TRANSFER_IN_MEM[1].transfer_in_mem_inst/mem0_mem0_0_2_s/CLKB |
| 0.817 | 0.032 | tHld | 1 | BSRAM_R38[8][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/gen_in_ep_ping_pong[2].transfer_in_mem_ping_pong_inst/GEN_TRANSFER_IN_MEM[1].transfer_in_mem_inst/mem0_mem0_0_2_s |
Path Statistics:
| Clock Skew | 0.174 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.612, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.137, 51.351%; tC2Q: 0.130, 48.649% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.786, 100.000% |
Path10
Path Summary:
| Slack | 0.062 |
| Data Arrival Time | 1.192 |
| Data Required Time | 1.130 |
| From | u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wbin_0_s0 |
| To | u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.mem_Big.mem_0_6_s |
| Launch Clk | rgb_clk:[R] |
| Latch Clk | rgb_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | rgb_clk | ||||
| 0.000 | 0.000 | tCL | RR | 431 | PLL_L[1] | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0 |
| 0.923 | 0.923 | tNET | RR | 1 | R39C15[1][A] | u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wbin_0_s0/CLK |
| 1.053 | 0.130 | tC2Q | RR | 11 | R39C15[1][A] | u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wbin_0_s0/Q |
| 1.192 | 0.139 | tNET | RR | 1 | BSRAM_R38[2][A] | u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.mem_Big.mem_0_6_s/ADA[3] |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | rgb_clk | ||||
| 0.000 | 0.000 | tCL | RR | 431 | PLL_L[1] | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0 |
| 1.097 | 1.097 | tNET | RR | 1 | BSRAM_R38[2][A] | u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.mem_Big.mem_0_6_s/CLKA |
| 1.130 | 0.033 | tHld | 1 | BSRAM_R38[2][A] | u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.mem_Big.mem_0_6_s |
Path Statistics:
| Clock Skew | 0.174 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.923, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.139, 51.839%; tC2Q: 0.130, 48.161% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.097, 100.000% |
Path11
Path Summary:
| Slack | 0.069 |
| Data Arrival Time | 0.883 |
| Data Required Time | 0.814 |
| From | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/gen_in_ep_ping_pong[2].transfer_in_mem_ping_pong_inst/GEN_TRANSFER_IN_MEM[1].transfer_in_mem_inst/transfer_in_pkt_rd_addr_6_s1 |
| To | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/gen_in_ep_ping_pong[2].transfer_in_mem_ping_pong_inst/GEN_TRANSFER_IN_MEM[1].transfer_in_mem_inst/mem0_mem0_0_0_s |
| Launch Clk | pclk:[R] |
| Latch Clk | pclk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | pclk | ||||
| 0.000 | 0.000 | tCL | RR | 10163 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK |
| 0.608 | 0.608 | tNET | RR | 1 | R42C45[2][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/gen_in_ep_ping_pong[2].transfer_in_mem_ping_pong_inst/GEN_TRANSFER_IN_MEM[1].transfer_in_mem_inst/transfer_in_pkt_rd_addr_6_s1/CLK |
| 0.738 | 0.130 | tC2Q | RR | 6 | R42C45[2][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/gen_in_ep_ping_pong[2].transfer_in_mem_ping_pong_inst/GEN_TRANSFER_IN_MEM[1].transfer_in_mem_inst/transfer_in_pkt_rd_addr_6_s1/Q |
| 0.883 | 0.145 | tNET | RR | 1 | BSRAM_R38[9] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/gen_in_ep_ping_pong[2].transfer_in_mem_ping_pong_inst/GEN_TRANSFER_IN_MEM[1].transfer_in_mem_inst/mem0_mem0_0_0_s/ADB[10] |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | pclk | ||||
| 0.000 | 0.000 | tCL | RR | 10163 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK |
| 0.782 | 0.782 | tNET | RR | 1 | BSRAM_R38[9] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/gen_in_ep_ping_pong[2].transfer_in_mem_ping_pong_inst/GEN_TRANSFER_IN_MEM[1].transfer_in_mem_inst/mem0_mem0_0_0_s/CLKB |
| 0.814 | 0.032 | tHld | 1 | BSRAM_R38[9] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/gen_in_ep_ping_pong[2].transfer_in_mem_ping_pong_inst/GEN_TRANSFER_IN_MEM[1].transfer_in_mem_inst/mem0_mem0_0_0_s |
Path Statistics:
| Clock Skew | 0.174 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.608, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.145, 52.787%; tC2Q: 0.130, 47.213% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.782, 100.000% |
Path12
Path Summary:
| Slack | 0.086 |
| Data Arrival Time | 0.739 |
| Data Required Time | 0.653 |
| From | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/rx_dph_len_d[5]_8_s0 |
| To | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/rx_dph_len_d[6]_0_s9 |
| Launch Clk | pclk:[R] |
| Latch Clk | pclk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | pclk | ||||
| 0.000 | 0.000 | tCL | RR | 10163 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK |
| 0.612 | 0.612 | tNET | RR | 1 | R9C103[0][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/rx_dph_len_d[5]_8_s0/CLK |
| 0.739 | 0.127 | tC2Q | RF | 1 | R9C103[0][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/rx_dph_len_d[5]_8_s0/Q |
| 0.739 | 0.000 | tNET | FF | 1 | R9C90 | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/rx_dph_len_d[6]_0_s9/DI[0] |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | pclk | ||||
| 0.000 | 0.000 | tCL | RR | 10163 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK |
| 0.608 | 0.608 | tNET | RR | 1 | R9C90 | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/rx_dph_len_d[6]_0_s9/CLK |
| 0.653 | 0.045 | tHld | 1 | R9C90 | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/rx_dph_len_d[6]_0_s9 |
Path Statistics:
| Clock Skew | -0.004 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.612, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.127, 100.000% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.608, 100.000% |
Path13
Path Summary:
| Slack | 0.111 |
| Data Arrival Time | 1.241 |
| Data Required Time | 1.130 |
| From | u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_data_53_s0 |
| To | u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.mem_Big.mem_0_6_s |
| Launch Clk | rgb_clk:[R] |
| Latch Clk | rgb_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | rgb_clk | ||||
| 0.000 | 0.000 | tCL | RR | 431 | PLL_L[1] | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0 |
| 0.920 | 0.920 | tNET | RR | 1 | R40C14[1][B] | u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_data_53_s0/CLK |
| 1.049 | 0.130 | tC2Q | RR | 1 | R40C14[1][B] | u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_data_53_s0/Q |
| 1.241 | 0.192 | tNET | RR | 1 | BSRAM_R38[2][A] | u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.mem_Big.mem_0_6_s/DI[5] |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | rgb_clk | ||||
| 0.000 | 0.000 | tCL | RR | 431 | PLL_L[1] | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0 |
| 1.097 | 1.097 | tNET | RR | 1 | BSRAM_R38[2][A] | u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.mem_Big.mem_0_6_s/CLKA |
| 1.130 | 0.033 | tHld | 1 | BSRAM_R38[2][A] | u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.mem_Big.mem_0_6_s |
Path Statistics:
| Clock Skew | 0.177 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.920, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.192, 59.664%; tC2Q: 0.130, 40.336% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.097, 100.000% |
Path14
Path Summary:
| Slack | 0.111 |
| Data Arrival Time | 1.241 |
| Data Required Time | 1.130 |
| From | u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_data_52_s0 |
| To | u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.mem_Big.mem_0_6_s |
| Launch Clk | rgb_clk:[R] |
| Latch Clk | rgb_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | rgb_clk | ||||
| 0.000 | 0.000 | tCL | RR | 431 | PLL_L[1] | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0 |
| 0.920 | 0.920 | tNET | RR | 1 | R40C14[1][A] | u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_data_52_s0/CLK |
| 1.049 | 0.130 | tC2Q | RR | 1 | R40C14[1][A] | u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_data_52_s0/Q |
| 1.241 | 0.192 | tNET | RR | 1 | BSRAM_R38[2][A] | u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.mem_Big.mem_0_6_s/DI[4] |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | rgb_clk | ||||
| 0.000 | 0.000 | tCL | RR | 431 | PLL_L[1] | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0 |
| 1.097 | 1.097 | tNET | RR | 1 | BSRAM_R38[2][A] | u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.mem_Big.mem_0_6_s/CLKA |
| 1.130 | 0.033 | tHld | 1 | BSRAM_R38[2][A] | u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.mem_Big.mem_0_6_s |
Path Statistics:
| Clock Skew | 0.177 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.920, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.192, 59.664%; tC2Q: 0.130, 40.336% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.097, 100.000% |
Path15
Path Summary:
| Slack | 0.111 |
| Data Arrival Time | 1.248 |
| Data Required Time | 1.138 |
| From | u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_data_20_s0 |
| To | u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.mem_Big.mem_0_2_s |
| Launch Clk | rgb_clk:[R] |
| Latch Clk | rgb_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | rgb_clk | ||||
| 0.000 | 0.000 | tCL | RR | 431 | PLL_L[1] | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0 |
| 0.927 | 0.927 | tNET | RR | 1 | R39C20[1][B] | u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_data_20_s0/CLK |
| 1.057 | 0.130 | tC2Q | RR | 1 | R39C20[1][B] | u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_data_20_s0/Q |
| 1.248 | 0.192 | tNET | RR | 1 | BSRAM_R38[3] | u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.mem_Big.mem_0_2_s/DI[4] |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | rgb_clk | ||||
| 0.000 | 0.000 | tCL | RR | 431 | PLL_L[1] | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0 |
| 1.104 | 1.104 | tNET | RR | 1 | BSRAM_R38[3] | u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.mem_Big.mem_0_2_s/CLKA |
| 1.138 | 0.033 | tHld | 1 | BSRAM_R38[3] | u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.mem_Big.mem_0_2_s |
Path Statistics:
| Clock Skew | 0.177 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.927, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.192, 59.664%; tC2Q: 0.130, 40.336% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.104, 100.000% |
Path16
Path Summary:
| Slack | 0.111 |
| Data Arrival Time | 1.248 |
| Data Required Time | 1.138 |
| From | u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_data_18_s0 |
| To | u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.mem_Big.mem_0_2_s |
| Launch Clk | rgb_clk:[R] |
| Latch Clk | rgb_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | rgb_clk | ||||
| 0.000 | 0.000 | tCL | RR | 431 | PLL_L[1] | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0 |
| 0.927 | 0.927 | tNET | RR | 1 | R39C20[2][A] | u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_data_18_s0/CLK |
| 1.057 | 0.130 | tC2Q | RR | 1 | R39C20[2][A] | u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_data_18_s0/Q |
| 1.248 | 0.192 | tNET | RR | 1 | BSRAM_R38[3] | u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.mem_Big.mem_0_2_s/DI[2] |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | rgb_clk | ||||
| 0.000 | 0.000 | tCL | RR | 431 | PLL_L[1] | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0 |
| 1.104 | 1.104 | tNET | RR | 1 | BSRAM_R38[3] | u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.mem_Big.mem_0_2_s/CLKA |
| 1.138 | 0.033 | tHld | 1 | BSRAM_R38[3] | u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.mem_Big.mem_0_2_s |
Path Statistics:
| Clock Skew | 0.177 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.927, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.192, 59.664%; tC2Q: 0.130, 40.336% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.104, 100.000% |
Path17
Path Summary:
| Slack | 0.111 |
| Data Arrival Time | 1.245 |
| Data Required Time | 1.134 |
| From | u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_data_44_s0 |
| To | u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.mem_Big.mem_0_5_s |
| Launch Clk | rgb_clk:[R] |
| Latch Clk | rgb_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | rgb_clk | ||||
| 0.000 | 0.000 | tCL | RR | 431 | PLL_L[1] | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0 |
| 0.923 | 0.923 | tNET | RR | 1 | R39C17[0][A] | u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_data_44_s0/CLK |
| 1.053 | 0.130 | tC2Q | RR | 1 | R39C17[0][A] | u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_data_44_s0/Q |
| 1.245 | 0.192 | tNET | RR | 1 | BSRAM_R38[2][B] | u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.mem_Big.mem_0_5_s/DI[4] |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | rgb_clk | ||||
| 0.000 | 0.000 | tCL | RR | 431 | PLL_L[1] | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0 |
| 1.101 | 1.101 | tNET | RR | 1 | BSRAM_R38[2][B] | u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.mem_Big.mem_0_5_s/CLKA |
| 1.134 | 0.033 | tHld | 1 | BSRAM_R38[2][B] | u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.mem_Big.mem_0_5_s |
Path Statistics:
| Clock Skew | 0.177 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.923, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.192, 59.664%; tC2Q: 0.130, 40.336% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.101, 100.000% |
Path18
Path Summary:
| Slack | 0.120 |
| Data Arrival Time | 0.729 |
| Data Required Time | 0.609 |
| From | DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/VALUE_rrr_11_s0 |
| To | DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/dq_iobuf_gen[11].dq_iodelay |
| Launch Clk | dma_clk:[R] |
| Latch Clk | dma_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | dma_clk | ||||
| 0.000 | 0.000 | tCL | RR | 3995 | BOTTOMSIDE[0] | DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 0.602 | 0.602 | tNET | RR | 1 | R71C11[0][A] | DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/VALUE_rrr_11_s0/CLK |
| 0.729 | 0.127 | tC2Q | RF | 1 | R71C11[0][A] | DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/VALUE_rrr_11_s0/Q |
| 0.729 | 0.000 | tNET | FF | 1 | IOB1[A] | DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/dq_iobuf_gen[11].dq_iodelay/VALUE |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | dma_clk | ||||
| 0.000 | 0.000 | tCL | RR | 3995 | BOTTOMSIDE[0] | DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 0.609 | 0.609 | tNET | RR | 1 | IOB1[A] | DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[3].u_ides8_dq/PCLK |
| 0.609 | 0.000 | tHld | 1 | IOB1[A] | DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/dq_iobuf_gen[11].dq_iodelay |
Path Statistics:
| Clock Skew | 0.007 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.602, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.127, 100.000% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.609, 100.000% |
Path19
Path Summary:
| Slack | 0.120 |
| Data Arrival Time | 0.729 |
| Data Required Time | 0.609 |
| From | DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/VALUE_rrr_10_s0 |
| To | DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/dq_iobuf_gen[10].dq_iodelay |
| Launch Clk | dma_clk:[R] |
| Latch Clk | dma_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | dma_clk | ||||
| 0.000 | 0.000 | tCL | RR | 3995 | BOTTOMSIDE[0] | DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 0.602 | 0.602 | tNET | RR | 1 | R63C11[0][A] | DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/VALUE_rrr_10_s0/CLK |
| 0.729 | 0.127 | tC2Q | RF | 1 | R63C11[0][A] | DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/VALUE_rrr_10_s0/Q |
| 0.729 | 0.000 | tNET | FF | 1 | IOB16[B] | DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/dq_iobuf_gen[10].dq_iodelay/VALUE |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | dma_clk | ||||
| 0.000 | 0.000 | tCL | RR | 3995 | BOTTOMSIDE[0] | DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 0.609 | 0.609 | tNET | RR | 1 | IOB16[B] | DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[2].u_ides8_dq/PCLK |
| 0.609 | 0.000 | tHld | 1 | IOB16[B] | DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/dq_iobuf_gen[10].dq_iodelay |
Path Statistics:
| Clock Skew | 0.007 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.602, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.127, 100.000% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.609, 100.000% |
Path20
Path Summary:
| Slack | 0.120 |
| Data Arrival Time | 0.729 |
| Data Required Time | 0.609 |
| From | DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/VALUE_rrr_7_s0 |
| To | DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/dq_iobuf_gen[7].dq_iodelay |
| Launch Clk | dma_clk:[R] |
| Latch Clk | dma_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | dma_clk | ||||
| 0.000 | 0.000 | tCL | RR | 3995 | BOTTOMSIDE[0] | DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 0.602 | 0.602 | tNET | RR | 1 | R62C11[1][A] | DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/VALUE_rrr_7_s0/CLK |
| 0.729 | 0.127 | tC2Q | RF | 1 | R62C11[1][A] | DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/VALUE_rrr_7_s0/Q |
| 0.729 | 0.000 | tNET | FF | 1 | IOB29[A] | DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/dq_iobuf_gen[7].dq_iodelay/VALUE |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | dma_clk | ||||
| 0.000 | 0.000 | tCL | RR | 3995 | BOTTOMSIDE[0] | DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 0.609 | 0.609 | tNET | RR | 1 | IOB29[A] | DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[7].u_ides8_dq/PCLK |
| 0.609 | 0.000 | tHld | 1 | IOB29[A] | DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/dq_iobuf_gen[7].dq_iodelay |
Path Statistics:
| Clock Skew | 0.007 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.602, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.127, 100.000% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.609, 100.000% |
Path21
Path Summary:
| Slack | 0.120 |
| Data Arrival Time | 0.729 |
| Data Required Time | 0.609 |
| From | DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/VALUE_rrr_0_s0 |
| To | DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/dq_iobuf_gen[0].dq_iodelay |
| Launch Clk | dma_clk:[R] |
| Latch Clk | dma_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | dma_clk | ||||
| 0.000 | 0.000 | tCL | RR | 3995 | BOTTOMSIDE[0] | DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 0.602 | 0.602 | tNET | RR | 1 | R70C15[2][A] | DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/VALUE_rrr_0_s0/CLK |
| 0.729 | 0.127 | tC2Q | RF | 1 | R70C15[2][A] | DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/VALUE_rrr_0_s0/Q |
| 0.729 | 0.000 | tNET | FF | 1 | IOB24[B] | DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/dq_iobuf_gen[0].dq_iodelay/VALUE |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | dma_clk | ||||
| 0.000 | 0.000 | tCL | RR | 3995 | BOTTOMSIDE[0] | DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 0.609 | 0.609 | tNET | RR | 1 | IOB24[B] | DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[0].u_ides8_dq/PCLK |
| 0.609 | 0.000 | tHld | 1 | IOB24[B] | DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/dq_iobuf_gen[0].dq_iodelay |
Path Statistics:
| Clock Skew | 0.007 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.602, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.127, 100.000% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.609, 100.000% |
Path22
Path Summary:
| Slack | 0.122 |
| Data Arrival Time | 0.939 |
| Data Required Time | 0.817 |
| From | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/gen_in_ep_ping_pong[2].transfer_in_mem_ping_pong_inst/GEN_TRANSFER_IN_MEM[2].transfer_in_mem_inst/transfer_in_pkt_rd_addr_6_s1 |
| To | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/gen_in_ep_ping_pong[2].transfer_in_mem_ping_pong_inst/GEN_TRANSFER_IN_MEM[2].transfer_in_mem_inst/mem0_mem0_0_2_s |
| Launch Clk | pclk:[R] |
| Latch Clk | pclk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | pclk | ||||
| 0.000 | 0.000 | tCL | RR | 10163 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK |
| 0.605 | 0.605 | tNET | RR | 1 | R42C40[0][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/gen_in_ep_ping_pong[2].transfer_in_mem_ping_pong_inst/GEN_TRANSFER_IN_MEM[2].transfer_in_mem_inst/transfer_in_pkt_rd_addr_6_s1/CLK |
| 0.734 | 0.130 | tC2Q | RR | 6 | R42C40[0][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/gen_in_ep_ping_pong[2].transfer_in_mem_ping_pong_inst/GEN_TRANSFER_IN_MEM[2].transfer_in_mem_inst/transfer_in_pkt_rd_addr_6_s1/Q |
| 0.939 | 0.204 | tNET | RR | 1 | BSRAM_R38[7] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/gen_in_ep_ping_pong[2].transfer_in_mem_ping_pong_inst/GEN_TRANSFER_IN_MEM[2].transfer_in_mem_inst/mem0_mem0_0_2_s/ADB[10] |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | pclk | ||||
| 0.000 | 0.000 | tCL | RR | 10163 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK |
| 0.786 | 0.786 | tNET | RR | 1 | BSRAM_R38[7] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/gen_in_ep_ping_pong[2].transfer_in_mem_ping_pong_inst/GEN_TRANSFER_IN_MEM[2].transfer_in_mem_inst/mem0_mem0_0_2_s/CLKB |
| 0.817 | 0.032 | tHld | 1 | BSRAM_R38[7] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/gen_in_ep_ping_pong[2].transfer_in_mem_ping_pong_inst/GEN_TRANSFER_IN_MEM[2].transfer_in_mem_inst/mem0_mem0_0_2_s |
Path Statistics:
| Clock Skew | 0.181 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.605, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.204, 61.186%; tC2Q: 0.130, 38.814% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.786, 100.000% |
Path23
Path Summary:
| Slack | 0.123 |
| Data Arrival Time | 0.729 |
| Data Required Time | 0.606 |
| From | DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/VALUE_rrr_15_s0 |
| To | DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/dq_iobuf_gen[15].dq_iodelay |
| Launch Clk | dma_clk:[R] |
| Latch Clk | dma_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | dma_clk | ||||
| 0.000 | 0.000 | tCL | RR | 3995 | BOTTOMSIDE[0] | DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 0.602 | 0.602 | tNET | RR | 1 | R71C11[0][B] | DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/VALUE_rrr_15_s0/CLK |
| 0.729 | 0.127 | tC2Q | RF | 1 | R71C11[0][B] | DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/VALUE_rrr_15_s0/Q |
| 0.729 | 0.000 | tNET | FF | 1 | IOB1[B] | DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/dq_iobuf_gen[15].dq_iodelay/VALUE |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | dma_clk | ||||
| 0.000 | 0.000 | tCL | RR | 3995 | BOTTOMSIDE[0] | DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 0.606 | 0.606 | tNET | RR | 1 | IOB1[B] | DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[7].u_ides8_dq/PCLK |
| 0.606 | 0.000 | tHld | 1 | IOB1[B] | DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/dq_iobuf_gen[15].dq_iodelay |
Path Statistics:
| Clock Skew | 0.004 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.602, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.127, 100.000% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.606, 100.000% |
Path24
Path Summary:
| Slack | 0.123 |
| Data Arrival Time | 0.729 |
| Data Required Time | 0.606 |
| From | DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/VALUE_rrr_14_s0 |
| To | DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/dq_iobuf_gen[14].dq_iodelay |
| Launch Clk | dma_clk:[R] |
| Latch Clk | dma_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | dma_clk | ||||
| 0.000 | 0.000 | tCL | RR | 3995 | BOTTOMSIDE[0] | DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 0.602 | 0.602 | tNET | RR | 1 | R63C11[0][B] | DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/VALUE_rrr_14_s0/CLK |
| 0.729 | 0.127 | tC2Q | RF | 1 | R63C11[0][B] | DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/VALUE_rrr_14_s0/Q |
| 0.729 | 0.000 | tNET | FF | 1 | IOB16[A] | DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/dq_iobuf_gen[14].dq_iodelay/VALUE |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | dma_clk | ||||
| 0.000 | 0.000 | tCL | RR | 3995 | BOTTOMSIDE[0] | DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 0.606 | 0.606 | tNET | RR | 1 | IOB16[A] | DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[6].u_ides8_dq/PCLK |
| 0.606 | 0.000 | tHld | 1 | IOB16[A] | DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/dq_iobuf_gen[14].dq_iodelay |
Path Statistics:
| Clock Skew | 0.004 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.602, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.127, 100.000% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.606, 100.000% |
Path25
Path Summary:
| Slack | 0.123 |
| Data Arrival Time | 0.729 |
| Data Required Time | 0.606 |
| From | DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/VALUE_rrr_1_s0 |
| To | DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/dq_iobuf_gen[1].dq_iodelay |
| Launch Clk | dma_clk:[R] |
| Latch Clk | dma_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | dma_clk | ||||
| 0.000 | 0.000 | tCL | RR | 3995 | BOTTOMSIDE[0] | DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 0.602 | 0.602 | tNET | RR | 1 | R70C15[0][B] | DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/VALUE_rrr_1_s0/CLK |
| 0.729 | 0.127 | tC2Q | RF | 1 | R70C15[0][B] | DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/VALUE_rrr_1_s0/Q |
| 0.729 | 0.000 | tNET | FF | 1 | IOB20[A] | DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/dq_iobuf_gen[1].dq_iodelay/VALUE |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | dma_clk | ||||
| 0.000 | 0.000 | tCL | RR | 3995 | BOTTOMSIDE[0] | DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 0.606 | 0.606 | tNET | RR | 1 | IOB20[A] | DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[1].u_ides8_dq/PCLK |
| 0.606 | 0.000 | tHld | 1 | IOB20[A] | DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/dq_iobuf_gen[1].dq_iodelay |
Path Statistics:
| Clock Skew | 0.004 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.602, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.127, 100.000% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.606, 100.000% |
Recovery Analysis Report
Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1
Path1
Path Summary:
| Slack | 0.310 |
| Data Arrival Time | 9.081 |
| Data Required Time | 9.391 |
| From | line_fifo_inst/fifo_inst/reset_w_1_s0 |
| To | line_fifo_inst/fifo_inst/Equal.wq2_rptr_3_s0 |
| Launch Clk | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk:[F] |
| Latch Clk | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 3.361 | 3.361 | active clock edge time | ||||
| 3.361 | 0.000 | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk | ||||
| 4.412 | 1.051 | tCL | FF | 158 | PLL_L[1] | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1 |
| 6.284 | 1.872 | tNET | FF | 1 | R32C23[3][A] | line_fifo_inst/fifo_inst/reset_w_1_s0/CLK |
| 6.603 | 0.319 | tC2Q | FF | 49 | R32C23[3][A] | line_fifo_inst/fifo_inst/reset_w_1_s0/Q |
| 9.081 | 2.478 | tNET | FF | 1 | R31C18[1][A] | line_fifo_inst/fifo_inst/Equal.wq2_rptr_3_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.723 | 6.723 | active clock edge time | ||||
| 6.723 | 0.000 | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk | ||||
| 7.773 | 1.051 | tCL | RR | 158 | PLL_L[1] | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1 |
| 9.641 | 1.868 | tNET | RR | 1 | R31C18[1][A] | line_fifo_inst/fifo_inst/Equal.wq2_rptr_3_s0/CLK |
| 9.391 | -0.250 | tSu | 1 | R31C18[1][A] | line_fifo_inst/fifo_inst/Equal.wq2_rptr_3_s0 |
Path Statistics:
| Clock Skew | -0.004 |
| Setup Relationship | 3.361 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.872, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.478, 88.609%; tC2Q: 0.319, 11.391% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.868, 100.000% |
Path2
Path Summary:
| Slack | 0.310 |
| Data Arrival Time | 9.081 |
| Data Required Time | 9.391 |
| From | line_fifo_inst/fifo_inst/reset_w_1_s0 |
| To | line_fifo_inst/fifo_inst/Equal.wq2_rptr_4_s0 |
| Launch Clk | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk:[F] |
| Latch Clk | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 3.361 | 3.361 | active clock edge time | ||||
| 3.361 | 0.000 | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk | ||||
| 4.412 | 1.051 | tCL | FF | 158 | PLL_L[1] | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1 |
| 6.284 | 1.872 | tNET | FF | 1 | R32C23[3][A] | line_fifo_inst/fifo_inst/reset_w_1_s0/CLK |
| 6.603 | 0.319 | tC2Q | FF | 49 | R32C23[3][A] | line_fifo_inst/fifo_inst/reset_w_1_s0/Q |
| 9.081 | 2.478 | tNET | FF | 1 | R32C18[0][B] | line_fifo_inst/fifo_inst/Equal.wq2_rptr_4_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.723 | 6.723 | active clock edge time | ||||
| 6.723 | 0.000 | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk | ||||
| 7.773 | 1.051 | tCL | RR | 158 | PLL_L[1] | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1 |
| 9.641 | 1.868 | tNET | RR | 1 | R32C18[0][B] | line_fifo_inst/fifo_inst/Equal.wq2_rptr_4_s0/CLK |
| 9.391 | -0.250 | tSu | 1 | R32C18[0][B] | line_fifo_inst/fifo_inst/Equal.wq2_rptr_4_s0 |
Path Statistics:
| Clock Skew | -0.004 |
| Setup Relationship | 3.361 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.872, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.478, 88.609%; tC2Q: 0.319, 11.391% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.868, 100.000% |
Path3
Path Summary:
| Slack | 0.310 |
| Data Arrival Time | 9.081 |
| Data Required Time | 9.391 |
| From | line_fifo_inst/fifo_inst/reset_w_1_s0 |
| To | line_fifo_inst/fifo_inst/Equal.wq2_rptr_8_s0 |
| Launch Clk | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk:[F] |
| Latch Clk | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 3.361 | 3.361 | active clock edge time | ||||
| 3.361 | 0.000 | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk | ||||
| 4.412 | 1.051 | tCL | FF | 158 | PLL_L[1] | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1 |
| 6.284 | 1.872 | tNET | FF | 1 | R32C23[3][A] | line_fifo_inst/fifo_inst/reset_w_1_s0/CLK |
| 6.603 | 0.319 | tC2Q | FF | 49 | R32C23[3][A] | line_fifo_inst/fifo_inst/reset_w_1_s0/Q |
| 9.081 | 2.478 | tNET | FF | 1 | R32C18[1][B] | line_fifo_inst/fifo_inst/Equal.wq2_rptr_8_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.723 | 6.723 | active clock edge time | ||||
| 6.723 | 0.000 | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk | ||||
| 7.773 | 1.051 | tCL | RR | 158 | PLL_L[1] | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1 |
| 9.641 | 1.868 | tNET | RR | 1 | R32C18[1][B] | line_fifo_inst/fifo_inst/Equal.wq2_rptr_8_s0/CLK |
| 9.391 | -0.250 | tSu | 1 | R32C18[1][B] | line_fifo_inst/fifo_inst/Equal.wq2_rptr_8_s0 |
Path Statistics:
| Clock Skew | -0.004 |
| Setup Relationship | 3.361 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.872, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.478, 88.609%; tC2Q: 0.319, 11.391% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.868, 100.000% |
Path4
Path Summary:
| Slack | 0.310 |
| Data Arrival Time | 9.081 |
| Data Required Time | 9.391 |
| From | line_fifo_inst/fifo_inst/reset_w_1_s0 |
| To | line_fifo_inst/fifo_inst/Equal.wq2_rptr_11_s0 |
| Launch Clk | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk:[F] |
| Latch Clk | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 3.361 | 3.361 | active clock edge time | ||||
| 3.361 | 0.000 | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk | ||||
| 4.412 | 1.051 | tCL | FF | 158 | PLL_L[1] | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1 |
| 6.284 | 1.872 | tNET | FF | 1 | R32C23[3][A] | line_fifo_inst/fifo_inst/reset_w_1_s0/CLK |
| 6.603 | 0.319 | tC2Q | FF | 49 | R32C23[3][A] | line_fifo_inst/fifo_inst/reset_w_1_s0/Q |
| 9.081 | 2.478 | tNET | FF | 1 | R32C18[2][A] | line_fifo_inst/fifo_inst/Equal.wq2_rptr_11_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.723 | 6.723 | active clock edge time | ||||
| 6.723 | 0.000 | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk | ||||
| 7.773 | 1.051 | tCL | RR | 158 | PLL_L[1] | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1 |
| 9.641 | 1.868 | tNET | RR | 1 | R32C18[2][A] | line_fifo_inst/fifo_inst/Equal.wq2_rptr_11_s0/CLK |
| 9.391 | -0.250 | tSu | 1 | R32C18[2][A] | line_fifo_inst/fifo_inst/Equal.wq2_rptr_11_s0 |
Path Statistics:
| Clock Skew | -0.004 |
| Setup Relationship | 3.361 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.872, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.478, 88.609%; tC2Q: 0.319, 11.391% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.868, 100.000% |
Path5
Path Summary:
| Slack | 0.310 |
| Data Arrival Time | 9.081 |
| Data Required Time | 9.391 |
| From | line_fifo_inst/fifo_inst/reset_w_1_s0 |
| To | line_fifo_inst/fifo_inst/Equal.wq1_rptr_3_s0 |
| Launch Clk | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk:[F] |
| Latch Clk | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 3.361 | 3.361 | active clock edge time | ||||
| 3.361 | 0.000 | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk | ||||
| 4.412 | 1.051 | tCL | FF | 158 | PLL_L[1] | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1 |
| 6.284 | 1.872 | tNET | FF | 1 | R32C23[3][A] | line_fifo_inst/fifo_inst/reset_w_1_s0/CLK |
| 6.603 | 0.319 | tC2Q | FF | 49 | R32C23[3][A] | line_fifo_inst/fifo_inst/reset_w_1_s0/Q |
| 9.081 | 2.478 | tNET | FF | 1 | R31C18[1][B] | line_fifo_inst/fifo_inst/Equal.wq1_rptr_3_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.723 | 6.723 | active clock edge time | ||||
| 6.723 | 0.000 | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk | ||||
| 7.773 | 1.051 | tCL | RR | 158 | PLL_L[1] | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1 |
| 9.641 | 1.868 | tNET | RR | 1 | R31C18[1][B] | line_fifo_inst/fifo_inst/Equal.wq1_rptr_3_s0/CLK |
| 9.391 | -0.250 | tSu | 1 | R31C18[1][B] | line_fifo_inst/fifo_inst/Equal.wq1_rptr_3_s0 |
Path Statistics:
| Clock Skew | -0.004 |
| Setup Relationship | 3.361 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.872, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.478, 88.609%; tC2Q: 0.319, 11.391% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.868, 100.000% |
Path6
Path Summary:
| Slack | 0.310 |
| Data Arrival Time | 9.081 |
| Data Required Time | 9.391 |
| From | line_fifo_inst/fifo_inst/reset_w_1_s0 |
| To | line_fifo_inst/fifo_inst/Equal.wq1_rptr_4_s0 |
| Launch Clk | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk:[F] |
| Latch Clk | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 3.361 | 3.361 | active clock edge time | ||||
| 3.361 | 0.000 | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk | ||||
| 4.412 | 1.051 | tCL | FF | 158 | PLL_L[1] | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1 |
| 6.284 | 1.872 | tNET | FF | 1 | R32C23[3][A] | line_fifo_inst/fifo_inst/reset_w_1_s0/CLK |
| 6.603 | 0.319 | tC2Q | FF | 49 | R32C23[3][A] | line_fifo_inst/fifo_inst/reset_w_1_s0/Q |
| 9.081 | 2.478 | tNET | FF | 1 | R32C18[1][A] | line_fifo_inst/fifo_inst/Equal.wq1_rptr_4_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.723 | 6.723 | active clock edge time | ||||
| 6.723 | 0.000 | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk | ||||
| 7.773 | 1.051 | tCL | RR | 158 | PLL_L[1] | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1 |
| 9.641 | 1.868 | tNET | RR | 1 | R32C18[1][A] | line_fifo_inst/fifo_inst/Equal.wq1_rptr_4_s0/CLK |
| 9.391 | -0.250 | tSu | 1 | R32C18[1][A] | line_fifo_inst/fifo_inst/Equal.wq1_rptr_4_s0 |
Path Statistics:
| Clock Skew | -0.004 |
| Setup Relationship | 3.361 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.872, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.478, 88.609%; tC2Q: 0.319, 11.391% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.868, 100.000% |
Path7
Path Summary:
| Slack | 0.310 |
| Data Arrival Time | 9.081 |
| Data Required Time | 9.391 |
| From | line_fifo_inst/fifo_inst/reset_w_1_s0 |
| To | line_fifo_inst/fifo_inst/Equal.wq1_rptr_8_s0 |
| Launch Clk | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk:[F] |
| Latch Clk | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 3.361 | 3.361 | active clock edge time | ||||
| 3.361 | 0.000 | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk | ||||
| 4.412 | 1.051 | tCL | FF | 158 | PLL_L[1] | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1 |
| 6.284 | 1.872 | tNET | FF | 1 | R32C23[3][A] | line_fifo_inst/fifo_inst/reset_w_1_s0/CLK |
| 6.603 | 0.319 | tC2Q | FF | 49 | R32C23[3][A] | line_fifo_inst/fifo_inst/reset_w_1_s0/Q |
| 9.081 | 2.478 | tNET | FF | 1 | R32C18[0][A] | line_fifo_inst/fifo_inst/Equal.wq1_rptr_8_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.723 | 6.723 | active clock edge time | ||||
| 6.723 | 0.000 | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk | ||||
| 7.773 | 1.051 | tCL | RR | 158 | PLL_L[1] | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1 |
| 9.641 | 1.868 | tNET | RR | 1 | R32C18[0][A] | line_fifo_inst/fifo_inst/Equal.wq1_rptr_8_s0/CLK |
| 9.391 | -0.250 | tSu | 1 | R32C18[0][A] | line_fifo_inst/fifo_inst/Equal.wq1_rptr_8_s0 |
Path Statistics:
| Clock Skew | -0.004 |
| Setup Relationship | 3.361 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.872, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.478, 88.609%; tC2Q: 0.319, 11.391% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.868, 100.000% |
Path8
Path Summary:
| Slack | 0.310 |
| Data Arrival Time | 9.081 |
| Data Required Time | 9.391 |
| From | line_fifo_inst/fifo_inst/reset_w_1_s0 |
| To | line_fifo_inst/fifo_inst/Equal.wq1_rptr_11_s0 |
| Launch Clk | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk:[F] |
| Latch Clk | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 3.361 | 3.361 | active clock edge time | ||||
| 3.361 | 0.000 | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk | ||||
| 4.412 | 1.051 | tCL | FF | 158 | PLL_L[1] | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1 |
| 6.284 | 1.872 | tNET | FF | 1 | R32C23[3][A] | line_fifo_inst/fifo_inst/reset_w_1_s0/CLK |
| 6.603 | 0.319 | tC2Q | FF | 49 | R32C23[3][A] | line_fifo_inst/fifo_inst/reset_w_1_s0/Q |
| 9.081 | 2.478 | tNET | FF | 1 | R31C18[0][A] | line_fifo_inst/fifo_inst/Equal.wq1_rptr_11_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.723 | 6.723 | active clock edge time | ||||
| 6.723 | 0.000 | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk | ||||
| 7.773 | 1.051 | tCL | RR | 158 | PLL_L[1] | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1 |
| 9.641 | 1.868 | tNET | RR | 1 | R31C18[0][A] | line_fifo_inst/fifo_inst/Equal.wq1_rptr_11_s0/CLK |
| 9.391 | -0.250 | tSu | 1 | R31C18[0][A] | line_fifo_inst/fifo_inst/Equal.wq1_rptr_11_s0 |
Path Statistics:
| Clock Skew | -0.004 |
| Setup Relationship | 3.361 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.872, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.478, 88.609%; tC2Q: 0.319, 11.391% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.868, 100.000% |
Path9
Path Summary:
| Slack | 0.318 |
| Data Arrival Time | 7.545 |
| Data Required Time | 7.863 |
| From | line_fifo_inst/fifo_inst/reset_r_1_s0 |
| To | line_fifo_inst/fifo_inst/Rnum_6_s0 |
| Launch Clk | pclk:[F] |
| Latch Clk | pclk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 3.200 | 3.200 | active clock edge time | ||||
| 3.200 | 0.000 | pclk | ||||
| 3.200 | 0.000 | tCL | FF | 10163 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK |
| 4.706 | 1.506 | tNET | FF | 1 | R39C48[0][A] | line_fifo_inst/fifo_inst/reset_r_1_s0/CLK |
| 5.024 | 0.319 | tC2Q | FF | 68 | R39C48[0][A] | line_fifo_inst/fifo_inst/reset_r_1_s0/Q |
| 7.545 | 2.521 | tNET | FF | 1 | R30C28[0][A] | line_fifo_inst/fifo_inst/Rnum_6_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.250 | 6.250 | active clock edge time | ||||
| 6.250 | 0.000 | pclk | ||||
| 6.250 | 0.000 | tCL | RR | 10163 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK |
| 8.113 | 1.863 | tNET | RR | 1 | R30C28[0][A] | line_fifo_inst/fifo_inst/Rnum_6_s0/CLK |
| 7.863 | -0.250 | tSu | 1 | R30C28[0][A] | line_fifo_inst/fifo_inst/Rnum_6_s0 |
Path Statistics:
| Clock Skew | 0.357 |
| Setup Relationship | 3.050 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.506, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.521, 88.780%; tC2Q: 0.319, 11.220% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.863, 100.000% |
Path10
Path Summary:
| Slack | 0.318 |
| Data Arrival Time | 7.545 |
| Data Required Time | 7.863 |
| From | line_fifo_inst/fifo_inst/reset_r_1_s0 |
| To | line_fifo_inst/fifo_inst/Rnum_7_s0 |
| Launch Clk | pclk:[F] |
| Latch Clk | pclk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 3.200 | 3.200 | active clock edge time | ||||
| 3.200 | 0.000 | pclk | ||||
| 3.200 | 0.000 | tCL | FF | 10163 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK |
| 4.706 | 1.506 | tNET | FF | 1 | R39C48[0][A] | line_fifo_inst/fifo_inst/reset_r_1_s0/CLK |
| 5.024 | 0.319 | tC2Q | FF | 68 | R39C48[0][A] | line_fifo_inst/fifo_inst/reset_r_1_s0/Q |
| 7.545 | 2.521 | tNET | FF | 1 | R30C28[0][B] | line_fifo_inst/fifo_inst/Rnum_7_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.250 | 6.250 | active clock edge time | ||||
| 6.250 | 0.000 | pclk | ||||
| 6.250 | 0.000 | tCL | RR | 10163 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK |
| 8.113 | 1.863 | tNET | RR | 1 | R30C28[0][B] | line_fifo_inst/fifo_inst/Rnum_7_s0/CLK |
| 7.863 | -0.250 | tSu | 1 | R30C28[0][B] | line_fifo_inst/fifo_inst/Rnum_7_s0 |
Path Statistics:
| Clock Skew | 0.357 |
| Setup Relationship | 3.050 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.506, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.521, 88.780%; tC2Q: 0.319, 11.220% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.863, 100.000% |
Path11
Path Summary:
| Slack | 0.318 |
| Data Arrival Time | 7.545 |
| Data Required Time | 7.863 |
| From | line_fifo_inst/fifo_inst/reset_r_1_s0 |
| To | line_fifo_inst/fifo_inst/Rnum_8_s0 |
| Launch Clk | pclk:[F] |
| Latch Clk | pclk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 3.200 | 3.200 | active clock edge time | ||||
| 3.200 | 0.000 | pclk | ||||
| 3.200 | 0.000 | tCL | FF | 10163 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK |
| 4.706 | 1.506 | tNET | FF | 1 | R39C48[0][A] | line_fifo_inst/fifo_inst/reset_r_1_s0/CLK |
| 5.024 | 0.319 | tC2Q | FF | 68 | R39C48[0][A] | line_fifo_inst/fifo_inst/reset_r_1_s0/Q |
| 7.545 | 2.521 | tNET | FF | 1 | R30C28[1][A] | line_fifo_inst/fifo_inst/Rnum_8_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.250 | 6.250 | active clock edge time | ||||
| 6.250 | 0.000 | pclk | ||||
| 6.250 | 0.000 | tCL | RR | 10163 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK |
| 8.113 | 1.863 | tNET | RR | 1 | R30C28[1][A] | line_fifo_inst/fifo_inst/Rnum_8_s0/CLK |
| 7.863 | -0.250 | tSu | 1 | R30C28[1][A] | line_fifo_inst/fifo_inst/Rnum_8_s0 |
Path Statistics:
| Clock Skew | 0.357 |
| Setup Relationship | 3.050 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.506, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.521, 88.780%; tC2Q: 0.319, 11.220% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.863, 100.000% |
Path12
Path Summary:
| Slack | 0.318 |
| Data Arrival Time | 7.545 |
| Data Required Time | 7.863 |
| From | line_fifo_inst/fifo_inst/reset_r_1_s0 |
| To | line_fifo_inst/fifo_inst/Rnum_9_s0 |
| Launch Clk | pclk:[F] |
| Latch Clk | pclk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 3.200 | 3.200 | active clock edge time | ||||
| 3.200 | 0.000 | pclk | ||||
| 3.200 | 0.000 | tCL | FF | 10163 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK |
| 4.706 | 1.506 | tNET | FF | 1 | R39C48[0][A] | line_fifo_inst/fifo_inst/reset_r_1_s0/CLK |
| 5.024 | 0.319 | tC2Q | FF | 68 | R39C48[0][A] | line_fifo_inst/fifo_inst/reset_r_1_s0/Q |
| 7.545 | 2.521 | tNET | FF | 1 | R30C28[1][B] | line_fifo_inst/fifo_inst/Rnum_9_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.250 | 6.250 | active clock edge time | ||||
| 6.250 | 0.000 | pclk | ||||
| 6.250 | 0.000 | tCL | RR | 10163 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK |
| 8.113 | 1.863 | tNET | RR | 1 | R30C28[1][B] | line_fifo_inst/fifo_inst/Rnum_9_s0/CLK |
| 7.863 | -0.250 | tSu | 1 | R30C28[1][B] | line_fifo_inst/fifo_inst/Rnum_9_s0 |
Path Statistics:
| Clock Skew | 0.357 |
| Setup Relationship | 3.050 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.506, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.521, 88.780%; tC2Q: 0.319, 11.220% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.863, 100.000% |
Path13
Path Summary:
| Slack | 0.318 |
| Data Arrival Time | 7.545 |
| Data Required Time | 7.863 |
| From | line_fifo_inst/fifo_inst/reset_r_1_s0 |
| To | line_fifo_inst/fifo_inst/Rnum_10_s0 |
| Launch Clk | pclk:[F] |
| Latch Clk | pclk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 3.200 | 3.200 | active clock edge time | ||||
| 3.200 | 0.000 | pclk | ||||
| 3.200 | 0.000 | tCL | FF | 10163 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK |
| 4.706 | 1.506 | tNET | FF | 1 | R39C48[0][A] | line_fifo_inst/fifo_inst/reset_r_1_s0/CLK |
| 5.024 | 0.319 | tC2Q | FF | 68 | R39C48[0][A] | line_fifo_inst/fifo_inst/reset_r_1_s0/Q |
| 7.545 | 2.521 | tNET | FF | 1 | R30C28[2][A] | line_fifo_inst/fifo_inst/Rnum_10_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.250 | 6.250 | active clock edge time | ||||
| 6.250 | 0.000 | pclk | ||||
| 6.250 | 0.000 | tCL | RR | 10163 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK |
| 8.113 | 1.863 | tNET | RR | 1 | R30C28[2][A] | line_fifo_inst/fifo_inst/Rnum_10_s0/CLK |
| 7.863 | -0.250 | tSu | 1 | R30C28[2][A] | line_fifo_inst/fifo_inst/Rnum_10_s0 |
Path Statistics:
| Clock Skew | 0.357 |
| Setup Relationship | 3.050 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.506, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.521, 88.780%; tC2Q: 0.319, 11.220% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.863, 100.000% |
Path14
Path Summary:
| Slack | 0.318 |
| Data Arrival Time | 7.545 |
| Data Required Time | 7.863 |
| From | line_fifo_inst/fifo_inst/reset_r_1_s0 |
| To | line_fifo_inst/fifo_inst/Rnum_11_s0 |
| Launch Clk | pclk:[F] |
| Latch Clk | pclk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 3.200 | 3.200 | active clock edge time | ||||
| 3.200 | 0.000 | pclk | ||||
| 3.200 | 0.000 | tCL | FF | 10163 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK |
| 4.706 | 1.506 | tNET | FF | 1 | R39C48[0][A] | line_fifo_inst/fifo_inst/reset_r_1_s0/CLK |
| 5.024 | 0.319 | tC2Q | FF | 68 | R39C48[0][A] | line_fifo_inst/fifo_inst/reset_r_1_s0/Q |
| 7.545 | 2.521 | tNET | FF | 1 | R30C28[2][B] | line_fifo_inst/fifo_inst/Rnum_11_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.250 | 6.250 | active clock edge time | ||||
| 6.250 | 0.000 | pclk | ||||
| 6.250 | 0.000 | tCL | RR | 10163 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK |
| 8.113 | 1.863 | tNET | RR | 1 | R30C28[2][B] | line_fifo_inst/fifo_inst/Rnum_11_s0/CLK |
| 7.863 | -0.250 | tSu | 1 | R30C28[2][B] | line_fifo_inst/fifo_inst/Rnum_11_s0 |
Path Statistics:
| Clock Skew | 0.357 |
| Setup Relationship | 3.050 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.506, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.521, 88.780%; tC2Q: 0.319, 11.220% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.863, 100.000% |
Path15
Path Summary:
| Slack | 0.324 |
| Data Arrival Time | 7.545 |
| Data Required Time | 7.870 |
| From | line_fifo_inst/fifo_inst/reset_r_1_s0 |
| To | line_fifo_inst/fifo_inst/Rnum_0_s0 |
| Launch Clk | pclk:[F] |
| Latch Clk | pclk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 3.200 | 3.200 | active clock edge time | ||||
| 3.200 | 0.000 | pclk | ||||
| 3.200 | 0.000 | tCL | FF | 10163 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK |
| 4.706 | 1.506 | tNET | FF | 1 | R39C48[0][A] | line_fifo_inst/fifo_inst/reset_r_1_s0/CLK |
| 5.024 | 0.319 | tC2Q | FF | 68 | R39C48[0][A] | line_fifo_inst/fifo_inst/reset_r_1_s0/Q |
| 7.545 | 2.521 | tNET | FF | 1 | R30C27[0][A] | line_fifo_inst/fifo_inst/Rnum_0_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.250 | 6.250 | active clock edge time | ||||
| 6.250 | 0.000 | pclk | ||||
| 6.250 | 0.000 | tCL | RR | 10163 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK |
| 8.120 | 1.870 | tNET | RR | 1 | R30C27[0][A] | line_fifo_inst/fifo_inst/Rnum_0_s0/CLK |
| 7.870 | -0.250 | tSu | 1 | R30C27[0][A] | line_fifo_inst/fifo_inst/Rnum_0_s0 |
Path Statistics:
| Clock Skew | 0.364 |
| Setup Relationship | 3.050 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.506, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.521, 88.780%; tC2Q: 0.319, 11.220% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.870, 100.000% |
Path16
Path Summary:
| Slack | 0.324 |
| Data Arrival Time | 7.545 |
| Data Required Time | 7.870 |
| From | line_fifo_inst/fifo_inst/reset_r_1_s0 |
| To | line_fifo_inst/fifo_inst/Rnum_1_s0 |
| Launch Clk | pclk:[F] |
| Latch Clk | pclk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 3.200 | 3.200 | active clock edge time | ||||
| 3.200 | 0.000 | pclk | ||||
| 3.200 | 0.000 | tCL | FF | 10163 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK |
| 4.706 | 1.506 | tNET | FF | 1 | R39C48[0][A] | line_fifo_inst/fifo_inst/reset_r_1_s0/CLK |
| 5.024 | 0.319 | tC2Q | FF | 68 | R39C48[0][A] | line_fifo_inst/fifo_inst/reset_r_1_s0/Q |
| 7.545 | 2.521 | tNET | FF | 1 | R30C27[0][B] | line_fifo_inst/fifo_inst/Rnum_1_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.250 | 6.250 | active clock edge time | ||||
| 6.250 | 0.000 | pclk | ||||
| 6.250 | 0.000 | tCL | RR | 10163 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK |
| 8.120 | 1.870 | tNET | RR | 1 | R30C27[0][B] | line_fifo_inst/fifo_inst/Rnum_1_s0/CLK |
| 7.870 | -0.250 | tSu | 1 | R30C27[0][B] | line_fifo_inst/fifo_inst/Rnum_1_s0 |
Path Statistics:
| Clock Skew | 0.364 |
| Setup Relationship | 3.050 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.506, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.521, 88.780%; tC2Q: 0.319, 11.220% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.870, 100.000% |
Path17
Path Summary:
| Slack | 0.324 |
| Data Arrival Time | 7.545 |
| Data Required Time | 7.870 |
| From | line_fifo_inst/fifo_inst/reset_r_1_s0 |
| To | line_fifo_inst/fifo_inst/Rnum_2_s0 |
| Launch Clk | pclk:[F] |
| Latch Clk | pclk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 3.200 | 3.200 | active clock edge time | ||||
| 3.200 | 0.000 | pclk | ||||
| 3.200 | 0.000 | tCL | FF | 10163 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK |
| 4.706 | 1.506 | tNET | FF | 1 | R39C48[0][A] | line_fifo_inst/fifo_inst/reset_r_1_s0/CLK |
| 5.024 | 0.319 | tC2Q | FF | 68 | R39C48[0][A] | line_fifo_inst/fifo_inst/reset_r_1_s0/Q |
| 7.545 | 2.521 | tNET | FF | 1 | R30C27[1][A] | line_fifo_inst/fifo_inst/Rnum_2_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.250 | 6.250 | active clock edge time | ||||
| 6.250 | 0.000 | pclk | ||||
| 6.250 | 0.000 | tCL | RR | 10163 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK |
| 8.120 | 1.870 | tNET | RR | 1 | R30C27[1][A] | line_fifo_inst/fifo_inst/Rnum_2_s0/CLK |
| 7.870 | -0.250 | tSu | 1 | R30C27[1][A] | line_fifo_inst/fifo_inst/Rnum_2_s0 |
Path Statistics:
| Clock Skew | 0.364 |
| Setup Relationship | 3.050 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.506, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.521, 88.780%; tC2Q: 0.319, 11.220% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.870, 100.000% |
Path18
Path Summary:
| Slack | 0.324 |
| Data Arrival Time | 7.545 |
| Data Required Time | 7.870 |
| From | line_fifo_inst/fifo_inst/reset_r_1_s0 |
| To | line_fifo_inst/fifo_inst/Rnum_3_s0 |
| Launch Clk | pclk:[F] |
| Latch Clk | pclk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 3.200 | 3.200 | active clock edge time | ||||
| 3.200 | 0.000 | pclk | ||||
| 3.200 | 0.000 | tCL | FF | 10163 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK |
| 4.706 | 1.506 | tNET | FF | 1 | R39C48[0][A] | line_fifo_inst/fifo_inst/reset_r_1_s0/CLK |
| 5.024 | 0.319 | tC2Q | FF | 68 | R39C48[0][A] | line_fifo_inst/fifo_inst/reset_r_1_s0/Q |
| 7.545 | 2.521 | tNET | FF | 1 | R30C27[1][B] | line_fifo_inst/fifo_inst/Rnum_3_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.250 | 6.250 | active clock edge time | ||||
| 6.250 | 0.000 | pclk | ||||
| 6.250 | 0.000 | tCL | RR | 10163 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK |
| 8.120 | 1.870 | tNET | RR | 1 | R30C27[1][B] | line_fifo_inst/fifo_inst/Rnum_3_s0/CLK |
| 7.870 | -0.250 | tSu | 1 | R30C27[1][B] | line_fifo_inst/fifo_inst/Rnum_3_s0 |
Path Statistics:
| Clock Skew | 0.364 |
| Setup Relationship | 3.050 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.506, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.521, 88.780%; tC2Q: 0.319, 11.220% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.870, 100.000% |
Path19
Path Summary:
| Slack | 0.324 |
| Data Arrival Time | 7.545 |
| Data Required Time | 7.870 |
| From | line_fifo_inst/fifo_inst/reset_r_1_s0 |
| To | line_fifo_inst/fifo_inst/Rnum_4_s0 |
| Launch Clk | pclk:[F] |
| Latch Clk | pclk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 3.200 | 3.200 | active clock edge time | ||||
| 3.200 | 0.000 | pclk | ||||
| 3.200 | 0.000 | tCL | FF | 10163 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK |
| 4.706 | 1.506 | tNET | FF | 1 | R39C48[0][A] | line_fifo_inst/fifo_inst/reset_r_1_s0/CLK |
| 5.024 | 0.319 | tC2Q | FF | 68 | R39C48[0][A] | line_fifo_inst/fifo_inst/reset_r_1_s0/Q |
| 7.545 | 2.521 | tNET | FF | 1 | R30C27[2][A] | line_fifo_inst/fifo_inst/Rnum_4_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.250 | 6.250 | active clock edge time | ||||
| 6.250 | 0.000 | pclk | ||||
| 6.250 | 0.000 | tCL | RR | 10163 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK |
| 8.120 | 1.870 | tNET | RR | 1 | R30C27[2][A] | line_fifo_inst/fifo_inst/Rnum_4_s0/CLK |
| 7.870 | -0.250 | tSu | 1 | R30C27[2][A] | line_fifo_inst/fifo_inst/Rnum_4_s0 |
Path Statistics:
| Clock Skew | 0.364 |
| Setup Relationship | 3.050 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.506, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.521, 88.780%; tC2Q: 0.319, 11.220% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.870, 100.000% |
Path20
Path Summary:
| Slack | 0.324 |
| Data Arrival Time | 7.545 |
| Data Required Time | 7.870 |
| From | line_fifo_inst/fifo_inst/reset_r_1_s0 |
| To | line_fifo_inst/fifo_inst/Rnum_5_s0 |
| Launch Clk | pclk:[F] |
| Latch Clk | pclk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 3.200 | 3.200 | active clock edge time | ||||
| 3.200 | 0.000 | pclk | ||||
| 3.200 | 0.000 | tCL | FF | 10163 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK |
| 4.706 | 1.506 | tNET | FF | 1 | R39C48[0][A] | line_fifo_inst/fifo_inst/reset_r_1_s0/CLK |
| 5.024 | 0.319 | tC2Q | FF | 68 | R39C48[0][A] | line_fifo_inst/fifo_inst/reset_r_1_s0/Q |
| 7.545 | 2.521 | tNET | FF | 1 | R30C27[2][B] | line_fifo_inst/fifo_inst/Rnum_5_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.250 | 6.250 | active clock edge time | ||||
| 6.250 | 0.000 | pclk | ||||
| 6.250 | 0.000 | tCL | RR | 10163 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK |
| 8.120 | 1.870 | tNET | RR | 1 | R30C27[2][B] | line_fifo_inst/fifo_inst/Rnum_5_s0/CLK |
| 7.870 | -0.250 | tSu | 1 | R30C27[2][B] | line_fifo_inst/fifo_inst/Rnum_5_s0 |
Path Statistics:
| Clock Skew | 0.364 |
| Setup Relationship | 3.050 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.506, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.521, 88.780%; tC2Q: 0.319, 11.220% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.870, 100.000% |
Path21
Path Summary:
| Slack | 0.328 |
| Data Arrival Time | 9.070 |
| Data Required Time | 9.398 |
| From | line_fifo_inst/fifo_inst/reset_w_1_s0 |
| To | line_fifo_inst/fifo_inst/Equal.wq2_rptr_0_s0 |
| Launch Clk | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk:[F] |
| Latch Clk | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 3.361 | 3.361 | active clock edge time | ||||
| 3.361 | 0.000 | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk | ||||
| 4.412 | 1.051 | tCL | FF | 158 | PLL_L[1] | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1 |
| 6.284 | 1.872 | tNET | FF | 1 | R32C23[3][A] | line_fifo_inst/fifo_inst/reset_w_1_s0/CLK |
| 6.603 | 0.319 | tC2Q | FF | 49 | R32C23[3][A] | line_fifo_inst/fifo_inst/reset_w_1_s0/Q |
| 9.070 | 2.468 | tNET | FF | 1 | R32C19[1][B] | line_fifo_inst/fifo_inst/Equal.wq2_rptr_0_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.723 | 6.723 | active clock edge time | ||||
| 6.723 | 0.000 | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk | ||||
| 7.773 | 1.051 | tCL | RR | 158 | PLL_L[1] | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1 |
| 9.648 | 1.875 | tNET | RR | 1 | R32C19[1][B] | line_fifo_inst/fifo_inst/Equal.wq2_rptr_0_s0/CLK |
| 9.398 | -0.250 | tSu | 1 | R32C19[1][B] | line_fifo_inst/fifo_inst/Equal.wq2_rptr_0_s0 |
Path Statistics:
| Clock Skew | 0.003 |
| Setup Relationship | 3.361 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.872, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.468, 88.565%; tC2Q: 0.319, 11.435% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.875, 100.000% |
Path22
Path Summary:
| Slack | 0.328 |
| Data Arrival Time | 9.070 |
| Data Required Time | 9.398 |
| From | line_fifo_inst/fifo_inst/reset_w_1_s0 |
| To | line_fifo_inst/fifo_inst/Equal.wq2_rptr_2_s0 |
| Launch Clk | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk:[F] |
| Latch Clk | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 3.361 | 3.361 | active clock edge time | ||||
| 3.361 | 0.000 | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk | ||||
| 4.412 | 1.051 | tCL | FF | 158 | PLL_L[1] | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1 |
| 6.284 | 1.872 | tNET | FF | 1 | R32C23[3][A] | line_fifo_inst/fifo_inst/reset_w_1_s0/CLK |
| 6.603 | 0.319 | tC2Q | FF | 49 | R32C23[3][A] | line_fifo_inst/fifo_inst/reset_w_1_s0/Q |
| 9.070 | 2.468 | tNET | FF | 1 | R31C19[2][A] | line_fifo_inst/fifo_inst/Equal.wq2_rptr_2_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.723 | 6.723 | active clock edge time | ||||
| 6.723 | 0.000 | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk | ||||
| 7.773 | 1.051 | tCL | RR | 158 | PLL_L[1] | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1 |
| 9.648 | 1.875 | tNET | RR | 1 | R31C19[2][A] | line_fifo_inst/fifo_inst/Equal.wq2_rptr_2_s0/CLK |
| 9.398 | -0.250 | tSu | 1 | R31C19[2][A] | line_fifo_inst/fifo_inst/Equal.wq2_rptr_2_s0 |
Path Statistics:
| Clock Skew | 0.003 |
| Setup Relationship | 3.361 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.872, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.468, 88.565%; tC2Q: 0.319, 11.435% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.875, 100.000% |
Path23
Path Summary:
| Slack | 0.328 |
| Data Arrival Time | 9.070 |
| Data Required Time | 9.398 |
| From | line_fifo_inst/fifo_inst/reset_w_1_s0 |
| To | line_fifo_inst/fifo_inst/Equal.wq2_rptr_6_s0 |
| Launch Clk | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk:[F] |
| Latch Clk | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 3.361 | 3.361 | active clock edge time | ||||
| 3.361 | 0.000 | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk | ||||
| 4.412 | 1.051 | tCL | FF | 158 | PLL_L[1] | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1 |
| 6.284 | 1.872 | tNET | FF | 1 | R32C23[3][A] | line_fifo_inst/fifo_inst/reset_w_1_s0/CLK |
| 6.603 | 0.319 | tC2Q | FF | 49 | R32C23[3][A] | line_fifo_inst/fifo_inst/reset_w_1_s0/Q |
| 9.070 | 2.468 | tNET | FF | 1 | R32C19[3][A] | line_fifo_inst/fifo_inst/Equal.wq2_rptr_6_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.723 | 6.723 | active clock edge time | ||||
| 6.723 | 0.000 | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk | ||||
| 7.773 | 1.051 | tCL | RR | 158 | PLL_L[1] | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1 |
| 9.648 | 1.875 | tNET | RR | 1 | R32C19[3][A] | line_fifo_inst/fifo_inst/Equal.wq2_rptr_6_s0/CLK |
| 9.398 | -0.250 | tSu | 1 | R32C19[3][A] | line_fifo_inst/fifo_inst/Equal.wq2_rptr_6_s0 |
Path Statistics:
| Clock Skew | 0.003 |
| Setup Relationship | 3.361 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.872, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.468, 88.565%; tC2Q: 0.319, 11.435% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.875, 100.000% |
Path24
Path Summary:
| Slack | 0.328 |
| Data Arrival Time | 9.070 |
| Data Required Time | 9.398 |
| From | line_fifo_inst/fifo_inst/reset_w_1_s0 |
| To | line_fifo_inst/fifo_inst/Equal.wq2_rptr_9_s0 |
| Launch Clk | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk:[F] |
| Latch Clk | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 3.361 | 3.361 | active clock edge time | ||||
| 3.361 | 0.000 | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk | ||||
| 4.412 | 1.051 | tCL | FF | 158 | PLL_L[1] | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1 |
| 6.284 | 1.872 | tNET | FF | 1 | R32C23[3][A] | line_fifo_inst/fifo_inst/reset_w_1_s0/CLK |
| 6.603 | 0.319 | tC2Q | FF | 49 | R32C23[3][A] | line_fifo_inst/fifo_inst/reset_w_1_s0/Q |
| 9.070 | 2.468 | tNET | FF | 1 | R32C19[0][B] | line_fifo_inst/fifo_inst/Equal.wq2_rptr_9_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.723 | 6.723 | active clock edge time | ||||
| 6.723 | 0.000 | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk | ||||
| 7.773 | 1.051 | tCL | RR | 158 | PLL_L[1] | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1 |
| 9.648 | 1.875 | tNET | RR | 1 | R32C19[0][B] | line_fifo_inst/fifo_inst/Equal.wq2_rptr_9_s0/CLK |
| 9.398 | -0.250 | tSu | 1 | R32C19[0][B] | line_fifo_inst/fifo_inst/Equal.wq2_rptr_9_s0 |
Path Statistics:
| Clock Skew | 0.003 |
| Setup Relationship | 3.361 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.872, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.468, 88.565%; tC2Q: 0.319, 11.435% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.875, 100.000% |
Path25
Path Summary:
| Slack | 0.328 |
| Data Arrival Time | 9.070 |
| Data Required Time | 9.398 |
| From | line_fifo_inst/fifo_inst/reset_w_1_s0 |
| To | line_fifo_inst/fifo_inst/Equal.wq1_rptr_6_s0 |
| Launch Clk | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk:[F] |
| Latch Clk | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 3.361 | 3.361 | active clock edge time | ||||
| 3.361 | 0.000 | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk | ||||
| 4.412 | 1.051 | tCL | FF | 158 | PLL_L[1] | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1 |
| 6.284 | 1.872 | tNET | FF | 1 | R32C23[3][A] | line_fifo_inst/fifo_inst/reset_w_1_s0/CLK |
| 6.603 | 0.319 | tC2Q | FF | 49 | R32C23[3][A] | line_fifo_inst/fifo_inst/reset_w_1_s0/Q |
| 9.070 | 2.468 | tNET | FF | 1 | R31C19[2][B] | line_fifo_inst/fifo_inst/Equal.wq1_rptr_6_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.723 | 6.723 | active clock edge time | ||||
| 6.723 | 0.000 | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk | ||||
| 7.773 | 1.051 | tCL | RR | 158 | PLL_L[1] | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1 |
| 9.648 | 1.875 | tNET | RR | 1 | R31C19[2][B] | line_fifo_inst/fifo_inst/Equal.wq1_rptr_6_s0/CLK |
| 9.398 | -0.250 | tSu | 1 | R31C19[2][B] | line_fifo_inst/fifo_inst/Equal.wq1_rptr_6_s0 |
Path Statistics:
| Clock Skew | 0.003 |
| Setup Relationship | 3.361 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.872, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.468, 88.565%; tC2Q: 0.319, 11.435% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.875, 100.000% |
Removal Analysis Report
Report Command:report_timing -removal -max_paths 25 -max_common_paths 1
Path1
Path Summary:
| Slack | 0.261 |
| Data Arrival Time | 1.187 |
| Data Required Time | 0.926 |
| From | frame_read_inst/rst_n_d_1_s0 |
| To | frame_read_inst/v_cnt_9_s1 |
| Launch Clk | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk:[R] |
| Latch Clk | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk | ||||
| 0.368 | 0.368 | tCL | RR | 158 | PLL_L[1] | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1 |
| 0.974 | 0.606 | tNET | RR | 1 | R41C20[2][A] | frame_read_inst/rst_n_d_1_s0/CLK |
| 1.103 | 0.130 | tC2Q | RR | 25 | R41C20[2][A] | frame_read_inst/rst_n_d_1_s0/Q |
| 1.187 | 0.084 | tNET | RR | 1 | R41C20[1][B] | frame_read_inst/v_cnt_9_s1/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk | ||||
| 0.368 | 0.368 | tCL | RR | 158 | PLL_L[1] | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1 |
| 0.974 | 0.606 | tNET | RR | 1 | R41C20[1][B] | frame_read_inst/v_cnt_9_s1/CLK |
| 0.926 | -0.048 | tHld | 1 | R41C20[1][B] | frame_read_inst/v_cnt_9_s1 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.606, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.084, 39.241%; tC2Q: 0.130, 60.759% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.606, 100.000% |
Path2
Path Summary:
| Slack | 0.261 |
| Data Arrival Time | 1.187 |
| Data Required Time | 0.926 |
| From | frame_read_inst/rst_n_d_1_s0 |
| To | frame_read_inst/v_cnt_10_s0 |
| Launch Clk | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk:[R] |
| Latch Clk | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk | ||||
| 0.368 | 0.368 | tCL | RR | 158 | PLL_L[1] | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1 |
| 0.974 | 0.606 | tNET | RR | 1 | R41C20[2][A] | frame_read_inst/rst_n_d_1_s0/CLK |
| 1.103 | 0.130 | tC2Q | RR | 25 | R41C20[2][A] | frame_read_inst/rst_n_d_1_s0/Q |
| 1.187 | 0.084 | tNET | RR | 1 | R41C20[0][B] | frame_read_inst/v_cnt_10_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk | ||||
| 0.368 | 0.368 | tCL | RR | 158 | PLL_L[1] | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1 |
| 0.974 | 0.606 | tNET | RR | 1 | R41C20[0][B] | frame_read_inst/v_cnt_10_s0/CLK |
| 0.926 | -0.048 | tHld | 1 | R41C20[0][B] | frame_read_inst/v_cnt_10_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.606, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.084, 39.241%; tC2Q: 0.130, 60.759% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.606, 100.000% |
Path3
Path Summary:
| Slack | 0.280 |
| Data Arrival Time | 1.018 |
| Data Required Time | 0.738 |
| From | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/reset_n_d_s0 |
| To | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_dpp_8_s1 |
| Launch Clk | pclk:[R] |
| Latch Clk | pclk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | pclk | ||||
| 0.000 | 0.000 | tCL | RR | 10163 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK |
| 0.786 | 0.786 | tNET | RR | 1 | R30C63[1][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/reset_n_d_s0/CLK |
| 0.915 | 0.130 | tC2Q | RR | 159 | R30C63[1][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/reset_n_d_s0/Q |
| 1.018 | 0.103 | tNET | RR | 1 | R30C63[3][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_dpp_8_s1/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | pclk | ||||
| 0.000 | 0.000 | tCL | RR | 10163 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK |
| 0.786 | 0.786 | tNET | RR | 1 | R30C63[3][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_dpp_8_s1/CLK |
| 0.738 | -0.048 | tHld | 1 | R30C63[3][A] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_dpp_8_s1 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.786, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.103, 44.186%; tC2Q: 0.130, 55.814% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.786, 100.000% |
Path4
Path Summary:
| Slack | 0.347 |
| Data Arrival Time | 1.273 |
| Data Required Time | 0.926 |
| From | frame_read_inst/rst_n_d_1_s0 |
| To | frame_read_inst/v_cnt_4_s1 |
| Launch Clk | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk:[R] |
| Latch Clk | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk | ||||
| 0.368 | 0.368 | tCL | RR | 158 | PLL_L[1] | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1 |
| 0.974 | 0.606 | tNET | RR | 1 | R41C20[2][A] | frame_read_inst/rst_n_d_1_s0/CLK |
| 1.103 | 0.130 | tC2Q | RR | 25 | R41C20[2][A] | frame_read_inst/rst_n_d_1_s0/Q |
| 1.273 | 0.170 | tNET | RR | 1 | R42C20[0][A] | frame_read_inst/v_cnt_4_s1/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk | ||||
| 0.368 | 0.368 | tCL | RR | 158 | PLL_L[1] | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1 |
| 0.974 | 0.606 | tNET | RR | 1 | R42C20[0][A] | frame_read_inst/v_cnt_4_s1/CLK |
| 0.926 | -0.048 | tHld | 1 | R42C20[0][A] | frame_read_inst/v_cnt_4_s1 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.606, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.170, 56.757%; tC2Q: 0.130, 43.243% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.606, 100.000% |
Path5
Path Summary:
| Slack | 0.347 |
| Data Arrival Time | 1.273 |
| Data Required Time | 0.926 |
| From | frame_read_inst/rst_n_d_1_s0 |
| To | frame_read_inst/v_cnt_6_s1 |
| Launch Clk | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk:[R] |
| Latch Clk | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk | ||||
| 0.368 | 0.368 | tCL | RR | 158 | PLL_L[1] | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1 |
| 0.974 | 0.606 | tNET | RR | 1 | R41C20[2][A] | frame_read_inst/rst_n_d_1_s0/CLK |
| 1.103 | 0.130 | tC2Q | RR | 25 | R41C20[2][A] | frame_read_inst/rst_n_d_1_s0/Q |
| 1.273 | 0.170 | tNET | RR | 1 | R42C20[0][B] | frame_read_inst/v_cnt_6_s1/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk | ||||
| 0.368 | 0.368 | tCL | RR | 158 | PLL_L[1] | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1 |
| 0.974 | 0.606 | tNET | RR | 1 | R42C20[0][B] | frame_read_inst/v_cnt_6_s1/CLK |
| 0.926 | -0.048 | tHld | 1 | R42C20[0][B] | frame_read_inst/v_cnt_6_s1 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.606, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.170, 56.757%; tC2Q: 0.130, 43.243% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.606, 100.000% |
Path6
Path Summary:
| Slack | 0.347 |
| Data Arrival Time | 1.273 |
| Data Required Time | 0.926 |
| From | frame_read_inst/rst_n_d_1_s0 |
| To | frame_read_inst/v_cnt_8_s0 |
| Launch Clk | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk:[R] |
| Latch Clk | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk | ||||
| 0.368 | 0.368 | tCL | RR | 158 | PLL_L[1] | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1 |
| 0.974 | 0.606 | tNET | RR | 1 | R41C20[2][A] | frame_read_inst/rst_n_d_1_s0/CLK |
| 1.103 | 0.130 | tC2Q | RR | 25 | R41C20[2][A] | frame_read_inst/rst_n_d_1_s0/Q |
| 1.273 | 0.170 | tNET | RR | 1 | R42C20[2][B] | frame_read_inst/v_cnt_8_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk | ||||
| 0.368 | 0.368 | tCL | RR | 158 | PLL_L[1] | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1 |
| 0.974 | 0.606 | tNET | RR | 1 | R42C20[2][B] | frame_read_inst/v_cnt_8_s0/CLK |
| 0.926 | -0.048 | tHld | 1 | R42C20[2][B] | frame_read_inst/v_cnt_8_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.606, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.170, 56.757%; tC2Q: 0.130, 43.243% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.606, 100.000% |
Path7
Path Summary:
| Slack | 0.347 |
| Data Arrival Time | 1.273 |
| Data Required Time | 0.926 |
| From | frame_read_inst/rst_n_d_1_s0 |
| To | frame_read_inst/v_cnt_11_s0 |
| Launch Clk | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk:[R] |
| Latch Clk | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk | ||||
| 0.368 | 0.368 | tCL | RR | 158 | PLL_L[1] | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1 |
| 0.974 | 0.606 | tNET | RR | 1 | R41C20[2][A] | frame_read_inst/rst_n_d_1_s0/CLK |
| 1.103 | 0.130 | tC2Q | RR | 25 | R41C20[2][A] | frame_read_inst/rst_n_d_1_s0/Q |
| 1.273 | 0.170 | tNET | RR | 1 | R42C20[3][A] | frame_read_inst/v_cnt_11_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk | ||||
| 0.368 | 0.368 | tCL | RR | 158 | PLL_L[1] | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1 |
| 0.974 | 0.606 | tNET | RR | 1 | R42C20[3][A] | frame_read_inst/v_cnt_11_s0/CLK |
| 0.926 | -0.048 | tHld | 1 | R42C20[3][A] | frame_read_inst/v_cnt_11_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.606, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.170, 56.757%; tC2Q: 0.130, 43.243% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.606, 100.000% |
Path8
Path Summary:
| Slack | 0.351 |
| Data Arrival Time | 1.273 |
| Data Required Time | 0.923 |
| From | frame_read_inst/rst_n_d_1_s0 |
| To | frame_read_inst/v_cnt_0_s1 |
| Launch Clk | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk:[R] |
| Latch Clk | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk | ||||
| 0.368 | 0.368 | tCL | RR | 158 | PLL_L[1] | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1 |
| 0.974 | 0.606 | tNET | RR | 1 | R41C20[2][A] | frame_read_inst/rst_n_d_1_s0/CLK |
| 1.103 | 0.130 | tC2Q | RR | 25 | R41C20[2][A] | frame_read_inst/rst_n_d_1_s0/Q |
| 1.273 | 0.170 | tNET | RR | 1 | R41C21[1][A] | frame_read_inst/v_cnt_0_s1/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk | ||||
| 0.368 | 0.368 | tCL | RR | 158 | PLL_L[1] | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1 |
| 0.970 | 0.602 | tNET | RR | 1 | R41C21[1][A] | frame_read_inst/v_cnt_0_s1/CLK |
| 0.923 | -0.048 | tHld | 1 | R41C21[1][A] | frame_read_inst/v_cnt_0_s1 |
Path Statistics:
| Clock Skew | -0.004 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.606, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.170, 56.757%; tC2Q: 0.130, 43.243% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.602, 100.000% |
Path9
Path Summary:
| Slack | 0.351 |
| Data Arrival Time | 1.273 |
| Data Required Time | 0.923 |
| From | frame_read_inst/rst_n_d_1_s0 |
| To | frame_read_inst/v_cnt_1_s1 |
| Launch Clk | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk:[R] |
| Latch Clk | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk | ||||
| 0.368 | 0.368 | tCL | RR | 158 | PLL_L[1] | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1 |
| 0.974 | 0.606 | tNET | RR | 1 | R41C20[2][A] | frame_read_inst/rst_n_d_1_s0/CLK |
| 1.103 | 0.130 | tC2Q | RR | 25 | R41C20[2][A] | frame_read_inst/rst_n_d_1_s0/Q |
| 1.273 | 0.170 | tNET | RR | 1 | R41C21[1][B] | frame_read_inst/v_cnt_1_s1/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk | ||||
| 0.368 | 0.368 | tCL | RR | 158 | PLL_L[1] | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1 |
| 0.970 | 0.602 | tNET | RR | 1 | R41C21[1][B] | frame_read_inst/v_cnt_1_s1/CLK |
| 0.923 | -0.048 | tHld | 1 | R41C21[1][B] | frame_read_inst/v_cnt_1_s1 |
Path Statistics:
| Clock Skew | -0.004 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.606, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.170, 56.757%; tC2Q: 0.130, 43.243% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.602, 100.000% |
Path10
Path Summary:
| Slack | 0.351 |
| Data Arrival Time | 1.273 |
| Data Required Time | 0.923 |
| From | frame_read_inst/rst_n_d_1_s0 |
| To | frame_read_inst/vfb_out_vs_s0 |
| Launch Clk | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk:[R] |
| Latch Clk | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk | ||||
| 0.368 | 0.368 | tCL | RR | 158 | PLL_L[1] | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1 |
| 0.974 | 0.606 | tNET | RR | 1 | R41C20[2][A] | frame_read_inst/rst_n_d_1_s0/CLK |
| 1.103 | 0.130 | tC2Q | RR | 25 | R41C20[2][A] | frame_read_inst/rst_n_d_1_s0/Q |
| 1.273 | 0.170 | tNET | RR | 1 | R41C21[2][A] | frame_read_inst/vfb_out_vs_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk | ||||
| 0.368 | 0.368 | tCL | RR | 158 | PLL_L[1] | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1 |
| 0.970 | 0.602 | tNET | RR | 1 | R41C21[2][A] | frame_read_inst/vfb_out_vs_s0/CLK |
| 0.923 | -0.048 | tHld | 1 | R41C21[2][A] | frame_read_inst/vfb_out_vs_s0 |
Path Statistics:
| Clock Skew | -0.004 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.606, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.170, 56.757%; tC2Q: 0.130, 43.243% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.602, 100.000% |
Path11
Path Summary:
| Slack | 0.360 |
| Data Arrival Time | 2.150 |
| Data Required Time | 1.790 |
| From | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/rstn_s0 |
| To | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_strb_o_3_s1 |
| Launch Clk | drp_clk:[R] |
| Latch Clk | drp_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | drp_clk | ||||
| 0.000 | 0.000 | tCL | RR | 249 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/FABRIC_CM_LIFE_CLK_O |
| 1.838 | 1.838 | tNET | RR | 1 | R37C70[2][B] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/rstn_s0/CLK |
| 1.967 | 0.130 | tC2Q | RR | 175 | R37C70[2][B] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/rstn_s0/Q |
| 2.150 | 0.183 | tNET | RR | 1 | R37C68[3][A] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_strb_o_3_s1/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | drp_clk | ||||
| 0.000 | 0.000 | tCL | RR | 249 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/FABRIC_CM_LIFE_CLK_O |
| 1.838 | 1.838 | tNET | RR | 1 | R37C68[3][A] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_strb_o_3_s1/CLK |
| 1.790 | -0.048 | tHld | 1 | R37C68[3][A] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_strb_o_3_s1 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.838, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.183, 58.501%; tC2Q: 0.130, 41.499% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.838, 100.000% |
Path12
Path Summary:
| Slack | 0.360 |
| Data Arrival Time | 2.150 |
| Data Required Time | 1.790 |
| From | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/rstn_s0 |
| To | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wrdata_o_28_s1 |
| Launch Clk | drp_clk:[R] |
| Latch Clk | drp_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | drp_clk | ||||
| 0.000 | 0.000 | tCL | RR | 249 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/FABRIC_CM_LIFE_CLK_O |
| 1.838 | 1.838 | tNET | RR | 1 | R37C70[2][B] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/rstn_s0/CLK |
| 1.967 | 0.130 | tC2Q | RR | 175 | R37C70[2][B] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/rstn_s0/Q |
| 2.150 | 0.183 | tNET | RR | 1 | R35C70[1][A] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wrdata_o_28_s1/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | drp_clk | ||||
| 0.000 | 0.000 | tCL | RR | 249 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/FABRIC_CM_LIFE_CLK_O |
| 1.838 | 1.838 | tNET | RR | 1 | R35C70[1][A] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wrdata_o_28_s1/CLK |
| 1.790 | -0.048 | tHld | 1 | R35C70[1][A] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wrdata_o_28_s1 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.838, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.183, 58.501%; tC2Q: 0.130, 41.499% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.838, 100.000% |
Path13
Path Summary:
| Slack | 0.360 |
| Data Arrival Time | 2.150 |
| Data Required Time | 1.790 |
| From | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/rstn_s0 |
| To | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/drp_strb_serdes_3_s0 |
| Launch Clk | drp_clk:[R] |
| Latch Clk | drp_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | drp_clk | ||||
| 0.000 | 0.000 | tCL | RR | 249 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/FABRIC_CM_LIFE_CLK_O |
| 1.838 | 1.838 | tNET | RR | 1 | R37C70[2][B] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/rstn_s0/CLK |
| 1.967 | 0.130 | tC2Q | RR | 175 | R37C70[2][B] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/rstn_s0/Q |
| 2.150 | 0.183 | tNET | RR | 1 | R37C68[0][A] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/drp_strb_serdes_3_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | drp_clk | ||||
| 0.000 | 0.000 | tCL | RR | 249 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/FABRIC_CM_LIFE_CLK_O |
| 1.838 | 1.838 | tNET | RR | 1 | R37C68[0][A] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/drp_strb_serdes_3_s0/CLK |
| 1.790 | -0.048 | tHld | 1 | R37C68[0][A] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/drp_strb_serdes_3_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.838, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.183, 58.501%; tC2Q: 0.130, 41.499% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.838, 100.000% |
Path14
Path Summary:
| Slack | 0.360 |
| Data Arrival Time | 2.150 |
| Data Required Time | 1.790 |
| From | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/rstn_s0 |
| To | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/drp_wrdata_serdes_28_s0 |
| Launch Clk | drp_clk:[R] |
| Latch Clk | drp_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | drp_clk | ||||
| 0.000 | 0.000 | tCL | RR | 249 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/FABRIC_CM_LIFE_CLK_O |
| 1.838 | 1.838 | tNET | RR | 1 | R37C70[2][B] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/rstn_s0/CLK |
| 1.967 | 0.130 | tC2Q | RR | 175 | R37C70[2][B] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/rstn_s0/Q |
| 2.150 | 0.183 | tNET | RR | 1 | R35C70[0][A] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/drp_wrdata_serdes_28_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | drp_clk | ||||
| 0.000 | 0.000 | tCL | RR | 249 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/FABRIC_CM_LIFE_CLK_O |
| 1.838 | 1.838 | tNET | RR | 1 | R35C70[0][A] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/drp_wrdata_serdes_28_s0/CLK |
| 1.790 | -0.048 | tHld | 1 | R35C70[0][A] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/drp_wrdata_serdes_28_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.838, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.183, 58.501%; tC2Q: 0.130, 41.499% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.838, 100.000% |
Path15
Path Summary:
| Slack | 0.360 |
| Data Arrival Time | 1.290 |
| Data Required Time | 0.930 |
| From | frame_read_inst/rst_n_d_1_s0 |
| To | frame_read_inst/h_cnt_2_s1 |
| Launch Clk | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk:[R] |
| Latch Clk | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk | ||||
| 0.368 | 0.368 | tCL | RR | 158 | PLL_L[1] | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1 |
| 0.974 | 0.606 | tNET | RR | 1 | R41C20[2][A] | frame_read_inst/rst_n_d_1_s0/CLK |
| 1.103 | 0.130 | tC2Q | RR | 25 | R41C20[2][A] | frame_read_inst/rst_n_d_1_s0/Q |
| 1.290 | 0.186 | tNET | RR | 1 | R41C23[3][A] | frame_read_inst/h_cnt_2_s1/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk | ||||
| 0.368 | 0.368 | tCL | RR | 158 | PLL_L[1] | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1 |
| 0.977 | 0.609 | tNET | RR | 1 | R41C23[3][A] | frame_read_inst/h_cnt_2_s1/CLK |
| 0.930 | -0.048 | tHld | 1 | R41C23[3][A] | frame_read_inst/h_cnt_2_s1 |
Path Statistics:
| Clock Skew | 0.004 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.606, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.186, 58.974%; tC2Q: 0.130, 41.026% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.609, 100.000% |
Path16
Path Summary:
| Slack | 0.360 |
| Data Arrival Time | 1.290 |
| Data Required Time | 0.930 |
| From | frame_read_inst/rst_n_d_1_s0 |
| To | frame_read_inst/h_cnt_3_s1 |
| Launch Clk | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk:[R] |
| Latch Clk | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk | ||||
| 0.368 | 0.368 | tCL | RR | 158 | PLL_L[1] | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1 |
| 0.974 | 0.606 | tNET | RR | 1 | R41C20[2][A] | frame_read_inst/rst_n_d_1_s0/CLK |
| 1.103 | 0.130 | tC2Q | RR | 25 | R41C20[2][A] | frame_read_inst/rst_n_d_1_s0/Q |
| 1.290 | 0.186 | tNET | RR | 1 | R41C23[0][B] | frame_read_inst/h_cnt_3_s1/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk | ||||
| 0.368 | 0.368 | tCL | RR | 158 | PLL_L[1] | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1 |
| 0.977 | 0.609 | tNET | RR | 1 | R41C23[0][B] | frame_read_inst/h_cnt_3_s1/CLK |
| 0.930 | -0.048 | tHld | 1 | R41C23[0][B] | frame_read_inst/h_cnt_3_s1 |
Path Statistics:
| Clock Skew | 0.004 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.606, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.186, 58.974%; tC2Q: 0.130, 41.026% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.609, 100.000% |
Path17
Path Summary:
| Slack | 0.360 |
| Data Arrival Time | 1.290 |
| Data Required Time | 0.930 |
| From | frame_read_inst/rst_n_d_1_s0 |
| To | frame_read_inst/h_cnt_4_s1 |
| Launch Clk | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk:[R] |
| Latch Clk | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk | ||||
| 0.368 | 0.368 | tCL | RR | 158 | PLL_L[1] | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1 |
| 0.974 | 0.606 | tNET | RR | 1 | R41C20[2][A] | frame_read_inst/rst_n_d_1_s0/CLK |
| 1.103 | 0.130 | tC2Q | RR | 25 | R41C20[2][A] | frame_read_inst/rst_n_d_1_s0/Q |
| 1.290 | 0.186 | tNET | RR | 1 | R41C23[1][B] | frame_read_inst/h_cnt_4_s1/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk | ||||
| 0.368 | 0.368 | tCL | RR | 158 | PLL_L[1] | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1 |
| 0.977 | 0.609 | tNET | RR | 1 | R41C23[1][B] | frame_read_inst/h_cnt_4_s1/CLK |
| 0.930 | -0.048 | tHld | 1 | R41C23[1][B] | frame_read_inst/h_cnt_4_s1 |
Path Statistics:
| Clock Skew | 0.004 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.606, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.186, 58.974%; tC2Q: 0.130, 41.026% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.609, 100.000% |
Path18
Path Summary:
| Slack | 0.360 |
| Data Arrival Time | 1.290 |
| Data Required Time | 0.930 |
| From | frame_read_inst/rst_n_d_1_s0 |
| To | frame_read_inst/h_cnt_5_s1 |
| Launch Clk | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk:[R] |
| Latch Clk | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk | ||||
| 0.368 | 0.368 | tCL | RR | 158 | PLL_L[1] | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1 |
| 0.974 | 0.606 | tNET | RR | 1 | R41C20[2][A] | frame_read_inst/rst_n_d_1_s0/CLK |
| 1.103 | 0.130 | tC2Q | RR | 25 | R41C20[2][A] | frame_read_inst/rst_n_d_1_s0/Q |
| 1.290 | 0.186 | tNET | RR | 1 | R41C23[1][A] | frame_read_inst/h_cnt_5_s1/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk | ||||
| 0.368 | 0.368 | tCL | RR | 158 | PLL_L[1] | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1 |
| 0.977 | 0.609 | tNET | RR | 1 | R41C23[1][A] | frame_read_inst/h_cnt_5_s1/CLK |
| 0.930 | -0.048 | tHld | 1 | R41C23[1][A] | frame_read_inst/h_cnt_5_s1 |
Path Statistics:
| Clock Skew | 0.004 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.606, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.186, 58.974%; tC2Q: 0.130, 41.026% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.609, 100.000% |
Path19
Path Summary:
| Slack | 0.363 |
| Data Arrival Time | 1.238 |
| Data Required Time | 0.876 |
| From | testpattern_yuv_inst/rst_n_local_s0 |
| To | testpattern_yuv_inst/yuv_data_45_s0 |
| Launch Clk | rgb_clk:[R] |
| Latch Clk | rgb_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | rgb_clk | ||||
| 0.000 | 0.000 | tCL | RR | 431 | PLL_L[1] | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0 |
| 0.920 | 0.920 | tNET | RR | 1 | R41C18[0][A] | testpattern_yuv_inst/rst_n_local_s0/CLK |
| 1.049 | 0.130 | tC2Q | RR | 198 | R41C18[0][A] | testpattern_yuv_inst/rst_n_local_s0/Q |
| 1.238 | 0.189 | tNET | RR | 1 | R41C19[1][A] | testpattern_yuv_inst/yuv_data_45_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | rgb_clk | ||||
| 0.000 | 0.000 | tCL | RR | 431 | PLL_L[1] | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0 |
| 0.923 | 0.923 | tNET | RR | 1 | R41C19[1][A] | testpattern_yuv_inst/yuv_data_45_s0/CLK |
| 0.876 | -0.048 | tHld | 1 | R41C19[1][A] | testpattern_yuv_inst/yuv_data_45_s0 |
Path Statistics:
| Clock Skew | 0.004 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.920, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.189, 59.322%; tC2Q: 0.130, 40.678% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.923, 100.000% |
Path20
Path Summary:
| Slack | 0.363 |
| Data Arrival Time | 2.149 |
| Data Required Time | 1.786 |
| From | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/upar_rstn_r1_s0 |
| To | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_upar_csr/csr_addr_12_s0 |
| Launch Clk | drp_clk:[R] |
| Latch Clk | drp_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | drp_clk | ||||
| 0.000 | 0.000 | tCL | RR | 249 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/FABRIC_CM_LIFE_CLK_O |
| 1.664 | 1.664 | tNET | RR | 1 | R36C76[1][B] | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/upar_rstn_r1_s0/CLK |
| 1.794 | 0.130 | tC2Q | RR | 54 | R36C76[1][B] | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/upar_rstn_r1_s0/Q |
| 2.149 | 0.355 | tNET | RR | 1 | R32C73[1][A] | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_upar_csr/csr_addr_12_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | drp_clk | ||||
| 0.000 | 0.000 | tCL | RR | 249 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/FABRIC_CM_LIFE_CLK_O |
| 1.834 | 1.834 | tNET | RR | 1 | R32C73[1][A] | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_upar_csr/csr_addr_12_s0/CLK |
| 1.786 | -0.048 | tHld | 1 | R32C73[1][A] | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_upar_csr/csr_addr_12_s0 |
Path Statistics:
| Clock Skew | 0.170 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.664, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.355, 73.284%; tC2Q: 0.130, 26.716% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.834, 100.000% |
Path21
Path Summary:
| Slack | 0.365 |
| Data Arrival Time | 1.984 |
| Data Required Time | 1.620 |
| From | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/upar_rstn_r1_s0 |
| To | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_upar_csr/tx_detect_rx_en_d2_s0 |
| Launch Clk | drp_clk:[R] |
| Latch Clk | drp_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | drp_clk | ||||
| 0.000 | 0.000 | tCL | RR | 249 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/FABRIC_CM_LIFE_CLK_O |
| 1.664 | 1.664 | tNET | RR | 1 | R36C76[1][B] | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/upar_rstn_r1_s0/CLK |
| 1.794 | 0.130 | tC2Q | RR | 54 | R36C76[1][B] | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/upar_rstn_r1_s0/Q |
| 1.984 | 0.191 | tNET | RR | 1 | R36C75[0][A] | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_upar_csr/tx_detect_rx_en_d2_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | drp_clk | ||||
| 0.000 | 0.000 | tCL | RR | 249 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/FABRIC_CM_LIFE_CLK_O |
| 1.667 | 1.667 | tNET | RR | 1 | R36C75[0][A] | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_upar_csr/tx_detect_rx_en_d2_s0/CLK |
| 1.620 | -0.048 | tHld | 1 | R36C75[0][A] | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_upar_csr/tx_detect_rx_en_d2_s0 |
Path Statistics:
| Clock Skew | 0.003 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.664, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.191, 59.551%; tC2Q: 0.130, 40.449% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.667, 100.000% |
Path22
Path Summary:
| Slack | 0.365 |
| Data Arrival Time | 1.984 |
| Data Required Time | 1.620 |
| From | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/upar_rstn_r1_s0 |
| To | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_upar_csr/tx_detect_rx_en_d1_s0 |
| Launch Clk | drp_clk:[R] |
| Latch Clk | drp_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | drp_clk | ||||
| 0.000 | 0.000 | tCL | RR | 249 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/FABRIC_CM_LIFE_CLK_O |
| 1.664 | 1.664 | tNET | RR | 1 | R36C76[1][B] | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/upar_rstn_r1_s0/CLK |
| 1.794 | 0.130 | tC2Q | RR | 54 | R36C76[1][B] | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/upar_rstn_r1_s0/Q |
| 1.984 | 0.191 | tNET | RR | 1 | R36C75[1][A] | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_upar_csr/tx_detect_rx_en_d1_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | drp_clk | ||||
| 0.000 | 0.000 | tCL | RR | 249 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/FABRIC_CM_LIFE_CLK_O |
| 1.667 | 1.667 | tNET | RR | 1 | R36C75[1][A] | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_upar_csr/tx_detect_rx_en_d1_s0/CLK |
| 1.620 | -0.048 | tHld | 1 | R36C75[1][A] | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_upar_csr/tx_detect_rx_en_d1_s0 |
Path Statistics:
| Clock Skew | 0.003 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.664, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.191, 59.551%; tC2Q: 0.130, 40.449% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.667, 100.000% |
Path23
Path Summary:
| Slack | 0.365 |
| Data Arrival Time | 1.984 |
| Data Required Time | 1.620 |
| From | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/upar_rstn_r1_s0 |
| To | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_upar_csr/eidle_en_d2_s0 |
| Launch Clk | drp_clk:[R] |
| Latch Clk | drp_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | drp_clk | ||||
| 0.000 | 0.000 | tCL | RR | 249 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/FABRIC_CM_LIFE_CLK_O |
| 1.664 | 1.664 | tNET | RR | 1 | R36C76[1][B] | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/upar_rstn_r1_s0/CLK |
| 1.794 | 0.130 | tC2Q | RR | 54 | R36C76[1][B] | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/upar_rstn_r1_s0/Q |
| 1.984 | 0.191 | tNET | RR | 1 | R36C75[1][B] | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_upar_csr/eidle_en_d2_s0/PRESET |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | drp_clk | ||||
| 0.000 | 0.000 | tCL | RR | 249 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/FABRIC_CM_LIFE_CLK_O |
| 1.667 | 1.667 | tNET | RR | 1 | R36C75[1][B] | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_upar_csr/eidle_en_d2_s0/CLK |
| 1.620 | -0.048 | tHld | 1 | R36C75[1][B] | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_upar_csr/eidle_en_d2_s0 |
Path Statistics:
| Clock Skew | 0.003 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.664, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.191, 59.551%; tC2Q: 0.130, 40.449% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.667, 100.000% |
Path24
Path Summary:
| Slack | 0.366 |
| Data Arrival Time | 1.104 |
| Data Required Time | 0.738 |
| From | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/reset_n_d_s0 |
| To | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_dpp_13_s1 |
| Launch Clk | pclk:[R] |
| Latch Clk | pclk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | pclk | ||||
| 0.000 | 0.000 | tCL | RR | 10163 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK |
| 0.786 | 0.786 | tNET | RR | 1 | R30C63[1][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/reset_n_d_s0/CLK |
| 0.915 | 0.130 | tC2Q | RR | 159 | R30C63[1][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/reset_n_d_s0/Q |
| 1.104 | 0.189 | tNET | RR | 1 | R31C63[2][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_dpp_13_s1/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | pclk | ||||
| 0.000 | 0.000 | tCL | RR | 10163 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK |
| 0.786 | 0.786 | tNET | RR | 1 | R31C63[2][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_dpp_13_s1/CLK |
| 0.738 | -0.048 | tHld | 1 | R31C63[2][B] | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_dpp_13_s1 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.786, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.189, 59.322%; tC2Q: 0.130, 40.678% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.786, 100.000% |
Path25
Path Summary:
| Slack | 0.366 |
| Data Arrival Time | 2.153 |
| Data Required Time | 1.786 |
| From | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/rstn_s0 |
| To | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wrdata_o_6_s1 |
| Launch Clk | drp_clk:[R] |
| Latch Clk | drp_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | drp_clk | ||||
| 0.000 | 0.000 | tCL | RR | 249 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/FABRIC_CM_LIFE_CLK_O |
| 1.838 | 1.838 | tNET | RR | 1 | R37C70[2][B] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/rstn_s0/CLK |
| 1.967 | 0.130 | tC2Q | RR | 175 | R37C70[2][B] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/rstn_s0/Q |
| 2.153 | 0.185 | tNET | RR | 1 | R37C69[1][A] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wrdata_o_6_s1/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | drp_clk | ||||
| 0.000 | 0.000 | tCL | RR | 249 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/FABRIC_CM_LIFE_CLK_O |
| 1.834 | 1.834 | tNET | RR | 1 | R37C69[1][A] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wrdata_o_6_s1/CLK |
| 1.786 | -0.048 | tHld | 1 | R37C69[1][A] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wrdata_o_6_s1 |
Path Statistics:
| Clock Skew | -0.004 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.838, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.185, 58.857%; tC2Q: 0.130, 41.143% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.834, 100.000% |
Minimum Pulse Width Report:
Report Command:report_min_pulse_width -nworst 10 -detail
MPW1
MPW Summary:
| Slack: | 0.817 |
| Actual Width: | 1.593 |
| Required Width: | 0.776 |
| Type: | Low Pulse Width |
| Clock: | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk |
| Objects: | u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.mem_Small.mem_0_4_s |
Late clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 3.361 | 0.000 | active clock edge time | ||
| 3.361 | 0.000 | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk | ||
| 4.412 | 1.051 | tCL | FF | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1 |
| 6.284 | 1.872 | tNET | FF | u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.mem_Small.mem_0_4_s/CLKB |
Early clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 6.723 | 0.000 | active clock edge time | ||
| 6.723 | 0.000 | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk | ||
| 7.091 | 0.368 | tCL | RR | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1 |
| 7.877 | 0.787 | tNET | RR | u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.mem_Small.mem_0_4_s/CLKB |
MPW2
MPW Summary:
| Slack: | 0.817 |
| Actual Width: | 1.593 |
| Required Width: | 0.776 |
| Type: | Low Pulse Width |
| Clock: | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk |
| Objects: | line_fifo_inst/fifo_inst/Equal.mem_Equal.mem_0_4_s |
Late clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 3.361 | 0.000 | active clock edge time | ||
| 3.361 | 0.000 | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk | ||
| 4.412 | 1.051 | tCL | FF | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1 |
| 6.284 | 1.872 | tNET | FF | line_fifo_inst/fifo_inst/Equal.mem_Equal.mem_0_4_s/CLKA |
Early clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 6.723 | 0.000 | active clock edge time | ||
| 6.723 | 0.000 | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk | ||
| 7.091 | 0.368 | tCL | RR | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1 |
| 7.877 | 0.787 | tNET | RR | line_fifo_inst/fifo_inst/Equal.mem_Equal.mem_0_4_s/CLKA |
MPW3
MPW Summary:
| Slack: | 0.819 |
| Actual Width: | 1.595 |
| Required Width: | 0.776 |
| Type: | High Pulse Width |
| Clock: | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk |
| Objects: | u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.mem_Small.mem_0_4_s |
Late clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||
| 0.000 | 0.000 | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk | ||
| 1.051 | 1.051 | tCL | RR | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1 |
| 2.925 | 1.875 | tNET | RR | u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.mem_Small.mem_0_4_s/CLKB |
Early clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 3.361 | 0.000 | active clock edge time | ||
| 3.361 | 0.000 | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk | ||
| 3.729 | 0.368 | tCL | FF | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1 |
| 4.521 | 0.791 | tNET | FF | u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.mem_Small.mem_0_4_s/CLKB |
MPW4
MPW Summary:
| Slack: | 0.819 |
| Actual Width: | 1.595 |
| Required Width: | 0.776 |
| Type: | High Pulse Width |
| Clock: | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk |
| Objects: | line_fifo_inst/fifo_inst/Equal.mem_Equal.mem_0_4_s |
Late clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||
| 0.000 | 0.000 | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk | ||
| 1.051 | 1.051 | tCL | RR | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1 |
| 2.925 | 1.875 | tNET | RR | line_fifo_inst/fifo_inst/Equal.mem_Equal.mem_0_4_s/CLKA |
Early clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 3.361 | 0.000 | active clock edge time | ||
| 3.361 | 0.000 | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk | ||
| 3.729 | 0.368 | tCL | FF | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1 |
| 4.521 | 0.791 | tNET | FF | line_fifo_inst/fifo_inst/Equal.mem_Equal.mem_0_4_s/CLKA |
MPW5
MPW Summary:
| Slack: | 0.821 |
| Actual Width: | 1.596 |
| Required Width: | 0.776 |
| Type: | Low Pulse Width |
| Clock: | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk |
| Objects: | u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.mem_Small.mem_0_0_s |
Late clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 3.361 | 0.000 | active clock edge time | ||
| 3.361 | 0.000 | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk | ||
| 4.412 | 1.051 | tCL | FF | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1 |
| 6.277 | 1.865 | tNET | FF | u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.mem_Small.mem_0_0_s/CLKB |
Early clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 6.723 | 0.000 | active clock edge time | ||
| 6.723 | 0.000 | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk | ||
| 7.091 | 0.368 | tCL | RR | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1 |
| 7.874 | 0.783 | tNET | RR | u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.mem_Small.mem_0_0_s/CLKB |
MPW6
MPW Summary:
| Slack: | 0.821 |
| Actual Width: | 1.596 |
| Required Width: | 0.776 |
| Type: | Low Pulse Width |
| Clock: | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk |
| Objects: | u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.mem_Small.mem_0_6_s |
Late clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 3.361 | 0.000 | active clock edge time | ||
| 3.361 | 0.000 | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk | ||
| 4.412 | 1.051 | tCL | FF | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1 |
| 6.277 | 1.865 | tNET | FF | u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.mem_Small.mem_0_6_s/CLKB |
Early clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 6.723 | 0.000 | active clock edge time | ||
| 6.723 | 0.000 | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk | ||
| 7.091 | 0.368 | tCL | RR | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1 |
| 7.874 | 0.783 | tNET | RR | u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.mem_Small.mem_0_6_s/CLKB |
MPW7
MPW Summary:
| Slack: | 0.821 |
| Actual Width: | 1.596 |
| Required Width: | 0.776 |
| Type: | Low Pulse Width |
| Clock: | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk |
| Objects: | line_fifo_inst/fifo_inst/Equal.mem_Equal.mem_0_1_s |
Late clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 3.361 | 0.000 | active clock edge time | ||
| 3.361 | 0.000 | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk | ||
| 4.412 | 1.051 | tCL | FF | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1 |
| 6.277 | 1.865 | tNET | FF | line_fifo_inst/fifo_inst/Equal.mem_Equal.mem_0_1_s/CLKA |
Early clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 6.723 | 0.000 | active clock edge time | ||
| 6.723 | 0.000 | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk | ||
| 7.091 | 0.368 | tCL | RR | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1 |
| 7.874 | 0.783 | tNET | RR | line_fifo_inst/fifo_inst/Equal.mem_Equal.mem_0_1_s/CLKA |
MPW8
MPW Summary:
| Slack: | 0.822 |
| Actual Width: | 1.598 |
| Required Width: | 0.776 |
| Type: | High Pulse Width |
| Clock: | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk |
| Objects: | u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.mem_Small.mem_0_0_s |
Late clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||
| 0.000 | 0.000 | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk | ||
| 1.051 | 1.051 | tCL | RR | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1 |
| 2.919 | 1.868 | tNET | RR | u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.mem_Small.mem_0_0_s/CLKB |
Early clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 3.361 | 0.000 | active clock edge time | ||
| 3.361 | 0.000 | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk | ||
| 3.729 | 0.368 | tCL | FF | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1 |
| 4.517 | 0.787 | tNET | FF | u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.mem_Small.mem_0_0_s/CLKB |
MPW9
MPW Summary:
| Slack: | 0.822 |
| Actual Width: | 1.598 |
| Required Width: | 0.776 |
| Type: | High Pulse Width |
| Clock: | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk |
| Objects: | u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.mem_Small.mem_0_6_s |
Late clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||
| 0.000 | 0.000 | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk | ||
| 1.051 | 1.051 | tCL | RR | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1 |
| 2.919 | 1.868 | tNET | RR | u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.mem_Small.mem_0_6_s/CLKB |
Early clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 3.361 | 0.000 | active clock edge time | ||
| 3.361 | 0.000 | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk | ||
| 3.729 | 0.368 | tCL | FF | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1 |
| 4.517 | 0.787 | tNET | FF | u_Video_Frame_Buffer_Top/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.mem_Small.mem_0_6_s/CLKB |
MPW10
MPW Summary:
| Slack: | 0.822 |
| Actual Width: | 1.598 |
| Required Width: | 0.776 |
| Type: | High Pulse Width |
| Clock: | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk |
| Objects: | line_fifo_inst/fifo_inst/Equal.mem_Equal.mem_0_1_s |
Late clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||
| 0.000 | 0.000 | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk | ||
| 1.051 | 1.051 | tCL | RR | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1 |
| 2.919 | 1.868 | tNET | RR | line_fifo_inst/fifo_inst/Equal.mem_Equal.mem_0_1_s/CLKA |
Early clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 3.361 | 0.000 | active clock edge time | ||
| 3.361 | 0.000 | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1.default_gen_clk | ||
| 3.729 | 0.368 | tCL | FF | Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT1 |
| 4.517 | 0.787 | tNET | FF | line_fifo_inst/fifo_inst/Equal.mem_Equal.mem_0_1_s/CLKA |
High Fanout Nets Report:
Report Command:report_high_fanout_nets -max_nets 10
| FANOUT | NET NAME | WORST SLACK | MAX DELAY |
|---|---|---|---|
| 10163 | pclk | 0.047 | 1.876 |
| 3995 | dma_clk | 0.902 | 1.875 |
| 2598 | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0 | 0.067 | 2.097 |
| 954 | UserLayer_top_inst/rst_n_d[1] | 3.413 | 1.981 |
| 518 | SerDes_Top_inst/q0_lane1_fabric_rx_clk | 0.280 | 1.876 |
| 516 | SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/internel_resetn | 2.861 | 2.609 |
| 470 | clk_24m_d | 36.832 | 1.973 |
| 431 | rgb_clk | 1.332 | 2.493 |
| 375 | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/n340_7 | 3.331 | 1.414 |
| 332 | USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/prot_rst_n_d1 | 3.207 | 2.286 |
Route Congestions Report:
Report Command:report_route_congestion -max_grids 10
| GRID LOC | ROUTE CONGESTIONS |
|---|---|
| R55C55 | 94.44% |
| R70C100 | 94.44% |
| R71C101 | 91.67% |
| R69C99 | 90.28% |
| R69C100 | 90.28% |
| R70C55 | 90.28% |
| R71C98 | 90.28% |
| R70C96 | 90.28% |
| R70C97 | 90.28% |
| R4C83 | 88.89% |
Timing Exceptions Report:
Setup Analysis Report
Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Hold Analysis Report
Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Recovery Analysis Report
Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Removal Analysis Report
Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Timing Constraints Report:
| SDC Command Type | State | Detail Command |
|---|---|---|
| TC_CLOCK | Actived | create_clock -name pclk -period 6.25 -waveform {0 3.2} [get_nets {pclk}] |
| TC_CLOCK | Actived | create_clock -name q0_lane1_fabric_rx_clk -period 6.25 -waveform {0 3.2} [get_nets {SerDes_Top_inst/q0_lane1_fabric_rx_clk}] |
| TC_CLOCK | Actived | create_clock -name drp_clk -period 10 -waveform {0 5} [get_nets {SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst_drp_clk_o[1]}] |
| TC_CLOCK | Actived | create_clock -name clk_24m -period 41.667 -waveform {0 20.834} [get_nets {clk_24m}] |
| TC_CLOCK | Actived | create_clock -name sys_clk -period 5 -waveform {0 2.5} [get_nets {sys_clk}] |
| TC_CLOCK | Actived | create_clock -name rgb_clk -period 6.25 -waveform {0 3.125} [get_nets {rgb_clk}] |
| TC_CLOCK | Actived | create_clock -name dma_clk -period 7.273 -waveform {0 3.636} [get_nets {dma_clk}] |
| TC_CLOCK | Actived | create_clock -name memory_clk -period 1.818 -waveform {0 0.909} [get_nets {memory_clk}] |
| TC_CLOCK_GROUP | Actived | set_clock_groups -asynchronous -group [get_clocks {pclk}] |
| TC_CLOCK_GROUP | Actived | set_clock_groups -asynchronous -group [get_clocks {q0_lane1_fabric_rx_clk}] |
| TC_CLOCK_GROUP | Actived | set_clock_groups -asynchronous -group [get_clocks {drp_clk}] |
| TC_CLOCK_GROUP | Actived | set_clock_groups -asynchronous -group [get_clocks {sys_clk}] |
| TC_CLOCK_GROUP | Actived | set_clock_groups -asynchronous -group [get_clocks {rgb_clk}] |
| TC_CLOCK_GROUP | Actived | set_clock_groups -asynchronous -group [get_clocks {dma_clk}] |
| TC_CLOCK_GROUP | Actived | set_clock_groups -asynchronous -group [get_clocks {clk_24m}] |
| TC_CLOCK_GROUP | Actived | set_clock_groups -asynchronous -group [get_clocks {memory_clk}] |
| TC_REPORT_TIMING | Actived | report_timing -setup -max_paths 100 -max_common_paths 1 |