Synthesis Messages

Report Title GowinSynthesis Report
Design File D:\Gowin\Gowin_V1.9.12.01_x64\IDE\ipcore\SDIDecoder\data\sdi_decoder_top.v
D:\Gowin\Gowin_V1.9.12.01_x64\IDE\ipcore\SDIDecoder\data\sdi_decoder_wrapper.v
GowinSynthesis Constraints File ---
Tool Version V1.9.12.01 (64-bit)
Part Number GW5AT-LV60PG484AES
Device GW5AT-60
Device Version B
Created Time Mon Dec 8 16:52:24 2025
Legal Announcement Copyright (C)2014-2025 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module SDI_Decoder_Top
Synthesis Process Running parser:
    CPU time = 0h 0m 0.343s, Elapsed time = 0h 0m 0.333s, Peak memory usage = 95.531MB
Running netlist conversion:
    CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.045s, Peak memory usage = 95.531MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0.14s, Elapsed time = 0h 0m 0.143s, Peak memory usage = 95.531MB
    Optimizing Phase 1: CPU time = 0h 0m 0.093s, Elapsed time = 0h 0m 0.094s, Peak memory usage = 95.531MB
    Optimizing Phase 2: CPU time = 0h 0m 0.156s, Elapsed time = 0h 0m 0.154s, Peak memory usage = 95.531MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.063s, Peak memory usage = 95.531MB
    Inferring Phase 1: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.04s, Peak memory usage = 95.531MB
    Inferring Phase 2: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.02s, Peak memory usage = 95.531MB
    Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.009s, Peak memory usage = 95.531MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0.187s, Elapsed time = 0h 0m 0.176s, Peak memory usage = 95.531MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.059s, Peak memory usage = 95.531MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.023s, Peak memory usage = 95.531MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s, Peak memory usage = 120.809MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.125s, Elapsed time = 0h 0m 0.163s, Peak memory usage = 120.809MB
Generate output files:
    CPU time = 0h 0m 0.156s, Elapsed time = 0h 0m 0.16s, Peak memory usage = 120.809MB
Total Time and Memory Usage CPU time = 0h 0m 3s, Elapsed time = 0h 0m 3s, Peak memory usage = 120.809MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 596
I/O Buf 495
    IBUF 30
    OBUF 465
Register 2085
    DFFRE 13
    DFFPE 8
    DFFCE 2064
LUT 1197
    LUT2 127
    LUT3 418
    LUT4 652
MUX 72
    MUX2 72
ALU 42
    ALU 42
INV 10
    INV 10
BSRAM 16
    SDPB 4
    SDPX9B 12

Resource Utilization Summary

Resource Usage Utilization
Logic 1321(1279 LUT, 42 ALU) / 59904 3%
Register 2085 / 60780 4%
  --Register as Latch 0 / 60780 0%
  --Register as FF 2085 / 60780 4%
BSRAM 16 / 118 14%

Timing

Clock Summary:

NO. Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
1 I_clk Base 10.000 100.000 0.000 5.000 I_clk_ibuf/I
2 I_clk_half Base 10.000 100.000 0.000 5.000 I_clk_half_ibuf/I
3 I_drp_clk Base 10.000 100.000 0.000 5.000 I_drp_clk_ibuf/I

Max Frequency Summary:

NO. Clock Name Constraint Actual Fmax Logic Level Entity
1 I_clk 100.000(MHz) 214.420(MHz) 5 TOP
2 I_clk_half 100.000(MHz) 214.420(MHz) 5 TOP
3 I_drp_clk 100.000(MHz) 213.961(MHz) 5 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack 5.326
Data Arrival Time 4.737
Data Required Time 10.064
From sdi_decoder_wrapper_inst/rx_link_rate_change_inst/locked_cnt_11_s0
To sdi_decoder_wrapper_inst/rx_link_rate_change_inst/locked_cnt_31_s0
Launch Clk I_drp_clk[R]
Latch Clk I_drp_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 I_drp_clk
0.000 0.000 tCL RR 1 I_drp_clk_ibuf/I
0.000 0.000 tINS RR 103 I_drp_clk_ibuf/O
0.375 0.375 tNET RR 1 sdi_decoder_wrapper_inst/rx_link_rate_change_inst/locked_cnt_11_s0/CLK
0.757 0.382 tC2Q RR 2 sdi_decoder_wrapper_inst/rx_link_rate_change_inst/locked_cnt_11_s0/Q
1.132 0.375 tNET RR 1 sdi_decoder_wrapper_inst/rx_link_rate_change_inst/n7_s97/I0
1.659 0.526 tINS RR 1 sdi_decoder_wrapper_inst/rx_link_rate_change_inst/n7_s97/F
2.034 0.375 tNET RR 1 sdi_decoder_wrapper_inst/rx_link_rate_change_inst/n7_s94/I0
2.560 0.526 tINS RR 1 sdi_decoder_wrapper_inst/rx_link_rate_change_inst/n7_s94/F
2.935 0.375 tNET RR 1 sdi_decoder_wrapper_inst/rx_link_rate_change_inst/n7_s91/I0
3.461 0.526 tINS RR 2 sdi_decoder_wrapper_inst/rx_link_rate_change_inst/n7_s91/F
3.836 0.375 tNET RR 1 sdi_decoder_wrapper_inst/rx_link_rate_change_inst/n7_s90/I0
4.362 0.526 tINS RR 32 sdi_decoder_wrapper_inst/rx_link_rate_change_inst/n7_s90/F
4.737 0.375 tNET RR 1 sdi_decoder_wrapper_inst/rx_link_rate_change_inst/locked_cnt_31_s0/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 I_drp_clk
10.000 0.000 tCL RR 1 I_drp_clk_ibuf/I
10.000 0.000 tINS RR 103 I_drp_clk_ibuf/O
10.375 0.375 tNET RR 1 sdi_decoder_wrapper_inst/rx_link_rate_change_inst/locked_cnt_31_s0/CLK
10.064 -0.311 tSu 1 sdi_decoder_wrapper_inst/rx_link_rate_change_inst/locked_cnt_31_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%
Arrival Data Path Delay: cell: 2.105, 48.252%; route: 1.875, 42.980%; tC2Q: 0.382, 8.768%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%

Path 2

Path Summary:
Slack 5.326
Data Arrival Time 4.737
Data Required Time 10.064
From sdi_decoder_wrapper_inst/rx_link_rate_change_inst/locked_cnt_11_s0
To sdi_decoder_wrapper_inst/rx_link_rate_change_inst/locked_cnt_0_s0
Launch Clk I_drp_clk[R]
Latch Clk I_drp_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 I_drp_clk
0.000 0.000 tCL RR 1 I_drp_clk_ibuf/I
0.000 0.000 tINS RR 103 I_drp_clk_ibuf/O
0.375 0.375 tNET RR 1 sdi_decoder_wrapper_inst/rx_link_rate_change_inst/locked_cnt_11_s0/CLK
0.757 0.382 tC2Q RR 2 sdi_decoder_wrapper_inst/rx_link_rate_change_inst/locked_cnt_11_s0/Q
1.132 0.375 tNET RR 1 sdi_decoder_wrapper_inst/rx_link_rate_change_inst/n7_s97/I0
1.659 0.526 tINS RR 1 sdi_decoder_wrapper_inst/rx_link_rate_change_inst/n7_s97/F
2.034 0.375 tNET RR 1 sdi_decoder_wrapper_inst/rx_link_rate_change_inst/n7_s94/I0
2.560 0.526 tINS RR 1 sdi_decoder_wrapper_inst/rx_link_rate_change_inst/n7_s94/F
2.935 0.375 tNET RR 1 sdi_decoder_wrapper_inst/rx_link_rate_change_inst/n7_s91/I0
3.461 0.526 tINS RR 2 sdi_decoder_wrapper_inst/rx_link_rate_change_inst/n7_s91/F
3.836 0.375 tNET RR 1 sdi_decoder_wrapper_inst/rx_link_rate_change_inst/n7_s90/I0
4.362 0.526 tINS RR 32 sdi_decoder_wrapper_inst/rx_link_rate_change_inst/n7_s90/F
4.737 0.375 tNET RR 1 sdi_decoder_wrapper_inst/rx_link_rate_change_inst/locked_cnt_0_s0/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 I_drp_clk
10.000 0.000 tCL RR 1 I_drp_clk_ibuf/I
10.000 0.000 tINS RR 103 I_drp_clk_ibuf/O
10.375 0.375 tNET RR 1 sdi_decoder_wrapper_inst/rx_link_rate_change_inst/locked_cnt_0_s0/CLK
10.064 -0.311 tSu 1 sdi_decoder_wrapper_inst/rx_link_rate_change_inst/locked_cnt_0_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%
Arrival Data Path Delay: cell: 2.105, 48.252%; route: 1.875, 42.980%; tC2Q: 0.382, 8.768%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%

Path 3

Path Summary:
Slack 5.326
Data Arrival Time 4.737
Data Required Time 10.064
From sdi_decoder_wrapper_inst/rx_link_rate_change_inst/locked_cnt_11_s0
To sdi_decoder_wrapper_inst/rx_link_rate_change_inst/locked_cnt_1_s0
Launch Clk I_drp_clk[R]
Latch Clk I_drp_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 I_drp_clk
0.000 0.000 tCL RR 1 I_drp_clk_ibuf/I
0.000 0.000 tINS RR 103 I_drp_clk_ibuf/O
0.375 0.375 tNET RR 1 sdi_decoder_wrapper_inst/rx_link_rate_change_inst/locked_cnt_11_s0/CLK
0.757 0.382 tC2Q RR 2 sdi_decoder_wrapper_inst/rx_link_rate_change_inst/locked_cnt_11_s0/Q
1.132 0.375 tNET RR 1 sdi_decoder_wrapper_inst/rx_link_rate_change_inst/n7_s97/I0
1.659 0.526 tINS RR 1 sdi_decoder_wrapper_inst/rx_link_rate_change_inst/n7_s97/F
2.034 0.375 tNET RR 1 sdi_decoder_wrapper_inst/rx_link_rate_change_inst/n7_s94/I0
2.560 0.526 tINS RR 1 sdi_decoder_wrapper_inst/rx_link_rate_change_inst/n7_s94/F
2.935 0.375 tNET RR 1 sdi_decoder_wrapper_inst/rx_link_rate_change_inst/n7_s91/I0
3.461 0.526 tINS RR 2 sdi_decoder_wrapper_inst/rx_link_rate_change_inst/n7_s91/F
3.836 0.375 tNET RR 1 sdi_decoder_wrapper_inst/rx_link_rate_change_inst/n7_s90/I0
4.362 0.526 tINS RR 32 sdi_decoder_wrapper_inst/rx_link_rate_change_inst/n7_s90/F
4.737 0.375 tNET RR 1 sdi_decoder_wrapper_inst/rx_link_rate_change_inst/locked_cnt_1_s0/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 I_drp_clk
10.000 0.000 tCL RR 1 I_drp_clk_ibuf/I
10.000 0.000 tINS RR 103 I_drp_clk_ibuf/O
10.375 0.375 tNET RR 1 sdi_decoder_wrapper_inst/rx_link_rate_change_inst/locked_cnt_1_s0/CLK
10.064 -0.311 tSu 1 sdi_decoder_wrapper_inst/rx_link_rate_change_inst/locked_cnt_1_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%
Arrival Data Path Delay: cell: 2.105, 48.252%; route: 1.875, 42.980%; tC2Q: 0.382, 8.768%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%

Path 4

Path Summary:
Slack 5.326
Data Arrival Time 4.737
Data Required Time 10.064
From sdi_decoder_wrapper_inst/rx_link_rate_change_inst/locked_cnt_11_s0
To sdi_decoder_wrapper_inst/rx_link_rate_change_inst/locked_cnt_2_s0
Launch Clk I_drp_clk[R]
Latch Clk I_drp_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 I_drp_clk
0.000 0.000 tCL RR 1 I_drp_clk_ibuf/I
0.000 0.000 tINS RR 103 I_drp_clk_ibuf/O
0.375 0.375 tNET RR 1 sdi_decoder_wrapper_inst/rx_link_rate_change_inst/locked_cnt_11_s0/CLK
0.757 0.382 tC2Q RR 2 sdi_decoder_wrapper_inst/rx_link_rate_change_inst/locked_cnt_11_s0/Q
1.132 0.375 tNET RR 1 sdi_decoder_wrapper_inst/rx_link_rate_change_inst/n7_s97/I0
1.659 0.526 tINS RR 1 sdi_decoder_wrapper_inst/rx_link_rate_change_inst/n7_s97/F
2.034 0.375 tNET RR 1 sdi_decoder_wrapper_inst/rx_link_rate_change_inst/n7_s94/I0
2.560 0.526 tINS RR 1 sdi_decoder_wrapper_inst/rx_link_rate_change_inst/n7_s94/F
2.935 0.375 tNET RR 1 sdi_decoder_wrapper_inst/rx_link_rate_change_inst/n7_s91/I0
3.461 0.526 tINS RR 2 sdi_decoder_wrapper_inst/rx_link_rate_change_inst/n7_s91/F
3.836 0.375 tNET RR 1 sdi_decoder_wrapper_inst/rx_link_rate_change_inst/n7_s90/I0
4.362 0.526 tINS RR 32 sdi_decoder_wrapper_inst/rx_link_rate_change_inst/n7_s90/F
4.737 0.375 tNET RR 1 sdi_decoder_wrapper_inst/rx_link_rate_change_inst/locked_cnt_2_s0/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 I_drp_clk
10.000 0.000 tCL RR 1 I_drp_clk_ibuf/I
10.000 0.000 tINS RR 103 I_drp_clk_ibuf/O
10.375 0.375 tNET RR 1 sdi_decoder_wrapper_inst/rx_link_rate_change_inst/locked_cnt_2_s0/CLK
10.064 -0.311 tSu 1 sdi_decoder_wrapper_inst/rx_link_rate_change_inst/locked_cnt_2_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%
Arrival Data Path Delay: cell: 2.105, 48.252%; route: 1.875, 42.980%; tC2Q: 0.382, 8.768%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%

Path 5

Path Summary:
Slack 5.326
Data Arrival Time 4.737
Data Required Time 10.064
From sdi_decoder_wrapper_inst/rx_link_rate_change_inst/locked_cnt_11_s0
To sdi_decoder_wrapper_inst/rx_link_rate_change_inst/locked_cnt_3_s0
Launch Clk I_drp_clk[R]
Latch Clk I_drp_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 I_drp_clk
0.000 0.000 tCL RR 1 I_drp_clk_ibuf/I
0.000 0.000 tINS RR 103 I_drp_clk_ibuf/O
0.375 0.375 tNET RR 1 sdi_decoder_wrapper_inst/rx_link_rate_change_inst/locked_cnt_11_s0/CLK
0.757 0.382 tC2Q RR 2 sdi_decoder_wrapper_inst/rx_link_rate_change_inst/locked_cnt_11_s0/Q
1.132 0.375 tNET RR 1 sdi_decoder_wrapper_inst/rx_link_rate_change_inst/n7_s97/I0
1.659 0.526 tINS RR 1 sdi_decoder_wrapper_inst/rx_link_rate_change_inst/n7_s97/F
2.034 0.375 tNET RR 1 sdi_decoder_wrapper_inst/rx_link_rate_change_inst/n7_s94/I0
2.560 0.526 tINS RR 1 sdi_decoder_wrapper_inst/rx_link_rate_change_inst/n7_s94/F
2.935 0.375 tNET RR 1 sdi_decoder_wrapper_inst/rx_link_rate_change_inst/n7_s91/I0
3.461 0.526 tINS RR 2 sdi_decoder_wrapper_inst/rx_link_rate_change_inst/n7_s91/F
3.836 0.375 tNET RR 1 sdi_decoder_wrapper_inst/rx_link_rate_change_inst/n7_s90/I0
4.362 0.526 tINS RR 32 sdi_decoder_wrapper_inst/rx_link_rate_change_inst/n7_s90/F
4.737 0.375 tNET RR 1 sdi_decoder_wrapper_inst/rx_link_rate_change_inst/locked_cnt_3_s0/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 I_drp_clk
10.000 0.000 tCL RR 1 I_drp_clk_ibuf/I
10.000 0.000 tINS RR 103 I_drp_clk_ibuf/O
10.375 0.375 tNET RR 1 sdi_decoder_wrapper_inst/rx_link_rate_change_inst/locked_cnt_3_s0/CLK
10.064 -0.311 tSu 1 sdi_decoder_wrapper_inst/rx_link_rate_change_inst/locked_cnt_3_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%
Arrival Data Path Delay: cell: 2.105, 48.252%; route: 1.875, 42.980%; tC2Q: 0.382, 8.768%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%