Synthesis Messages

Report Title GowinSynthesis Report
Design File E:\Gowin_Board_5at_SDI\DK_START_GW5AT-LV60PG484A_V1.1\Gowin_SDI_RefDesign_250503_t1_1080_50p_60k484_v1.1_src_audio_loop_lb_la\project\src\sdi_audio_buffer_pro\sdi_audio_buffer_fifo\temp\FIFO\fifo_define.v
E:\Gowin_Board_5at_SDI\DK_START_GW5AT-LV60PG484A_V1.1\Gowin_SDI_RefDesign_250503_t1_1080_50p_60k484_v1.1_src_audio_loop_lb_la\project\src\sdi_audio_buffer_pro\sdi_audio_buffer_fifo\temp\FIFO\fifo_parameter.v
D:\Gowin\Gowin_V1.9.12_x64\IDE\ipcore\FIFO\data\edc.v
D:\Gowin\Gowin_V1.9.12_x64\IDE\ipcore\FIFO\data\fifo.v
D:\Gowin\Gowin_V1.9.12_x64\IDE\ipcore\FIFO\data\fifo_top.v
GowinSynthesis Constraints File ---
Tool Version V1.9.12 (64-bit)
Part Number GW5AT-LV60PG484AES
Device GW5AT-60
Device Version B
Created Time Tue Aug 26 15:55:38 2025
Legal Announcement Copyright (C)2014-2025 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module sdi_audio_buffer_fifo
Synthesis Process Running parser:
    CPU time = 0h 0m 0.328s, Elapsed time = 0h 0m 0.364s, Peak memory usage = 80.016MB
Running netlist conversion:
    CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 80.016MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 80.016MB
    Optimizing Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 80.016MB
    Optimizing Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 80.016MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.006s, Peak memory usage = 80.016MB
    Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 80.016MB
    Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 80.016MB
    Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 80.016MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 80.016MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 80.016MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 80.016MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 0.14s, Elapsed time = 0h 0m 0.21s, Peak memory usage = 94.418MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.05s, Peak memory usage = 94.418MB
Generate output files:
    CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.016s, Peak memory usage = 94.418MB
Total Time and Memory Usage CPU time = 0h 0m 0.498s, Elapsed time = 0h 0m 0.662s, Peak memory usage = 94.418MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 199
I/O Buf 199
    IBUF 101
    OBUF 98
Register 60
    DFFPE 5
    DFFCE 55
LUT 43
    LUT2 8
    LUT3 15
    LUT4 20
ALU 6
    ALU 6
INV 2
    INV 2
BSRAM 3
    SDPB 3

Resource Utilization Summary

Resource Usage Utilization
Logic 51(45 LUT, 6 ALU) / 59904 <1%
Register 60 / 60780 <1%
  --Register as Latch 0 / 60780 0%
  --Register as FF 60 / 60780 <1%
BSRAM 3 / 118 3%

Timing

Clock Summary:

NO. Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
1 RdClk Base 10.000 100.000 0.000 5.000 RdClk_ibuf/I
2 WrClk Base 10.000 100.000 0.000 5.000 WrClk_ibuf/I

Max Frequency Summary:

NO. Clock Name Constraint Actual Fmax Logic Level Entity
1 RdClk 100.000(MHz) 181.901(MHz) 7 TOP
2 WrClk 100.000(MHz) 226.436(MHz) 5 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack 4.502
Data Arrival Time 5.809
Data Required Time 10.311
From fifo_inst/rbin_num_0_s0
To fifo_inst/Empty_s0
Launch Clk RdClk[R]
Latch Clk RdClk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 RdClk
0.000 0.000 tCL RR 1 RdClk_ibuf/I
0.000 0.000 tINS RR 33 RdClk_ibuf/O
0.375 0.375 tNET RR 1 fifo_inst/rbin_num_0_s0/CLK
0.757 0.382 tC2Q RR 7 fifo_inst/rbin_num_0_s0/Q
1.132 0.375 tNET RR 1 fifo_inst/rbin_num_next_2_s5/I0
1.659 0.526 tINS RR 6 fifo_inst/rbin_num_next_2_s5/F
2.034 0.375 tNET RR 1 fifo_inst/rbin_num_next_2_s3/I1
2.550 0.516 tINS RR 2 fifo_inst/rbin_num_next_2_s3/F
2.925 0.375 tNET RR 1 fifo_inst/Equal.rgraynext_2_s1/I0
3.451 0.526 tINS RR 2 fifo_inst/Equal.rgraynext_2_s1/F
3.826 0.375 tNET RR 2 fifo_inst/n536_s0/I0
4.383 0.556 tINS RF 1 fifo_inst/n536_s0/COUT
4.383 0.000 tNET FF 2 fifo_inst/n537_s0/CIN
4.433 0.050 tINS FR 1 fifo_inst/n537_s0/COUT
4.433 0.000 tNET RR 2 fifo_inst/n538_s0/CIN
4.483 0.050 tINS RR 1 fifo_inst/n538_s0/COUT
4.483 0.000 tNET RR 2 fifo_inst/n539_s0/CIN
4.533 0.050 tINS RR 1 fifo_inst/n539_s0/COUT
4.908 0.375 tNET RR 1 fifo_inst/rempty_val_s1/I0
5.434 0.526 tINS RR 1 fifo_inst/rempty_val_s1/F
5.809 0.375 tNET RR 1 fifo_inst/Empty_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 RdClk
10.000 0.000 tCL RR 1 RdClk_ibuf/I
10.000 0.000 tINS RR 33 RdClk_ibuf/O
10.375 0.375 tNET RR 1 fifo_inst/Empty_s0/CLK
10.311 -0.064 tSu 1 fifo_inst/Empty_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 7
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%
Arrival Data Path Delay: cell: 2.801, 51.553%; route: 2.250, 41.408%; tC2Q: 0.382, 7.039%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%

Path 2

Path Summary:
Slack 5.584
Data Arrival Time 4.727
Data Required Time 10.311
From fifo_inst/Full_s0
To fifo_inst/Full_s0
Launch Clk WrClk[R]
Latch Clk WrClk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 WrClk
0.000 0.000 tCL RR 1 WrClk_ibuf/I
0.000 0.000 tINS RR 33 WrClk_ibuf/O
0.375 0.375 tNET RR 1 fifo_inst/Full_s0/CLK
0.757 0.382 tC2Q RR 6 fifo_inst/Full_s0/Q
1.132 0.375 tNET RR 1 fifo_inst/Equal.wgraynext_2_s1/I0
1.659 0.526 tINS RR 10 fifo_inst/Equal.wgraynext_2_s1/F
2.034 0.375 tNET RR 1 fifo_inst/wfull_val_s4/I1
2.550 0.516 tINS RR 1 fifo_inst/wfull_val_s4/F
2.925 0.375 tNET RR 1 fifo_inst/wfull_val_s1/I0
3.451 0.526 tINS RR 1 fifo_inst/wfull_val_s1/F
3.826 0.375 tNET RR 1 fifo_inst/wfull_val_s0/I0
4.352 0.526 tINS RR 1 fifo_inst/wfull_val_s0/F
4.727 0.375 tNET RR 1 fifo_inst/Full_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 WrClk
10.000 0.000 tCL RR 1 WrClk_ibuf/I
10.000 0.000 tINS RR 33 WrClk_ibuf/O
10.375 0.375 tNET RR 1 fifo_inst/Full_s0/CLK
10.311 -0.064 tSu 1 fifo_inst/Full_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%
Arrival Data Path Delay: cell: 2.095, 48.133%; route: 1.875, 43.079%; tC2Q: 0.382, 8.788%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%

Path 3

Path Summary:
Slack 6.485
Data Arrival Time 3.826
Data Required Time 10.311
From fifo_inst/Full_s0
To fifo_inst/Equal.wbin_4_s0
Launch Clk WrClk[R]
Latch Clk WrClk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 WrClk
0.000 0.000 tCL RR 1 WrClk_ibuf/I
0.000 0.000 tINS RR 33 WrClk_ibuf/O
0.375 0.375 tNET RR 1 fifo_inst/Full_s0/CLK
0.757 0.382 tC2Q RR 6 fifo_inst/Full_s0/Q
1.132 0.375 tNET RR 1 fifo_inst/Equal.wgraynext_2_s1/I0
1.659 0.526 tINS RR 10 fifo_inst/Equal.wgraynext_2_s1/F
2.034 0.375 tNET RR 1 fifo_inst/Equal.wgraynext_5_s2/I0
2.560 0.526 tINS RR 3 fifo_inst/Equal.wgraynext_5_s2/F
2.935 0.375 tNET RR 1 fifo_inst/Equal.wbinnext_4_s3/I1
3.451 0.516 tINS RR 1 fifo_inst/Equal.wbinnext_4_s3/F
3.826 0.375 tNET RR 1 fifo_inst/Equal.wbin_4_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 WrClk
10.000 0.000 tCL RR 1 WrClk_ibuf/I
10.000 0.000 tINS RR 33 WrClk_ibuf/O
10.375 0.375 tNET RR 1 fifo_inst/Equal.wbin_4_s0/CLK
10.311 -0.064 tSu 1 fifo_inst/Equal.wbin_4_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 4
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%
Arrival Data Path Delay: cell: 1.569, 45.454%; route: 1.500, 43.463%; tC2Q: 0.382, 11.083%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%

Path 4

Path Summary:
Slack 6.485
Data Arrival Time 3.826
Data Required Time 10.311
From fifo_inst/Full_s0
To fifo_inst/Equal.wbin_5_s0
Launch Clk WrClk[R]
Latch Clk WrClk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 WrClk
0.000 0.000 tCL RR 1 WrClk_ibuf/I
0.000 0.000 tINS RR 33 WrClk_ibuf/O
0.375 0.375 tNET RR 1 fifo_inst/Full_s0/CLK
0.757 0.382 tC2Q RR 6 fifo_inst/Full_s0/Q
1.132 0.375 tNET RR 1 fifo_inst/Equal.wgraynext_2_s1/I0
1.659 0.526 tINS RR 10 fifo_inst/Equal.wgraynext_2_s1/F
2.034 0.375 tNET RR 1 fifo_inst/Equal.wgraynext_5_s2/I0
2.560 0.526 tINS RR 3 fifo_inst/Equal.wgraynext_5_s2/F
2.935 0.375 tNET RR 1 fifo_inst/Equal.wbinnext_5_s3/I1
3.451 0.516 tINS RR 1 fifo_inst/Equal.wbinnext_5_s3/F
3.826 0.375 tNET RR 1 fifo_inst/Equal.wbin_5_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 WrClk
10.000 0.000 tCL RR 1 WrClk_ibuf/I
10.000 0.000 tINS RR 33 WrClk_ibuf/O
10.375 0.375 tNET RR 1 fifo_inst/Equal.wbin_5_s0/CLK
10.311 -0.064 tSu 1 fifo_inst/Equal.wbin_5_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 4
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%
Arrival Data Path Delay: cell: 1.569, 45.454%; route: 1.500, 43.463%; tC2Q: 0.382, 11.083%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%

Path 5

Path Summary:
Slack 6.485
Data Arrival Time 3.826
Data Required Time 10.311
From fifo_inst/Full_s0
To fifo_inst/Equal.wptr_5_s0
Launch Clk WrClk[R]
Latch Clk WrClk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 WrClk
0.000 0.000 tCL RR 1 WrClk_ibuf/I
0.000 0.000 tINS RR 33 WrClk_ibuf/O
0.375 0.375 tNET RR 1 fifo_inst/Full_s0/CLK
0.757 0.382 tC2Q RR 6 fifo_inst/Full_s0/Q
1.132 0.375 tNET RR 1 fifo_inst/Equal.wgraynext_2_s1/I0
1.659 0.526 tINS RR 10 fifo_inst/Equal.wgraynext_2_s1/F
2.034 0.375 tNET RR 1 fifo_inst/Equal.wgraynext_5_s2/I0
2.560 0.526 tINS RR 3 fifo_inst/Equal.wgraynext_5_s2/F
2.935 0.375 tNET RR 1 fifo_inst/Equal.wgraynext_5_s0/I1
3.451 0.516 tINS RR 1 fifo_inst/Equal.wgraynext_5_s0/F
3.826 0.375 tNET RR 1 fifo_inst/Equal.wptr_5_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 WrClk
10.000 0.000 tCL RR 1 WrClk_ibuf/I
10.000 0.000 tINS RR 33 WrClk_ibuf/O
10.375 0.375 tNET RR 1 fifo_inst/Equal.wptr_5_s0/CLK
10.311 -0.064 tSu 1 fifo_inst/Equal.wptr_5_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 4
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%
Arrival Data Path Delay: cell: 1.569, 45.454%; route: 1.500, 43.463%; tC2Q: 0.382, 11.083%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%