Timing Messages
| Report Title | Timing Analysis Report |
| Design File | E:\Gowin_Board_5at_SDI\DK_START_GW5AT-LV60PG484A_V1.1\R\Gowin_SDI_RefDesign_250526_t1_720_60p_60k484_v1.1_audio_loop_la_ref\project\impl\gwsynthesis\dk_video.vg |
| Physical Constraints File | E:\Gowin_Board_5at_SDI\DK_START_GW5AT-LV60PG484A_V1.1\R\Gowin_SDI_RefDesign_250526_t1_720_60p_60k484_v1.1_audio_loop_la_ref\project\src\dk_video.cst |
| Timing Constraint File | E:\Gowin_Board_5at_SDI\DK_START_GW5AT-LV60PG484A_V1.1\R\Gowin_SDI_RefDesign_250526_t1_720_60p_60k484_v1.1_audio_loop_la_ref\project\src\dk_video.sdc |
| Tool Version | V1.9.12.01 (64-bit) |
| Part Number | GW5AT-LV60PG484AES |
| Device | GW5AT-60 |
| Device Version | B |
| Created Time | Tue Dec 16 10:33:59 2025 |
| Legal Announcement | Copyright (C)2014-2025 Gowin Semiconductor Corporation. All rights reserved. |
Timing Summaries
STA Tool Run Summary:
| Setup Delay Model | Slow 0.855V 0C ES |
| Hold Delay Model | Fast 0.945V 85C ES |
| Numbers of Paths Analyzed | 17177 |
| Numbers of Endpoints Analyzed | 22576 |
| Numbers of Falling Endpoints | 9 |
| Numbers of Setup Violated Endpoints | 0 |
| Numbers of Hold Violated Endpoints | 0 |
Clock Summary:
| NO. | Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Objects |
|---|---|---|---|---|---|---|---|---|---|
| 1 | sclk | Base | 20.000 | 50.000 | 0.000 | 10.000 | sclk | ||
| 2 | I_pcm2706_bclk | Base | 325.520 | 3.072 | 0.000 | 162.760 | I_pcm2706_bclk | ||
| 3 | I_audio_refclk | Base | 81.380 | 12.288 | 0.000 | 40.690 | I_audio_refclk | ||
| 4 | sdi_phy_drp_clk | Base | 10.000 | 100.000 | 0.000 | 5.000 | sdi_phy_drp_clk | ||
| 5 | sdi_phy_tx_clk | Base | 13.468 | 74.250 | 0.000 | 6.734 | sdi_phy_tx_clk | ||
| 6 | sdi_phy_rx_clk | Base | 13.468 | 74.250 | 0.000 | 6.734 | sdi_phy_rx_clk | ||
| 7 | Gowin_OSC_inst/osc_inst/OSCOUT.default_clk | Base | 47.619 | 21.000 | 0.000 | 23.810 | Gowin_OSC_inst/osc_inst/OSCOUT | ||
| 8 | I_clk_p | Base | 5.000 | 200.000 | 0.000 | 2.500 | IB_clk_inst/I | ||
| 9 | adv7513_pll_inst/u_pll/PLLA_inst/CLKOUT0.default_gen_clk | Generated | 13.468 | 74.250 | 6.734 | 0.000 | SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_RX_O_FABRIC_CLK | sdi_phy_rx_clk | adv7513_pll_inst/u_pll/PLLA_inst/CLKOUT0 |
| 10 | i2s_clkdiv4_inst0/clkdiv_inst/CLKOUT.default_gen_clk | Generated | 325.520 | 3.072 | 0.000 | 162.760 | I_audio_refclk_ibuf/I | I_audio_refclk | i2s_clkdiv4_inst0/clkdiv_inst/CLKOUT |
Max Frequency Summary:
| NO. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
|---|---|---|---|---|---|
| 1 | sclk | 50.000(MHz) | 180.302(MHz) | 6 | TOP |
| 2 | sdi_phy_drp_clk | 100.000(MHz) | 120.581(MHz) | 3 | TOP |
| 3 | sdi_phy_tx_clk | 74.250(MHz) | 120.563(MHz) | 13 | TOP |
| 4 | sdi_phy_rx_clk | 74.250(MHz) | 161.355(MHz) | 10 | TOP |
| 5 | Gowin_OSC_inst/osc_inst/OSCOUT.default_clk | 21.000(MHz) | 118.072(MHz) | 7 | TOP |
| 6 | i2s_clkdiv4_inst0/clkdiv_inst/CLKOUT.default_gen_clk | 3.072(MHz) | 235.917(MHz) | 7 | TOP |
No timing paths to get frequency of I_pcm2706_bclk!
No timing paths to get frequency of I_audio_refclk!
No timing paths to get frequency of I_clk_p!
No timing paths to get frequency of adv7513_pll_inst/u_pll/PLLA_inst/CLKOUT0.default_gen_clk!
Total Negative Slack Summary:
| Clock Name | Analysis Type | Endpoints TNS | Number of Endpoints |
|---|---|---|---|
| sclk | Setup | 0.000 | 0 |
| sclk | Hold | 0.000 | 0 |
| I_pcm2706_bclk | Setup | 0.000 | 0 |
| I_pcm2706_bclk | Hold | 0.000 | 0 |
| I_audio_refclk | Setup | 0.000 | 0 |
| I_audio_refclk | Hold | 0.000 | 0 |
| sdi_phy_drp_clk | Setup | 0.000 | 0 |
| sdi_phy_drp_clk | Hold | 0.000 | 0 |
| sdi_phy_tx_clk | Setup | 0.000 | 0 |
| sdi_phy_tx_clk | Hold | 0.000 | 0 |
| sdi_phy_rx_clk | Setup | 0.000 | 0 |
| sdi_phy_rx_clk | Hold | 0.000 | 0 |
| Gowin_OSC_inst/osc_inst/OSCOUT.default_clk | Setup | 0.000 | 0 |
| Gowin_OSC_inst/osc_inst/OSCOUT.default_clk | Hold | 0.000 | 0 |
| I_clk_p | Setup | 0.000 | 0 |
| I_clk_p | Hold | 0.000 | 0 |
| adv7513_pll_inst/u_pll/PLLA_inst/CLKOUT0.default_gen_clk | Setup | 0.000 | 0 |
| adv7513_pll_inst/u_pll/PLLA_inst/CLKOUT0.default_gen_clk | Hold | 0.000 | 0 |
| i2s_clkdiv4_inst0/clkdiv_inst/CLKOUT.default_gen_clk | Setup | 0.000 | 0 |
| i2s_clkdiv4_inst0/clkdiv_inst/CLKOUT.default_gen_clk | Hold | 0.000 | 0 |
Timing Details
Path Slacks Table:
Setup Paths Table
Report Command:report_timing -setup -max_paths 25 -max_common_paths 1
| Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
|---|---|---|---|---|---|---|---|---|
| 1 | 1.707 | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wren_o_s1/Q | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_addr_o_11_s1/CE | sdi_phy_drp_clk:[R] | sdi_phy_drp_clk:[R] | 10.000 | -0.019 | 8.001 |
| 2 | 1.771 | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wren_o_s1/Q | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_addr_o_9_s1/CE | sdi_phy_drp_clk:[R] | sdi_phy_drp_clk:[R] | 10.000 | 0.000 | 7.918 |
| 3 | 1.887 | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wren_o_s1/Q | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_addr_o_10_s1/CE | sdi_phy_drp_clk:[R] | sdi_phy_drp_clk:[R] | 10.000 | -0.009 | 7.811 |
| 4 | 1.996 | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wren_o_s1/Q | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_addr_o_13_s1/CE | sdi_phy_drp_clk:[R] | sdi_phy_drp_clk:[R] | 10.000 | 0.000 | 7.693 |
| 5 | 1.996 | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wren_o_s1/Q | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_addr_o_14_s1/CE | sdi_phy_drp_clk:[R] | sdi_phy_drp_clk:[R] | 10.000 | 0.000 | 7.693 |
| 6 | 1.996 | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wren_o_s1/Q | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_addr_o_16_s1/CE | sdi_phy_drp_clk:[R] | sdi_phy_drp_clk:[R] | 10.000 | 0.000 | 7.693 |
| 7 | 1.996 | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wren_o_s1/Q | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_addr_o_19_s1/CE | sdi_phy_drp_clk:[R] | sdi_phy_drp_clk:[R] | 10.000 | 0.000 | 7.693 |
| 8 | 1.996 | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wren_o_s1/Q | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_addr_o_23_s1/CE | sdi_phy_drp_clk:[R] | sdi_phy_drp_clk:[R] | 10.000 | 0.000 | 7.693 |
| 9 | 2.124 | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wren_o_s1/Q | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_addr_o_6_s1/CE | sdi_phy_drp_clk:[R] | sdi_phy_drp_clk:[R] | 10.000 | -0.019 | 7.583 |
| 10 | 2.124 | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wren_o_s1/Q | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_addr_o_12_s1/CE | sdi_phy_drp_clk:[R] | sdi_phy_drp_clk:[R] | 10.000 | -0.019 | 7.583 |
| 11 | 2.131 | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wren_o_s1/Q | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wren_o_s1/CE | sdi_phy_drp_clk:[R] | sdi_phy_drp_clk:[R] | 10.000 | 0.000 | 7.558 |
| 12 | 2.197 | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wren_o_s1/Q | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_addr_o_17_s1/CE | sdi_phy_drp_clk:[R] | sdi_phy_drp_clk:[R] | 10.000 | -0.009 | 7.501 |
| 13 | 2.222 | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wren_o_s1/Q | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wrdata_o_0_s1/CE | sdi_phy_drp_clk:[R] | sdi_phy_drp_clk:[R] | 10.000 | 0.000 | 7.466 |
| 14 | 2.383 | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wren_o_s1/Q | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_addr_o_20_s1/CE | sdi_phy_drp_clk:[R] | sdi_phy_drp_clk:[R] | 10.000 | 0.000 | 7.306 |
| 15 | 2.433 | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wren_o_s1/Q | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_strb_o_2_s1/CE | sdi_phy_drp_clk:[R] | sdi_phy_drp_clk:[R] | 10.000 | 0.000 | 7.256 |
| 16 | 2.433 | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wren_o_s1/Q | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_strb_o_3_s1/CE | sdi_phy_drp_clk:[R] | sdi_phy_drp_clk:[R] | 10.000 | 0.000 | 7.256 |
| 17 | 2.433 | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wren_o_s1/Q | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_strb_o_4_s1/CE | sdi_phy_drp_clk:[R] | sdi_phy_drp_clk:[R] | 10.000 | 0.000 | 7.256 |
| 18 | 2.433 | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wren_o_s1/Q | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wrdata_o_5_s1/CE | sdi_phy_drp_clk:[R] | sdi_phy_drp_clk:[R] | 10.000 | 0.000 | 7.256 |
| 19 | 2.433 | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wren_o_s1/Q | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wrdata_o_30_s1/CE | sdi_phy_drp_clk:[R] | sdi_phy_drp_clk:[R] | 10.000 | 0.000 | 7.256 |
| 20 | 2.433 | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wren_o_s1/Q | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wrdata_o_31_s1/CE | sdi_phy_drp_clk:[R] | sdi_phy_drp_clk:[R] | 10.000 | 0.000 | 7.256 |
| 21 | 2.442 | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wren_o_s1/Q | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_strb_o_5_s1/CE | sdi_phy_drp_clk:[R] | sdi_phy_drp_clk:[R] | 10.000 | -0.009 | 7.256 |
| 22 | 2.442 | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wren_o_s1/Q | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wrdata_o_19_s1/CE | sdi_phy_drp_clk:[R] | sdi_phy_drp_clk:[R] | 10.000 | -0.009 | 7.256 |
| 23 | 2.442 | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wren_o_s1/Q | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wrdata_o_20_s1/CE | sdi_phy_drp_clk:[R] | sdi_phy_drp_clk:[R] | 10.000 | -0.009 | 7.256 |
| 24 | 2.649 | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wren_o_s1/Q | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wrdata_o_25_s1/CE | sdi_phy_drp_clk:[R] | sdi_phy_drp_clk:[R] | 10.000 | -0.019 | 7.058 |
| 25 | 2.777 | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wren_o_s1/Q | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_addr_o_0_s1/CE | sdi_phy_drp_clk:[R] | sdi_phy_drp_clk:[R] | 10.000 | -0.009 | 6.921 |
Hold Paths Table
Report Command:report_timing -hold -max_paths 25 -max_common_paths 1
| Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
|---|---|---|---|---|---|---|---|---|
| 1 | 0.007 | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_hd_level_b_dl_wrapper_inst/rx_hd_type2_to_type1_inst/datas2_d1_3_s0/Q | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_hd_level_b_dl_wrapper_inst/rx_hd_type2_to_type1_inst/rx_hd_lbdl_sdpb_even_inst0/sdpx9b_inst_2/DI[3] | sdi_phy_rx_clk:[R] | sdi_phy_rx_clk:[R] | 0.000 | -0.197 | 0.241 |
| 2 | 0.007 | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_level_datastream_inst/tx_hd_level_b_dl_sdpb_pro_inst/rd_addr_5_s1/Q | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_level_datastream_inst/tx_hd_level_b_dl_sdpb_pro_inst/tx_hd_lbdl_sdpb_inst0/sdpx9b_inst_1/ADB[8] | sdi_phy_tx_clk:[R] | sdi_phy_tx_clk:[R] | 0.000 | -0.201 | 0.243 |
| 3 | 0.007 | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_hd_level_b_dl_wrapper_inst/rx_hd_type2_to_type1_inst/datas2_d2_6_s0/Q | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_hd_level_b_dl_wrapper_inst/rx_hd_type2_to_type1_inst/rx_hd_lbdl_sdpb_even_inst0/sdpx9b_inst_3/DI[7] | sdi_phy_rx_clk:[R] | sdi_phy_rx_clk:[R] | 0.000 | -0.197 | 0.241 |
| 4 | 0.007 | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_hd_level_b_dl_wrapper_inst/rx_hd_type2_to_type1_inst/datas1_d2_4_s0/Q | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_hd_level_b_dl_wrapper_inst/rx_hd_type2_to_type1_inst/rx_hd_lbdl_sdpb_odd_inst0/sdpx9b_inst_4/DI[5] | sdi_phy_rx_clk:[R] | sdi_phy_rx_clk:[R] | 0.000 | -0.197 | 0.241 |
| 5 | 0.007 | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_hd_level_b_dl_wrapper_inst/rx_hd_type2_to_type1_inst/datas1_d2_2_s0/Q | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_hd_level_b_dl_wrapper_inst/rx_hd_type2_to_type1_inst/rx_hd_lbdl_sdpb_odd_inst0/sdpx9b_inst_4/DI[3] | sdi_phy_rx_clk:[R] | sdi_phy_rx_clk:[R] | 0.000 | -0.197 | 0.241 |
| 6 | 0.010 | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_level_datastream_inst/tx_hd_level_b_dl_sdpb_pro_inst/rd_addr_4_s1/Q | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_level_datastream_inst/tx_hd_level_b_dl_sdpb_pro_inst/tx_hd_lbdl_sdpb_inst0/sdpx9b_inst_1/ADB[7] | sdi_phy_tx_clk:[R] | sdi_phy_tx_clk:[R] | 0.000 | -0.201 | 0.246 |
| 7 | 0.027 | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_hd_level_b_dl_wrapper_inst/rx_hd_type2_to_type1_inst/datas1_d2_3_s0/Q | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_hd_level_b_dl_wrapper_inst/rx_hd_type2_to_type1_inst/rx_hd_lbdl_sdpb_odd_inst0/sdpx9b_inst_4/DI[4] | sdi_phy_rx_clk:[R] | sdi_phy_rx_clk:[R] | 0.000 | -0.197 | 0.261 |
| 8 | 0.027 | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_hd_level_b_dl_wrapper_inst/rx_hd_type2_to_type1_inst/datas1_d2_0_s0/Q | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_hd_level_b_dl_wrapper_inst/rx_hd_type2_to_type1_inst/rx_hd_lbdl_sdpb_odd_inst0/sdpx9b_inst_4/DI[1] | sdi_phy_rx_clk:[R] | sdi_phy_rx_clk:[R] | 0.000 | -0.197 | 0.261 |
| 9 | 0.030 | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_hd_level_b_dl_wrapper_inst/rx_hd_type2_to_type1_inst/datas2_d2_3_s0/Q | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_hd_level_b_dl_wrapper_inst/rx_hd_type2_to_type1_inst/rx_hd_lbdl_sdpb_even_inst0/sdpx9b_inst_3/DI[4] | sdi_phy_rx_clk:[R] | sdi_phy_rx_clk:[R] | 0.000 | -0.197 | 0.264 |
| 10 | 0.030 | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_hd_level_b_dl_wrapper_inst/rx_hd_type2_to_type1_inst/datas2_d2_2_s0/Q | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_hd_level_b_dl_wrapper_inst/rx_hd_type2_to_type1_inst/rx_hd_lbdl_sdpb_even_inst0/sdpx9b_inst_3/DI[3] | sdi_phy_rx_clk:[R] | sdi_phy_rx_clk:[R] | 0.000 | -0.197 | 0.264 |
| 11 | 0.030 | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_hd_level_b_dl_wrapper_inst/rx_hd_type2_to_type1_inst/datas2_d2_0_s0/Q | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_hd_level_b_dl_wrapper_inst/rx_hd_type2_to_type1_inst/rx_hd_lbdl_sdpb_even_inst0/sdpx9b_inst_3/DI[1] | sdi_phy_rx_clk:[R] | sdi_phy_rx_clk:[R] | 0.000 | -0.197 | 0.264 |
| 12 | 0.030 | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_hd_level_b_dl_wrapper_inst/rx_hd_type2_to_type1_inst/datas1_d2_5_s0/Q | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_hd_level_b_dl_wrapper_inst/rx_hd_type2_to_type1_inst/rx_hd_lbdl_sdpb_odd_inst0/sdpx9b_inst_4/DI[6] | sdi_phy_rx_clk:[R] | sdi_phy_rx_clk:[R] | 0.000 | -0.197 | 0.264 |
| 13 | 0.030 | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_hd_level_b_dl_wrapper_inst/rx_hd_type2_to_type1_inst/datas1_d2_1_s0/Q | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_hd_level_b_dl_wrapper_inst/rx_hd_type2_to_type1_inst/rx_hd_lbdl_sdpb_odd_inst0/sdpx9b_inst_4/DI[2] | sdi_phy_rx_clk:[R] | sdi_phy_rx_clk:[R] | 0.000 | -0.197 | 0.264 |
| 14 | 0.033 | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_hd_level_b_dl_wrapper_inst/rx_hd_type2_to_type1_inst/datas2_d1_0_s0/Q | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_hd_level_b_dl_wrapper_inst/rx_hd_type2_to_type1_inst/rx_hd_lbdl_sdpb_even_inst0/sdpx9b_inst_2/DI[0] | sdi_phy_rx_clk:[R] | sdi_phy_rx_clk:[R] | 0.000 | -0.197 | 0.267 |
| 15 | 0.070 | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_hd_level_b_dl_wrapper_inst/rx_hd_type2_to_type1_inst/datas1_d1_2_s0/Q | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_hd_level_b_dl_wrapper_inst/rx_hd_type2_to_type1_inst/rx_hd_lbdl_sdpb_odd_inst0/sdpx9b_inst_2/DI[2] | sdi_phy_rx_clk:[R] | sdi_phy_rx_clk:[R] | 0.000 | -0.201 | 0.308 |
| 16 | 0.070 | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_hd_level_b_dl_wrapper_inst/rx_hd_type2_to_type1_inst/datas2_d1_2_s0/Q | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_hd_level_b_dl_wrapper_inst/rx_hd_type2_to_type1_inst/rx_hd_lbdl_sdpb_even_inst0/sdpx9b_inst_2/DI[2] | sdi_phy_rx_clk:[R] | sdi_phy_rx_clk:[R] | 0.000 | -0.201 | 0.308 |
| 17 | 0.084 | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_level_datastream_inst/tx_hd_level_b_dl_sdpb_pro_inst/wr_addr_5_s0/Q | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_level_datastream_inst/tx_hd_level_b_dl_sdpb_pro_inst/tx_hd_lbdl_sdpb_inst1/sdpx9b_inst_4/ADA[8] | sdi_phy_tx_clk:[R] | sdi_phy_tx_clk:[R] | 0.000 | -0.197 | 0.318 |
| 18 | 0.097 | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_level_datastream_inst/tx_hd_level_b_dl_sdpb_pro_inst/rd_addr_0_s3/Q | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_level_datastream_inst/tx_hd_level_b_dl_sdpb_pro_inst/tx_hd_lbdl_sdpb_inst1/sdpx9b_inst_0/ADB[3] | sdi_phy_tx_clk:[R] | sdi_phy_tx_clk:[R] | 0.000 | -0.205 | 0.337 |
| 19 | 0.103 | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_level_datastream_inst/tx_hd_level_b_dl_sdpb_pro_inst/datas2_d1_6_s0/Q | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_level_datastream_inst/tx_hd_level_b_dl_sdpb_pro_inst/tx_hd_lbdl_sdpb_inst1/sdpx9b_inst_4/DI[7] | sdi_phy_tx_clk:[R] | sdi_phy_tx_clk:[R] | 0.000 | -0.193 | 0.333 |
| 20 | 0.105 | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_hd_level_b_dl_wrapper_inst/rx_hd_type2_to_type1_inst/datas1_d1_5_s0/Q | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_hd_level_b_dl_wrapper_inst/rx_hd_type2_to_type1_inst/rx_hd_lbdl_sdpb_odd_inst0/sdpx9b_inst_2/DI[5] | sdi_phy_rx_clk:[R] | sdi_phy_rx_clk:[R] | 0.000 | -0.201 | 0.343 |
| 21 | 0.106 | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_level_datastream_inst/tx_hd_level_b_dl_sdpb_pro_inst/wr_addr_4_s0/Q | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_level_datastream_inst/tx_hd_level_b_dl_sdpb_pro_inst/tx_hd_lbdl_sdpb_inst1/sdpx9b_inst_4/ADA[7] | sdi_phy_tx_clk:[R] | sdi_phy_tx_clk:[R] | 0.000 | -0.197 | 0.340 |
| 22 | 0.107 | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_level_datastream_inst/tx_hd_level_b_dl_sdpb_pro_inst/rd_addr_1_s1/Q | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_level_datastream_inst/tx_hd_level_b_dl_sdpb_pro_inst/tx_hd_lbdl_sdpb_inst0/sdpx9b_inst_1/ADB[4] | sdi_phy_tx_clk:[R] | sdi_phy_tx_clk:[R] | 0.000 | -0.201 | 0.343 |
| 23 | 0.108 | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_level_datastream_inst/tx_hd_level_b_dl_sdpb_pro_inst/rd_addr_7_s1/Q | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_level_datastream_inst/tx_hd_level_b_dl_sdpb_pro_inst/tx_hd_lbdl_sdpb_inst1/sdpx9b_inst_0/ADB[10] | sdi_phy_tx_clk:[R] | sdi_phy_tx_clk:[R] | 0.000 | -0.201 | 0.344 |
| 24 | 0.109 | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_hd_level_b_dl_wrapper_inst/rx_hd_type2_to_type1_inst/datas1_d1_5_s0/Q | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_hd_level_b_dl_wrapper_inst/rx_hd_type2_to_type1_inst/rx_hd_lbdl_sdpb_odd_inst0/sdpx9b_inst_1/DI[5] | sdi_phy_rx_clk:[R] | sdi_phy_rx_clk:[R] | 0.000 | -0.197 | 0.343 |
| 25 | 0.114 | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_hd_level_b_dl_wrapper_inst/rx_hd_type2_to_type1_inst/datas1_d1_2_s0/Q | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_hd_level_b_dl_wrapper_inst/rx_hd_type2_to_type1_inst/rx_hd_lbdl_sdpb_odd_inst0/sdpx9b_inst_0/DI[2] | sdi_phy_rx_clk:[R] | sdi_phy_rx_clk:[R] | 0.000 | -0.197 | 0.348 |
Recovery Paths Table
Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1
| Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
|---|---|---|---|---|---|---|---|---|
| 1 | 4.827 | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_add_audio_inst/tx_hd_audio_data_wrapper_inst/tx_hd_audio_data_store_inst/fifo_rest_s0/Q | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_add_audio_inst/tx_hd_audio_data_wrapper_inst/tx_hd_audio_data_store_inst/tx_hd_audio_fifo_data/reset_w_1_s0/PRESET | sdi_phy_tx_clk:[R] | sdi_phy_tx_clk:[F] | 6.734 | 0.001 | 1.614 |
| 2 | 4.958 | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_add_audio_inst/tx_hd_audio_data_wrapper_inst/tx_hd_audio_data_store_inst/fifo_rest_s0/Q | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_add_audio_inst/tx_hd_audio_data_wrapper_inst/tx_hd_audio_data_store_inst/tx_hd_audio_fifo_data/reset_r_0_s0/PRESET | sdi_phy_tx_clk:[R] | sdi_phy_tx_clk:[F] | 6.734 | 0.011 | 1.472 |
| 3 | 4.977 | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_add_audio_inst/tx_hd_audio_data_wrapper_inst/tx_hd_audio_data_store_inst/fifo_rest_s0/Q | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_add_audio_inst/tx_hd_audio_data_wrapper_inst/tx_hd_audio_data_store_inst/tx_hd_audio_fifo_data/gowin_replicate_reg_reset_w[1]_1/PRESET | sdi_phy_tx_clk:[R] | sdi_phy_tx_clk:[F] | 6.734 | -0.008 | 1.472 |
| 4 | 10.160 | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s0/Q | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst4/crc_r_6_s0/CLEAR | sdi_phy_tx_clk:[R] | sdi_phy_tx_clk:[R] | 13.468 | 0.009 | 2.951 |
| 5 | 10.160 | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s0/Q | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst4/crc_r_7_s0/CLEAR | sdi_phy_tx_clk:[R] | sdi_phy_tx_clk:[R] | 13.468 | 0.009 | 2.951 |
| 6 | 10.160 | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s0/Q | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst4/crc_r_10_s0/CLEAR | sdi_phy_tx_clk:[R] | sdi_phy_tx_clk:[R] | 13.468 | 0.009 | 2.951 |
| 7 | 10.160 | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s0/Q | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst4/crc_r_11_s0/CLEAR | sdi_phy_tx_clk:[R] | sdi_phy_tx_clk:[R] | 13.468 | 0.009 | 2.951 |
| 8 | 10.169 | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s0/Q | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst4/crc_r_0_s0/CLEAR | sdi_phy_tx_clk:[R] | sdi_phy_tx_clk:[R] | 13.468 | 0.000 | 2.951 |
| 9 | 10.169 | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s0/Q | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst4/crc_r_4_s0/CLEAR | sdi_phy_tx_clk:[R] | sdi_phy_tx_clk:[R] | 13.468 | 0.000 | 2.951 |
| 10 | 10.169 | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s0/Q | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst4/crc_r_5_s0/CLEAR | sdi_phy_tx_clk:[R] | sdi_phy_tx_clk:[R] | 13.468 | 0.000 | 2.951 |
| 11 | 10.169 | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s0/Q | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst4/crc_r_8_s0/CLEAR | sdi_phy_tx_clk:[R] | sdi_phy_tx_clk:[R] | 13.468 | 0.000 | 2.951 |
| 12 | 10.169 | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s0/Q | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst4/crc_r_9_s0/CLEAR | sdi_phy_tx_clk:[R] | sdi_phy_tx_clk:[R] | 13.468 | 0.000 | 2.951 |
| 13 | 5.140 | sdi_audio_buffer_pro_tx_inst/sdi_audio_buffer_fifo_inst/fifo_inst/reset_r_1_s0/Q | sdi_audio_buffer_pro_tx_inst/sdi_audio_buffer_fifo_inst/fifo_inst/gowin_add_SDPB_Equal.mem_Equal.mem_0_1_s/RESET | sdi_phy_tx_clk:[F] | sdi_phy_tx_clk:[R] | 6.734 | -0.001 | 1.515 |
| 14 | 10.356 | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s0/Q | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst3/crc_r_17_s0/CLEAR | sdi_phy_tx_clk:[R] | sdi_phy_tx_clk:[R] | 13.468 | 0.000 | 2.765 |
| 15 | 10.356 | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s0/Q | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst3/crc_r_1_s0/CLEAR | sdi_phy_tx_clk:[R] | sdi_phy_tx_clk:[R] | 13.468 | 0.000 | 2.765 |
| 16 | 10.356 | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s0/Q | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst3/crc_r_5_s0/CLEAR | sdi_phy_tx_clk:[R] | sdi_phy_tx_clk:[R] | 13.468 | 0.000 | 2.765 |
| 17 | 10.356 | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s0/Q | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst3/crc_r_8_s0/CLEAR | sdi_phy_tx_clk:[R] | sdi_phy_tx_clk:[R] | 13.468 | 0.000 | 2.765 |
| 18 | 10.356 | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s0/Q | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst3/crc_r_9_s0/CLEAR | sdi_phy_tx_clk:[R] | sdi_phy_tx_clk:[R] | 13.468 | 0.000 | 2.765 |
| 19 | 10.356 | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s0/Q | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst3/crc_r_11_s0/CLEAR | sdi_phy_tx_clk:[R] | sdi_phy_tx_clk:[R] | 13.468 | 0.000 | 2.765 |
| 20 | 10.356 | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s0/Q | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst3/crc_r_12_s0/CLEAR | sdi_phy_tx_clk:[R] | sdi_phy_tx_clk:[R] | 13.468 | 0.000 | 2.765 |
| 21 | 10.356 | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s0/Q | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst3/crc_r_13_s0/CLEAR | sdi_phy_tx_clk:[R] | sdi_phy_tx_clk:[R] | 13.468 | 0.000 | 2.765 |
| 22 | 10.356 | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s0/Q | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst3/crc_r_14_s0/CLEAR | sdi_phy_tx_clk:[R] | sdi_phy_tx_clk:[R] | 13.468 | 0.000 | 2.765 |
| 23 | 5.185 | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_add_audio_inst/tx_hd_audio_data_wrapper_inst/tx_hd_audio_data_store_inst/tx_hd_audio_fifo_data/reset_w_1_s0/Q | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_add_audio_inst/tx_hd_audio_data_wrapper_inst/tx_hd_audio_data_store_inst/tx_hd_audio_fifo_data/raddr_num_dly_1_s0/CLEAR | sdi_phy_tx_clk:[F] | sdi_phy_tx_clk:[R] | 6.734 | -0.011 | 1.212 |
| 24 | 5.185 | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_add_audio_inst/tx_hd_audio_data_wrapper_inst/tx_hd_audio_data_store_inst/tx_hd_audio_fifo_data/reset_w_1_s0/Q | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_add_audio_inst/tx_hd_audio_data_wrapper_inst/tx_hd_audio_data_store_inst/tx_hd_audio_fifo_data/raddr_num_dly_2_s0/CLEAR | sdi_phy_tx_clk:[F] | sdi_phy_tx_clk:[R] | 6.734 | -0.011 | 1.212 |
| 25 | 10.389 | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s0/Q | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst4/crc_r_17_s0/CLEAR | sdi_phy_tx_clk:[R] | sdi_phy_tx_clk:[R] | 13.468 | -0.009 | 2.741 |
Removal Paths Table
Report Command:report_timing -removal -max_paths 25 -max_common_paths 1
| Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
|---|---|---|---|---|---|---|---|---|
| 1 | 0.705 | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s0/Q | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst2/crc_r_9_s0/CLEAR | sdi_phy_tx_clk:[R] | sdi_phy_tx_clk:[R] | 0.000 | -0.004 | 0.656 |
| 2 | 0.705 | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s0/Q | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst2/crc_r_14_s0/CLEAR | sdi_phy_tx_clk:[R] | sdi_phy_tx_clk:[R] | 0.000 | -0.004 | 0.656 |
| 3 | 0.713 | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s0/Q | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst2/crc_r_5_s0/CLEAR | sdi_phy_tx_clk:[R] | sdi_phy_tx_clk:[R] | 0.000 | -0.004 | 0.664 |
| 4 | 0.713 | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s0/Q | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst2/crc_r_15_s0/CLEAR | sdi_phy_tx_clk:[R] | sdi_phy_tx_clk:[R] | 0.000 | -0.004 | 0.664 |
| 5 | 0.713 | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s0/Q | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst2/crc_r_16_s0/CLEAR | sdi_phy_tx_clk:[R] | sdi_phy_tx_clk:[R] | 0.000 | -0.004 | 0.664 |
| 6 | 0.717 | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s0/Q | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst2/crc_r_6_s0/CLEAR | sdi_phy_tx_clk:[R] | sdi_phy_tx_clk:[R] | 0.000 | 0.000 | 0.664 |
| 7 | 0.717 | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s0/Q | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst2/crc_r_7_s0/CLEAR | sdi_phy_tx_clk:[R] | sdi_phy_tx_clk:[R] | 0.000 | 0.000 | 0.664 |
| 8 | 0.717 | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s0/Q | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst2/crc_r_10_s0/CLEAR | sdi_phy_tx_clk:[R] | sdi_phy_tx_clk:[R] | 0.000 | 0.000 | 0.664 |
| 9 | 0.717 | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s0/Q | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst2/crc_r_11_s0/CLEAR | sdi_phy_tx_clk:[R] | sdi_phy_tx_clk:[R] | 0.000 | 0.000 | 0.664 |
| 10 | 0.721 | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s0/Q | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst2/crc_r_17_s0/CLEAR | sdi_phy_tx_clk:[R] | sdi_phy_tx_clk:[R] | 0.000 | 0.000 | 0.668 |
| 11 | 0.721 | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s0/Q | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst2/crc_r_1_s0/CLEAR | sdi_phy_tx_clk:[R] | sdi_phy_tx_clk:[R] | 0.000 | 0.000 | 0.668 |
| 12 | 0.721 | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s0/Q | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst2/crc_r_2_s0/CLEAR | sdi_phy_tx_clk:[R] | sdi_phy_tx_clk:[R] | 0.000 | 0.000 | 0.668 |
| 13 | 0.811 | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s0/Q | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst2/crc_r_0_s0/CLEAR | sdi_phy_tx_clk:[R] | sdi_phy_tx_clk:[R] | 0.000 | 0.000 | 0.758 |
| 14 | 0.811 | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s0/Q | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst2/crc_r_3_s0/CLEAR | sdi_phy_tx_clk:[R] | sdi_phy_tx_clk:[R] | 0.000 | 0.000 | 0.758 |
| 15 | 0.811 | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s0/Q | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst2/crc_r_4_s0/CLEAR | sdi_phy_tx_clk:[R] | sdi_phy_tx_clk:[R] | 0.000 | 0.000 | 0.758 |
| 16 | 0.811 | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s0/Q | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst2/crc_r_8_s0/CLEAR | sdi_phy_tx_clk:[R] | sdi_phy_tx_clk:[R] | 0.000 | 0.000 | 0.758 |
| 17 | 0.811 | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s0/Q | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst2/crc_r_12_s0/CLEAR | sdi_phy_tx_clk:[R] | sdi_phy_tx_clk:[R] | 0.000 | 0.000 | 0.758 |
| 18 | 0.811 | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s0/Q | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst2/crc_r_13_s0/CLEAR | sdi_phy_tx_clk:[R] | sdi_phy_tx_clk:[R] | 0.000 | 0.000 | 0.758 |
| 19 | 1.097 | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/rstn_s0/Q | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wrdata_o_1_s1/CLEAR | sdi_phy_drp_clk:[R] | sdi_phy_drp_clk:[R] | 0.000 | 0.000 | 1.044 |
| 20 | 1.097 | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/rstn_s0/Q | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wrdata_o_6_s1/CLEAR | sdi_phy_drp_clk:[R] | sdi_phy_drp_clk:[R] | 0.000 | 0.000 | 1.044 |
| 21 | 1.097 | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/rstn_s0/Q | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wrdata_o_7_s1/CLEAR | sdi_phy_drp_clk:[R] | sdi_phy_drp_clk:[R] | 0.000 | 0.000 | 1.044 |
| 22 | 1.111 | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/rstn_s0/Q | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wren_o_s1/CLEAR | sdi_phy_drp_clk:[R] | sdi_phy_drp_clk:[R] | 0.000 | 0.004 | 1.054 |
| 23 | 1.111 | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/rstn_s0/Q | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wrdata_o_15_s1/CLEAR | sdi_phy_drp_clk:[R] | sdi_phy_drp_clk:[R] | 0.000 | -0.004 | 1.062 |
| 24 | 1.111 | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/rstn_s0/Q | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wrdata_o_25_s1/CLEAR | sdi_phy_drp_clk:[R] | sdi_phy_drp_clk:[R] | 0.000 | -0.004 | 1.062 |
| 25 | 1.111 | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/rstn_s0/Q | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_addr_o_11_s1/CLEAR | sdi_phy_drp_clk:[R] | sdi_phy_drp_clk:[R] | 0.000 | -0.004 | 1.062 |
Minimum Pulse Width Table:
| Number | Slack | Actual Width | Required Width | Type | Clock | Objects |
|---|---|---|---|---|---|---|
| 1 | 2.354 | 2.604 | 0.250 | Low Pulse Width | sdi_phy_drp_clk | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_link_rate_change_inst/locked_cnt_12_s0 |
| 2 | 2.354 | 2.604 | 0.250 | Low Pulse Width | sdi_phy_drp_clk | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_link_rate_change_inst/locked_cnt_11_s0 |
| 3 | 2.354 | 2.604 | 0.250 | Low Pulse Width | sdi_phy_drp_clk | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_link_rate_change_inst/locked_cnt_10_s0 |
| 4 | 2.354 | 2.604 | 0.250 | Low Pulse Width | sdi_phy_drp_clk | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_link_rate_change_inst/cnt_25_s0 |
| 5 | 2.354 | 2.604 | 0.250 | Low Pulse Width | sdi_phy_drp_clk | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_link_rate_change_inst/cnt_24_s0 |
| 6 | 2.354 | 2.604 | 0.250 | Low Pulse Width | sdi_phy_drp_clk | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_link_rate_change_inst/cnt_5_s0 |
| 7 | 2.354 | 2.604 | 0.250 | Low Pulse Width | sdi_phy_drp_clk | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_link_rate_change_inst/cnt_1_s0 |
| 8 | 2.354 | 2.604 | 0.250 | Low Pulse Width | sdi_phy_drp_clk | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_link_rate_change_inst/cnt_0_s0 |
| 9 | 2.354 | 2.604 | 0.250 | Low Pulse Width | sdi_phy_drp_clk | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_link_rate_change_inst/cnt_4_s0 |
| 10 | 2.354 | 2.604 | 0.250 | Low Pulse Width | sdi_phy_drp_clk | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_link_rate_change_inst/cnt_3_s0 |
Timing Report By Analysis Type:
Setup Analysis Report
Report Command:report_timing -setup -max_paths 25 -max_common_paths 1
Path1
Path Summary:
| Slack | 1.707 |
| Data Arrival Time | 12.358 |
| Data Required Time | 14.065 |
| From | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wren_o_s1 |
| To | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_addr_o_11_s1 |
| Launch Clk | sdi_phy_drp_clk:[R] |
| Latch Clk | sdi_phy_drp_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sdi_phy_drp_clk | ||||
| 0.000 | 0.000 | tCL | RR | 262 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/FABRIC_CM_LIFE_CLK_O |
| 4.358 | 4.358 | tNET | RR | 1 | R32C34[2][A] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wren_o_s1/CLK |
| 4.725 | 0.368 | tC2Q | RF | 1 | R32C34[2][A] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wren_o_s1/Q |
| 6.124 | 1.399 | tNET | FF | 1 | R2C2 | SerDes_Top_inst/gtr12_upar_inst/UPAR_WREN_S |
| 7.378 | 1.254 | tINS | FR | 4 | R2C2 | SerDes_Top_inst/gtr12_upar_inst/UPAR_READY_S |
| 8.689 | 1.311 | tNET | RR | 1 | R34C76[2][B] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_addr_o_23_s4/I2 |
| 9.151 | 0.461 | tINS | RR | 24 | R34C76[2][B] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_addr_o_23_s4/F |
| 12.358 | 3.208 | tNET | RR | 1 | R32C40[0][A] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_addr_o_11_s1/CE |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | ||||
| 10.000 | 0.000 | sdi_phy_drp_clk | ||||
| 10.000 | 0.000 | tCL | RR | 262 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/FABRIC_CM_LIFE_CLK_O |
| 14.376 | 4.376 | tNET | RR | 1 | R32C40[0][A] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_addr_o_11_s1/CLK |
| 14.065 | -0.311 | tSu | 1 | R32C40[0][A] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_addr_o_11_s1 |
Path Statistics:
| Clock Skew | 0.019 |
| Setup Relationship | 10.000 |
| Logic Level | 3 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 4.358, 100.000% |
| Arrival Data Path Delay | cell: 1.716, 21.444%; route: 5.918, 73.963%; tC2Q: 0.368, 4.593% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 4.376, 100.000% |
Path2
Path Summary:
| Slack | 1.771 |
| Data Arrival Time | 12.276 |
| Data Required Time | 14.046 |
| From | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wren_o_s1 |
| To | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_addr_o_9_s1 |
| Launch Clk | sdi_phy_drp_clk:[R] |
| Latch Clk | sdi_phy_drp_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sdi_phy_drp_clk | ||||
| 0.000 | 0.000 | tCL | RR | 262 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/FABRIC_CM_LIFE_CLK_O |
| 4.358 | 4.358 | tNET | RR | 1 | R32C34[2][A] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wren_o_s1/CLK |
| 4.725 | 0.368 | tC2Q | RF | 1 | R32C34[2][A] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wren_o_s1/Q |
| 6.124 | 1.399 | tNET | FF | 1 | R2C2 | SerDes_Top_inst/gtr12_upar_inst/UPAR_WREN_S |
| 7.378 | 1.254 | tINS | FR | 4 | R2C2 | SerDes_Top_inst/gtr12_upar_inst/UPAR_READY_S |
| 8.689 | 1.311 | tNET | RR | 1 | R34C76[2][B] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_addr_o_23_s4/I2 |
| 9.151 | 0.461 | tINS | RR | 24 | R34C76[2][B] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_addr_o_23_s4/F |
| 12.276 | 3.125 | tNET | RR | 1 | R30C46[2][A] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_addr_o_9_s1/CE |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | ||||
| 10.000 | 0.000 | sdi_phy_drp_clk | ||||
| 10.000 | 0.000 | tCL | RR | 262 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/FABRIC_CM_LIFE_CLK_O |
| 14.358 | 4.358 | tNET | RR | 1 | R30C46[2][A] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_addr_o_9_s1/CLK |
| 14.046 | -0.311 | tSu | 1 | R30C46[2][A] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_addr_o_9_s1 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 10.000 |
| Logic Level | 3 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 4.358, 100.000% |
| Arrival Data Path Delay | cell: 1.716, 21.667%; route: 5.835, 73.691%; tC2Q: 0.368, 4.641% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 4.358, 100.000% |
Path3
Path Summary:
| Slack | 1.887 |
| Data Arrival Time | 12.168 |
| Data Required Time | 14.056 |
| From | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wren_o_s1 |
| To | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_addr_o_10_s1 |
| Launch Clk | sdi_phy_drp_clk:[R] |
| Latch Clk | sdi_phy_drp_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sdi_phy_drp_clk | ||||
| 0.000 | 0.000 | tCL | RR | 262 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/FABRIC_CM_LIFE_CLK_O |
| 4.358 | 4.358 | tNET | RR | 1 | R32C34[2][A] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wren_o_s1/CLK |
| 4.725 | 0.368 | tC2Q | RF | 1 | R32C34[2][A] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wren_o_s1/Q |
| 6.124 | 1.399 | tNET | FF | 1 | R2C2 | SerDes_Top_inst/gtr12_upar_inst/UPAR_WREN_S |
| 7.378 | 1.254 | tINS | FR | 4 | R2C2 | SerDes_Top_inst/gtr12_upar_inst/UPAR_READY_S |
| 8.689 | 1.311 | tNET | RR | 1 | R34C76[2][B] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_addr_o_23_s4/I2 |
| 9.151 | 0.461 | tINS | RR | 24 | R34C76[2][B] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_addr_o_23_s4/F |
| 12.168 | 3.018 | tNET | RR | 1 | R30C41[1][A] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_addr_o_10_s1/CE |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | ||||
| 10.000 | 0.000 | sdi_phy_drp_clk | ||||
| 10.000 | 0.000 | tCL | RR | 262 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/FABRIC_CM_LIFE_CLK_O |
| 14.367 | 4.367 | tNET | RR | 1 | R30C41[1][A] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_addr_o_10_s1/CLK |
| 14.056 | -0.311 | tSu | 1 | R30C41[1][A] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_addr_o_10_s1 |
Path Statistics:
| Clock Skew | 0.009 |
| Setup Relationship | 10.000 |
| Logic Level | 3 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 4.358, 100.000% |
| Arrival Data Path Delay | cell: 1.716, 21.966%; route: 5.727, 73.329%; tC2Q: 0.368, 4.705% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 4.367, 100.000% |
Path4
Path Summary:
| Slack | 1.996 |
| Data Arrival Time | 12.051 |
| Data Required Time | 14.046 |
| From | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wren_o_s1 |
| To | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_addr_o_13_s1 |
| Launch Clk | sdi_phy_drp_clk:[R] |
| Latch Clk | sdi_phy_drp_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sdi_phy_drp_clk | ||||
| 0.000 | 0.000 | tCL | RR | 262 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/FABRIC_CM_LIFE_CLK_O |
| 4.358 | 4.358 | tNET | RR | 1 | R32C34[2][A] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wren_o_s1/CLK |
| 4.725 | 0.368 | tC2Q | RF | 1 | R32C34[2][A] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wren_o_s1/Q |
| 6.124 | 1.399 | tNET | FF | 1 | R2C2 | SerDes_Top_inst/gtr12_upar_inst/UPAR_WREN_S |
| 7.378 | 1.254 | tINS | FR | 4 | R2C2 | SerDes_Top_inst/gtr12_upar_inst/UPAR_READY_S |
| 8.689 | 1.311 | tNET | RR | 1 | R34C76[2][B] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_addr_o_23_s4/I2 |
| 9.151 | 0.461 | tINS | RR | 24 | R34C76[2][B] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_addr_o_23_s4/F |
| 12.051 | 2.900 | tNET | RR | 1 | R31C34[2][B] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_addr_o_13_s1/CE |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | ||||
| 10.000 | 0.000 | sdi_phy_drp_clk | ||||
| 10.000 | 0.000 | tCL | RR | 262 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/FABRIC_CM_LIFE_CLK_O |
| 14.358 | 4.358 | tNET | RR | 1 | R31C34[2][B] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_addr_o_13_s1/CLK |
| 14.046 | -0.311 | tSu | 1 | R31C34[2][B] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_addr_o_13_s1 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 10.000 |
| Logic Level | 3 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 4.358, 100.000% |
| Arrival Data Path Delay | cell: 1.716, 22.301%; route: 5.610, 72.922%; tC2Q: 0.368, 4.777% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 4.358, 100.000% |
Path5
Path Summary:
| Slack | 1.996 |
| Data Arrival Time | 12.051 |
| Data Required Time | 14.046 |
| From | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wren_o_s1 |
| To | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_addr_o_14_s1 |
| Launch Clk | sdi_phy_drp_clk:[R] |
| Latch Clk | sdi_phy_drp_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sdi_phy_drp_clk | ||||
| 0.000 | 0.000 | tCL | RR | 262 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/FABRIC_CM_LIFE_CLK_O |
| 4.358 | 4.358 | tNET | RR | 1 | R32C34[2][A] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wren_o_s1/CLK |
| 4.725 | 0.368 | tC2Q | RF | 1 | R32C34[2][A] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wren_o_s1/Q |
| 6.124 | 1.399 | tNET | FF | 1 | R2C2 | SerDes_Top_inst/gtr12_upar_inst/UPAR_WREN_S |
| 7.378 | 1.254 | tINS | FR | 4 | R2C2 | SerDes_Top_inst/gtr12_upar_inst/UPAR_READY_S |
| 8.689 | 1.311 | tNET | RR | 1 | R34C76[2][B] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_addr_o_23_s4/I2 |
| 9.151 | 0.461 | tINS | RR | 24 | R34C76[2][B] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_addr_o_23_s4/F |
| 12.051 | 2.900 | tNET | RR | 1 | R31C34[2][A] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_addr_o_14_s1/CE |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | ||||
| 10.000 | 0.000 | sdi_phy_drp_clk | ||||
| 10.000 | 0.000 | tCL | RR | 262 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/FABRIC_CM_LIFE_CLK_O |
| 14.358 | 4.358 | tNET | RR | 1 | R31C34[2][A] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_addr_o_14_s1/CLK |
| 14.046 | -0.311 | tSu | 1 | R31C34[2][A] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_addr_o_14_s1 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 10.000 |
| Logic Level | 3 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 4.358, 100.000% |
| Arrival Data Path Delay | cell: 1.716, 22.301%; route: 5.610, 72.922%; tC2Q: 0.368, 4.777% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 4.358, 100.000% |
Path6
Path Summary:
| Slack | 1.996 |
| Data Arrival Time | 12.051 |
| Data Required Time | 14.046 |
| From | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wren_o_s1 |
| To | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_addr_o_16_s1 |
| Launch Clk | sdi_phy_drp_clk:[R] |
| Latch Clk | sdi_phy_drp_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sdi_phy_drp_clk | ||||
| 0.000 | 0.000 | tCL | RR | 262 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/FABRIC_CM_LIFE_CLK_O |
| 4.358 | 4.358 | tNET | RR | 1 | R32C34[2][A] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wren_o_s1/CLK |
| 4.725 | 0.368 | tC2Q | RF | 1 | R32C34[2][A] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wren_o_s1/Q |
| 6.124 | 1.399 | tNET | FF | 1 | R2C2 | SerDes_Top_inst/gtr12_upar_inst/UPAR_WREN_S |
| 7.378 | 1.254 | tINS | FR | 4 | R2C2 | SerDes_Top_inst/gtr12_upar_inst/UPAR_READY_S |
| 8.689 | 1.311 | tNET | RR | 1 | R34C76[2][B] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_addr_o_23_s4/I2 |
| 9.151 | 0.461 | tINS | RR | 24 | R34C76[2][B] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_addr_o_23_s4/F |
| 12.051 | 2.900 | tNET | RR | 1 | R31C34[3][B] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_addr_o_16_s1/CE |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | ||||
| 10.000 | 0.000 | sdi_phy_drp_clk | ||||
| 10.000 | 0.000 | tCL | RR | 262 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/FABRIC_CM_LIFE_CLK_O |
| 14.358 | 4.358 | tNET | RR | 1 | R31C34[3][B] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_addr_o_16_s1/CLK |
| 14.046 | -0.311 | tSu | 1 | R31C34[3][B] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_addr_o_16_s1 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 10.000 |
| Logic Level | 3 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 4.358, 100.000% |
| Arrival Data Path Delay | cell: 1.716, 22.301%; route: 5.610, 72.922%; tC2Q: 0.368, 4.777% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 4.358, 100.000% |
Path7
Path Summary:
| Slack | 1.996 |
| Data Arrival Time | 12.051 |
| Data Required Time | 14.046 |
| From | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wren_o_s1 |
| To | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_addr_o_19_s1 |
| Launch Clk | sdi_phy_drp_clk:[R] |
| Latch Clk | sdi_phy_drp_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sdi_phy_drp_clk | ||||
| 0.000 | 0.000 | tCL | RR | 262 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/FABRIC_CM_LIFE_CLK_O |
| 4.358 | 4.358 | tNET | RR | 1 | R32C34[2][A] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wren_o_s1/CLK |
| 4.725 | 0.368 | tC2Q | RF | 1 | R32C34[2][A] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wren_o_s1/Q |
| 6.124 | 1.399 | tNET | FF | 1 | R2C2 | SerDes_Top_inst/gtr12_upar_inst/UPAR_WREN_S |
| 7.378 | 1.254 | tINS | FR | 4 | R2C2 | SerDes_Top_inst/gtr12_upar_inst/UPAR_READY_S |
| 8.689 | 1.311 | tNET | RR | 1 | R34C76[2][B] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_addr_o_23_s4/I2 |
| 9.151 | 0.461 | tINS | RR | 24 | R34C76[2][B] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_addr_o_23_s4/F |
| 12.051 | 2.900 | tNET | RR | 1 | R31C34[3][A] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_addr_o_19_s1/CE |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | ||||
| 10.000 | 0.000 | sdi_phy_drp_clk | ||||
| 10.000 | 0.000 | tCL | RR | 262 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/FABRIC_CM_LIFE_CLK_O |
| 14.358 | 4.358 | tNET | RR | 1 | R31C34[3][A] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_addr_o_19_s1/CLK |
| 14.046 | -0.311 | tSu | 1 | R31C34[3][A] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_addr_o_19_s1 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 10.000 |
| Logic Level | 3 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 4.358, 100.000% |
| Arrival Data Path Delay | cell: 1.716, 22.301%; route: 5.610, 72.922%; tC2Q: 0.368, 4.777% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 4.358, 100.000% |
Path8
Path Summary:
| Slack | 1.996 |
| Data Arrival Time | 12.051 |
| Data Required Time | 14.046 |
| From | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wren_o_s1 |
| To | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_addr_o_23_s1 |
| Launch Clk | sdi_phy_drp_clk:[R] |
| Latch Clk | sdi_phy_drp_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sdi_phy_drp_clk | ||||
| 0.000 | 0.000 | tCL | RR | 262 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/FABRIC_CM_LIFE_CLK_O |
| 4.358 | 4.358 | tNET | RR | 1 | R32C34[2][A] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wren_o_s1/CLK |
| 4.725 | 0.368 | tC2Q | RF | 1 | R32C34[2][A] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wren_o_s1/Q |
| 6.124 | 1.399 | tNET | FF | 1 | R2C2 | SerDes_Top_inst/gtr12_upar_inst/UPAR_WREN_S |
| 7.378 | 1.254 | tINS | FR | 4 | R2C2 | SerDes_Top_inst/gtr12_upar_inst/UPAR_READY_S |
| 8.689 | 1.311 | tNET | RR | 1 | R34C76[2][B] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_addr_o_23_s4/I2 |
| 9.151 | 0.461 | tINS | RR | 24 | R34C76[2][B] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_addr_o_23_s4/F |
| 12.051 | 2.900 | tNET | RR | 1 | R31C34[0][B] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_addr_o_23_s1/CE |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | ||||
| 10.000 | 0.000 | sdi_phy_drp_clk | ||||
| 10.000 | 0.000 | tCL | RR | 262 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/FABRIC_CM_LIFE_CLK_O |
| 14.358 | 4.358 | tNET | RR | 1 | R31C34[0][B] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_addr_o_23_s1/CLK |
| 14.046 | -0.311 | tSu | 1 | R31C34[0][B] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_addr_o_23_s1 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 10.000 |
| Logic Level | 3 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 4.358, 100.000% |
| Arrival Data Path Delay | cell: 1.716, 22.301%; route: 5.610, 72.922%; tC2Q: 0.368, 4.777% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 4.358, 100.000% |
Path9
Path Summary:
| Slack | 2.124 |
| Data Arrival Time | 11.941 |
| Data Required Time | 14.065 |
| From | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wren_o_s1 |
| To | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_addr_o_6_s1 |
| Launch Clk | sdi_phy_drp_clk:[R] |
| Latch Clk | sdi_phy_drp_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sdi_phy_drp_clk | ||||
| 0.000 | 0.000 | tCL | RR | 262 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/FABRIC_CM_LIFE_CLK_O |
| 4.358 | 4.358 | tNET | RR | 1 | R32C34[2][A] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wren_o_s1/CLK |
| 4.725 | 0.368 | tC2Q | RF | 1 | R32C34[2][A] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wren_o_s1/Q |
| 6.124 | 1.399 | tNET | FF | 1 | R2C2 | SerDes_Top_inst/gtr12_upar_inst/UPAR_WREN_S |
| 7.378 | 1.254 | tINS | FR | 4 | R2C2 | SerDes_Top_inst/gtr12_upar_inst/UPAR_READY_S |
| 8.689 | 1.311 | tNET | RR | 1 | R34C76[2][B] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_addr_o_23_s4/I2 |
| 9.151 | 0.461 | tINS | RR | 24 | R34C76[2][B] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_addr_o_23_s4/F |
| 11.941 | 2.790 | tNET | RR | 1 | R30C36[1][B] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_addr_o_6_s1/CE |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | ||||
| 10.000 | 0.000 | sdi_phy_drp_clk | ||||
| 10.000 | 0.000 | tCL | RR | 262 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/FABRIC_CM_LIFE_CLK_O |
| 14.376 | 4.376 | tNET | RR | 1 | R30C36[1][B] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_addr_o_6_s1/CLK |
| 14.065 | -0.311 | tSu | 1 | R30C36[1][B] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_addr_o_6_s1 |
Path Statistics:
| Clock Skew | 0.019 |
| Setup Relationship | 10.000 |
| Logic Level | 3 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 4.358, 100.000% |
| Arrival Data Path Delay | cell: 1.716, 22.625%; route: 5.500, 72.529%; tC2Q: 0.368, 4.846% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 4.376, 100.000% |
Path10
Path Summary:
| Slack | 2.124 |
| Data Arrival Time | 11.941 |
| Data Required Time | 14.065 |
| From | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wren_o_s1 |
| To | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_addr_o_12_s1 |
| Launch Clk | sdi_phy_drp_clk:[R] |
| Latch Clk | sdi_phy_drp_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sdi_phy_drp_clk | ||||
| 0.000 | 0.000 | tCL | RR | 262 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/FABRIC_CM_LIFE_CLK_O |
| 4.358 | 4.358 | tNET | RR | 1 | R32C34[2][A] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wren_o_s1/CLK |
| 4.725 | 0.368 | tC2Q | RF | 1 | R32C34[2][A] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wren_o_s1/Q |
| 6.124 | 1.399 | tNET | FF | 1 | R2C2 | SerDes_Top_inst/gtr12_upar_inst/UPAR_WREN_S |
| 7.378 | 1.254 | tINS | FR | 4 | R2C2 | SerDes_Top_inst/gtr12_upar_inst/UPAR_READY_S |
| 8.689 | 1.311 | tNET | RR | 1 | R34C76[2][B] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_addr_o_23_s4/I2 |
| 9.151 | 0.461 | tINS | RR | 24 | R34C76[2][B] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_addr_o_23_s4/F |
| 11.941 | 2.790 | tNET | RR | 1 | R30C36[1][A] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_addr_o_12_s1/CE |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | ||||
| 10.000 | 0.000 | sdi_phy_drp_clk | ||||
| 10.000 | 0.000 | tCL | RR | 262 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/FABRIC_CM_LIFE_CLK_O |
| 14.376 | 4.376 | tNET | RR | 1 | R30C36[1][A] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_addr_o_12_s1/CLK |
| 14.065 | -0.311 | tSu | 1 | R30C36[1][A] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_addr_o_12_s1 |
Path Statistics:
| Clock Skew | 0.019 |
| Setup Relationship | 10.000 |
| Logic Level | 3 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 4.358, 100.000% |
| Arrival Data Path Delay | cell: 1.716, 22.625%; route: 5.500, 72.529%; tC2Q: 0.368, 4.846% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 4.376, 100.000% |
Path11
Path Summary:
| Slack | 2.131 |
| Data Arrival Time | 11.916 |
| Data Required Time | 14.046 |
| From | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wren_o_s1 |
| To | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wren_o_s1 |
| Launch Clk | sdi_phy_drp_clk:[R] |
| Latch Clk | sdi_phy_drp_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sdi_phy_drp_clk | ||||
| 0.000 | 0.000 | tCL | RR | 262 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/FABRIC_CM_LIFE_CLK_O |
| 4.358 | 4.358 | tNET | RR | 1 | R32C34[2][A] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wren_o_s1/CLK |
| 4.725 | 0.368 | tC2Q | RF | 1 | R32C34[2][A] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wren_o_s1/Q |
| 6.124 | 1.399 | tNET | FF | 1 | R2C2 | SerDes_Top_inst/gtr12_upar_inst/UPAR_WREN_S |
| 7.378 | 1.254 | tINS | FR | 4 | R2C2 | SerDes_Top_inst/gtr12_upar_inst/UPAR_READY_S |
| 8.538 | 1.160 | tNET | RR | 1 | R37C76[3][A] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wren_o_s4/I2 |
| 8.953 | 0.415 | tINS | RR | 41 | R37C76[3][A] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wren_o_s4/F |
| 11.916 | 2.963 | tNET | RR | 1 | R32C34[2][A] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wren_o_s1/CE |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | ||||
| 10.000 | 0.000 | sdi_phy_drp_clk | ||||
| 10.000 | 0.000 | tCL | RR | 262 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/FABRIC_CM_LIFE_CLK_O |
| 14.358 | 4.358 | tNET | RR | 1 | R32C34[2][A] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wren_o_s1/CLK |
| 14.046 | -0.311 | tSu | 1 | R32C34[2][A] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wren_o_s1 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 10.000 |
| Logic Level | 3 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 4.358, 100.000% |
| Arrival Data Path Delay | cell: 1.669, 22.088%; route: 5.521, 73.050%; tC2Q: 0.368, 4.862% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 4.358, 100.000% |
Path12
Path Summary:
| Slack | 2.197 |
| Data Arrival Time | 11.858 |
| Data Required Time | 14.056 |
| From | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wren_o_s1 |
| To | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_addr_o_17_s1 |
| Launch Clk | sdi_phy_drp_clk:[R] |
| Latch Clk | sdi_phy_drp_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sdi_phy_drp_clk | ||||
| 0.000 | 0.000 | tCL | RR | 262 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/FABRIC_CM_LIFE_CLK_O |
| 4.358 | 4.358 | tNET | RR | 1 | R32C34[2][A] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wren_o_s1/CLK |
| 4.725 | 0.368 | tC2Q | RF | 1 | R32C34[2][A] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wren_o_s1/Q |
| 6.124 | 1.399 | tNET | FF | 1 | R2C2 | SerDes_Top_inst/gtr12_upar_inst/UPAR_WREN_S |
| 7.378 | 1.254 | tINS | FR | 4 | R2C2 | SerDes_Top_inst/gtr12_upar_inst/UPAR_READY_S |
| 8.689 | 1.311 | tNET | RR | 1 | R34C76[2][B] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_addr_o_23_s4/I2 |
| 9.151 | 0.461 | tINS | RR | 24 | R34C76[2][B] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_addr_o_23_s4/F |
| 11.858 | 2.708 | tNET | RR | 1 | R31C31[0][A] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_addr_o_17_s1/CE |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | ||||
| 10.000 | 0.000 | sdi_phy_drp_clk | ||||
| 10.000 | 0.000 | tCL | RR | 262 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/FABRIC_CM_LIFE_CLK_O |
| 14.367 | 4.367 | tNET | RR | 1 | R31C31[0][A] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_addr_o_17_s1/CLK |
| 14.056 | -0.311 | tSu | 1 | R31C31[0][A] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_addr_o_17_s1 |
Path Statistics:
| Clock Skew | 0.009 |
| Setup Relationship | 10.000 |
| Logic Level | 3 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 4.358, 100.000% |
| Arrival Data Path Delay | cell: 1.716, 22.874%; route: 5.418, 72.227%; tC2Q: 0.368, 4.900% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 4.367, 100.000% |
Path13
Path Summary:
| Slack | 2.222 |
| Data Arrival Time | 11.824 |
| Data Required Time | 14.046 |
| From | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wren_o_s1 |
| To | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wrdata_o_0_s1 |
| Launch Clk | sdi_phy_drp_clk:[R] |
| Latch Clk | sdi_phy_drp_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sdi_phy_drp_clk | ||||
| 0.000 | 0.000 | tCL | RR | 262 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/FABRIC_CM_LIFE_CLK_O |
| 4.358 | 4.358 | tNET | RR | 1 | R32C34[2][A] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wren_o_s1/CLK |
| 4.725 | 0.368 | tC2Q | RF | 1 | R32C34[2][A] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wren_o_s1/Q |
| 6.124 | 1.399 | tNET | FF | 1 | R2C2 | SerDes_Top_inst/gtr12_upar_inst/UPAR_WREN_S |
| 7.378 | 1.254 | tINS | FR | 4 | R2C2 | SerDes_Top_inst/gtr12_upar_inst/UPAR_READY_S |
| 8.538 | 1.160 | tNET | RR | 1 | R37C76[3][A] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wren_o_s4/I2 |
| 8.953 | 0.415 | tINS | RR | 41 | R37C76[3][A] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wren_o_s4/F |
| 11.824 | 2.871 | tNET | RR | 1 | R31C42[0][A] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wrdata_o_0_s1/CE |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | ||||
| 10.000 | 0.000 | sdi_phy_drp_clk | ||||
| 10.000 | 0.000 | tCL | RR | 262 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/FABRIC_CM_LIFE_CLK_O |
| 14.358 | 4.358 | tNET | RR | 1 | R31C42[0][A] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wrdata_o_0_s1/CLK |
| 14.046 | -0.311 | tSu | 1 | R31C42[0][A] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wrdata_o_0_s1 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 10.000 |
| Logic Level | 3 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 4.358, 100.000% |
| Arrival Data Path Delay | cell: 1.669, 22.359%; route: 5.429, 72.719%; tC2Q: 0.368, 4.922% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 4.358, 100.000% |
Path14
Path Summary:
| Slack | 2.383 |
| Data Arrival Time | 11.663 |
| Data Required Time | 14.046 |
| From | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wren_o_s1 |
| To | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_addr_o_20_s1 |
| Launch Clk | sdi_phy_drp_clk:[R] |
| Latch Clk | sdi_phy_drp_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sdi_phy_drp_clk | ||||
| 0.000 | 0.000 | tCL | RR | 262 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/FABRIC_CM_LIFE_CLK_O |
| 4.358 | 4.358 | tNET | RR | 1 | R32C34[2][A] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wren_o_s1/CLK |
| 4.725 | 0.368 | tC2Q | RF | 1 | R32C34[2][A] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wren_o_s1/Q |
| 6.124 | 1.399 | tNET | FF | 1 | R2C2 | SerDes_Top_inst/gtr12_upar_inst/UPAR_WREN_S |
| 7.378 | 1.254 | tINS | FR | 4 | R2C2 | SerDes_Top_inst/gtr12_upar_inst/UPAR_READY_S |
| 8.689 | 1.311 | tNET | RR | 1 | R34C76[2][B] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_addr_o_23_s4/I2 |
| 9.151 | 0.461 | tINS | RR | 24 | R34C76[2][B] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_addr_o_23_s4/F |
| 11.663 | 2.513 | tNET | RR | 1 | R31C30[0][A] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_addr_o_20_s1/CE |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | ||||
| 10.000 | 0.000 | sdi_phy_drp_clk | ||||
| 10.000 | 0.000 | tCL | RR | 262 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/FABRIC_CM_LIFE_CLK_O |
| 14.358 | 4.358 | tNET | RR | 1 | R31C30[0][A] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_addr_o_20_s1/CLK |
| 14.046 | -0.311 | tSu | 1 | R31C30[0][A] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_addr_o_20_s1 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 10.000 |
| Logic Level | 3 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 4.358, 100.000% |
| Arrival Data Path Delay | cell: 1.716, 23.484%; route: 5.223, 71.486%; tC2Q: 0.368, 5.030% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 4.358, 100.000% |
Path15
Path Summary:
| Slack | 2.433 |
| Data Arrival Time | 11.613 |
| Data Required Time | 14.046 |
| From | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wren_o_s1 |
| To | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_strb_o_2_s1 |
| Launch Clk | sdi_phy_drp_clk:[R] |
| Latch Clk | sdi_phy_drp_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sdi_phy_drp_clk | ||||
| 0.000 | 0.000 | tCL | RR | 262 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/FABRIC_CM_LIFE_CLK_O |
| 4.358 | 4.358 | tNET | RR | 1 | R32C34[2][A] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wren_o_s1/CLK |
| 4.725 | 0.368 | tC2Q | RF | 1 | R32C34[2][A] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wren_o_s1/Q |
| 6.124 | 1.399 | tNET | FF | 1 | R2C2 | SerDes_Top_inst/gtr12_upar_inst/UPAR_WREN_S |
| 7.378 | 1.254 | tINS | FR | 4 | R2C2 | SerDes_Top_inst/gtr12_upar_inst/UPAR_READY_S |
| 8.538 | 1.160 | tNET | RR | 1 | R37C76[3][A] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wren_o_s4/I2 |
| 8.953 | 0.415 | tINS | RR | 41 | R37C76[3][A] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wren_o_s4/F |
| 11.613 | 2.660 | tNET | RR | 1 | R30C42[2][A] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_strb_o_2_s1/CE |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | ||||
| 10.000 | 0.000 | sdi_phy_drp_clk | ||||
| 10.000 | 0.000 | tCL | RR | 262 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/FABRIC_CM_LIFE_CLK_O |
| 14.358 | 4.358 | tNET | RR | 1 | R30C42[2][A] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_strb_o_2_s1/CLK |
| 14.046 | -0.311 | tSu | 1 | R30C42[2][A] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_strb_o_2_s1 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 10.000 |
| Logic Level | 3 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 4.358, 100.000% |
| Arrival Data Path Delay | cell: 1.669, 23.008%; route: 5.219, 71.927%; tC2Q: 0.368, 5.065% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 4.358, 100.000% |
Path16
Path Summary:
| Slack | 2.433 |
| Data Arrival Time | 11.613 |
| Data Required Time | 14.046 |
| From | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wren_o_s1 |
| To | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_strb_o_3_s1 |
| Launch Clk | sdi_phy_drp_clk:[R] |
| Latch Clk | sdi_phy_drp_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sdi_phy_drp_clk | ||||
| 0.000 | 0.000 | tCL | RR | 262 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/FABRIC_CM_LIFE_CLK_O |
| 4.358 | 4.358 | tNET | RR | 1 | R32C34[2][A] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wren_o_s1/CLK |
| 4.725 | 0.368 | tC2Q | RF | 1 | R32C34[2][A] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wren_o_s1/Q |
| 6.124 | 1.399 | tNET | FF | 1 | R2C2 | SerDes_Top_inst/gtr12_upar_inst/UPAR_WREN_S |
| 7.378 | 1.254 | tINS | FR | 4 | R2C2 | SerDes_Top_inst/gtr12_upar_inst/UPAR_READY_S |
| 8.538 | 1.160 | tNET | RR | 1 | R37C76[3][A] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wren_o_s4/I2 |
| 8.953 | 0.415 | tINS | RR | 41 | R37C76[3][A] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wren_o_s4/F |
| 11.613 | 2.660 | tNET | RR | 1 | R30C42[2][B] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_strb_o_3_s1/CE |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | ||||
| 10.000 | 0.000 | sdi_phy_drp_clk | ||||
| 10.000 | 0.000 | tCL | RR | 262 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/FABRIC_CM_LIFE_CLK_O |
| 14.358 | 4.358 | tNET | RR | 1 | R30C42[2][B] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_strb_o_3_s1/CLK |
| 14.046 | -0.311 | tSu | 1 | R30C42[2][B] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_strb_o_3_s1 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 10.000 |
| Logic Level | 3 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 4.358, 100.000% |
| Arrival Data Path Delay | cell: 1.669, 23.008%; route: 5.219, 71.927%; tC2Q: 0.368, 5.065% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 4.358, 100.000% |
Path17
Path Summary:
| Slack | 2.433 |
| Data Arrival Time | 11.613 |
| Data Required Time | 14.046 |
| From | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wren_o_s1 |
| To | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_strb_o_4_s1 |
| Launch Clk | sdi_phy_drp_clk:[R] |
| Latch Clk | sdi_phy_drp_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sdi_phy_drp_clk | ||||
| 0.000 | 0.000 | tCL | RR | 262 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/FABRIC_CM_LIFE_CLK_O |
| 4.358 | 4.358 | tNET | RR | 1 | R32C34[2][A] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wren_o_s1/CLK |
| 4.725 | 0.368 | tC2Q | RF | 1 | R32C34[2][A] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wren_o_s1/Q |
| 6.124 | 1.399 | tNET | FF | 1 | R2C2 | SerDes_Top_inst/gtr12_upar_inst/UPAR_WREN_S |
| 7.378 | 1.254 | tINS | FR | 4 | R2C2 | SerDes_Top_inst/gtr12_upar_inst/UPAR_READY_S |
| 8.538 | 1.160 | tNET | RR | 1 | R37C76[3][A] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wren_o_s4/I2 |
| 8.953 | 0.415 | tINS | RR | 41 | R37C76[3][A] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wren_o_s4/F |
| 11.613 | 2.660 | tNET | RR | 1 | R30C42[0][A] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_strb_o_4_s1/CE |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | ||||
| 10.000 | 0.000 | sdi_phy_drp_clk | ||||
| 10.000 | 0.000 | tCL | RR | 262 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/FABRIC_CM_LIFE_CLK_O |
| 14.358 | 4.358 | tNET | RR | 1 | R30C42[0][A] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_strb_o_4_s1/CLK |
| 14.046 | -0.311 | tSu | 1 | R30C42[0][A] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_strb_o_4_s1 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 10.000 |
| Logic Level | 3 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 4.358, 100.000% |
| Arrival Data Path Delay | cell: 1.669, 23.008%; route: 5.219, 71.927%; tC2Q: 0.368, 5.065% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 4.358, 100.000% |
Path18
Path Summary:
| Slack | 2.433 |
| Data Arrival Time | 11.613 |
| Data Required Time | 14.046 |
| From | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wren_o_s1 |
| To | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wrdata_o_5_s1 |
| Launch Clk | sdi_phy_drp_clk:[R] |
| Latch Clk | sdi_phy_drp_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sdi_phy_drp_clk | ||||
| 0.000 | 0.000 | tCL | RR | 262 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/FABRIC_CM_LIFE_CLK_O |
| 4.358 | 4.358 | tNET | RR | 1 | R32C34[2][A] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wren_o_s1/CLK |
| 4.725 | 0.368 | tC2Q | RF | 1 | R32C34[2][A] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wren_o_s1/Q |
| 6.124 | 1.399 | tNET | FF | 1 | R2C2 | SerDes_Top_inst/gtr12_upar_inst/UPAR_WREN_S |
| 7.378 | 1.254 | tINS | FR | 4 | R2C2 | SerDes_Top_inst/gtr12_upar_inst/UPAR_READY_S |
| 8.538 | 1.160 | tNET | RR | 1 | R37C76[3][A] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wren_o_s4/I2 |
| 8.953 | 0.415 | tINS | RR | 41 | R37C76[3][A] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wren_o_s4/F |
| 11.613 | 2.660 | tNET | RR | 1 | R30C42[0][B] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wrdata_o_5_s1/CE |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | ||||
| 10.000 | 0.000 | sdi_phy_drp_clk | ||||
| 10.000 | 0.000 | tCL | RR | 262 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/FABRIC_CM_LIFE_CLK_O |
| 14.358 | 4.358 | tNET | RR | 1 | R30C42[0][B] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wrdata_o_5_s1/CLK |
| 14.046 | -0.311 | tSu | 1 | R30C42[0][B] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wrdata_o_5_s1 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 10.000 |
| Logic Level | 3 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 4.358, 100.000% |
| Arrival Data Path Delay | cell: 1.669, 23.008%; route: 5.219, 71.927%; tC2Q: 0.368, 5.065% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 4.358, 100.000% |
Path19
Path Summary:
| Slack | 2.433 |
| Data Arrival Time | 11.613 |
| Data Required Time | 14.046 |
| From | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wren_o_s1 |
| To | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wrdata_o_30_s1 |
| Launch Clk | sdi_phy_drp_clk:[R] |
| Latch Clk | sdi_phy_drp_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sdi_phy_drp_clk | ||||
| 0.000 | 0.000 | tCL | RR | 262 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/FABRIC_CM_LIFE_CLK_O |
| 4.358 | 4.358 | tNET | RR | 1 | R32C34[2][A] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wren_o_s1/CLK |
| 4.725 | 0.368 | tC2Q | RF | 1 | R32C34[2][A] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wren_o_s1/Q |
| 6.124 | 1.399 | tNET | FF | 1 | R2C2 | SerDes_Top_inst/gtr12_upar_inst/UPAR_WREN_S |
| 7.378 | 1.254 | tINS | FR | 4 | R2C2 | SerDes_Top_inst/gtr12_upar_inst/UPAR_READY_S |
| 8.538 | 1.160 | tNET | RR | 1 | R37C76[3][A] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wren_o_s4/I2 |
| 8.953 | 0.415 | tINS | RR | 41 | R37C76[3][A] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wren_o_s4/F |
| 11.613 | 2.660 | tNET | RR | 1 | R30C42[3][B] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wrdata_o_30_s1/CE |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | ||||
| 10.000 | 0.000 | sdi_phy_drp_clk | ||||
| 10.000 | 0.000 | tCL | RR | 262 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/FABRIC_CM_LIFE_CLK_O |
| 14.358 | 4.358 | tNET | RR | 1 | R30C42[3][B] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wrdata_o_30_s1/CLK |
| 14.046 | -0.311 | tSu | 1 | R30C42[3][B] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wrdata_o_30_s1 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 10.000 |
| Logic Level | 3 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 4.358, 100.000% |
| Arrival Data Path Delay | cell: 1.669, 23.008%; route: 5.219, 71.927%; tC2Q: 0.368, 5.065% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 4.358, 100.000% |
Path20
Path Summary:
| Slack | 2.433 |
| Data Arrival Time | 11.613 |
| Data Required Time | 14.046 |
| From | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wren_o_s1 |
| To | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wrdata_o_31_s1 |
| Launch Clk | sdi_phy_drp_clk:[R] |
| Latch Clk | sdi_phy_drp_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sdi_phy_drp_clk | ||||
| 0.000 | 0.000 | tCL | RR | 262 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/FABRIC_CM_LIFE_CLK_O |
| 4.358 | 4.358 | tNET | RR | 1 | R32C34[2][A] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wren_o_s1/CLK |
| 4.725 | 0.368 | tC2Q | RF | 1 | R32C34[2][A] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wren_o_s1/Q |
| 6.124 | 1.399 | tNET | FF | 1 | R2C2 | SerDes_Top_inst/gtr12_upar_inst/UPAR_WREN_S |
| 7.378 | 1.254 | tINS | FR | 4 | R2C2 | SerDes_Top_inst/gtr12_upar_inst/UPAR_READY_S |
| 8.538 | 1.160 | tNET | RR | 1 | R37C76[3][A] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wren_o_s4/I2 |
| 8.953 | 0.415 | tINS | RR | 41 | R37C76[3][A] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wren_o_s4/F |
| 11.613 | 2.660 | tNET | RR | 1 | R30C42[3][A] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wrdata_o_31_s1/CE |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | ||||
| 10.000 | 0.000 | sdi_phy_drp_clk | ||||
| 10.000 | 0.000 | tCL | RR | 262 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/FABRIC_CM_LIFE_CLK_O |
| 14.358 | 4.358 | tNET | RR | 1 | R30C42[3][A] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wrdata_o_31_s1/CLK |
| 14.046 | -0.311 | tSu | 1 | R30C42[3][A] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wrdata_o_31_s1 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 10.000 |
| Logic Level | 3 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 4.358, 100.000% |
| Arrival Data Path Delay | cell: 1.669, 23.008%; route: 5.219, 71.927%; tC2Q: 0.368, 5.065% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 4.358, 100.000% |
Path21
Path Summary:
| Slack | 2.442 |
| Data Arrival Time | 11.613 |
| Data Required Time | 14.056 |
| From | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wren_o_s1 |
| To | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_strb_o_5_s1 |
| Launch Clk | sdi_phy_drp_clk:[R] |
| Latch Clk | sdi_phy_drp_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sdi_phy_drp_clk | ||||
| 0.000 | 0.000 | tCL | RR | 262 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/FABRIC_CM_LIFE_CLK_O |
| 4.358 | 4.358 | tNET | RR | 1 | R32C34[2][A] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wren_o_s1/CLK |
| 4.725 | 0.368 | tC2Q | RF | 1 | R32C34[2][A] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wren_o_s1/Q |
| 6.124 | 1.399 | tNET | FF | 1 | R2C2 | SerDes_Top_inst/gtr12_upar_inst/UPAR_WREN_S |
| 7.378 | 1.254 | tINS | FR | 4 | R2C2 | SerDes_Top_inst/gtr12_upar_inst/UPAR_READY_S |
| 8.538 | 1.160 | tNET | RR | 1 | R37C76[3][A] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wren_o_s4/I2 |
| 8.953 | 0.415 | tINS | RR | 41 | R37C76[3][A] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wren_o_s4/F |
| 11.613 | 2.660 | tNET | RR | 1 | R30C41[2][A] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_strb_o_5_s1/CE |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | ||||
| 10.000 | 0.000 | sdi_phy_drp_clk | ||||
| 10.000 | 0.000 | tCL | RR | 262 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/FABRIC_CM_LIFE_CLK_O |
| 14.367 | 4.367 | tNET | RR | 1 | R30C41[2][A] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_strb_o_5_s1/CLK |
| 14.056 | -0.311 | tSu | 1 | R30C41[2][A] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_strb_o_5_s1 |
Path Statistics:
| Clock Skew | 0.009 |
| Setup Relationship | 10.000 |
| Logic Level | 3 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 4.358, 100.000% |
| Arrival Data Path Delay | cell: 1.669, 23.008%; route: 5.219, 71.927%; tC2Q: 0.368, 5.065% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 4.367, 100.000% |
Path22
Path Summary:
| Slack | 2.442 |
| Data Arrival Time | 11.613 |
| Data Required Time | 14.056 |
| From | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wren_o_s1 |
| To | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wrdata_o_19_s1 |
| Launch Clk | sdi_phy_drp_clk:[R] |
| Latch Clk | sdi_phy_drp_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sdi_phy_drp_clk | ||||
| 0.000 | 0.000 | tCL | RR | 262 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/FABRIC_CM_LIFE_CLK_O |
| 4.358 | 4.358 | tNET | RR | 1 | R32C34[2][A] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wren_o_s1/CLK |
| 4.725 | 0.368 | tC2Q | RF | 1 | R32C34[2][A] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wren_o_s1/Q |
| 6.124 | 1.399 | tNET | FF | 1 | R2C2 | SerDes_Top_inst/gtr12_upar_inst/UPAR_WREN_S |
| 7.378 | 1.254 | tINS | FR | 4 | R2C2 | SerDes_Top_inst/gtr12_upar_inst/UPAR_READY_S |
| 8.538 | 1.160 | tNET | RR | 1 | R37C76[3][A] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wren_o_s4/I2 |
| 8.953 | 0.415 | tINS | RR | 41 | R37C76[3][A] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wren_o_s4/F |
| 11.613 | 2.660 | tNET | RR | 1 | R30C41[2][B] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wrdata_o_19_s1/CE |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | ||||
| 10.000 | 0.000 | sdi_phy_drp_clk | ||||
| 10.000 | 0.000 | tCL | RR | 262 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/FABRIC_CM_LIFE_CLK_O |
| 14.367 | 4.367 | tNET | RR | 1 | R30C41[2][B] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wrdata_o_19_s1/CLK |
| 14.056 | -0.311 | tSu | 1 | R30C41[2][B] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wrdata_o_19_s1 |
Path Statistics:
| Clock Skew | 0.009 |
| Setup Relationship | 10.000 |
| Logic Level | 3 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 4.358, 100.000% |
| Arrival Data Path Delay | cell: 1.669, 23.008%; route: 5.219, 71.927%; tC2Q: 0.368, 5.065% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 4.367, 100.000% |
Path23
Path Summary:
| Slack | 2.442 |
| Data Arrival Time | 11.613 |
| Data Required Time | 14.056 |
| From | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wren_o_s1 |
| To | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wrdata_o_20_s1 |
| Launch Clk | sdi_phy_drp_clk:[R] |
| Latch Clk | sdi_phy_drp_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sdi_phy_drp_clk | ||||
| 0.000 | 0.000 | tCL | RR | 262 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/FABRIC_CM_LIFE_CLK_O |
| 4.358 | 4.358 | tNET | RR | 1 | R32C34[2][A] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wren_o_s1/CLK |
| 4.725 | 0.368 | tC2Q | RF | 1 | R32C34[2][A] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wren_o_s1/Q |
| 6.124 | 1.399 | tNET | FF | 1 | R2C2 | SerDes_Top_inst/gtr12_upar_inst/UPAR_WREN_S |
| 7.378 | 1.254 | tINS | FR | 4 | R2C2 | SerDes_Top_inst/gtr12_upar_inst/UPAR_READY_S |
| 8.538 | 1.160 | tNET | RR | 1 | R37C76[3][A] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wren_o_s4/I2 |
| 8.953 | 0.415 | tINS | RR | 41 | R37C76[3][A] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wren_o_s4/F |
| 11.613 | 2.660 | tNET | RR | 1 | R30C41[3][A] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wrdata_o_20_s1/CE |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | ||||
| 10.000 | 0.000 | sdi_phy_drp_clk | ||||
| 10.000 | 0.000 | tCL | RR | 262 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/FABRIC_CM_LIFE_CLK_O |
| 14.367 | 4.367 | tNET | RR | 1 | R30C41[3][A] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wrdata_o_20_s1/CLK |
| 14.056 | -0.311 | tSu | 1 | R30C41[3][A] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wrdata_o_20_s1 |
Path Statistics:
| Clock Skew | 0.009 |
| Setup Relationship | 10.000 |
| Logic Level | 3 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 4.358, 100.000% |
| Arrival Data Path Delay | cell: 1.669, 23.008%; route: 5.219, 71.927%; tC2Q: 0.368, 5.065% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 4.367, 100.000% |
Path24
Path Summary:
| Slack | 2.649 |
| Data Arrival Time | 11.416 |
| Data Required Time | 14.065 |
| From | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wren_o_s1 |
| To | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wrdata_o_25_s1 |
| Launch Clk | sdi_phy_drp_clk:[R] |
| Latch Clk | sdi_phy_drp_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sdi_phy_drp_clk | ||||
| 0.000 | 0.000 | tCL | RR | 262 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/FABRIC_CM_LIFE_CLK_O |
| 4.358 | 4.358 | tNET | RR | 1 | R32C34[2][A] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wren_o_s1/CLK |
| 4.725 | 0.368 | tC2Q | RF | 1 | R32C34[2][A] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wren_o_s1/Q |
| 6.124 | 1.399 | tNET | FF | 1 | R2C2 | SerDes_Top_inst/gtr12_upar_inst/UPAR_WREN_S |
| 7.378 | 1.254 | tINS | FR | 4 | R2C2 | SerDes_Top_inst/gtr12_upar_inst/UPAR_READY_S |
| 8.538 | 1.160 | tNET | RR | 1 | R37C76[3][A] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wren_o_s4/I2 |
| 8.953 | 0.415 | tINS | RR | 41 | R37C76[3][A] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wren_o_s4/F |
| 11.416 | 2.463 | tNET | RR | 1 | R32C40[1][A] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wrdata_o_25_s1/CE |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | ||||
| 10.000 | 0.000 | sdi_phy_drp_clk | ||||
| 10.000 | 0.000 | tCL | RR | 262 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/FABRIC_CM_LIFE_CLK_O |
| 14.376 | 4.376 | tNET | RR | 1 | R32C40[1][A] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wrdata_o_25_s1/CLK |
| 14.065 | -0.311 | tSu | 1 | R32C40[1][A] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wrdata_o_25_s1 |
Path Statistics:
| Clock Skew | 0.019 |
| Setup Relationship | 10.000 |
| Logic Level | 3 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 4.358, 100.000% |
| Arrival Data Path Delay | cell: 1.669, 23.652%; route: 5.021, 71.141%; tC2Q: 0.368, 5.207% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 4.376, 100.000% |
Path25
Path Summary:
| Slack | 2.777 |
| Data Arrival Time | 11.278 |
| Data Required Time | 14.056 |
| From | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wren_o_s1 |
| To | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_addr_o_0_s1 |
| Launch Clk | sdi_phy_drp_clk:[R] |
| Latch Clk | sdi_phy_drp_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sdi_phy_drp_clk | ||||
| 0.000 | 0.000 | tCL | RR | 262 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/FABRIC_CM_LIFE_CLK_O |
| 4.358 | 4.358 | tNET | RR | 1 | R32C34[2][A] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wren_o_s1/CLK |
| 4.725 | 0.368 | tC2Q | RF | 1 | R32C34[2][A] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wren_o_s1/Q |
| 6.124 | 1.399 | tNET | FF | 1 | R2C2 | SerDes_Top_inst/gtr12_upar_inst/UPAR_WREN_S |
| 7.378 | 1.254 | tINS | FR | 4 | R2C2 | SerDes_Top_inst/gtr12_upar_inst/UPAR_READY_S |
| 8.689 | 1.311 | tNET | RR | 1 | R34C76[2][B] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_addr_o_23_s4/I2 |
| 9.151 | 0.461 | tINS | RR | 24 | R34C76[2][B] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_addr_o_23_s4/F |
| 11.278 | 2.128 | tNET | RR | 1 | R30C31[2][A] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_addr_o_0_s1/CE |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | ||||
| 10.000 | 0.000 | sdi_phy_drp_clk | ||||
| 10.000 | 0.000 | tCL | RR | 262 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/FABRIC_CM_LIFE_CLK_O |
| 14.367 | 4.367 | tNET | RR | 1 | R30C31[2][A] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_addr_o_0_s1/CLK |
| 14.056 | -0.311 | tSu | 1 | R30C31[2][A] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_addr_o_0_s1 |
Path Statistics:
| Clock Skew | 0.009 |
| Setup Relationship | 10.000 |
| Logic Level | 3 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 4.358, 100.000% |
| Arrival Data Path Delay | cell: 1.716, 24.790%; route: 4.838, 69.899%; tC2Q: 0.368, 5.310% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 4.367, 100.000% |
Hold Analysis Report
Report Command:report_timing -hold -max_paths 25 -max_common_paths 1
Path1
Path Summary:
| Slack | 0.007 |
| Data Arrival Time | 0.917 |
| Data Required Time | 0.910 |
| From | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_hd_level_b_dl_wrapper_inst/rx_hd_type2_to_type1_inst/datas2_d1_3_s0 |
| To | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_hd_level_b_dl_wrapper_inst/rx_hd_type2_to_type1_inst/rx_hd_lbdl_sdpb_even_inst0/sdpx9b_inst_2 |
| Launch Clk | sdi_phy_rx_clk:[R] |
| Latch Clk | sdi_phy_rx_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sdi_phy_rx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1923 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_RX_O_FABRIC_CLK |
| 0.676 | 0.676 | tNET | RR | 1 | R39C62[1][B] | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_hd_level_b_dl_wrapper_inst/rx_hd_type2_to_type1_inst/datas2_d1_3_s0/CLK |
| 0.817 | 0.141 | tC2Q | RF | 4 | R39C62[1][B] | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_hd_level_b_dl_wrapper_inst/rx_hd_type2_to_type1_inst/datas2_d1_3_s0/Q |
| 0.917 | 0.100 | tNET | FF | 1 | BSRAM_R38[12][B] | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_hd_level_b_dl_wrapper_inst/rx_hd_type2_to_type1_inst/rx_hd_lbdl_sdpb_even_inst0/sdpx9b_inst_2/DI[3] |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sdi_phy_rx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1923 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_RX_O_FABRIC_CLK |
| 0.873 | 0.873 | tNET | RR | 1 | BSRAM_R38[12][B] | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_hd_level_b_dl_wrapper_inst/rx_hd_type2_to_type1_inst/rx_hd_lbdl_sdpb_even_inst0/sdpx9b_inst_2/CLKA |
| 0.910 | 0.037 | tHld | 1 | BSRAM_R38[12][B] | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_hd_level_b_dl_wrapper_inst/rx_hd_type2_to_type1_inst/rx_hd_lbdl_sdpb_even_inst0/sdpx9b_inst_2 |
Path Statistics:
| Clock Skew | 0.197 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.676, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.100, 41.494%; tC2Q: 0.141, 58.506% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.873, 100.000% |
Path2
Path Summary:
| Slack | 0.007 |
| Data Arrival Time | 0.915 |
| Data Required Time | 0.908 |
| From | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_level_datastream_inst/tx_hd_level_b_dl_sdpb_pro_inst/rd_addr_5_s1 |
| To | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_level_datastream_inst/tx_hd_level_b_dl_sdpb_pro_inst/tx_hd_lbdl_sdpb_inst0/sdpx9b_inst_1 |
| Launch Clk | sdi_phy_tx_clk:[R] |
| Latch Clk | sdi_phy_tx_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sdi_phy_tx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 3886 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK |
| 0.672 | 0.672 | tNET | RR | 1 | R45C32[2][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_level_datastream_inst/tx_hd_level_b_dl_sdpb_pro_inst/rd_addr_5_s1/CLK |
| 0.813 | 0.141 | tC2Q | RF | 17 | R45C32[2][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_level_datastream_inst/tx_hd_level_b_dl_sdpb_pro_inst/rd_addr_5_s1/Q |
| 0.915 | 0.102 | tNET | FF | 1 | BSRAM_R38[6][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_level_datastream_inst/tx_hd_level_b_dl_sdpb_pro_inst/tx_hd_lbdl_sdpb_inst0/sdpx9b_inst_1/ADB[8] |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sdi_phy_tx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 3886 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK |
| 0.873 | 0.873 | tNET | RR | 1 | BSRAM_R38[6][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_level_datastream_inst/tx_hd_level_b_dl_sdpb_pro_inst/tx_hd_lbdl_sdpb_inst0/sdpx9b_inst_1/CLKB |
| 0.908 | 0.035 | tHld | 1 | BSRAM_R38[6][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_level_datastream_inst/tx_hd_level_b_dl_sdpb_pro_inst/tx_hd_lbdl_sdpb_inst0/sdpx9b_inst_1 |
Path Statistics:
| Clock Skew | 0.201 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.672, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.102, 41.975%; tC2Q: 0.141, 58.025% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.873, 100.000% |
Path3
Path Summary:
| Slack | 0.007 |
| Data Arrival Time | 0.921 |
| Data Required Time | 0.914 |
| From | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_hd_level_b_dl_wrapper_inst/rx_hd_type2_to_type1_inst/datas2_d2_6_s0 |
| To | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_hd_level_b_dl_wrapper_inst/rx_hd_type2_to_type1_inst/rx_hd_lbdl_sdpb_even_inst0/sdpx9b_inst_3 |
| Launch Clk | sdi_phy_rx_clk:[R] |
| Latch Clk | sdi_phy_rx_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sdi_phy_rx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1923 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_RX_O_FABRIC_CLK |
| 0.680 | 0.680 | tNET | RR | 1 | R39C65[1][B] | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_hd_level_b_dl_wrapper_inst/rx_hd_type2_to_type1_inst/datas2_d2_6_s0/CLK |
| 0.821 | 0.141 | tC2Q | RF | 3 | R39C65[1][B] | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_hd_level_b_dl_wrapper_inst/rx_hd_type2_to_type1_inst/datas2_d2_6_s0/Q |
| 0.921 | 0.100 | tNET | FF | 1 | BSRAM_R38[13] | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_hd_level_b_dl_wrapper_inst/rx_hd_type2_to_type1_inst/rx_hd_lbdl_sdpb_even_inst0/sdpx9b_inst_3/DI[7] |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sdi_phy_rx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1923 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_RX_O_FABRIC_CLK |
| 0.877 | 0.877 | tNET | RR | 1 | BSRAM_R38[13] | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_hd_level_b_dl_wrapper_inst/rx_hd_type2_to_type1_inst/rx_hd_lbdl_sdpb_even_inst0/sdpx9b_inst_3/CLKA |
| 0.914 | 0.037 | tHld | 1 | BSRAM_R38[13] | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_hd_level_b_dl_wrapper_inst/rx_hd_type2_to_type1_inst/rx_hd_lbdl_sdpb_even_inst0/sdpx9b_inst_3 |
Path Statistics:
| Clock Skew | 0.197 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.680, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.100, 41.494%; tC2Q: 0.141, 58.506% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.877, 100.000% |
Path4
Path Summary:
| Slack | 0.007 |
| Data Arrival Time | 0.913 |
| Data Required Time | 0.906 |
| From | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_hd_level_b_dl_wrapper_inst/rx_hd_type2_to_type1_inst/datas1_d2_4_s0 |
| To | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_hd_level_b_dl_wrapper_inst/rx_hd_type2_to_type1_inst/rx_hd_lbdl_sdpb_odd_inst0/sdpx9b_inst_4 |
| Launch Clk | sdi_phy_rx_clk:[R] |
| Latch Clk | sdi_phy_rx_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sdi_phy_rx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1923 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_RX_O_FABRIC_CLK |
| 0.672 | 0.672 | tNET | RR | 1 | R39C47[1][A] | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_hd_level_b_dl_wrapper_inst/rx_hd_type2_to_type1_inst/datas1_d2_4_s0/CLK |
| 0.813 | 0.141 | tC2Q | RF | 3 | R39C47[1][A] | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_hd_level_b_dl_wrapper_inst/rx_hd_type2_to_type1_inst/datas1_d2_4_s0/Q |
| 0.913 | 0.100 | tNET | FF | 1 | BSRAM_R38[9] | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_hd_level_b_dl_wrapper_inst/rx_hd_type2_to_type1_inst/rx_hd_lbdl_sdpb_odd_inst0/sdpx9b_inst_4/DI[5] |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sdi_phy_rx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1923 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_RX_O_FABRIC_CLK |
| 0.869 | 0.869 | tNET | RR | 1 | BSRAM_R38[9] | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_hd_level_b_dl_wrapper_inst/rx_hd_type2_to_type1_inst/rx_hd_lbdl_sdpb_odd_inst0/sdpx9b_inst_4/CLKA |
| 0.906 | 0.037 | tHld | 1 | BSRAM_R38[9] | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_hd_level_b_dl_wrapper_inst/rx_hd_type2_to_type1_inst/rx_hd_lbdl_sdpb_odd_inst0/sdpx9b_inst_4 |
Path Statistics:
| Clock Skew | 0.197 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.672, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.100, 41.494%; tC2Q: 0.141, 58.506% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.869, 100.000% |
Path5
Path Summary:
| Slack | 0.007 |
| Data Arrival Time | 0.913 |
| Data Required Time | 0.906 |
| From | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_hd_level_b_dl_wrapper_inst/rx_hd_type2_to_type1_inst/datas1_d2_2_s0 |
| To | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_hd_level_b_dl_wrapper_inst/rx_hd_type2_to_type1_inst/rx_hd_lbdl_sdpb_odd_inst0/sdpx9b_inst_4 |
| Launch Clk | sdi_phy_rx_clk:[R] |
| Latch Clk | sdi_phy_rx_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sdi_phy_rx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1923 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_RX_O_FABRIC_CLK |
| 0.672 | 0.672 | tNET | RR | 1 | R39C47[2][A] | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_hd_level_b_dl_wrapper_inst/rx_hd_type2_to_type1_inst/datas1_d2_2_s0/CLK |
| 0.813 | 0.141 | tC2Q | RF | 3 | R39C47[2][A] | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_hd_level_b_dl_wrapper_inst/rx_hd_type2_to_type1_inst/datas1_d2_2_s0/Q |
| 0.913 | 0.100 | tNET | FF | 1 | BSRAM_R38[9] | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_hd_level_b_dl_wrapper_inst/rx_hd_type2_to_type1_inst/rx_hd_lbdl_sdpb_odd_inst0/sdpx9b_inst_4/DI[3] |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sdi_phy_rx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1923 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_RX_O_FABRIC_CLK |
| 0.869 | 0.869 | tNET | RR | 1 | BSRAM_R38[9] | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_hd_level_b_dl_wrapper_inst/rx_hd_type2_to_type1_inst/rx_hd_lbdl_sdpb_odd_inst0/sdpx9b_inst_4/CLKA |
| 0.906 | 0.037 | tHld | 1 | BSRAM_R38[9] | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_hd_level_b_dl_wrapper_inst/rx_hd_type2_to_type1_inst/rx_hd_lbdl_sdpb_odd_inst0/sdpx9b_inst_4 |
Path Statistics:
| Clock Skew | 0.197 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.672, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.100, 41.494%; tC2Q: 0.141, 58.506% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.869, 100.000% |
Path6
Path Summary:
| Slack | 0.010 |
| Data Arrival Time | 0.918 |
| Data Required Time | 0.908 |
| From | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_level_datastream_inst/tx_hd_level_b_dl_sdpb_pro_inst/rd_addr_4_s1 |
| To | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_level_datastream_inst/tx_hd_level_b_dl_sdpb_pro_inst/tx_hd_lbdl_sdpb_inst0/sdpx9b_inst_1 |
| Launch Clk | sdi_phy_tx_clk:[R] |
| Latch Clk | sdi_phy_tx_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sdi_phy_tx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 3886 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK |
| 0.672 | 0.672 | tNET | RR | 1 | R45C32[2][B] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_level_datastream_inst/tx_hd_level_b_dl_sdpb_pro_inst/rd_addr_4_s1/CLK |
| 0.813 | 0.141 | tC2Q | RF | 18 | R45C32[2][B] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_level_datastream_inst/tx_hd_level_b_dl_sdpb_pro_inst/rd_addr_4_s1/Q |
| 0.918 | 0.105 | tNET | FF | 1 | BSRAM_R38[6][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_level_datastream_inst/tx_hd_level_b_dl_sdpb_pro_inst/tx_hd_lbdl_sdpb_inst0/sdpx9b_inst_1/ADB[7] |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sdi_phy_tx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 3886 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK |
| 0.873 | 0.873 | tNET | RR | 1 | BSRAM_R38[6][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_level_datastream_inst/tx_hd_level_b_dl_sdpb_pro_inst/tx_hd_lbdl_sdpb_inst0/sdpx9b_inst_1/CLKB |
| 0.908 | 0.035 | tHld | 1 | BSRAM_R38[6][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_level_datastream_inst/tx_hd_level_b_dl_sdpb_pro_inst/tx_hd_lbdl_sdpb_inst0/sdpx9b_inst_1 |
Path Statistics:
| Clock Skew | 0.201 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.672, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.105, 42.683%; tC2Q: 0.141, 57.317% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.873, 100.000% |
Path7
Path Summary:
| Slack | 0.027 |
| Data Arrival Time | 0.933 |
| Data Required Time | 0.906 |
| From | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_hd_level_b_dl_wrapper_inst/rx_hd_type2_to_type1_inst/datas1_d2_3_s0 |
| To | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_hd_level_b_dl_wrapper_inst/rx_hd_type2_to_type1_inst/rx_hd_lbdl_sdpb_odd_inst0/sdpx9b_inst_4 |
| Launch Clk | sdi_phy_rx_clk:[R] |
| Latch Clk | sdi_phy_rx_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sdi_phy_rx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1923 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_RX_O_FABRIC_CLK |
| 0.672 | 0.672 | tNET | RR | 1 | R39C47[0][A] | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_hd_level_b_dl_wrapper_inst/rx_hd_type2_to_type1_inst/datas1_d2_3_s0/CLK |
| 0.813 | 0.141 | tC2Q | RF | 3 | R39C47[0][A] | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_hd_level_b_dl_wrapper_inst/rx_hd_type2_to_type1_inst/datas1_d2_3_s0/Q |
| 0.933 | 0.120 | tNET | FF | 1 | BSRAM_R38[9] | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_hd_level_b_dl_wrapper_inst/rx_hd_type2_to_type1_inst/rx_hd_lbdl_sdpb_odd_inst0/sdpx9b_inst_4/DI[4] |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sdi_phy_rx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1923 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_RX_O_FABRIC_CLK |
| 0.869 | 0.869 | tNET | RR | 1 | BSRAM_R38[9] | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_hd_level_b_dl_wrapper_inst/rx_hd_type2_to_type1_inst/rx_hd_lbdl_sdpb_odd_inst0/sdpx9b_inst_4/CLKA |
| 0.906 | 0.037 | tHld | 1 | BSRAM_R38[9] | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_hd_level_b_dl_wrapper_inst/rx_hd_type2_to_type1_inst/rx_hd_lbdl_sdpb_odd_inst0/sdpx9b_inst_4 |
Path Statistics:
| Clock Skew | 0.197 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.672, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.120, 45.977%; tC2Q: 0.141, 54.023% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.869, 100.000% |
Path8
Path Summary:
| Slack | 0.027 |
| Data Arrival Time | 0.933 |
| Data Required Time | 0.906 |
| From | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_hd_level_b_dl_wrapper_inst/rx_hd_type2_to_type1_inst/datas1_d2_0_s0 |
| To | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_hd_level_b_dl_wrapper_inst/rx_hd_type2_to_type1_inst/rx_hd_lbdl_sdpb_odd_inst0/sdpx9b_inst_4 |
| Launch Clk | sdi_phy_rx_clk:[R] |
| Latch Clk | sdi_phy_rx_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sdi_phy_rx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1923 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_RX_O_FABRIC_CLK |
| 0.672 | 0.672 | tNET | RR | 1 | R39C47[3][A] | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_hd_level_b_dl_wrapper_inst/rx_hd_type2_to_type1_inst/datas1_d2_0_s0/CLK |
| 0.813 | 0.141 | tC2Q | RF | 3 | R39C47[3][A] | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_hd_level_b_dl_wrapper_inst/rx_hd_type2_to_type1_inst/datas1_d2_0_s0/Q |
| 0.933 | 0.120 | tNET | FF | 1 | BSRAM_R38[9] | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_hd_level_b_dl_wrapper_inst/rx_hd_type2_to_type1_inst/rx_hd_lbdl_sdpb_odd_inst0/sdpx9b_inst_4/DI[1] |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sdi_phy_rx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1923 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_RX_O_FABRIC_CLK |
| 0.869 | 0.869 | tNET | RR | 1 | BSRAM_R38[9] | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_hd_level_b_dl_wrapper_inst/rx_hd_type2_to_type1_inst/rx_hd_lbdl_sdpb_odd_inst0/sdpx9b_inst_4/CLKA |
| 0.906 | 0.037 | tHld | 1 | BSRAM_R38[9] | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_hd_level_b_dl_wrapper_inst/rx_hd_type2_to_type1_inst/rx_hd_lbdl_sdpb_odd_inst0/sdpx9b_inst_4 |
Path Statistics:
| Clock Skew | 0.197 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.672, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.120, 45.977%; tC2Q: 0.141, 54.023% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.869, 100.000% |
Path9
Path Summary:
| Slack | 0.030 |
| Data Arrival Time | 0.944 |
| Data Required Time | 0.914 |
| From | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_hd_level_b_dl_wrapper_inst/rx_hd_type2_to_type1_inst/datas2_d2_3_s0 |
| To | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_hd_level_b_dl_wrapper_inst/rx_hd_type2_to_type1_inst/rx_hd_lbdl_sdpb_even_inst0/sdpx9b_inst_3 |
| Launch Clk | sdi_phy_rx_clk:[R] |
| Latch Clk | sdi_phy_rx_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sdi_phy_rx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1923 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_RX_O_FABRIC_CLK |
| 0.680 | 0.680 | tNET | RR | 1 | R39C65[0][A] | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_hd_level_b_dl_wrapper_inst/rx_hd_type2_to_type1_inst/datas2_d2_3_s0/CLK |
| 0.821 | 0.141 | tC2Q | RF | 3 | R39C65[0][A] | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_hd_level_b_dl_wrapper_inst/rx_hd_type2_to_type1_inst/datas2_d2_3_s0/Q |
| 0.944 | 0.123 | tNET | FF | 1 | BSRAM_R38[13] | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_hd_level_b_dl_wrapper_inst/rx_hd_type2_to_type1_inst/rx_hd_lbdl_sdpb_even_inst0/sdpx9b_inst_3/DI[4] |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sdi_phy_rx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1923 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_RX_O_FABRIC_CLK |
| 0.877 | 0.877 | tNET | RR | 1 | BSRAM_R38[13] | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_hd_level_b_dl_wrapper_inst/rx_hd_type2_to_type1_inst/rx_hd_lbdl_sdpb_even_inst0/sdpx9b_inst_3/CLKA |
| 0.914 | 0.037 | tHld | 1 | BSRAM_R38[13] | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_hd_level_b_dl_wrapper_inst/rx_hd_type2_to_type1_inst/rx_hd_lbdl_sdpb_even_inst0/sdpx9b_inst_3 |
Path Statistics:
| Clock Skew | 0.197 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.680, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.123, 46.591%; tC2Q: 0.141, 53.409% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.877, 100.000% |
Path10
Path Summary:
| Slack | 0.030 |
| Data Arrival Time | 0.944 |
| Data Required Time | 0.914 |
| From | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_hd_level_b_dl_wrapper_inst/rx_hd_type2_to_type1_inst/datas2_d2_2_s0 |
| To | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_hd_level_b_dl_wrapper_inst/rx_hd_type2_to_type1_inst/rx_hd_lbdl_sdpb_even_inst0/sdpx9b_inst_3 |
| Launch Clk | sdi_phy_rx_clk:[R] |
| Latch Clk | sdi_phy_rx_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sdi_phy_rx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1923 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_RX_O_FABRIC_CLK |
| 0.680 | 0.680 | tNET | RR | 1 | R39C65[2][A] | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_hd_level_b_dl_wrapper_inst/rx_hd_type2_to_type1_inst/datas2_d2_2_s0/CLK |
| 0.821 | 0.141 | tC2Q | RF | 3 | R39C65[2][A] | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_hd_level_b_dl_wrapper_inst/rx_hd_type2_to_type1_inst/datas2_d2_2_s0/Q |
| 0.944 | 0.123 | tNET | FF | 1 | BSRAM_R38[13] | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_hd_level_b_dl_wrapper_inst/rx_hd_type2_to_type1_inst/rx_hd_lbdl_sdpb_even_inst0/sdpx9b_inst_3/DI[3] |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sdi_phy_rx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1923 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_RX_O_FABRIC_CLK |
| 0.877 | 0.877 | tNET | RR | 1 | BSRAM_R38[13] | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_hd_level_b_dl_wrapper_inst/rx_hd_type2_to_type1_inst/rx_hd_lbdl_sdpb_even_inst0/sdpx9b_inst_3/CLKA |
| 0.914 | 0.037 | tHld | 1 | BSRAM_R38[13] | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_hd_level_b_dl_wrapper_inst/rx_hd_type2_to_type1_inst/rx_hd_lbdl_sdpb_even_inst0/sdpx9b_inst_3 |
Path Statistics:
| Clock Skew | 0.197 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.680, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.123, 46.591%; tC2Q: 0.141, 53.409% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.877, 100.000% |
Path11
Path Summary:
| Slack | 0.030 |
| Data Arrival Time | 0.944 |
| Data Required Time | 0.914 |
| From | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_hd_level_b_dl_wrapper_inst/rx_hd_type2_to_type1_inst/datas2_d2_0_s0 |
| To | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_hd_level_b_dl_wrapper_inst/rx_hd_type2_to_type1_inst/rx_hd_lbdl_sdpb_even_inst0/sdpx9b_inst_3 |
| Launch Clk | sdi_phy_rx_clk:[R] |
| Latch Clk | sdi_phy_rx_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sdi_phy_rx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1923 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_RX_O_FABRIC_CLK |
| 0.680 | 0.680 | tNET | RR | 1 | R39C65[0][B] | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_hd_level_b_dl_wrapper_inst/rx_hd_type2_to_type1_inst/datas2_d2_0_s0/CLK |
| 0.821 | 0.141 | tC2Q | RF | 3 | R39C65[0][B] | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_hd_level_b_dl_wrapper_inst/rx_hd_type2_to_type1_inst/datas2_d2_0_s0/Q |
| 0.944 | 0.123 | tNET | FF | 1 | BSRAM_R38[13] | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_hd_level_b_dl_wrapper_inst/rx_hd_type2_to_type1_inst/rx_hd_lbdl_sdpb_even_inst0/sdpx9b_inst_3/DI[1] |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sdi_phy_rx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1923 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_RX_O_FABRIC_CLK |
| 0.877 | 0.877 | tNET | RR | 1 | BSRAM_R38[13] | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_hd_level_b_dl_wrapper_inst/rx_hd_type2_to_type1_inst/rx_hd_lbdl_sdpb_even_inst0/sdpx9b_inst_3/CLKA |
| 0.914 | 0.037 | tHld | 1 | BSRAM_R38[13] | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_hd_level_b_dl_wrapper_inst/rx_hd_type2_to_type1_inst/rx_hd_lbdl_sdpb_even_inst0/sdpx9b_inst_3 |
Path Statistics:
| Clock Skew | 0.197 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.680, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.123, 46.591%; tC2Q: 0.141, 53.409% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.877, 100.000% |
Path12
Path Summary:
| Slack | 0.030 |
| Data Arrival Time | 0.936 |
| Data Required Time | 0.906 |
| From | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_hd_level_b_dl_wrapper_inst/rx_hd_type2_to_type1_inst/datas1_d2_5_s0 |
| To | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_hd_level_b_dl_wrapper_inst/rx_hd_type2_to_type1_inst/rx_hd_lbdl_sdpb_odd_inst0/sdpx9b_inst_4 |
| Launch Clk | sdi_phy_rx_clk:[R] |
| Latch Clk | sdi_phy_rx_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sdi_phy_rx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1923 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_RX_O_FABRIC_CLK |
| 0.672 | 0.672 | tNET | RR | 1 | R39C47[2][B] | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_hd_level_b_dl_wrapper_inst/rx_hd_type2_to_type1_inst/datas1_d2_5_s0/CLK |
| 0.813 | 0.141 | tC2Q | RF | 3 | R39C47[2][B] | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_hd_level_b_dl_wrapper_inst/rx_hd_type2_to_type1_inst/datas1_d2_5_s0/Q |
| 0.936 | 0.123 | tNET | FF | 1 | BSRAM_R38[9] | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_hd_level_b_dl_wrapper_inst/rx_hd_type2_to_type1_inst/rx_hd_lbdl_sdpb_odd_inst0/sdpx9b_inst_4/DI[6] |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sdi_phy_rx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1923 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_RX_O_FABRIC_CLK |
| 0.869 | 0.869 | tNET | RR | 1 | BSRAM_R38[9] | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_hd_level_b_dl_wrapper_inst/rx_hd_type2_to_type1_inst/rx_hd_lbdl_sdpb_odd_inst0/sdpx9b_inst_4/CLKA |
| 0.906 | 0.037 | tHld | 1 | BSRAM_R38[9] | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_hd_level_b_dl_wrapper_inst/rx_hd_type2_to_type1_inst/rx_hd_lbdl_sdpb_odd_inst0/sdpx9b_inst_4 |
Path Statistics:
| Clock Skew | 0.197 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.672, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.123, 46.591%; tC2Q: 0.141, 53.409% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.869, 100.000% |
Path13
Path Summary:
| Slack | 0.030 |
| Data Arrival Time | 0.936 |
| Data Required Time | 0.906 |
| From | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_hd_level_b_dl_wrapper_inst/rx_hd_type2_to_type1_inst/datas1_d2_1_s0 |
| To | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_hd_level_b_dl_wrapper_inst/rx_hd_type2_to_type1_inst/rx_hd_lbdl_sdpb_odd_inst0/sdpx9b_inst_4 |
| Launch Clk | sdi_phy_rx_clk:[R] |
| Latch Clk | sdi_phy_rx_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sdi_phy_rx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1923 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_RX_O_FABRIC_CLK |
| 0.672 | 0.672 | tNET | RR | 1 | R39C47[1][B] | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_hd_level_b_dl_wrapper_inst/rx_hd_type2_to_type1_inst/datas1_d2_1_s0/CLK |
| 0.813 | 0.141 | tC2Q | RF | 3 | R39C47[1][B] | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_hd_level_b_dl_wrapper_inst/rx_hd_type2_to_type1_inst/datas1_d2_1_s0/Q |
| 0.936 | 0.123 | tNET | FF | 1 | BSRAM_R38[9] | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_hd_level_b_dl_wrapper_inst/rx_hd_type2_to_type1_inst/rx_hd_lbdl_sdpb_odd_inst0/sdpx9b_inst_4/DI[2] |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sdi_phy_rx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1923 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_RX_O_FABRIC_CLK |
| 0.869 | 0.869 | tNET | RR | 1 | BSRAM_R38[9] | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_hd_level_b_dl_wrapper_inst/rx_hd_type2_to_type1_inst/rx_hd_lbdl_sdpb_odd_inst0/sdpx9b_inst_4/CLKA |
| 0.906 | 0.037 | tHld | 1 | BSRAM_R38[9] | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_hd_level_b_dl_wrapper_inst/rx_hd_type2_to_type1_inst/rx_hd_lbdl_sdpb_odd_inst0/sdpx9b_inst_4 |
Path Statistics:
| Clock Skew | 0.197 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.672, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.123, 46.591%; tC2Q: 0.141, 53.409% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.869, 100.000% |
Path14
Path Summary:
| Slack | 0.033 |
| Data Arrival Time | 0.943 |
| Data Required Time | 0.910 |
| From | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_hd_level_b_dl_wrapper_inst/rx_hd_type2_to_type1_inst/datas2_d1_0_s0 |
| To | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_hd_level_b_dl_wrapper_inst/rx_hd_type2_to_type1_inst/rx_hd_lbdl_sdpb_even_inst0/sdpx9b_inst_2 |
| Launch Clk | sdi_phy_rx_clk:[R] |
| Latch Clk | sdi_phy_rx_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sdi_phy_rx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1923 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_RX_O_FABRIC_CLK |
| 0.676 | 0.676 | tNET | RR | 1 | R39C62[0][B] | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_hd_level_b_dl_wrapper_inst/rx_hd_type2_to_type1_inst/datas2_d1_0_s0/CLK |
| 0.817 | 0.141 | tC2Q | RF | 4 | R39C62[0][B] | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_hd_level_b_dl_wrapper_inst/rx_hd_type2_to_type1_inst/datas2_d1_0_s0/Q |
| 0.943 | 0.126 | tNET | FF | 1 | BSRAM_R38[12][B] | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_hd_level_b_dl_wrapper_inst/rx_hd_type2_to_type1_inst/rx_hd_lbdl_sdpb_even_inst0/sdpx9b_inst_2/DI[0] |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sdi_phy_rx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1923 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_RX_O_FABRIC_CLK |
| 0.873 | 0.873 | tNET | RR | 1 | BSRAM_R38[12][B] | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_hd_level_b_dl_wrapper_inst/rx_hd_type2_to_type1_inst/rx_hd_lbdl_sdpb_even_inst0/sdpx9b_inst_2/CLKA |
| 0.910 | 0.037 | tHld | 1 | BSRAM_R38[12][B] | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_hd_level_b_dl_wrapper_inst/rx_hd_type2_to_type1_inst/rx_hd_lbdl_sdpb_even_inst0/sdpx9b_inst_2 |
Path Statistics:
| Clock Skew | 0.197 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.676, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.126, 47.191%; tC2Q: 0.141, 52.809% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.873, 100.000% |
Path15
Path Summary:
| Slack | 0.070 |
| Data Arrival Time | 0.984 |
| Data Required Time | 0.914 |
| From | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_hd_level_b_dl_wrapper_inst/rx_hd_type2_to_type1_inst/datas1_d1_2_s0 |
| To | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_hd_level_b_dl_wrapper_inst/rx_hd_type2_to_type1_inst/rx_hd_lbdl_sdpb_odd_inst0/sdpx9b_inst_2 |
| Launch Clk | sdi_phy_rx_clk:[R] |
| Latch Clk | sdi_phy_rx_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sdi_phy_rx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1923 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_RX_O_FABRIC_CLK |
| 0.676 | 0.676 | tNET | RR | 1 | R40C54[1][A] | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_hd_level_b_dl_wrapper_inst/rx_hd_type2_to_type1_inst/datas1_d1_2_s0/CLK |
| 0.817 | 0.141 | tC2Q | RF | 4 | R40C54[1][A] | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_hd_level_b_dl_wrapper_inst/rx_hd_type2_to_type1_inst/datas1_d1_2_s0/Q |
| 0.984 | 0.167 | tNET | FF | 1 | BSRAM_R38[10][B] | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_hd_level_b_dl_wrapper_inst/rx_hd_type2_to_type1_inst/rx_hd_lbdl_sdpb_odd_inst0/sdpx9b_inst_2/DI[2] |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sdi_phy_rx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1923 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_RX_O_FABRIC_CLK |
| 0.877 | 0.877 | tNET | RR | 1 | BSRAM_R38[10][B] | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_hd_level_b_dl_wrapper_inst/rx_hd_type2_to_type1_inst/rx_hd_lbdl_sdpb_odd_inst0/sdpx9b_inst_2/CLKA |
| 0.914 | 0.037 | tHld | 1 | BSRAM_R38[10][B] | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_hd_level_b_dl_wrapper_inst/rx_hd_type2_to_type1_inst/rx_hd_lbdl_sdpb_odd_inst0/sdpx9b_inst_2 |
Path Statistics:
| Clock Skew | 0.201 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.676, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.167, 54.221%; tC2Q: 0.141, 45.779% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.877, 100.000% |
Path16
Path Summary:
| Slack | 0.070 |
| Data Arrival Time | 0.980 |
| Data Required Time | 0.910 |
| From | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_hd_level_b_dl_wrapper_inst/rx_hd_type2_to_type1_inst/datas2_d1_2_s0 |
| To | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_hd_level_b_dl_wrapper_inst/rx_hd_type2_to_type1_inst/rx_hd_lbdl_sdpb_even_inst0/sdpx9b_inst_2 |
| Launch Clk | sdi_phy_rx_clk:[R] |
| Latch Clk | sdi_phy_rx_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sdi_phy_rx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1923 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_RX_O_FABRIC_CLK |
| 0.672 | 0.672 | tNET | RR | 1 | R39C63[0][A] | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_hd_level_b_dl_wrapper_inst/rx_hd_type2_to_type1_inst/datas2_d1_2_s0/CLK |
| 0.813 | 0.141 | tC2Q | RF | 4 | R39C63[0][A] | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_hd_level_b_dl_wrapper_inst/rx_hd_type2_to_type1_inst/datas2_d1_2_s0/Q |
| 0.980 | 0.167 | tNET | FF | 1 | BSRAM_R38[12][B] | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_hd_level_b_dl_wrapper_inst/rx_hd_type2_to_type1_inst/rx_hd_lbdl_sdpb_even_inst0/sdpx9b_inst_2/DI[2] |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sdi_phy_rx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1923 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_RX_O_FABRIC_CLK |
| 0.873 | 0.873 | tNET | RR | 1 | BSRAM_R38[12][B] | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_hd_level_b_dl_wrapper_inst/rx_hd_type2_to_type1_inst/rx_hd_lbdl_sdpb_even_inst0/sdpx9b_inst_2/CLKA |
| 0.910 | 0.037 | tHld | 1 | BSRAM_R38[12][B] | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_hd_level_b_dl_wrapper_inst/rx_hd_type2_to_type1_inst/rx_hd_lbdl_sdpb_even_inst0/sdpx9b_inst_2 |
Path Statistics:
| Clock Skew | 0.201 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.672, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.167, 54.221%; tC2Q: 0.141, 45.779% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.873, 100.000% |
Path17
Path Summary:
| Slack | 0.084 |
| Data Arrival Time | 0.994 |
| Data Required Time | 0.910 |
| From | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_level_datastream_inst/tx_hd_level_b_dl_sdpb_pro_inst/wr_addr_5_s0 |
| To | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_level_datastream_inst/tx_hd_level_b_dl_sdpb_pro_inst/tx_hd_lbdl_sdpb_inst1/sdpx9b_inst_4 |
| Launch Clk | sdi_phy_tx_clk:[R] |
| Latch Clk | sdi_phy_tx_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sdi_phy_tx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 3886 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK |
| 0.676 | 0.676 | tNET | RR | 1 | R45C35[1][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_level_datastream_inst/tx_hd_level_b_dl_sdpb_pro_inst/wr_addr_5_s0/CLK |
| 0.817 | 0.141 | tC2Q | RF | 17 | R45C35[1][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_level_datastream_inst/tx_hd_level_b_dl_sdpb_pro_inst/wr_addr_5_s0/Q |
| 0.994 | 0.177 | tNET | FF | 1 | BSRAM_R38[6][B] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_level_datastream_inst/tx_hd_level_b_dl_sdpb_pro_inst/tx_hd_lbdl_sdpb_inst1/sdpx9b_inst_4/ADA[8] |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sdi_phy_tx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 3886 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK |
| 0.873 | 0.873 | tNET | RR | 1 | BSRAM_R38[6][B] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_level_datastream_inst/tx_hd_level_b_dl_sdpb_pro_inst/tx_hd_lbdl_sdpb_inst1/sdpx9b_inst_4/CLKA |
| 0.910 | 0.037 | tHld | 1 | BSRAM_R38[6][B] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_level_datastream_inst/tx_hd_level_b_dl_sdpb_pro_inst/tx_hd_lbdl_sdpb_inst1/sdpx9b_inst_4 |
Path Statistics:
| Clock Skew | 0.197 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.676, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.177, 55.660%; tC2Q: 0.141, 44.340% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.873, 100.000% |
Path18
Path Summary:
| Slack | 0.097 |
| Data Arrival Time | 1.009 |
| Data Required Time | 0.912 |
| From | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_level_datastream_inst/tx_hd_level_b_dl_sdpb_pro_inst/rd_addr_0_s3 |
| To | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_level_datastream_inst/tx_hd_level_b_dl_sdpb_pro_inst/tx_hd_lbdl_sdpb_inst1/sdpx9b_inst_0 |
| Launch Clk | sdi_phy_tx_clk:[R] |
| Latch Clk | sdi_phy_tx_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sdi_phy_tx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 3886 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK |
| 0.672 | 0.672 | tNET | RR | 1 | R45C32[0][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_level_datastream_inst/tx_hd_level_b_dl_sdpb_pro_inst/rd_addr_0_s3/CLK |
| 0.816 | 0.144 | tC2Q | RR | 19 | R45C32[0][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_level_datastream_inst/tx_hd_level_b_dl_sdpb_pro_inst/rd_addr_0_s3/Q |
| 1.009 | 0.193 | tNET | RR | 1 | BSRAM_R38[5] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_level_datastream_inst/tx_hd_level_b_dl_sdpb_pro_inst/tx_hd_lbdl_sdpb_inst1/sdpx9b_inst_0/ADB[3] |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sdi_phy_tx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 3886 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK |
| 0.877 | 0.877 | tNET | RR | 1 | BSRAM_R38[5] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_level_datastream_inst/tx_hd_level_b_dl_sdpb_pro_inst/tx_hd_lbdl_sdpb_inst1/sdpx9b_inst_0/CLKB |
| 0.912 | 0.035 | tHld | 1 | BSRAM_R38[5] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_level_datastream_inst/tx_hd_level_b_dl_sdpb_pro_inst/tx_hd_lbdl_sdpb_inst1/sdpx9b_inst_0 |
Path Statistics:
| Clock Skew | 0.205 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.672, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.193, 57.270%; tC2Q: 0.144, 42.730% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.877, 100.000% |
Path19
Path Summary:
| Slack | 0.103 |
| Data Arrival Time | 1.013 |
| Data Required Time | 0.910 |
| From | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_level_datastream_inst/tx_hd_level_b_dl_sdpb_pro_inst/datas2_d1_6_s0 |
| To | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_level_datastream_inst/tx_hd_level_b_dl_sdpb_pro_inst/tx_hd_lbdl_sdpb_inst1/sdpx9b_inst_4 |
| Launch Clk | sdi_phy_tx_clk:[R] |
| Latch Clk | sdi_phy_tx_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sdi_phy_tx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 3886 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK |
| 0.680 | 0.680 | tNET | RR | 1 | R50C34[3][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_level_datastream_inst/tx_hd_level_b_dl_sdpb_pro_inst/datas2_d1_6_s0/CLK |
| 0.824 | 0.144 | tC2Q | RR | 6 | R50C34[3][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_level_datastream_inst/tx_hd_level_b_dl_sdpb_pro_inst/datas2_d1_6_s0/Q |
| 1.013 | 0.189 | tNET | RR | 1 | BSRAM_R38[6][B] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_level_datastream_inst/tx_hd_level_b_dl_sdpb_pro_inst/tx_hd_lbdl_sdpb_inst1/sdpx9b_inst_4/DI[7] |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sdi_phy_tx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 3886 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK |
| 0.873 | 0.873 | tNET | RR | 1 | BSRAM_R38[6][B] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_level_datastream_inst/tx_hd_level_b_dl_sdpb_pro_inst/tx_hd_lbdl_sdpb_inst1/sdpx9b_inst_4/CLKA |
| 0.910 | 0.037 | tHld | 1 | BSRAM_R38[6][B] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_level_datastream_inst/tx_hd_level_b_dl_sdpb_pro_inst/tx_hd_lbdl_sdpb_inst1/sdpx9b_inst_4 |
Path Statistics:
| Clock Skew | 0.193 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.680, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.189, 56.757%; tC2Q: 0.144, 43.243% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.873, 100.000% |
Path20
Path Summary:
| Slack | 0.105 |
| Data Arrival Time | 1.019 |
| Data Required Time | 0.914 |
| From | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_hd_level_b_dl_wrapper_inst/rx_hd_type2_to_type1_inst/datas1_d1_5_s0 |
| To | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_hd_level_b_dl_wrapper_inst/rx_hd_type2_to_type1_inst/rx_hd_lbdl_sdpb_odd_inst0/sdpx9b_inst_2 |
| Launch Clk | sdi_phy_rx_clk:[R] |
| Latch Clk | sdi_phy_rx_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sdi_phy_rx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1923 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_RX_O_FABRIC_CLK |
| 0.676 | 0.676 | tNET | RR | 1 | R39C52[1][A] | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_hd_level_b_dl_wrapper_inst/rx_hd_type2_to_type1_inst/datas1_d1_5_s0/CLK |
| 0.820 | 0.144 | tC2Q | RR | 4 | R39C52[1][A] | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_hd_level_b_dl_wrapper_inst/rx_hd_type2_to_type1_inst/datas1_d1_5_s0/Q |
| 1.019 | 0.199 | tNET | RR | 1 | BSRAM_R38[10][B] | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_hd_level_b_dl_wrapper_inst/rx_hd_type2_to_type1_inst/rx_hd_lbdl_sdpb_odd_inst0/sdpx9b_inst_2/DI[5] |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sdi_phy_rx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1923 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_RX_O_FABRIC_CLK |
| 0.877 | 0.877 | tNET | RR | 1 | BSRAM_R38[10][B] | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_hd_level_b_dl_wrapper_inst/rx_hd_type2_to_type1_inst/rx_hd_lbdl_sdpb_odd_inst0/sdpx9b_inst_2/CLKA |
| 0.914 | 0.037 | tHld | 1 | BSRAM_R38[10][B] | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_hd_level_b_dl_wrapper_inst/rx_hd_type2_to_type1_inst/rx_hd_lbdl_sdpb_odd_inst0/sdpx9b_inst_2 |
Path Statistics:
| Clock Skew | 0.201 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.676, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.199, 58.017%; tC2Q: 0.144, 41.983% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.877, 100.000% |
Path21
Path Summary:
| Slack | 0.106 |
| Data Arrival Time | 1.016 |
| Data Required Time | 0.910 |
| From | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_level_datastream_inst/tx_hd_level_b_dl_sdpb_pro_inst/wr_addr_4_s0 |
| To | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_level_datastream_inst/tx_hd_level_b_dl_sdpb_pro_inst/tx_hd_lbdl_sdpb_inst1/sdpx9b_inst_4 |
| Launch Clk | sdi_phy_tx_clk:[R] |
| Latch Clk | sdi_phy_tx_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sdi_phy_tx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 3886 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK |
| 0.676 | 0.676 | tNET | RR | 1 | R46C33[3][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_level_datastream_inst/tx_hd_level_b_dl_sdpb_pro_inst/wr_addr_4_s0/CLK |
| 0.820 | 0.144 | tC2Q | RR | 18 | R46C33[3][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_level_datastream_inst/tx_hd_level_b_dl_sdpb_pro_inst/wr_addr_4_s0/Q |
| 1.016 | 0.196 | tNET | RR | 1 | BSRAM_R38[6][B] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_level_datastream_inst/tx_hd_level_b_dl_sdpb_pro_inst/tx_hd_lbdl_sdpb_inst1/sdpx9b_inst_4/ADA[7] |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sdi_phy_tx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 3886 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK |
| 0.873 | 0.873 | tNET | RR | 1 | BSRAM_R38[6][B] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_level_datastream_inst/tx_hd_level_b_dl_sdpb_pro_inst/tx_hd_lbdl_sdpb_inst1/sdpx9b_inst_4/CLKA |
| 0.910 | 0.037 | tHld | 1 | BSRAM_R38[6][B] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_level_datastream_inst/tx_hd_level_b_dl_sdpb_pro_inst/tx_hd_lbdl_sdpb_inst1/sdpx9b_inst_4 |
Path Statistics:
| Clock Skew | 0.197 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.676, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.196, 57.647%; tC2Q: 0.144, 42.353% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.873, 100.000% |
Path22
Path Summary:
| Slack | 0.107 |
| Data Arrival Time | 1.015 |
| Data Required Time | 0.908 |
| From | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_level_datastream_inst/tx_hd_level_b_dl_sdpb_pro_inst/rd_addr_1_s1 |
| To | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_level_datastream_inst/tx_hd_level_b_dl_sdpb_pro_inst/tx_hd_lbdl_sdpb_inst0/sdpx9b_inst_1 |
| Launch Clk | sdi_phy_tx_clk:[R] |
| Latch Clk | sdi_phy_tx_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sdi_phy_tx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 3886 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK |
| 0.672 | 0.672 | tNET | RR | 1 | R45C32[1][B] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_level_datastream_inst/tx_hd_level_b_dl_sdpb_pro_inst/rd_addr_1_s1/CLK |
| 0.816 | 0.144 | tC2Q | RR | 18 | R45C32[1][B] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_level_datastream_inst/tx_hd_level_b_dl_sdpb_pro_inst/rd_addr_1_s1/Q |
| 1.015 | 0.199 | tNET | RR | 1 | BSRAM_R38[6][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_level_datastream_inst/tx_hd_level_b_dl_sdpb_pro_inst/tx_hd_lbdl_sdpb_inst0/sdpx9b_inst_1/ADB[4] |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sdi_phy_tx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 3886 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK |
| 0.873 | 0.873 | tNET | RR | 1 | BSRAM_R38[6][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_level_datastream_inst/tx_hd_level_b_dl_sdpb_pro_inst/tx_hd_lbdl_sdpb_inst0/sdpx9b_inst_1/CLKB |
| 0.908 | 0.035 | tHld | 1 | BSRAM_R38[6][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_level_datastream_inst/tx_hd_level_b_dl_sdpb_pro_inst/tx_hd_lbdl_sdpb_inst0/sdpx9b_inst_1 |
Path Statistics:
| Clock Skew | 0.201 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.672, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.199, 58.017%; tC2Q: 0.144, 41.983% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.873, 100.000% |
Path23
Path Summary:
| Slack | 0.108 |
| Data Arrival Time | 1.020 |
| Data Required Time | 0.912 |
| From | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_level_datastream_inst/tx_hd_level_b_dl_sdpb_pro_inst/rd_addr_7_s1 |
| To | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_level_datastream_inst/tx_hd_level_b_dl_sdpb_pro_inst/tx_hd_lbdl_sdpb_inst1/sdpx9b_inst_0 |
| Launch Clk | sdi_phy_tx_clk:[R] |
| Latch Clk | sdi_phy_tx_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sdi_phy_tx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 3886 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK |
| 0.676 | 0.676 | tNET | RR | 1 | R44C31[0][B] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_level_datastream_inst/tx_hd_level_b_dl_sdpb_pro_inst/rd_addr_7_s1/CLK |
| 0.820 | 0.144 | tC2Q | RR | 18 | R44C31[0][B] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_level_datastream_inst/tx_hd_level_b_dl_sdpb_pro_inst/rd_addr_7_s1/Q |
| 1.020 | 0.200 | tNET | RR | 1 | BSRAM_R38[5] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_level_datastream_inst/tx_hd_level_b_dl_sdpb_pro_inst/tx_hd_lbdl_sdpb_inst1/sdpx9b_inst_0/ADB[10] |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sdi_phy_tx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 3886 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK |
| 0.877 | 0.877 | tNET | RR | 1 | BSRAM_R38[5] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_level_datastream_inst/tx_hd_level_b_dl_sdpb_pro_inst/tx_hd_lbdl_sdpb_inst1/sdpx9b_inst_0/CLKB |
| 0.912 | 0.035 | tHld | 1 | BSRAM_R38[5] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_level_datastream_inst/tx_hd_level_b_dl_sdpb_pro_inst/tx_hd_lbdl_sdpb_inst1/sdpx9b_inst_0 |
Path Statistics:
| Clock Skew | 0.201 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.676, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.200, 58.140%; tC2Q: 0.144, 41.860% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.877, 100.000% |
Path24
Path Summary:
| Slack | 0.109 |
| Data Arrival Time | 1.019 |
| Data Required Time | 0.910 |
| From | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_hd_level_b_dl_wrapper_inst/rx_hd_type2_to_type1_inst/datas1_d1_5_s0 |
| To | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_hd_level_b_dl_wrapper_inst/rx_hd_type2_to_type1_inst/rx_hd_lbdl_sdpb_odd_inst0/sdpx9b_inst_1 |
| Launch Clk | sdi_phy_rx_clk:[R] |
| Latch Clk | sdi_phy_rx_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sdi_phy_rx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1923 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_RX_O_FABRIC_CLK |
| 0.676 | 0.676 | tNET | RR | 1 | R39C52[1][A] | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_hd_level_b_dl_wrapper_inst/rx_hd_type2_to_type1_inst/datas1_d1_5_s0/CLK |
| 0.820 | 0.144 | tC2Q | RR | 4 | R39C52[1][A] | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_hd_level_b_dl_wrapper_inst/rx_hd_type2_to_type1_inst/datas1_d1_5_s0/Q |
| 1.019 | 0.199 | tNET | RR | 1 | BSRAM_R38[10][A] | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_hd_level_b_dl_wrapper_inst/rx_hd_type2_to_type1_inst/rx_hd_lbdl_sdpb_odd_inst0/sdpx9b_inst_1/DI[5] |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sdi_phy_rx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1923 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_RX_O_FABRIC_CLK |
| 0.873 | 0.873 | tNET | RR | 1 | BSRAM_R38[10][A] | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_hd_level_b_dl_wrapper_inst/rx_hd_type2_to_type1_inst/rx_hd_lbdl_sdpb_odd_inst0/sdpx9b_inst_1/CLKA |
| 0.910 | 0.037 | tHld | 1 | BSRAM_R38[10][A] | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_hd_level_b_dl_wrapper_inst/rx_hd_type2_to_type1_inst/rx_hd_lbdl_sdpb_odd_inst0/sdpx9b_inst_1 |
Path Statistics:
| Clock Skew | 0.197 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.676, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.199, 58.017%; tC2Q: 0.144, 41.983% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.873, 100.000% |
Path25
Path Summary:
| Slack | 0.114 |
| Data Arrival Time | 1.024 |
| Data Required Time | 0.910 |
| From | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_hd_level_b_dl_wrapper_inst/rx_hd_type2_to_type1_inst/datas1_d1_2_s0 |
| To | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_hd_level_b_dl_wrapper_inst/rx_hd_type2_to_type1_inst/rx_hd_lbdl_sdpb_odd_inst0/sdpx9b_inst_0 |
| Launch Clk | sdi_phy_rx_clk:[R] |
| Latch Clk | sdi_phy_rx_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sdi_phy_rx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1923 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_RX_O_FABRIC_CLK |
| 0.676 | 0.676 | tNET | RR | 1 | R40C54[1][A] | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_hd_level_b_dl_wrapper_inst/rx_hd_type2_to_type1_inst/datas1_d1_2_s0/CLK |
| 0.820 | 0.144 | tC2Q | RR | 4 | R40C54[1][A] | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_hd_level_b_dl_wrapper_inst/rx_hd_type2_to_type1_inst/datas1_d1_2_s0/Q |
| 1.024 | 0.204 | tNET | RR | 1 | BSRAM_R38[11] | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_hd_level_b_dl_wrapper_inst/rx_hd_type2_to_type1_inst/rx_hd_lbdl_sdpb_odd_inst0/sdpx9b_inst_0/DI[2] |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sdi_phy_rx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1923 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_RX_O_FABRIC_CLK |
| 0.873 | 0.873 | tNET | RR | 1 | BSRAM_R38[11] | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_hd_level_b_dl_wrapper_inst/rx_hd_type2_to_type1_inst/rx_hd_lbdl_sdpb_odd_inst0/sdpx9b_inst_0/CLKA |
| 0.910 | 0.037 | tHld | 1 | BSRAM_R38[11] | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_hd_level_b_dl_wrapper_inst/rx_hd_type2_to_type1_inst/rx_hd_lbdl_sdpb_odd_inst0/sdpx9b_inst_0 |
Path Statistics:
| Clock Skew | 0.197 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.676, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.204, 58.621%; tC2Q: 0.144, 41.379% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.873, 100.000% |
Recovery Analysis Report
Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1
Path1
Path Summary:
| Slack | 4.827 |
| Data Arrival Time | 3.716 |
| Data Required Time | 8.542 |
| From | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_add_audio_inst/tx_hd_audio_data_wrapper_inst/tx_hd_audio_data_store_inst/fifo_rest_s0 |
| To | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_add_audio_inst/tx_hd_audio_data_wrapper_inst/tx_hd_audio_data_store_inst/tx_hd_audio_fifo_data/reset_w_1_s0 |
| Launch Clk | sdi_phy_tx_clk:[R] |
| Latch Clk | sdi_phy_tx_clk:[F] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sdi_phy_tx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 3886 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK |
| 2.102 | 2.102 | tNET | RR | 1 | R57C43[2][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_add_audio_inst/tx_hd_audio_data_wrapper_inst/tx_hd_audio_data_store_inst/fifo_rest_s0/CLK |
| 2.484 | 0.382 | tC2Q | RR | 1 | R57C43[2][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_add_audio_inst/tx_hd_audio_data_wrapper_inst/tx_hd_audio_data_store_inst/fifo_rest_s0/Q |
| 2.622 | 0.137 | tNET | RR | 1 | R57C43[3][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_add_audio_inst/tx_hd_audio_data_wrapper_inst/tx_hd_audio_data_store_inst/n176_s0/I0 |
| 3.054 | 0.432 | tINS | RF | 3 | R57C43[3][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_add_audio_inst/tx_hd_audio_data_wrapper_inst/tx_hd_audio_data_store_inst/n176_s0/F |
| 3.716 | 0.661 | tNET | FF | 1 | R64C47[0][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_add_audio_inst/tx_hd_audio_data_wrapper_inst/tx_hd_audio_data_store_inst/tx_hd_audio_fifo_data/reset_w_1_s0/PRESET |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.734 | 6.734 | active clock edge time | ||||
| 6.734 | 0.000 | sdi_phy_tx_clk | ||||
| 6.734 | 0.000 | tCL | FF | 3886 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK |
| 8.835 | 2.101 | tNET | FF | 1 | R64C47[0][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_add_audio_inst/tx_hd_audio_data_wrapper_inst/tx_hd_audio_data_store_inst/tx_hd_audio_fifo_data/reset_w_1_s0/CLK |
| 8.542 | -0.292 | tSu | 1 | R64C47[0][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_add_audio_inst/tx_hd_audio_data_wrapper_inst/tx_hd_audio_data_store_inst/tx_hd_audio_fifo_data/reset_w_1_s0 |
Path Statistics:
| Clock Skew | -0.001 |
| Setup Relationship | 6.734 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.102, 100.000% |
| Arrival Data Path Delay | cell: 0.432, 26.801%; route: 0.799, 49.497%; tC2Q: 0.382, 23.703% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.101, 100.000% |
Path2
Path Summary:
| Slack | 4.958 |
| Data Arrival Time | 3.574 |
| Data Required Time | 8.533 |
| From | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_add_audio_inst/tx_hd_audio_data_wrapper_inst/tx_hd_audio_data_store_inst/fifo_rest_s0 |
| To | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_add_audio_inst/tx_hd_audio_data_wrapper_inst/tx_hd_audio_data_store_inst/tx_hd_audio_fifo_data/reset_r_0_s0 |
| Launch Clk | sdi_phy_tx_clk:[R] |
| Latch Clk | sdi_phy_tx_clk:[F] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sdi_phy_tx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 3886 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK |
| 2.102 | 2.102 | tNET | RR | 1 | R57C43[2][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_add_audio_inst/tx_hd_audio_data_wrapper_inst/tx_hd_audio_data_store_inst/fifo_rest_s0/CLK |
| 2.484 | 0.382 | tC2Q | RR | 1 | R57C43[2][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_add_audio_inst/tx_hd_audio_data_wrapper_inst/tx_hd_audio_data_store_inst/fifo_rest_s0/Q |
| 2.622 | 0.137 | tNET | RR | 1 | R57C43[3][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_add_audio_inst/tx_hd_audio_data_wrapper_inst/tx_hd_audio_data_store_inst/n176_s0/I0 |
| 3.054 | 0.432 | tINS | RF | 3 | R57C43[3][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_add_audio_inst/tx_hd_audio_data_wrapper_inst/tx_hd_audio_data_store_inst/n176_s0/F |
| 3.574 | 0.520 | tNET | FF | 1 | R60C44[1][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_add_audio_inst/tx_hd_audio_data_wrapper_inst/tx_hd_audio_data_store_inst/tx_hd_audio_fifo_data/reset_r_0_s0/PRESET |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.734 | 6.734 | active clock edge time | ||||
| 6.734 | 0.000 | sdi_phy_tx_clk | ||||
| 6.734 | 0.000 | tCL | FF | 3886 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK |
| 8.825 | 2.091 | tNET | FF | 1 | R60C44[1][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_add_audio_inst/tx_hd_audio_data_wrapper_inst/tx_hd_audio_data_store_inst/tx_hd_audio_fifo_data/reset_r_0_s0/CLK |
| 8.533 | -0.292 | tSu | 1 | R60C44[1][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_add_audio_inst/tx_hd_audio_data_wrapper_inst/tx_hd_audio_data_store_inst/tx_hd_audio_fifo_data/reset_r_0_s0 |
Path Statistics:
| Clock Skew | -0.011 |
| Setup Relationship | 6.734 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.102, 100.000% |
| Arrival Data Path Delay | cell: 0.432, 29.372%; route: 0.657, 44.652%; tC2Q: 0.382, 25.976% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.091, 100.000% |
Path3
Path Summary:
| Slack | 4.977 |
| Data Arrival Time | 3.574 |
| Data Required Time | 8.552 |
| From | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_add_audio_inst/tx_hd_audio_data_wrapper_inst/tx_hd_audio_data_store_inst/fifo_rest_s0 |
| To | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_add_audio_inst/tx_hd_audio_data_wrapper_inst/tx_hd_audio_data_store_inst/tx_hd_audio_fifo_data/gowin_replicate_reg_reset_w[1]_1 |
| Launch Clk | sdi_phy_tx_clk:[R] |
| Latch Clk | sdi_phy_tx_clk:[F] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sdi_phy_tx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 3886 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK |
| 2.102 | 2.102 | tNET | RR | 1 | R57C43[2][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_add_audio_inst/tx_hd_audio_data_wrapper_inst/tx_hd_audio_data_store_inst/fifo_rest_s0/CLK |
| 2.484 | 0.382 | tC2Q | RR | 1 | R57C43[2][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_add_audio_inst/tx_hd_audio_data_wrapper_inst/tx_hd_audio_data_store_inst/fifo_rest_s0/Q |
| 2.622 | 0.137 | tNET | RR | 1 | R57C43[3][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_add_audio_inst/tx_hd_audio_data_wrapper_inst/tx_hd_audio_data_store_inst/n176_s0/I0 |
| 3.054 | 0.432 | tINS | RF | 3 | R57C43[3][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_add_audio_inst/tx_hd_audio_data_wrapper_inst/tx_hd_audio_data_store_inst/n176_s0/F |
| 3.574 | 0.520 | tNET | FF | 1 | R60C42[0][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_add_audio_inst/tx_hd_audio_data_wrapper_inst/tx_hd_audio_data_store_inst/tx_hd_audio_fifo_data/gowin_replicate_reg_reset_w[1]_1/PRESET |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.734 | 6.734 | active clock edge time | ||||
| 6.734 | 0.000 | sdi_phy_tx_clk | ||||
| 6.734 | 0.000 | tCL | FF | 3886 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK |
| 8.844 | 2.110 | tNET | FF | 1 | R60C42[0][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_add_audio_inst/tx_hd_audio_data_wrapper_inst/tx_hd_audio_data_store_inst/tx_hd_audio_fifo_data/gowin_replicate_reg_reset_w[1]_1/CLK |
| 8.552 | -0.292 | tSu | 1 | R60C42[0][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_add_audio_inst/tx_hd_audio_data_wrapper_inst/tx_hd_audio_data_store_inst/tx_hd_audio_fifo_data/gowin_replicate_reg_reset_w[1]_1 |
Path Statistics:
| Clock Skew | 0.008 |
| Setup Relationship | 6.734 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.102, 100.000% |
| Arrival Data Path Delay | cell: 0.432, 29.372%; route: 0.657, 44.652%; tC2Q: 0.382, 25.976% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.110, 100.000% |
Path4
Path Summary:
| Slack | 10.160 |
| Data Arrival Time | 5.053 |
| Data Required Time | 15.213 |
| From | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s0 |
| To | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst4/crc_r_6_s0 |
| Launch Clk | sdi_phy_tx_clk:[R] |
| Latch Clk | sdi_phy_tx_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sdi_phy_tx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 3886 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK |
| 2.102 | 2.102 | tNET | RR | 1 | R62C31[0][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s0/CLK |
| 2.484 | 0.382 | tC2Q | RR | 1 | R62C31[0][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s0/Q |
| 2.622 | 0.137 | tNET | RR | 1 | R62C31[2][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst1/n34_s1/I1 |
| 3.002 | 0.380 | tINS | RF | 73 | R62C31[2][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst1/n34_s1/F |
| 5.053 | 2.051 | tNET | FF | 1 | R62C24[1][B] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst4/crc_r_6_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 13.468 | 13.468 | active clock edge time | ||||
| 13.468 | 0.000 | sdi_phy_tx_clk | ||||
| 13.468 | 0.000 | tCL | RR | 3886 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK |
| 15.561 | 2.092 | tNET | RR | 1 | R62C24[1][B] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst4/crc_r_6_s0/CLK |
| 15.213 | -0.347 | tSu | 1 | R62C24[1][B] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst4/crc_r_6_s0 |
Path Statistics:
| Clock Skew | -0.009 |
| Setup Relationship | 13.468 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.102, 100.000% |
| Arrival Data Path Delay | cell: 0.380, 12.876%; route: 2.189, 74.163%; tC2Q: 0.382, 12.961% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.092, 100.000% |
Path5
Path Summary:
| Slack | 10.160 |
| Data Arrival Time | 5.053 |
| Data Required Time | 15.213 |
| From | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s0 |
| To | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst4/crc_r_7_s0 |
| Launch Clk | sdi_phy_tx_clk:[R] |
| Latch Clk | sdi_phy_tx_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sdi_phy_tx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 3886 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK |
| 2.102 | 2.102 | tNET | RR | 1 | R62C31[0][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s0/CLK |
| 2.484 | 0.382 | tC2Q | RR | 1 | R62C31[0][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s0/Q |
| 2.622 | 0.137 | tNET | RR | 1 | R62C31[2][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst1/n34_s1/I1 |
| 3.002 | 0.380 | tINS | RF | 73 | R62C31[2][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst1/n34_s1/F |
| 5.053 | 2.051 | tNET | FF | 1 | R62C24[1][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst4/crc_r_7_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 13.468 | 13.468 | active clock edge time | ||||
| 13.468 | 0.000 | sdi_phy_tx_clk | ||||
| 13.468 | 0.000 | tCL | RR | 3886 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK |
| 15.561 | 2.092 | tNET | RR | 1 | R62C24[1][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst4/crc_r_7_s0/CLK |
| 15.213 | -0.347 | tSu | 1 | R62C24[1][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst4/crc_r_7_s0 |
Path Statistics:
| Clock Skew | -0.009 |
| Setup Relationship | 13.468 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.102, 100.000% |
| Arrival Data Path Delay | cell: 0.380, 12.876%; route: 2.189, 74.163%; tC2Q: 0.382, 12.961% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.092, 100.000% |
Path6
Path Summary:
| Slack | 10.160 |
| Data Arrival Time | 5.053 |
| Data Required Time | 15.213 |
| From | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s0 |
| To | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst4/crc_r_10_s0 |
| Launch Clk | sdi_phy_tx_clk:[R] |
| Latch Clk | sdi_phy_tx_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sdi_phy_tx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 3886 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK |
| 2.102 | 2.102 | tNET | RR | 1 | R62C31[0][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s0/CLK |
| 2.484 | 0.382 | tC2Q | RR | 1 | R62C31[0][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s0/Q |
| 2.622 | 0.137 | tNET | RR | 1 | R62C31[2][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst1/n34_s1/I1 |
| 3.002 | 0.380 | tINS | RF | 73 | R62C31[2][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst1/n34_s1/F |
| 5.053 | 2.051 | tNET | FF | 1 | R62C24[0][B] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst4/crc_r_10_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 13.468 | 13.468 | active clock edge time | ||||
| 13.468 | 0.000 | sdi_phy_tx_clk | ||||
| 13.468 | 0.000 | tCL | RR | 3886 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK |
| 15.561 | 2.092 | tNET | RR | 1 | R62C24[0][B] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst4/crc_r_10_s0/CLK |
| 15.213 | -0.347 | tSu | 1 | R62C24[0][B] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst4/crc_r_10_s0 |
Path Statistics:
| Clock Skew | -0.009 |
| Setup Relationship | 13.468 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.102, 100.000% |
| Arrival Data Path Delay | cell: 0.380, 12.876%; route: 2.189, 74.163%; tC2Q: 0.382, 12.961% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.092, 100.000% |
Path7
Path Summary:
| Slack | 10.160 |
| Data Arrival Time | 5.053 |
| Data Required Time | 15.213 |
| From | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s0 |
| To | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst4/crc_r_11_s0 |
| Launch Clk | sdi_phy_tx_clk:[R] |
| Latch Clk | sdi_phy_tx_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sdi_phy_tx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 3886 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK |
| 2.102 | 2.102 | tNET | RR | 1 | R62C31[0][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s0/CLK |
| 2.484 | 0.382 | tC2Q | RR | 1 | R62C31[0][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s0/Q |
| 2.622 | 0.137 | tNET | RR | 1 | R62C31[2][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst1/n34_s1/I1 |
| 3.002 | 0.380 | tINS | RF | 73 | R62C31[2][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst1/n34_s1/F |
| 5.053 | 2.051 | tNET | FF | 1 | R62C24[0][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst4/crc_r_11_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 13.468 | 13.468 | active clock edge time | ||||
| 13.468 | 0.000 | sdi_phy_tx_clk | ||||
| 13.468 | 0.000 | tCL | RR | 3886 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK |
| 15.561 | 2.092 | tNET | RR | 1 | R62C24[0][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst4/crc_r_11_s0/CLK |
| 15.213 | -0.347 | tSu | 1 | R62C24[0][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst4/crc_r_11_s0 |
Path Statistics:
| Clock Skew | -0.009 |
| Setup Relationship | 13.468 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.102, 100.000% |
| Arrival Data Path Delay | cell: 0.380, 12.876%; route: 2.189, 74.163%; tC2Q: 0.382, 12.961% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.092, 100.000% |
Path8
Path Summary:
| Slack | 10.169 |
| Data Arrival Time | 5.053 |
| Data Required Time | 15.222 |
| From | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s0 |
| To | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst4/crc_r_0_s0 |
| Launch Clk | sdi_phy_tx_clk:[R] |
| Latch Clk | sdi_phy_tx_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sdi_phy_tx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 3886 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK |
| 2.102 | 2.102 | tNET | RR | 1 | R62C31[0][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s0/CLK |
| 2.484 | 0.382 | tC2Q | RR | 1 | R62C31[0][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s0/Q |
| 2.622 | 0.137 | tNET | RR | 1 | R62C31[2][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst1/n34_s1/I1 |
| 3.002 | 0.380 | tINS | RF | 73 | R62C31[2][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst1/n34_s1/F |
| 5.053 | 2.051 | tNET | FF | 1 | R62C23[2][B] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst4/crc_r_0_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 13.468 | 13.468 | active clock edge time | ||||
| 13.468 | 0.000 | sdi_phy_tx_clk | ||||
| 13.468 | 0.000 | tCL | RR | 3886 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK |
| 15.570 | 2.102 | tNET | RR | 1 | R62C23[2][B] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst4/crc_r_0_s0/CLK |
| 15.222 | -0.347 | tSu | 1 | R62C23[2][B] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst4/crc_r_0_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 13.468 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.102, 100.000% |
| Arrival Data Path Delay | cell: 0.380, 12.876%; route: 2.189, 74.163%; tC2Q: 0.382, 12.961% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.102, 100.000% |
Path9
Path Summary:
| Slack | 10.169 |
| Data Arrival Time | 5.053 |
| Data Required Time | 15.222 |
| From | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s0 |
| To | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst4/crc_r_4_s0 |
| Launch Clk | sdi_phy_tx_clk:[R] |
| Latch Clk | sdi_phy_tx_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sdi_phy_tx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 3886 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK |
| 2.102 | 2.102 | tNET | RR | 1 | R62C31[0][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s0/CLK |
| 2.484 | 0.382 | tC2Q | RR | 1 | R62C31[0][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s0/Q |
| 2.622 | 0.137 | tNET | RR | 1 | R62C31[2][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst1/n34_s1/I1 |
| 3.002 | 0.380 | tINS | RF | 73 | R62C31[2][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst1/n34_s1/F |
| 5.053 | 2.051 | tNET | FF | 1 | R62C23[1][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst4/crc_r_4_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 13.468 | 13.468 | active clock edge time | ||||
| 13.468 | 0.000 | sdi_phy_tx_clk | ||||
| 13.468 | 0.000 | tCL | RR | 3886 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK |
| 15.570 | 2.102 | tNET | RR | 1 | R62C23[1][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst4/crc_r_4_s0/CLK |
| 15.222 | -0.347 | tSu | 1 | R62C23[1][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst4/crc_r_4_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 13.468 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.102, 100.000% |
| Arrival Data Path Delay | cell: 0.380, 12.876%; route: 2.189, 74.163%; tC2Q: 0.382, 12.961% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.102, 100.000% |
Path10
Path Summary:
| Slack | 10.169 |
| Data Arrival Time | 5.053 |
| Data Required Time | 15.222 |
| From | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s0 |
| To | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst4/crc_r_5_s0 |
| Launch Clk | sdi_phy_tx_clk:[R] |
| Latch Clk | sdi_phy_tx_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sdi_phy_tx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 3886 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK |
| 2.102 | 2.102 | tNET | RR | 1 | R62C31[0][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s0/CLK |
| 2.484 | 0.382 | tC2Q | RR | 1 | R62C31[0][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s0/Q |
| 2.622 | 0.137 | tNET | RR | 1 | R62C31[2][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst1/n34_s1/I1 |
| 3.002 | 0.380 | tINS | RF | 73 | R62C31[2][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst1/n34_s1/F |
| 5.053 | 2.051 | tNET | FF | 1 | R62C23[3][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst4/crc_r_5_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 13.468 | 13.468 | active clock edge time | ||||
| 13.468 | 0.000 | sdi_phy_tx_clk | ||||
| 13.468 | 0.000 | tCL | RR | 3886 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK |
| 15.570 | 2.102 | tNET | RR | 1 | R62C23[3][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst4/crc_r_5_s0/CLK |
| 15.222 | -0.347 | tSu | 1 | R62C23[3][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst4/crc_r_5_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 13.468 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.102, 100.000% |
| Arrival Data Path Delay | cell: 0.380, 12.876%; route: 2.189, 74.163%; tC2Q: 0.382, 12.961% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.102, 100.000% |
Path11
Path Summary:
| Slack | 10.169 |
| Data Arrival Time | 5.053 |
| Data Required Time | 15.222 |
| From | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s0 |
| To | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst4/crc_r_8_s0 |
| Launch Clk | sdi_phy_tx_clk:[R] |
| Latch Clk | sdi_phy_tx_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sdi_phy_tx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 3886 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK |
| 2.102 | 2.102 | tNET | RR | 1 | R62C31[0][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s0/CLK |
| 2.484 | 0.382 | tC2Q | RR | 1 | R62C31[0][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s0/Q |
| 2.622 | 0.137 | tNET | RR | 1 | R62C31[2][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst1/n34_s1/I1 |
| 3.002 | 0.380 | tINS | RF | 73 | R62C31[2][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst1/n34_s1/F |
| 5.053 | 2.051 | tNET | FF | 1 | R62C23[1][B] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst4/crc_r_8_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 13.468 | 13.468 | active clock edge time | ||||
| 13.468 | 0.000 | sdi_phy_tx_clk | ||||
| 13.468 | 0.000 | tCL | RR | 3886 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK |
| 15.570 | 2.102 | tNET | RR | 1 | R62C23[1][B] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst4/crc_r_8_s0/CLK |
| 15.222 | -0.347 | tSu | 1 | R62C23[1][B] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst4/crc_r_8_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 13.468 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.102, 100.000% |
| Arrival Data Path Delay | cell: 0.380, 12.876%; route: 2.189, 74.163%; tC2Q: 0.382, 12.961% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.102, 100.000% |
Path12
Path Summary:
| Slack | 10.169 |
| Data Arrival Time | 5.053 |
| Data Required Time | 15.222 |
| From | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s0 |
| To | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst4/crc_r_9_s0 |
| Launch Clk | sdi_phy_tx_clk:[R] |
| Latch Clk | sdi_phy_tx_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sdi_phy_tx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 3886 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK |
| 2.102 | 2.102 | tNET | RR | 1 | R62C31[0][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s0/CLK |
| 2.484 | 0.382 | tC2Q | RR | 1 | R62C31[0][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s0/Q |
| 2.622 | 0.137 | tNET | RR | 1 | R62C31[2][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst1/n34_s1/I1 |
| 3.002 | 0.380 | tINS | RF | 73 | R62C31[2][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst1/n34_s1/F |
| 5.053 | 2.051 | tNET | FF | 1 | R62C23[2][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst4/crc_r_9_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 13.468 | 13.468 | active clock edge time | ||||
| 13.468 | 0.000 | sdi_phy_tx_clk | ||||
| 13.468 | 0.000 | tCL | RR | 3886 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK |
| 15.570 | 2.102 | tNET | RR | 1 | R62C23[2][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst4/crc_r_9_s0/CLK |
| 15.222 | -0.347 | tSu | 1 | R62C23[2][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst4/crc_r_9_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 13.468 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.102, 100.000% |
| Arrival Data Path Delay | cell: 0.380, 12.876%; route: 2.189, 74.163%; tC2Q: 0.382, 12.961% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.102, 100.000% |
Path13
Path Summary:
| Slack | 5.140 |
| Data Arrival Time | 10.350 |
| Data Required Time | 15.490 |
| From | sdi_audio_buffer_pro_tx_inst/sdi_audio_buffer_fifo_inst/fifo_inst/reset_r_1_s0 |
| To | sdi_audio_buffer_pro_tx_inst/sdi_audio_buffer_fifo_inst/fifo_inst/gowin_add_SDPB_Equal.mem_Equal.mem_0_1_s |
| Launch Clk | sdi_phy_tx_clk:[F] |
| Latch Clk | sdi_phy_tx_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.734 | 6.734 | active clock edge time | ||||
| 6.734 | 0.000 | sdi_phy_tx_clk | ||||
| 6.734 | 0.000 | tCL | FF | 3886 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK |
| 8.835 | 2.101 | tNET | FF | 1 | R54C49[0][B] | sdi_audio_buffer_pro_tx_inst/sdi_audio_buffer_fifo_inst/fifo_inst/reset_r_1_s0/CLK |
| 9.277 | 0.442 | tC2Q | FF | 34 | R54C49[0][B] | sdi_audio_buffer_pro_tx_inst/sdi_audio_buffer_fifo_inst/fifo_inst/reset_r_1_s0/Q |
| 10.350 | 1.072 | tNET | FF | 16 | BSRAM_R56[13][B] | sdi_audio_buffer_pro_tx_inst/sdi_audio_buffer_fifo_inst/fifo_inst/gowin_add_SDPB_Equal.mem_Equal.mem_0_1_s/RESET |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 13.468 | 13.468 | active clock edge time | ||||
| 13.468 | 0.000 | sdi_phy_tx_clk | ||||
| 13.468 | 0.000 | tCL | RR | 3886 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK |
| 15.570 | 2.102 | tNET | RR | 1 | BSRAM_R56[13][B] | sdi_audio_buffer_pro_tx_inst/sdi_audio_buffer_fifo_inst/fifo_inst/gowin_add_SDPB_Equal.mem_Equal.mem_0_1_s/CLKB |
| 15.490 | -0.080 | tSu | 1 | BSRAM_R56[13][B] | sdi_audio_buffer_pro_tx_inst/sdi_audio_buffer_fifo_inst/fifo_inst/gowin_add_SDPB_Equal.mem_Equal.mem_0_1_s |
Path Statistics:
| Clock Skew | 0.001 |
| Setup Relationship | 6.734 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.101, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.072, 70.792%; tC2Q: 0.442, 29.208% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.102, 100.000% |
Path14
Path Summary:
| Slack | 10.356 |
| Data Arrival Time | 4.867 |
| Data Required Time | 15.222 |
| From | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s0 |
| To | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst3/crc_r_17_s0 |
| Launch Clk | sdi_phy_tx_clk:[R] |
| Latch Clk | sdi_phy_tx_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sdi_phy_tx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 3886 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK |
| 2.102 | 2.102 | tNET | RR | 1 | R62C31[0][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s0/CLK |
| 2.484 | 0.382 | tC2Q | RR | 1 | R62C31[0][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s0/Q |
| 2.622 | 0.137 | tNET | RR | 1 | R62C31[2][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst1/n34_s1/I1 |
| 3.002 | 0.380 | tINS | RF | 73 | R62C31[2][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst1/n34_s1/F |
| 4.867 | 1.865 | tNET | FF | 1 | R58C23[0][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst3/crc_r_17_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 13.468 | 13.468 | active clock edge time | ||||
| 13.468 | 0.000 | sdi_phy_tx_clk | ||||
| 13.468 | 0.000 | tCL | RR | 3886 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK |
| 15.570 | 2.102 | tNET | RR | 1 | R58C23[0][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst3/crc_r_17_s0/CLK |
| 15.222 | -0.347 | tSu | 1 | R58C23[0][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst3/crc_r_17_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 13.468 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.102, 100.000% |
| Arrival Data Path Delay | cell: 0.380, 13.743%; route: 2.002, 72.423%; tC2Q: 0.382, 13.834% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.102, 100.000% |
Path15
Path Summary:
| Slack | 10.356 |
| Data Arrival Time | 4.867 |
| Data Required Time | 15.222 |
| From | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s0 |
| To | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst3/crc_r_1_s0 |
| Launch Clk | sdi_phy_tx_clk:[R] |
| Latch Clk | sdi_phy_tx_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sdi_phy_tx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 3886 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK |
| 2.102 | 2.102 | tNET | RR | 1 | R62C31[0][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s0/CLK |
| 2.484 | 0.382 | tC2Q | RR | 1 | R62C31[0][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s0/Q |
| 2.622 | 0.137 | tNET | RR | 1 | R62C31[2][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst1/n34_s1/I1 |
| 3.002 | 0.380 | tINS | RF | 73 | R62C31[2][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst1/n34_s1/F |
| 4.867 | 1.865 | tNET | FF | 1 | R59C23[1][B] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst3/crc_r_1_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 13.468 | 13.468 | active clock edge time | ||||
| 13.468 | 0.000 | sdi_phy_tx_clk | ||||
| 13.468 | 0.000 | tCL | RR | 3886 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK |
| 15.570 | 2.102 | tNET | RR | 1 | R59C23[1][B] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst3/crc_r_1_s0/CLK |
| 15.222 | -0.347 | tSu | 1 | R59C23[1][B] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst3/crc_r_1_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 13.468 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.102, 100.000% |
| Arrival Data Path Delay | cell: 0.380, 13.743%; route: 2.002, 72.423%; tC2Q: 0.382, 13.834% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.102, 100.000% |
Path16
Path Summary:
| Slack | 10.356 |
| Data Arrival Time | 4.867 |
| Data Required Time | 15.222 |
| From | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s0 |
| To | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst3/crc_r_5_s0 |
| Launch Clk | sdi_phy_tx_clk:[R] |
| Latch Clk | sdi_phy_tx_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sdi_phy_tx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 3886 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK |
| 2.102 | 2.102 | tNET | RR | 1 | R62C31[0][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s0/CLK |
| 2.484 | 0.382 | tC2Q | RR | 1 | R62C31[0][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s0/Q |
| 2.622 | 0.137 | tNET | RR | 1 | R62C31[2][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst1/n34_s1/I1 |
| 3.002 | 0.380 | tINS | RF | 73 | R62C31[2][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst1/n34_s1/F |
| 4.867 | 1.865 | tNET | FF | 1 | R59C23[1][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst3/crc_r_5_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 13.468 | 13.468 | active clock edge time | ||||
| 13.468 | 0.000 | sdi_phy_tx_clk | ||||
| 13.468 | 0.000 | tCL | RR | 3886 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK |
| 15.570 | 2.102 | tNET | RR | 1 | R59C23[1][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst3/crc_r_5_s0/CLK |
| 15.222 | -0.347 | tSu | 1 | R59C23[1][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst3/crc_r_5_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 13.468 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.102, 100.000% |
| Arrival Data Path Delay | cell: 0.380, 13.743%; route: 2.002, 72.423%; tC2Q: 0.382, 13.834% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.102, 100.000% |
Path17
Path Summary:
| Slack | 10.356 |
| Data Arrival Time | 4.867 |
| Data Required Time | 15.222 |
| From | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s0 |
| To | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst3/crc_r_8_s0 |
| Launch Clk | sdi_phy_tx_clk:[R] |
| Latch Clk | sdi_phy_tx_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sdi_phy_tx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 3886 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK |
| 2.102 | 2.102 | tNET | RR | 1 | R62C31[0][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s0/CLK |
| 2.484 | 0.382 | tC2Q | RR | 1 | R62C31[0][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s0/Q |
| 2.622 | 0.137 | tNET | RR | 1 | R62C31[2][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst1/n34_s1/I1 |
| 3.002 | 0.380 | tINS | RF | 73 | R62C31[2][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst1/n34_s1/F |
| 4.867 | 1.865 | tNET | FF | 1 | R59C23[2][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst3/crc_r_8_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 13.468 | 13.468 | active clock edge time | ||||
| 13.468 | 0.000 | sdi_phy_tx_clk | ||||
| 13.468 | 0.000 | tCL | RR | 3886 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK |
| 15.570 | 2.102 | tNET | RR | 1 | R59C23[2][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst3/crc_r_8_s0/CLK |
| 15.222 | -0.347 | tSu | 1 | R59C23[2][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst3/crc_r_8_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 13.468 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.102, 100.000% |
| Arrival Data Path Delay | cell: 0.380, 13.743%; route: 2.002, 72.423%; tC2Q: 0.382, 13.834% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.102, 100.000% |
Path18
Path Summary:
| Slack | 10.356 |
| Data Arrival Time | 4.867 |
| Data Required Time | 15.222 |
| From | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s0 |
| To | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst3/crc_r_9_s0 |
| Launch Clk | sdi_phy_tx_clk:[R] |
| Latch Clk | sdi_phy_tx_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sdi_phy_tx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 3886 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK |
| 2.102 | 2.102 | tNET | RR | 1 | R62C31[0][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s0/CLK |
| 2.484 | 0.382 | tC2Q | RR | 1 | R62C31[0][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s0/Q |
| 2.622 | 0.137 | tNET | RR | 1 | R62C31[2][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst1/n34_s1/I1 |
| 3.002 | 0.380 | tINS | RF | 73 | R62C31[2][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst1/n34_s1/F |
| 4.867 | 1.865 | tNET | FF | 1 | R58C23[1][B] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst3/crc_r_9_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 13.468 | 13.468 | active clock edge time | ||||
| 13.468 | 0.000 | sdi_phy_tx_clk | ||||
| 13.468 | 0.000 | tCL | RR | 3886 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK |
| 15.570 | 2.102 | tNET | RR | 1 | R58C23[1][B] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst3/crc_r_9_s0/CLK |
| 15.222 | -0.347 | tSu | 1 | R58C23[1][B] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst3/crc_r_9_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 13.468 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.102, 100.000% |
| Arrival Data Path Delay | cell: 0.380, 13.743%; route: 2.002, 72.423%; tC2Q: 0.382, 13.834% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.102, 100.000% |
Path19
Path Summary:
| Slack | 10.356 |
| Data Arrival Time | 4.867 |
| Data Required Time | 15.222 |
| From | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s0 |
| To | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst3/crc_r_11_s0 |
| Launch Clk | sdi_phy_tx_clk:[R] |
| Latch Clk | sdi_phy_tx_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sdi_phy_tx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 3886 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK |
| 2.102 | 2.102 | tNET | RR | 1 | R62C31[0][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s0/CLK |
| 2.484 | 0.382 | tC2Q | RR | 1 | R62C31[0][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s0/Q |
| 2.622 | 0.137 | tNET | RR | 1 | R62C31[2][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst1/n34_s1/I1 |
| 3.002 | 0.380 | tINS | RF | 73 | R62C31[2][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst1/n34_s1/F |
| 4.867 | 1.865 | tNET | FF | 1 | R59C23[0][B] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst3/crc_r_11_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 13.468 | 13.468 | active clock edge time | ||||
| 13.468 | 0.000 | sdi_phy_tx_clk | ||||
| 13.468 | 0.000 | tCL | RR | 3886 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK |
| 15.570 | 2.102 | tNET | RR | 1 | R59C23[0][B] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst3/crc_r_11_s0/CLK |
| 15.222 | -0.347 | tSu | 1 | R59C23[0][B] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst3/crc_r_11_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 13.468 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.102, 100.000% |
| Arrival Data Path Delay | cell: 0.380, 13.743%; route: 2.002, 72.423%; tC2Q: 0.382, 13.834% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.102, 100.000% |
Path20
Path Summary:
| Slack | 10.356 |
| Data Arrival Time | 4.867 |
| Data Required Time | 15.222 |
| From | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s0 |
| To | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst3/crc_r_12_s0 |
| Launch Clk | sdi_phy_tx_clk:[R] |
| Latch Clk | sdi_phy_tx_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sdi_phy_tx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 3886 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK |
| 2.102 | 2.102 | tNET | RR | 1 | R62C31[0][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s0/CLK |
| 2.484 | 0.382 | tC2Q | RR | 1 | R62C31[0][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s0/Q |
| 2.622 | 0.137 | tNET | RR | 1 | R62C31[2][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst1/n34_s1/I1 |
| 3.002 | 0.380 | tINS | RF | 73 | R62C31[2][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst1/n34_s1/F |
| 4.867 | 1.865 | tNET | FF | 1 | R59C23[0][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst3/crc_r_12_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 13.468 | 13.468 | active clock edge time | ||||
| 13.468 | 0.000 | sdi_phy_tx_clk | ||||
| 13.468 | 0.000 | tCL | RR | 3886 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK |
| 15.570 | 2.102 | tNET | RR | 1 | R59C23[0][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst3/crc_r_12_s0/CLK |
| 15.222 | -0.347 | tSu | 1 | R59C23[0][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst3/crc_r_12_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 13.468 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.102, 100.000% |
| Arrival Data Path Delay | cell: 0.380, 13.743%; route: 2.002, 72.423%; tC2Q: 0.382, 13.834% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.102, 100.000% |
Path21
Path Summary:
| Slack | 10.356 |
| Data Arrival Time | 4.867 |
| Data Required Time | 15.222 |
| From | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s0 |
| To | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst3/crc_r_13_s0 |
| Launch Clk | sdi_phy_tx_clk:[R] |
| Latch Clk | sdi_phy_tx_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sdi_phy_tx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 3886 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK |
| 2.102 | 2.102 | tNET | RR | 1 | R62C31[0][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s0/CLK |
| 2.484 | 0.382 | tC2Q | RR | 1 | R62C31[0][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s0/Q |
| 2.622 | 0.137 | tNET | RR | 1 | R62C31[2][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst1/n34_s1/I1 |
| 3.002 | 0.380 | tINS | RF | 73 | R62C31[2][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst1/n34_s1/F |
| 4.867 | 1.865 | tNET | FF | 1 | R58C23[1][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst3/crc_r_13_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 13.468 | 13.468 | active clock edge time | ||||
| 13.468 | 0.000 | sdi_phy_tx_clk | ||||
| 13.468 | 0.000 | tCL | RR | 3886 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK |
| 15.570 | 2.102 | tNET | RR | 1 | R58C23[1][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst3/crc_r_13_s0/CLK |
| 15.222 | -0.347 | tSu | 1 | R58C23[1][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst3/crc_r_13_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 13.468 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.102, 100.000% |
| Arrival Data Path Delay | cell: 0.380, 13.743%; route: 2.002, 72.423%; tC2Q: 0.382, 13.834% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.102, 100.000% |
Path22
Path Summary:
| Slack | 10.356 |
| Data Arrival Time | 4.867 |
| Data Required Time | 15.222 |
| From | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s0 |
| To | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst3/crc_r_14_s0 |
| Launch Clk | sdi_phy_tx_clk:[R] |
| Latch Clk | sdi_phy_tx_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sdi_phy_tx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 3886 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK |
| 2.102 | 2.102 | tNET | RR | 1 | R62C31[0][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s0/CLK |
| 2.484 | 0.382 | tC2Q | RR | 1 | R62C31[0][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s0/Q |
| 2.622 | 0.137 | tNET | RR | 1 | R62C31[2][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst1/n34_s1/I1 |
| 3.002 | 0.380 | tINS | RF | 73 | R62C31[2][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst1/n34_s1/F |
| 4.867 | 1.865 | tNET | FF | 1 | R58C23[0][B] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst3/crc_r_14_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 13.468 | 13.468 | active clock edge time | ||||
| 13.468 | 0.000 | sdi_phy_tx_clk | ||||
| 13.468 | 0.000 | tCL | RR | 3886 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK |
| 15.570 | 2.102 | tNET | RR | 1 | R58C23[0][B] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst3/crc_r_14_s0/CLK |
| 15.222 | -0.347 | tSu | 1 | R58C23[0][B] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst3/crc_r_14_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 13.468 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.102, 100.000% |
| Arrival Data Path Delay | cell: 0.380, 13.743%; route: 2.002, 72.423%; tC2Q: 0.382, 13.834% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.102, 100.000% |
Path23
Path Summary:
| Slack | 5.185 |
| Data Arrival Time | 10.047 |
| Data Required Time | 15.232 |
| From | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_add_audio_inst/tx_hd_audio_data_wrapper_inst/tx_hd_audio_data_store_inst/tx_hd_audio_fifo_data/reset_w_1_s0 |
| To | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_add_audio_inst/tx_hd_audio_data_wrapper_inst/tx_hd_audio_data_store_inst/tx_hd_audio_fifo_data/raddr_num_dly_1_s0 |
| Launch Clk | sdi_phy_tx_clk:[F] |
| Latch Clk | sdi_phy_tx_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.734 | 6.734 | active clock edge time | ||||
| 6.734 | 0.000 | sdi_phy_tx_clk | ||||
| 6.734 | 0.000 | tCL | FF | 3886 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK |
| 8.835 | 2.101 | tNET | FF | 1 | R64C47[0][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_add_audio_inst/tx_hd_audio_data_wrapper_inst/tx_hd_audio_data_store_inst/tx_hd_audio_fifo_data/reset_w_1_s0/CLK |
| 9.277 | 0.442 | tC2Q | FF | 63 | R64C47[0][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_add_audio_inst/tx_hd_audio_data_wrapper_inst/tx_hd_audio_data_store_inst/tx_hd_audio_fifo_data/reset_w_1_s0/Q |
| 10.047 | 0.770 | tNET | FF | 1 | R59C46[1][B] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_add_audio_inst/tx_hd_audio_data_wrapper_inst/tx_hd_audio_data_store_inst/tx_hd_audio_fifo_data/raddr_num_dly_1_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 13.468 | 13.468 | active clock edge time | ||||
| 13.468 | 0.000 | sdi_phy_tx_clk | ||||
| 13.468 | 0.000 | tCL | RR | 3886 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK |
| 15.579 | 2.111 | tNET | RR | 1 | R59C46[1][B] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_add_audio_inst/tx_hd_audio_data_wrapper_inst/tx_hd_audio_data_store_inst/tx_hd_audio_fifo_data/raddr_num_dly_1_s0/CLK |
| 15.232 | -0.347 | tSu | 1 | R59C46[1][B] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_add_audio_inst/tx_hd_audio_data_wrapper_inst/tx_hd_audio_data_store_inst/tx_hd_audio_fifo_data/raddr_num_dly_1_s0 |
Path Statistics:
| Clock Skew | 0.011 |
| Setup Relationship | 6.734 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.101, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.770, 63.505%; tC2Q: 0.442, 36.495% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.111, 100.000% |
Path24
Path Summary:
| Slack | 5.185 |
| Data Arrival Time | 10.047 |
| Data Required Time | 15.232 |
| From | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_add_audio_inst/tx_hd_audio_data_wrapper_inst/tx_hd_audio_data_store_inst/tx_hd_audio_fifo_data/reset_w_1_s0 |
| To | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_add_audio_inst/tx_hd_audio_data_wrapper_inst/tx_hd_audio_data_store_inst/tx_hd_audio_fifo_data/raddr_num_dly_2_s0 |
| Launch Clk | sdi_phy_tx_clk:[F] |
| Latch Clk | sdi_phy_tx_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.734 | 6.734 | active clock edge time | ||||
| 6.734 | 0.000 | sdi_phy_tx_clk | ||||
| 6.734 | 0.000 | tCL | FF | 3886 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK |
| 8.835 | 2.101 | tNET | FF | 1 | R64C47[0][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_add_audio_inst/tx_hd_audio_data_wrapper_inst/tx_hd_audio_data_store_inst/tx_hd_audio_fifo_data/reset_w_1_s0/CLK |
| 9.277 | 0.442 | tC2Q | FF | 63 | R64C47[0][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_add_audio_inst/tx_hd_audio_data_wrapper_inst/tx_hd_audio_data_store_inst/tx_hd_audio_fifo_data/reset_w_1_s0/Q |
| 10.047 | 0.770 | tNET | FF | 1 | R59C46[1][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_add_audio_inst/tx_hd_audio_data_wrapper_inst/tx_hd_audio_data_store_inst/tx_hd_audio_fifo_data/raddr_num_dly_2_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 13.468 | 13.468 | active clock edge time | ||||
| 13.468 | 0.000 | sdi_phy_tx_clk | ||||
| 13.468 | 0.000 | tCL | RR | 3886 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK |
| 15.579 | 2.111 | tNET | RR | 1 | R59C46[1][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_add_audio_inst/tx_hd_audio_data_wrapper_inst/tx_hd_audio_data_store_inst/tx_hd_audio_fifo_data/raddr_num_dly_2_s0/CLK |
| 15.232 | -0.347 | tSu | 1 | R59C46[1][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_add_audio_inst/tx_hd_audio_data_wrapper_inst/tx_hd_audio_data_store_inst/tx_hd_audio_fifo_data/raddr_num_dly_2_s0 |
Path Statistics:
| Clock Skew | 0.011 |
| Setup Relationship | 6.734 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.101, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.770, 63.505%; tC2Q: 0.442, 36.495% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.111, 100.000% |
Path25
Path Summary:
| Slack | 10.389 |
| Data Arrival Time | 4.843 |
| Data Required Time | 15.232 |
| From | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s0 |
| To | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst4/crc_r_17_s0 |
| Launch Clk | sdi_phy_tx_clk:[R] |
| Latch Clk | sdi_phy_tx_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sdi_phy_tx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 3886 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK |
| 2.102 | 2.102 | tNET | RR | 1 | R62C31[0][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s0/CLK |
| 2.484 | 0.382 | tC2Q | RR | 1 | R62C31[0][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s0/Q |
| 2.622 | 0.137 | tNET | RR | 1 | R62C31[2][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst1/n34_s1/I1 |
| 3.002 | 0.380 | tINS | RF | 73 | R62C31[2][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst1/n34_s1/F |
| 4.843 | 1.841 | tNET | FF | 1 | R62C22[0][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst4/crc_r_17_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 13.468 | 13.468 | active clock edge time | ||||
| 13.468 | 0.000 | sdi_phy_tx_clk | ||||
| 13.468 | 0.000 | tCL | RR | 3886 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK |
| 15.579 | 2.111 | tNET | RR | 1 | R62C22[0][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst4/crc_r_17_s0/CLK |
| 15.232 | -0.347 | tSu | 1 | R62C22[0][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst4/crc_r_17_s0 |
Path Statistics:
| Clock Skew | 0.009 |
| Setup Relationship | 13.468 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.102, 100.000% |
| Arrival Data Path Delay | cell: 0.380, 13.862%; route: 1.979, 72.184%; tC2Q: 0.382, 13.953% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.111, 100.000% |
Removal Analysis Report
Report Command:report_timing -removal -max_paths 25 -max_common_paths 1
Path1
Path Summary:
| Slack | 0.705 |
| Data Arrival Time | 1.332 |
| Data Required Time | 0.627 |
| From | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s0 |
| To | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst2/crc_r_9_s0 |
| Launch Clk | sdi_phy_tx_clk:[R] |
| Latch Clk | sdi_phy_tx_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sdi_phy_tx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 3886 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK |
| 0.676 | 0.676 | tNET | RR | 1 | R62C31[0][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s0/CLK |
| 0.817 | 0.141 | tC2Q | RF | 1 | R62C31[0][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s0/Q |
| 0.883 | 0.066 | tNET | FF | 1 | R62C31[2][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst1/n34_s1/I1 |
| 1.137 | 0.254 | tINS | FR | 73 | R62C31[2][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst1/n34_s1/F |
| 1.332 | 0.195 | tNET | RR | 1 | R60C30[1][B] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst2/crc_r_9_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sdi_phy_tx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 3886 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK |
| 0.680 | 0.680 | tNET | RR | 1 | R60C30[1][B] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst2/crc_r_9_s0/CLK |
| 0.627 | -0.053 | tHld | 1 | R60C30[1][B] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst2/crc_r_9_s0 |
Path Statistics:
| Clock Skew | 0.004 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.676, 100.000% |
| Arrival Data Path Delay | cell: 0.254, 38.720%; route: 0.261, 39.787%; tC2Q: 0.141, 21.494% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.680, 100.000% |
Path2
Path Summary:
| Slack | 0.705 |
| Data Arrival Time | 1.332 |
| Data Required Time | 0.627 |
| From | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s0 |
| To | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst2/crc_r_14_s0 |
| Launch Clk | sdi_phy_tx_clk:[R] |
| Latch Clk | sdi_phy_tx_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sdi_phy_tx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 3886 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK |
| 0.676 | 0.676 | tNET | RR | 1 | R62C31[0][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s0/CLK |
| 0.817 | 0.141 | tC2Q | RF | 1 | R62C31[0][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s0/Q |
| 0.883 | 0.066 | tNET | FF | 1 | R62C31[2][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst1/n34_s1/I1 |
| 1.137 | 0.254 | tINS | FR | 73 | R62C31[2][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst1/n34_s1/F |
| 1.332 | 0.195 | tNET | RR | 1 | R60C30[1][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst2/crc_r_14_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sdi_phy_tx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 3886 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK |
| 0.680 | 0.680 | tNET | RR | 1 | R60C30[1][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst2/crc_r_14_s0/CLK |
| 0.627 | -0.053 | tHld | 1 | R60C30[1][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst2/crc_r_14_s0 |
Path Statistics:
| Clock Skew | 0.004 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.676, 100.000% |
| Arrival Data Path Delay | cell: 0.254, 38.720%; route: 0.261, 39.787%; tC2Q: 0.141, 21.494% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.680, 100.000% |
Path3
Path Summary:
| Slack | 0.713 |
| Data Arrival Time | 1.340 |
| Data Required Time | 0.627 |
| From | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s0 |
| To | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst2/crc_r_5_s0 |
| Launch Clk | sdi_phy_tx_clk:[R] |
| Latch Clk | sdi_phy_tx_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sdi_phy_tx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 3886 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK |
| 0.676 | 0.676 | tNET | RR | 1 | R62C31[0][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s0/CLK |
| 0.817 | 0.141 | tC2Q | RF | 1 | R62C31[0][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s0/Q |
| 0.883 | 0.066 | tNET | FF | 1 | R62C31[2][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst1/n34_s1/I1 |
| 1.137 | 0.254 | tINS | FR | 73 | R62C31[2][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst1/n34_s1/F |
| 1.340 | 0.203 | tNET | RR | 1 | R61C30[0][B] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst2/crc_r_5_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sdi_phy_tx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 3886 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK |
| 0.680 | 0.680 | tNET | RR | 1 | R61C30[0][B] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst2/crc_r_5_s0/CLK |
| 0.627 | -0.053 | tHld | 1 | R61C30[0][B] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst2/crc_r_5_s0 |
Path Statistics:
| Clock Skew | 0.004 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.676, 100.000% |
| Arrival Data Path Delay | cell: 0.254, 38.253%; route: 0.269, 40.512%; tC2Q: 0.141, 21.235% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.680, 100.000% |
Path4
Path Summary:
| Slack | 0.713 |
| Data Arrival Time | 1.340 |
| Data Required Time | 0.627 |
| From | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s0 |
| To | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst2/crc_r_15_s0 |
| Launch Clk | sdi_phy_tx_clk:[R] |
| Latch Clk | sdi_phy_tx_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sdi_phy_tx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 3886 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK |
| 0.676 | 0.676 | tNET | RR | 1 | R62C31[0][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s0/CLK |
| 0.817 | 0.141 | tC2Q | RF | 1 | R62C31[0][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s0/Q |
| 0.883 | 0.066 | tNET | FF | 1 | R62C31[2][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst1/n34_s1/I1 |
| 1.137 | 0.254 | tINS | FR | 73 | R62C31[2][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst1/n34_s1/F |
| 1.340 | 0.203 | tNET | RR | 1 | R61C30[0][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst2/crc_r_15_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sdi_phy_tx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 3886 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK |
| 0.680 | 0.680 | tNET | RR | 1 | R61C30[0][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst2/crc_r_15_s0/CLK |
| 0.627 | -0.053 | tHld | 1 | R61C30[0][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst2/crc_r_15_s0 |
Path Statistics:
| Clock Skew | 0.004 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.676, 100.000% |
| Arrival Data Path Delay | cell: 0.254, 38.253%; route: 0.269, 40.512%; tC2Q: 0.141, 21.235% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.680, 100.000% |
Path5
Path Summary:
| Slack | 0.713 |
| Data Arrival Time | 1.340 |
| Data Required Time | 0.627 |
| From | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s0 |
| To | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst2/crc_r_16_s0 |
| Launch Clk | sdi_phy_tx_clk:[R] |
| Latch Clk | sdi_phy_tx_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sdi_phy_tx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 3886 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK |
| 0.676 | 0.676 | tNET | RR | 1 | R62C31[0][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s0/CLK |
| 0.817 | 0.141 | tC2Q | RF | 1 | R62C31[0][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s0/Q |
| 0.883 | 0.066 | tNET | FF | 1 | R62C31[2][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst1/n34_s1/I1 |
| 1.137 | 0.254 | tINS | FR | 73 | R62C31[2][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst1/n34_s1/F |
| 1.340 | 0.203 | tNET | RR | 1 | R61C30[1][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst2/crc_r_16_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sdi_phy_tx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 3886 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK |
| 0.680 | 0.680 | tNET | RR | 1 | R61C30[1][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst2/crc_r_16_s0/CLK |
| 0.627 | -0.053 | tHld | 1 | R61C30[1][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst2/crc_r_16_s0 |
Path Statistics:
| Clock Skew | 0.004 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.676, 100.000% |
| Arrival Data Path Delay | cell: 0.254, 38.253%; route: 0.269, 40.512%; tC2Q: 0.141, 21.235% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.680, 100.000% |
Path6
Path Summary:
| Slack | 0.717 |
| Data Arrival Time | 1.340 |
| Data Required Time | 0.623 |
| From | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s0 |
| To | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst2/crc_r_6_s0 |
| Launch Clk | sdi_phy_tx_clk:[R] |
| Latch Clk | sdi_phy_tx_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sdi_phy_tx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 3886 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK |
| 0.676 | 0.676 | tNET | RR | 1 | R62C31[0][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s0/CLK |
| 0.817 | 0.141 | tC2Q | RF | 1 | R62C31[0][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s0/Q |
| 0.883 | 0.066 | tNET | FF | 1 | R62C31[2][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst1/n34_s1/I1 |
| 1.137 | 0.254 | tINS | FR | 73 | R62C31[2][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst1/n34_s1/F |
| 1.340 | 0.203 | tNET | RR | 1 | R61C29[2][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst2/crc_r_6_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sdi_phy_tx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 3886 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK |
| 0.676 | 0.676 | tNET | RR | 1 | R61C29[2][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst2/crc_r_6_s0/CLK |
| 0.623 | -0.053 | tHld | 1 | R61C29[2][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst2/crc_r_6_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.676, 100.000% |
| Arrival Data Path Delay | cell: 0.254, 38.253%; route: 0.269, 40.512%; tC2Q: 0.141, 21.235% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.676, 100.000% |
Path7
Path Summary:
| Slack | 0.717 |
| Data Arrival Time | 1.340 |
| Data Required Time | 0.623 |
| From | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s0 |
| To | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst2/crc_r_7_s0 |
| Launch Clk | sdi_phy_tx_clk:[R] |
| Latch Clk | sdi_phy_tx_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sdi_phy_tx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 3886 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK |
| 0.676 | 0.676 | tNET | RR | 1 | R62C31[0][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s0/CLK |
| 0.817 | 0.141 | tC2Q | RF | 1 | R62C31[0][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s0/Q |
| 0.883 | 0.066 | tNET | FF | 1 | R62C31[2][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst1/n34_s1/I1 |
| 1.137 | 0.254 | tINS | FR | 73 | R62C31[2][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst1/n34_s1/F |
| 1.340 | 0.203 | tNET | RR | 1 | R61C29[3][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst2/crc_r_7_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sdi_phy_tx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 3886 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK |
| 0.676 | 0.676 | tNET | RR | 1 | R61C29[3][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst2/crc_r_7_s0/CLK |
| 0.623 | -0.053 | tHld | 1 | R61C29[3][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst2/crc_r_7_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.676, 100.000% |
| Arrival Data Path Delay | cell: 0.254, 38.253%; route: 0.269, 40.512%; tC2Q: 0.141, 21.235% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.676, 100.000% |
Path8
Path Summary:
| Slack | 0.717 |
| Data Arrival Time | 1.340 |
| Data Required Time | 0.623 |
| From | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s0 |
| To | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst2/crc_r_10_s0 |
| Launch Clk | sdi_phy_tx_clk:[R] |
| Latch Clk | sdi_phy_tx_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sdi_phy_tx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 3886 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK |
| 0.676 | 0.676 | tNET | RR | 1 | R62C31[0][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s0/CLK |
| 0.817 | 0.141 | tC2Q | RF | 1 | R62C31[0][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s0/Q |
| 0.883 | 0.066 | tNET | FF | 1 | R62C31[2][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst1/n34_s1/I1 |
| 1.137 | 0.254 | tINS | FR | 73 | R62C31[2][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst1/n34_s1/F |
| 1.340 | 0.203 | tNET | RR | 1 | R61C29[0][B] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst2/crc_r_10_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sdi_phy_tx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 3886 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK |
| 0.676 | 0.676 | tNET | RR | 1 | R61C29[0][B] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst2/crc_r_10_s0/CLK |
| 0.623 | -0.053 | tHld | 1 | R61C29[0][B] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst2/crc_r_10_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.676, 100.000% |
| Arrival Data Path Delay | cell: 0.254, 38.253%; route: 0.269, 40.512%; tC2Q: 0.141, 21.235% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.676, 100.000% |
Path9
Path Summary:
| Slack | 0.717 |
| Data Arrival Time | 1.340 |
| Data Required Time | 0.623 |
| From | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s0 |
| To | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst2/crc_r_11_s0 |
| Launch Clk | sdi_phy_tx_clk:[R] |
| Latch Clk | sdi_phy_tx_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sdi_phy_tx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 3886 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK |
| 0.676 | 0.676 | tNET | RR | 1 | R62C31[0][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s0/CLK |
| 0.817 | 0.141 | tC2Q | RF | 1 | R62C31[0][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s0/Q |
| 0.883 | 0.066 | tNET | FF | 1 | R62C31[2][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst1/n34_s1/I1 |
| 1.137 | 0.254 | tINS | FR | 73 | R62C31[2][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst1/n34_s1/F |
| 1.340 | 0.203 | tNET | RR | 1 | R61C29[0][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst2/crc_r_11_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sdi_phy_tx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 3886 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK |
| 0.676 | 0.676 | tNET | RR | 1 | R61C29[0][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst2/crc_r_11_s0/CLK |
| 0.623 | -0.053 | tHld | 1 | R61C29[0][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst2/crc_r_11_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.676, 100.000% |
| Arrival Data Path Delay | cell: 0.254, 38.253%; route: 0.269, 40.512%; tC2Q: 0.141, 21.235% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.676, 100.000% |
Path10
Path Summary:
| Slack | 0.721 |
| Data Arrival Time | 1.344 |
| Data Required Time | 0.623 |
| From | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s0 |
| To | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst2/crc_r_17_s0 |
| Launch Clk | sdi_phy_tx_clk:[R] |
| Latch Clk | sdi_phy_tx_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sdi_phy_tx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 3886 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK |
| 0.676 | 0.676 | tNET | RR | 1 | R62C31[0][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s0/CLK |
| 0.817 | 0.141 | tC2Q | RF | 1 | R62C31[0][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s0/Q |
| 0.883 | 0.066 | tNET | FF | 1 | R62C31[2][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst1/n34_s1/I1 |
| 1.137 | 0.254 | tINS | FR | 73 | R62C31[2][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst1/n34_s1/F |
| 1.344 | 0.207 | tNET | RR | 1 | R62C29[0][B] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst2/crc_r_17_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sdi_phy_tx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 3886 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK |
| 0.676 | 0.676 | tNET | RR | 1 | R62C29[0][B] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst2/crc_r_17_s0/CLK |
| 0.623 | -0.053 | tHld | 1 | R62C29[0][B] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst2/crc_r_17_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.676, 100.000% |
| Arrival Data Path Delay | cell: 0.254, 38.024%; route: 0.273, 40.868%; tC2Q: 0.141, 21.108% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.676, 100.000% |
Path11
Path Summary:
| Slack | 0.721 |
| Data Arrival Time | 1.344 |
| Data Required Time | 0.623 |
| From | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s0 |
| To | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst2/crc_r_1_s0 |
| Launch Clk | sdi_phy_tx_clk:[R] |
| Latch Clk | sdi_phy_tx_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sdi_phy_tx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 3886 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK |
| 0.676 | 0.676 | tNET | RR | 1 | R62C31[0][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s0/CLK |
| 0.817 | 0.141 | tC2Q | RF | 1 | R62C31[0][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s0/Q |
| 0.883 | 0.066 | tNET | FF | 1 | R62C31[2][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst1/n34_s1/I1 |
| 1.137 | 0.254 | tINS | FR | 73 | R62C31[2][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst1/n34_s1/F |
| 1.344 | 0.207 | tNET | RR | 1 | R62C29[1][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst2/crc_r_1_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sdi_phy_tx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 3886 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK |
| 0.676 | 0.676 | tNET | RR | 1 | R62C29[1][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst2/crc_r_1_s0/CLK |
| 0.623 | -0.053 | tHld | 1 | R62C29[1][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst2/crc_r_1_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.676, 100.000% |
| Arrival Data Path Delay | cell: 0.254, 38.024%; route: 0.273, 40.868%; tC2Q: 0.141, 21.108% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.676, 100.000% |
Path12
Path Summary:
| Slack | 0.721 |
| Data Arrival Time | 1.344 |
| Data Required Time | 0.623 |
| From | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s0 |
| To | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst2/crc_r_2_s0 |
| Launch Clk | sdi_phy_tx_clk:[R] |
| Latch Clk | sdi_phy_tx_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sdi_phy_tx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 3886 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK |
| 0.676 | 0.676 | tNET | RR | 1 | R62C31[0][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s0/CLK |
| 0.817 | 0.141 | tC2Q | RF | 1 | R62C31[0][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s0/Q |
| 0.883 | 0.066 | tNET | FF | 1 | R62C31[2][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst1/n34_s1/I1 |
| 1.137 | 0.254 | tINS | FR | 73 | R62C31[2][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst1/n34_s1/F |
| 1.344 | 0.207 | tNET | RR | 1 | R62C29[1][B] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst2/crc_r_2_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sdi_phy_tx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 3886 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK |
| 0.676 | 0.676 | tNET | RR | 1 | R62C29[1][B] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst2/crc_r_2_s0/CLK |
| 0.623 | -0.053 | tHld | 1 | R62C29[1][B] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst2/crc_r_2_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.676, 100.000% |
| Arrival Data Path Delay | cell: 0.254, 38.024%; route: 0.273, 40.868%; tC2Q: 0.141, 21.108% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.676, 100.000% |
Path13
Path Summary:
| Slack | 0.811 |
| Data Arrival Time | 1.434 |
| Data Required Time | 0.623 |
| From | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s0 |
| To | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst2/crc_r_0_s0 |
| Launch Clk | sdi_phy_tx_clk:[R] |
| Latch Clk | sdi_phy_tx_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sdi_phy_tx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 3886 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK |
| 0.676 | 0.676 | tNET | RR | 1 | R62C31[0][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s0/CLK |
| 0.817 | 0.141 | tC2Q | RF | 1 | R62C31[0][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s0/Q |
| 0.883 | 0.066 | tNET | FF | 1 | R62C31[2][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst1/n34_s1/I1 |
| 1.137 | 0.254 | tINS | FR | 73 | R62C31[2][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst1/n34_s1/F |
| 1.434 | 0.297 | tNET | RR | 1 | R60C29[3][B] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst2/crc_r_0_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sdi_phy_tx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 3886 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK |
| 0.676 | 0.676 | tNET | RR | 1 | R60C29[3][B] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst2/crc_r_0_s0/CLK |
| 0.623 | -0.053 | tHld | 1 | R60C29[3][B] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst2/crc_r_0_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.676, 100.000% |
| Arrival Data Path Delay | cell: 0.254, 33.509%; route: 0.363, 47.889%; tC2Q: 0.141, 18.602% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.676, 100.000% |
Path14
Path Summary:
| Slack | 0.811 |
| Data Arrival Time | 1.434 |
| Data Required Time | 0.623 |
| From | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s0 |
| To | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst2/crc_r_3_s0 |
| Launch Clk | sdi_phy_tx_clk:[R] |
| Latch Clk | sdi_phy_tx_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sdi_phy_tx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 3886 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK |
| 0.676 | 0.676 | tNET | RR | 1 | R62C31[0][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s0/CLK |
| 0.817 | 0.141 | tC2Q | RF | 1 | R62C31[0][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s0/Q |
| 0.883 | 0.066 | tNET | FF | 1 | R62C31[2][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst1/n34_s1/I1 |
| 1.137 | 0.254 | tINS | FR | 73 | R62C31[2][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst1/n34_s1/F |
| 1.434 | 0.297 | tNET | RR | 1 | R60C29[1][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst2/crc_r_3_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sdi_phy_tx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 3886 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK |
| 0.676 | 0.676 | tNET | RR | 1 | R60C29[1][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst2/crc_r_3_s0/CLK |
| 0.623 | -0.053 | tHld | 1 | R60C29[1][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst2/crc_r_3_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.676, 100.000% |
| Arrival Data Path Delay | cell: 0.254, 33.509%; route: 0.363, 47.889%; tC2Q: 0.141, 18.602% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.676, 100.000% |
Path15
Path Summary:
| Slack | 0.811 |
| Data Arrival Time | 1.434 |
| Data Required Time | 0.623 |
| From | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s0 |
| To | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst2/crc_r_4_s0 |
| Launch Clk | sdi_phy_tx_clk:[R] |
| Latch Clk | sdi_phy_tx_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sdi_phy_tx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 3886 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK |
| 0.676 | 0.676 | tNET | RR | 1 | R62C31[0][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s0/CLK |
| 0.817 | 0.141 | tC2Q | RF | 1 | R62C31[0][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s0/Q |
| 0.883 | 0.066 | tNET | FF | 1 | R62C31[2][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst1/n34_s1/I1 |
| 1.137 | 0.254 | tINS | FR | 73 | R62C31[2][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst1/n34_s1/F |
| 1.434 | 0.297 | tNET | RR | 1 | R60C29[0][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst2/crc_r_4_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sdi_phy_tx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 3886 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK |
| 0.676 | 0.676 | tNET | RR | 1 | R60C29[0][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst2/crc_r_4_s0/CLK |
| 0.623 | -0.053 | tHld | 1 | R60C29[0][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst2/crc_r_4_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.676, 100.000% |
| Arrival Data Path Delay | cell: 0.254, 33.509%; route: 0.363, 47.889%; tC2Q: 0.141, 18.602% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.676, 100.000% |
Path16
Path Summary:
| Slack | 0.811 |
| Data Arrival Time | 1.434 |
| Data Required Time | 0.623 |
| From | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s0 |
| To | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst2/crc_r_8_s0 |
| Launch Clk | sdi_phy_tx_clk:[R] |
| Latch Clk | sdi_phy_tx_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sdi_phy_tx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 3886 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK |
| 0.676 | 0.676 | tNET | RR | 1 | R62C31[0][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s0/CLK |
| 0.817 | 0.141 | tC2Q | RF | 1 | R62C31[0][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s0/Q |
| 0.883 | 0.066 | tNET | FF | 1 | R62C31[2][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst1/n34_s1/I1 |
| 1.137 | 0.254 | tINS | FR | 73 | R62C31[2][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst1/n34_s1/F |
| 1.434 | 0.297 | tNET | RR | 1 | R60C29[0][B] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst2/crc_r_8_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sdi_phy_tx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 3886 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK |
| 0.676 | 0.676 | tNET | RR | 1 | R60C29[0][B] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst2/crc_r_8_s0/CLK |
| 0.623 | -0.053 | tHld | 1 | R60C29[0][B] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst2/crc_r_8_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.676, 100.000% |
| Arrival Data Path Delay | cell: 0.254, 33.509%; route: 0.363, 47.889%; tC2Q: 0.141, 18.602% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.676, 100.000% |
Path17
Path Summary:
| Slack | 0.811 |
| Data Arrival Time | 1.434 |
| Data Required Time | 0.623 |
| From | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s0 |
| To | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst2/crc_r_12_s0 |
| Launch Clk | sdi_phy_tx_clk:[R] |
| Latch Clk | sdi_phy_tx_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sdi_phy_tx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 3886 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK |
| 0.676 | 0.676 | tNET | RR | 1 | R62C31[0][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s0/CLK |
| 0.817 | 0.141 | tC2Q | RF | 1 | R62C31[0][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s0/Q |
| 0.883 | 0.066 | tNET | FF | 1 | R62C31[2][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst1/n34_s1/I1 |
| 1.137 | 0.254 | tINS | FR | 73 | R62C31[2][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst1/n34_s1/F |
| 1.434 | 0.297 | tNET | RR | 1 | R60C29[3][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst2/crc_r_12_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sdi_phy_tx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 3886 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK |
| 0.676 | 0.676 | tNET | RR | 1 | R60C29[3][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst2/crc_r_12_s0/CLK |
| 0.623 | -0.053 | tHld | 1 | R60C29[3][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst2/crc_r_12_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.676, 100.000% |
| Arrival Data Path Delay | cell: 0.254, 33.509%; route: 0.363, 47.889%; tC2Q: 0.141, 18.602% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.676, 100.000% |
Path18
Path Summary:
| Slack | 0.811 |
| Data Arrival Time | 1.434 |
| Data Required Time | 0.623 |
| From | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s0 |
| To | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst2/crc_r_13_s0 |
| Launch Clk | sdi_phy_tx_clk:[R] |
| Latch Clk | sdi_phy_tx_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sdi_phy_tx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 3886 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK |
| 0.676 | 0.676 | tNET | RR | 1 | R62C31[0][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s0/CLK |
| 0.817 | 0.141 | tC2Q | RF | 1 | R62C31[0][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s0/Q |
| 0.883 | 0.066 | tNET | FF | 1 | R62C31[2][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst1/n34_s1/I1 |
| 1.137 | 0.254 | tINS | FR | 73 | R62C31[2][A] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst1/n34_s1/F |
| 1.434 | 0.297 | tNET | RR | 1 | R60C29[1][B] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst2/crc_r_13_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sdi_phy_tx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 3886 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK |
| 0.676 | 0.676 | tNET | RR | 1 | R60C29[1][B] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst2/crc_r_13_s0/CLK |
| 0.623 | -0.053 | tHld | 1 | R60C29[1][B] | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst2/crc_r_13_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.676, 100.000% |
| Arrival Data Path Delay | cell: 0.254, 33.509%; route: 0.363, 47.889%; tC2Q: 0.141, 18.602% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.676, 100.000% |
Path19
Path Summary:
| Slack | 1.097 |
| Data Arrival Time | 3.042 |
| Data Required Time | 1.945 |
| From | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/rstn_s0 |
| To | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wrdata_o_1_s1 |
| Launch Clk | sdi_phy_drp_clk:[R] |
| Latch Clk | sdi_phy_drp_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sdi_phy_drp_clk | ||||
| 0.000 | 0.000 | tCL | RR | 262 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/FABRIC_CM_LIFE_CLK_O |
| 1.998 | 1.998 | tNET | RR | 1 | R33C59[0][A] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/rstn_s0/CLK |
| 2.142 | 0.144 | tC2Q | RR | 153 | R33C59[0][A] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/rstn_s0/Q |
| 3.042 | 0.900 | tNET | RR | 1 | R36C37[2][A] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wrdata_o_1_s1/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sdi_phy_drp_clk | ||||
| 0.000 | 0.000 | tCL | RR | 262 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/FABRIC_CM_LIFE_CLK_O |
| 1.998 | 1.998 | tNET | RR | 1 | R36C37[2][A] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wrdata_o_1_s1/CLK |
| 1.945 | -0.053 | tHld | 1 | R36C37[2][A] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wrdata_o_1_s1 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.998, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.900, 86.207%; tC2Q: 0.144, 13.793% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.998, 100.000% |
Path20
Path Summary:
| Slack | 1.097 |
| Data Arrival Time | 3.042 |
| Data Required Time | 1.945 |
| From | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/rstn_s0 |
| To | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wrdata_o_6_s1 |
| Launch Clk | sdi_phy_drp_clk:[R] |
| Latch Clk | sdi_phy_drp_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sdi_phy_drp_clk | ||||
| 0.000 | 0.000 | tCL | RR | 262 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/FABRIC_CM_LIFE_CLK_O |
| 1.998 | 1.998 | tNET | RR | 1 | R33C59[0][A] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/rstn_s0/CLK |
| 2.142 | 0.144 | tC2Q | RR | 153 | R33C59[0][A] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/rstn_s0/Q |
| 3.042 | 0.900 | tNET | RR | 1 | R36C37[2][B] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wrdata_o_6_s1/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sdi_phy_drp_clk | ||||
| 0.000 | 0.000 | tCL | RR | 262 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/FABRIC_CM_LIFE_CLK_O |
| 1.998 | 1.998 | tNET | RR | 1 | R36C37[2][B] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wrdata_o_6_s1/CLK |
| 1.945 | -0.053 | tHld | 1 | R36C37[2][B] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wrdata_o_6_s1 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.998, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.900, 86.207%; tC2Q: 0.144, 13.793% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.998, 100.000% |
Path21
Path Summary:
| Slack | 1.097 |
| Data Arrival Time | 3.042 |
| Data Required Time | 1.945 |
| From | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/rstn_s0 |
| To | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wrdata_o_7_s1 |
| Launch Clk | sdi_phy_drp_clk:[R] |
| Latch Clk | sdi_phy_drp_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sdi_phy_drp_clk | ||||
| 0.000 | 0.000 | tCL | RR | 262 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/FABRIC_CM_LIFE_CLK_O |
| 1.998 | 1.998 | tNET | RR | 1 | R33C59[0][A] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/rstn_s0/CLK |
| 2.142 | 0.144 | tC2Q | RR | 153 | R33C59[0][A] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/rstn_s0/Q |
| 3.042 | 0.900 | tNET | RR | 1 | R36C37[3][A] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wrdata_o_7_s1/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sdi_phy_drp_clk | ||||
| 0.000 | 0.000 | tCL | RR | 262 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/FABRIC_CM_LIFE_CLK_O |
| 1.998 | 1.998 | tNET | RR | 1 | R36C37[3][A] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wrdata_o_7_s1/CLK |
| 1.945 | -0.053 | tHld | 1 | R36C37[3][A] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wrdata_o_7_s1 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.998, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.900, 86.207%; tC2Q: 0.144, 13.793% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.998, 100.000% |
Path22
Path Summary:
| Slack | 1.111 |
| Data Arrival Time | 3.052 |
| Data Required Time | 1.941 |
| From | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/rstn_s0 |
| To | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wren_o_s1 |
| Launch Clk | sdi_phy_drp_clk:[R] |
| Latch Clk | sdi_phy_drp_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sdi_phy_drp_clk | ||||
| 0.000 | 0.000 | tCL | RR | 262 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/FABRIC_CM_LIFE_CLK_O |
| 1.998 | 1.998 | tNET | RR | 1 | R33C59[0][A] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/rstn_s0/CLK |
| 2.142 | 0.144 | tC2Q | RR | 153 | R33C59[0][A] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/rstn_s0/Q |
| 3.052 | 0.910 | tNET | RR | 1 | R32C34[2][A] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wren_o_s1/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sdi_phy_drp_clk | ||||
| 0.000 | 0.000 | tCL | RR | 262 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/FABRIC_CM_LIFE_CLK_O |
| 1.994 | 1.994 | tNET | RR | 1 | R32C34[2][A] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wren_o_s1/CLK |
| 1.941 | -0.053 | tHld | 1 | R32C34[2][A] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wren_o_s1 |
Path Statistics:
| Clock Skew | -0.004 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.998, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.910, 86.331%; tC2Q: 0.144, 13.669% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.994, 100.000% |
Path23
Path Summary:
| Slack | 1.111 |
| Data Arrival Time | 3.060 |
| Data Required Time | 1.949 |
| From | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/rstn_s0 |
| To | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wrdata_o_15_s1 |
| Launch Clk | sdi_phy_drp_clk:[R] |
| Latch Clk | sdi_phy_drp_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sdi_phy_drp_clk | ||||
| 0.000 | 0.000 | tCL | RR | 262 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/FABRIC_CM_LIFE_CLK_O |
| 1.998 | 1.998 | tNET | RR | 1 | R33C59[0][A] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/rstn_s0/CLK |
| 2.142 | 0.144 | tC2Q | RR | 153 | R33C59[0][A] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/rstn_s0/Q |
| 3.060 | 0.918 | tNET | RR | 1 | R32C36[2][A] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wrdata_o_15_s1/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sdi_phy_drp_clk | ||||
| 0.000 | 0.000 | tCL | RR | 262 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/FABRIC_CM_LIFE_CLK_O |
| 2.002 | 2.002 | tNET | RR | 1 | R32C36[2][A] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wrdata_o_15_s1/CLK |
| 1.949 | -0.053 | tHld | 1 | R32C36[2][A] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wrdata_o_15_s1 |
Path Statistics:
| Clock Skew | 0.004 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.998, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.918, 86.434%; tC2Q: 0.144, 13.566% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.002, 100.000% |
Path24
Path Summary:
| Slack | 1.111 |
| Data Arrival Time | 3.060 |
| Data Required Time | 1.949 |
| From | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/rstn_s0 |
| To | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wrdata_o_25_s1 |
| Launch Clk | sdi_phy_drp_clk:[R] |
| Latch Clk | sdi_phy_drp_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sdi_phy_drp_clk | ||||
| 0.000 | 0.000 | tCL | RR | 262 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/FABRIC_CM_LIFE_CLK_O |
| 1.998 | 1.998 | tNET | RR | 1 | R33C59[0][A] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/rstn_s0/CLK |
| 2.142 | 0.144 | tC2Q | RR | 153 | R33C59[0][A] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/rstn_s0/Q |
| 3.060 | 0.918 | tNET | RR | 1 | R32C40[1][A] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wrdata_o_25_s1/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sdi_phy_drp_clk | ||||
| 0.000 | 0.000 | tCL | RR | 262 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/FABRIC_CM_LIFE_CLK_O |
| 2.002 | 2.002 | tNET | RR | 1 | R32C40[1][A] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wrdata_o_25_s1/CLK |
| 1.949 | -0.053 | tHld | 1 | R32C40[1][A] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_wrdata_o_25_s1 |
Path Statistics:
| Clock Skew | 0.004 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.998, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.918, 86.434%; tC2Q: 0.144, 13.566% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.002, 100.000% |
Path25
Path Summary:
| Slack | 1.111 |
| Data Arrival Time | 3.060 |
| Data Required Time | 1.949 |
| From | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/rstn_s0 |
| To | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_addr_o_11_s1 |
| Launch Clk | sdi_phy_drp_clk:[R] |
| Latch Clk | sdi_phy_drp_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sdi_phy_drp_clk | ||||
| 0.000 | 0.000 | tCL | RR | 262 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/FABRIC_CM_LIFE_CLK_O |
| 1.998 | 1.998 | tNET | RR | 1 | R33C59[0][A] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/rstn_s0/CLK |
| 2.142 | 0.144 | tC2Q | RR | 153 | R33C59[0][A] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/rstn_s0/Q |
| 3.060 | 0.918 | tNET | RR | 1 | R32C40[0][A] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_addr_o_11_s1/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sdi_phy_drp_clk | ||||
| 0.000 | 0.000 | tCL | RR | 262 | R2C2 | SerDes_Top_inst/gtr12_quad_inst0/FABRIC_CM_LIFE_CLK_O |
| 2.002 | 2.002 | tNET | RR | 1 | R32C40[0][A] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_addr_o_11_s1/CLK |
| 1.949 | -0.053 | tHld | 1 | R32C40[0][A] | SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_addr_o_11_s1 |
Path Statistics:
| Clock Skew | 0.004 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.998, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.918, 86.434%; tC2Q: 0.144, 13.566% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.002, 100.000% |
Minimum Pulse Width Report:
Report Command:report_min_pulse_width -nworst 10 -detail
MPW1
MPW Summary:
| Slack: | 2.354 |
| Actual Width: | 2.604 |
| Required Width: | 0.250 |
| Type: | Low Pulse Width |
| Clock: | sdi_phy_drp_clk |
| Objects: | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_link_rate_change_inst/locked_cnt_12_s0 |
Late clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 5.000 | 0.000 | active clock edge time | ||
| 5.000 | 0.000 | sdi_phy_drp_clk | ||
| 5.000 | 0.000 | tCL | FF | SerDes_Top_inst/gtr12_quad_inst0/FABRIC_CM_LIFE_CLK_O |
| 9.402 | 4.402 | tNET | FF | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_link_rate_change_inst/locked_cnt_12_s0/CLK |
Early clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 10.000 | 0.000 | active clock edge time | ||
| 10.000 | 0.000 | sdi_phy_drp_clk | ||
| 10.000 | 0.000 | tCL | RR | SerDes_Top_inst/gtr12_quad_inst0/FABRIC_CM_LIFE_CLK_O |
| 12.005 | 2.005 | tNET | RR | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_link_rate_change_inst/locked_cnt_12_s0/CLK |
MPW2
MPW Summary:
| Slack: | 2.354 |
| Actual Width: | 2.604 |
| Required Width: | 0.250 |
| Type: | Low Pulse Width |
| Clock: | sdi_phy_drp_clk |
| Objects: | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_link_rate_change_inst/locked_cnt_11_s0 |
Late clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 5.000 | 0.000 | active clock edge time | ||
| 5.000 | 0.000 | sdi_phy_drp_clk | ||
| 5.000 | 0.000 | tCL | FF | SerDes_Top_inst/gtr12_quad_inst0/FABRIC_CM_LIFE_CLK_O |
| 9.402 | 4.402 | tNET | FF | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_link_rate_change_inst/locked_cnt_11_s0/CLK |
Early clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 10.000 | 0.000 | active clock edge time | ||
| 10.000 | 0.000 | sdi_phy_drp_clk | ||
| 10.000 | 0.000 | tCL | RR | SerDes_Top_inst/gtr12_quad_inst0/FABRIC_CM_LIFE_CLK_O |
| 12.005 | 2.005 | tNET | RR | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_link_rate_change_inst/locked_cnt_11_s0/CLK |
MPW3
MPW Summary:
| Slack: | 2.354 |
| Actual Width: | 2.604 |
| Required Width: | 0.250 |
| Type: | Low Pulse Width |
| Clock: | sdi_phy_drp_clk |
| Objects: | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_link_rate_change_inst/locked_cnt_10_s0 |
Late clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 5.000 | 0.000 | active clock edge time | ||
| 5.000 | 0.000 | sdi_phy_drp_clk | ||
| 5.000 | 0.000 | tCL | FF | SerDes_Top_inst/gtr12_quad_inst0/FABRIC_CM_LIFE_CLK_O |
| 9.402 | 4.402 | tNET | FF | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_link_rate_change_inst/locked_cnt_10_s0/CLK |
Early clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 10.000 | 0.000 | active clock edge time | ||
| 10.000 | 0.000 | sdi_phy_drp_clk | ||
| 10.000 | 0.000 | tCL | RR | SerDes_Top_inst/gtr12_quad_inst0/FABRIC_CM_LIFE_CLK_O |
| 12.005 | 2.005 | tNET | RR | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_link_rate_change_inst/locked_cnt_10_s0/CLK |
MPW4
MPW Summary:
| Slack: | 2.354 |
| Actual Width: | 2.604 |
| Required Width: | 0.250 |
| Type: | Low Pulse Width |
| Clock: | sdi_phy_drp_clk |
| Objects: | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_link_rate_change_inst/cnt_25_s0 |
Late clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 5.000 | 0.000 | active clock edge time | ||
| 5.000 | 0.000 | sdi_phy_drp_clk | ||
| 5.000 | 0.000 | tCL | FF | SerDes_Top_inst/gtr12_quad_inst0/FABRIC_CM_LIFE_CLK_O |
| 9.402 | 4.402 | tNET | FF | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_link_rate_change_inst/cnt_25_s0/CLK |
Early clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 10.000 | 0.000 | active clock edge time | ||
| 10.000 | 0.000 | sdi_phy_drp_clk | ||
| 10.000 | 0.000 | tCL | RR | SerDes_Top_inst/gtr12_quad_inst0/FABRIC_CM_LIFE_CLK_O |
| 12.005 | 2.005 | tNET | RR | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_link_rate_change_inst/cnt_25_s0/CLK |
MPW5
MPW Summary:
| Slack: | 2.354 |
| Actual Width: | 2.604 |
| Required Width: | 0.250 |
| Type: | Low Pulse Width |
| Clock: | sdi_phy_drp_clk |
| Objects: | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_link_rate_change_inst/cnt_24_s0 |
Late clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 5.000 | 0.000 | active clock edge time | ||
| 5.000 | 0.000 | sdi_phy_drp_clk | ||
| 5.000 | 0.000 | tCL | FF | SerDes_Top_inst/gtr12_quad_inst0/FABRIC_CM_LIFE_CLK_O |
| 9.402 | 4.402 | tNET | FF | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_link_rate_change_inst/cnt_24_s0/CLK |
Early clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 10.000 | 0.000 | active clock edge time | ||
| 10.000 | 0.000 | sdi_phy_drp_clk | ||
| 10.000 | 0.000 | tCL | RR | SerDes_Top_inst/gtr12_quad_inst0/FABRIC_CM_LIFE_CLK_O |
| 12.005 | 2.005 | tNET | RR | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_link_rate_change_inst/cnt_24_s0/CLK |
MPW6
MPW Summary:
| Slack: | 2.354 |
| Actual Width: | 2.604 |
| Required Width: | 0.250 |
| Type: | Low Pulse Width |
| Clock: | sdi_phy_drp_clk |
| Objects: | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_link_rate_change_inst/cnt_5_s0 |
Late clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 5.000 | 0.000 | active clock edge time | ||
| 5.000 | 0.000 | sdi_phy_drp_clk | ||
| 5.000 | 0.000 | tCL | FF | SerDes_Top_inst/gtr12_quad_inst0/FABRIC_CM_LIFE_CLK_O |
| 9.402 | 4.402 | tNET | FF | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_link_rate_change_inst/cnt_5_s0/CLK |
Early clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 10.000 | 0.000 | active clock edge time | ||
| 10.000 | 0.000 | sdi_phy_drp_clk | ||
| 10.000 | 0.000 | tCL | RR | SerDes_Top_inst/gtr12_quad_inst0/FABRIC_CM_LIFE_CLK_O |
| 12.005 | 2.005 | tNET | RR | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_link_rate_change_inst/cnt_5_s0/CLK |
MPW7
MPW Summary:
| Slack: | 2.354 |
| Actual Width: | 2.604 |
| Required Width: | 0.250 |
| Type: | Low Pulse Width |
| Clock: | sdi_phy_drp_clk |
| Objects: | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_link_rate_change_inst/cnt_1_s0 |
Late clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 5.000 | 0.000 | active clock edge time | ||
| 5.000 | 0.000 | sdi_phy_drp_clk | ||
| 5.000 | 0.000 | tCL | FF | SerDes_Top_inst/gtr12_quad_inst0/FABRIC_CM_LIFE_CLK_O |
| 9.402 | 4.402 | tNET | FF | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_link_rate_change_inst/cnt_1_s0/CLK |
Early clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 10.000 | 0.000 | active clock edge time | ||
| 10.000 | 0.000 | sdi_phy_drp_clk | ||
| 10.000 | 0.000 | tCL | RR | SerDes_Top_inst/gtr12_quad_inst0/FABRIC_CM_LIFE_CLK_O |
| 12.005 | 2.005 | tNET | RR | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_link_rate_change_inst/cnt_1_s0/CLK |
MPW8
MPW Summary:
| Slack: | 2.354 |
| Actual Width: | 2.604 |
| Required Width: | 0.250 |
| Type: | Low Pulse Width |
| Clock: | sdi_phy_drp_clk |
| Objects: | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_link_rate_change_inst/cnt_0_s0 |
Late clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 5.000 | 0.000 | active clock edge time | ||
| 5.000 | 0.000 | sdi_phy_drp_clk | ||
| 5.000 | 0.000 | tCL | FF | SerDes_Top_inst/gtr12_quad_inst0/FABRIC_CM_LIFE_CLK_O |
| 9.402 | 4.402 | tNET | FF | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_link_rate_change_inst/cnt_0_s0/CLK |
Early clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 10.000 | 0.000 | active clock edge time | ||
| 10.000 | 0.000 | sdi_phy_drp_clk | ||
| 10.000 | 0.000 | tCL | RR | SerDes_Top_inst/gtr12_quad_inst0/FABRIC_CM_LIFE_CLK_O |
| 12.005 | 2.005 | tNET | RR | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_link_rate_change_inst/cnt_0_s0/CLK |
MPW9
MPW Summary:
| Slack: | 2.354 |
| Actual Width: | 2.604 |
| Required Width: | 0.250 |
| Type: | Low Pulse Width |
| Clock: | sdi_phy_drp_clk |
| Objects: | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_link_rate_change_inst/cnt_4_s0 |
Late clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 5.000 | 0.000 | active clock edge time | ||
| 5.000 | 0.000 | sdi_phy_drp_clk | ||
| 5.000 | 0.000 | tCL | FF | SerDes_Top_inst/gtr12_quad_inst0/FABRIC_CM_LIFE_CLK_O |
| 9.402 | 4.402 | tNET | FF | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_link_rate_change_inst/cnt_4_s0/CLK |
Early clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 10.000 | 0.000 | active clock edge time | ||
| 10.000 | 0.000 | sdi_phy_drp_clk | ||
| 10.000 | 0.000 | tCL | RR | SerDes_Top_inst/gtr12_quad_inst0/FABRIC_CM_LIFE_CLK_O |
| 12.005 | 2.005 | tNET | RR | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_link_rate_change_inst/cnt_4_s0/CLK |
MPW10
MPW Summary:
| Slack: | 2.354 |
| Actual Width: | 2.604 |
| Required Width: | 0.250 |
| Type: | Low Pulse Width |
| Clock: | sdi_phy_drp_clk |
| Objects: | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_link_rate_change_inst/cnt_3_s0 |
Late clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 5.000 | 0.000 | active clock edge time | ||
| 5.000 | 0.000 | sdi_phy_drp_clk | ||
| 5.000 | 0.000 | tCL | FF | SerDes_Top_inst/gtr12_quad_inst0/FABRIC_CM_LIFE_CLK_O |
| 9.402 | 4.402 | tNET | FF | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_link_rate_change_inst/cnt_3_s0/CLK |
Early clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 10.000 | 0.000 | active clock edge time | ||
| 10.000 | 0.000 | sdi_phy_drp_clk | ||
| 10.000 | 0.000 | tCL | RR | SerDes_Top_inst/gtr12_quad_inst0/FABRIC_CM_LIFE_CLK_O |
| 12.005 | 2.005 | tNET | RR | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_link_rate_change_inst/cnt_3_s0/CLK |
High Fanout Nets Report:
Report Command:report_high_fanout_nets -max_nets 10
| FANOUT | NET NAME | WORST SLACK | MAX DELAY |
|---|---|---|---|
| 5539 | rst_n1 | 13.636 | 3.231 |
| 3886 | sdi_phy_tx_clk | 4.827 | 2.606 |
| 1923 | sdi_phy_rx_clk | 7.270 | 2.606 |
| 274 | sclk | 13.636 | 2.118 |
| 262 | sdi_phy_drp_clk | 2.335 | 4.402 |
| 252 | pll_mdclk | 39.150 | 2.604 |
| 155 | audio_ref_clk_div4 | 321.281 | 2.109 |
| 108 | rEnable[1] | 42.271 | 2.848 |
| 102 | I2C_MASTER_Top_inst0/u_i2c_master/n16_6 | 16.426 | 1.972 |
| 73 | SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/n34_5 | 10.160 | 2.051 |
Route Congestions Report:
Report Command:report_route_congestion -max_grids 10
| GRID LOC | ROUTE CONGESTIONS |
|---|---|
| R2C75 | 100.00% |
| R2C76 | 100.00% |
| R2C77 | 100.00% |
| R2C78 | 100.00% |
| R2C109 | 100.00% |
| R2C110 | 100.00% |
| R3C100 | 100.00% |
| R5C81 | 100.00% |
| R8C119 | 100.00% |
| R16C116 | 100.00% |
Timing Exceptions Report:
Setup Analysis Report
Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Hold Analysis Report
Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Recovery Analysis Report
Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Removal Analysis Report
Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Timing Constraints Report:
| SDC Command Type | State | Detail Command |
|---|---|---|
| TC_CLOCK | Actived | create_clock -name sclk -period 20 -waveform {0 10} [get_nets {sclk}] -add |
| TC_CLOCK | Actived | create_clock -name I_pcm2706_bclk -period 325.520 -waveform {0 162.76} [get_ports {I_pcm2706_bclk}] -add |
| TC_CLOCK | Actived | create_clock -name I_audio_refclk -period 81.380 -waveform {0 40.69} [get_ports {I_audio_refclk}] -add |
| TC_CLOCK | Actived | create_clock -name sdi_phy_drp_clk -period 10 -waveform {0 5} [get_nets {sdi_phy_drp_clk}] -add |
| TC_CLOCK | Actived | create_clock -name sdi_phy_tx_clk -period 13.468 -waveform {0 6.734} [get_nets {sdi_phy_tx_clk}] -add |
| TC_CLOCK | Actived | create_clock -name sdi_phy_rx_clk -period 13.468 -waveform {0 6.734} [get_nets {sdi_phy_rx_clk}] -add |
| TC_FALSE_PATH | Actived | set_false_path -from [get_clocks {sclk}] -to [get_clocks {sdi_phy_tx_clk}] |
| TC_FALSE_PATH | Actived | set_false_path -from [get_clocks {sdi_phy_tx_clk}] -to [get_clocks {sclk}] |
| TC_FALSE_PATH | Actived | set_false_path -from [get_clocks {sclk}] -to [get_clocks {sdi_phy_rx_clk}] |
| TC_FALSE_PATH | Actived | set_false_path -from [get_clocks {sdi_phy_rx_clk}] -to [get_clocks {sclk}] |
| TC_FALSE_PATH | Actived | set_false_path -from [get_clocks {sclk}] -to [get_clocks {sdi_phy_drp_clk}] |
| TC_FALSE_PATH | Actived | set_false_path -from [get_clocks {sdi_phy_drp_clk}] -to [get_clocks {sclk}] |
| TC_FALSE_PATH | Actived | set_false_path -from [get_clocks {sdi_phy_drp_clk}] -to [get_clocks {sdi_phy_rx_clk}] |
| TC_FALSE_PATH | Actived | set_false_path -from [get_clocks {sdi_phy_rx_clk}] -to [get_clocks {sdi_phy_drp_clk}] |