Timing Messages

Report Title	Timing Analysis Report
Design File	E:\myWork\IP\releaseVerify\version\1.9.11\Gowin_FP_Exponential_RefDesign\proj\impl\gwsynthesis\FP_Exponential.vg
Physical Constraints File	E:\myWork\IP\releaseVerify\version\1.9.11\Gowin_FP_Exponential_RefDesign\proj\src\fp_exponential.cst
Timing Constraint File	E:\myWork\IP\releaseVerify\version\1.9.11\Gowin_FP_Exponential_RefDesign\proj\src\fp_exponential.sdc
Tool Version	V1.9.11 (64-bit)
Part Number	GW5A-LV25UG324ES
Device	GW5A-25
Device Version	A
Created Time	Wed Dec 25 14:11:05 2024
Legal Announcement	Copyright (C)2014-2024 Gowin Semiconductor Corporation. All rights reserved.

Timing Summaries

STA Tool Run Summary:

Setup Delay Model	Slow 0.855V 0C ES
Hold Delay Model	Fast 0.945V 85C ES
Numbers of Paths Analyzed	7183
Numbers of Endpoints Analyzed	7427
Numbers of Falling Endpoints	3
Numbers of Setup Violated Endpoints	0
Numbers of Hold Violated Endpoints	0

Clock Summary:

NO.	Clock Name	Type	Period	Frequency(MHz)	Rise	Fall	Source	Master	Objects
1	clk	Base	50.000	20.000	0.000	10.000			clk
2	tck_pad_i	Base	50.000	20.000	0.000	25.000			tck_pad_i

Max Frequency Summary:

NO.	Clock Name	Constraint	Actual Fmax	Logic Level	Entity
1	clk	20.000(MHz)	55.843(MHz)	12	TOP
2	tck_pad_i	20.000(MHz)	130.091(MHz)	7	TOP

Total Negative Slack Summary:

Clock Name	Analysis Type	Endpoints TNS	Number of Endpoints
clk	Setup	0.000	0
clk	Hold	0.000	0
tck_pad_i	Setup	0.000	0
tck_pad_i	Hold	0.000	0

Timing Details

Path Slacks Table:

Setup Paths Table

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	42.313	gw_gao_inst_0/u_la0_top/module_state_1_s0/Q	gw_gao_inst_0/u_la0_top/bit_count_0_s1/CE	tck_pad_i:[R]	tck_pad_i:[R]	50.000	0.022	7.354
2	42.313	gw_gao_inst_0/u_la0_top/module_state_1_s0/Q	gw_gao_inst_0/u_la0_top/bit_count_1_s1/CE	tck_pad_i:[R]	tck_pad_i:[R]	50.000	0.022	7.354
3	42.313	gw_gao_inst_0/u_la0_top/module_state_1_s0/Q	gw_gao_inst_0/u_la0_top/bit_count_2_s1/CE	tck_pad_i:[R]	tck_pad_i:[R]	50.000	0.022	7.354
4	42.321	gw_gao_inst_0/u_la0_top/module_state_1_s0/Q	gw_gao_inst_0/u_la0_top/word_count_15_s0/CE	tck_pad_i:[R]	tck_pad_i:[R]	50.000	0.048	7.320
5	42.322	gw_gao_inst_0/u_la0_top/module_state_1_s0/Q	gw_gao_inst_0/u_la0_top/word_count_13_s0/CE	tck_pad_i:[R]	tck_pad_i:[R]	50.000	0.042	7.325
6	42.322	gw_gao_inst_0/u_la0_top/module_state_1_s0/Q	gw_gao_inst_0/u_la0_top/word_count_7_s0/CE	tck_pad_i:[R]	tck_pad_i:[R]	50.000	0.042	7.325
7	42.322	gw_gao_inst_0/u_la0_top/module_state_1_s0/Q	gw_gao_inst_0/u_la0_top/word_count_6_s0/CE	tck_pad_i:[R]	tck_pad_i:[R]	50.000	0.042	7.325
8	42.322	gw_gao_inst_0/u_la0_top/module_state_1_s0/Q	gw_gao_inst_0/u_la0_top/word_count_5_s0/CE	tck_pad_i:[R]	tck_pad_i:[R]	50.000	0.042	7.325
9	42.322	gw_gao_inst_0/u_la0_top/module_state_1_s0/Q	gw_gao_inst_0/u_la0_top/word_count_4_s0/CE	tck_pad_i:[R]	tck_pad_i:[R]	50.000	0.042	7.325
10	42.330	gw_gao_inst_0/u_la0_top/module_state_1_s0/Q	gw_gao_inst_0/u_la0_top/word_count_8_s0/CE	tck_pad_i:[R]	tck_pad_i:[R]	50.000	0.038	7.320
11	32.093	mem_data_in_mem_data_in_0_1_s/DO[5]	uut/FP_Exponential_inst/frac_part_63_s3/B[31]	clk:[R]	clk:[R]	50.000	-0.002	17.106
12	32.120	mem_data_in_mem_data_in_0_1_s/DO[5]	uut/FP_Exponential_inst/frac_part_63_s3/B[27]	clk:[R]	clk:[R]	50.000	-0.002	17.112
13	32.312	mem_data_in_mem_data_in_0_1_s/DO[5]	uut/FP_Exponential_inst/frac_part_63_s4/B[31]	clk:[R]	clk:[R]	50.000	0.008	16.877
14	32.699	mem_data_in_mem_data_in_0_1_s/DO[5]	uut/FP_Exponential_inst/frac_part_63_s4/B[27]	clk:[R]	clk:[R]	50.000	0.008	16.523
15	32.725	mem_data_in_mem_data_in_0_1_s/DO[5]	uut/FP_Exponential_inst/frac_part_63_s3/B[30]	clk:[R]	clk:[R]	50.000	-0.002	16.643
16	32.817	mem_data_in_mem_data_in_0_1_s/DO[5]	uut/FP_Exponential_inst/frac_part_63_s4/B[30]	clk:[R]	clk:[R]	50.000	0.008	16.542
17	32.916	mem_data_in_mem_data_in_0_1_s/DO[5]	uut/FP_Exponential_inst/frac_part_63_s4/B[29]	clk:[R]	clk:[R]	50.000	0.008	16.449
18	32.939	mem_data_in_mem_data_in_0_1_s/DO[5]	uut/FP_Exponential_inst/frac_part_63_s4/B[24]	clk:[R]	clk:[R]	50.000	0.008	16.267
19	33.002	mem_data_in_mem_data_in_0_1_s/DO[5]	uut/FP_Exponential_inst/frac_part_63_s4/B[23]	clk:[R]	clk:[R]	50.000	0.008	16.372
20	33.052	mem_data_in_mem_data_in_0_1_s/DO[5]	uut/FP_Exponential_inst/frac_part_63_s3/B[29]	clk:[R]	clk:[R]	50.000	-0.002	16.322
21	33.095	mem_data_in_mem_data_in_0_1_s/DO[5]	uut/FP_Exponential_inst/frac_part_63_s4/B[25]	clk:[R]	clk:[R]	50.000	0.008	16.091
22	33.097	mem_data_in_mem_data_in_0_1_s/DO[5]	uut/FP_Exponential_inst/frac_part_63_s3/B[23]	clk:[R]	clk:[R]	50.000	-0.002	16.286
23	33.109	mem_data_in_mem_data_in_0_1_s/DO[5]	uut/FP_Exponential_inst/frac_part_63_s4/B[28]	clk:[R]	clk:[R]	50.000	0.008	16.071
24	33.121	mem_data_in_mem_data_in_0_1_s/DO[5]	uut/FP_Exponential_inst/frac_part_63_s3/B[26]	clk:[R]	clk:[R]	50.000	-0.002	16.099
25	33.131	mem_data_in_mem_data_in_0_1_s/DO[5]	uut/FP_Exponential_inst/frac_part_63_s3/B[20]	clk:[R]	clk:[R]	50.000	-0.002	16.081

Hold Paths Table

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	0.143	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_20_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[4]	clk:[R]	clk:[R]	0.000	0.005	0.175
2	0.179	count_7_s0/Q	mem_data_in_mem_data_in_0_1_s/AD[11]	clk:[R]	clk:[R]	0.000	-0.003	0.217
3	0.224	gw_gao_inst_0/u_la0_top/address_counter_9_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/ADB[13]	tck_pad_i:[R]	tck_pad_i:[R]	0.000	-0.006	0.265
4	0.225	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_4_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/DI[4]	clk:[R]	clk:[R]	0.000	0.017	0.245
5	0.225	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_0_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/DI[0]	clk:[R]	clk:[R]	0.000	0.017	0.245
6	0.249	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_11_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/DI[11]	clk:[R]	clk:[R]	0.000	0.001	0.285
7	0.251	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_37_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/DI[5]	clk:[R]	clk:[R]	0.000	0.009	0.279
8	0.257	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_28_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[12]	clk:[R]	clk:[R]	0.000	0.009	0.285
9	0.275	uut/FP_Exponential_inst/data_z[18]_10_s0/Q	uut/FP_Exponential_inst/data_z[19]_10_s0/D	clk:[R]	clk:[R]	0.000	0.000	0.222
10	0.275	gw_gao_inst_0/u_la0_top/address_counter_0_s0/Q	gw_gao_inst_0/u_la0_top/address_counter_0_s0/D	tck_pad_i:[R]	tck_pad_i:[R]	0.000	0.000	0.300
11	0.275	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/D	clk:[R]	clk:[R]	0.000	0.000	0.300
12	0.275	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/D	clk:[R]	clk:[R]	0.000	0.000	0.300
13	0.275	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1/D	clk:[R]	clk:[R]	0.000	0.000	0.300
14	0.275	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/D	clk:[R]	clk:[R]	0.000	0.000	0.300
15	0.275	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1/D	clk:[R]	clk:[R]	0.000	0.000	0.300
16	0.275	gw_gao_inst_0/u_la0_top/word_count_9_s0/Q	gw_gao_inst_0/u_la0_top/word_count_9_s0/D	tck_pad_i:[R]	tck_pad_i:[R]	0.000	0.000	0.300
17	0.275	gw_gao_inst_0/u_la0_top/word_count_12_s0/Q	gw_gao_inst_0/u_la0_top/word_count_12_s0/D	tck_pad_i:[R]	tck_pad_i:[R]	0.000	0.000	0.300
18	0.278	gw_gao_inst_0/u_la0_top/bit_count_4_s1/Q	gw_gao_inst_0/u_la0_top/bit_count_4_s1/D	tck_pad_i:[R]	tck_pad_i:[R]	0.000	0.000	0.303
19	0.278	gw_gao_inst_0/u_la0_top/word_count_0_s0/Q	gw_gao_inst_0/u_la0_top/word_count_0_s0/D	tck_pad_i:[R]	tck_pad_i:[R]	0.000	0.000	0.303
20	0.278	gw_gao_inst_0/u_la0_top/address_counter_2_s0/Q	gw_gao_inst_0/u_la0_top/address_counter_2_s0/D	tck_pad_i:[R]	tck_pad_i:[R]	0.000	0.000	0.303
21	0.278	gw_gao_inst_0/u_la0_top/address_counter_8_s0/Q	gw_gao_inst_0/u_la0_top/address_counter_8_s0/D	tck_pad_i:[R]	tck_pad_i:[R]	0.000	0.000	0.303
22	0.278	gw_gao_inst_0/u_la0_top/capture_window_sel_4_s1/Q	gw_gao_inst_0/u_la0_top/capture_window_sel_4_s1/D	clk:[R]	clk:[R]	0.000	0.000	0.303
23	0.278	gw_gao_inst_0/u_la0_top/capture_window_sel_5_s1/Q	gw_gao_inst_0/u_la0_top/capture_window_sel_5_s1/D	clk:[R]	clk:[R]	0.000	0.000	0.303
24	0.278	gw_gao_inst_0/u_la0_top/capture_window_sel_6_s1/Q	gw_gao_inst_0/u_la0_top/capture_window_sel_6_s1/D	clk:[R]	clk:[R]	0.000	0.000	0.303
25	0.281	gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1/Q	gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1/D	clk:[R]	clk:[R]	0.000	0.000	0.306

Recovery Paths Table

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	38.411	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1/CLEAR	clk:[F]	clk:[R]	40.000	-0.006	1.247
2	38.411	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/CLEAR	clk:[F]	clk:[R]	40.000	-0.006	1.247
3	38.413	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLEAR	clk:[F]	clk:[R]	40.000	-0.008	1.247
4	38.413	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLEAR	clk:[F]	clk:[R]	40.000	-0.008	1.247
5	38.413	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLEAR	clk:[F]	clk:[R]	40.000	-0.008	1.247
6	38.413	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLEAR	clk:[F]	clk:[R]	40.000	-0.008	1.247
7	38.413	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/CLEAR	clk:[F]	clk:[R]	40.000	-0.008	1.247
8	38.434	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/CLEAR	clk:[F]	clk:[R]	40.000	0.003	1.215
9	38.434	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/start_reg_s0/CLEAR	clk:[F]	clk:[R]	40.000	0.003	1.215
10	38.457	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1/CLEAR	clk:[F]	clk:[R]	40.000	-0.011	1.206
11	38.457	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1/CLEAR	clk:[F]	clk:[R]	40.000	-0.011	1.206
12	38.457	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1/CLEAR	clk:[F]	clk:[R]	40.000	-0.011	1.206
13	38.457	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/capture_window_sel_8_s1/CLEAR	clk:[F]	clk:[R]	40.000	0.028	1.168
14	38.457	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/capture_window_sel_9_s1/CLEAR	clk:[F]	clk:[R]	40.000	0.028	1.168
15	38.614	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLEAR	clk:[F]	clk:[R]	40.000	-0.002	1.040
16	38.614	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/capture_end_dly_s0/PRESET	clk:[F]	clk:[R]	40.000	-0.002	1.040
17	38.623	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1/CLEAR	clk:[F]	clk:[R]	40.000	-0.011	1.040
18	38.623	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/CLEAR	clk:[F]	clk:[R]	40.000	-0.011	1.040
19	38.815	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1/PRESET	clk:[F]	clk:[R]	40.000	0.008	0.830
20	38.815	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/CLEAR	clk:[F]	clk:[R]	40.000	0.008	0.830
21	38.815	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1/CLEAR	clk:[F]	clk:[R]	40.000	0.008	0.830
22	38.822	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/CLEAR	clk:[F]	clk:[R]	40.000	0.001	0.830
23	38.822	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/CLEAR	clk:[F]	clk:[R]	40.000	0.001	0.830
24	38.824	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1/CLEAR	clk:[F]	clk:[R]	40.000	-0.002	0.830
25	38.824	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1/CLEAR	clk:[F]	clk:[R]	40.000	-0.002	0.830

Removal Paths Table

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	10.328	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/capture_window_sel_0_s3/CLEAR	clk:[F]	clk:[R]	-10.000	-0.001	0.276
2	10.328	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1/CLEAR	clk:[F]	clk:[R]	-10.000	-0.001	0.276
3	10.328	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1/CLEAR	clk:[F]	clk:[R]	-10.000	-0.001	0.276
4	10.328	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/capture_window_sel_4_s1/CLEAR	clk:[F]	clk:[R]	-10.000	-0.001	0.276
5	10.328	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/internal_reg_start_dly_0_s0/CLEAR	clk:[F]	clk:[R]	-10.000	-0.001	0.276
6	10.328	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/internal_reg_start_syn_1_s0/CLEAR	clk:[F]	clk:[R]	-10.000	-0.001	0.276
7	10.332	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CLEAR	clk:[F]	clk:[R]	-10.000	0.003	0.276
8	10.332	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1/CLEAR	clk:[F]	clk:[R]	-10.000	0.003	0.276
9	10.332	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/capture_window_sel_5_s1/CLEAR	clk:[F]	clk:[R]	-10.000	0.003	0.276
10	10.332	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/capture_window_sel_6_s1/CLEAR	clk:[F]	clk:[R]	-10.000	0.003	0.276
11	10.332	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/capture_window_sel_7_s1/CLEAR	clk:[F]	clk:[R]	-10.000	0.003	0.276
12	10.410	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0/CLEAR	clk:[F]	clk:[R]	-10.000	0.029	0.328
13	10.410	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_1_s0/CLEAR	clk:[F]	clk:[R]	-10.000	0.029	0.328
14	10.424	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1/CLEAR	clk:[F]	clk:[R]	-10.000	0.005	0.366
15	10.424	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1/CLEAR	clk:[F]	clk:[R]	-10.000	0.005	0.366
16	10.424	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_9_s1/CLEAR	clk:[F]	clk:[R]	-10.000	0.005	0.366
17	10.426	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/CLEAR	clk:[F]	clk:[R]	-10.000	0.007	0.366
18	10.426	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/CLEAR	clk:[F]	clk:[R]	-10.000	0.007	0.366
19	10.428	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1/PRESET	clk:[F]	clk:[R]	-10.000	0.009	0.366
20	10.428	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/CLEAR	clk:[F]	clk:[R]	-10.000	0.009	0.366
21	10.428	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1/CLEAR	clk:[F]	clk:[R]	-10.000	0.009	0.366
22	10.429	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/internal_reg_start_dly_1_s0/CLEAR	clk:[F]	clk:[R]	-10.000	0.021	0.355
23	10.429	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0/CLEAR	clk:[F]	clk:[R]	-10.000	0.021	0.355
24	10.430	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0/CLEAR	clk:[F]	clk:[R]	-10.000	0.032	0.345
25	10.430	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0/CLEAR	clk:[F]	clk:[R]	-10.000	0.032	0.345

Minimum Pulse Width Table:

Report Command:report_min_pulse_width -nworst 10 -detail

Number	Slack	Actual Width	Required Width	Type	Clock	Objects
1	7.759	8.759	1.000	High Pulse Width	clk	uut/FP_Exponential_inst/frac_part_63_s3
2	7.762	8.762	1.000	High Pulse Width	clk	mem_data_in_mem_data_in_0_1_s
3	7.764	8.764	1.000	High Pulse Width	clk	uut/FP_Exponential_inst/frac_part_63_s4
4	7.767	8.767	1.000	High Pulse Width	clk	mem_data_in_mem_data_in_0_0_s
5	7.767	8.767	1.000	High Pulse Width	clk	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s
6	7.767	8.767	1.000	High Pulse Width	clk	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s
7	7.773	8.773	1.000	High Pulse Width	clk	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s
8	8.498	8.748	0.250	High Pulse Width	clk	uut/FP_Exponential_inst/index[11]_4_s0
9	8.498	8.748	0.250	High Pulse Width	clk	uut/FP_Exponential_inst/index[12]_4_s0
10	8.498	8.748	0.250	High Pulse Width	clk	uut/FP_Exponential_inst/index[13]_4_s0

Timing Report By Analysis Type:

Setup Analysis Report

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	42.313
Data Arrival Time	11.425
Data Required Time	53.738
From	gw_gao_inst_0/u_la0_top/module_state_1_s0
To	gw_gao_inst_0/u_la0_top/bit_count_0_s1
Launch Clk	tck_pad_i:[R]
Latch Clk	tck_pad_i:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/I
0.683	0.683	tINS	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/O
0.683	0.000	tNET	RR	1	R28C89	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.365	0.683	tINS	RR	258	R28C89	gw_gao_inst_0/u_gw_jtag/tck_o
4.071	2.706	tNET	RR	1	R6C58[0][A]	gw_gao_inst_0/u_la0_top/module_state_1_s0/CLK
4.454	0.382	tC2Q	RR	20	R6C58[0][A]	gw_gao_inst_0/u_la0_top/module_state_1_s0/Q
6.544	2.090	tNET	RR	1	R33C57[3][A]	gw_gao_inst_0/u_la0_top/op_reg_en_s6/I1
7.065	0.521	tINS	RR	1	R33C57[3][A]	gw_gao_inst_0/u_la0_top/op_reg_en_s6/F
7.068	0.003	tNET	RR	1	R33C57[2][B]	gw_gao_inst_0/u_la0_top/op_reg_en_s4/I2
7.529	0.461	tINS	RR	3	R33C57[2][B]	gw_gao_inst_0/u_la0_top/op_reg_en_s4/F
8.134	0.605	tNET	RR	1	R8C58[0][B]	gw_gao_inst_0/u_la0_top/module_next_state_0_s23/I2
8.650	0.516	tINS	RR	1	R8C58[0][B]	gw_gao_inst_0/u_la0_top/module_next_state_0_s23/F
8.807	0.157	tNET	RR	1	R7C58[0][B]	gw_gao_inst_0/u_la0_top/module_next_state_0_s22/I0
9.324	0.516	tINS	RR	4	R7C58[0][B]	gw_gao_inst_0/u_la0_top/module_next_state_0_s22/F
9.679	0.355	tNET	RR	1	R6C59[3][B]	gw_gao_inst_0/u_la0_top/u_ao_crc32/crc_30_s3/I1
10.094	0.415	tINS	RR	33	R6C59[3][B]	gw_gao_inst_0/u_la0_top/u_ao_crc32/crc_30_s3/F
10.429	0.335	tNET	RR	1	R8C59[3][B]	gw_gao_inst_0/u_la0_top/bit_count_5_s3/I2
10.926	0.498	tINS	RR	6	R8C59[3][B]	gw_gao_inst_0/u_la0_top/bit_count_5_s3/F
11.425	0.499	tNET	RR	1	R11C59[1][B]	gw_gao_inst_0/u_la0_top/bit_count_0_s1/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
50.000	50.000					active clock edge time
50.000	0.000					tck_pad_i
50.000	0.000	tCL	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/I
50.682	0.683	tINS	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/O
50.682	0.000	tNET	RR	1	R28C89	gw_gao_inst_0/u_gw_jtag/tck_pad_i
51.365	0.683	tINS	RR	258	R28C89	gw_gao_inst_0/u_gw_jtag/tck_o
54.049	2.684	tNET	RR	1	R11C59[1][B]	gw_gao_inst_0/u_la0_top/bit_count_0_s1/CLK
53.738	-0.311	tSu		1	R11C59[1][B]	gw_gao_inst_0/u_la0_top/bit_count_0_s1

Path Statistics:

Clock Skew	-0.022
Setup Relationship	50.000
Logic Level	7
Arrival Clock Path Delay	cell: 1.365, 33.528%; route: 2.706, 66.472%
Arrival Data Path Delay	cell: 2.927, 39.810%; route: 4.044, 54.989%; tC2Q: 0.382, 5.201%
Required Clock Path Delay	cell: 1.365, 33.709%; route: 2.684, 66.291%

Path2

Path Summary:

Slack	42.313
Data Arrival Time	11.425
Data Required Time	53.738
From	gw_gao_inst_0/u_la0_top/module_state_1_s0
To	gw_gao_inst_0/u_la0_top/bit_count_1_s1
Launch Clk	tck_pad_i:[R]
Latch Clk	tck_pad_i:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/I
0.683	0.683	tINS	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/O
0.683	0.000	tNET	RR	1	R28C89	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.365	0.683	tINS	RR	258	R28C89	gw_gao_inst_0/u_gw_jtag/tck_o
4.071	2.706	tNET	RR	1	R6C58[0][A]	gw_gao_inst_0/u_la0_top/module_state_1_s0/CLK
4.454	0.382	tC2Q	RR	20	R6C58[0][A]	gw_gao_inst_0/u_la0_top/module_state_1_s0/Q
6.544	2.090	tNET	RR	1	R33C57[3][A]	gw_gao_inst_0/u_la0_top/op_reg_en_s6/I1
7.065	0.521	tINS	RR	1	R33C57[3][A]	gw_gao_inst_0/u_la0_top/op_reg_en_s6/F
7.068	0.003	tNET	RR	1	R33C57[2][B]	gw_gao_inst_0/u_la0_top/op_reg_en_s4/I2
7.529	0.461	tINS	RR	3	R33C57[2][B]	gw_gao_inst_0/u_la0_top/op_reg_en_s4/F
8.134	0.605	tNET	RR	1	R8C58[0][B]	gw_gao_inst_0/u_la0_top/module_next_state_0_s23/I2
8.650	0.516	tINS	RR	1	R8C58[0][B]	gw_gao_inst_0/u_la0_top/module_next_state_0_s23/F
8.807	0.157	tNET	RR	1	R7C58[0][B]	gw_gao_inst_0/u_la0_top/module_next_state_0_s22/I0
9.324	0.516	tINS	RR	4	R7C58[0][B]	gw_gao_inst_0/u_la0_top/module_next_state_0_s22/F
9.679	0.355	tNET	RR	1	R6C59[3][B]	gw_gao_inst_0/u_la0_top/u_ao_crc32/crc_30_s3/I1
10.094	0.415	tINS	RR	33	R6C59[3][B]	gw_gao_inst_0/u_la0_top/u_ao_crc32/crc_30_s3/F
10.429	0.335	tNET	RR	1	R8C59[3][B]	gw_gao_inst_0/u_la0_top/bit_count_5_s3/I2
10.926	0.498	tINS	RR	6	R8C59[3][B]	gw_gao_inst_0/u_la0_top/bit_count_5_s3/F
11.425	0.499	tNET	RR	1	R11C59[1][A]	gw_gao_inst_0/u_la0_top/bit_count_1_s1/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
50.000	50.000					active clock edge time
50.000	0.000					tck_pad_i
50.000	0.000	tCL	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/I
50.682	0.683	tINS	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/O
50.682	0.000	tNET	RR	1	R28C89	gw_gao_inst_0/u_gw_jtag/tck_pad_i
51.365	0.683	tINS	RR	258	R28C89	gw_gao_inst_0/u_gw_jtag/tck_o
54.049	2.684	tNET	RR	1	R11C59[1][A]	gw_gao_inst_0/u_la0_top/bit_count_1_s1/CLK
53.738	-0.311	tSu		1	R11C59[1][A]	gw_gao_inst_0/u_la0_top/bit_count_1_s1

Path Statistics:

Clock Skew	-0.022
Setup Relationship	50.000
Logic Level	7
Arrival Clock Path Delay	cell: 1.365, 33.528%; route: 2.706, 66.472%
Arrival Data Path Delay	cell: 2.927, 39.810%; route: 4.044, 54.989%; tC2Q: 0.382, 5.201%
Required Clock Path Delay	cell: 1.365, 33.709%; route: 2.684, 66.291%

Path3

Path Summary:

Slack	42.313
Data Arrival Time	11.425
Data Required Time	53.738
From	gw_gao_inst_0/u_la0_top/module_state_1_s0
To	gw_gao_inst_0/u_la0_top/bit_count_2_s1
Launch Clk	tck_pad_i:[R]
Latch Clk	tck_pad_i:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/I
0.683	0.683	tINS	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/O
0.683	0.000	tNET	RR	1	R28C89	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.365	0.683	tINS	RR	258	R28C89	gw_gao_inst_0/u_gw_jtag/tck_o
4.071	2.706	tNET	RR	1	R6C58[0][A]	gw_gao_inst_0/u_la0_top/module_state_1_s0/CLK
4.454	0.382	tC2Q	RR	20	R6C58[0][A]	gw_gao_inst_0/u_la0_top/module_state_1_s0/Q
6.544	2.090	tNET	RR	1	R33C57[3][A]	gw_gao_inst_0/u_la0_top/op_reg_en_s6/I1
7.065	0.521	tINS	RR	1	R33C57[3][A]	gw_gao_inst_0/u_la0_top/op_reg_en_s6/F
7.068	0.003	tNET	RR	1	R33C57[2][B]	gw_gao_inst_0/u_la0_top/op_reg_en_s4/I2
7.529	0.461	tINS	RR	3	R33C57[2][B]	gw_gao_inst_0/u_la0_top/op_reg_en_s4/F
8.134	0.605	tNET	RR	1	R8C58[0][B]	gw_gao_inst_0/u_la0_top/module_next_state_0_s23/I2
8.650	0.516	tINS	RR	1	R8C58[0][B]	gw_gao_inst_0/u_la0_top/module_next_state_0_s23/F
8.807	0.157	tNET	RR	1	R7C58[0][B]	gw_gao_inst_0/u_la0_top/module_next_state_0_s22/I0
9.324	0.516	tINS	RR	4	R7C58[0][B]	gw_gao_inst_0/u_la0_top/module_next_state_0_s22/F
9.679	0.355	tNET	RR	1	R6C59[3][B]	gw_gao_inst_0/u_la0_top/u_ao_crc32/crc_30_s3/I1
10.094	0.415	tINS	RR	33	R6C59[3][B]	gw_gao_inst_0/u_la0_top/u_ao_crc32/crc_30_s3/F
10.429	0.335	tNET	RR	1	R8C59[3][B]	gw_gao_inst_0/u_la0_top/bit_count_5_s3/I2
10.926	0.498	tINS	RR	6	R8C59[3][B]	gw_gao_inst_0/u_la0_top/bit_count_5_s3/F
11.425	0.499	tNET	RR	1	R11C59[0][B]	gw_gao_inst_0/u_la0_top/bit_count_2_s1/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
50.000	50.000					active clock edge time
50.000	0.000					tck_pad_i
50.000	0.000	tCL	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/I
50.682	0.683	tINS	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/O
50.682	0.000	tNET	RR	1	R28C89	gw_gao_inst_0/u_gw_jtag/tck_pad_i
51.365	0.683	tINS	RR	258	R28C89	gw_gao_inst_0/u_gw_jtag/tck_o
54.049	2.684	tNET	RR	1	R11C59[0][B]	gw_gao_inst_0/u_la0_top/bit_count_2_s1/CLK
53.738	-0.311	tSu		1	R11C59[0][B]	gw_gao_inst_0/u_la0_top/bit_count_2_s1

Path Statistics:

Clock Skew	-0.022
Setup Relationship	50.000
Logic Level	7
Arrival Clock Path Delay	cell: 1.365, 33.528%; route: 2.706, 66.472%
Arrival Data Path Delay	cell: 2.927, 39.810%; route: 4.044, 54.989%; tC2Q: 0.382, 5.201%
Required Clock Path Delay	cell: 1.365, 33.709%; route: 2.684, 66.291%

Path4

Path Summary:

Slack	42.321
Data Arrival Time	11.391
Data Required Time	53.712
From	gw_gao_inst_0/u_la0_top/module_state_1_s0
To	gw_gao_inst_0/u_la0_top/word_count_15_s0
Launch Clk	tck_pad_i:[R]
Latch Clk	tck_pad_i:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/I
0.683	0.683	tINS	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/O
0.683	0.000	tNET	RR	1	R28C89	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.365	0.683	tINS	RR	258	R28C89	gw_gao_inst_0/u_gw_jtag/tck_o
4.071	2.706	tNET	RR	1	R6C58[0][A]	gw_gao_inst_0/u_la0_top/module_state_1_s0/CLK
4.454	0.382	tC2Q	RR	20	R6C58[0][A]	gw_gao_inst_0/u_la0_top/module_state_1_s0/Q
6.544	2.090	tNET	RR	1	R33C57[3][A]	gw_gao_inst_0/u_la0_top/op_reg_en_s6/I1
7.065	0.521	tINS	RR	1	R33C57[3][A]	gw_gao_inst_0/u_la0_top/op_reg_en_s6/F
7.068	0.003	tNET	RR	1	R33C57[2][B]	gw_gao_inst_0/u_la0_top/op_reg_en_s4/I2
7.529	0.461	tINS	RR	3	R33C57[2][B]	gw_gao_inst_0/u_la0_top/op_reg_en_s4/F
8.081	0.553	tNET	RR	1	R9C59[3][A]	gw_gao_inst_0/u_la0_top/op_reg_en_s7/I0
8.579	0.498	tINS	RR	34	R9C59[3][A]	gw_gao_inst_0/u_la0_top/op_reg_en_s7/F
8.586	0.008	tNET	RR	1	R9C59[1][B]	gw_gao_inst_0/u_la0_top/addr_ct_en_s30/I3
9.048	0.461	tINS	RR	3	R9C59[1][B]	gw_gao_inst_0/u_la0_top/addr_ct_en_s30/F
9.053	0.005	tNET	RR	1	R9C59[0][B]	gw_gao_inst_0/u_la0_top/word_ct_en_s26/I2
9.569	0.516	tINS	RR	6	R9C59[0][B]	gw_gao_inst_0/u_la0_top/word_ct_en_s26/F
9.771	0.203	tNET	RR	1	R7C59[2][A]	gw_gao_inst_0/u_la0_top/word_ct_en_s23/I3
10.298	0.526	tINS	RR	16	R7C59[2][A]	gw_gao_inst_0/u_la0_top/word_ct_en_s23/F
11.391	1.094	tNET	RR	1	R12C58[0][B]	gw_gao_inst_0/u_la0_top/word_count_15_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
50.000	50.000					active clock edge time
50.000	0.000					tck_pad_i
50.000	0.000	tCL	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/I
50.682	0.683	tINS	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/O
50.682	0.000	tNET	RR	1	R28C89	gw_gao_inst_0/u_gw_jtag/tck_pad_i
51.365	0.683	tINS	RR	258	R28C89	gw_gao_inst_0/u_gw_jtag/tck_o
54.023	2.658	tNET	RR	1	R12C58[0][B]	gw_gao_inst_0/u_la0_top/word_count_15_s0/CLK
53.712	-0.311	tSu		1	R12C58[0][B]	gw_gao_inst_0/u_la0_top/word_count_15_s0

Path Statistics:

Clock Skew	-0.048
Setup Relationship	50.000
Logic Level	7
Arrival Clock Path Delay	cell: 1.365, 33.528%; route: 2.706, 66.472%
Arrival Data Path Delay	cell: 2.984, 40.762%; route: 3.954, 54.013%; tC2Q: 0.382, 5.225%
Required Clock Path Delay	cell: 1.365, 33.926%; route: 2.658, 66.074%

Path5

Path Summary:

Slack	42.322
Data Arrival Time	11.396
Data Required Time	53.718
From	gw_gao_inst_0/u_la0_top/module_state_1_s0
To	gw_gao_inst_0/u_la0_top/word_count_13_s0
Launch Clk	tck_pad_i:[R]
Latch Clk	tck_pad_i:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/I
0.683	0.683	tINS	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/O
0.683	0.000	tNET	RR	1	R28C89	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.365	0.683	tINS	RR	258	R28C89	gw_gao_inst_0/u_gw_jtag/tck_o
4.071	2.706	tNET	RR	1	R6C58[0][A]	gw_gao_inst_0/u_la0_top/module_state_1_s0/CLK
4.454	0.382	tC2Q	RR	20	R6C58[0][A]	gw_gao_inst_0/u_la0_top/module_state_1_s0/Q
6.544	2.090	tNET	RR	1	R33C57[3][A]	gw_gao_inst_0/u_la0_top/op_reg_en_s6/I1
7.065	0.521	tINS	RR	1	R33C57[3][A]	gw_gao_inst_0/u_la0_top/op_reg_en_s6/F
7.068	0.003	tNET	RR	1	R33C57[2][B]	gw_gao_inst_0/u_la0_top/op_reg_en_s4/I2
7.529	0.461	tINS	RR	3	R33C57[2][B]	gw_gao_inst_0/u_la0_top/op_reg_en_s4/F
8.081	0.553	tNET	RR	1	R9C59[3][A]	gw_gao_inst_0/u_la0_top/op_reg_en_s7/I0
8.579	0.498	tINS	RR	34	R9C59[3][A]	gw_gao_inst_0/u_la0_top/op_reg_en_s7/F
8.586	0.008	tNET	RR	1	R9C59[1][B]	gw_gao_inst_0/u_la0_top/addr_ct_en_s30/I3
9.048	0.461	tINS	RR	3	R9C59[1][B]	gw_gao_inst_0/u_la0_top/addr_ct_en_s30/F
9.053	0.005	tNET	RR	1	R9C59[0][B]	gw_gao_inst_0/u_la0_top/word_ct_en_s26/I2
9.569	0.516	tINS	RR	6	R9C59[0][B]	gw_gao_inst_0/u_la0_top/word_ct_en_s26/F
9.771	0.203	tNET	RR	1	R7C59[2][A]	gw_gao_inst_0/u_la0_top/word_ct_en_s23/I3
10.298	0.526	tINS	RR	16	R7C59[2][A]	gw_gao_inst_0/u_la0_top/word_ct_en_s23/F
11.396	1.099	tNET	RR	1	R13C58[2][A]	gw_gao_inst_0/u_la0_top/word_count_13_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
50.000	50.000					active clock edge time
50.000	0.000					tck_pad_i
50.000	0.000	tCL	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/I
50.682	0.683	tINS	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/O
50.682	0.000	tNET	RR	1	R28C89	gw_gao_inst_0/u_gw_jtag/tck_pad_i
51.365	0.683	tINS	RR	258	R28C89	gw_gao_inst_0/u_gw_jtag/tck_o
54.029	2.664	tNET	RR	1	R13C58[2][A]	gw_gao_inst_0/u_la0_top/word_count_13_s0/CLK
53.718	-0.311	tSu		1	R13C58[2][A]	gw_gao_inst_0/u_la0_top/word_count_13_s0

Path Statistics:

Clock Skew	-0.042
Setup Relationship	50.000
Logic Level	7
Arrival Clock Path Delay	cell: 1.365, 33.528%; route: 2.706, 66.472%
Arrival Data Path Delay	cell: 2.984, 40.734%; route: 3.959, 54.044%; tC2Q: 0.382, 5.222%
Required Clock Path Delay	cell: 1.365, 33.876%; route: 2.664, 66.124%

Path6

Path Summary:

Slack	42.322
Data Arrival Time	11.396
Data Required Time	53.718
From	gw_gao_inst_0/u_la0_top/module_state_1_s0
To	gw_gao_inst_0/u_la0_top/word_count_7_s0
Launch Clk	tck_pad_i:[R]
Latch Clk	tck_pad_i:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/I
0.683	0.683	tINS	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/O
0.683	0.000	tNET	RR	1	R28C89	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.365	0.683	tINS	RR	258	R28C89	gw_gao_inst_0/u_gw_jtag/tck_o
4.071	2.706	tNET	RR	1	R6C58[0][A]	gw_gao_inst_0/u_la0_top/module_state_1_s0/CLK
4.454	0.382	tC2Q	RR	20	R6C58[0][A]	gw_gao_inst_0/u_la0_top/module_state_1_s0/Q
6.544	2.090	tNET	RR	1	R33C57[3][A]	gw_gao_inst_0/u_la0_top/op_reg_en_s6/I1
7.065	0.521	tINS	RR	1	R33C57[3][A]	gw_gao_inst_0/u_la0_top/op_reg_en_s6/F
7.068	0.003	tNET	RR	1	R33C57[2][B]	gw_gao_inst_0/u_la0_top/op_reg_en_s4/I2
7.529	0.461	tINS	RR	3	R33C57[2][B]	gw_gao_inst_0/u_la0_top/op_reg_en_s4/F
8.081	0.553	tNET	RR	1	R9C59[3][A]	gw_gao_inst_0/u_la0_top/op_reg_en_s7/I0
8.579	0.498	tINS	RR	34	R9C59[3][A]	gw_gao_inst_0/u_la0_top/op_reg_en_s7/F
8.586	0.008	tNET	RR	1	R9C59[1][B]	gw_gao_inst_0/u_la0_top/addr_ct_en_s30/I3
9.048	0.461	tINS	RR	3	R9C59[1][B]	gw_gao_inst_0/u_la0_top/addr_ct_en_s30/F
9.053	0.005	tNET	RR	1	R9C59[0][B]	gw_gao_inst_0/u_la0_top/word_ct_en_s26/I2
9.569	0.516	tINS	RR	6	R9C59[0][B]	gw_gao_inst_0/u_la0_top/word_ct_en_s26/F
9.771	0.203	tNET	RR	1	R7C59[2][A]	gw_gao_inst_0/u_la0_top/word_ct_en_s23/I3
10.298	0.526	tINS	RR	16	R7C59[2][A]	gw_gao_inst_0/u_la0_top/word_ct_en_s23/F
11.396	1.099	tNET	RR	1	R13C58[0][B]	gw_gao_inst_0/u_la0_top/word_count_7_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
50.000	50.000					active clock edge time
50.000	0.000					tck_pad_i
50.000	0.000	tCL	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/I
50.682	0.683	tINS	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/O
50.682	0.000	tNET	RR	1	R28C89	gw_gao_inst_0/u_gw_jtag/tck_pad_i
51.365	0.683	tINS	RR	258	R28C89	gw_gao_inst_0/u_gw_jtag/tck_o
54.029	2.664	tNET	RR	1	R13C58[0][B]	gw_gao_inst_0/u_la0_top/word_count_7_s0/CLK
53.718	-0.311	tSu		1	R13C58[0][B]	gw_gao_inst_0/u_la0_top/word_count_7_s0

Path Statistics:

Clock Skew	-0.042
Setup Relationship	50.000
Logic Level	7
Arrival Clock Path Delay	cell: 1.365, 33.528%; route: 2.706, 66.472%
Arrival Data Path Delay	cell: 2.984, 40.734%; route: 3.959, 54.044%; tC2Q: 0.382, 5.222%
Required Clock Path Delay	cell: 1.365, 33.876%; route: 2.664, 66.124%

Path7

Path Summary:

Slack	42.322
Data Arrival Time	11.396
Data Required Time	53.718
From	gw_gao_inst_0/u_la0_top/module_state_1_s0
To	gw_gao_inst_0/u_la0_top/word_count_6_s0
Launch Clk	tck_pad_i:[R]
Latch Clk	tck_pad_i:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/I
0.683	0.683	tINS	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/O
0.683	0.000	tNET	RR	1	R28C89	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.365	0.683	tINS	RR	258	R28C89	gw_gao_inst_0/u_gw_jtag/tck_o
4.071	2.706	tNET	RR	1	R6C58[0][A]	gw_gao_inst_0/u_la0_top/module_state_1_s0/CLK
4.454	0.382	tC2Q	RR	20	R6C58[0][A]	gw_gao_inst_0/u_la0_top/module_state_1_s0/Q
6.544	2.090	tNET	RR	1	R33C57[3][A]	gw_gao_inst_0/u_la0_top/op_reg_en_s6/I1
7.065	0.521	tINS	RR	1	R33C57[3][A]	gw_gao_inst_0/u_la0_top/op_reg_en_s6/F
7.068	0.003	tNET	RR	1	R33C57[2][B]	gw_gao_inst_0/u_la0_top/op_reg_en_s4/I2
7.529	0.461	tINS	RR	3	R33C57[2][B]	gw_gao_inst_0/u_la0_top/op_reg_en_s4/F
8.081	0.553	tNET	RR	1	R9C59[3][A]	gw_gao_inst_0/u_la0_top/op_reg_en_s7/I0
8.579	0.498	tINS	RR	34	R9C59[3][A]	gw_gao_inst_0/u_la0_top/op_reg_en_s7/F
8.586	0.008	tNET	RR	1	R9C59[1][B]	gw_gao_inst_0/u_la0_top/addr_ct_en_s30/I3
9.048	0.461	tINS	RR	3	R9C59[1][B]	gw_gao_inst_0/u_la0_top/addr_ct_en_s30/F
9.053	0.005	tNET	RR	1	R9C59[0][B]	gw_gao_inst_0/u_la0_top/word_ct_en_s26/I2
9.569	0.516	tINS	RR	6	R9C59[0][B]	gw_gao_inst_0/u_la0_top/word_ct_en_s26/F
9.771	0.203	tNET	RR	1	R7C59[2][A]	gw_gao_inst_0/u_la0_top/word_ct_en_s23/I3
10.298	0.526	tINS	RR	16	R7C59[2][A]	gw_gao_inst_0/u_la0_top/word_ct_en_s23/F
11.396	1.099	tNET	RR	1	R13C58[2][B]	gw_gao_inst_0/u_la0_top/word_count_6_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
50.000	50.000					active clock edge time
50.000	0.000					tck_pad_i
50.000	0.000	tCL	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/I
50.682	0.683	tINS	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/O
50.682	0.000	tNET	RR	1	R28C89	gw_gao_inst_0/u_gw_jtag/tck_pad_i
51.365	0.683	tINS	RR	258	R28C89	gw_gao_inst_0/u_gw_jtag/tck_o
54.029	2.664	tNET	RR	1	R13C58[2][B]	gw_gao_inst_0/u_la0_top/word_count_6_s0/CLK
53.718	-0.311	tSu		1	R13C58[2][B]	gw_gao_inst_0/u_la0_top/word_count_6_s0

Path Statistics:

Clock Skew	-0.042
Setup Relationship	50.000
Logic Level	7
Arrival Clock Path Delay	cell: 1.365, 33.528%; route: 2.706, 66.472%
Arrival Data Path Delay	cell: 2.984, 40.734%; route: 3.959, 54.044%; tC2Q: 0.382, 5.222%
Required Clock Path Delay	cell: 1.365, 33.876%; route: 2.664, 66.124%

Path8

Path Summary:

Slack	42.322
Data Arrival Time	11.396
Data Required Time	53.718
From	gw_gao_inst_0/u_la0_top/module_state_1_s0
To	gw_gao_inst_0/u_la0_top/word_count_5_s0
Launch Clk	tck_pad_i:[R]
Latch Clk	tck_pad_i:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/I
0.683	0.683	tINS	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/O
0.683	0.000	tNET	RR	1	R28C89	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.365	0.683	tINS	RR	258	R28C89	gw_gao_inst_0/u_gw_jtag/tck_o
4.071	2.706	tNET	RR	1	R6C58[0][A]	gw_gao_inst_0/u_la0_top/module_state_1_s0/CLK
4.454	0.382	tC2Q	RR	20	R6C58[0][A]	gw_gao_inst_0/u_la0_top/module_state_1_s0/Q
6.544	2.090	tNET	RR	1	R33C57[3][A]	gw_gao_inst_0/u_la0_top/op_reg_en_s6/I1
7.065	0.521	tINS	RR	1	R33C57[3][A]	gw_gao_inst_0/u_la0_top/op_reg_en_s6/F
7.068	0.003	tNET	RR	1	R33C57[2][B]	gw_gao_inst_0/u_la0_top/op_reg_en_s4/I2
7.529	0.461	tINS	RR	3	R33C57[2][B]	gw_gao_inst_0/u_la0_top/op_reg_en_s4/F
8.081	0.553	tNET	RR	1	R9C59[3][A]	gw_gao_inst_0/u_la0_top/op_reg_en_s7/I0
8.579	0.498	tINS	RR	34	R9C59[3][A]	gw_gao_inst_0/u_la0_top/op_reg_en_s7/F
8.586	0.008	tNET	RR	1	R9C59[1][B]	gw_gao_inst_0/u_la0_top/addr_ct_en_s30/I3
9.048	0.461	tINS	RR	3	R9C59[1][B]	gw_gao_inst_0/u_la0_top/addr_ct_en_s30/F
9.053	0.005	tNET	RR	1	R9C59[0][B]	gw_gao_inst_0/u_la0_top/word_ct_en_s26/I2
9.569	0.516	tINS	RR	6	R9C59[0][B]	gw_gao_inst_0/u_la0_top/word_ct_en_s26/F
9.771	0.203	tNET	RR	1	R7C59[2][A]	gw_gao_inst_0/u_la0_top/word_ct_en_s23/I3
10.298	0.526	tINS	RR	16	R7C59[2][A]	gw_gao_inst_0/u_la0_top/word_ct_en_s23/F
11.396	1.099	tNET	RR	1	R13C58[1][A]	gw_gao_inst_0/u_la0_top/word_count_5_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
50.000	50.000					active clock edge time
50.000	0.000					tck_pad_i
50.000	0.000	tCL	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/I
50.682	0.683	tINS	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/O
50.682	0.000	tNET	RR	1	R28C89	gw_gao_inst_0/u_gw_jtag/tck_pad_i
51.365	0.683	tINS	RR	258	R28C89	gw_gao_inst_0/u_gw_jtag/tck_o
54.029	2.664	tNET	RR	1	R13C58[1][A]	gw_gao_inst_0/u_la0_top/word_count_5_s0/CLK
53.718	-0.311	tSu		1	R13C58[1][A]	gw_gao_inst_0/u_la0_top/word_count_5_s0

Path Statistics:

Clock Skew	-0.042
Setup Relationship	50.000
Logic Level	7
Arrival Clock Path Delay	cell: 1.365, 33.528%; route: 2.706, 66.472%
Arrival Data Path Delay	cell: 2.984, 40.734%; route: 3.959, 54.044%; tC2Q: 0.382, 5.222%
Required Clock Path Delay	cell: 1.365, 33.876%; route: 2.664, 66.124%

Path9

Path Summary:

Slack	42.322
Data Arrival Time	11.396
Data Required Time	53.718
From	gw_gao_inst_0/u_la0_top/module_state_1_s0
To	gw_gao_inst_0/u_la0_top/word_count_4_s0
Launch Clk	tck_pad_i:[R]
Latch Clk	tck_pad_i:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/I
0.683	0.683	tINS	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/O
0.683	0.000	tNET	RR	1	R28C89	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.365	0.683	tINS	RR	258	R28C89	gw_gao_inst_0/u_gw_jtag/tck_o
4.071	2.706	tNET	RR	1	R6C58[0][A]	gw_gao_inst_0/u_la0_top/module_state_1_s0/CLK
4.454	0.382	tC2Q	RR	20	R6C58[0][A]	gw_gao_inst_0/u_la0_top/module_state_1_s0/Q
6.544	2.090	tNET	RR	1	R33C57[3][A]	gw_gao_inst_0/u_la0_top/op_reg_en_s6/I1
7.065	0.521	tINS	RR	1	R33C57[3][A]	gw_gao_inst_0/u_la0_top/op_reg_en_s6/F
7.068	0.003	tNET	RR	1	R33C57[2][B]	gw_gao_inst_0/u_la0_top/op_reg_en_s4/I2
7.529	0.461	tINS	RR	3	R33C57[2][B]	gw_gao_inst_0/u_la0_top/op_reg_en_s4/F
8.081	0.553	tNET	RR	1	R9C59[3][A]	gw_gao_inst_0/u_la0_top/op_reg_en_s7/I0
8.579	0.498	tINS	RR	34	R9C59[3][A]	gw_gao_inst_0/u_la0_top/op_reg_en_s7/F
8.586	0.008	tNET	RR	1	R9C59[1][B]	gw_gao_inst_0/u_la0_top/addr_ct_en_s30/I3
9.048	0.461	tINS	RR	3	R9C59[1][B]	gw_gao_inst_0/u_la0_top/addr_ct_en_s30/F
9.053	0.005	tNET	RR	1	R9C59[0][B]	gw_gao_inst_0/u_la0_top/word_ct_en_s26/I2
9.569	0.516	tINS	RR	6	R9C59[0][B]	gw_gao_inst_0/u_la0_top/word_ct_en_s26/F
9.771	0.203	tNET	RR	1	R7C59[2][A]	gw_gao_inst_0/u_la0_top/word_ct_en_s23/I3
10.298	0.526	tINS	RR	16	R7C59[2][A]	gw_gao_inst_0/u_la0_top/word_ct_en_s23/F
11.396	1.099	tNET	RR	1	R13C58[3][A]	gw_gao_inst_0/u_la0_top/word_count_4_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
50.000	50.000					active clock edge time
50.000	0.000					tck_pad_i
50.000	0.000	tCL	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/I
50.682	0.683	tINS	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/O
50.682	0.000	tNET	RR	1	R28C89	gw_gao_inst_0/u_gw_jtag/tck_pad_i
51.365	0.683	tINS	RR	258	R28C89	gw_gao_inst_0/u_gw_jtag/tck_o
54.029	2.664	tNET	RR	1	R13C58[3][A]	gw_gao_inst_0/u_la0_top/word_count_4_s0/CLK
53.718	-0.311	tSu		1	R13C58[3][A]	gw_gao_inst_0/u_la0_top/word_count_4_s0

Path Statistics:

Clock Skew	-0.042
Setup Relationship	50.000
Logic Level	7
Arrival Clock Path Delay	cell: 1.365, 33.528%; route: 2.706, 66.472%
Arrival Data Path Delay	cell: 2.984, 40.734%; route: 3.959, 54.044%; tC2Q: 0.382, 5.222%
Required Clock Path Delay	cell: 1.365, 33.876%; route: 2.664, 66.124%

Path10

Path Summary:

Slack	42.330
Data Arrival Time	11.391
Data Required Time	53.722
From	gw_gao_inst_0/u_la0_top/module_state_1_s0
To	gw_gao_inst_0/u_la0_top/word_count_8_s0
Launch Clk	tck_pad_i:[R]
Latch Clk	tck_pad_i:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/I
0.683	0.683	tINS	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/O
0.683	0.000	tNET	RR	1	R28C89	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.365	0.683	tINS	RR	258	R28C89	gw_gao_inst_0/u_gw_jtag/tck_o
4.071	2.706	tNET	RR	1	R6C58[0][A]	gw_gao_inst_0/u_la0_top/module_state_1_s0/CLK
4.454	0.382	tC2Q	RR	20	R6C58[0][A]	gw_gao_inst_0/u_la0_top/module_state_1_s0/Q
6.544	2.090	tNET	RR	1	R33C57[3][A]	gw_gao_inst_0/u_la0_top/op_reg_en_s6/I1
7.065	0.521	tINS	RR	1	R33C57[3][A]	gw_gao_inst_0/u_la0_top/op_reg_en_s6/F
7.068	0.003	tNET	RR	1	R33C57[2][B]	gw_gao_inst_0/u_la0_top/op_reg_en_s4/I2
7.529	0.461	tINS	RR	3	R33C57[2][B]	gw_gao_inst_0/u_la0_top/op_reg_en_s4/F
8.081	0.553	tNET	RR	1	R9C59[3][A]	gw_gao_inst_0/u_la0_top/op_reg_en_s7/I0
8.579	0.498	tINS	RR	34	R9C59[3][A]	gw_gao_inst_0/u_la0_top/op_reg_en_s7/F
8.586	0.008	tNET	RR	1	R9C59[1][B]	gw_gao_inst_0/u_la0_top/addr_ct_en_s30/I3
9.048	0.461	tINS	RR	3	R9C59[1][B]	gw_gao_inst_0/u_la0_top/addr_ct_en_s30/F
9.053	0.005	tNET	RR	1	R9C59[0][B]	gw_gao_inst_0/u_la0_top/word_ct_en_s26/I2
9.569	0.516	tINS	RR	6	R9C59[0][B]	gw_gao_inst_0/u_la0_top/word_ct_en_s26/F
9.771	0.203	tNET	RR	1	R7C59[2][A]	gw_gao_inst_0/u_la0_top/word_ct_en_s23/I3
10.298	0.526	tINS	RR	16	R7C59[2][A]	gw_gao_inst_0/u_la0_top/word_ct_en_s23/F
11.391	1.094	tNET	RR	1	R12C59[1][A]	gw_gao_inst_0/u_la0_top/word_count_8_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
50.000	50.000					active clock edge time
50.000	0.000					tck_pad_i
50.000	0.000	tCL	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/I
50.682	0.683	tINS	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/O
50.682	0.000	tNET	RR	1	R28C89	gw_gao_inst_0/u_gw_jtag/tck_pad_i
51.365	0.683	tINS	RR	258	R28C89	gw_gao_inst_0/u_gw_jtag/tck_o
54.033	2.668	tNET	RR	1	R12C59[1][A]	gw_gao_inst_0/u_la0_top/word_count_8_s0/CLK
53.722	-0.311	tSu		1	R12C59[1][A]	gw_gao_inst_0/u_la0_top/word_count_8_s0

Path Statistics:

Clock Skew	-0.038
Setup Relationship	50.000
Logic Level	7
Arrival Clock Path Delay	cell: 1.365, 33.528%; route: 2.706, 66.472%
Arrival Data Path Delay	cell: 2.984, 40.762%; route: 3.954, 54.013%; tC2Q: 0.382, 5.225%
Required Clock Path Delay	cell: 1.365, 33.847%; route: 2.668, 66.153%

Path11

Path Summary:

Slack	32.093
Data Arrival Time	19.729
Data Required Time	51.822
From	mem_data_in_mem_data_in_0_1_s
To	uut/FP_Exponential_inst/frac_part_63_s3
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.683	0.683	tINS	RR	2137	IOB29[A]	clk_ibuf/O
2.623	1.941	tNET	RR	16	BSRAM_R10[17]	mem_data_in_mem_data_in_0_1_s/CLK
4.633	2.010	tC2Q	RR	11	BSRAM_R10[17]	mem_data_in_mem_data_in_0_1_s/DO[5]
6.397	1.764	tNET	RR	1	R16C51[2][A]	uut/FP_Exponential_inst/n42_s6/I0
6.858	0.461	tINS	RR	2	R16C51[2][A]	uut/FP_Exponential_inst/n42_s6/F
7.208	0.350	tNET	RR	1	R14C51[3][B]	uut/FP_Exponential_inst/n140_Z_s2/I2
7.623	0.415	tINS	RR	3	R14C51[3][B]	uut/FP_Exponential_inst/n140_Z_s2/F
7.976	0.352	tNET	RR	1	R13C50[2][B]	uut/FP_Exponential_inst/n144_Z_s3/I0
8.502	0.526	tINS	RR	2	R13C50[2][B]	uut/FP_Exponential_inst/n144_Z_s3/F
8.697	0.195	tNET	RR	1	R13C48[3][A]	uut/FP_Exponential_inst/n152_Z_s0/I1
9.195	0.498	tINS	RR	2	R13C48[3][A]	uut/FP_Exponential_inst/n152_Z_s0/F
9.355	0.160	tNET	RR	1	R12C48[2][B]	uut/FP_Exponential_inst/n168_Z_s0/I1
9.881	0.526	tINS	RR	2	R12C48[2][B]	uut/FP_Exponential_inst/n168_Z_s0/F
10.873	0.993	tNET	RR	1	R15C54[2][B]	uut/FP_Exponential_inst/n168_Z_s/I1
11.390	0.516	tINS	RR	1	R15C54[2][B]	uut/FP_Exponential_inst/n168_Z_s/F
12.613	1.224	tNET	RR	21	DSP_R19[19]	uut/FP_Exponential_inst/mult_122_s7/A[24]
14.963	2.349	tINS	RR	1	DSP_R19[19]	uut/FP_Exponential_inst/mult_122_s7/DOUT[42]
15.884	0.921	tNET	RR	2	R11C54[2][A]	uut/FP_Exponential_inst/n246_s0/I0
16.447	0.563	tINS	RF	1	R11C54[2][A]	uut/FP_Exponential_inst/n246_s0/COUT
16.447	0.000	tNET	FF	2	R11C54[2][B]	uut/FP_Exponential_inst/n245_s0/CIN
16.497	0.050	tINS	FR	1	R11C54[2][B]	uut/FP_Exponential_inst/n245_s0/COUT
16.497	0.000	tNET	RR	2	R11C55[0][A]	uut/FP_Exponential_inst/n244_s0/CIN
16.547	0.050	tINS	RR	1	R11C55[0][A]	uut/FP_Exponential_inst/n244_s0/COUT
16.547	0.000	tNET	RR	2	R11C55[0][B]	uut/FP_Exponential_inst/n243_s0/CIN
16.597	0.050	tINS	RR	1	R11C55[0][B]	uut/FP_Exponential_inst/n243_s0/COUT
16.597	0.000	tNET	RR	2	R11C55[1][A]	uut/FP_Exponential_inst/n242_s0/CIN
16.647	0.050	tINS	RR	1	R11C55[1][A]	uut/FP_Exponential_inst/n242_s0/COUT
16.647	0.000	tNET	RR	2	R11C55[1][B]	uut/FP_Exponential_inst/n241_s0/CIN
16.697	0.050	tINS	RR	1	R11C55[1][B]	uut/FP_Exponential_inst/n241_s0/COUT
16.697	0.000	tNET	RR	2	R11C55[2][A]	uut/FP_Exponential_inst/n240_s0/CIN
16.747	0.050	tINS	RR	1	R11C55[2][A]	uut/FP_Exponential_inst/n240_s0/COUT
16.747	0.000	tNET	RR	2	R11C55[2][B]	uut/FP_Exponential_inst/n239_s0/CIN
16.797	0.050	tINS	RR	1	R11C55[2][B]	uut/FP_Exponential_inst/n239_s0/COUT
16.797	0.000	tNET	RR	2	R11C56[0][A]	uut/FP_Exponential_inst/n238_s0/CIN
16.847	0.050	tINS	RR	1	R11C56[0][A]	uut/FP_Exponential_inst/n238_s0/COUT
16.847	0.000	tNET	RR	2	R11C56[0][B]	uut/FP_Exponential_inst/n237_s0/CIN
16.897	0.050	tINS	RR	1	R11C56[0][B]	uut/FP_Exponential_inst/n237_s0/COUT
16.897	0.000	tNET	RR	2	R11C56[1][A]	uut/FP_Exponential_inst/n236_s0/CIN
16.947	0.050	tINS	RR	1	R11C56[1][A]	uut/FP_Exponential_inst/n236_s0/COUT
16.947	0.000	tNET	RR	2	R11C56[1][B]	uut/FP_Exponential_inst/n235_s0/CIN
16.997	0.050	tINS	RR	1	R11C56[1][B]	uut/FP_Exponential_inst/n235_s0/COUT
16.997	0.000	tNET	RR	2	R11C56[2][A]	uut/FP_Exponential_inst/n234_s0/CIN
17.047	0.050	tINS	RR	1	R11C56[2][A]	uut/FP_Exponential_inst/n234_s0/COUT
17.047	0.000	tNET	RR	2	R11C56[2][B]	uut/FP_Exponential_inst/n233_s0/CIN
17.343	0.296	tINS	RR	1	R11C56[2][B]	uut/FP_Exponential_inst/n233_s0/SUM
18.153	0.810	tNET	RR	1	R18C59[3][A]	uut/FP_Exponential_inst/n396_s0/I0
18.650	0.498	tINS	RR	2	R18C59[3][A]	uut/FP_Exponential_inst/n396_s0/F
19.729	1.079	tNET	RR	1	DSP_R19[11]	uut/FP_Exponential_inst/frac_part_63_s3/B[31]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
50.000	50.000					active clock edge time
50.000	0.000					clk
50.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
50.682	0.683	tINS	RR	2137	IOB29[A]	clk_ibuf/O
52.625	1.942	tNET	RR	1	DSP_R19[11]	uut/FP_Exponential_inst/frac_part_63_s3/CLK[0]
51.822	-0.803	tSu		1	DSP_R19[11]	uut/FP_Exponential_inst/frac_part_63_s3

Path Statistics:

Clock Skew	0.002
Setup Relationship	50.000
Logic Level	12
Arrival Clock Path Delay	cell: 0.683, 26.015%; route: 1.941, 73.985%
Arrival Data Path Delay	cell: 7.248, 42.373%; route: 7.848, 45.877%; tC2Q: 2.010, 11.750%
Required Clock Path Delay	cell: 0.683, 26.000%; route: 1.942, 74.000%

Path12

Path Summary:

Slack	32.120
Data Arrival Time	19.735
Data Required Time	51.855
From	mem_data_in_mem_data_in_0_1_s
To	uut/FP_Exponential_inst/frac_part_63_s3
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.683	0.683	tINS	RR	2137	IOB29[A]	clk_ibuf/O
2.623	1.941	tNET	RR	16	BSRAM_R10[17]	mem_data_in_mem_data_in_0_1_s/CLK
4.633	2.010	tC2Q	RR	11	BSRAM_R10[17]	mem_data_in_mem_data_in_0_1_s/DO[5]
6.397	1.764	tNET	RR	1	R16C51[2][A]	uut/FP_Exponential_inst/n42_s6/I0
6.858	0.461	tINS	RR	2	R16C51[2][A]	uut/FP_Exponential_inst/n42_s6/F
7.208	0.350	tNET	RR	1	R14C51[3][B]	uut/FP_Exponential_inst/n140_Z_s2/I2
7.623	0.415	tINS	RR	3	R14C51[3][B]	uut/FP_Exponential_inst/n140_Z_s2/F
7.976	0.352	tNET	RR	1	R13C50[2][B]	uut/FP_Exponential_inst/n144_Z_s3/I0
8.502	0.526	tINS	RR	2	R13C50[2][B]	uut/FP_Exponential_inst/n144_Z_s3/F
8.697	0.195	tNET	RR	1	R13C48[3][A]	uut/FP_Exponential_inst/n152_Z_s0/I1
9.195	0.498	tINS	RR	2	R13C48[3][A]	uut/FP_Exponential_inst/n152_Z_s0/F
9.355	0.160	tNET	RR	1	R12C48[2][B]	uut/FP_Exponential_inst/n168_Z_s0/I1
9.881	0.526	tINS	RR	2	R12C48[2][B]	uut/FP_Exponential_inst/n168_Z_s0/F
10.873	0.993	tNET	RR	1	R15C54[2][B]	uut/FP_Exponential_inst/n168_Z_s/I1
11.390	0.516	tINS	RR	1	R15C54[2][B]	uut/FP_Exponential_inst/n168_Z_s/F
12.613	1.224	tNET	RR	21	DSP_R19[19]	uut/FP_Exponential_inst/mult_122_s7/A[24]
14.963	2.349	tINS	RR	1	DSP_R19[19]	uut/FP_Exponential_inst/mult_122_s7/DOUT[42]
15.884	0.921	tNET	RR	2	R11C54[2][A]	uut/FP_Exponential_inst/n246_s0/I0
16.447	0.563	tINS	RF	1	R11C54[2][A]	uut/FP_Exponential_inst/n246_s0/COUT
16.447	0.000	tNET	FF	2	R11C54[2][B]	uut/FP_Exponential_inst/n245_s0/CIN
16.497	0.050	tINS	FR	1	R11C54[2][B]	uut/FP_Exponential_inst/n245_s0/COUT
16.497	0.000	tNET	RR	2	R11C55[0][A]	uut/FP_Exponential_inst/n244_s0/CIN
16.547	0.050	tINS	RR	1	R11C55[0][A]	uut/FP_Exponential_inst/n244_s0/COUT
16.547	0.000	tNET	RR	2	R11C55[0][B]	uut/FP_Exponential_inst/n243_s0/CIN
16.597	0.050	tINS	RR	1	R11C55[0][B]	uut/FP_Exponential_inst/n243_s0/COUT
16.597	0.000	tNET	RR	2	R11C55[1][A]	uut/FP_Exponential_inst/n242_s0/CIN
16.647	0.050	tINS	RR	1	R11C55[1][A]	uut/FP_Exponential_inst/n242_s0/COUT
16.647	0.000	tNET	RR	2	R11C55[1][B]	uut/FP_Exponential_inst/n241_s0/CIN
16.697	0.050	tINS	RR	1	R11C55[1][B]	uut/FP_Exponential_inst/n241_s0/COUT
16.697	0.000	tNET	RR	2	R11C55[2][A]	uut/FP_Exponential_inst/n240_s0/CIN
16.747	0.050	tINS	RR	1	R11C55[2][A]	uut/FP_Exponential_inst/n240_s0/COUT
16.747	0.000	tNET	RR	2	R11C55[2][B]	uut/FP_Exponential_inst/n239_s0/CIN
16.797	0.050	tINS	RR	1	R11C55[2][B]	uut/FP_Exponential_inst/n239_s0/COUT
16.797	0.000	tNET	RR	2	R11C56[0][A]	uut/FP_Exponential_inst/n238_s0/CIN
16.847	0.050	tINS	RR	1	R11C56[0][A]	uut/FP_Exponential_inst/n238_s0/COUT
16.847	0.000	tNET	RR	2	R11C56[0][B]	uut/FP_Exponential_inst/n237_s0/CIN
17.143	0.296	tINS	RR	1	R11C56[0][B]	uut/FP_Exponential_inst/n237_s0/SUM
18.000	0.858	tNET	RR	1	R18C60[3][A]	uut/FP_Exponential_inst/n400_s0/I0
18.522	0.521	tINS	RR	2	R18C60[3][A]	uut/FP_Exponential_inst/n400_s0/F
19.735	1.214	tNET	RR	1	DSP_R19[11]	uut/FP_Exponential_inst/frac_part_63_s3/B[27]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
50.000	50.000					active clock edge time
50.000	0.000					clk
50.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
50.682	0.683	tINS	RR	2137	IOB29[A]	clk_ibuf/O
52.625	1.942	tNET	RR	1	DSP_R19[11]	uut/FP_Exponential_inst/frac_part_63_s3/CLK[0]
51.855	-0.770	tSu		1	DSP_R19[11]	uut/FP_Exponential_inst/frac_part_63_s3

Path Statistics:

Clock Skew	0.002
Setup Relationship	50.000
Logic Level	12
Arrival Clock Path Delay	cell: 0.683, 26.015%; route: 1.941, 73.985%
Arrival Data Path Delay	cell: 7.072, 41.328%; route: 8.030, 46.926%; tC2Q: 2.010, 11.746%
Required Clock Path Delay	cell: 0.683, 26.000%; route: 1.942, 74.000%

Path13

Path Summary:

Slack	32.312
Data Arrival Time	19.500
Data Required Time	51.813
From	mem_data_in_mem_data_in_0_1_s
To	uut/FP_Exponential_inst/frac_part_63_s4
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.683	0.683	tINS	RR	2137	IOB29[A]	clk_ibuf/O
2.623	1.941	tNET	RR	16	BSRAM_R10[17]	mem_data_in_mem_data_in_0_1_s/CLK
4.633	2.010	tC2Q	RR	11	BSRAM_R10[17]	mem_data_in_mem_data_in_0_1_s/DO[5]
6.397	1.764	tNET	RR	1	R16C51[2][A]	uut/FP_Exponential_inst/n42_s6/I0
6.858	0.461	tINS	RR	2	R16C51[2][A]	uut/FP_Exponential_inst/n42_s6/F
7.208	0.350	tNET	RR	1	R14C51[3][B]	uut/FP_Exponential_inst/n140_Z_s2/I2
7.623	0.415	tINS	RR	3	R14C51[3][B]	uut/FP_Exponential_inst/n140_Z_s2/F
7.976	0.352	tNET	RR	1	R13C50[2][B]	uut/FP_Exponential_inst/n144_Z_s3/I0
8.502	0.526	tINS	RR	2	R13C50[2][B]	uut/FP_Exponential_inst/n144_Z_s3/F
8.697	0.195	tNET	RR	1	R13C48[3][A]	uut/FP_Exponential_inst/n152_Z_s0/I1
9.195	0.498	tINS	RR	2	R13C48[3][A]	uut/FP_Exponential_inst/n152_Z_s0/F
9.355	0.160	tNET	RR	1	R12C48[2][B]	uut/FP_Exponential_inst/n168_Z_s0/I1
9.881	0.526	tINS	RR	2	R12C48[2][B]	uut/FP_Exponential_inst/n168_Z_s0/F
10.873	0.993	tNET	RR	1	R15C54[2][B]	uut/FP_Exponential_inst/n168_Z_s/I1
11.390	0.516	tINS	RR	1	R15C54[2][B]	uut/FP_Exponential_inst/n168_Z_s/F
12.613	1.224	tNET	RR	21	DSP_R19[19]	uut/FP_Exponential_inst/mult_122_s7/A[24]
14.963	2.349	tINS	RR	1	DSP_R19[19]	uut/FP_Exponential_inst/mult_122_s7/DOUT[42]
15.884	0.921	tNET	RR	2	R11C54[2][A]	uut/FP_Exponential_inst/n246_s0/I0
16.447	0.563	tINS	RF	1	R11C54[2][A]	uut/FP_Exponential_inst/n246_s0/COUT
16.447	0.000	tNET	FF	2	R11C54[2][B]	uut/FP_Exponential_inst/n245_s0/CIN
16.497	0.050	tINS	FR	1	R11C54[2][B]	uut/FP_Exponential_inst/n245_s0/COUT
16.497	0.000	tNET	RR	2	R11C55[0][A]	uut/FP_Exponential_inst/n244_s0/CIN
16.547	0.050	tINS	RR	1	R11C55[0][A]	uut/FP_Exponential_inst/n244_s0/COUT
16.547	0.000	tNET	RR	2	R11C55[0][B]	uut/FP_Exponential_inst/n243_s0/CIN
16.597	0.050	tINS	RR	1	R11C55[0][B]	uut/FP_Exponential_inst/n243_s0/COUT
16.597	0.000	tNET	RR	2	R11C55[1][A]	uut/FP_Exponential_inst/n242_s0/CIN
16.647	0.050	tINS	RR	1	R11C55[1][A]	uut/FP_Exponential_inst/n242_s0/COUT
16.647	0.000	tNET	RR	2	R11C55[1][B]	uut/FP_Exponential_inst/n241_s0/CIN
16.697	0.050	tINS	RR	1	R11C55[1][B]	uut/FP_Exponential_inst/n241_s0/COUT
16.697	0.000	tNET	RR	2	R11C55[2][A]	uut/FP_Exponential_inst/n240_s0/CIN
16.747	0.050	tINS	RR	1	R11C55[2][A]	uut/FP_Exponential_inst/n240_s0/COUT
16.747	0.000	tNET	RR	2	R11C55[2][B]	uut/FP_Exponential_inst/n239_s0/CIN
16.797	0.050	tINS	RR	1	R11C55[2][B]	uut/FP_Exponential_inst/n239_s0/COUT
16.797	0.000	tNET	RR	2	R11C56[0][A]	uut/FP_Exponential_inst/n238_s0/CIN
16.847	0.050	tINS	RR	1	R11C56[0][A]	uut/FP_Exponential_inst/n238_s0/COUT
16.847	0.000	tNET	RR	2	R11C56[0][B]	uut/FP_Exponential_inst/n237_s0/CIN
16.897	0.050	tINS	RR	1	R11C56[0][B]	uut/FP_Exponential_inst/n237_s0/COUT
16.897	0.000	tNET	RR	2	R11C56[1][A]	uut/FP_Exponential_inst/n236_s0/CIN
16.947	0.050	tINS	RR	1	R11C56[1][A]	uut/FP_Exponential_inst/n236_s0/COUT
16.947	0.000	tNET	RR	2	R11C56[1][B]	uut/FP_Exponential_inst/n235_s0/CIN
16.997	0.050	tINS	RR	1	R11C56[1][B]	uut/FP_Exponential_inst/n235_s0/COUT
16.997	0.000	tNET	RR	2	R11C56[2][A]	uut/FP_Exponential_inst/n234_s0/CIN
17.047	0.050	tINS	RR	1	R11C56[2][A]	uut/FP_Exponential_inst/n234_s0/COUT
17.047	0.000	tNET	RR	2	R11C56[2][B]	uut/FP_Exponential_inst/n233_s0/CIN
17.343	0.296	tINS	RR	1	R11C56[2][B]	uut/FP_Exponential_inst/n233_s0/SUM
18.153	0.810	tNET	RR	1	R18C59[3][A]	uut/FP_Exponential_inst/n396_s0/I0
18.650	0.498	tINS	RR	2	R18C59[3][A]	uut/FP_Exponential_inst/n396_s0/F
19.500	0.850	tNET	RR	1	DSP_R19[21]	uut/FP_Exponential_inst/frac_part_63_s4/B[31]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
50.000	50.000					active clock edge time
50.000	0.000					clk
50.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
50.682	0.683	tINS	RR	2137	IOB29[A]	clk_ibuf/O
52.616	1.933	tNET	RR	1	DSP_R19[21]	uut/FP_Exponential_inst/frac_part_63_s4/CLK[0]
51.813	-0.803	tSu		1	DSP_R19[21]	uut/FP_Exponential_inst/frac_part_63_s4

Path Statistics:

Clock Skew	-0.008
Setup Relationship	50.000
Logic Level	12
Arrival Clock Path Delay	cell: 0.683, 26.015%; route: 1.941, 73.985%
Arrival Data Path Delay	cell: 7.248, 42.947%; route: 7.619, 45.143%; tC2Q: 2.010, 11.910%
Required Clock Path Delay	cell: 0.683, 26.093%; route: 1.933, 73.907%

Path14

Path Summary:

Slack	32.699
Data Arrival Time	19.147
Data Required Time	51.846
From	mem_data_in_mem_data_in_0_1_s
To	uut/FP_Exponential_inst/frac_part_63_s4
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.683	0.683	tINS	RR	2137	IOB29[A]	clk_ibuf/O
2.623	1.941	tNET	RR	16	BSRAM_R10[17]	mem_data_in_mem_data_in_0_1_s/CLK
4.633	2.010	tC2Q	RR	11	BSRAM_R10[17]	mem_data_in_mem_data_in_0_1_s/DO[5]
6.397	1.764	tNET	RR	1	R16C51[2][A]	uut/FP_Exponential_inst/n42_s6/I0
6.858	0.461	tINS	RR	2	R16C51[2][A]	uut/FP_Exponential_inst/n42_s6/F
7.208	0.350	tNET	RR	1	R14C51[3][B]	uut/FP_Exponential_inst/n140_Z_s2/I2
7.623	0.415	tINS	RR	3	R14C51[3][B]	uut/FP_Exponential_inst/n140_Z_s2/F
7.976	0.352	tNET	RR	1	R13C50[2][B]	uut/FP_Exponential_inst/n144_Z_s3/I0
8.502	0.526	tINS	RR	2	R13C50[2][B]	uut/FP_Exponential_inst/n144_Z_s3/F
8.697	0.195	tNET	RR	1	R13C48[3][A]	uut/FP_Exponential_inst/n152_Z_s0/I1
9.195	0.498	tINS	RR	2	R13C48[3][A]	uut/FP_Exponential_inst/n152_Z_s0/F
9.355	0.160	tNET	RR	1	R12C48[2][B]	uut/FP_Exponential_inst/n168_Z_s0/I1
9.881	0.526	tINS	RR	2	R12C48[2][B]	uut/FP_Exponential_inst/n168_Z_s0/F
10.873	0.993	tNET	RR	1	R15C54[2][B]	uut/FP_Exponential_inst/n168_Z_s/I1
11.390	0.516	tINS	RR	1	R15C54[2][B]	uut/FP_Exponential_inst/n168_Z_s/F
12.613	1.224	tNET	RR	21	DSP_R19[19]	uut/FP_Exponential_inst/mult_122_s7/A[24]
14.963	2.349	tINS	RR	1	DSP_R19[19]	uut/FP_Exponential_inst/mult_122_s7/DOUT[42]
15.884	0.921	tNET	RR	2	R11C54[2][A]	uut/FP_Exponential_inst/n246_s0/I0
16.447	0.563	tINS	RF	1	R11C54[2][A]	uut/FP_Exponential_inst/n246_s0/COUT
16.447	0.000	tNET	FF	2	R11C54[2][B]	uut/FP_Exponential_inst/n245_s0/CIN
16.497	0.050	tINS	FR	1	R11C54[2][B]	uut/FP_Exponential_inst/n245_s0/COUT
16.497	0.000	tNET	RR	2	R11C55[0][A]	uut/FP_Exponential_inst/n244_s0/CIN
16.547	0.050	tINS	RR	1	R11C55[0][A]	uut/FP_Exponential_inst/n244_s0/COUT
16.547	0.000	tNET	RR	2	R11C55[0][B]	uut/FP_Exponential_inst/n243_s0/CIN
16.597	0.050	tINS	RR	1	R11C55[0][B]	uut/FP_Exponential_inst/n243_s0/COUT
16.597	0.000	tNET	RR	2	R11C55[1][A]	uut/FP_Exponential_inst/n242_s0/CIN
16.647	0.050	tINS	RR	1	R11C55[1][A]	uut/FP_Exponential_inst/n242_s0/COUT
16.647	0.000	tNET	RR	2	R11C55[1][B]	uut/FP_Exponential_inst/n241_s0/CIN
16.697	0.050	tINS	RR	1	R11C55[1][B]	uut/FP_Exponential_inst/n241_s0/COUT
16.697	0.000	tNET	RR	2	R11C55[2][A]	uut/FP_Exponential_inst/n240_s0/CIN
16.747	0.050	tINS	RR	1	R11C55[2][A]	uut/FP_Exponential_inst/n240_s0/COUT
16.747	0.000	tNET	RR	2	R11C55[2][B]	uut/FP_Exponential_inst/n239_s0/CIN
16.797	0.050	tINS	RR	1	R11C55[2][B]	uut/FP_Exponential_inst/n239_s0/COUT
16.797	0.000	tNET	RR	2	R11C56[0][A]	uut/FP_Exponential_inst/n238_s0/CIN
16.847	0.050	tINS	RR	1	R11C56[0][A]	uut/FP_Exponential_inst/n238_s0/COUT
16.847	0.000	tNET	RR	2	R11C56[0][B]	uut/FP_Exponential_inst/n237_s0/CIN
17.143	0.296	tINS	RR	1	R11C56[0][B]	uut/FP_Exponential_inst/n237_s0/SUM
18.000	0.858	tNET	RR	1	R18C60[3][A]	uut/FP_Exponential_inst/n400_s0/I0
18.522	0.521	tINS	RR	2	R18C60[3][A]	uut/FP_Exponential_inst/n400_s0/F
19.147	0.625	tNET	RR	1	DSP_R19[21]	uut/FP_Exponential_inst/frac_part_63_s4/B[27]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
50.000	50.000					active clock edge time
50.000	0.000					clk
50.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
50.682	0.683	tINS	RR	2137	IOB29[A]	clk_ibuf/O
52.616	1.933	tNET	RR	1	DSP_R19[21]	uut/FP_Exponential_inst/frac_part_63_s4/CLK[0]
51.846	-0.770	tSu		1	DSP_R19[21]	uut/FP_Exponential_inst/frac_part_63_s4

Path Statistics:

Clock Skew	-0.008
Setup Relationship	50.000
Logic Level	12
Arrival Clock Path Delay	cell: 0.683, 26.015%; route: 1.941, 73.985%
Arrival Data Path Delay	cell: 7.072, 42.800%; route: 7.441, 45.035%; tC2Q: 2.010, 12.165%
Required Clock Path Delay	cell: 0.683, 26.093%; route: 1.933, 73.907%

Path15

Path Summary:

Slack	32.725
Data Arrival Time	19.267
Data Required Time	51.992
From	mem_data_in_mem_data_in_0_1_s
To	uut/FP_Exponential_inst/frac_part_63_s3
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.683	0.683	tINS	RR	2137	IOB29[A]	clk_ibuf/O
2.623	1.941	tNET	RR	16	BSRAM_R10[17]	mem_data_in_mem_data_in_0_1_s/CLK
4.633	2.010	tC2Q	RR	11	BSRAM_R10[17]	mem_data_in_mem_data_in_0_1_s/DO[5]
6.397	1.764	tNET	RR	1	R16C51[2][A]	uut/FP_Exponential_inst/n42_s6/I0
6.858	0.461	tINS	RR	2	R16C51[2][A]	uut/FP_Exponential_inst/n42_s6/F
7.208	0.350	tNET	RR	1	R14C51[3][B]	uut/FP_Exponential_inst/n140_Z_s2/I2
7.623	0.415	tINS	RR	3	R14C51[3][B]	uut/FP_Exponential_inst/n140_Z_s2/F
7.976	0.352	tNET	RR	1	R13C50[2][B]	uut/FP_Exponential_inst/n144_Z_s3/I0
8.502	0.526	tINS	RR	2	R13C50[2][B]	uut/FP_Exponential_inst/n144_Z_s3/F
8.697	0.195	tNET	RR	1	R13C48[3][A]	uut/FP_Exponential_inst/n152_Z_s0/I1
9.195	0.498	tINS	RR	2	R13C48[3][A]	uut/FP_Exponential_inst/n152_Z_s0/F
9.355	0.160	tNET	RR	1	R12C48[2][B]	uut/FP_Exponential_inst/n168_Z_s0/I1
9.881	0.526	tINS	RR	2	R12C48[2][B]	uut/FP_Exponential_inst/n168_Z_s0/F
10.873	0.993	tNET	RR	1	R15C54[2][B]	uut/FP_Exponential_inst/n168_Z_s/I1
11.390	0.516	tINS	RR	1	R15C54[2][B]	uut/FP_Exponential_inst/n168_Z_s/F
12.613	1.224	tNET	RR	21	DSP_R19[19]	uut/FP_Exponential_inst/mult_122_s7/A[24]
14.963	2.349	tINS	RR	1	DSP_R19[19]	uut/FP_Exponential_inst/mult_122_s7/DOUT[42]
15.884	0.921	tNET	RR	2	R11C54[2][A]	uut/FP_Exponential_inst/n246_s0/I0
16.447	0.563	tINS	RF	1	R11C54[2][A]	uut/FP_Exponential_inst/n246_s0/COUT
16.447	0.000	tNET	FF	2	R11C54[2][B]	uut/FP_Exponential_inst/n245_s0/CIN
16.497	0.050	tINS	FR	1	R11C54[2][B]	uut/FP_Exponential_inst/n245_s0/COUT
16.497	0.000	tNET	RR	2	R11C55[0][A]	uut/FP_Exponential_inst/n244_s0/CIN
16.547	0.050	tINS	RR	1	R11C55[0][A]	uut/FP_Exponential_inst/n244_s0/COUT
16.547	0.000	tNET	RR	2	R11C55[0][B]	uut/FP_Exponential_inst/n243_s0/CIN
16.597	0.050	tINS	RR	1	R11C55[0][B]	uut/FP_Exponential_inst/n243_s0/COUT
16.597	0.000	tNET	RR	2	R11C55[1][A]	uut/FP_Exponential_inst/n242_s0/CIN
16.647	0.050	tINS	RR	1	R11C55[1][A]	uut/FP_Exponential_inst/n242_s0/COUT
16.647	0.000	tNET	RR	2	R11C55[1][B]	uut/FP_Exponential_inst/n241_s0/CIN
16.697	0.050	tINS	RR	1	R11C55[1][B]	uut/FP_Exponential_inst/n241_s0/COUT
16.697	0.000	tNET	RR	2	R11C55[2][A]	uut/FP_Exponential_inst/n240_s0/CIN
16.747	0.050	tINS	RR	1	R11C55[2][A]	uut/FP_Exponential_inst/n240_s0/COUT
16.747	0.000	tNET	RR	2	R11C55[2][B]	uut/FP_Exponential_inst/n239_s0/CIN
16.797	0.050	tINS	RR	1	R11C55[2][B]	uut/FP_Exponential_inst/n239_s0/COUT
16.797	0.000	tNET	RR	2	R11C56[0][A]	uut/FP_Exponential_inst/n238_s0/CIN
16.847	0.050	tINS	RR	1	R11C56[0][A]	uut/FP_Exponential_inst/n238_s0/COUT
16.847	0.000	tNET	RR	2	R11C56[0][B]	uut/FP_Exponential_inst/n237_s0/CIN
16.897	0.050	tINS	RR	1	R11C56[0][B]	uut/FP_Exponential_inst/n237_s0/COUT
16.897	0.000	tNET	RR	2	R11C56[1][A]	uut/FP_Exponential_inst/n236_s0/CIN
16.947	0.050	tINS	RR	1	R11C56[1][A]	uut/FP_Exponential_inst/n236_s0/COUT
16.947	0.000	tNET	RR	2	R11C56[1][B]	uut/FP_Exponential_inst/n235_s0/CIN
16.997	0.050	tINS	RR	1	R11C56[1][B]	uut/FP_Exponential_inst/n235_s0/COUT
16.997	0.000	tNET	RR	2	R11C56[2][A]	uut/FP_Exponential_inst/n234_s0/CIN
17.240	0.244	tINS	RR	1	R11C56[2][A]	uut/FP_Exponential_inst/n234_s0/SUM
18.050	0.810	tNET	RR	1	R18C59[3][B]	uut/FP_Exponential_inst/n397_s0/I0
18.315	0.265	tINS	RR	2	R18C59[3][B]	uut/FP_Exponential_inst/n397_s0/F
19.267	0.951	tNET	RR	1	DSP_R19[11]	uut/FP_Exponential_inst/frac_part_63_s3/B[30]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
50.000	50.000					active clock edge time
50.000	0.000					clk
50.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
50.682	0.683	tINS	RR	2137	IOB29[A]	clk_ibuf/O
52.625	1.942	tNET	RR	1	DSP_R19[11]	uut/FP_Exponential_inst/frac_part_63_s3/CLK[0]
51.992	-0.633	tSu		1	DSP_R19[11]	uut/FP_Exponential_inst/frac_part_63_s3

Path Statistics:

Clock Skew	0.002
Setup Relationship	50.000
Logic Level	12
Arrival Clock Path Delay	cell: 0.683, 26.015%; route: 1.941, 73.985%
Arrival Data Path Delay	cell: 6.913, 41.538%; route: 7.720, 46.385%; tC2Q: 2.010, 12.077%
Required Clock Path Delay	cell: 0.683, 26.000%; route: 1.942, 74.000%

Path16

Path Summary:

Slack	32.817
Data Arrival Time	19.165
Data Required Time	51.982
From	mem_data_in_mem_data_in_0_1_s
To	uut/FP_Exponential_inst/frac_part_63_s4
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.683	0.683	tINS	RR	2137	IOB29[A]	clk_ibuf/O
2.623	1.941	tNET	RR	16	BSRAM_R10[17]	mem_data_in_mem_data_in_0_1_s/CLK
4.633	2.010	tC2Q	RR	11	BSRAM_R10[17]	mem_data_in_mem_data_in_0_1_s/DO[5]
6.397	1.764	tNET	RR	1	R16C51[2][A]	uut/FP_Exponential_inst/n42_s6/I0
6.858	0.461	tINS	RR	2	R16C51[2][A]	uut/FP_Exponential_inst/n42_s6/F
7.208	0.350	tNET	RR	1	R14C51[3][B]	uut/FP_Exponential_inst/n140_Z_s2/I2
7.623	0.415	tINS	RR	3	R14C51[3][B]	uut/FP_Exponential_inst/n140_Z_s2/F
7.976	0.352	tNET	RR	1	R13C50[2][B]	uut/FP_Exponential_inst/n144_Z_s3/I0
8.502	0.526	tINS	RR	2	R13C50[2][B]	uut/FP_Exponential_inst/n144_Z_s3/F
8.697	0.195	tNET	RR	1	R13C48[3][A]	uut/FP_Exponential_inst/n152_Z_s0/I1
9.195	0.498	tINS	RR	2	R13C48[3][A]	uut/FP_Exponential_inst/n152_Z_s0/F
9.355	0.160	tNET	RR	1	R12C48[2][B]	uut/FP_Exponential_inst/n168_Z_s0/I1
9.881	0.526	tINS	RR	2	R12C48[2][B]	uut/FP_Exponential_inst/n168_Z_s0/F
10.873	0.993	tNET	RR	1	R15C54[2][B]	uut/FP_Exponential_inst/n168_Z_s/I1
11.390	0.516	tINS	RR	1	R15C54[2][B]	uut/FP_Exponential_inst/n168_Z_s/F
12.613	1.224	tNET	RR	21	DSP_R19[19]	uut/FP_Exponential_inst/mult_122_s7/A[24]
14.963	2.349	tINS	RR	1	DSP_R19[19]	uut/FP_Exponential_inst/mult_122_s7/DOUT[42]
15.884	0.921	tNET	RR	2	R11C54[2][A]	uut/FP_Exponential_inst/n246_s0/I0
16.447	0.563	tINS	RF	1	R11C54[2][A]	uut/FP_Exponential_inst/n246_s0/COUT
16.447	0.000	tNET	FF	2	R11C54[2][B]	uut/FP_Exponential_inst/n245_s0/CIN
16.497	0.050	tINS	FR	1	R11C54[2][B]	uut/FP_Exponential_inst/n245_s0/COUT
16.497	0.000	tNET	RR	2	R11C55[0][A]	uut/FP_Exponential_inst/n244_s0/CIN
16.547	0.050	tINS	RR	1	R11C55[0][A]	uut/FP_Exponential_inst/n244_s0/COUT
16.547	0.000	tNET	RR	2	R11C55[0][B]	uut/FP_Exponential_inst/n243_s0/CIN
16.597	0.050	tINS	RR	1	R11C55[0][B]	uut/FP_Exponential_inst/n243_s0/COUT
16.597	0.000	tNET	RR	2	R11C55[1][A]	uut/FP_Exponential_inst/n242_s0/CIN
16.647	0.050	tINS	RR	1	R11C55[1][A]	uut/FP_Exponential_inst/n242_s0/COUT
16.647	0.000	tNET	RR	2	R11C55[1][B]	uut/FP_Exponential_inst/n241_s0/CIN
16.697	0.050	tINS	RR	1	R11C55[1][B]	uut/FP_Exponential_inst/n241_s0/COUT
16.697	0.000	tNET	RR	2	R11C55[2][A]	uut/FP_Exponential_inst/n240_s0/CIN
16.747	0.050	tINS	RR	1	R11C55[2][A]	uut/FP_Exponential_inst/n240_s0/COUT
16.747	0.000	tNET	RR	2	R11C55[2][B]	uut/FP_Exponential_inst/n239_s0/CIN
16.797	0.050	tINS	RR	1	R11C55[2][B]	uut/FP_Exponential_inst/n239_s0/COUT
16.797	0.000	tNET	RR	2	R11C56[0][A]	uut/FP_Exponential_inst/n238_s0/CIN
16.847	0.050	tINS	RR	1	R11C56[0][A]	uut/FP_Exponential_inst/n238_s0/COUT
16.847	0.000	tNET	RR	2	R11C56[0][B]	uut/FP_Exponential_inst/n237_s0/CIN
16.897	0.050	tINS	RR	1	R11C56[0][B]	uut/FP_Exponential_inst/n237_s0/COUT
16.897	0.000	tNET	RR	2	R11C56[1][A]	uut/FP_Exponential_inst/n236_s0/CIN
16.947	0.050	tINS	RR	1	R11C56[1][A]	uut/FP_Exponential_inst/n236_s0/COUT
16.947	0.000	tNET	RR	2	R11C56[1][B]	uut/FP_Exponential_inst/n235_s0/CIN
16.997	0.050	tINS	RR	1	R11C56[1][B]	uut/FP_Exponential_inst/n235_s0/COUT
16.997	0.000	tNET	RR	2	R11C56[2][A]	uut/FP_Exponential_inst/n234_s0/CIN
17.240	0.244	tINS	RR	1	R11C56[2][A]	uut/FP_Exponential_inst/n234_s0/SUM
18.050	0.810	tNET	RR	1	R18C59[3][B]	uut/FP_Exponential_inst/n397_s0/I0
18.315	0.265	tINS	RR	2	R18C59[3][B]	uut/FP_Exponential_inst/n397_s0/F
19.165	0.850	tNET	RR	1	DSP_R19[21]	uut/FP_Exponential_inst/frac_part_63_s4/B[30]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
50.000	50.000					active clock edge time
50.000	0.000					clk
50.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
50.682	0.683	tINS	RR	2137	IOB29[A]	clk_ibuf/O
52.616	1.933	tNET	RR	1	DSP_R19[21]	uut/FP_Exponential_inst/frac_part_63_s4/CLK[0]
51.982	-0.633	tSu		1	DSP_R19[21]	uut/FP_Exponential_inst/frac_part_63_s4

Path Statistics:

Clock Skew	-0.008
Setup Relationship	50.000
Logic Level	12
Arrival Clock Path Delay	cell: 0.683, 26.015%; route: 1.941, 73.985%
Arrival Data Path Delay	cell: 6.913, 41.792%; route: 7.619, 46.057%; tC2Q: 2.010, 12.151%
Required Clock Path Delay	cell: 0.683, 26.093%; route: 1.933, 73.907%

Path17

Path Summary:

Slack	32.916
Data Arrival Time	19.073
Data Required Time	51.988
From	mem_data_in_mem_data_in_0_1_s
To	uut/FP_Exponential_inst/frac_part_63_s4
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.683	0.683	tINS	RR	2137	IOB29[A]	clk_ibuf/O
2.623	1.941	tNET	RR	16	BSRAM_R10[17]	mem_data_in_mem_data_in_0_1_s/CLK
4.633	2.010	tC2Q	RR	11	BSRAM_R10[17]	mem_data_in_mem_data_in_0_1_s/DO[5]
6.397	1.764	tNET	RR	1	R16C51[2][A]	uut/FP_Exponential_inst/n42_s6/I0
6.858	0.461	tINS	RR	2	R16C51[2][A]	uut/FP_Exponential_inst/n42_s6/F
7.208	0.350	tNET	RR	1	R14C51[3][B]	uut/FP_Exponential_inst/n140_Z_s2/I2
7.623	0.415	tINS	RR	3	R14C51[3][B]	uut/FP_Exponential_inst/n140_Z_s2/F
7.976	0.352	tNET	RR	1	R13C50[2][B]	uut/FP_Exponential_inst/n144_Z_s3/I0
8.502	0.526	tINS	RR	2	R13C50[2][B]	uut/FP_Exponential_inst/n144_Z_s3/F
8.697	0.195	tNET	RR	1	R13C48[3][A]	uut/FP_Exponential_inst/n152_Z_s0/I1
9.195	0.498	tINS	RR	2	R13C48[3][A]	uut/FP_Exponential_inst/n152_Z_s0/F
9.355	0.160	tNET	RR	1	R12C48[2][B]	uut/FP_Exponential_inst/n168_Z_s0/I1
9.881	0.526	tINS	RR	2	R12C48[2][B]	uut/FP_Exponential_inst/n168_Z_s0/F
10.873	0.993	tNET	RR	1	R15C54[2][B]	uut/FP_Exponential_inst/n168_Z_s/I1
11.390	0.516	tINS	RR	1	R15C54[2][B]	uut/FP_Exponential_inst/n168_Z_s/F
12.613	1.224	tNET	RR	21	DSP_R19[19]	uut/FP_Exponential_inst/mult_122_s7/A[24]
14.963	2.349	tINS	RR	1	DSP_R19[19]	uut/FP_Exponential_inst/mult_122_s7/DOUT[42]
15.884	0.921	tNET	RR	2	R11C54[2][A]	uut/FP_Exponential_inst/n246_s0/I0
16.447	0.563	tINS	RF	1	R11C54[2][A]	uut/FP_Exponential_inst/n246_s0/COUT
16.447	0.000	tNET	FF	2	R11C54[2][B]	uut/FP_Exponential_inst/n245_s0/CIN
16.497	0.050	tINS	FR	1	R11C54[2][B]	uut/FP_Exponential_inst/n245_s0/COUT
16.497	0.000	tNET	RR	2	R11C55[0][A]	uut/FP_Exponential_inst/n244_s0/CIN
16.547	0.050	tINS	RR	1	R11C55[0][A]	uut/FP_Exponential_inst/n244_s0/COUT
16.547	0.000	tNET	RR	2	R11C55[0][B]	uut/FP_Exponential_inst/n243_s0/CIN
16.597	0.050	tINS	RR	1	R11C55[0][B]	uut/FP_Exponential_inst/n243_s0/COUT
16.597	0.000	tNET	RR	2	R11C55[1][A]	uut/FP_Exponential_inst/n242_s0/CIN
16.647	0.050	tINS	RR	1	R11C55[1][A]	uut/FP_Exponential_inst/n242_s0/COUT
16.647	0.000	tNET	RR	2	R11C55[1][B]	uut/FP_Exponential_inst/n241_s0/CIN
16.697	0.050	tINS	RR	1	R11C55[1][B]	uut/FP_Exponential_inst/n241_s0/COUT
16.697	0.000	tNET	RR	2	R11C55[2][A]	uut/FP_Exponential_inst/n240_s0/CIN
16.747	0.050	tINS	RR	1	R11C55[2][A]	uut/FP_Exponential_inst/n240_s0/COUT
16.747	0.000	tNET	RR	2	R11C55[2][B]	uut/FP_Exponential_inst/n239_s0/CIN
16.797	0.050	tINS	RR	1	R11C55[2][B]	uut/FP_Exponential_inst/n239_s0/COUT
16.797	0.000	tNET	RR	2	R11C56[0][A]	uut/FP_Exponential_inst/n238_s0/CIN
16.847	0.050	tINS	RR	1	R11C56[0][A]	uut/FP_Exponential_inst/n238_s0/COUT
16.847	0.000	tNET	RR	2	R11C56[0][B]	uut/FP_Exponential_inst/n237_s0/CIN
16.897	0.050	tINS	RR	1	R11C56[0][B]	uut/FP_Exponential_inst/n237_s0/COUT
16.897	0.000	tNET	RR	2	R11C56[1][A]	uut/FP_Exponential_inst/n236_s0/CIN
16.947	0.050	tINS	RR	1	R11C56[1][A]	uut/FP_Exponential_inst/n236_s0/COUT
16.947	0.000	tNET	RR	2	R11C56[1][B]	uut/FP_Exponential_inst/n235_s0/CIN
17.248	0.301	tINS	RF	1	R11C56[1][B]	uut/FP_Exponential_inst/n235_s0/SUM
17.714	0.466	tNET	FF	1	R18C56[3][B]	uut/FP_Exponential_inst/n398_s0/I0
18.212	0.498	tINS	FR	2	R18C56[3][B]	uut/FP_Exponential_inst/n398_s0/F
19.073	0.861	tNET	RR	1	DSP_R19[21]	uut/FP_Exponential_inst/frac_part_63_s4/B[29]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
50.000	50.000					active clock edge time
50.000	0.000					clk
50.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
50.682	0.683	tINS	RR	2137	IOB29[A]	clk_ibuf/O
52.616	1.933	tNET	RR	1	DSP_R19[21]	uut/FP_Exponential_inst/frac_part_63_s4/CLK[0]
51.988	-0.627	tSu		1	DSP_R19[21]	uut/FP_Exponential_inst/frac_part_63_s4

Path Statistics:

Clock Skew	-0.008
Setup Relationship	50.000
Logic Level	12
Arrival Clock Path Delay	cell: 0.683, 26.015%; route: 1.941, 73.985%
Arrival Data Path Delay	cell: 7.153, 43.486%; route: 7.286, 44.295%; tC2Q: 2.010, 12.219%
Required Clock Path Delay	cell: 0.683, 26.093%; route: 1.933, 73.907%

Path18

Path Summary:

Slack	32.939
Data Arrival Time	18.890
Data Required Time	51.830
From	mem_data_in_mem_data_in_0_1_s
To	uut/FP_Exponential_inst/frac_part_63_s4
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.683	0.683	tINS	RR	2137	IOB29[A]	clk_ibuf/O
2.623	1.941	tNET	RR	16	BSRAM_R10[17]	mem_data_in_mem_data_in_0_1_s/CLK
4.633	2.010	tC2Q	RR	11	BSRAM_R10[17]	mem_data_in_mem_data_in_0_1_s/DO[5]
6.397	1.764	tNET	RR	1	R16C51[2][A]	uut/FP_Exponential_inst/n42_s6/I0
6.858	0.461	tINS	RR	2	R16C51[2][A]	uut/FP_Exponential_inst/n42_s6/F
7.208	0.350	tNET	RR	1	R14C51[3][B]	uut/FP_Exponential_inst/n140_Z_s2/I2
7.623	0.415	tINS	RR	3	R14C51[3][B]	uut/FP_Exponential_inst/n140_Z_s2/F
7.976	0.352	tNET	RR	1	R13C50[2][B]	uut/FP_Exponential_inst/n144_Z_s3/I0
8.502	0.526	tINS	RR	2	R13C50[2][B]	uut/FP_Exponential_inst/n144_Z_s3/F
8.697	0.195	tNET	RR	1	R13C48[3][A]	uut/FP_Exponential_inst/n152_Z_s0/I1
9.195	0.498	tINS	RR	2	R13C48[3][A]	uut/FP_Exponential_inst/n152_Z_s0/F
9.355	0.160	tNET	RR	1	R12C48[2][B]	uut/FP_Exponential_inst/n168_Z_s0/I1
9.881	0.526	tINS	RR	2	R12C48[2][B]	uut/FP_Exponential_inst/n168_Z_s0/F
10.873	0.993	tNET	RR	1	R15C54[2][B]	uut/FP_Exponential_inst/n168_Z_s/I1
11.390	0.516	tINS	RR	1	R15C54[2][B]	uut/FP_Exponential_inst/n168_Z_s/F
12.613	1.224	tNET	RR	21	DSP_R19[19]	uut/FP_Exponential_inst/mult_122_s7/A[24]
14.963	2.349	tINS	RR	1	DSP_R19[19]	uut/FP_Exponential_inst/mult_122_s7/DOUT[42]
15.884	0.921	tNET	RR	2	R11C54[2][A]	uut/FP_Exponential_inst/n246_s0/I0
16.447	0.563	tINS	RF	1	R11C54[2][A]	uut/FP_Exponential_inst/n246_s0/COUT
16.447	0.000	tNET	FF	2	R11C54[2][B]	uut/FP_Exponential_inst/n245_s0/CIN
16.497	0.050	tINS	FR	1	R11C54[2][B]	uut/FP_Exponential_inst/n245_s0/COUT
16.497	0.000	tNET	RR	2	R11C55[0][A]	uut/FP_Exponential_inst/n244_s0/CIN
16.547	0.050	tINS	RR	1	R11C55[0][A]	uut/FP_Exponential_inst/n244_s0/COUT
16.547	0.000	tNET	RR	2	R11C55[0][B]	uut/FP_Exponential_inst/n243_s0/CIN
16.597	0.050	tINS	RR	1	R11C55[0][B]	uut/FP_Exponential_inst/n243_s0/COUT
16.597	0.000	tNET	RR	2	R11C55[1][A]	uut/FP_Exponential_inst/n242_s0/CIN
16.647	0.050	tINS	RR	1	R11C55[1][A]	uut/FP_Exponential_inst/n242_s0/COUT
16.647	0.000	tNET	RR	2	R11C55[1][B]	uut/FP_Exponential_inst/n241_s0/CIN
16.697	0.050	tINS	RR	1	R11C55[1][B]	uut/FP_Exponential_inst/n241_s0/COUT
16.697	0.000	tNET	RR	2	R11C55[2][A]	uut/FP_Exponential_inst/n240_s0/CIN
16.940	0.244	tINS	RF	1	R11C55[2][A]	uut/FP_Exponential_inst/n240_s0/SUM
17.407	0.466	tNET	FF	1	R18C55[1][A]	uut/FP_Exponential_inst/n403_s0/I0
17.933	0.526	tINS	FR	2	R18C55[1][A]	uut/FP_Exponential_inst/n403_s0/F
18.890	0.957	tNET	RR	1	DSP_R19[21]	uut/FP_Exponential_inst/frac_part_63_s4/B[24]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
50.000	50.000					active clock edge time
50.000	0.000					clk
50.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
50.682	0.683	tINS	RR	2137	IOB29[A]	clk_ibuf/O
52.616	1.933	tNET	RR	1	DSP_R19[21]	uut/FP_Exponential_inst/frac_part_63_s4/CLK[0]
51.830	-0.786	tSu		1	DSP_R19[21]	uut/FP_Exponential_inst/frac_part_63_s4

Path Statistics:

Clock Skew	-0.008
Setup Relationship	50.000
Logic Level	12
Arrival Clock Path Delay	cell: 0.683, 26.015%; route: 1.941, 73.985%
Arrival Data Path Delay	cell: 6.874, 42.260%; route: 7.383, 45.383%; tC2Q: 2.010, 12.356%
Required Clock Path Delay	cell: 0.683, 26.093%; route: 1.933, 73.907%

Path19

Path Summary:

Slack	33.002
Data Arrival Time	18.995
Data Required Time	51.997
From	mem_data_in_mem_data_in_0_1_s
To	uut/FP_Exponential_inst/frac_part_63_s4
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.683	0.683	tINS	RR	2137	IOB29[A]	clk_ibuf/O
2.623	1.941	tNET	RR	16	BSRAM_R10[17]	mem_data_in_mem_data_in_0_1_s/CLK
4.633	2.010	tC2Q	RR	11	BSRAM_R10[17]	mem_data_in_mem_data_in_0_1_s/DO[5]
6.397	1.764	tNET	RR	1	R16C51[2][A]	uut/FP_Exponential_inst/n42_s6/I0
6.858	0.461	tINS	RR	2	R16C51[2][A]	uut/FP_Exponential_inst/n42_s6/F
7.208	0.350	tNET	RR	1	R14C51[3][B]	uut/FP_Exponential_inst/n140_Z_s2/I2
7.623	0.415	tINS	RR	3	R14C51[3][B]	uut/FP_Exponential_inst/n140_Z_s2/F
7.976	0.352	tNET	RR	1	R13C50[2][B]	uut/FP_Exponential_inst/n144_Z_s3/I0
8.502	0.526	tINS	RR	2	R13C50[2][B]	uut/FP_Exponential_inst/n144_Z_s3/F
8.697	0.195	tNET	RR	1	R13C48[3][A]	uut/FP_Exponential_inst/n152_Z_s0/I1
9.195	0.498	tINS	RR	2	R13C48[3][A]	uut/FP_Exponential_inst/n152_Z_s0/F
9.355	0.160	tNET	RR	1	R12C48[2][B]	uut/FP_Exponential_inst/n168_Z_s0/I1
9.881	0.526	tINS	RR	2	R12C48[2][B]	uut/FP_Exponential_inst/n168_Z_s0/F
10.873	0.993	tNET	RR	1	R15C54[2][B]	uut/FP_Exponential_inst/n168_Z_s/I1
11.390	0.516	tINS	RR	1	R15C54[2][B]	uut/FP_Exponential_inst/n168_Z_s/F
12.613	1.224	tNET	RR	21	DSP_R19[19]	uut/FP_Exponential_inst/mult_122_s7/A[24]
14.963	2.349	tINS	RR	1	DSP_R19[19]	uut/FP_Exponential_inst/mult_122_s7/DOUT[42]
15.884	0.921	tNET	RR	2	R11C54[2][A]	uut/FP_Exponential_inst/n246_s0/I0
16.447	0.563	tINS	RF	1	R11C54[2][A]	uut/FP_Exponential_inst/n246_s0/COUT
16.447	0.000	tNET	FF	2	R11C54[2][B]	uut/FP_Exponential_inst/n245_s0/CIN
16.497	0.050	tINS	FR	1	R11C54[2][B]	uut/FP_Exponential_inst/n245_s0/COUT
16.497	0.000	tNET	RR	2	R11C55[0][A]	uut/FP_Exponential_inst/n244_s0/CIN
16.547	0.050	tINS	RR	1	R11C55[0][A]	uut/FP_Exponential_inst/n244_s0/COUT
16.547	0.000	tNET	RR	2	R11C55[0][B]	uut/FP_Exponential_inst/n243_s0/CIN
16.597	0.050	tINS	RR	1	R11C55[0][B]	uut/FP_Exponential_inst/n243_s0/COUT
16.597	0.000	tNET	RR	2	R11C55[1][A]	uut/FP_Exponential_inst/n242_s0/CIN
16.647	0.050	tINS	RR	1	R11C55[1][A]	uut/FP_Exponential_inst/n242_s0/COUT
16.647	0.000	tNET	RR	2	R11C55[1][B]	uut/FP_Exponential_inst/n241_s0/CIN
16.948	0.301	tINS	RF	1	R11C55[1][B]	uut/FP_Exponential_inst/n241_s0/SUM
17.414	0.466	tNET	FF	1	R18C55[0][B]	uut/FP_Exponential_inst/n404_s0/I0
17.930	0.516	tINS	FR	2	R18C55[0][B]	uut/FP_Exponential_inst/n404_s0/F
18.995	1.065	tNET	RR	1	DSP_R19[21]	uut/FP_Exponential_inst/frac_part_63_s4/B[23]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
50.000	50.000					active clock edge time
50.000	0.000					clk
50.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
50.682	0.683	tINS	RR	2137	IOB29[A]	clk_ibuf/O
52.616	1.933	tNET	RR	1	DSP_R19[21]	uut/FP_Exponential_inst/frac_part_63_s4/CLK[0]
51.997	-0.619	tSu		1	DSP_R19[21]	uut/FP_Exponential_inst/frac_part_63_s4

Path Statistics:

Clock Skew	-0.008
Setup Relationship	50.000
Logic Level	11
Arrival Clock Path Delay	cell: 0.683, 26.015%; route: 1.941, 73.985%
Arrival Data Path Delay	cell: 6.872, 41.974%; route: 7.490, 45.749%; tC2Q: 2.010, 12.277%
Required Clock Path Delay	cell: 0.683, 26.093%; route: 1.933, 73.907%

Path20

Path Summary:

Slack	33.052
Data Arrival Time	18.945
Data Required Time	51.998
From	mem_data_in_mem_data_in_0_1_s
To	uut/FP_Exponential_inst/frac_part_63_s3
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.683	0.683	tINS	RR	2137	IOB29[A]	clk_ibuf/O
2.623	1.941	tNET	RR	16	BSRAM_R10[17]	mem_data_in_mem_data_in_0_1_s/CLK
4.633	2.010	tC2Q	RR	11	BSRAM_R10[17]	mem_data_in_mem_data_in_0_1_s/DO[5]
6.397	1.764	tNET	RR	1	R16C51[2][A]	uut/FP_Exponential_inst/n42_s6/I0
6.858	0.461	tINS	RR	2	R16C51[2][A]	uut/FP_Exponential_inst/n42_s6/F
7.208	0.350	tNET	RR	1	R14C51[3][B]	uut/FP_Exponential_inst/n140_Z_s2/I2
7.623	0.415	tINS	RR	3	R14C51[3][B]	uut/FP_Exponential_inst/n140_Z_s2/F
7.976	0.352	tNET	RR	1	R13C50[2][B]	uut/FP_Exponential_inst/n144_Z_s3/I0
8.502	0.526	tINS	RR	2	R13C50[2][B]	uut/FP_Exponential_inst/n144_Z_s3/F
8.697	0.195	tNET	RR	1	R13C48[3][A]	uut/FP_Exponential_inst/n152_Z_s0/I1
9.195	0.498	tINS	RR	2	R13C48[3][A]	uut/FP_Exponential_inst/n152_Z_s0/F
9.355	0.160	tNET	RR	1	R12C48[2][B]	uut/FP_Exponential_inst/n168_Z_s0/I1
9.881	0.526	tINS	RR	2	R12C48[2][B]	uut/FP_Exponential_inst/n168_Z_s0/F
10.873	0.993	tNET	RR	1	R15C54[2][B]	uut/FP_Exponential_inst/n168_Z_s/I1
11.390	0.516	tINS	RR	1	R15C54[2][B]	uut/FP_Exponential_inst/n168_Z_s/F
12.613	1.224	tNET	RR	21	DSP_R19[19]	uut/FP_Exponential_inst/mult_122_s7/A[24]
14.963	2.349	tINS	RR	1	DSP_R19[19]	uut/FP_Exponential_inst/mult_122_s7/DOUT[42]
15.884	0.921	tNET	RR	2	R11C54[2][A]	uut/FP_Exponential_inst/n246_s0/I0
16.447	0.563	tINS	RF	1	R11C54[2][A]	uut/FP_Exponential_inst/n246_s0/COUT
16.447	0.000	tNET	FF	2	R11C54[2][B]	uut/FP_Exponential_inst/n245_s0/CIN
16.497	0.050	tINS	FR	1	R11C54[2][B]	uut/FP_Exponential_inst/n245_s0/COUT
16.497	0.000	tNET	RR	2	R11C55[0][A]	uut/FP_Exponential_inst/n244_s0/CIN
16.547	0.050	tINS	RR	1	R11C55[0][A]	uut/FP_Exponential_inst/n244_s0/COUT
16.547	0.000	tNET	RR	2	R11C55[0][B]	uut/FP_Exponential_inst/n243_s0/CIN
16.597	0.050	tINS	RR	1	R11C55[0][B]	uut/FP_Exponential_inst/n243_s0/COUT
16.597	0.000	tNET	RR	2	R11C55[1][A]	uut/FP_Exponential_inst/n242_s0/CIN
16.647	0.050	tINS	RR	1	R11C55[1][A]	uut/FP_Exponential_inst/n242_s0/COUT
16.647	0.000	tNET	RR	2	R11C55[1][B]	uut/FP_Exponential_inst/n241_s0/CIN
16.697	0.050	tINS	RR	1	R11C55[1][B]	uut/FP_Exponential_inst/n241_s0/COUT
16.697	0.000	tNET	RR	2	R11C55[2][A]	uut/FP_Exponential_inst/n240_s0/CIN
16.747	0.050	tINS	RR	1	R11C55[2][A]	uut/FP_Exponential_inst/n240_s0/COUT
16.747	0.000	tNET	RR	2	R11C55[2][B]	uut/FP_Exponential_inst/n239_s0/CIN
16.797	0.050	tINS	RR	1	R11C55[2][B]	uut/FP_Exponential_inst/n239_s0/COUT
16.797	0.000	tNET	RR	2	R11C56[0][A]	uut/FP_Exponential_inst/n238_s0/CIN
16.847	0.050	tINS	RR	1	R11C56[0][A]	uut/FP_Exponential_inst/n238_s0/COUT
16.847	0.000	tNET	RR	2	R11C56[0][B]	uut/FP_Exponential_inst/n237_s0/CIN
16.897	0.050	tINS	RR	1	R11C56[0][B]	uut/FP_Exponential_inst/n237_s0/COUT
16.897	0.000	tNET	RR	2	R11C56[1][A]	uut/FP_Exponential_inst/n236_s0/CIN
16.947	0.050	tINS	RR	1	R11C56[1][A]	uut/FP_Exponential_inst/n236_s0/COUT
16.947	0.000	tNET	RR	2	R11C56[1][B]	uut/FP_Exponential_inst/n235_s0/CIN
17.248	0.301	tINS	RF	1	R11C56[1][B]	uut/FP_Exponential_inst/n235_s0/SUM
17.714	0.466	tNET	FF	1	R18C56[3][B]	uut/FP_Exponential_inst/n398_s0/I0
18.212	0.498	tINS	FR	2	R18C56[3][B]	uut/FP_Exponential_inst/n398_s0/F
18.945	0.734	tNET	RR	1	DSP_R19[11]	uut/FP_Exponential_inst/frac_part_63_s3/B[29]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
50.000	50.000					active clock edge time
50.000	0.000					clk
50.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
50.682	0.683	tINS	RR	2137	IOB29[A]	clk_ibuf/O
52.625	1.942	tNET	RR	1	DSP_R19[11]	uut/FP_Exponential_inst/frac_part_63_s3/CLK[0]
51.998	-0.627	tSu		1	DSP_R19[11]	uut/FP_Exponential_inst/frac_part_63_s3

Path Statistics:

Clock Skew	0.002
Setup Relationship	50.000
Logic Level	12
Arrival Clock Path Delay	cell: 0.683, 26.015%; route: 1.941, 73.985%
Arrival Data Path Delay	cell: 7.153, 43.826%; route: 7.159, 43.860%; tC2Q: 2.010, 12.315%
Required Clock Path Delay	cell: 0.683, 26.000%; route: 1.942, 74.000%

Path21

Path Summary:

Slack	33.095
Data Arrival Time	18.714
Data Required Time	51.809
From	mem_data_in_mem_data_in_0_1_s
To	uut/FP_Exponential_inst/frac_part_63_s4
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.683	0.683	tINS	RR	2137	IOB29[A]	clk_ibuf/O
2.623	1.941	tNET	RR	16	BSRAM_R10[17]	mem_data_in_mem_data_in_0_1_s/CLK
4.633	2.010	tC2Q	RR	11	BSRAM_R10[17]	mem_data_in_mem_data_in_0_1_s/DO[5]
6.397	1.764	tNET	RR	1	R16C51[2][A]	uut/FP_Exponential_inst/n42_s6/I0
6.858	0.461	tINS	RR	2	R16C51[2][A]	uut/FP_Exponential_inst/n42_s6/F
7.208	0.350	tNET	RR	1	R14C51[3][B]	uut/FP_Exponential_inst/n140_Z_s2/I2
7.623	0.415	tINS	RR	3	R14C51[3][B]	uut/FP_Exponential_inst/n140_Z_s2/F
7.976	0.352	tNET	RR	1	R13C50[2][B]	uut/FP_Exponential_inst/n144_Z_s3/I0
8.502	0.526	tINS	RR	2	R13C50[2][B]	uut/FP_Exponential_inst/n144_Z_s3/F
8.697	0.195	tNET	RR	1	R13C48[3][A]	uut/FP_Exponential_inst/n152_Z_s0/I1
9.195	0.498	tINS	RR	2	R13C48[3][A]	uut/FP_Exponential_inst/n152_Z_s0/F
9.355	0.160	tNET	RR	1	R12C48[2][B]	uut/FP_Exponential_inst/n168_Z_s0/I1
9.881	0.526	tINS	RR	2	R12C48[2][B]	uut/FP_Exponential_inst/n168_Z_s0/F
10.873	0.993	tNET	RR	1	R15C54[2][B]	uut/FP_Exponential_inst/n168_Z_s/I1
11.390	0.516	tINS	RR	1	R15C54[2][B]	uut/FP_Exponential_inst/n168_Z_s/F
12.613	1.224	tNET	RR	21	DSP_R19[19]	uut/FP_Exponential_inst/mult_122_s7/A[24]
14.963	2.349	tINS	RR	1	DSP_R19[19]	uut/FP_Exponential_inst/mult_122_s7/DOUT[42]
15.884	0.921	tNET	RR	2	R11C54[2][A]	uut/FP_Exponential_inst/n246_s0/I0
16.447	0.563	tINS	RF	1	R11C54[2][A]	uut/FP_Exponential_inst/n246_s0/COUT
16.447	0.000	tNET	FF	2	R11C54[2][B]	uut/FP_Exponential_inst/n245_s0/CIN
16.497	0.050	tINS	FR	1	R11C54[2][B]	uut/FP_Exponential_inst/n245_s0/COUT
16.497	0.000	tNET	RR	2	R11C55[0][A]	uut/FP_Exponential_inst/n244_s0/CIN
16.547	0.050	tINS	RR	1	R11C55[0][A]	uut/FP_Exponential_inst/n244_s0/COUT
16.547	0.000	tNET	RR	2	R11C55[0][B]	uut/FP_Exponential_inst/n243_s0/CIN
16.597	0.050	tINS	RR	1	R11C55[0][B]	uut/FP_Exponential_inst/n243_s0/COUT
16.597	0.000	tNET	RR	2	R11C55[1][A]	uut/FP_Exponential_inst/n242_s0/CIN
16.647	0.050	tINS	RR	1	R11C55[1][A]	uut/FP_Exponential_inst/n242_s0/COUT
16.647	0.000	tNET	RR	2	R11C55[1][B]	uut/FP_Exponential_inst/n241_s0/CIN
16.697	0.050	tINS	RR	1	R11C55[1][B]	uut/FP_Exponential_inst/n241_s0/COUT
16.697	0.000	tNET	RR	2	R11C55[2][A]	uut/FP_Exponential_inst/n240_s0/CIN
16.747	0.050	tINS	RR	1	R11C55[2][A]	uut/FP_Exponential_inst/n240_s0/COUT
16.747	0.000	tNET	RR	2	R11C55[2][B]	uut/FP_Exponential_inst/n239_s0/CIN
17.043	0.296	tINS	RR	1	R11C55[2][B]	uut/FP_Exponential_inst/n239_s0/SUM
17.492	0.449	tNET	RR	1	R18C55[3][B]	uut/FP_Exponential_inst/n402_s0/I0
17.757	0.265	tINS	RR	2	R18C55[3][B]	uut/FP_Exponential_inst/n402_s0/F
18.714	0.957	tNET	RR	1	DSP_R19[21]	uut/FP_Exponential_inst/frac_part_63_s4/B[25]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
50.000	50.000					active clock edge time
50.000	0.000					clk
50.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
50.682	0.683	tINS	RR	2137	IOB29[A]	clk_ibuf/O
52.616	1.933	tNET	RR	1	DSP_R19[21]	uut/FP_Exponential_inst/frac_part_63_s4/CLK[0]
51.809	-0.807	tSu		1	DSP_R19[21]	uut/FP_Exponential_inst/frac_part_63_s4

Path Statistics:

Clock Skew	-0.008
Setup Relationship	50.000
Logic Level	12
Arrival Clock Path Delay	cell: 0.683, 26.015%; route: 1.941, 73.985%
Arrival Data Path Delay	cell: 6.716, 41.737%; route: 7.365, 45.772%; tC2Q: 2.010, 12.492%
Required Clock Path Delay	cell: 0.683, 26.093%; route: 1.933, 73.907%

Path22

Path Summary:

Slack	33.097
Data Arrival Time	18.909
Data Required Time	52.006
From	mem_data_in_mem_data_in_0_1_s
To	uut/FP_Exponential_inst/frac_part_63_s3
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.683	0.683	tINS	RR	2137	IOB29[A]	clk_ibuf/O
2.623	1.941	tNET	RR	16	BSRAM_R10[17]	mem_data_in_mem_data_in_0_1_s/CLK
4.633	2.010	tC2Q	RR	11	BSRAM_R10[17]	mem_data_in_mem_data_in_0_1_s/DO[5]
6.397	1.764	tNET	RR	1	R16C51[2][A]	uut/FP_Exponential_inst/n42_s6/I0
6.858	0.461	tINS	RR	2	R16C51[2][A]	uut/FP_Exponential_inst/n42_s6/F
7.208	0.350	tNET	RR	1	R14C51[3][B]	uut/FP_Exponential_inst/n140_Z_s2/I2
7.623	0.415	tINS	RR	3	R14C51[3][B]	uut/FP_Exponential_inst/n140_Z_s2/F
7.976	0.352	tNET	RR	1	R13C50[2][B]	uut/FP_Exponential_inst/n144_Z_s3/I0
8.502	0.526	tINS	RR	2	R13C50[2][B]	uut/FP_Exponential_inst/n144_Z_s3/F
8.697	0.195	tNET	RR	1	R13C48[3][A]	uut/FP_Exponential_inst/n152_Z_s0/I1
9.195	0.498	tINS	RR	2	R13C48[3][A]	uut/FP_Exponential_inst/n152_Z_s0/F
9.355	0.160	tNET	RR	1	R12C48[2][B]	uut/FP_Exponential_inst/n168_Z_s0/I1
9.881	0.526	tINS	RR	2	R12C48[2][B]	uut/FP_Exponential_inst/n168_Z_s0/F
10.873	0.993	tNET	RR	1	R15C54[2][B]	uut/FP_Exponential_inst/n168_Z_s/I1
11.390	0.516	tINS	RR	1	R15C54[2][B]	uut/FP_Exponential_inst/n168_Z_s/F
12.613	1.224	tNET	RR	21	DSP_R19[19]	uut/FP_Exponential_inst/mult_122_s7/A[24]
14.963	2.349	tINS	RR	1	DSP_R19[19]	uut/FP_Exponential_inst/mult_122_s7/DOUT[42]
15.884	0.921	tNET	RR	2	R11C54[2][A]	uut/FP_Exponential_inst/n246_s0/I0
16.447	0.563	tINS	RF	1	R11C54[2][A]	uut/FP_Exponential_inst/n246_s0/COUT
16.447	0.000	tNET	FF	2	R11C54[2][B]	uut/FP_Exponential_inst/n245_s0/CIN
16.497	0.050	tINS	FR	1	R11C54[2][B]	uut/FP_Exponential_inst/n245_s0/COUT
16.497	0.000	tNET	RR	2	R11C55[0][A]	uut/FP_Exponential_inst/n244_s0/CIN
16.547	0.050	tINS	RR	1	R11C55[0][A]	uut/FP_Exponential_inst/n244_s0/COUT
16.547	0.000	tNET	RR	2	R11C55[0][B]	uut/FP_Exponential_inst/n243_s0/CIN
16.597	0.050	tINS	RR	1	R11C55[0][B]	uut/FP_Exponential_inst/n243_s0/COUT
16.597	0.000	tNET	RR	2	R11C55[1][A]	uut/FP_Exponential_inst/n242_s0/CIN
16.647	0.050	tINS	RR	1	R11C55[1][A]	uut/FP_Exponential_inst/n242_s0/COUT
16.647	0.000	tNET	RR	2	R11C55[1][B]	uut/FP_Exponential_inst/n241_s0/CIN
16.948	0.301	tINS	RF	1	R11C55[1][B]	uut/FP_Exponential_inst/n241_s0/SUM
17.414	0.466	tNET	FF	1	R18C55[0][B]	uut/FP_Exponential_inst/n404_s0/I0
17.930	0.516	tINS	FR	2	R18C55[0][B]	uut/FP_Exponential_inst/n404_s0/F
18.909	0.979	tNET	RR	1	DSP_R19[11]	uut/FP_Exponential_inst/frac_part_63_s3/B[23]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
50.000	50.000					active clock edge time
50.000	0.000					clk
50.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
50.682	0.683	tINS	RR	2137	IOB29[A]	clk_ibuf/O
52.625	1.942	tNET	RR	1	DSP_R19[11]	uut/FP_Exponential_inst/frac_part_63_s3/CLK[0]
52.006	-0.619	tSu		1	DSP_R19[11]	uut/FP_Exponential_inst/frac_part_63_s3

Path Statistics:

Clock Skew	0.002
Setup Relationship	50.000
Logic Level	11
Arrival Clock Path Delay	cell: 0.683, 26.015%; route: 1.941, 73.985%
Arrival Data Path Delay	cell: 6.872, 42.196%; route: 7.404, 45.462%; tC2Q: 2.010, 12.342%
Required Clock Path Delay	cell: 0.683, 26.000%; route: 1.942, 74.000%

Path23

Path Summary:

Slack	33.109
Data Arrival Time	18.694
Data Required Time	51.803
From	mem_data_in_mem_data_in_0_1_s
To	uut/FP_Exponential_inst/frac_part_63_s4
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.683	0.683	tINS	RR	2137	IOB29[A]	clk_ibuf/O
2.623	1.941	tNET	RR	16	BSRAM_R10[17]	mem_data_in_mem_data_in_0_1_s/CLK
4.633	2.010	tC2Q	RR	11	BSRAM_R10[17]	mem_data_in_mem_data_in_0_1_s/DO[5]
6.397	1.764	tNET	RR	1	R16C51[2][A]	uut/FP_Exponential_inst/n42_s6/I0
6.858	0.461	tINS	RR	2	R16C51[2][A]	uut/FP_Exponential_inst/n42_s6/F
7.208	0.350	tNET	RR	1	R14C51[3][B]	uut/FP_Exponential_inst/n140_Z_s2/I2
7.623	0.415	tINS	RR	3	R14C51[3][B]	uut/FP_Exponential_inst/n140_Z_s2/F
7.976	0.352	tNET	RR	1	R13C50[2][B]	uut/FP_Exponential_inst/n144_Z_s3/I0
8.502	0.526	tINS	RR	2	R13C50[2][B]	uut/FP_Exponential_inst/n144_Z_s3/F
8.697	0.195	tNET	RR	1	R13C48[3][A]	uut/FP_Exponential_inst/n152_Z_s0/I1
9.195	0.498	tINS	RR	2	R13C48[3][A]	uut/FP_Exponential_inst/n152_Z_s0/F
9.355	0.160	tNET	RR	1	R12C48[2][B]	uut/FP_Exponential_inst/n168_Z_s0/I1
9.881	0.526	tINS	RR	2	R12C48[2][B]	uut/FP_Exponential_inst/n168_Z_s0/F
10.873	0.993	tNET	RR	1	R15C54[2][B]	uut/FP_Exponential_inst/n168_Z_s/I1
11.390	0.516	tINS	RR	1	R15C54[2][B]	uut/FP_Exponential_inst/n168_Z_s/F
12.613	1.224	tNET	RR	21	DSP_R19[19]	uut/FP_Exponential_inst/mult_122_s7/A[24]
14.963	2.349	tINS	RR	1	DSP_R19[19]	uut/FP_Exponential_inst/mult_122_s7/DOUT[42]
15.884	0.921	tNET	RR	2	R11C54[2][A]	uut/FP_Exponential_inst/n246_s0/I0
16.447	0.563	tINS	RF	1	R11C54[2][A]	uut/FP_Exponential_inst/n246_s0/COUT
16.447	0.000	tNET	FF	2	R11C54[2][B]	uut/FP_Exponential_inst/n245_s0/CIN
16.497	0.050	tINS	FR	1	R11C54[2][B]	uut/FP_Exponential_inst/n245_s0/COUT
16.497	0.000	tNET	RR	2	R11C55[0][A]	uut/FP_Exponential_inst/n244_s0/CIN
16.547	0.050	tINS	RR	1	R11C55[0][A]	uut/FP_Exponential_inst/n244_s0/COUT
16.547	0.000	tNET	RR	2	R11C55[0][B]	uut/FP_Exponential_inst/n243_s0/CIN
16.597	0.050	tINS	RR	1	R11C55[0][B]	uut/FP_Exponential_inst/n243_s0/COUT
16.597	0.000	tNET	RR	2	R11C55[1][A]	uut/FP_Exponential_inst/n242_s0/CIN
16.647	0.050	tINS	RR	1	R11C55[1][A]	uut/FP_Exponential_inst/n242_s0/COUT
16.647	0.000	tNET	RR	2	R11C55[1][B]	uut/FP_Exponential_inst/n241_s0/CIN
16.697	0.050	tINS	RR	1	R11C55[1][B]	uut/FP_Exponential_inst/n241_s0/COUT
16.697	0.000	tNET	RR	2	R11C55[2][A]	uut/FP_Exponential_inst/n240_s0/CIN
16.747	0.050	tINS	RR	1	R11C55[2][A]	uut/FP_Exponential_inst/n240_s0/COUT
16.747	0.000	tNET	RR	2	R11C55[2][B]	uut/FP_Exponential_inst/n239_s0/CIN
16.797	0.050	tINS	RR	1	R11C55[2][B]	uut/FP_Exponential_inst/n239_s0/COUT
16.797	0.000	tNET	RR	2	R11C56[0][A]	uut/FP_Exponential_inst/n238_s0/CIN
16.847	0.050	tINS	RR	1	R11C56[0][A]	uut/FP_Exponential_inst/n238_s0/COUT
16.847	0.000	tNET	RR	2	R11C56[0][B]	uut/FP_Exponential_inst/n237_s0/CIN
16.897	0.050	tINS	RR	1	R11C56[0][B]	uut/FP_Exponential_inst/n237_s0/COUT
16.897	0.000	tNET	RR	2	R11C56[1][A]	uut/FP_Exponential_inst/n236_s0/CIN
17.140	0.244	tINS	RR	1	R11C56[1][A]	uut/FP_Exponential_inst/n236_s0/SUM
17.570	0.430	tNET	RR	1	R18C56[0][A]	uut/FP_Exponential_inst/n399_s0/I0
17.833	0.262	tINS	RR	2	R18C56[0][A]	uut/FP_Exponential_inst/n399_s0/F
18.694	0.861	tNET	RR	1	DSP_R19[21]	uut/FP_Exponential_inst/frac_part_63_s4/B[28]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
50.000	50.000					active clock edge time
50.000	0.000					clk
50.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
50.682	0.683	tINS	RR	2137	IOB29[A]	clk_ibuf/O
52.616	1.933	tNET	RR	1	DSP_R19[21]	uut/FP_Exponential_inst/frac_part_63_s4/CLK[0]
51.803	-0.812	tSu		1	DSP_R19[21]	uut/FP_Exponential_inst/frac_part_63_s4

Path Statistics:

Clock Skew	-0.008
Setup Relationship	50.000
Logic Level	12
Arrival Clock Path Delay	cell: 0.683, 26.015%; route: 1.941, 73.985%
Arrival Data Path Delay	cell: 6.811, 42.380%; route: 7.250, 45.113%; tC2Q: 2.010, 12.507%
Required Clock Path Delay	cell: 0.683, 26.093%; route: 1.933, 73.907%

Path24

Path Summary:

Slack	33.121
Data Arrival Time	18.723
Data Required Time	51.844
From	mem_data_in_mem_data_in_0_1_s
To	uut/FP_Exponential_inst/frac_part_63_s3
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.683	0.683	tINS	RR	2137	IOB29[A]	clk_ibuf/O
2.623	1.941	tNET	RR	16	BSRAM_R10[17]	mem_data_in_mem_data_in_0_1_s/CLK
4.633	2.010	tC2Q	RR	11	BSRAM_R10[17]	mem_data_in_mem_data_in_0_1_s/DO[5]
6.397	1.764	tNET	RR	1	R16C51[2][A]	uut/FP_Exponential_inst/n42_s6/I0
6.858	0.461	tINS	RR	2	R16C51[2][A]	uut/FP_Exponential_inst/n42_s6/F
7.208	0.350	tNET	RR	1	R14C51[3][B]	uut/FP_Exponential_inst/n140_Z_s2/I2
7.623	0.415	tINS	RR	3	R14C51[3][B]	uut/FP_Exponential_inst/n140_Z_s2/F
7.976	0.352	tNET	RR	1	R13C50[2][B]	uut/FP_Exponential_inst/n144_Z_s3/I0
8.502	0.526	tINS	RR	2	R13C50[2][B]	uut/FP_Exponential_inst/n144_Z_s3/F
8.697	0.195	tNET	RR	1	R13C48[3][A]	uut/FP_Exponential_inst/n152_Z_s0/I1
9.195	0.498	tINS	RR	2	R13C48[3][A]	uut/FP_Exponential_inst/n152_Z_s0/F
9.355	0.160	tNET	RR	1	R12C48[2][B]	uut/FP_Exponential_inst/n168_Z_s0/I1
9.881	0.526	tINS	RR	2	R12C48[2][B]	uut/FP_Exponential_inst/n168_Z_s0/F
10.873	0.993	tNET	RR	1	R15C54[2][B]	uut/FP_Exponential_inst/n168_Z_s/I1
11.390	0.516	tINS	RR	1	R15C54[2][B]	uut/FP_Exponential_inst/n168_Z_s/F
12.613	1.224	tNET	RR	21	DSP_R19[19]	uut/FP_Exponential_inst/mult_122_s7/A[24]
14.963	2.349	tINS	RR	1	DSP_R19[19]	uut/FP_Exponential_inst/mult_122_s7/DOUT[42]
15.884	0.921	tNET	RR	2	R11C54[2][A]	uut/FP_Exponential_inst/n246_s0/I0
16.447	0.563	tINS	RF	1	R11C54[2][A]	uut/FP_Exponential_inst/n246_s0/COUT
16.447	0.000	tNET	FF	2	R11C54[2][B]	uut/FP_Exponential_inst/n245_s0/CIN
16.497	0.050	tINS	FR	1	R11C54[2][B]	uut/FP_Exponential_inst/n245_s0/COUT
16.497	0.000	tNET	RR	2	R11C55[0][A]	uut/FP_Exponential_inst/n244_s0/CIN
16.547	0.050	tINS	RR	1	R11C55[0][A]	uut/FP_Exponential_inst/n244_s0/COUT
16.547	0.000	tNET	RR	2	R11C55[0][B]	uut/FP_Exponential_inst/n243_s0/CIN
16.597	0.050	tINS	RR	1	R11C55[0][B]	uut/FP_Exponential_inst/n243_s0/COUT
16.597	0.000	tNET	RR	2	R11C55[1][A]	uut/FP_Exponential_inst/n242_s0/CIN
16.647	0.050	tINS	RR	1	R11C55[1][A]	uut/FP_Exponential_inst/n242_s0/COUT
16.647	0.000	tNET	RR	2	R11C55[1][B]	uut/FP_Exponential_inst/n241_s0/CIN
16.697	0.050	tINS	RR	1	R11C55[1][B]	uut/FP_Exponential_inst/n241_s0/COUT
16.697	0.000	tNET	RR	2	R11C55[2][A]	uut/FP_Exponential_inst/n240_s0/CIN
16.747	0.050	tINS	RR	1	R11C55[2][A]	uut/FP_Exponential_inst/n240_s0/COUT
16.747	0.000	tNET	RR	2	R11C55[2][B]	uut/FP_Exponential_inst/n239_s0/CIN
16.797	0.050	tINS	RR	1	R11C55[2][B]	uut/FP_Exponential_inst/n239_s0/COUT
16.797	0.000	tNET	RR	2	R11C56[0][A]	uut/FP_Exponential_inst/n238_s0/CIN
17.040	0.244	tINS	RR	1	R11C56[0][A]	uut/FP_Exponential_inst/n238_s0/SUM
17.625	0.585	tNET	RR	1	R18C57[3][A]	uut/FP_Exponential_inst/n401_s0/I0
17.890	0.265	tINS	RR	2	R18C57[3][A]	uut/FP_Exponential_inst/n401_s0/F
18.723	0.832	tNET	RR	1	DSP_R19[11]	uut/FP_Exponential_inst/frac_part_63_s3/B[26]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
50.000	50.000					active clock edge time
50.000	0.000					clk
50.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
50.682	0.683	tINS	RR	2137	IOB29[A]	clk_ibuf/O
52.625	1.942	tNET	RR	1	DSP_R19[11]	uut/FP_Exponential_inst/frac_part_63_s3/CLK[0]
51.844	-0.781	tSu		1	DSP_R19[11]	uut/FP_Exponential_inst/frac_part_63_s3

Path Statistics:

Clock Skew	0.002
Setup Relationship	50.000
Logic Level	12
Arrival Clock Path Delay	cell: 0.683, 26.015%; route: 1.941, 73.985%
Arrival Data Path Delay	cell: 6.713, 41.698%; route: 7.376, 45.817%; tC2Q: 2.010, 12.485%
Required Clock Path Delay	cell: 0.683, 26.000%; route: 1.942, 74.000%

Path25

Path Summary:

Slack	33.131
Data Arrival Time	18.704
Data Required Time	51.835
From	mem_data_in_mem_data_in_0_1_s
To	uut/FP_Exponential_inst/frac_part_63_s3
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.683	0.683	tINS	RR	2137	IOB29[A]	clk_ibuf/O
2.623	1.941	tNET	RR	16	BSRAM_R10[17]	mem_data_in_mem_data_in_0_1_s/CLK
4.633	2.010	tC2Q	RR	11	BSRAM_R10[17]	mem_data_in_mem_data_in_0_1_s/DO[5]
6.397	1.764	tNET	RR	1	R16C51[2][A]	uut/FP_Exponential_inst/n42_s6/I0
6.858	0.461	tINS	RR	2	R16C51[2][A]	uut/FP_Exponential_inst/n42_s6/F
7.208	0.350	tNET	RR	1	R14C51[3][B]	uut/FP_Exponential_inst/n140_Z_s2/I2
7.623	0.415	tINS	RR	3	R14C51[3][B]	uut/FP_Exponential_inst/n140_Z_s2/F
7.976	0.352	tNET	RR	1	R13C50[2][B]	uut/FP_Exponential_inst/n144_Z_s3/I0
8.502	0.526	tINS	RR	2	R13C50[2][B]	uut/FP_Exponential_inst/n144_Z_s3/F
8.697	0.195	tNET	RR	1	R13C48[3][A]	uut/FP_Exponential_inst/n152_Z_s0/I1
9.195	0.498	tINS	RR	2	R13C48[3][A]	uut/FP_Exponential_inst/n152_Z_s0/F
9.355	0.160	tNET	RR	1	R12C48[2][B]	uut/FP_Exponential_inst/n168_Z_s0/I1
9.881	0.526	tINS	RR	2	R12C48[2][B]	uut/FP_Exponential_inst/n168_Z_s0/F
10.873	0.993	tNET	RR	1	R15C54[2][B]	uut/FP_Exponential_inst/n168_Z_s/I1
11.390	0.516	tINS	RR	1	R15C54[2][B]	uut/FP_Exponential_inst/n168_Z_s/F
12.613	1.224	tNET	RR	21	DSP_R19[19]	uut/FP_Exponential_inst/mult_122_s7/A[24]
14.963	2.349	tINS	RR	1	DSP_R19[19]	uut/FP_Exponential_inst/mult_122_s7/DOUT[42]
15.884	0.921	tNET	RR	2	R11C54[2][A]	uut/FP_Exponential_inst/n246_s0/I0
16.447	0.563	tINS	RF	1	R11C54[2][A]	uut/FP_Exponential_inst/n246_s0/COUT
16.447	0.000	tNET	FF	2	R11C54[2][B]	uut/FP_Exponential_inst/n245_s0/CIN
16.497	0.050	tINS	FR	1	R11C54[2][B]	uut/FP_Exponential_inst/n245_s0/COUT
16.497	0.000	tNET	RR	2	R11C55[0][A]	uut/FP_Exponential_inst/n244_s0/CIN
16.740	0.244	tINS	RR	1	R11C55[0][A]	uut/FP_Exponential_inst/n244_s0/SUM
17.325	0.585	tNET	RR	1	R18C55[2][A]	uut/FP_Exponential_inst/n407_s0/I0
17.588	0.262	tINS	RR	2	R18C55[2][A]	uut/FP_Exponential_inst/n407_s0/F
18.704	1.116	tNET	RR	1	DSP_R19[11]	uut/FP_Exponential_inst/frac_part_63_s3/B[20]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
50.000	50.000					active clock edge time
50.000	0.000					clk
50.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
50.682	0.683	tINS	RR	2137	IOB29[A]	clk_ibuf/O
52.625	1.942	tNET	RR	1	DSP_R19[11]	uut/FP_Exponential_inst/frac_part_63_s3/CLK[0]
51.835	-0.790	tSu		1	DSP_R19[11]	uut/FP_Exponential_inst/frac_part_63_s3

Path Statistics:

Clock Skew	0.002
Setup Relationship	50.000
Logic Level	11
Arrival Clock Path Delay	cell: 0.683, 26.015%; route: 1.941, 73.985%
Arrival Data Path Delay	cell: 6.411, 39.866%; route: 7.660, 47.635%; tC2Q: 2.010, 12.499%
Required Clock Path Delay	cell: 0.683, 26.000%; route: 1.942, 74.000%

Hold Analysis Report

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	0.143
Data Arrival Time	1.551
Data Required Time	1.408
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_20_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	2137	IOB29[A]	clk_ibuf/O
1.375	0.700	tNET	RR	1	R27C59[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_20_s0/CLK
1.516	0.141	tC2Q	RF	1	R27C59[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_20_s0/Q
1.551	0.034	tNET	FF	1	BSRAM_R28[18]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[4]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	2137	IOB29[A]	clk_ibuf/O
1.371	0.695	tNET	RR	1	BSRAM_R28[18]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CLKA
1.408	0.037	tHld		1	BSRAM_R28[18]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s

Path Statistics:

Clock Skew	-0.005
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 49.109%; route: 0.700, 50.891%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.034, 19.429%; tC2Q: 0.141, 80.571%
Required Clock Path Delay	cell: 0.675, 49.289%; route: 0.695, 50.711%

Path2

Path Summary:

Slack	0.179
Data Arrival Time	1.592
Data Required Time	1.413
From	count_7_s0
To	mem_data_in_mem_data_in_0_1_s
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	2137	IOB29[A]	clk_ibuf/O
1.375	0.700	tNET	RR	1	R17C56[0][A]	count_7_s0/CLK
1.516	0.141	tC2Q	RF	4	R17C56[0][A]	count_7_s0/Q
1.592	0.076	tNET	FF	1	BSRAM_R10[17]	mem_data_in_mem_data_in_0_1_s/AD[11]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	2137	IOB29[A]	clk_ibuf/O
1.378	0.703	tNET	RR	1	BSRAM_R10[17]	mem_data_in_mem_data_in_0_1_s/CLK
1.413	0.035	tHld		1	BSRAM_R10[17]	mem_data_in_mem_data_in_0_1_s

Path Statistics:

Clock Skew	0.003
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 49.127%; route: 0.700, 50.873%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.076, 35.023%; tC2Q: 0.141, 64.977%
Required Clock Path Delay	cell: 0.675, 49.003%; route: 0.703, 50.997%

Path3

Path Summary:

Slack	0.224
Data Arrival Time	2.676
Data Required Time	2.452
From	gw_gao_inst_0/u_la0_top/address_counter_9_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s
Launch Clk	tck_pad_i:[R]
Latch Clk	tck_pad_i:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/I
0.675	0.675	tINS	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/O
0.675	0.000	tNET	RR	1	R28C89	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351	0.675	tINS	RR	258	R28C89	gw_gao_inst_0/u_gw_jtag/tck_o
2.411	1.060	tNET	RR	1	R14C60[2][B]	gw_gao_inst_0/u_la0_top/address_counter_9_s0/CLK
2.552	0.141	tC2Q	RF	4	R14C60[2][B]	gw_gao_inst_0/u_la0_top/address_counter_9_s0/Q
2.676	0.124	tNET	FF	1	BSRAM_R28[18]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/ADB[13]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/I
0.675	0.675	tINS	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/O
0.675	0.000	tNET	RR	1	R28C89	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351	0.675	tINS	RR	258	R28C89	gw_gao_inst_0/u_gw_jtag/tck_o
2.417	1.066	tNET	RR	1	BSRAM_R28[18]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CLKB
2.452	0.035	tHld		1	BSRAM_R28[18]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s

Path Statistics:

Clock Skew	0.006
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 1.351, 56.035%; route: 1.060, 43.965%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.124, 46.792%; tC2Q: 0.141, 53.208%
Required Clock Path Delay	cell: 1.351, 55.896%; route: 1.066, 44.104%

Path4

Path Summary:

Slack	0.225
Data Arrival Time	1.636
Data Required Time	1.411
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_4_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	2137	IOB29[A]	clk_ibuf/O
1.391	0.716	tNET	RR	1	R24C58[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_4_s0/CLK
1.535	0.144	tC2Q	RR	1	R24C58[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_4_s0/Q
1.636	0.101	tNET	RR	1	BSRAM_R28[17]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/DI[4]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	2137	IOB29[A]	clk_ibuf/O
1.375	0.699	tNET	RR	1	BSRAM_R28[17]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CLKA
1.411	0.037	tHld		1	BSRAM_R28[17]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s

Path Statistics:

Clock Skew	-0.017
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 48.553%; route: 0.716, 51.447%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.101, 41.224%; tC2Q: 0.144, 58.776%
Required Clock Path Delay	cell: 0.675, 49.145%; route: 0.699, 50.855%

Path5

Path Summary:

Slack	0.225
Data Arrival Time	1.636
Data Required Time	1.411
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_0_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	2137	IOB29[A]	clk_ibuf/O
1.391	0.716	tNET	RR	1	R24C58[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_0_s0/CLK
1.535	0.144	tC2Q	RR	1	R24C58[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_0_s0/Q
1.636	0.101	tNET	RR	1	BSRAM_R28[17]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/DI[0]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	2137	IOB29[A]	clk_ibuf/O
1.375	0.699	tNET	RR	1	BSRAM_R28[17]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CLKA
1.411	0.037	tHld		1	BSRAM_R28[17]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s

Path Statistics:

Clock Skew	-0.017
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 48.553%; route: 0.716, 51.447%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.101, 41.224%; tC2Q: 0.144, 58.776%
Required Clock Path Delay	cell: 0.675, 49.145%; route: 0.699, 50.855%

Path6

Path Summary:

Slack	0.249
Data Arrival Time	1.661
Data Required Time	1.411
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_11_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	2137	IOB29[A]	clk_ibuf/O
1.375	0.700	tNET	RR	1	R27C59[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_11_s0/CLK
1.520	0.144	tC2Q	RR	1	R27C59[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_11_s0/Q
1.661	0.141	tNET	RR	1	BSRAM_R28[17]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/DI[11]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	2137	IOB29[A]	clk_ibuf/O
1.375	0.699	tNET	RR	1	BSRAM_R28[17]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CLKA
1.411	0.037	tHld		1	BSRAM_R28[17]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s

Path Statistics:

Clock Skew	-0.001
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 49.109%; route: 0.700, 50.891%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.141, 49.474%; tC2Q: 0.144, 50.526%
Required Clock Path Delay	cell: 0.675, 49.145%; route: 0.699, 50.855%

Path7

Path Summary:

Slack	0.251
Data Arrival Time	1.663
Data Required Time	1.411
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_37_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	2137	IOB29[A]	clk_ibuf/O
1.384	0.708	tNET	RR	1	R27C61[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_37_s0/CLK
1.528	0.144	tC2Q	RR	1	R27C61[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_37_s0/Q
1.663	0.135	tNET	RR	1	BSRAM_R28[19]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/DI[5]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	2137	IOB29[A]	clk_ibuf/O
1.375	0.699	tNET	RR	1	BSRAM_R28[19]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/CLKA
1.411	0.037	tHld		1	BSRAM_R28[19]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s

Path Statistics:

Clock Skew	-0.009
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 48.825%; route: 0.708, 51.175%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.135, 48.387%; tC2Q: 0.144, 51.613%
Required Clock Path Delay	cell: 0.675, 49.145%; route: 0.699, 50.855%

Path8

Path Summary:

Slack	0.257
Data Arrival Time	1.664
Data Required Time	1.408
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_28_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	2137	IOB29[A]	clk_ibuf/O
1.379	0.704	tNET	RR	1	R27C58[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_28_s0/CLK
1.523	0.144	tC2Q	RR	1	R27C58[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_28_s0/Q
1.664	0.141	tNET	RR	1	BSRAM_R28[18]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[12]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	2137	IOB29[A]	clk_ibuf/O
1.371	0.695	tNET	RR	1	BSRAM_R28[18]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CLKA
1.408	0.037	tHld		1	BSRAM_R28[18]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s

Path Statistics:

Clock Skew	-0.009
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 48.967%; route: 0.704, 51.033%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.141, 49.474%; tC2Q: 0.144, 50.526%
Required Clock Path Delay	cell: 0.675, 49.289%; route: 0.695, 50.711%

Path9

Path Summary:

Slack	0.275
Data Arrival Time	1.613
Data Required Time	1.338
From	uut/FP_Exponential_inst/data_z[18]_10_s0
To	uut/FP_Exponential_inst/data_z[19]_10_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	2137	IOB29[A]	clk_ibuf/O
1.391	0.716	tNET	RR	1	R6C40[0][B]	uut/FP_Exponential_inst/data_z[18]_10_s0/CLK
1.535	0.144	tC2Q	RR	1	R6C40[0][B]	uut/FP_Exponential_inst/data_z[18]_10_s0/Q
1.613	0.078	tNET	RR	1	R6C40[2][A]	uut/FP_Exponential_inst/data_z[19]_10_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	2137	IOB29[A]	clk_ibuf/O
1.391	0.716	tNET	RR	1	R6C40[2][A]	uut/FP_Exponential_inst/data_z[19]_10_s0/CLK
1.338	-0.053	tHld		1	R6C40[2][A]	uut/FP_Exponential_inst/data_z[19]_10_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 48.553%; route: 0.716, 51.447%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.078, 35.135%; tC2Q: 0.144, 64.865%
Required Clock Path Delay	cell: 0.675, 48.553%; route: 0.716, 51.447%

Path10

Path Summary:

Slack	0.275
Data Arrival Time	2.711
Data Required Time	2.436
From	gw_gao_inst_0/u_la0_top/address_counter_0_s0
To	gw_gao_inst_0/u_la0_top/address_counter_0_s0
Launch Clk	tck_pad_i:[R]
Latch Clk	tck_pad_i:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/I
0.675	0.675	tINS	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/O
0.675	0.000	tNET	RR	1	R28C89	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351	0.675	tINS	RR	258	R28C89	gw_gao_inst_0/u_gw_jtag/tck_o
2.411	1.060	tNET	RR	1	R14C60[1][A]	gw_gao_inst_0/u_la0_top/address_counter_0_s0/CLK
2.552	0.141	tC2Q	RF	8	R14C60[1][A]	gw_gao_inst_0/u_la0_top/address_counter_0_s0/Q
2.558	0.006	tNET	FF	1	R14C60[1][A]	gw_gao_inst_0/u_la0_top/data_to_addr_counter_0_s0/I0
2.711	0.153	tINS	FF	1	R14C60[1][A]	gw_gao_inst_0/u_la0_top/data_to_addr_counter_0_s0/F
2.711	0.000	tNET	FF	1	R14C60[1][A]	gw_gao_inst_0/u_la0_top/address_counter_0_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/I
0.675	0.675	tINS	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/O
0.675	0.000	tNET	RR	1	R28C89	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351	0.675	tINS	RR	258	R28C89	gw_gao_inst_0/u_gw_jtag/tck_o
2.411	1.060	tNET	RR	1	R14C60[1][A]	gw_gao_inst_0/u_la0_top/address_counter_0_s0/CLK
2.436	0.025	tHld		1	R14C60[1][A]	gw_gao_inst_0/u_la0_top/address_counter_0_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 1.351, 56.035%; route: 1.060, 43.965%
Arrival Data Path Delay	cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay	cell: 1.351, 56.035%; route: 1.060, 43.965%

Path11

Path Summary:

Slack	0.275
Data Arrival Time	1.699
Data Required Time	1.424
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	2137	IOB29[A]	clk_ibuf/O
1.399	0.723	tNET	RR	1	R22C57[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLK
1.540	0.141	tC2Q	RF	7	R22C57[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/Q
1.546	0.006	tNET	FF	1	R22C57[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n404_s1/I1
1.699	0.153	tINS	FF	1	R22C57[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n404_s1/F
1.699	0.000	tNET	FF	1	R22C57[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	2137	IOB29[A]	clk_ibuf/O
1.399	0.723	tNET	RR	1	R22C57[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLK
1.424	0.025	tHld		1	R22C57[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.675, 48.293%; route: 0.723, 51.707%
Arrival Data Path Delay	cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay	cell: 0.675, 48.293%; route: 0.723, 51.707%

Path12

Path Summary:

Slack	0.275
Data Arrival Time	1.695
Data Required Time	1.420
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	2137	IOB29[A]	clk_ibuf/O
1.395	0.719	tNET	RR	1	R22C58[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/CLK
1.536	0.141	tC2Q	RF	6	R22C58[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/Q
1.542	0.006	tNET	FF	1	R22C58[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n401_s1/I1
1.695	0.153	tINS	FF	1	R22C58[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n401_s1/F
1.695	0.000	tNET	FF	1	R22C58[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	2137	IOB29[A]	clk_ibuf/O
1.395	0.719	tNET	RR	1	R22C58[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/CLK
1.420	0.025	tHld		1	R22C58[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.675, 48.432%; route: 0.719, 51.568%
Arrival Data Path Delay	cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay	cell: 0.675, 48.432%; route: 0.719, 51.568%

Path13

Path Summary:

Slack	0.275
Data Arrival Time	1.701
Data Required Time	1.426
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	2137	IOB29[A]	clk_ibuf/O
1.401	0.725	tNET	RR	1	R21C61[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1/CLK
1.542	0.141	tC2Q	RF	6	R21C61[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1/Q
1.548	0.006	tNET	FF	1	R21C61[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n314_s2/I1
1.701	0.153	tINS	FF	1	R21C61[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n314_s2/F
1.701	0.000	tNET	FF	1	R21C61[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	2137	IOB29[A]	clk_ibuf/O
1.401	0.725	tNET	RR	1	R21C61[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1/CLK
1.426	0.025	tHld		1	R21C61[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.675, 48.233%; route: 0.725, 51.767%
Arrival Data Path Delay	cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay	cell: 0.675, 48.233%; route: 0.725, 51.767%

Path14

Path Summary:

Slack	0.275
Data Arrival Time	1.692
Data Required Time	1.417
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	2137	IOB29[A]	clk_ibuf/O
1.392	0.717	tNET	RR	1	R21C59[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/CLK
1.533	0.141	tC2Q	RF	5	R21C59[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/Q
1.539	0.006	tNET	FF	1	R21C59[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n313_s0/I2
1.692	0.153	tINS	FF	1	R21C59[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n313_s0/F
1.692	0.000	tNET	FF	1	R21C59[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	2137	IOB29[A]	clk_ibuf/O
1.392	0.717	tNET	RR	1	R21C59[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/CLK
1.417	0.025	tHld		1	R21C59[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.675, 48.510%; route: 0.717, 51.490%
Arrival Data Path Delay	cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay	cell: 0.675, 48.510%; route: 0.717, 51.490%

Path15

Path Summary:

Slack	0.275
Data Arrival Time	1.692
Data Required Time	1.417
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	2137	IOB29[A]	clk_ibuf/O
1.392	0.717	tNET	RR	1	R21C59[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1/CLK
1.533	0.141	tC2Q	RF	4	R21C59[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1/Q
1.539	0.006	tNET	FF	1	R21C59[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n312_s0/I1
1.692	0.153	tINS	FF	1	R21C59[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n312_s0/F
1.692	0.000	tNET	FF	1	R21C59[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	2137	IOB29[A]	clk_ibuf/O
1.392	0.717	tNET	RR	1	R21C59[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1/CLK
1.417	0.025	tHld		1	R21C59[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.675, 48.510%; route: 0.717, 51.490%
Arrival Data Path Delay	cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay	cell: 0.675, 48.510%; route: 0.717, 51.490%

Path16

Path Summary:

Slack	0.275
Data Arrival Time	2.703
Data Required Time	2.428
From	gw_gao_inst_0/u_la0_top/word_count_9_s0
To	gw_gao_inst_0/u_la0_top/word_count_9_s0
Launch Clk	tck_pad_i:[R]
Latch Clk	tck_pad_i:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/I
0.675	0.675	tINS	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/O
0.675	0.000	tNET	RR	1	R28C89	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351	0.675	tINS	RR	258	R28C89	gw_gao_inst_0/u_gw_jtag/tck_o
2.403	1.052	tNET	RR	1	R13C59[0][A]	gw_gao_inst_0/u_la0_top/word_count_9_s0/CLK
2.544	0.141	tC2Q	RF	5	R13C59[0][A]	gw_gao_inst_0/u_la0_top/word_count_9_s0/Q
2.550	0.006	tNET	FF	1	R13C59[0][A]	gw_gao_inst_0/u_la0_top/data_to_word_counter_9_s0/I1
2.703	0.153	tINS	FF	1	R13C59[0][A]	gw_gao_inst_0/u_la0_top/data_to_word_counter_9_s0/F
2.703	0.000	tNET	FF	1	R13C59[0][A]	gw_gao_inst_0/u_la0_top/word_count_9_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/I
0.675	0.675	tINS	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/O
0.675	0.000	tNET	RR	1	R28C89	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351	0.675	tINS	RR	258	R28C89	gw_gao_inst_0/u_gw_jtag/tck_o
2.403	1.052	tNET	RR	1	R13C59[0][A]	gw_gao_inst_0/u_la0_top/word_count_9_s0/CLK
2.428	0.025	tHld		1	R13C59[0][A]	gw_gao_inst_0/u_la0_top/word_count_9_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 1.351, 56.221%; route: 1.052, 43.779%
Arrival Data Path Delay	cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay	cell: 1.351, 56.221%; route: 1.052, 43.779%

Path17

Path Summary:

Slack	0.275
Data Arrival Time	2.703
Data Required Time	2.428
From	gw_gao_inst_0/u_la0_top/word_count_12_s0
To	gw_gao_inst_0/u_la0_top/word_count_12_s0
Launch Clk	tck_pad_i:[R]
Latch Clk	tck_pad_i:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/I
0.675	0.675	tINS	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/O
0.675	0.000	tNET	RR	1	R28C89	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351	0.675	tINS	RR	258	R28C89	gw_gao_inst_0/u_gw_jtag/tck_o
2.403	1.052	tNET	RR	1	R13C59[1][A]	gw_gao_inst_0/u_la0_top/word_count_12_s0/CLK
2.544	0.141	tC2Q	RF	2	R13C59[1][A]	gw_gao_inst_0/u_la0_top/word_count_12_s0/Q
2.550	0.006	tNET	FF	1	R13C59[1][A]	gw_gao_inst_0/u_la0_top/data_to_word_counter_12_s0/I1
2.703	0.153	tINS	FF	1	R13C59[1][A]	gw_gao_inst_0/u_la0_top/data_to_word_counter_12_s0/F
2.703	0.000	tNET	FF	1	R13C59[1][A]	gw_gao_inst_0/u_la0_top/word_count_12_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/I
0.675	0.675	tINS	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/O
0.675	0.000	tNET	RR	1	R28C89	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351	0.675	tINS	RR	258	R28C89	gw_gao_inst_0/u_gw_jtag/tck_o
2.403	1.052	tNET	RR	1	R13C59[1][A]	gw_gao_inst_0/u_la0_top/word_count_12_s0/CLK
2.428	0.025	tHld		1	R13C59[1][A]	gw_gao_inst_0/u_la0_top/word_count_12_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 1.351, 56.221%; route: 1.052, 43.779%
Arrival Data Path Delay	cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay	cell: 1.351, 56.221%; route: 1.052, 43.779%

Path18

Path Summary:

Slack	0.278
Data Arrival Time	2.731
Data Required Time	2.453
From	gw_gao_inst_0/u_la0_top/bit_count_4_s1
To	gw_gao_inst_0/u_la0_top/bit_count_4_s1
Launch Clk	tck_pad_i:[R]
Latch Clk	tck_pad_i:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/I
0.675	0.675	tINS	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/O
0.675	0.000	tNET	RR	1	R28C89	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351	0.675	tINS	RR	258	R28C89	gw_gao_inst_0/u_gw_jtag/tck_o
2.428	1.077	tNET	RR	1	R7C59[0][A]	gw_gao_inst_0/u_la0_top/bit_count_4_s1/CLK
2.569	0.141	tC2Q	RF	6	R7C59[0][A]	gw_gao_inst_0/u_la0_top/bit_count_4_s1/Q
2.578	0.009	tNET	FF	1	R7C59[0][A]	gw_gao_inst_0/u_la0_top/n585_s2/I0
2.731	0.153	tINS	FF	1	R7C59[0][A]	gw_gao_inst_0/u_la0_top/n585_s2/F
2.731	0.000	tNET	FF	1	R7C59[0][A]	gw_gao_inst_0/u_la0_top/bit_count_4_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/I
0.675	0.675	tINS	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/O
0.675	0.000	tNET	RR	1	R28C89	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351	0.675	tINS	RR	258	R28C89	gw_gao_inst_0/u_gw_jtag/tck_o
2.428	1.077	tNET	RR	1	R7C59[0][A]	gw_gao_inst_0/u_la0_top/bit_count_4_s1/CLK
2.453	0.025	tHld		1	R7C59[0][A]	gw_gao_inst_0/u_la0_top/bit_count_4_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 1.351, 55.643%; route: 1.077, 44.357%
Arrival Data Path Delay	cell: 0.153, 50.495%; route: 0.009, 2.970%; tC2Q: 0.141, 46.535%
Required Clock Path Delay	cell: 1.351, 55.643%; route: 1.077, 44.357%

Path19

Path Summary:

Slack	0.278
Data Arrival Time	2.735
Data Required Time	2.457
From	gw_gao_inst_0/u_la0_top/word_count_0_s0
To	gw_gao_inst_0/u_la0_top/word_count_0_s0
Launch Clk	tck_pad_i:[R]
Latch Clk	tck_pad_i:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/I
0.675	0.675	tINS	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/O
0.675	0.000	tNET	RR	1	R28C89	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351	0.675	tINS	RR	258	R28C89	gw_gao_inst_0/u_gw_jtag/tck_o
2.432	1.081	tNET	RR	1	R7C60[0][A]	gw_gao_inst_0/u_la0_top/word_count_0_s0/CLK
2.573	0.141	tC2Q	RF	5	R7C60[0][A]	gw_gao_inst_0/u_la0_top/word_count_0_s0/Q
2.582	0.009	tNET	FF	1	R7C60[0][A]	gw_gao_inst_0/u_la0_top/data_to_word_counter_0_s1/I1
2.735	0.153	tINS	FF	1	R7C60[0][A]	gw_gao_inst_0/u_la0_top/data_to_word_counter_0_s1/F
2.735	0.000	tNET	FF	1	R7C60[0][A]	gw_gao_inst_0/u_la0_top/word_count_0_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/I
0.675	0.675	tINS	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/O
0.675	0.000	tNET	RR	1	R28C89	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351	0.675	tINS	RR	258	R28C89	gw_gao_inst_0/u_gw_jtag/tck_o
2.432	1.081	tNET	RR	1	R7C60[0][A]	gw_gao_inst_0/u_la0_top/word_count_0_s0/CLK
2.457	0.025	tHld		1	R7C60[0][A]	gw_gao_inst_0/u_la0_top/word_count_0_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 1.351, 55.551%; route: 1.081, 44.449%
Arrival Data Path Delay	cell: 0.153, 50.495%; route: 0.009, 2.970%; tC2Q: 0.141, 46.535%
Required Clock Path Delay	cell: 1.351, 55.551%; route: 1.081, 44.449%

Path20

Path Summary:

Slack	0.278
Data Arrival Time	2.706
Data Required Time	2.428
From	gw_gao_inst_0/u_la0_top/address_counter_2_s0
To	gw_gao_inst_0/u_la0_top/address_counter_2_s0
Launch Clk	tck_pad_i:[R]
Latch Clk	tck_pad_i:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/I
0.675	0.675	tINS	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/O
0.675	0.000	tNET	RR	1	R28C89	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351	0.675	tINS	RR	258	R28C89	gw_gao_inst_0/u_gw_jtag/tck_o
2.403	1.052	tNET	RR	1	R14C58[1][A]	gw_gao_inst_0/u_la0_top/address_counter_2_s0/CLK
2.544	0.141	tC2Q	RF	6	R14C58[1][A]	gw_gao_inst_0/u_la0_top/address_counter_2_s0/Q
2.553	0.009	tNET	FF	1	R14C58[1][A]	gw_gao_inst_0/u_la0_top/data_to_addr_counter_2_s0/I1
2.706	0.153	tINS	FF	1	R14C58[1][A]	gw_gao_inst_0/u_la0_top/data_to_addr_counter_2_s0/F
2.706	0.000	tNET	FF	1	R14C58[1][A]	gw_gao_inst_0/u_la0_top/address_counter_2_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/I
0.675	0.675	tINS	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/O
0.675	0.000	tNET	RR	1	R28C89	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351	0.675	tINS	RR	258	R28C89	gw_gao_inst_0/u_gw_jtag/tck_o
2.403	1.052	tNET	RR	1	R14C58[1][A]	gw_gao_inst_0/u_la0_top/address_counter_2_s0/CLK
2.428	0.025	tHld		1	R14C58[1][A]	gw_gao_inst_0/u_la0_top/address_counter_2_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 1.351, 56.221%; route: 1.052, 43.779%
Arrival Data Path Delay	cell: 0.153, 50.495%; route: 0.009, 2.970%; tC2Q: 0.141, 46.535%
Required Clock Path Delay	cell: 1.351, 56.221%; route: 1.052, 43.779%

Path21

Path Summary:

Slack	0.278
Data Arrival Time	2.710
Data Required Time	2.432
From	gw_gao_inst_0/u_la0_top/address_counter_8_s0
To	gw_gao_inst_0/u_la0_top/address_counter_8_s0
Launch Clk	tck_pad_i:[R]
Latch Clk	tck_pad_i:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/I
0.675	0.675	tINS	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/O
0.675	0.000	tNET	RR	1	R28C89	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351	0.675	tINS	RR	258	R28C89	gw_gao_inst_0/u_gw_jtag/tck_o
2.407	1.056	tNET	RR	1	R14C59[0][A]	gw_gao_inst_0/u_la0_top/address_counter_8_s0/CLK
2.548	0.141	tC2Q	RF	5	R14C59[0][A]	gw_gao_inst_0/u_la0_top/address_counter_8_s0/Q
2.557	0.009	tNET	FF	1	R14C59[0][A]	gw_gao_inst_0/u_la0_top/data_to_addr_counter_8_s0/I1
2.710	0.153	tINS	FF	1	R14C59[0][A]	gw_gao_inst_0/u_la0_top/data_to_addr_counter_8_s0/F
2.710	0.000	tNET	FF	1	R14C59[0][A]	gw_gao_inst_0/u_la0_top/address_counter_8_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/I
0.675	0.675	tINS	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/O
0.675	0.000	tNET	RR	1	R28C89	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351	0.675	tINS	RR	258	R28C89	gw_gao_inst_0/u_gw_jtag/tck_o
2.407	1.056	tNET	RR	1	R14C59[0][A]	gw_gao_inst_0/u_la0_top/address_counter_8_s0/CLK
2.432	0.025	tHld		1	R14C59[0][A]	gw_gao_inst_0/u_la0_top/address_counter_8_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 1.351, 56.128%; route: 1.056, 43.872%
Arrival Data Path Delay	cell: 0.153, 50.495%; route: 0.009, 2.970%; tC2Q: 0.141, 46.535%
Required Clock Path Delay	cell: 1.351, 56.128%; route: 1.056, 43.872%

Path22

Path Summary:

Slack	0.278
Data Arrival Time	1.705
Data Required Time	1.427
From	gw_gao_inst_0/u_la0_top/capture_window_sel_4_s1
To	gw_gao_inst_0/u_la0_top/capture_window_sel_4_s1
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	2137	IOB29[A]	clk_ibuf/O
1.402	0.727	tNET	RR	1	R20C57[0][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_4_s1/CLK
1.543	0.141	tC2Q	RF	7	R20C57[0][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_4_s1/Q
1.552	0.009	tNET	FF	1	R20C57[0][A]	gw_gao_inst_0/u_la0_top/n2056_s1/I2
1.705	0.153	tINS	FF	1	R20C57[0][A]	gw_gao_inst_0/u_la0_top/n2056_s1/F
1.705	0.000	tNET	FF	1	R20C57[0][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_4_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	2137	IOB29[A]	clk_ibuf/O
1.402	0.727	tNET	RR	1	R20C57[0][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_4_s1/CLK
1.427	0.025	tHld		1	R20C57[0][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_4_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.675, 48.173%; route: 0.727, 51.827%
Arrival Data Path Delay	cell: 0.153, 50.495%; route: 0.009, 2.970%; tC2Q: 0.141, 46.535%
Required Clock Path Delay	cell: 0.675, 48.173%; route: 0.727, 51.827%

Path23

Path Summary:

Slack	0.278
Data Arrival Time	1.701
Data Required Time	1.423
From	gw_gao_inst_0/u_la0_top/capture_window_sel_5_s1
To	gw_gao_inst_0/u_la0_top/capture_window_sel_5_s1
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	2137	IOB29[A]	clk_ibuf/O
1.398	0.723	tNET	RR	1	R20C58[0][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_5_s1/CLK
1.539	0.141	tC2Q	RF	8	R20C58[0][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_5_s1/Q
1.548	0.009	tNET	FF	1	R20C58[0][A]	gw_gao_inst_0/u_la0_top/n2055_s1/I0
1.701	0.153	tINS	FF	1	R20C58[0][A]	gw_gao_inst_0/u_la0_top/n2055_s1/F
1.701	0.000	tNET	FF	1	R20C58[0][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_5_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	2137	IOB29[A]	clk_ibuf/O
1.398	0.723	tNET	RR	1	R20C58[0][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_5_s1/CLK
1.423	0.025	tHld		1	R20C58[0][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_5_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.675, 48.310%; route: 0.723, 51.690%
Arrival Data Path Delay	cell: 0.153, 50.495%; route: 0.009, 2.970%; tC2Q: 0.141, 46.535%
Required Clock Path Delay	cell: 0.675, 48.310%; route: 0.723, 51.690%

Path24

Path Summary:

Slack	0.278
Data Arrival Time	1.701
Data Required Time	1.423
From	gw_gao_inst_0/u_la0_top/capture_window_sel_6_s1
To	gw_gao_inst_0/u_la0_top/capture_window_sel_6_s1
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	2137	IOB29[A]	clk_ibuf/O
1.398	0.723	tNET	RR	1	R20C58[1][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_6_s1/CLK
1.539	0.141	tC2Q	RF	6	R20C58[1][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_6_s1/Q
1.548	0.009	tNET	FF	1	R20C58[1][A]	gw_gao_inst_0/u_la0_top/n2054_s3/I0
1.701	0.153	tINS	FF	1	R20C58[1][A]	gw_gao_inst_0/u_la0_top/n2054_s3/F
1.701	0.000	tNET	FF	1	R20C58[1][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_6_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	2137	IOB29[A]	clk_ibuf/O
1.398	0.723	tNET	RR	1	R20C58[1][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_6_s1/CLK
1.423	0.025	tHld		1	R20C58[1][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_6_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.675, 48.310%; route: 0.723, 51.690%
Arrival Data Path Delay	cell: 0.153, 50.495%; route: 0.009, 2.970%; tC2Q: 0.141, 46.535%
Required Clock Path Delay	cell: 0.675, 48.310%; route: 0.723, 51.690%

Path25

Path Summary:

Slack	0.281
Data Arrival Time	1.708
Data Required Time	1.427
From	gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1
To	gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	2137	IOB29[A]	clk_ibuf/O
1.402	0.727	tNET	RR	1	R20C57[1][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1/CLK
1.543	0.141	tC2Q	RF	10	R20C57[1][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1/Q
1.555	0.012	tNET	FF	1	R20C57[1][A]	gw_gao_inst_0/u_la0_top/n2058_s3/I0
1.708	0.153	tINS	FF	1	R20C57[1][A]	gw_gao_inst_0/u_la0_top/n2058_s3/F
1.708	0.000	tNET	FF	1	R20C57[1][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	2137	IOB29[A]	clk_ibuf/O
1.402	0.727	tNET	RR	1	R20C57[1][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1/CLK
1.427	0.025	tHld		1	R20C57[1][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.675, 48.173%; route: 0.727, 51.827%
Arrival Data Path Delay	cell: 0.153, 50.000%; route: 0.012, 3.922%; tC2Q: 0.141, 46.078%
Required Clock Path Delay	cell: 0.675, 48.173%; route: 0.727, 51.827%

Recovery Analysis Report

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	38.411
Data Arrival Time	13.892
Data Required Time	52.303
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.688	0.688	tINS	FF	2137	IOB29[A]	clk_ibuf/O
12.644	1.957	tNET	FF	1	R20C59[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
13.087	0.442	tC2Q	FF	54	R20C59[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
13.892	0.805	tNET	FF	1	R23C57[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
50.000	50.000					active clock edge time
50.000	0.000					clk
50.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
50.682	0.683	tINS	RR	2137	IOB29[A]	clk_ibuf/O
52.650	1.967	tNET	RR	1	R23C57[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1/CLK
52.303	-0.347	tSu		1	R23C57[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1

Path Statistics:

Clock Skew	0.006
Setup Relationship	40.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 26.002%; route: 1.957, 73.998%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.805, 64.529%; tC2Q: 0.442, 35.471%
Required Clock Path Delay	cell: 0.683, 25.755%; route: 1.967, 74.245%

Path2

Path Summary:

Slack	38.411
Data Arrival Time	13.892
Data Required Time	52.303
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.688	0.688	tINS	FF	2137	IOB29[A]	clk_ibuf/O
12.644	1.957	tNET	FF	1	R20C59[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
13.087	0.442	tC2Q	FF	54	R20C59[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
13.892	0.805	tNET	FF	1	R23C57[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
50.000	50.000					active clock edge time
50.000	0.000					clk
50.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
50.682	0.683	tINS	RR	2137	IOB29[A]	clk_ibuf/O
52.650	1.967	tNET	RR	1	R23C57[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/CLK
52.303	-0.347	tSu		1	R23C57[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1

Path Statistics:

Clock Skew	0.006
Setup Relationship	40.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 26.002%; route: 1.957, 73.998%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.805, 64.529%; tC2Q: 0.442, 35.471%
Required Clock Path Delay	cell: 0.683, 25.755%; route: 1.967, 74.245%

Path3

Path Summary:

Slack	38.413
Data Arrival Time	13.892
Data Required Time	52.305
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.688	0.688	tINS	FF	2137	IOB29[A]	clk_ibuf/O
12.644	1.957	tNET	FF	1	R20C59[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
13.087	0.442	tC2Q	FF	54	R20C59[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
13.892	0.805	tNET	FF	1	R22C57[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
50.000	50.000					active clock edge time
50.000	0.000					clk
50.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
50.682	0.683	tINS	RR	2137	IOB29[A]	clk_ibuf/O
52.653	1.970	tNET	RR	1	R22C57[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLK
52.305	-0.347	tSu		1	R22C57[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1

Path Statistics:

Clock Skew	0.008
Setup Relationship	40.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 26.002%; route: 1.957, 73.998%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.805, 64.529%; tC2Q: 0.442, 35.471%
Required Clock Path Delay	cell: 0.683, 25.730%; route: 1.970, 74.270%

Path4

Path Summary:

Slack	38.413
Data Arrival Time	13.892
Data Required Time	52.305
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.688	0.688	tINS	FF	2137	IOB29[A]	clk_ibuf/O
12.644	1.957	tNET	FF	1	R20C59[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
13.087	0.442	tC2Q	FF	54	R20C59[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
13.892	0.805	tNET	FF	1	R22C57[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
50.000	50.000					active clock edge time
50.000	0.000					clk
50.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
50.682	0.683	tINS	RR	2137	IOB29[A]	clk_ibuf/O
52.653	1.970	tNET	RR	1	R22C57[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLK
52.305	-0.347	tSu		1	R22C57[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1

Path Statistics:

Clock Skew	0.008
Setup Relationship	40.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 26.002%; route: 1.957, 73.998%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.805, 64.529%; tC2Q: 0.442, 35.471%
Required Clock Path Delay	cell: 0.683, 25.730%; route: 1.970, 74.270%

Path5

Path Summary:

Slack	38.413
Data Arrival Time	13.892
Data Required Time	52.305
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.688	0.688	tINS	FF	2137	IOB29[A]	clk_ibuf/O
12.644	1.957	tNET	FF	1	R20C59[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
13.087	0.442	tC2Q	FF	54	R20C59[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
13.892	0.805	tNET	FF	1	R22C57[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
50.000	50.000					active clock edge time
50.000	0.000					clk
50.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
50.682	0.683	tINS	RR	2137	IOB29[A]	clk_ibuf/O
52.653	1.970	tNET	RR	1	R22C57[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLK
52.305	-0.347	tSu		1	R22C57[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1

Path Statistics:

Clock Skew	0.008
Setup Relationship	40.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 26.002%; route: 1.957, 73.998%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.805, 64.529%; tC2Q: 0.442, 35.471%
Required Clock Path Delay	cell: 0.683, 25.730%; route: 1.970, 74.270%

Path6

Path Summary:

Slack	38.413
Data Arrival Time	13.892
Data Required Time	52.305
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.688	0.688	tINS	FF	2137	IOB29[A]	clk_ibuf/O
12.644	1.957	tNET	FF	1	R20C59[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
13.087	0.442	tC2Q	FF	54	R20C59[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
13.892	0.805	tNET	FF	1	R22C57[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
50.000	50.000					active clock edge time
50.000	0.000					clk
50.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
50.682	0.683	tINS	RR	2137	IOB29[A]	clk_ibuf/O
52.653	1.970	tNET	RR	1	R22C57[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLK
52.305	-0.347	tSu		1	R22C57[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1

Path Statistics:

Clock Skew	0.008
Setup Relationship	40.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 26.002%; route: 1.957, 73.998%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.805, 64.529%; tC2Q: 0.442, 35.471%
Required Clock Path Delay	cell: 0.683, 25.730%; route: 1.970, 74.270%

Path7

Path Summary:

Slack	38.413
Data Arrival Time	13.892
Data Required Time	52.305
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.688	0.688	tINS	FF	2137	IOB29[A]	clk_ibuf/O
12.644	1.957	tNET	FF	1	R20C59[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
13.087	0.442	tC2Q	FF	54	R20C59[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
13.892	0.805	tNET	FF	1	R22C57[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
50.000	50.000					active clock edge time
50.000	0.000					clk
50.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
50.682	0.683	tINS	RR	2137	IOB29[A]	clk_ibuf/O
52.653	1.970	tNET	RR	1	R22C57[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/CLK
52.305	-0.347	tSu		1	R22C57[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1

Path Statistics:

Clock Skew	0.008
Setup Relationship	40.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 26.002%; route: 1.957, 73.998%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.805, 64.529%; tC2Q: 0.442, 35.471%
Required Clock Path Delay	cell: 0.683, 25.730%; route: 1.970, 74.270%

Path8

Path Summary:

Slack	38.434
Data Arrival Time	13.859
Data Required Time	52.293
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.688	0.688	tINS	FF	2137	IOB29[A]	clk_ibuf/O
12.644	1.957	tNET	FF	1	R20C59[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
13.087	0.442	tC2Q	FF	54	R20C59[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
13.859	0.772	tNET	FF	1	R23C58[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
50.000	50.000					active clock edge time
50.000	0.000					clk
50.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
50.682	0.683	tINS	RR	2137	IOB29[A]	clk_ibuf/O
52.641	1.958	tNET	RR	1	R23C58[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/CLK
52.293	-0.347	tSu		1	R23C58[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1

Path Statistics:

Clock Skew	-0.003
Setup Relationship	40.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 26.002%; route: 1.957, 73.998%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.772, 63.580%; tC2Q: 0.442, 36.420%
Required Clock Path Delay	cell: 0.683, 25.846%; route: 1.958, 74.154%

Path9

Path Summary:

Slack	38.434
Data Arrival Time	13.859
Data Required Time	52.293
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/start_reg_s0
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.688	0.688	tINS	FF	2137	IOB29[A]	clk_ibuf/O
12.644	1.957	tNET	FF	1	R20C59[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
13.087	0.442	tC2Q	FF	54	R20C59[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
13.859	0.772	tNET	FF	1	R23C58[0][A]	gw_gao_inst_0/u_la0_top/start_reg_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
50.000	50.000					active clock edge time
50.000	0.000					clk
50.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
50.682	0.683	tINS	RR	2137	IOB29[A]	clk_ibuf/O
52.641	1.958	tNET	RR	1	R23C58[0][A]	gw_gao_inst_0/u_la0_top/start_reg_s0/CLK
52.293	-0.347	tSu		1	R23C58[0][A]	gw_gao_inst_0/u_la0_top/start_reg_s0

Path Statistics:

Clock Skew	-0.003
Setup Relationship	40.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 26.002%; route: 1.957, 73.998%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.772, 63.580%; tC2Q: 0.442, 36.420%
Required Clock Path Delay	cell: 0.683, 25.846%; route: 1.958, 74.154%

Path10

Path Summary:

Slack	38.457
Data Arrival Time	13.850
Data Required Time	52.307
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.688	0.688	tINS	FF	2137	IOB29[A]	clk_ibuf/O
12.644	1.957	tNET	FF	1	R20C59[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
13.087	0.442	tC2Q	FF	54	R20C59[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
13.850	0.764	tNET	FF	1	R21C57[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
50.000	50.000					active clock edge time
50.000	0.000					clk
50.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
50.682	0.683	tINS	RR	2137	IOB29[A]	clk_ibuf/O
52.655	1.972	tNET	RR	1	R21C57[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1/CLK
52.307	-0.347	tSu		1	R21C57[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1

Path Statistics:

Clock Skew	0.011
Setup Relationship	40.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 26.002%; route: 1.957, 73.998%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.764, 63.316%; tC2Q: 0.442, 36.684%
Required Clock Path Delay	cell: 0.683, 25.706%; route: 1.972, 74.294%

Path11

Path Summary:

Slack	38.457
Data Arrival Time	13.850
Data Required Time	52.307
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.688	0.688	tINS	FF	2137	IOB29[A]	clk_ibuf/O
12.644	1.957	tNET	FF	1	R20C59[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
13.087	0.442	tC2Q	FF	54	R20C59[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
13.850	0.764	tNET	FF	1	R21C57[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
50.000	50.000					active clock edge time
50.000	0.000					clk
50.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
50.682	0.683	tINS	RR	2137	IOB29[A]	clk_ibuf/O
52.655	1.972	tNET	RR	1	R21C57[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1/CLK
52.307	-0.347	tSu		1	R21C57[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1

Path Statistics:

Clock Skew	0.011
Setup Relationship	40.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 26.002%; route: 1.957, 73.998%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.764, 63.316%; tC2Q: 0.442, 36.684%
Required Clock Path Delay	cell: 0.683, 25.706%; route: 1.972, 74.294%

Path12

Path Summary:

Slack	38.457
Data Arrival Time	13.850
Data Required Time	52.307
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.688	0.688	tINS	FF	2137	IOB29[A]	clk_ibuf/O
12.644	1.957	tNET	FF	1	R20C59[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
13.087	0.442	tC2Q	FF	54	R20C59[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
13.850	0.764	tNET	FF	1	R21C57[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
50.000	50.000					active clock edge time
50.000	0.000					clk
50.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
50.682	0.683	tINS	RR	2137	IOB29[A]	clk_ibuf/O
52.655	1.972	tNET	RR	1	R21C57[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1/CLK
52.307	-0.347	tSu		1	R21C57[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1

Path Statistics:

Clock Skew	0.011
Setup Relationship	40.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 26.002%; route: 1.957, 73.998%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.764, 63.316%; tC2Q: 0.442, 36.684%
Required Clock Path Delay	cell: 0.683, 25.706%; route: 1.972, 74.294%

Path13

Path Summary:

Slack	38.457
Data Arrival Time	13.812
Data Required Time	52.269
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/capture_window_sel_8_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.688	0.688	tINS	FF	2137	IOB29[A]	clk_ibuf/O
12.644	1.957	tNET	FF	1	R20C59[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
13.087	0.442	tC2Q	FF	54	R20C59[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
13.812	0.725	tNET	FF	1	R29C57[3][B]	gw_gao_inst_0/u_la0_top/capture_window_sel_8_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
50.000	50.000					active clock edge time
50.000	0.000					clk
50.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
50.682	0.683	tINS	RR	2137	IOB29[A]	clk_ibuf/O
52.616	1.934	tNET	RR	1	R29C57[3][B]	gw_gao_inst_0/u_la0_top/capture_window_sel_8_s1/CLK
52.269	-0.347	tSu		1	R29C57[3][B]	gw_gao_inst_0/u_la0_top/capture_window_sel_8_s1

Path Statistics:

Clock Skew	-0.028
Setup Relationship	40.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 26.002%; route: 1.957, 73.998%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.725, 62.098%; tC2Q: 0.442, 37.901%
Required Clock Path Delay	cell: 0.683, 26.087%; route: 1.934, 73.913%

Path14

Path Summary:

Slack	38.457
Data Arrival Time	13.812
Data Required Time	52.269
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/capture_window_sel_9_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.688	0.688	tINS	FF	2137	IOB29[A]	clk_ibuf/O
12.644	1.957	tNET	FF	1	R20C59[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
13.087	0.442	tC2Q	FF	54	R20C59[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
13.812	0.725	tNET	FF	1	R29C57[3][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_9_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
50.000	50.000					active clock edge time
50.000	0.000					clk
50.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
50.682	0.683	tINS	RR	2137	IOB29[A]	clk_ibuf/O
52.616	1.934	tNET	RR	1	R29C57[3][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_9_s1/CLK
52.269	-0.347	tSu		1	R29C57[3][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_9_s1

Path Statistics:

Clock Skew	-0.028
Setup Relationship	40.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 26.002%; route: 1.957, 73.998%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.725, 62.098%; tC2Q: 0.442, 37.901%
Required Clock Path Delay	cell: 0.683, 26.087%; route: 1.934, 73.913%

Path15

Path Summary:

Slack	38.614
Data Arrival Time	13.684
Data Required Time	52.298
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.688	0.688	tINS	FF	2137	IOB29[A]	clk_ibuf/O
12.644	1.957	tNET	FF	1	R20C59[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
13.087	0.442	tC2Q	FF	54	R20C59[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
13.684	0.597	tNET	FF	1	R21C60[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
50.000	50.000					active clock edge time
50.000	0.000					clk
50.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
50.682	0.683	tINS	RR	2137	IOB29[A]	clk_ibuf/O
52.646	1.963	tNET	RR	1	R21C60[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLK
52.298	-0.347	tSu		1	R21C60[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1

Path Statistics:

Clock Skew	0.002
Setup Relationship	40.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 26.002%; route: 1.957, 73.998%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.597, 57.452%; tC2Q: 0.442, 42.548%
Required Clock Path Delay	cell: 0.683, 25.797%; route: 1.963, 74.203%

Path16

Path Summary:

Slack	38.614
Data Arrival Time	13.684
Data Required Time	52.298
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/capture_end_dly_s0
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.688	0.688	tINS	FF	2137	IOB29[A]	clk_ibuf/O
12.644	1.957	tNET	FF	1	R20C59[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
13.087	0.442	tC2Q	FF	54	R20C59[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
13.684	0.597	tNET	FF	1	R21C60[1][A]	gw_gao_inst_0/u_la0_top/capture_end_dly_s0/PRESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
50.000	50.000					active clock edge time
50.000	0.000					clk
50.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
50.682	0.683	tINS	RR	2137	IOB29[A]	clk_ibuf/O
52.646	1.963	tNET	RR	1	R21C60[1][A]	gw_gao_inst_0/u_la0_top/capture_end_dly_s0/CLK
52.298	-0.347	tSu		1	R21C60[1][A]	gw_gao_inst_0/u_la0_top/capture_end_dly_s0

Path Statistics:

Clock Skew	0.002
Setup Relationship	40.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 26.002%; route: 1.957, 73.998%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.597, 57.452%; tC2Q: 0.442, 42.548%
Required Clock Path Delay	cell: 0.683, 25.797%; route: 1.963, 74.203%

Path17

Path Summary:

Slack	38.623
Data Arrival Time	13.684
Data Required Time	52.307
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.688	0.688	tINS	FF	2137	IOB29[A]	clk_ibuf/O
12.644	1.957	tNET	FF	1	R20C59[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
13.087	0.442	tC2Q	FF	54	R20C59[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
13.684	0.597	tNET	FF	1	R21C61[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
50.000	50.000					active clock edge time
50.000	0.000					clk
50.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
50.682	0.683	tINS	RR	2137	IOB29[A]	clk_ibuf/O
52.655	1.972	tNET	RR	1	R21C61[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1/CLK
52.307	-0.347	tSu		1	R21C61[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1

Path Statistics:

Clock Skew	0.011
Setup Relationship	40.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 26.002%; route: 1.957, 73.998%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.597, 57.452%; tC2Q: 0.442, 42.548%
Required Clock Path Delay	cell: 0.683, 25.706%; route: 1.972, 74.294%

Path18

Path Summary:

Slack	38.623
Data Arrival Time	13.684
Data Required Time	52.307
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.688	0.688	tINS	FF	2137	IOB29[A]	clk_ibuf/O
12.644	1.957	tNET	FF	1	R20C59[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
13.087	0.442	tC2Q	FF	54	R20C59[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
13.684	0.597	tNET	FF	1	R21C61[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
50.000	50.000					active clock edge time
50.000	0.000					clk
50.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
50.682	0.683	tINS	RR	2137	IOB29[A]	clk_ibuf/O
52.655	1.972	tNET	RR	1	R21C61[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/CLK
52.307	-0.347	tSu		1	R21C61[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1

Path Statistics:

Clock Skew	0.011
Setup Relationship	40.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 26.002%; route: 1.957, 73.998%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.597, 57.452%; tC2Q: 0.442, 42.548%
Required Clock Path Delay	cell: 0.683, 25.706%; route: 1.972, 74.294%

Path19

Path Summary:

Slack	38.815
Data Arrival Time	13.474
Data Required Time	52.289
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.688	0.688	tINS	FF	2137	IOB29[A]	clk_ibuf/O
12.644	1.957	tNET	FF	1	R20C59[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
13.087	0.442	tC2Q	FF	54	R20C59[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
13.474	0.388	tNET	FF	1	R21C59[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1/PRESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
50.000	50.000					active clock edge time
50.000	0.000					clk
50.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
50.682	0.683	tINS	RR	2137	IOB29[A]	clk_ibuf/O
52.636	1.954	tNET	RR	1	R21C59[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1/CLK
52.289	-0.347	tSu		1	R21C59[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1

Path Statistics:

Clock Skew	-0.008
Setup Relationship	40.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 26.002%; route: 1.957, 73.998%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.388, 46.687%; tC2Q: 0.442, 53.313%
Required Clock Path Delay	cell: 0.683, 25.889%; route: 1.954, 74.111%

Path20

Path Summary:

Slack	38.815
Data Arrival Time	13.474
Data Required Time	52.289
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.688	0.688	tINS	FF	2137	IOB29[A]	clk_ibuf/O
12.644	1.957	tNET	FF	1	R20C59[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
13.087	0.442	tC2Q	FF	54	R20C59[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
13.474	0.388	tNET	FF	1	R21C59[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
50.000	50.000					active clock edge time
50.000	0.000					clk
50.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
50.682	0.683	tINS	RR	2137	IOB29[A]	clk_ibuf/O
52.636	1.954	tNET	RR	1	R21C59[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/CLK
52.289	-0.347	tSu		1	R21C59[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1

Path Statistics:

Clock Skew	-0.008
Setup Relationship	40.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 26.002%; route: 1.957, 73.998%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.388, 46.687%; tC2Q: 0.442, 53.313%
Required Clock Path Delay	cell: 0.683, 25.889%; route: 1.954, 74.111%

Path21

Path Summary:

Slack	38.815
Data Arrival Time	13.474
Data Required Time	52.289
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.688	0.688	tINS	FF	2137	IOB29[A]	clk_ibuf/O
12.644	1.957	tNET	FF	1	R20C59[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
13.087	0.442	tC2Q	FF	54	R20C59[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
13.474	0.388	tNET	FF	1	R21C59[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
50.000	50.000					active clock edge time
50.000	0.000					clk
50.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
50.682	0.683	tINS	RR	2137	IOB29[A]	clk_ibuf/O
52.636	1.954	tNET	RR	1	R21C59[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1/CLK
52.289	-0.347	tSu		1	R21C59[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1

Path Statistics:

Clock Skew	-0.008
Setup Relationship	40.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 26.002%; route: 1.957, 73.998%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.388, 46.687%; tC2Q: 0.442, 53.313%
Required Clock Path Delay	cell: 0.683, 25.889%; route: 1.954, 74.111%

Path22

Path Summary:

Slack	38.822
Data Arrival Time	13.474
Data Required Time	52.296
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.688	0.688	tINS	FF	2137	IOB29[A]	clk_ibuf/O
12.644	1.957	tNET	FF	1	R20C59[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
13.087	0.442	tC2Q	FF	54	R20C59[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
13.474	0.388	tNET	FF	1	R22C58[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
50.000	50.000					active clock edge time
50.000	0.000					clk
50.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
50.682	0.683	tINS	RR	2137	IOB29[A]	clk_ibuf/O
52.643	1.961	tNET	RR	1	R22C58[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/CLK
52.296	-0.347	tSu		1	R22C58[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1

Path Statistics:

Clock Skew	-0.001
Setup Relationship	40.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 26.002%; route: 1.957, 73.998%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.388, 46.687%; tC2Q: 0.442, 53.313%
Required Clock Path Delay	cell: 0.683, 25.822%; route: 1.961, 74.178%

Path23

Path Summary:

Slack	38.822
Data Arrival Time	13.474
Data Required Time	52.296
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.688	0.688	tINS	FF	2137	IOB29[A]	clk_ibuf/O
12.644	1.957	tNET	FF	1	R20C59[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
13.087	0.442	tC2Q	FF	54	R20C59[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
13.474	0.388	tNET	FF	1	R22C58[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
50.000	50.000					active clock edge time
50.000	0.000					clk
50.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
50.682	0.683	tINS	RR	2137	IOB29[A]	clk_ibuf/O
52.643	1.961	tNET	RR	1	R22C58[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/CLK
52.296	-0.347	tSu		1	R22C58[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1

Path Statistics:

Clock Skew	-0.001
Setup Relationship	40.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 26.002%; route: 1.957, 73.998%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.388, 46.687%; tC2Q: 0.442, 53.313%
Required Clock Path Delay	cell: 0.683, 25.822%; route: 1.961, 74.178%

Path24

Path Summary:

Slack	38.824
Data Arrival Time	13.474
Data Required Time	52.298
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.688	0.688	tINS	FF	2137	IOB29[A]	clk_ibuf/O
12.644	1.957	tNET	FF	1	R20C59[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
13.087	0.442	tC2Q	FF	54	R20C59[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
13.474	0.388	tNET	FF	1	R21C58[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
50.000	50.000					active clock edge time
50.000	0.000					clk
50.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
50.682	0.683	tINS	RR	2137	IOB29[A]	clk_ibuf/O
52.646	1.963	tNET	RR	1	R21C58[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1/CLK
52.298	-0.347	tSu		1	R21C58[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1

Path Statistics:

Clock Skew	0.002
Setup Relationship	40.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 26.002%; route: 1.957, 73.998%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.388, 46.687%; tC2Q: 0.442, 53.313%
Required Clock Path Delay	cell: 0.683, 25.797%; route: 1.963, 74.203%

Path25

Path Summary:

Slack	38.824
Data Arrival Time	13.474
Data Required Time	52.298
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.688	0.688	tINS	FF	2137	IOB29[A]	clk_ibuf/O
12.644	1.957	tNET	FF	1	R20C59[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
13.087	0.442	tC2Q	FF	54	R20C59[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
13.474	0.388	tNET	FF	1	R21C58[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
50.000	50.000					active clock edge time
50.000	0.000					clk
50.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
50.682	0.683	tINS	RR	2137	IOB29[A]	clk_ibuf/O
52.646	1.963	tNET	RR	1	R21C58[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1/CLK
52.298	-0.347	tSu		1	R21C58[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1

Path Statistics:

Clock Skew	0.002
Setup Relationship	40.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 26.002%; route: 1.957, 73.998%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.388, 46.687%; tC2Q: 0.442, 53.313%
Required Clock Path Delay	cell: 0.683, 25.797%; route: 1.963, 74.203%

Removal Analysis Report

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	10.328
Data Arrival Time	11.677
Data Required Time	1.349
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/capture_window_sel_0_s3
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.677	0.678	tINS	FF	2137	IOB29[A]	clk_ibuf/O
11.401	0.724	tNET	FF	1	R20C59[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
11.559	0.158	tC2Q	FR	54	R20C59[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
11.677	0.118	tNET	RR	1	R20C57[2][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_0_s3/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	2137	IOB29[A]	clk_ibuf/O
1.402	0.727	tNET	RR	1	R20C57[2][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_0_s3/CLK
1.349	-0.053	tHld		1	R20C57[2][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_0_s3

Path Statistics:

Clock Skew	0.001
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 48.341%; route: 0.724, 51.659%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.118, 42.754%; tC2Q: 0.158, 57.246%
Required Clock Path Delay	cell: 0.675, 48.173%; route: 0.727, 51.827%

Path2

Path Summary:

Slack	10.328
Data Arrival Time	11.677
Data Required Time	1.349
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.677	0.678	tINS	FF	2137	IOB29[A]	clk_ibuf/O
11.401	0.724	tNET	FF	1	R20C59[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
11.559	0.158	tC2Q	FR	54	R20C59[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
11.677	0.118	tNET	RR	1	R20C57[0][B]	gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	2137	IOB29[A]	clk_ibuf/O
1.402	0.727	tNET	RR	1	R20C57[0][B]	gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1/CLK
1.349	-0.053	tHld		1	R20C57[0][B]	gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1

Path Statistics:

Clock Skew	0.001
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 48.341%; route: 0.724, 51.659%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.118, 42.754%; tC2Q: 0.158, 57.246%
Required Clock Path Delay	cell: 0.675, 48.173%; route: 0.727, 51.827%

Path3

Path Summary:

Slack	10.328
Data Arrival Time	11.677
Data Required Time	1.349
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.677	0.678	tINS	FF	2137	IOB29[A]	clk_ibuf/O
11.401	0.724	tNET	FF	1	R20C59[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
11.559	0.158	tC2Q	FR	54	R20C59[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
11.677	0.118	tNET	RR	1	R20C57[1][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	2137	IOB29[A]	clk_ibuf/O
1.402	0.727	tNET	RR	1	R20C57[1][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1/CLK
1.349	-0.053	tHld		1	R20C57[1][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1

Path Statistics:

Clock Skew	0.001
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 48.341%; route: 0.724, 51.659%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.118, 42.754%; tC2Q: 0.158, 57.246%
Required Clock Path Delay	cell: 0.675, 48.173%; route: 0.727, 51.827%

Path4

Path Summary:

Slack	10.328
Data Arrival Time	11.677
Data Required Time	1.349
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/capture_window_sel_4_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.677	0.678	tINS	FF	2137	IOB29[A]	clk_ibuf/O
11.401	0.724	tNET	FF	1	R20C59[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
11.559	0.158	tC2Q	FR	54	R20C59[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
11.677	0.118	tNET	RR	1	R20C57[0][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_4_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	2137	IOB29[A]	clk_ibuf/O
1.402	0.727	tNET	RR	1	R20C57[0][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_4_s1/CLK
1.349	-0.053	tHld		1	R20C57[0][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_4_s1

Path Statistics:

Clock Skew	0.001
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 48.341%; route: 0.724, 51.659%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.118, 42.754%; tC2Q: 0.158, 57.246%
Required Clock Path Delay	cell: 0.675, 48.173%; route: 0.727, 51.827%

Path5

Path Summary:

Slack	10.328
Data Arrival Time	11.677
Data Required Time	1.349
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/internal_reg_start_dly_0_s0
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.677	0.678	tINS	FF	2137	IOB29[A]	clk_ibuf/O
11.401	0.724	tNET	FF	1	R20C59[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
11.559	0.158	tC2Q	FR	54	R20C59[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
11.677	0.118	tNET	RR	1	R20C57[3][A]	gw_gao_inst_0/u_la0_top/internal_reg_start_dly_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	2137	IOB29[A]	clk_ibuf/O
1.402	0.727	tNET	RR	1	R20C57[3][A]	gw_gao_inst_0/u_la0_top/internal_reg_start_dly_0_s0/CLK
1.349	-0.053	tHld		1	R20C57[3][A]	gw_gao_inst_0/u_la0_top/internal_reg_start_dly_0_s0

Path Statistics:

Clock Skew	0.001
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 48.341%; route: 0.724, 51.659%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.118, 42.754%; tC2Q: 0.158, 57.246%
Required Clock Path Delay	cell: 0.675, 48.173%; route: 0.727, 51.827%

Path6

Path Summary:

Slack	10.328
Data Arrival Time	11.677
Data Required Time	1.349
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/internal_reg_start_syn_1_s0
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.677	0.678	tINS	FF	2137	IOB29[A]	clk_ibuf/O
11.401	0.724	tNET	FF	1	R20C59[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
11.559	0.158	tC2Q	FR	54	R20C59[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
11.677	0.118	tNET	RR	1	R20C57[2][B]	gw_gao_inst_0/u_la0_top/internal_reg_start_syn_1_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	2137	IOB29[A]	clk_ibuf/O
1.402	0.727	tNET	RR	1	R20C57[2][B]	gw_gao_inst_0/u_la0_top/internal_reg_start_syn_1_s0/CLK
1.349	-0.053	tHld		1	R20C57[2][B]	gw_gao_inst_0/u_la0_top/internal_reg_start_syn_1_s0

Path Statistics:

Clock Skew	0.001
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 48.341%; route: 0.724, 51.659%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.118, 42.754%; tC2Q: 0.158, 57.246%
Required Clock Path Delay	cell: 0.675, 48.173%; route: 0.727, 51.827%

Path7

Path Summary:

Slack	10.332
Data Arrival Time	11.677
Data Required Time	1.345
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.677	0.678	tINS	FF	2137	IOB29[A]	clk_ibuf/O
11.401	0.724	tNET	FF	1	R20C59[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
11.559	0.158	tC2Q	FR	54	R20C59[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
11.677	0.118	tNET	RR	1	R20C58[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	2137	IOB29[A]	clk_ibuf/O
1.398	0.723	tNET	RR	1	R20C58[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CLK
1.345	-0.053	tHld		1	R20C58[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1

Path Statistics:

Clock Skew	-0.003
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 48.341%; route: 0.724, 51.659%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.118, 42.754%; tC2Q: 0.158, 57.246%
Required Clock Path Delay	cell: 0.675, 48.310%; route: 0.723, 51.690%

Path8

Path Summary:

Slack	10.332
Data Arrival Time	11.677
Data Required Time	1.345
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.677	0.678	tINS	FF	2137	IOB29[A]	clk_ibuf/O
11.401	0.724	tNET	FF	1	R20C59[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
11.559	0.158	tC2Q	FR	54	R20C59[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
11.677	0.118	tNET	RR	1	R20C58[1][B]	gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	2137	IOB29[A]	clk_ibuf/O
1.398	0.723	tNET	RR	1	R20C58[1][B]	gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1/CLK
1.345	-0.053	tHld		1	R20C58[1][B]	gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1

Path Statistics:

Clock Skew	-0.003
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 48.341%; route: 0.724, 51.659%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.118, 42.754%; tC2Q: 0.158, 57.246%
Required Clock Path Delay	cell: 0.675, 48.310%; route: 0.723, 51.690%

Path9

Path Summary:

Slack	10.332
Data Arrival Time	11.677
Data Required Time	1.345
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/capture_window_sel_5_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.677	0.678	tINS	FF	2137	IOB29[A]	clk_ibuf/O
11.401	0.724	tNET	FF	1	R20C59[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
11.559	0.158	tC2Q	FR	54	R20C59[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
11.677	0.118	tNET	RR	1	R20C58[0][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_5_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	2137	IOB29[A]	clk_ibuf/O
1.398	0.723	tNET	RR	1	R20C58[0][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_5_s1/CLK
1.345	-0.053	tHld		1	R20C58[0][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_5_s1

Path Statistics:

Clock Skew	-0.003
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 48.341%; route: 0.724, 51.659%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.118, 42.754%; tC2Q: 0.158, 57.246%
Required Clock Path Delay	cell: 0.675, 48.310%; route: 0.723, 51.690%

Path10

Path Summary:

Slack	10.332
Data Arrival Time	11.677
Data Required Time	1.345
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/capture_window_sel_6_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.677	0.678	tINS	FF	2137	IOB29[A]	clk_ibuf/O
11.401	0.724	tNET	FF	1	R20C59[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
11.559	0.158	tC2Q	FR	54	R20C59[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
11.677	0.118	tNET	RR	1	R20C58[1][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_6_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	2137	IOB29[A]	clk_ibuf/O
1.398	0.723	tNET	RR	1	R20C58[1][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_6_s1/CLK
1.345	-0.053	tHld		1	R20C58[1][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_6_s1

Path Statistics:

Clock Skew	-0.003
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 48.341%; route: 0.724, 51.659%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.118, 42.754%; tC2Q: 0.158, 57.246%
Required Clock Path Delay	cell: 0.675, 48.310%; route: 0.723, 51.690%

Path11

Path Summary:

Slack	10.332
Data Arrival Time	11.677
Data Required Time	1.345
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/capture_window_sel_7_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.677	0.678	tINS	FF	2137	IOB29[A]	clk_ibuf/O
11.401	0.724	tNET	FF	1	R20C59[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
11.559	0.158	tC2Q	FR	54	R20C59[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
11.677	0.118	tNET	RR	1	R20C58[0][B]	gw_gao_inst_0/u_la0_top/capture_window_sel_7_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	2137	IOB29[A]	clk_ibuf/O
1.398	0.723	tNET	RR	1	R20C58[0][B]	gw_gao_inst_0/u_la0_top/capture_window_sel_7_s1/CLK
1.345	-0.053	tHld		1	R20C58[0][B]	gw_gao_inst_0/u_la0_top/capture_window_sel_7_s1

Path Statistics:

Clock Skew	-0.003
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 48.341%; route: 0.724, 51.659%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.118, 42.754%; tC2Q: 0.158, 57.246%
Required Clock Path Delay	cell: 0.675, 48.310%; route: 0.723, 51.690%

Path12

Path Summary:

Slack	10.410
Data Arrival Time	11.729
Data Required Time	1.319
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.677	0.678	tINS	FF	2137	IOB29[A]	clk_ibuf/O
11.401	0.724	tNET	FF	1	R20C59[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
11.559	0.158	tC2Q	FR	54	R20C59[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
11.729	0.170	tNET	RR	1	R18C59[2][A]	gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	2137	IOB29[A]	clk_ibuf/O
1.372	0.697	tNET	RR	1	R18C59[2][A]	gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0/CLK
1.319	-0.053	tHld		1	R18C59[2][A]	gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0

Path Statistics:

Clock Skew	-0.029
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 48.341%; route: 0.724, 51.659%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.170, 51.829%; tC2Q: 0.158, 48.171%
Required Clock Path Delay	cell: 0.675, 49.226%; route: 0.697, 50.774%

Path13

Path Summary:

Slack	10.410
Data Arrival Time	11.729
Data Required Time	1.319
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_1_s0
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.677	0.678	tINS	FF	2137	IOB29[A]	clk_ibuf/O
11.401	0.724	tNET	FF	1	R20C59[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
11.559	0.158	tC2Q	FR	54	R20C59[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
11.729	0.170	tNET	RR	1	R18C59[2][B]	gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_1_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	2137	IOB29[A]	clk_ibuf/O
1.372	0.697	tNET	RR	1	R18C59[2][B]	gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_1_s0/CLK
1.319	-0.053	tHld		1	R18C59[2][B]	gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_1_s0

Path Statistics:

Clock Skew	-0.029
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 48.341%; route: 0.724, 51.659%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.170, 51.829%; tC2Q: 0.158, 48.171%
Required Clock Path Delay	cell: 0.675, 49.226%; route: 0.697, 50.774%

Path14

Path Summary:

Slack	10.424
Data Arrival Time	11.767
Data Required Time	1.343
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.677	0.678	tINS	FF	2137	IOB29[A]	clk_ibuf/O
11.401	0.724	tNET	FF	1	R20C59[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
11.559	0.158	tC2Q	FR	54	R20C59[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
11.767	0.208	tNET	RR	1	R21C58[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	2137	IOB29[A]	clk_ibuf/O
1.397	0.721	tNET	RR	1	R21C58[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1/CLK
1.344	-0.053	tHld		1	R21C58[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1

Path Statistics:

Clock Skew	-0.005
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 48.341%; route: 0.724, 51.659%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.208, 56.831%; tC2Q: 0.158, 43.169%
Required Clock Path Delay	cell: 0.675, 48.371%; route: 0.721, 51.629%

Path15

Path Summary:

Slack	10.424
Data Arrival Time	11.767
Data Required Time	1.343
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.677	0.678	tINS	FF	2137	IOB29[A]	clk_ibuf/O
11.401	0.724	tNET	FF	1	R20C59[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
11.559	0.158	tC2Q	FR	54	R20C59[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
11.767	0.208	tNET	RR	1	R21C58[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	2137	IOB29[A]	clk_ibuf/O
1.397	0.721	tNET	RR	1	R21C58[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1/CLK
1.344	-0.053	tHld		1	R21C58[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1

Path Statistics:

Clock Skew	-0.005
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 48.341%; route: 0.724, 51.659%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.208, 56.831%; tC2Q: 0.158, 43.169%
Required Clock Path Delay	cell: 0.675, 48.371%; route: 0.721, 51.629%

Path16

Path Summary:

Slack	10.424
Data Arrival Time	11.767
Data Required Time	1.343
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_9_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.677	0.678	tINS	FF	2137	IOB29[A]	clk_ibuf/O
11.401	0.724	tNET	FF	1	R20C59[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
11.559	0.158	tC2Q	FR	54	R20C59[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
11.767	0.208	tNET	RR	1	R21C58[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_9_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	2137	IOB29[A]	clk_ibuf/O
1.397	0.721	tNET	RR	1	R21C58[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_9_s1/CLK
1.344	-0.053	tHld		1	R21C58[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_9_s1

Path Statistics:

Clock Skew	-0.005
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 48.341%; route: 0.724, 51.659%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.208, 56.831%; tC2Q: 0.158, 43.169%
Required Clock Path Delay	cell: 0.675, 48.371%; route: 0.721, 51.629%

Path17

Path Summary:

Slack	10.426
Data Arrival Time	11.767
Data Required Time	1.342
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.677	0.678	tINS	FF	2137	IOB29[A]	clk_ibuf/O
11.401	0.724	tNET	FF	1	R20C59[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
11.559	0.158	tC2Q	FR	54	R20C59[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
11.767	0.208	tNET	RR	1	R22C58[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	2137	IOB29[A]	clk_ibuf/O
1.395	0.719	tNET	RR	1	R22C58[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/CLK
1.342	-0.053	tHld		1	R22C58[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1

Path Statistics:

Clock Skew	-0.007
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 48.341%; route: 0.724, 51.659%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.208, 56.831%; tC2Q: 0.158, 43.169%
Required Clock Path Delay	cell: 0.675, 48.432%; route: 0.719, 51.568%

Path18

Path Summary:

Slack	10.426
Data Arrival Time	11.767
Data Required Time	1.342
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.677	0.678	tINS	FF	2137	IOB29[A]	clk_ibuf/O
11.401	0.724	tNET	FF	1	R20C59[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
11.559	0.158	tC2Q	FR	54	R20C59[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
11.767	0.208	tNET	RR	1	R22C58[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	2137	IOB29[A]	clk_ibuf/O
1.395	0.719	tNET	RR	1	R22C58[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/CLK
1.342	-0.053	tHld		1	R22C58[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1

Path Statistics:

Clock Skew	-0.007
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 48.341%; route: 0.724, 51.659%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.208, 56.831%; tC2Q: 0.158, 43.169%
Required Clock Path Delay	cell: 0.675, 48.432%; route: 0.719, 51.568%

Path19

Path Summary:

Slack	10.428
Data Arrival Time	11.767
Data Required Time	1.339
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.677	0.678	tINS	FF	2137	IOB29[A]	clk_ibuf/O
11.401	0.724	tNET	FF	1	R20C59[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
11.559	0.158	tC2Q	FR	54	R20C59[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
11.767	0.208	tNET	RR	1	R21C59[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1/PRESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	2137	IOB29[A]	clk_ibuf/O
1.392	0.717	tNET	RR	1	R21C59[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1/CLK
1.339	-0.053	tHld		1	R21C59[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1

Path Statistics:

Clock Skew	-0.009
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 48.341%; route: 0.724, 51.659%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.208, 56.831%; tC2Q: 0.158, 43.169%
Required Clock Path Delay	cell: 0.675, 48.510%; route: 0.717, 51.490%

Path20

Path Summary:

Slack	10.428
Data Arrival Time	11.767
Data Required Time	1.339
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.677	0.678	tINS	FF	2137	IOB29[A]	clk_ibuf/O
11.401	0.724	tNET	FF	1	R20C59[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
11.559	0.158	tC2Q	FR	54	R20C59[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
11.767	0.208	tNET	RR	1	R21C59[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	2137	IOB29[A]	clk_ibuf/O
1.392	0.717	tNET	RR	1	R21C59[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/CLK
1.339	-0.053	tHld		1	R21C59[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1

Path Statistics:

Clock Skew	-0.009
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 48.341%; route: 0.724, 51.659%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.208, 56.831%; tC2Q: 0.158, 43.169%
Required Clock Path Delay	cell: 0.675, 48.510%; route: 0.717, 51.490%

Path21

Path Summary:

Slack	10.428
Data Arrival Time	11.767
Data Required Time	1.339
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.677	0.678	tINS	FF	2137	IOB29[A]	clk_ibuf/O
11.401	0.724	tNET	FF	1	R20C59[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
11.559	0.158	tC2Q	FR	54	R20C59[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
11.767	0.208	tNET	RR	1	R21C59[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	2137	IOB29[A]	clk_ibuf/O
1.392	0.717	tNET	RR	1	R21C59[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1/CLK
1.339	-0.053	tHld		1	R21C59[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1

Path Statistics:

Clock Skew	-0.009
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 48.341%; route: 0.724, 51.659%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.208, 56.831%; tC2Q: 0.158, 43.169%
Required Clock Path Delay	cell: 0.675, 48.510%; route: 0.717, 51.490%

Path22

Path Summary:

Slack	10.429
Data Arrival Time	11.756
Data Required Time	1.327
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/internal_reg_start_dly_1_s0
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.677	0.678	tINS	FF	2137	IOB29[A]	clk_ibuf/O
11.401	0.724	tNET	FF	1	R20C59[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
11.559	0.158	tC2Q	FR	54	R20C59[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
11.756	0.197	tNET	RR	1	R18C57[3][B]	gw_gao_inst_0/u_la0_top/internal_reg_start_dly_1_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	2137	IOB29[A]	clk_ibuf/O
1.380	0.705	tNET	RR	1	R18C57[3][B]	gw_gao_inst_0/u_la0_top/internal_reg_start_dly_1_s0/CLK
1.327	-0.053	tHld		1	R18C57[3][B]	gw_gao_inst_0/u_la0_top/internal_reg_start_dly_1_s0

Path Statistics:

Clock Skew	-0.021
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 48.341%; route: 0.724, 51.659%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.197, 55.493%; tC2Q: 0.158, 44.507%
Required Clock Path Delay	cell: 0.675, 48.940%; route: 0.705, 51.060%

Path23

Path Summary:

Slack	10.429
Data Arrival Time	11.756
Data Required Time	1.327
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.677	0.678	tINS	FF	2137	IOB29[A]	clk_ibuf/O
11.401	0.724	tNET	FF	1	R20C59[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
11.559	0.158	tC2Q	FR	54	R20C59[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
11.756	0.197	tNET	RR	1	R18C57[2][B]	gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	2137	IOB29[A]	clk_ibuf/O
1.380	0.705	tNET	RR	1	R18C57[2][B]	gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0/CLK
1.327	-0.053	tHld		1	R18C57[2][B]	gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0

Path Statistics:

Clock Skew	-0.021
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 48.341%; route: 0.724, 51.659%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.197, 55.493%; tC2Q: 0.158, 44.507%
Required Clock Path Delay	cell: 0.675, 48.940%; route: 0.705, 51.060%

Path24

Path Summary:

Slack	10.430
Data Arrival Time	11.747
Data Required Time	1.317
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.677	0.678	tINS	FF	2137	IOB29[A]	clk_ibuf/O
11.401	0.724	tNET	FF	1	R20C59[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
11.559	0.158	tC2Q	FR	54	R20C59[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
11.747	0.187	tNET	RR	1	R11C60[2][B]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	2137	IOB29[A]	clk_ibuf/O
1.369	0.694	tNET	RR	1	R11C60[2][B]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0/CLK
1.316	-0.053	tHld		1	R11C60[2][B]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0

Path Statistics:

Clock Skew	-0.032
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 48.341%; route: 0.724, 51.659%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.187, 54.203%; tC2Q: 0.158, 45.797%
Required Clock Path Delay	cell: 0.675, 49.325%; route: 0.694, 50.675%

Path25

Path Summary:

Slack	10.430
Data Arrival Time	11.747
Data Required Time	1.317
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.677	0.678	tINS	FF	2137	IOB29[A]	clk_ibuf/O
11.401	0.724	tNET	FF	1	R20C59[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
11.559	0.158	tC2Q	FR	54	R20C59[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
11.747	0.187	tNET	RR	1	R11C60[0][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	2137	IOB29[A]	clk_ibuf/O
1.369	0.694	tNET	RR	1	R11C60[0][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0/CLK
1.316	-0.053	tHld		1	R11C60[0][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0

Path Statistics:

Clock Skew	-0.032
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 48.341%; route: 0.724, 51.659%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.187, 54.203%; tC2Q: 0.158, 45.797%
Required Clock Path Delay	cell: 0.675, 49.325%; route: 0.694, 50.675%

Minimum Pulse Width Report:

Report Command:report_min_pulse_width -nworst 10 -detail

MPW1

MPW Summary:

Slack:	7.759
Actual Width:	8.759
Required Width:	1.000
Type:	High Pulse Width
Clock:	clk
Objects:	uut/FP_Exponential_inst/frac_part_63_s3

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			clk
0.000	0.000	tCL	RR	clk_ibuf/I
0.683	0.683	tINS	RR	clk_ibuf/O
2.625	1.942	tNET	RR	uut/FP_Exponential_inst/frac_part_63_s3/CLK[0]

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	FF	clk_ibuf/I
10.677	0.678	tINS	FF	clk_ibuf/O
11.384	0.706	tNET	FF	uut/FP_Exponential_inst/frac_part_63_s3/CLK[0]

MPW2

MPW Summary:

Slack:	7.762
Actual Width:	8.762
Required Width:	1.000
Type:	High Pulse Width
Clock:	clk
Objects:	mem_data_in_mem_data_in_0_1_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			clk
0.000	0.000	tCL	RR	clk_ibuf/I
0.683	0.683	tINS	RR	clk_ibuf/O
2.623	1.941	tNET	RR	mem_data_in_mem_data_in_0_1_s/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	FF	clk_ibuf/I
10.677	0.678	tINS	FF	clk_ibuf/O
11.385	0.708	tNET	FF	mem_data_in_mem_data_in_0_1_s/CLK

MPW3

MPW Summary:

Slack:	7.764
Actual Width:	8.764
Required Width:	1.000
Type:	High Pulse Width
Clock:	clk
Objects:	uut/FP_Exponential_inst/frac_part_63_s4

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			clk
0.000	0.000	tCL	RR	clk_ibuf/I
0.683	0.683	tINS	RR	clk_ibuf/O
2.616	1.933	tNET	RR	uut/FP_Exponential_inst/frac_part_63_s4/CLK[0]

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	FF	clk_ibuf/I
10.677	0.678	tINS	FF	clk_ibuf/O
11.379	0.702	tNET	FF	uut/FP_Exponential_inst/frac_part_63_s4/CLK[0]

MPW4

MPW Summary:

Slack:	7.767
Actual Width:	8.767
Required Width:	1.000
Type:	High Pulse Width
Clock:	clk
Objects:	mem_data_in_mem_data_in_0_0_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			clk
0.000	0.000	tCL	RR	clk_ibuf/I
0.683	0.683	tINS	RR	clk_ibuf/O
2.614	1.932	tNET	RR	mem_data_in_mem_data_in_0_0_s/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	FF	clk_ibuf/I
10.677	0.678	tINS	FF	clk_ibuf/O
11.381	0.704	tNET	FF	mem_data_in_mem_data_in_0_0_s/CLK

MPW5

MPW Summary:

Slack:	7.767
Actual Width:	8.767
Required Width:	1.000
Type:	High Pulse Width
Clock:	clk
Objects:	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			clk
0.000	0.000	tCL	RR	clk_ibuf/I
0.683	0.683	tINS	RR	clk_ibuf/O
2.614	1.932	tNET	RR	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CLKA

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	FF	clk_ibuf/I
10.677	0.678	tINS	FF	clk_ibuf/O
11.381	0.704	tNET	FF	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CLKA

MPW6

MPW Summary:

Slack:	7.767
Actual Width:	8.767
Required Width:	1.000
Type:	High Pulse Width
Clock:	clk
Objects:	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			clk
0.000	0.000	tCL	RR	clk_ibuf/I
0.683	0.683	tINS	RR	clk_ibuf/O
2.614	1.932	tNET	RR	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/CLKA

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	FF	clk_ibuf/I
10.677	0.678	tINS	FF	clk_ibuf/O
11.381	0.704	tNET	FF	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/CLKA

MPW7

MPW Summary:

Slack:	7.773
Actual Width:	8.773
Required Width:	1.000
Type:	High Pulse Width
Clock:	clk
Objects:	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			clk
0.000	0.000	tCL	RR	clk_ibuf/I
0.683	0.683	tINS	RR	clk_ibuf/O
2.605	1.922	tNET	RR	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CLKA

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	FF	clk_ibuf/I
10.677	0.678	tINS	FF	clk_ibuf/O
11.377	0.700	tNET	FF	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CLKA

MPW8

MPW Summary:

Slack:	8.498
Actual Width:	8.748
Required Width:	0.250
Type:	High Pulse Width
Clock:	clk
Objects:	uut/FP_Exponential_inst/index[11]_4_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			clk
0.000	0.000	tCL	RR	clk_ibuf/I
0.683	0.683	tINS	RR	clk_ibuf/O
2.659	1.977	tNET	RR	uut/FP_Exponential_inst/index[11]_4_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	FF	clk_ibuf/I
10.677	0.678	tINS	FF	clk_ibuf/O
11.407	0.730	tNET	FF	uut/FP_Exponential_inst/index[11]_4_s0/CLK

MPW9

MPW Summary:

Slack:	8.498
Actual Width:	8.748
Required Width:	0.250
Type:	High Pulse Width
Clock:	clk
Objects:	uut/FP_Exponential_inst/index[12]_4_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			clk
0.000	0.000	tCL	RR	clk_ibuf/I
0.683	0.683	tINS	RR	clk_ibuf/O
2.659	1.977	tNET	RR	uut/FP_Exponential_inst/index[12]_4_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	FF	clk_ibuf/I
10.677	0.678	tINS	FF	clk_ibuf/O
11.407	0.730	tNET	FF	uut/FP_Exponential_inst/index[12]_4_s0/CLK

MPW10

MPW Summary:

Slack:	8.498
Actual Width:	8.748
Required Width:	0.250
Type:	High Pulse Width
Clock:	clk
Objects:	uut/FP_Exponential_inst/index[13]_4_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			clk
0.000	0.000	tCL	RR	clk_ibuf/I
0.683	0.683	tINS	RR	clk_ibuf/O
2.659	1.977	tNET	RR	uut/FP_Exponential_inst/index[13]_4_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	FF	clk_ibuf/I
10.677	0.678	tINS	FF	clk_ibuf/O
11.407	0.730	tNET	FF	uut/FP_Exponential_inst/index[13]_4_s0/CLK

High Fanout Nets Report:

Report Command:report_high_fanout_nets -max_nets 10

FANOUT	NET NAME	WORST SLACK	MAX DELAY
2137	clk_d	32.093	1.977
1975	ce	47.044	2.493
258	control0[0]	42.313	2.735
106	index[27][0]	42.332	1.834
104	data[24]	33.084	1.676
95	data[23]	32.267	2.127
87	index[27][1]	42.632	2.108
61	n20_3	46.747	1.233
57	data_z[1][31]	45.514	1.562
55	data[25]	33.390	1.500

Route Congestions Report:

Report Command:report_route_congestion -max_grids 10

GRID LOC	ROUTE CONGESTIONS
R19C56	58.33%
R26C33	56.94%
R15C51	55.56%
R20C57	55.56%
R19C59	52.78%
R27C48	51.39%
R26C35	51.39%
R19C63	51.39%
R30C50	51.39%
R27C51	50.00%

Timing Exceptions Report:

Setup Analysis Report

Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Hold Analysis Report

Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Recovery Analysis Report

Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Removal Analysis Report

Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Timing Constraints Report:

SDC Command Type	State	Detail Command
TC_CLOCK	Actived	create_clock -name clk -period 50 -waveform {0 10} [get_ports {clk}]
TC_CLOCK	Actived	create_clock -name tck_pad_i -period 50 -waveform {0 25} [get_ports {tck_pad_i}]
TC_FALSE_PATH	Actived	set_false_path -to [get_regs {gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_38_s0}]
TC_CLOCK_GROUP	Actived	set_clock_groups -asynchronous -group [get_clocks {clk}] -group [get_clocks {tck_pad_i}]