Synthesis Messages
| Report Title | GowinSynthesis Report |
| Design File | E:\myWork\IP\releaseVerify\version\1.9.11\Gowin_FP_Exponential_RefDesign\proj\src\fp_exponential\fp_exponential.v E:\myWork\IP\releaseVerify\version\1.9.11\Gowin_FP_Exponential_RefDesign\proj\src\top.v C:\Gowin\78162\Gowin_V1.9.11_x64\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_crc32.v C:\Gowin\78162\Gowin_V1.9.11_x64\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_match.v C:\Gowin\78162\Gowin_V1.9.11_x64\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_mem_ctrl.v C:\Gowin\78162\Gowin_V1.9.11_x64\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_top.v C:\Gowin\78162\Gowin_V1.9.11_x64\IDE\data\ipcores\GAO\GW_CON\gw_con_top.v C:\Gowin\78162\Gowin_V1.9.11_x64\IDE\data\ipcores\gw_jtag.v E:\myWork\IP\releaseVerify\version\1.9.11\Gowin_FP_Exponential_RefDesign\proj\impl\gwsynthesis\RTL_GAO\gw_gao_top.v |
| GowinSynthesis Constraints File | --- |
| Tool Version | V1.9.11 (64-bit) |
| Part Number | GW5A-LV25UG324ES |
| Device | GW5A-25 |
| Device Version | A |
| Created Time | Wed Dec 25 13:26:51 2024 |
| Legal Announcement | Copyright (C)2014-2024 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
| Top Level Module | top |
| Synthesis Process | Running parser: CPU time = 0h 0m 0.906s, Elapsed time = 0h 0m 0.887s, Peak memory usage = 200.047MB Running netlist conversion: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0.14s, Elapsed time = 0h 0m 0.133s, Peak memory usage = 200.047MB Optimizing Phase 1: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.09s, Peak memory usage = 200.047MB Optimizing Phase 2: CPU time = 0h 0m 0.25s, Elapsed time = 0h 0m 0.248s, Peak memory usage = 200.047MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0.109s, Elapsed time = 0h 0m 0.097s, Peak memory usage = 200.047MB Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.013s, Peak memory usage = 200.047MB Inferring Phase 2: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.016s, Peak memory usage = 200.047MB Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.01s, Peak memory usage = 200.047MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0.125s, Elapsed time = 0h 0m 0.119s, Peak memory usage = 200.047MB Tech-Mapping Phase 1: CPU time = 0h 0m 0.093s, Elapsed time = 0h 0m 0.097s, Peak memory usage = 200.047MB Tech-Mapping Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.022s, Peak memory usage = 200.047MB Tech-Mapping Phase 3: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 211.867MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.14s, Elapsed time = 0h 0m 0.163s, Peak memory usage = 211.867MB Generate output files: CPU time = 0h 0m 0.265s, Elapsed time = 0h 0m 0.318s, Peak memory usage = 220.750MB |
| Total Time and Memory Usage | CPU time = 0h 0m 3s, Elapsed time = 0h 0m 3s, Peak memory usage = 220.750MB |
Resource
Resource Usage Summary
| Resource | Usage |
| I/O Port | 42 |
| I/O Buf | 42 |
| IBUF | 5 |
| OBUF | 37 |
| Register | 2384 |
| DFFRE | 1 |
| DFFPE | 36 |
| DFFCE | 2347 |
| LUT | 1579 |
| LUT2 | 198 |
| LUT3 | 536 |
| LUT4 | 845 |
| MUX | 1 |
| MUX16 | 1 |
| ALU | 1480 |
| ALU | 1480 |
| INV | 32 |
| INV | 32 |
| DSP | |
| MULT27X36 | 6 |
| BSRAM | 5 |
| SDPB | 3 |
| pROM | 2 |
| Black Box | 1 |
| GW_JTAG | 1 |
Resource Utilization Summary
| Resource | Usage | Utilization |
| Logic | 3099(1619 LUT, 1480 ALU) / 23040 | 14% |
| Register | 2384 / 23685 | 11% |
| --Register as Latch | 0 / 23685 | 0% |
| --Register as FF | 2384 / 23685 | 11% |
| BSRAM | 5 / 56 | 9% |
Timing
Clock Summary:
| NO. | Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
|---|---|---|---|---|---|---|---|---|---|
| 1 | clk | Base | 10.000 | 100.0 | 0.000 | 5.000 | clk_ibuf/I |
Max Frequency Summary:
| NO. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
|---|---|---|---|---|---|
| 1 | clk | 100.000(MHz) | 67.654(MHz) | 12 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:| Slack | -4.781 |
| Data Arrival Time | 14.353 |
| Data Required Time | 9.572 |
| From | mem_data_in_mem_data_in_0_0_s |
| To | uut/FP_Exponential_inst/frac_part_63_s4 |
| Launch Clk | clk[R] |
| Latch Clk | clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | clk | |||
| 0.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 2137 | clk_ibuf/O |
| 0.375 | 0.375 | tNET | RR | 16 | mem_data_in_mem_data_in_0_0_s/CLK |
| 2.385 | 2.010 | tC2Q | RR | 8 | mem_data_in_mem_data_in_0_0_s/DO[13] |
| 2.760 | 0.375 | tNET | RR | 1 | uut/FP_Exponential_inst/n114_s4/I0 |
| 3.286 | 0.526 | tINS | RR | 2 | uut/FP_Exponential_inst/n114_s4/F |
| 3.661 | 0.375 | tNET | RR | 1 | uut/FP_Exponential_inst/n114_s3/I0 |
| 4.188 | 0.526 | tINS | RR | 2 | uut/FP_Exponential_inst/n114_s3/F |
| 4.563 | 0.375 | tNET | RR | 1 | uut/FP_Exponential_inst/n150_Z_s2/I0 |
| 5.089 | 0.526 | tINS | RR | 2 | uut/FP_Exponential_inst/n150_Z_s2/F |
| 5.464 | 0.375 | tNET | RR | 1 | uut/FP_Exponential_inst/n150_Z_s0/I0 |
| 5.990 | 0.526 | tINS | RR | 2 | uut/FP_Exponential_inst/n150_Z_s0/F |
| 6.365 | 0.375 | tNET | RR | 1 | uut/FP_Exponential_inst/n166_Z_s0/I1 |
| 6.881 | 0.516 | tINS | RR | 2 | uut/FP_Exponential_inst/n166_Z_s0/F |
| 7.256 | 0.375 | tNET | RR | 1 | uut/FP_Exponential_inst/n166_Z_s/I1 |
| 7.773 | 0.516 | tINS | RR | 1 | uut/FP_Exponential_inst/n166_Z_s/F |
| 8.148 | 0.375 | tNET | RR | 63 | uut/FP_Exponential_inst/mult_122_s8/A[0] |
| 10.789 | 2.642 | tINS | RR | 1 | uut/FP_Exponential_inst/mult_122_s8/DOUT[28] |
| 11.164 | 0.375 | tNET | RR | 2 | uut/FP_Exponential_inst/mult_1223_28_s/I0 |
| 11.896 | 0.731 | tINS | RR | 1 | uut/FP_Exponential_inst/mult_1223_28_s/SUM |
| 12.271 | 0.375 | tNET | RR | 2 | uut/FP_Exponential_inst/n234_s0/I1 |
| 12.833 | 0.563 | tINS | RF | 1 | uut/FP_Exponential_inst/n234_s0/COUT |
| 12.833 | 0.000 | tNET | FF | 2 | uut/FP_Exponential_inst/n233_s0/CIN |
| 13.077 | 0.244 | tINS | FR | 1 | uut/FP_Exponential_inst/n233_s0/SUM |
| 13.452 | 0.375 | tNET | RR | 1 | uut/FP_Exponential_inst/n396_s0/I0 |
| 13.978 | 0.526 | tINS | RR | 2 | uut/FP_Exponential_inst/n396_s0/F |
| 14.353 | 0.375 | tNET | RR | 1 | uut/FP_Exponential_inst/frac_part_63_s4/B[31] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | clk | |||
| 10.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 2137 | clk_ibuf/O |
| 10.375 | 0.375 | tNET | RR | 1 | uut/FP_Exponential_inst/frac_part_63_s4/CLK[0] |
| 9.572 | -0.803 | tSu | 1 | uut/FP_Exponential_inst/frac_part_63_s4 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 12 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
| Arrival Data Path Delay: | cell: 7.843, 56.109%; route: 4.125, 29.511%; tC2Q: 2.010, 14.380% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
Path 2
Path Summary:| Slack | -4.781 |
| Data Arrival Time | 14.353 |
| Data Required Time | 9.572 |
| From | mem_data_in_mem_data_in_0_0_s |
| To | uut/FP_Exponential_inst/frac_part_63_s3 |
| Launch Clk | clk[R] |
| Latch Clk | clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | clk | |||
| 0.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 2137 | clk_ibuf/O |
| 0.375 | 0.375 | tNET | RR | 16 | mem_data_in_mem_data_in_0_0_s/CLK |
| 2.385 | 2.010 | tC2Q | RR | 8 | mem_data_in_mem_data_in_0_0_s/DO[13] |
| 2.760 | 0.375 | tNET | RR | 1 | uut/FP_Exponential_inst/n114_s4/I0 |
| 3.286 | 0.526 | tINS | RR | 2 | uut/FP_Exponential_inst/n114_s4/F |
| 3.661 | 0.375 | tNET | RR | 1 | uut/FP_Exponential_inst/n114_s3/I0 |
| 4.188 | 0.526 | tINS | RR | 2 | uut/FP_Exponential_inst/n114_s3/F |
| 4.563 | 0.375 | tNET | RR | 1 | uut/FP_Exponential_inst/n150_Z_s2/I0 |
| 5.089 | 0.526 | tINS | RR | 2 | uut/FP_Exponential_inst/n150_Z_s2/F |
| 5.464 | 0.375 | tNET | RR | 1 | uut/FP_Exponential_inst/n150_Z_s0/I0 |
| 5.990 | 0.526 | tINS | RR | 2 | uut/FP_Exponential_inst/n150_Z_s0/F |
| 6.365 | 0.375 | tNET | RR | 1 | uut/FP_Exponential_inst/n166_Z_s0/I1 |
| 6.881 | 0.516 | tINS | RR | 2 | uut/FP_Exponential_inst/n166_Z_s0/F |
| 7.256 | 0.375 | tNET | RR | 1 | uut/FP_Exponential_inst/n166_Z_s/I1 |
| 7.773 | 0.516 | tINS | RR | 1 | uut/FP_Exponential_inst/n166_Z_s/F |
| 8.148 | 0.375 | tNET | RR | 63 | uut/FP_Exponential_inst/mult_122_s8/A[0] |
| 10.789 | 2.642 | tINS | RR | 1 | uut/FP_Exponential_inst/mult_122_s8/DOUT[28] |
| 11.164 | 0.375 | tNET | RR | 2 | uut/FP_Exponential_inst/mult_1223_28_s/I0 |
| 11.896 | 0.731 | tINS | RR | 1 | uut/FP_Exponential_inst/mult_1223_28_s/SUM |
| 12.271 | 0.375 | tNET | RR | 2 | uut/FP_Exponential_inst/n234_s0/I1 |
| 12.833 | 0.563 | tINS | RF | 1 | uut/FP_Exponential_inst/n234_s0/COUT |
| 12.833 | 0.000 | tNET | FF | 2 | uut/FP_Exponential_inst/n233_s0/CIN |
| 13.077 | 0.244 | tINS | FR | 1 | uut/FP_Exponential_inst/n233_s0/SUM |
| 13.452 | 0.375 | tNET | RR | 1 | uut/FP_Exponential_inst/n396_s0/I0 |
| 13.978 | 0.526 | tINS | RR | 2 | uut/FP_Exponential_inst/n396_s0/F |
| 14.353 | 0.375 | tNET | RR | 1 | uut/FP_Exponential_inst/frac_part_63_s3/B[31] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | clk | |||
| 10.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 2137 | clk_ibuf/O |
| 10.375 | 0.375 | tNET | RR | 1 | uut/FP_Exponential_inst/frac_part_63_s3/CLK[0] |
| 9.572 | -0.803 | tSu | 1 | uut/FP_Exponential_inst/frac_part_63_s3 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 12 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
| Arrival Data Path Delay: | cell: 7.843, 56.109%; route: 4.125, 29.511%; tC2Q: 2.010, 14.380% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
Path 3
Path Summary:| Slack | -4.590 |
| Data Arrival Time | 14.153 |
| Data Required Time | 9.563 |
| From | mem_data_in_mem_data_in_0_0_s |
| To | uut/FP_Exponential_inst/frac_part_63_s4 |
| Launch Clk | clk[R] |
| Latch Clk | clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | clk | |||
| 0.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 2137 | clk_ibuf/O |
| 0.375 | 0.375 | tNET | RR | 16 | mem_data_in_mem_data_in_0_0_s/CLK |
| 2.385 | 2.010 | tC2Q | RR | 8 | mem_data_in_mem_data_in_0_0_s/DO[4] |
| 2.760 | 0.375 | tNET | RR | 1 | uut/FP_Exponential_inst/n123_s11/I0 |
| 3.286 | 0.526 | tINS | RR | 2 | uut/FP_Exponential_inst/n123_s11/F |
| 3.661 | 0.375 | tNET | RR | 1 | uut/FP_Exponential_inst/n123_s10/I0 |
| 4.188 | 0.526 | tINS | RR | 2 | uut/FP_Exponential_inst/n123_s10/F |
| 4.563 | 0.375 | tNET | RR | 1 | uut/FP_Exponential_inst/n183_Z_s2/I0 |
| 5.089 | 0.526 | tINS | RR | 2 | uut/FP_Exponential_inst/n183_Z_s2/F |
| 5.464 | 0.375 | tNET | RR | 1 | uut/FP_Exponential_inst/n175_Z_s1/I0 |
| 5.990 | 0.526 | tINS | RR | 2 | uut/FP_Exponential_inst/n175_Z_s1/F |
| 6.365 | 0.375 | tNET | RR | 1 | uut/FP_Exponential_inst/n175_Z_s0/I2 |
| 6.826 | 0.461 | tINS | RR | 2 | uut/FP_Exponential_inst/n175_Z_s0/F |
| 7.201 | 0.375 | tNET | RR | 1 | uut/FP_Exponential_inst/n175_Z_s/I1 |
| 7.717 | 0.516 | tINS | RR | 1 | uut/FP_Exponential_inst/n175_Z_s/F |
| 8.092 | 0.375 | tNET | RR | 29 | uut/FP_Exponential_inst/mult_122_s7/A[17] |
| 11.252 | 3.159 | tINS | RR | 1 | uut/FP_Exponential_inst/mult_122_s7/DOUT[42] |
| 11.627 | 0.375 | tNET | RR | 2 | uut/FP_Exponential_inst/n246_s0/I0 |
| 12.183 | 0.556 | tINS | RF | 1 | uut/FP_Exponential_inst/n246_s0/COUT |
| 12.183 | 0.000 | tNET | FF | 2 | uut/FP_Exponential_inst/n245_s0/CIN |
| 12.233 | 0.050 | tINS | FR | 1 | uut/FP_Exponential_inst/n245_s0/COUT |
| 12.233 | 0.000 | tNET | RR | 2 | uut/FP_Exponential_inst/n244_s0/CIN |
| 12.283 | 0.050 | tINS | RR | 1 | uut/FP_Exponential_inst/n244_s0/COUT |
| 12.283 | 0.000 | tNET | RR | 2 | uut/FP_Exponential_inst/n243_s0/CIN |
| 12.333 | 0.050 | tINS | RR | 1 | uut/FP_Exponential_inst/n243_s0/COUT |
| 12.333 | 0.000 | tNET | RR | 2 | uut/FP_Exponential_inst/n242_s0/CIN |
| 12.383 | 0.050 | tINS | RR | 1 | uut/FP_Exponential_inst/n242_s0/COUT |
| 12.383 | 0.000 | tNET | RR | 2 | uut/FP_Exponential_inst/n241_s0/CIN |
| 12.433 | 0.050 | tINS | RR | 1 | uut/FP_Exponential_inst/n241_s0/COUT |
| 12.433 | 0.000 | tNET | RR | 2 | uut/FP_Exponential_inst/n240_s0/CIN |
| 12.483 | 0.050 | tINS | RR | 1 | uut/FP_Exponential_inst/n240_s0/COUT |
| 12.483 | 0.000 | tNET | RR | 2 | uut/FP_Exponential_inst/n239_s0/CIN |
| 12.533 | 0.050 | tINS | RR | 1 | uut/FP_Exponential_inst/n239_s0/COUT |
| 12.533 | 0.000 | tNET | RR | 2 | uut/FP_Exponential_inst/n238_s0/CIN |
| 12.583 | 0.050 | tINS | RR | 1 | uut/FP_Exponential_inst/n238_s0/COUT |
| 12.583 | 0.000 | tNET | RR | 2 | uut/FP_Exponential_inst/n237_s0/CIN |
| 12.633 | 0.050 | tINS | RR | 1 | uut/FP_Exponential_inst/n237_s0/COUT |
| 12.633 | 0.000 | tNET | RR | 2 | uut/FP_Exponential_inst/n236_s0/CIN |
| 12.877 | 0.244 | tINS | RR | 1 | uut/FP_Exponential_inst/n236_s0/SUM |
| 13.252 | 0.375 | tNET | RR | 1 | uut/FP_Exponential_inst/n399_s0/I0 |
| 13.778 | 0.526 | tINS | RR | 2 | uut/FP_Exponential_inst/n399_s0/F |
| 14.153 | 0.375 | tNET | RR | 1 | uut/FP_Exponential_inst/frac_part_63_s4/B[28] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | clk | |||
| 10.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 2137 | clk_ibuf/O |
| 10.375 | 0.375 | tNET | RR | 1 | uut/FP_Exponential_inst/frac_part_63_s4/CLK[0] |
| 9.563 | -0.812 | tSu | 1 | uut/FP_Exponential_inst/frac_part_63_s4 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 12 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
| Arrival Data Path Delay: | cell: 8.018, 58.195%; route: 3.750, 27.217%; tC2Q: 2.010, 14.588% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
Path 4
Path Summary:| Slack | -4.590 |
| Data Arrival Time | 14.153 |
| Data Required Time | 9.563 |
| From | mem_data_in_mem_data_in_0_0_s |
| To | uut/FP_Exponential_inst/frac_part_63_s3 |
| Launch Clk | clk[R] |
| Latch Clk | clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | clk | |||
| 0.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 2137 | clk_ibuf/O |
| 0.375 | 0.375 | tNET | RR | 16 | mem_data_in_mem_data_in_0_0_s/CLK |
| 2.385 | 2.010 | tC2Q | RR | 8 | mem_data_in_mem_data_in_0_0_s/DO[4] |
| 2.760 | 0.375 | tNET | RR | 1 | uut/FP_Exponential_inst/n123_s11/I0 |
| 3.286 | 0.526 | tINS | RR | 2 | uut/FP_Exponential_inst/n123_s11/F |
| 3.661 | 0.375 | tNET | RR | 1 | uut/FP_Exponential_inst/n123_s10/I0 |
| 4.188 | 0.526 | tINS | RR | 2 | uut/FP_Exponential_inst/n123_s10/F |
| 4.563 | 0.375 | tNET | RR | 1 | uut/FP_Exponential_inst/n183_Z_s2/I0 |
| 5.089 | 0.526 | tINS | RR | 2 | uut/FP_Exponential_inst/n183_Z_s2/F |
| 5.464 | 0.375 | tNET | RR | 1 | uut/FP_Exponential_inst/n175_Z_s1/I0 |
| 5.990 | 0.526 | tINS | RR | 2 | uut/FP_Exponential_inst/n175_Z_s1/F |
| 6.365 | 0.375 | tNET | RR | 1 | uut/FP_Exponential_inst/n175_Z_s0/I2 |
| 6.826 | 0.461 | tINS | RR | 2 | uut/FP_Exponential_inst/n175_Z_s0/F |
| 7.201 | 0.375 | tNET | RR | 1 | uut/FP_Exponential_inst/n175_Z_s/I1 |
| 7.717 | 0.516 | tINS | RR | 1 | uut/FP_Exponential_inst/n175_Z_s/F |
| 8.092 | 0.375 | tNET | RR | 29 | uut/FP_Exponential_inst/mult_122_s7/A[17] |
| 11.252 | 3.159 | tINS | RR | 1 | uut/FP_Exponential_inst/mult_122_s7/DOUT[42] |
| 11.627 | 0.375 | tNET | RR | 2 | uut/FP_Exponential_inst/n246_s0/I0 |
| 12.183 | 0.556 | tINS | RF | 1 | uut/FP_Exponential_inst/n246_s0/COUT |
| 12.183 | 0.000 | tNET | FF | 2 | uut/FP_Exponential_inst/n245_s0/CIN |
| 12.233 | 0.050 | tINS | FR | 1 | uut/FP_Exponential_inst/n245_s0/COUT |
| 12.233 | 0.000 | tNET | RR | 2 | uut/FP_Exponential_inst/n244_s0/CIN |
| 12.283 | 0.050 | tINS | RR | 1 | uut/FP_Exponential_inst/n244_s0/COUT |
| 12.283 | 0.000 | tNET | RR | 2 | uut/FP_Exponential_inst/n243_s0/CIN |
| 12.333 | 0.050 | tINS | RR | 1 | uut/FP_Exponential_inst/n243_s0/COUT |
| 12.333 | 0.000 | tNET | RR | 2 | uut/FP_Exponential_inst/n242_s0/CIN |
| 12.383 | 0.050 | tINS | RR | 1 | uut/FP_Exponential_inst/n242_s0/COUT |
| 12.383 | 0.000 | tNET | RR | 2 | uut/FP_Exponential_inst/n241_s0/CIN |
| 12.433 | 0.050 | tINS | RR | 1 | uut/FP_Exponential_inst/n241_s0/COUT |
| 12.433 | 0.000 | tNET | RR | 2 | uut/FP_Exponential_inst/n240_s0/CIN |
| 12.483 | 0.050 | tINS | RR | 1 | uut/FP_Exponential_inst/n240_s0/COUT |
| 12.483 | 0.000 | tNET | RR | 2 | uut/FP_Exponential_inst/n239_s0/CIN |
| 12.533 | 0.050 | tINS | RR | 1 | uut/FP_Exponential_inst/n239_s0/COUT |
| 12.533 | 0.000 | tNET | RR | 2 | uut/FP_Exponential_inst/n238_s0/CIN |
| 12.583 | 0.050 | tINS | RR | 1 | uut/FP_Exponential_inst/n238_s0/COUT |
| 12.583 | 0.000 | tNET | RR | 2 | uut/FP_Exponential_inst/n237_s0/CIN |
| 12.633 | 0.050 | tINS | RR | 1 | uut/FP_Exponential_inst/n237_s0/COUT |
| 12.633 | 0.000 | tNET | RR | 2 | uut/FP_Exponential_inst/n236_s0/CIN |
| 12.877 | 0.244 | tINS | RR | 1 | uut/FP_Exponential_inst/n236_s0/SUM |
| 13.252 | 0.375 | tNET | RR | 1 | uut/FP_Exponential_inst/n399_s0/I0 |
| 13.778 | 0.526 | tINS | RR | 2 | uut/FP_Exponential_inst/n399_s0/F |
| 14.153 | 0.375 | tNET | RR | 1 | uut/FP_Exponential_inst/frac_part_63_s3/B[28] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | clk | |||
| 10.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 2137 | clk_ibuf/O |
| 10.375 | 0.375 | tNET | RR | 1 | uut/FP_Exponential_inst/frac_part_63_s3/CLK[0] |
| 9.563 | -0.812 | tSu | 1 | uut/FP_Exponential_inst/frac_part_63_s3 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 12 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
| Arrival Data Path Delay: | cell: 8.018, 58.195%; route: 3.750, 27.217%; tC2Q: 2.010, 14.588% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
Path 5
Path Summary:| Slack | -4.535 |
| Data Arrival Time | 14.277 |
| Data Required Time | 9.742 |
| From | mem_data_in_mem_data_in_0_0_s |
| To | uut/FP_Exponential_inst/frac_part_63_s3 |
| Launch Clk | clk[R] |
| Latch Clk | clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | clk | |||
| 0.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 2137 | clk_ibuf/O |
| 0.375 | 0.375 | tNET | RR | 16 | mem_data_in_mem_data_in_0_0_s/CLK |
| 2.385 | 2.010 | tC2Q | RR | 8 | mem_data_in_mem_data_in_0_0_s/DO[13] |
| 2.760 | 0.375 | tNET | RR | 1 | uut/FP_Exponential_inst/n114_s4/I0 |
| 3.286 | 0.526 | tINS | RR | 2 | uut/FP_Exponential_inst/n114_s4/F |
| 3.661 | 0.375 | tNET | RR | 1 | uut/FP_Exponential_inst/n114_s3/I0 |
| 4.188 | 0.526 | tINS | RR | 2 | uut/FP_Exponential_inst/n114_s3/F |
| 4.563 | 0.375 | tNET | RR | 1 | uut/FP_Exponential_inst/n150_Z_s2/I0 |
| 5.089 | 0.526 | tINS | RR | 2 | uut/FP_Exponential_inst/n150_Z_s2/F |
| 5.464 | 0.375 | tNET | RR | 1 | uut/FP_Exponential_inst/n150_Z_s0/I0 |
| 5.990 | 0.526 | tINS | RR | 2 | uut/FP_Exponential_inst/n150_Z_s0/F |
| 6.365 | 0.375 | tNET | RR | 1 | uut/FP_Exponential_inst/n166_Z_s0/I1 |
| 6.881 | 0.516 | tINS | RR | 2 | uut/FP_Exponential_inst/n166_Z_s0/F |
| 7.256 | 0.375 | tNET | RR | 1 | uut/FP_Exponential_inst/n166_Z_s/I1 |
| 7.773 | 0.516 | tINS | RR | 1 | uut/FP_Exponential_inst/n166_Z_s/F |
| 8.148 | 0.375 | tNET | RR | 63 | uut/FP_Exponential_inst/mult_122_s8/A[0] |
| 10.789 | 2.642 | tINS | RR | 1 | uut/FP_Exponential_inst/mult_122_s8/DOUT[28] |
| 11.164 | 0.375 | tNET | RR | 2 | uut/FP_Exponential_inst/mult_1223_28_s/I0 |
| 11.896 | 0.731 | tINS | RR | 1 | uut/FP_Exponential_inst/mult_1223_28_s/SUM |
| 12.271 | 0.375 | tNET | RR | 2 | uut/FP_Exponential_inst/n234_s0/I1 |
| 13.001 | 0.730 | tINS | RR | 1 | uut/FP_Exponential_inst/n234_s0/SUM |
| 13.376 | 0.375 | tNET | RR | 1 | uut/FP_Exponential_inst/n397_s0/I0 |
| 13.902 | 0.526 | tINS | RR | 2 | uut/FP_Exponential_inst/n397_s0/F |
| 14.277 | 0.375 | tNET | RR | 1 | uut/FP_Exponential_inst/frac_part_63_s3/B[30] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | clk | |||
| 10.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 2137 | clk_ibuf/O |
| 10.375 | 0.375 | tNET | RR | 1 | uut/FP_Exponential_inst/frac_part_63_s3/CLK[0] |
| 9.742 | -0.633 | tSu | 1 | uut/FP_Exponential_inst/frac_part_63_s3 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 11 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
| Arrival Data Path Delay: | cell: 7.767, 55.869%; route: 4.125, 29.672%; tC2Q: 2.010, 14.459% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |