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         Gowin_Black_Level_Correction 参考设计阅读指南
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目标器件：GW2A-LV18PG256C8/I7
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文件列表
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.
| -- docs
|    `-- readme.txt				-->	自述文件
| -- project
|    |	`-- fpga_project.gprj			-->	参考设计工程
|    |-- src
|      	|  `-- BLC_exp.v			-->	工程顶层模块
|      	|  `-- demo.cst
|      	|  `-- data.dat
|      	|  `-- fpga_project.rao
|      	|  `-- fpga_project.sdc
|       |   -- black_level_correction
|        	|   `-- black_level_correction.ipc
|        	|   `-- black_level_correction.v
|        	|   `-- black_level_correction.vo		    -->	仿真使用vo文件
|    |-- impl
| -- simulation
|    |-- ModelSim
|       |   `-- cmd.do				-->	modelsim仿真脚本
|       |   `-- data.dat
|    |-- VCS
|       |   `-- makefile			-->	vcs仿真脚本
|       |   `-- data.dat
| -- tb
|    `-- tb_mod.v					-->	modelsim仿真testbench
|    `-- tb_vcs.v					-->	vcs仿真testbench
|    `-- prim_sim.v				    -->	仿真原语库

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使用说明：
	1、板测：使用云源软件打开上述文件中fpga_project.gprj，设置工程顶层模块，综合；根据所使用器件设置约束和gao.v后布局布线后下载测试。使用GAO抓取数据。
	2、modelsim仿真：仿真脚本存放于Modelsim文件夹中
	3、VCS仿真：仿真脚本存放于VCS文件夹中

	注：tb文件夹下prim_sim.v仅供参考，建议用户根据情况在仿真时使用最新版替换。

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        Example Gowin_Black_Level_Correction Design Readme
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Object device：GW2A-LV18PG256C8/I7
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File List:
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.
| -- docs
|    `-- readme.txt				-->	Read Me file (this file)
| -- project
|    |	`-- fpga_project.gprj		-->	GOWIN FPGA Designer project File for Example Design
|    |-- src
|      	|  `-- BLC_exp.v			-->	File for GOWIN FPGA Designer Project
|      	|  `-- demo.cst
|      	|  `-- fpga_project.rao
|      	|  `-- fpga_project.sdc
|       |   -- black_level_correction
|        	|   `-- black_level_correction.ipc
|        	|   `-- black_level_correction.v
|        	|   `-- black_level_correction.vo	    -->	Verilog simulation File for tb
|    |-- impl
| -- simulation
|    |-- ModelSim
|       |   `-- cmd.do				-->	modelsim simulation script
|       |   `-- data.dat
|    |-- VCS
|       |   `-- makefile			-->	vcs simulation script
|       |   `-- data.dat
| -- tb
|    `-- tb_mod.v					-->	TestBench for modelsim simulation
|    `-- tb_vcs.v					-->	TestBench for vcs simulation
|    `-- prim_sim.v				    -->	Verilog functional simulation library

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Instructions:
	1、Onboard test:Launch Gowin and select "File -> Open -> Project", set Top Module and Include Path. After Sythesize, cofigure Physical Constraints and GAO Config Files.
	2、modelsim simulation:Use script in Modelsim folder.
	3、VCS simulation:Use script in VCS folder.

	Note: The prim_sim.v under the tb folder is for reference only. It is recommended that users replace it with the latest version during simulation.
