Attention:
	1. if you reconfig the ip parameters,which reload the uhs_psram_memory_interface_v2.ipc and re-generator. 
	   please attention bits width of the top.v, tb.v, test.v file. for example, in the tb.v:
	   	O_ck,IO_dqs, IO_dq......

	   int the top.v file:
	   O_apsram_ck, IO_apsram_dqs, IO_apsram_dq, O_apsram_cs_n...........

	2. for simulation, please in the../../project/fpga_project/src/top.v file,open below:
	   `define SIM
	   for board test, please in the../../project/fpga_project/src/top.v file,close below:
	   `define SIM

../project/src/*.v : 
                        test design for uhs_psram_memory_interface_v2 ip
../project/src/uhs_psram_memory_interface_v2/uhs_psram_memory_interface_v2.vo :
                        uhs_psram_memory_interface_v2 IP
../tb/tb.v :
                        testbench for simulation
prim_sim.v:             simulation library