Timing Messages

Report Title	Timing Analysis Report
Design File	E:\memory\apm26408a\Gowin_UHS_PSRAM_Memory_Interface_refDesign\UHS_PSRAM_V2.0_64Mbit\project\fpga_project\impl\gwsynthesis\fpga_project.vg
Physical Constraints File	E:\memory\apm26408a\Gowin_UHS_PSRAM_Memory_Interface_refDesign\UHS_PSRAM_V2.0_64Mbit\project\fpga_project\src\fpga_project.cst
Timing Constraint File	E:\memory\apm26408a\Gowin_UHS_PSRAM_Memory_Interface_refDesign\UHS_PSRAM_V2.0_64Mbit\project\fpga_project\src\fpga_project.sdc
Tool Version	V1.9.10.01 (64-bit)
Part Number	GW5AR-LV25UG256PC2/I1
Device	GW5AR-25
Device Version	A
Created Time	Thu Aug 8 18:54:23 2024
Legal Announcement	Copyright (C)2014-2024 Gowin Semiconductor Corporation. All rights reserved.

Timing Summaries

STA Tool Run Summary:

Setup Delay Model	Slow 0.855V 0C C2/I1
Hold Delay Model	Fast 0.945V 85C C2/I1
Numbers of Paths Analyzed	9337
Numbers of Endpoints Analyzed	8328
Numbers of Falling Endpoints	0
Numbers of Setup Violated Endpoints	0
Numbers of Hold Violated Endpoints	0

Clock Summary:

NO.	Clock Name	Type	Period	Frequency(MHz)	Rise	Fall	Source	Master	Objects
1	clkin	Base	20.000	50.000	0.000	10.000			clk
2	mem_clk	Base	2.500	400.000	0.000	1.250			memory_clk
3	userclk	Generated	10.000	100.000	0.000	5.000	memory_clk	mem_clk	inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT

Max Frequency Summary:

NO.	Clock Name	Constraint	Actual Fmax	Logic Level	Entity
1	clkin	50.000(MHz)	296.780(MHz)	5	TOP
2	mem_clk	400.000(MHz)	2338.895(MHz)	1	TOP
3	userclk	100.000(MHz)	132.503(MHz)	4	TOP

Total Negative Slack Summary:

Clock Name	Analysis Type	Endpoints TNS	Number of Endpoints
clkin	Setup	0.000	0
clkin	Hold	0.000	0
mem_clk	Setup	0.000	0
mem_clk	Hold	0.000	0
userclk	Setup	0.000	0
userclk	Hold	0.000	0

Timing Details

Path Slacks Table:

Setup Paths Table

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	2.072	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_dqs/RPOINT[2]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[7].u_ides8_mem/RADDR[2]	mem_clk:[R]	mem_clk:[R]	2.500	0.000	0.428
2	2.072	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_dqs/RPOINT[1]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[7].u_ides8_mem/RADDR[1]	mem_clk:[R]	mem_clk:[R]	2.500	0.000	0.428
3	2.072	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_dqs/RPOINT[0]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[7].u_ides8_mem/RADDR[0]	mem_clk:[R]	mem_clk:[R]	2.500	0.000	0.428
4	2.072	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_dqs/RPOINT[2]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[6].u_ides8_mem/RADDR[2]	mem_clk:[R]	mem_clk:[R]	2.500	0.000	0.428
5	2.072	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_dqs/RPOINT[1]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[6].u_ides8_mem/RADDR[1]	mem_clk:[R]	mem_clk:[R]	2.500	0.000	0.428
6	2.072	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_dqs/RPOINT[0]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[6].u_ides8_mem/RADDR[0]	mem_clk:[R]	mem_clk:[R]	2.500	0.000	0.428
7	2.072	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_dqs/RPOINT[2]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[5].u_ides8_mem/RADDR[2]	mem_clk:[R]	mem_clk:[R]	2.500	0.000	0.428
8	2.072	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_dqs/RPOINT[1]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[5].u_ides8_mem/RADDR[1]	mem_clk:[R]	mem_clk:[R]	2.500	0.000	0.428
9	2.072	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_dqs/RPOINT[0]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[5].u_ides8_mem/RADDR[0]	mem_clk:[R]	mem_clk:[R]	2.500	0.000	0.428
10	2.072	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_dqs/RPOINT[2]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[4].u_ides8_mem/RADDR[2]	mem_clk:[R]	mem_clk:[R]	2.500	0.000	0.428
11	2.072	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_dqs/RPOINT[1]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[4].u_ides8_mem/RADDR[1]	mem_clk:[R]	mem_clk:[R]	2.500	0.000	0.428
12	2.072	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_dqs/RPOINT[0]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[4].u_ides8_mem/RADDR[0]	mem_clk:[R]	mem_clk:[R]	2.500	0.000	0.428
13	2.072	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_dqs/RPOINT[2]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[3].u_ides8_mem/RADDR[2]	mem_clk:[R]	mem_clk:[R]	2.500	0.000	0.428
14	2.072	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_dqs/RPOINT[1]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[3].u_ides8_mem/RADDR[1]	mem_clk:[R]	mem_clk:[R]	2.500	0.000	0.428
15	2.072	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_dqs/RPOINT[0]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[3].u_ides8_mem/RADDR[0]	mem_clk:[R]	mem_clk:[R]	2.500	0.000	0.428
16	2.072	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_dqs/RPOINT[2]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[2].u_ides8_mem/RADDR[2]	mem_clk:[R]	mem_clk:[R]	2.500	0.000	0.428
17	2.072	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_dqs/RPOINT[1]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[2].u_ides8_mem/RADDR[1]	mem_clk:[R]	mem_clk:[R]	2.500	0.000	0.428
18	2.072	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_dqs/RPOINT[0]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[2].u_ides8_mem/RADDR[0]	mem_clk:[R]	mem_clk:[R]	2.500	0.000	0.428
19	2.072	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_dqs/RPOINT[2]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[1].u_ides8_mem/RADDR[2]	mem_clk:[R]	mem_clk:[R]	2.500	0.000	0.428
20	2.072	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_dqs/RPOINT[1]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[1].u_ides8_mem/RADDR[1]	mem_clk:[R]	mem_clk:[R]	2.500	0.000	0.428
21	2.072	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_dqs/RPOINT[0]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[1].u_ides8_mem/RADDR[0]	mem_clk:[R]	mem_clk:[R]	2.500	0.000	0.428
22	2.072	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_dqs/RPOINT[2]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[0].u_ides8_mem/RADDR[2]	mem_clk:[R]	mem_clk:[R]	2.500	0.000	0.428
23	2.072	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_dqs/RPOINT[1]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[0].u_ides8_mem/RADDR[1]	mem_clk:[R]	mem_clk:[R]	2.500	0.000	0.428
24	2.072	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_dqs/RPOINT[0]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[0].u_ides8_mem/RADDR[0]	mem_clk:[R]	mem_clk:[R]	2.500	0.000	0.428
25	2.072	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[0].u_apm64_data_lane/u_dqs/RPOINT[2]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[0].u_apm64_data_lane/iserdes_gen[7].u_ides8_mem/RADDR[2]	mem_clk:[R]	mem_clk:[R]	2.500	0.000	0.428

Hold Paths Table

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	0.157	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[0].u_apm64_data_lane/dqs_dx_1_s0/Q	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_dqs_gen/D2	userclk:[R]	userclk:[R]	0.000	-0.002	0.241
2	0.157	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[0].u_apm64_data_lane/dqs_dx_1_s0/Q	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_dqs_gen/D0	userclk:[R]	userclk:[R]	0.000	-0.002	0.241
3	0.166	u_test/error_int1_3_s0/Q	led_1_s2/D	userclk:[R]	clkin:[R]	0.000	-0.575	0.801
4	0.275	u_test/wcnt_4_s1/Q	u_test/wcnt_4_s1/D	userclk:[R]	userclk:[R]	0.000	0.000	0.300
5	0.275	inst_apm64_top/u_apm64_top/u_apsram_ctrl/ctrl_cnt_1_s0/Q	inst_apm64_top/u_apm64_top/u_apsram_ctrl/ctrl_cnt_1_s0/D	userclk:[R]	userclk:[R]	0.000	0.000	0.300
6	0.275	inst_apm64_top/u_apm64_top/u_apsram_ctrl/tXHS_cnt_13_s0/Q	inst_apm64_top/u_apm64_top/u_apsram_ctrl/tXHS_cnt_13_s0/D	userclk:[R]	userclk:[R]	0.000	0.000	0.300
7	0.275	inst_apm64_top/u_apm64_top/u_apsram_init/readback_check_0_s26/Q	inst_apm64_top/u_apm64_top/u_apsram_init/readback_check_0_s26/D	userclk:[R]	userclk:[R]	0.000	0.000	0.300
8	0.275	inst_apm64_top/u_apm64_top/u_apsram_init/rclk_sel_reg_4_s1/Q	inst_apm64_top/u_apm64_top/u_apsram_init/rclk_sel_reg_4_s1/D	userclk:[R]	userclk:[R]	0.000	0.000	0.300
9	0.275	inst_apm64_top/u_apm64_top/u_apsram_init/rmove_cnt_9_s1/Q	inst_apm64_top/u_apm64_top/u_apsram_init/rmove_cnt_9_s1/D	userclk:[R]	userclk:[R]	0.000	0.000	0.300
10	0.275	inst_apm64_top/u_apm64_top/u_apsram_init/rdback_check_cnt_2_s1/Q	inst_apm64_top/u_apm64_top/u_apsram_init/rdback_check_cnt_2_s1/D	userclk:[R]	userclk:[R]	0.000	0.000	0.300
11	0.275	inst_apm64_top/u_apm64_top/u_apsram_init/tRST_cnt_2_s0/Q	inst_apm64_top/u_apm64_top/u_apsram_init/tRST_cnt_2_s0/D	userclk:[R]	userclk:[R]	0.000	0.000	0.300
12	0.275	inst_apm64_top/u_apm64_top/u_apsram_ctrl/ctrl_tRFC_done_s6/Q	inst_apm64_top/u_apm64_top/u_apsram_ctrl/ctrl_tRFC_done_s6/D	userclk:[R]	userclk:[R]	0.000	0.000	0.300
13	0.275	inst_apm64_top/u_apm64_top/u_apsram_ctrl/tcphr_cnt_3_s1/Q	inst_apm64_top/u_apm64_top/u_apsram_ctrl/tcphr_cnt_3_s1/D	userclk:[R]	userclk:[R]	0.000	0.000	0.300
14	0.275	inst_apm64_top/u_apm64_top/u_apsram_ctrl/tcphr_cnt_6_s1/Q	inst_apm64_top/u_apm64_top/u_apsram_ctrl/tcphr_cnt_6_s1/D	userclk:[R]	userclk:[R]	0.000	0.000	0.300
15	0.275	inst_apm64_top/u_apm64_top/u_apsram_ctrl/prescaler_cnt_0_s0/Q	inst_apm64_top/u_apm64_top/u_apsram_ctrl/prescaler_cnt_0_s0/D	userclk:[R]	userclk:[R]	0.000	0.000	0.300
16	0.275	inst_apm64_top/u_apm64_top/u_apsram_ctrl/ctrl_cnt_7_s0/Q	inst_apm64_top/u_apm64_top/u_apsram_ctrl/ctrl_cnt_7_s0/D	userclk:[R]	userclk:[R]	0.000	0.000	0.300
17	0.275	inst_apm64_top/u_apm64_top/u_apsram_ctrl/rw_burst_cnt_2_s0/Q	inst_apm64_top/u_apm64_top/u_apsram_ctrl/rw_burst_cnt_2_s0/D	userclk:[R]	userclk:[R]	0.000	0.000	0.300
18	0.275	inst_apm64_top/u_apm64_top/u_apsram_ctrl/c_state.CMDR_WAITE_s0/Q	inst_apm64_top/u_apm64_top/u_apsram_ctrl/c_state.CMDR_WAITE_s0/D	userclk:[R]	userclk:[R]	0.000	0.000	0.300
19	0.275	inst_apm64_top/u_apm64_top/u_apsram_ctrl/tXPHS_cnt_2_s0/Q	inst_apm64_top/u_apm64_top/u_apsram_ctrl/tXPHS_cnt_2_s0/D	userclk:[R]	userclk:[R]	0.000	0.000	0.300
20	0.275	inst_apm64_top/u_apm64_top/u_apsram_ctrl/tHS_cnt_2_s0/Q	inst_apm64_top/u_apm64_top/u_apsram_ctrl/tHS_cnt_2_s0/D	userclk:[R]	userclk:[R]	0.000	0.000	0.300
21	0.275	inst_apm64_top/u_apm64_top/u_apsram_ctrl/tHS_cnt_3_s0/Q	inst_apm64_top/u_apm64_top/u_apsram_ctrl/tHS_cnt_3_s0/D	userclk:[R]	userclk:[R]	0.000	0.000	0.300
22	0.275	inst_apm64_top/u_apm64_top/u_apsram_ctrl/tHS_cnt_7_s0/Q	inst_apm64_top/u_apm64_top/u_apsram_ctrl/tHS_cnt_7_s0/D	userclk:[R]	userclk:[R]	0.000	0.000	0.300
23	0.275	inst_apm64_top/u_apm64_top/u_apsram_ctrl/tHS_cnt_8_s0/Q	inst_apm64_top/u_apm64_top/u_apsram_ctrl/tHS_cnt_8_s0/D	userclk:[R]	userclk:[R]	0.000	0.000	0.300
24	0.275	inst_apm64_top/u_apm64_top/u_apsram_ctrl/tXSR_cnt_1_s0/Q	inst_apm64_top/u_apm64_top/u_apsram_ctrl/tXSR_cnt_1_s0/D	userclk:[R]	userclk:[R]	0.000	0.000	0.300
25	0.275	inst_apm64_top/u_apm64_top/u_cmd_fifo/addr_2_s1/Q	inst_apm64_top/u_apm64_top/u_cmd_fifo/addr_2_s1/D	userclk:[R]	userclk:[R]	0.000	0.000	0.300

Recovery Paths Table

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	4.993	inst_apm64_top/u_apm64_top/u_apsram_sync/dll_rst_s0/Q	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[0].u_apm64_data_lane/u_dqs/RESET	clkin:[R]	userclk:[R]	10.000	0.594	3.948
2	5.008	inst_apm64_top/u_apm64_top/u_apsram_sync/dll_rst_s0/Q	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_dqs/RESET	clkin:[R]	userclk:[R]	10.000	0.579	3.948
3	5.132	inst_apm64_top/u_apm64_top/u_apsram_sync/dll_rst_s0/Q	inst_apm64_top/u_apm64_top/u_apsram_init/timer_cnt0_4_s3/CLEAR	clkin:[R]	userclk:[R]	10.000	0.638	3.917
4	5.132	inst_apm64_top/u_apm64_top/u_apsram_sync/dll_rst_s0/Q	inst_apm64_top/u_apm64_top/u_apsram_init/rdback_check_cnt_5_s1/CLEAR	clkin:[R]	userclk:[R]	10.000	0.638	3.917
5	5.132	inst_apm64_top/u_apm64_top/u_apsram_sync/dll_rst_s0/Q	inst_apm64_top/u_apm64_top/u_apsram_init/timer_cnt0_3_s1/CLEAR	clkin:[R]	userclk:[R]	10.000	0.638	3.917
6	5.132	inst_apm64_top/u_apm64_top/u_apsram_sync/dll_rst_s0/Q	inst_apm64_top/u_apm64_top/u_apsram_init/timer_cnt0_5_s1/CLEAR	clkin:[R]	userclk:[R]	10.000	0.638	3.917
7	5.132	inst_apm64_top/u_apm64_top/u_apsram_sync/dll_rst_s0/Q	inst_apm64_top/u_apm64_top/u_apsram_init/write_done_s0/CLEAR	clkin:[R]	userclk:[R]	10.000	0.638	3.917
8	5.132	inst_apm64_top/u_apm64_top/u_apsram_sync/dll_rst_s0/Q	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/of_RdData_reg_10_s0/CLEAR	clkin:[R]	userclk:[R]	10.000	0.638	3.917
9	5.132	inst_apm64_top/u_apm64_top/u_apsram_sync/dll_rst_s0/Q	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/of_RdData_reg_18_s0/CLEAR	clkin:[R]	userclk:[R]	10.000	0.633	3.922
10	5.132	inst_apm64_top/u_apm64_top/u_apsram_sync/dll_rst_s0/Q	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/of_RdData_reg_25_s0/CLEAR	clkin:[R]	userclk:[R]	10.000	0.633	3.922
11	5.132	inst_apm64_top/u_apm64_top/u_apsram_sync/dll_rst_s0/Q	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/wr_dq_r_14_s0/CLEAR	clkin:[R]	userclk:[R]	10.000	0.638	3.917
12	5.132	inst_apm64_top/u_apm64_top/u_apsram_sync/dll_rst_s0/Q	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/wr_dq_r_15_s0/CLEAR	clkin:[R]	userclk:[R]	10.000	0.638	3.917
13	5.132	inst_apm64_top/u_apm64_top/u_apsram_sync/dll_rst_s0/Q	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/wr_dq_r_22_s0/CLEAR	clkin:[R]	userclk:[R]	10.000	0.633	3.922
14	5.132	inst_apm64_top/u_apm64_top/u_apsram_sync/dll_rst_s0/Q	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/wr_dq_r_29_s0/CLEAR	clkin:[R]	userclk:[R]	10.000	0.633	3.922
15	5.132	inst_apm64_top/u_apm64_top/u_apsram_sync/dll_rst_s0/Q	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/wr_dq_15_s0/CLEAR	clkin:[R]	userclk:[R]	10.000	0.638	3.917
16	5.132	inst_apm64_top/u_apm64_top/u_apsram_sync/dll_rst_s0/Q	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/wr_dq_22_s0/CLEAR	clkin:[R]	userclk:[R]	10.000	0.633	3.922
17	5.132	inst_apm64_top/u_apm64_top/u_apsram_sync/dll_rst_s0/Q	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/wr_dq_29_s0/CLEAR	clkin:[R]	userclk:[R]	10.000	0.633	3.922
18	5.132	inst_apm64_top/u_apm64_top/u_apsram_sync/dll_rst_s0/Q	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/wr_dq_d1_15_s0/CLEAR	clkin:[R]	userclk:[R]	10.000	0.638	3.917
19	5.132	inst_apm64_top/u_apm64_top/u_apsram_sync/dll_rst_s0/Q	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/wr_dq_d1_22_s0/CLEAR	clkin:[R]	userclk:[R]	10.000	0.633	3.922
20	5.132	inst_apm64_top/u_apm64_top/u_apsram_sync/dll_rst_s0/Q	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/wr_dq_d1_29_s0/CLEAR	clkin:[R]	userclk:[R]	10.000	0.633	3.922
21	5.132	inst_apm64_top/u_apm64_top/u_apsram_sync/dll_rst_s0/Q	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/wr_dq_d_14_s0/CLEAR	clkin:[R]	userclk:[R]	10.000	0.638	3.917
22	5.132	inst_apm64_top/u_apm64_top/u_apsram_sync/dll_rst_s0/Q	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/wr_dq_d_15_s0/CLEAR	clkin:[R]	userclk:[R]	10.000	0.638	3.917
23	5.132	inst_apm64_top/u_apm64_top/u_apsram_sync/dll_rst_s0/Q	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/wr_dq_d_22_s0/CLEAR	clkin:[R]	userclk:[R]	10.000	0.633	3.922
24	5.132	inst_apm64_top/u_apm64_top/u_apsram_sync/dll_rst_s0/Q	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/wr_dq_d_29_s0/CLEAR	clkin:[R]	userclk:[R]	10.000	0.633	3.922
25	5.132	inst_apm64_top/u_apm64_top/u_apsram_sync/dll_rst_s0/Q	inst_apm64_top/u_apm64_top/rdbk_data_71_s1/CLEAR	clkin:[R]	userclk:[R]	10.000	0.638	3.917

Removal Paths Table

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	1.215	u_reset_key/key_1_s0/Q	cnt_7_s0/CLEAR	clkin:[R]	clkin:[R]	0.000	0.013	1.149
2	1.215	u_reset_key/key_1_s0/Q	cnt_8_s0/CLEAR	clkin:[R]	clkin:[R]	0.000	0.013	1.149
3	1.215	u_reset_key/key_1_s0/Q	cnt_9_s0/CLEAR	clkin:[R]	clkin:[R]	0.000	0.013	1.149
4	1.215	u_reset_key/key_1_s0/Q	cnt_10_s0/CLEAR	clkin:[R]	clkin:[R]	0.000	0.013	1.149
5	1.215	u_reset_key/key_1_s0/Q	cnt_11_s0/CLEAR	clkin:[R]	clkin:[R]	0.000	0.013	1.149
6	1.215	u_reset_key/key_1_s0/Q	cnt_12_s0/CLEAR	clkin:[R]	clkin:[R]	0.000	0.013	1.149
7	1.215	u_reset_key/key_1_s0/Q	inst_apm64_top/u_apm64_top/u_apsram_sync/flag_0_s4/CLEAR	clkin:[R]	clkin:[R]	0.000	0.027	1.135
8	1.215	u_reset_key/key_1_s0/Q	inst_apm64_top/u_apm64_top/u_apsram_sync/cs_memsync_4_s0/CLEAR	clkin:[R]	clkin:[R]	0.000	0.027	1.135
9	1.219	u_reset_key/key_1_s0/Q	cnt_1_s0/CLEAR	clkin:[R]	clkin:[R]	0.000	0.017	1.149
10	1.219	u_reset_key/key_1_s0/Q	cnt_2_s0/CLEAR	clkin:[R]	clkin:[R]	0.000	0.017	1.149
11	1.219	u_reset_key/key_1_s0/Q	cnt_3_s0/CLEAR	clkin:[R]	clkin:[R]	0.000	0.017	1.149
12	1.219	u_reset_key/key_1_s0/Q	cnt_4_s0/CLEAR	clkin:[R]	clkin:[R]	0.000	0.017	1.149
13	1.219	u_reset_key/key_1_s0/Q	cnt_5_s0/CLEAR	clkin:[R]	clkin:[R]	0.000	0.017	1.149
14	1.219	u_reset_key/key_1_s0/Q	cnt_6_s0/CLEAR	clkin:[R]	clkin:[R]	0.000	0.017	1.149
15	1.219	u_reset_key/key_1_s0/Q	cnt_13_s0/CLEAR	clkin:[R]	clkin:[R]	0.000	0.017	1.149
16	1.219	u_reset_key/key_1_s0/Q	cnt_14_s0/CLEAR	clkin:[R]	clkin:[R]	0.000	0.017	1.149
17	1.219	u_reset_key/key_1_s0/Q	cnt_15_s0/CLEAR	clkin:[R]	clkin:[R]	0.000	0.017	1.149
18	1.219	u_reset_key/key_1_s0/Q	cnt_16_s0/CLEAR	clkin:[R]	clkin:[R]	0.000	0.017	1.149
19	1.219	u_reset_key/key_1_s0/Q	cnt_17_s0/CLEAR	clkin:[R]	clkin:[R]	0.000	0.017	1.149
20	1.219	u_reset_key/key_1_s0/Q	cnt_18_s0/CLEAR	clkin:[R]	clkin:[R]	0.000	0.017	1.149
21	1.219	u_reset_key/key_1_s0/Q	cnt_0_s0/CLEAR	clkin:[R]	clkin:[R]	0.000	0.012	1.154
22	1.222	u_reset_key/key_1_s0/Q	inst_apm64_top/u_apm64_top/u_apsram_sync/lock_cnt_1_s3/CLEAR	clkin:[R]	clkin:[R]	0.000	-0.002	1.171
23	1.222	u_reset_key/key_1_s0/Q	inst_apm64_top/u_apm64_top/u_apsram_sync/lock_cnt_4_s3/CLEAR	clkin:[R]	clkin:[R]	0.000	0.003	1.166
24	1.222	u_reset_key/key_1_s0/Q	inst_apm64_top/u_apm64_top/u_apsram_sync/lock_cnt_7_s3/CLEAR	clkin:[R]	clkin:[R]	0.000	-0.002	1.171
25	1.222	u_reset_key/key_1_s0/Q	inst_apm64_top/u_apm64_top/u_apsram_sync/lock_cnt_10_s3/CLEAR	clkin:[R]	clkin:[R]	0.000	-0.002	1.171

Minimum Pulse Width Table:

Report Command:report_min_pulse_width -nworst 10 -detail

Number	Slack	Actual Width	Required Width	Type	Clock	Objects
1	3.290	4.152	0.862	Low Pulse Width	userclk	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[0].u_apm64_data_lane/u_out_fifo/mem2_mem2_0_1_s
2	3.290	4.152	0.862	Low Pulse Width	userclk	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[0].u_apm64_data_lane/u_in_fifo/mem0_mem0_0_0_s
3	3.290	4.152	0.862	Low Pulse Width	userclk	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[0].u_apm64_data_lane/u_in_fifo/mem0_mem0_0_1_s
4	3.290	4.152	0.862	Low Pulse Width	userclk	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_out_fifo/mem2_mem2_0_0_s
5	3.290	4.152	0.862	Low Pulse Width	userclk	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_in_fifo/mem0_mem0_0_0_s
6	3.290	4.152	0.862	Low Pulse Width	userclk	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[0].u_apm64_data_lane/u_out_fifo/gowin_add_SDPX9B_mem2_mem2_0_0_s
7	3.290	4.152	0.862	Low Pulse Width	userclk	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_out_fifo/gowin_add_SDPX9B_mem2_mem2_0_1_s
8	3.290	4.152	0.862	Low Pulse Width	userclk	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_in_fifo/gowin_add_SDPB_mem0_mem0_0_1_s
9	3.292	4.154	0.862	High Pulse Width	userclk	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[0].u_apm64_data_lane/u_out_fifo/mem2_mem2_0_1_s
10	3.292	4.154	0.862	High Pulse Width	userclk	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[0].u_apm64_data_lane/u_in_fifo/mem0_mem0_0_0_s

Timing Report By Analysis Type:

Setup Analysis Report

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	2.072
Data Arrival Time	0.937
Data Required Time	3.010
From	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_dqs
To	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[7].u_ides8_mem
Launch Clk	mem_clk:[R]
Latch Clk	mem_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					mem_clk
0.000	0.000	tCL	RR	1	PLL_R[0]	u_Gowin_PLL/PLLA_inst/CLKOUT0
0.000	0.000	tNET	RR	3	-	inst_apm64_top/u_apm64_top/u_dqce_clk_x4/CLKIN
0.157	0.157	tINS	RR	44	-	inst_apm64_top/u_apm64_top/u_dqce_clk_x4/CLKOUT
0.510	0.353	tNET	RR	5	R0C60	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_dqs/FCLK
0.937	0.428	tC2Q	RF	8	R0C60	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_dqs/RPOINT[2]
0.937	0.000	tNET	FF	1	IOT70[B]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[7].u_ides8_mem/RADDR[2]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
2.500	2.500					active clock edge time
2.500	0.000					mem_clk
2.500	0.000	tCL	RR	1	PLL_R[0]	u_Gowin_PLL/PLLA_inst/CLKOUT0
2.500	0.000	tNET	RR	3	-	inst_apm64_top/u_apm64_top/u_dqce_clk_x4/CLKIN
2.657	0.157	tINS	RR	44	-	inst_apm64_top/u_apm64_top/u_dqce_clk_x4/CLKOUT
3.010	0.353	tNET	RR	1	IOT70[B]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[7].u_ides8_mem/FCLK
3.010	0.000	tSu		1	IOT70[B]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[7].u_ides8_mem

Path Statistics:

Clock Skew	0.000
Setup Relationship	2.500
Logic Level	1
Arrival Clock Path Delay	cell: 0.157, 30.769%; route: 0.353, 69.231%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.428, 100.000%
Required Clock Path Delay	cell: 0.157, 30.769%; route: 0.353, 69.231%

Path2

Path Summary:

Slack	2.072
Data Arrival Time	0.937
Data Required Time	3.010
From	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_dqs
To	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[7].u_ides8_mem
Launch Clk	mem_clk:[R]
Latch Clk	mem_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					mem_clk
0.000	0.000	tCL	RR	1	PLL_R[0]	u_Gowin_PLL/PLLA_inst/CLKOUT0
0.000	0.000	tNET	RR	3	-	inst_apm64_top/u_apm64_top/u_dqce_clk_x4/CLKIN
0.157	0.157	tINS	RR	44	-	inst_apm64_top/u_apm64_top/u_dqce_clk_x4/CLKOUT
0.510	0.353	tNET	RR	5	R0C60	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_dqs/FCLK
0.937	0.428	tC2Q	RF	8	R0C60	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_dqs/RPOINT[1]
0.937	0.000	tNET	FF	1	IOT70[B]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[7].u_ides8_mem/RADDR[1]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
2.500	2.500					active clock edge time
2.500	0.000					mem_clk
2.500	0.000	tCL	RR	1	PLL_R[0]	u_Gowin_PLL/PLLA_inst/CLKOUT0
2.500	0.000	tNET	RR	3	-	inst_apm64_top/u_apm64_top/u_dqce_clk_x4/CLKIN
2.657	0.157	tINS	RR	44	-	inst_apm64_top/u_apm64_top/u_dqce_clk_x4/CLKOUT
3.010	0.353	tNET	RR	1	IOT70[B]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[7].u_ides8_mem/FCLK
3.010	0.000	tSu		1	IOT70[B]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[7].u_ides8_mem

Path Statistics:

Clock Skew	0.000
Setup Relationship	2.500
Logic Level	1
Arrival Clock Path Delay	cell: 0.157, 30.769%; route: 0.353, 69.231%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.428, 100.000%
Required Clock Path Delay	cell: 0.157, 30.769%; route: 0.353, 69.231%

Path3

Path Summary:

Slack	2.072
Data Arrival Time	0.937
Data Required Time	3.010
From	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_dqs
To	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[7].u_ides8_mem
Launch Clk	mem_clk:[R]
Latch Clk	mem_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					mem_clk
0.000	0.000	tCL	RR	1	PLL_R[0]	u_Gowin_PLL/PLLA_inst/CLKOUT0
0.000	0.000	tNET	RR	3	-	inst_apm64_top/u_apm64_top/u_dqce_clk_x4/CLKIN
0.157	0.157	tINS	RR	44	-	inst_apm64_top/u_apm64_top/u_dqce_clk_x4/CLKOUT
0.510	0.353	tNET	RR	5	R0C60	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_dqs/FCLK
0.937	0.428	tC2Q	RF	8	R0C60	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_dqs/RPOINT[0]
0.937	0.000	tNET	FF	1	IOT70[B]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[7].u_ides8_mem/RADDR[0]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
2.500	2.500					active clock edge time
2.500	0.000					mem_clk
2.500	0.000	tCL	RR	1	PLL_R[0]	u_Gowin_PLL/PLLA_inst/CLKOUT0
2.500	0.000	tNET	RR	3	-	inst_apm64_top/u_apm64_top/u_dqce_clk_x4/CLKIN
2.657	0.157	tINS	RR	44	-	inst_apm64_top/u_apm64_top/u_dqce_clk_x4/CLKOUT
3.010	0.353	tNET	RR	1	IOT70[B]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[7].u_ides8_mem/FCLK
3.010	0.000	tSu		1	IOT70[B]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[7].u_ides8_mem

Path Statistics:

Clock Skew	0.000
Setup Relationship	2.500
Logic Level	1
Arrival Clock Path Delay	cell: 0.157, 30.769%; route: 0.353, 69.231%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.428, 100.000%
Required Clock Path Delay	cell: 0.157, 30.769%; route: 0.353, 69.231%

Path4

Path Summary:

Slack	2.072
Data Arrival Time	0.937
Data Required Time	3.010
From	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_dqs
To	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[6].u_ides8_mem
Launch Clk	mem_clk:[R]
Latch Clk	mem_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					mem_clk
0.000	0.000	tCL	RR	1	PLL_R[0]	u_Gowin_PLL/PLLA_inst/CLKOUT0
0.000	0.000	tNET	RR	3	-	inst_apm64_top/u_apm64_top/u_dqce_clk_x4/CLKIN
0.157	0.157	tINS	RR	44	-	inst_apm64_top/u_apm64_top/u_dqce_clk_x4/CLKOUT
0.510	0.353	tNET	RR	5	R0C60	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_dqs/FCLK
0.937	0.428	tC2Q	RF	8	R0C60	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_dqs/RPOINT[2]
0.937	0.000	tNET	FF	1	IOT70[A]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[6].u_ides8_mem/RADDR[2]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
2.500	2.500					active clock edge time
2.500	0.000					mem_clk
2.500	0.000	tCL	RR	1	PLL_R[0]	u_Gowin_PLL/PLLA_inst/CLKOUT0
2.500	0.000	tNET	RR	3	-	inst_apm64_top/u_apm64_top/u_dqce_clk_x4/CLKIN
2.657	0.157	tINS	RR	44	-	inst_apm64_top/u_apm64_top/u_dqce_clk_x4/CLKOUT
3.010	0.353	tNET	RR	1	IOT70[A]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[6].u_ides8_mem/FCLK
3.010	0.000	tSu		1	IOT70[A]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[6].u_ides8_mem

Path Statistics:

Clock Skew	0.000
Setup Relationship	2.500
Logic Level	1
Arrival Clock Path Delay	cell: 0.157, 30.769%; route: 0.353, 69.231%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.428, 100.000%
Required Clock Path Delay	cell: 0.157, 30.769%; route: 0.353, 69.231%

Path5

Path Summary:

Slack	2.072
Data Arrival Time	0.937
Data Required Time	3.010
From	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_dqs
To	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[6].u_ides8_mem
Launch Clk	mem_clk:[R]
Latch Clk	mem_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					mem_clk
0.000	0.000	tCL	RR	1	PLL_R[0]	u_Gowin_PLL/PLLA_inst/CLKOUT0
0.000	0.000	tNET	RR	3	-	inst_apm64_top/u_apm64_top/u_dqce_clk_x4/CLKIN
0.157	0.157	tINS	RR	44	-	inst_apm64_top/u_apm64_top/u_dqce_clk_x4/CLKOUT
0.510	0.353	tNET	RR	5	R0C60	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_dqs/FCLK
0.937	0.428	tC2Q	RF	8	R0C60	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_dqs/RPOINT[1]
0.937	0.000	tNET	FF	1	IOT70[A]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[6].u_ides8_mem/RADDR[1]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
2.500	2.500					active clock edge time
2.500	0.000					mem_clk
2.500	0.000	tCL	RR	1	PLL_R[0]	u_Gowin_PLL/PLLA_inst/CLKOUT0
2.500	0.000	tNET	RR	3	-	inst_apm64_top/u_apm64_top/u_dqce_clk_x4/CLKIN
2.657	0.157	tINS	RR	44	-	inst_apm64_top/u_apm64_top/u_dqce_clk_x4/CLKOUT
3.010	0.353	tNET	RR	1	IOT70[A]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[6].u_ides8_mem/FCLK
3.010	0.000	tSu		1	IOT70[A]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[6].u_ides8_mem

Path Statistics:

Clock Skew	0.000
Setup Relationship	2.500
Logic Level	1
Arrival Clock Path Delay	cell: 0.157, 30.769%; route: 0.353, 69.231%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.428, 100.000%
Required Clock Path Delay	cell: 0.157, 30.769%; route: 0.353, 69.231%

Path6

Path Summary:

Slack	2.072
Data Arrival Time	0.937
Data Required Time	3.010
From	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_dqs
To	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[6].u_ides8_mem
Launch Clk	mem_clk:[R]
Latch Clk	mem_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					mem_clk
0.000	0.000	tCL	RR	1	PLL_R[0]	u_Gowin_PLL/PLLA_inst/CLKOUT0
0.000	0.000	tNET	RR	3	-	inst_apm64_top/u_apm64_top/u_dqce_clk_x4/CLKIN
0.157	0.157	tINS	RR	44	-	inst_apm64_top/u_apm64_top/u_dqce_clk_x4/CLKOUT
0.510	0.353	tNET	RR	5	R0C60	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_dqs/FCLK
0.937	0.428	tC2Q	RF	8	R0C60	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_dqs/RPOINT[0]
0.937	0.000	tNET	FF	1	IOT70[A]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[6].u_ides8_mem/RADDR[0]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
2.500	2.500					active clock edge time
2.500	0.000					mem_clk
2.500	0.000	tCL	RR	1	PLL_R[0]	u_Gowin_PLL/PLLA_inst/CLKOUT0
2.500	0.000	tNET	RR	3	-	inst_apm64_top/u_apm64_top/u_dqce_clk_x4/CLKIN
2.657	0.157	tINS	RR	44	-	inst_apm64_top/u_apm64_top/u_dqce_clk_x4/CLKOUT
3.010	0.353	tNET	RR	1	IOT70[A]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[6].u_ides8_mem/FCLK
3.010	0.000	tSu		1	IOT70[A]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[6].u_ides8_mem

Path Statistics:

Clock Skew	0.000
Setup Relationship	2.500
Logic Level	1
Arrival Clock Path Delay	cell: 0.157, 30.769%; route: 0.353, 69.231%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.428, 100.000%
Required Clock Path Delay	cell: 0.157, 30.769%; route: 0.353, 69.231%

Path7

Path Summary:

Slack	2.072
Data Arrival Time	0.937
Data Required Time	3.010
From	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_dqs
To	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[5].u_ides8_mem
Launch Clk	mem_clk:[R]
Latch Clk	mem_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					mem_clk
0.000	0.000	tCL	RR	1	PLL_R[0]	u_Gowin_PLL/PLLA_inst/CLKOUT0
0.000	0.000	tNET	RR	3	-	inst_apm64_top/u_apm64_top/u_dqce_clk_x4/CLKIN
0.157	0.157	tINS	RR	44	-	inst_apm64_top/u_apm64_top/u_dqce_clk_x4/CLKOUT
0.510	0.353	tNET	RR	5	R0C60	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_dqs/FCLK
0.937	0.428	tC2Q	RF	8	R0C60	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_dqs/RPOINT[2]
0.937	0.000	tNET	FF	1	IOT68[B]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[5].u_ides8_mem/RADDR[2]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
2.500	2.500					active clock edge time
2.500	0.000					mem_clk
2.500	0.000	tCL	RR	1	PLL_R[0]	u_Gowin_PLL/PLLA_inst/CLKOUT0
2.500	0.000	tNET	RR	3	-	inst_apm64_top/u_apm64_top/u_dqce_clk_x4/CLKIN
2.657	0.157	tINS	RR	44	-	inst_apm64_top/u_apm64_top/u_dqce_clk_x4/CLKOUT
3.010	0.353	tNET	RR	1	IOT68[B]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[5].u_ides8_mem/FCLK
3.010	0.000	tSu		1	IOT68[B]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[5].u_ides8_mem

Path Statistics:

Clock Skew	0.000
Setup Relationship	2.500
Logic Level	1
Arrival Clock Path Delay	cell: 0.157, 30.769%; route: 0.353, 69.231%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.428, 100.000%
Required Clock Path Delay	cell: 0.157, 30.769%; route: 0.353, 69.231%

Path8

Path Summary:

Slack	2.072
Data Arrival Time	0.937
Data Required Time	3.010
From	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_dqs
To	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[5].u_ides8_mem
Launch Clk	mem_clk:[R]
Latch Clk	mem_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					mem_clk
0.000	0.000	tCL	RR	1	PLL_R[0]	u_Gowin_PLL/PLLA_inst/CLKOUT0
0.000	0.000	tNET	RR	3	-	inst_apm64_top/u_apm64_top/u_dqce_clk_x4/CLKIN
0.157	0.157	tINS	RR	44	-	inst_apm64_top/u_apm64_top/u_dqce_clk_x4/CLKOUT
0.510	0.353	tNET	RR	5	R0C60	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_dqs/FCLK
0.937	0.428	tC2Q	RF	8	R0C60	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_dqs/RPOINT[1]
0.937	0.000	tNET	FF	1	IOT68[B]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[5].u_ides8_mem/RADDR[1]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
2.500	2.500					active clock edge time
2.500	0.000					mem_clk
2.500	0.000	tCL	RR	1	PLL_R[0]	u_Gowin_PLL/PLLA_inst/CLKOUT0
2.500	0.000	tNET	RR	3	-	inst_apm64_top/u_apm64_top/u_dqce_clk_x4/CLKIN
2.657	0.157	tINS	RR	44	-	inst_apm64_top/u_apm64_top/u_dqce_clk_x4/CLKOUT
3.010	0.353	tNET	RR	1	IOT68[B]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[5].u_ides8_mem/FCLK
3.010	0.000	tSu		1	IOT68[B]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[5].u_ides8_mem

Path Statistics:

Clock Skew	0.000
Setup Relationship	2.500
Logic Level	1
Arrival Clock Path Delay	cell: 0.157, 30.769%; route: 0.353, 69.231%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.428, 100.000%
Required Clock Path Delay	cell: 0.157, 30.769%; route: 0.353, 69.231%

Path9

Path Summary:

Slack	2.072
Data Arrival Time	0.937
Data Required Time	3.010
From	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_dqs
To	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[5].u_ides8_mem
Launch Clk	mem_clk:[R]
Latch Clk	mem_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					mem_clk
0.000	0.000	tCL	RR	1	PLL_R[0]	u_Gowin_PLL/PLLA_inst/CLKOUT0
0.000	0.000	tNET	RR	3	-	inst_apm64_top/u_apm64_top/u_dqce_clk_x4/CLKIN
0.157	0.157	tINS	RR	44	-	inst_apm64_top/u_apm64_top/u_dqce_clk_x4/CLKOUT
0.510	0.353	tNET	RR	5	R0C60	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_dqs/FCLK
0.937	0.428	tC2Q	RF	8	R0C60	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_dqs/RPOINT[0]
0.937	0.000	tNET	FF	1	IOT68[B]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[5].u_ides8_mem/RADDR[0]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
2.500	2.500					active clock edge time
2.500	0.000					mem_clk
2.500	0.000	tCL	RR	1	PLL_R[0]	u_Gowin_PLL/PLLA_inst/CLKOUT0
2.500	0.000	tNET	RR	3	-	inst_apm64_top/u_apm64_top/u_dqce_clk_x4/CLKIN
2.657	0.157	tINS	RR	44	-	inst_apm64_top/u_apm64_top/u_dqce_clk_x4/CLKOUT
3.010	0.353	tNET	RR	1	IOT68[B]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[5].u_ides8_mem/FCLK
3.010	0.000	tSu		1	IOT68[B]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[5].u_ides8_mem

Path Statistics:

Clock Skew	0.000
Setup Relationship	2.500
Logic Level	1
Arrival Clock Path Delay	cell: 0.157, 30.769%; route: 0.353, 69.231%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.428, 100.000%
Required Clock Path Delay	cell: 0.157, 30.769%; route: 0.353, 69.231%

Path10

Path Summary:

Slack	2.072
Data Arrival Time	0.937
Data Required Time	3.010
From	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_dqs
To	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[4].u_ides8_mem
Launch Clk	mem_clk:[R]
Latch Clk	mem_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					mem_clk
0.000	0.000	tCL	RR	1	PLL_R[0]	u_Gowin_PLL/PLLA_inst/CLKOUT0
0.000	0.000	tNET	RR	3	-	inst_apm64_top/u_apm64_top/u_dqce_clk_x4/CLKIN
0.157	0.157	tINS	RR	44	-	inst_apm64_top/u_apm64_top/u_dqce_clk_x4/CLKOUT
0.510	0.353	tNET	RR	5	R0C60	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_dqs/FCLK
0.937	0.428	tC2Q	RF	8	R0C60	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_dqs/RPOINT[2]
0.937	0.000	tNET	FF	1	IOT68[A]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[4].u_ides8_mem/RADDR[2]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
2.500	2.500					active clock edge time
2.500	0.000					mem_clk
2.500	0.000	tCL	RR	1	PLL_R[0]	u_Gowin_PLL/PLLA_inst/CLKOUT0
2.500	0.000	tNET	RR	3	-	inst_apm64_top/u_apm64_top/u_dqce_clk_x4/CLKIN
2.657	0.157	tINS	RR	44	-	inst_apm64_top/u_apm64_top/u_dqce_clk_x4/CLKOUT
3.010	0.353	tNET	RR	1	IOT68[A]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[4].u_ides8_mem/FCLK
3.010	0.000	tSu		1	IOT68[A]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[4].u_ides8_mem

Path Statistics:

Clock Skew	0.000
Setup Relationship	2.500
Logic Level	1
Arrival Clock Path Delay	cell: 0.157, 30.769%; route: 0.353, 69.231%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.428, 100.000%
Required Clock Path Delay	cell: 0.157, 30.769%; route: 0.353, 69.231%

Path11

Path Summary:

Slack	2.072
Data Arrival Time	0.937
Data Required Time	3.010
From	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_dqs
To	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[4].u_ides8_mem
Launch Clk	mem_clk:[R]
Latch Clk	mem_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					mem_clk
0.000	0.000	tCL	RR	1	PLL_R[0]	u_Gowin_PLL/PLLA_inst/CLKOUT0
0.000	0.000	tNET	RR	3	-	inst_apm64_top/u_apm64_top/u_dqce_clk_x4/CLKIN
0.157	0.157	tINS	RR	44	-	inst_apm64_top/u_apm64_top/u_dqce_clk_x4/CLKOUT
0.510	0.353	tNET	RR	5	R0C60	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_dqs/FCLK
0.937	0.428	tC2Q	RF	8	R0C60	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_dqs/RPOINT[1]
0.937	0.000	tNET	FF	1	IOT68[A]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[4].u_ides8_mem/RADDR[1]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
2.500	2.500					active clock edge time
2.500	0.000					mem_clk
2.500	0.000	tCL	RR	1	PLL_R[0]	u_Gowin_PLL/PLLA_inst/CLKOUT0
2.500	0.000	tNET	RR	3	-	inst_apm64_top/u_apm64_top/u_dqce_clk_x4/CLKIN
2.657	0.157	tINS	RR	44	-	inst_apm64_top/u_apm64_top/u_dqce_clk_x4/CLKOUT
3.010	0.353	tNET	RR	1	IOT68[A]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[4].u_ides8_mem/FCLK
3.010	0.000	tSu		1	IOT68[A]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[4].u_ides8_mem

Path Statistics:

Clock Skew	0.000
Setup Relationship	2.500
Logic Level	1
Arrival Clock Path Delay	cell: 0.157, 30.769%; route: 0.353, 69.231%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.428, 100.000%
Required Clock Path Delay	cell: 0.157, 30.769%; route: 0.353, 69.231%

Path12

Path Summary:

Slack	2.072
Data Arrival Time	0.937
Data Required Time	3.010
From	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_dqs
To	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[4].u_ides8_mem
Launch Clk	mem_clk:[R]
Latch Clk	mem_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					mem_clk
0.000	0.000	tCL	RR	1	PLL_R[0]	u_Gowin_PLL/PLLA_inst/CLKOUT0
0.000	0.000	tNET	RR	3	-	inst_apm64_top/u_apm64_top/u_dqce_clk_x4/CLKIN
0.157	0.157	tINS	RR	44	-	inst_apm64_top/u_apm64_top/u_dqce_clk_x4/CLKOUT
0.510	0.353	tNET	RR	5	R0C60	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_dqs/FCLK
0.937	0.428	tC2Q	RF	8	R0C60	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_dqs/RPOINT[0]
0.937	0.000	tNET	FF	1	IOT68[A]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[4].u_ides8_mem/RADDR[0]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
2.500	2.500					active clock edge time
2.500	0.000					mem_clk
2.500	0.000	tCL	RR	1	PLL_R[0]	u_Gowin_PLL/PLLA_inst/CLKOUT0
2.500	0.000	tNET	RR	3	-	inst_apm64_top/u_apm64_top/u_dqce_clk_x4/CLKIN
2.657	0.157	tINS	RR	44	-	inst_apm64_top/u_apm64_top/u_dqce_clk_x4/CLKOUT
3.010	0.353	tNET	RR	1	IOT68[A]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[4].u_ides8_mem/FCLK
3.010	0.000	tSu		1	IOT68[A]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[4].u_ides8_mem

Path Statistics:

Clock Skew	0.000
Setup Relationship	2.500
Logic Level	1
Arrival Clock Path Delay	cell: 0.157, 30.769%; route: 0.353, 69.231%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.428, 100.000%
Required Clock Path Delay	cell: 0.157, 30.769%; route: 0.353, 69.231%

Path13

Path Summary:

Slack	2.072
Data Arrival Time	0.937
Data Required Time	3.010
From	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_dqs
To	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[3].u_ides8_mem
Launch Clk	mem_clk:[R]
Latch Clk	mem_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					mem_clk
0.000	0.000	tCL	RR	1	PLL_R[0]	u_Gowin_PLL/PLLA_inst/CLKOUT0
0.000	0.000	tNET	RR	3	-	inst_apm64_top/u_apm64_top/u_dqce_clk_x4/CLKIN
0.157	0.157	tINS	RR	44	-	inst_apm64_top/u_apm64_top/u_dqce_clk_x4/CLKOUT
0.510	0.353	tNET	RR	5	R0C60	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_dqs/FCLK
0.937	0.428	tC2Q	RF	8	R0C60	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_dqs/RPOINT[2]
0.937	0.000	tNET	FF	1	IOT66[B]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[3].u_ides8_mem/RADDR[2]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
2.500	2.500					active clock edge time
2.500	0.000					mem_clk
2.500	0.000	tCL	RR	1	PLL_R[0]	u_Gowin_PLL/PLLA_inst/CLKOUT0
2.500	0.000	tNET	RR	3	-	inst_apm64_top/u_apm64_top/u_dqce_clk_x4/CLKIN
2.657	0.157	tINS	RR	44	-	inst_apm64_top/u_apm64_top/u_dqce_clk_x4/CLKOUT
3.010	0.353	tNET	RR	1	IOT66[B]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[3].u_ides8_mem/FCLK
3.010	0.000	tSu		1	IOT66[B]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[3].u_ides8_mem

Path Statistics:

Clock Skew	0.000
Setup Relationship	2.500
Logic Level	1
Arrival Clock Path Delay	cell: 0.157, 30.769%; route: 0.353, 69.231%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.428, 100.000%
Required Clock Path Delay	cell: 0.157, 30.769%; route: 0.353, 69.231%

Path14

Path Summary:

Slack	2.072
Data Arrival Time	0.937
Data Required Time	3.010
From	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_dqs
To	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[3].u_ides8_mem
Launch Clk	mem_clk:[R]
Latch Clk	mem_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					mem_clk
0.000	0.000	tCL	RR	1	PLL_R[0]	u_Gowin_PLL/PLLA_inst/CLKOUT0
0.000	0.000	tNET	RR	3	-	inst_apm64_top/u_apm64_top/u_dqce_clk_x4/CLKIN
0.157	0.157	tINS	RR	44	-	inst_apm64_top/u_apm64_top/u_dqce_clk_x4/CLKOUT
0.510	0.353	tNET	RR	5	R0C60	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_dqs/FCLK
0.937	0.428	tC2Q	RF	8	R0C60	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_dqs/RPOINT[1]
0.937	0.000	tNET	FF	1	IOT66[B]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[3].u_ides8_mem/RADDR[1]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
2.500	2.500					active clock edge time
2.500	0.000					mem_clk
2.500	0.000	tCL	RR	1	PLL_R[0]	u_Gowin_PLL/PLLA_inst/CLKOUT0
2.500	0.000	tNET	RR	3	-	inst_apm64_top/u_apm64_top/u_dqce_clk_x4/CLKIN
2.657	0.157	tINS	RR	44	-	inst_apm64_top/u_apm64_top/u_dqce_clk_x4/CLKOUT
3.010	0.353	tNET	RR	1	IOT66[B]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[3].u_ides8_mem/FCLK
3.010	0.000	tSu		1	IOT66[B]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[3].u_ides8_mem

Path Statistics:

Clock Skew	0.000
Setup Relationship	2.500
Logic Level	1
Arrival Clock Path Delay	cell: 0.157, 30.769%; route: 0.353, 69.231%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.428, 100.000%
Required Clock Path Delay	cell: 0.157, 30.769%; route: 0.353, 69.231%

Path15

Path Summary:

Slack	2.072
Data Arrival Time	0.937
Data Required Time	3.010
From	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_dqs
To	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[3].u_ides8_mem
Launch Clk	mem_clk:[R]
Latch Clk	mem_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					mem_clk
0.000	0.000	tCL	RR	1	PLL_R[0]	u_Gowin_PLL/PLLA_inst/CLKOUT0
0.000	0.000	tNET	RR	3	-	inst_apm64_top/u_apm64_top/u_dqce_clk_x4/CLKIN
0.157	0.157	tINS	RR	44	-	inst_apm64_top/u_apm64_top/u_dqce_clk_x4/CLKOUT
0.510	0.353	tNET	RR	5	R0C60	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_dqs/FCLK
0.937	0.428	tC2Q	RF	8	R0C60	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_dqs/RPOINT[0]
0.937	0.000	tNET	FF	1	IOT66[B]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[3].u_ides8_mem/RADDR[0]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
2.500	2.500					active clock edge time
2.500	0.000					mem_clk
2.500	0.000	tCL	RR	1	PLL_R[0]	u_Gowin_PLL/PLLA_inst/CLKOUT0
2.500	0.000	tNET	RR	3	-	inst_apm64_top/u_apm64_top/u_dqce_clk_x4/CLKIN
2.657	0.157	tINS	RR	44	-	inst_apm64_top/u_apm64_top/u_dqce_clk_x4/CLKOUT
3.010	0.353	tNET	RR	1	IOT66[B]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[3].u_ides8_mem/FCLK
3.010	0.000	tSu		1	IOT66[B]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[3].u_ides8_mem

Path Statistics:

Clock Skew	0.000
Setup Relationship	2.500
Logic Level	1
Arrival Clock Path Delay	cell: 0.157, 30.769%; route: 0.353, 69.231%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.428, 100.000%
Required Clock Path Delay	cell: 0.157, 30.769%; route: 0.353, 69.231%

Path16

Path Summary:

Slack	2.072
Data Arrival Time	0.937
Data Required Time	3.010
From	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_dqs
To	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[2].u_ides8_mem
Launch Clk	mem_clk:[R]
Latch Clk	mem_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					mem_clk
0.000	0.000	tCL	RR	1	PLL_R[0]	u_Gowin_PLL/PLLA_inst/CLKOUT0
0.000	0.000	tNET	RR	3	-	inst_apm64_top/u_apm64_top/u_dqce_clk_x4/CLKIN
0.157	0.157	tINS	RR	44	-	inst_apm64_top/u_apm64_top/u_dqce_clk_x4/CLKOUT
0.510	0.353	tNET	RR	5	R0C60	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_dqs/FCLK
0.937	0.428	tC2Q	RF	8	R0C60	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_dqs/RPOINT[2]
0.937	0.000	tNET	FF	1	IOT66[A]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[2].u_ides8_mem/RADDR[2]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
2.500	2.500					active clock edge time
2.500	0.000					mem_clk
2.500	0.000	tCL	RR	1	PLL_R[0]	u_Gowin_PLL/PLLA_inst/CLKOUT0
2.500	0.000	tNET	RR	3	-	inst_apm64_top/u_apm64_top/u_dqce_clk_x4/CLKIN
2.657	0.157	tINS	RR	44	-	inst_apm64_top/u_apm64_top/u_dqce_clk_x4/CLKOUT
3.010	0.353	tNET	RR	1	IOT66[A]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[2].u_ides8_mem/FCLK
3.010	0.000	tSu		1	IOT66[A]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[2].u_ides8_mem

Path Statistics:

Clock Skew	0.000
Setup Relationship	2.500
Logic Level	1
Arrival Clock Path Delay	cell: 0.157, 30.769%; route: 0.353, 69.231%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.428, 100.000%
Required Clock Path Delay	cell: 0.157, 30.769%; route: 0.353, 69.231%

Path17

Path Summary:

Slack	2.072
Data Arrival Time	0.937
Data Required Time	3.010
From	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_dqs
To	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[2].u_ides8_mem
Launch Clk	mem_clk:[R]
Latch Clk	mem_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					mem_clk
0.000	0.000	tCL	RR	1	PLL_R[0]	u_Gowin_PLL/PLLA_inst/CLKOUT0
0.000	0.000	tNET	RR	3	-	inst_apm64_top/u_apm64_top/u_dqce_clk_x4/CLKIN
0.157	0.157	tINS	RR	44	-	inst_apm64_top/u_apm64_top/u_dqce_clk_x4/CLKOUT
0.510	0.353	tNET	RR	5	R0C60	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_dqs/FCLK
0.937	0.428	tC2Q	RF	8	R0C60	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_dqs/RPOINT[1]
0.937	0.000	tNET	FF	1	IOT66[A]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[2].u_ides8_mem/RADDR[1]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
2.500	2.500					active clock edge time
2.500	0.000					mem_clk
2.500	0.000	tCL	RR	1	PLL_R[0]	u_Gowin_PLL/PLLA_inst/CLKOUT0
2.500	0.000	tNET	RR	3	-	inst_apm64_top/u_apm64_top/u_dqce_clk_x4/CLKIN
2.657	0.157	tINS	RR	44	-	inst_apm64_top/u_apm64_top/u_dqce_clk_x4/CLKOUT
3.010	0.353	tNET	RR	1	IOT66[A]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[2].u_ides8_mem/FCLK
3.010	0.000	tSu		1	IOT66[A]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[2].u_ides8_mem

Path Statistics:

Clock Skew	0.000
Setup Relationship	2.500
Logic Level	1
Arrival Clock Path Delay	cell: 0.157, 30.769%; route: 0.353, 69.231%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.428, 100.000%
Required Clock Path Delay	cell: 0.157, 30.769%; route: 0.353, 69.231%

Path18

Path Summary:

Slack	2.072
Data Arrival Time	0.937
Data Required Time	3.010
From	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_dqs
To	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[2].u_ides8_mem
Launch Clk	mem_clk:[R]
Latch Clk	mem_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					mem_clk
0.000	0.000	tCL	RR	1	PLL_R[0]	u_Gowin_PLL/PLLA_inst/CLKOUT0
0.000	0.000	tNET	RR	3	-	inst_apm64_top/u_apm64_top/u_dqce_clk_x4/CLKIN
0.157	0.157	tINS	RR	44	-	inst_apm64_top/u_apm64_top/u_dqce_clk_x4/CLKOUT
0.510	0.353	tNET	RR	5	R0C60	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_dqs/FCLK
0.937	0.428	tC2Q	RF	8	R0C60	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_dqs/RPOINT[0]
0.937	0.000	tNET	FF	1	IOT66[A]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[2].u_ides8_mem/RADDR[0]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
2.500	2.500					active clock edge time
2.500	0.000					mem_clk
2.500	0.000	tCL	RR	1	PLL_R[0]	u_Gowin_PLL/PLLA_inst/CLKOUT0
2.500	0.000	tNET	RR	3	-	inst_apm64_top/u_apm64_top/u_dqce_clk_x4/CLKIN
2.657	0.157	tINS	RR	44	-	inst_apm64_top/u_apm64_top/u_dqce_clk_x4/CLKOUT
3.010	0.353	tNET	RR	1	IOT66[A]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[2].u_ides8_mem/FCLK
3.010	0.000	tSu		1	IOT66[A]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[2].u_ides8_mem

Path Statistics:

Clock Skew	0.000
Setup Relationship	2.500
Logic Level	1
Arrival Clock Path Delay	cell: 0.157, 30.769%; route: 0.353, 69.231%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.428, 100.000%
Required Clock Path Delay	cell: 0.157, 30.769%; route: 0.353, 69.231%

Path19

Path Summary:

Slack	2.072
Data Arrival Time	0.937
Data Required Time	3.010
From	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_dqs
To	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[1].u_ides8_mem
Launch Clk	mem_clk:[R]
Latch Clk	mem_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					mem_clk
0.000	0.000	tCL	RR	1	PLL_R[0]	u_Gowin_PLL/PLLA_inst/CLKOUT0
0.000	0.000	tNET	RR	3	-	inst_apm64_top/u_apm64_top/u_dqce_clk_x4/CLKIN
0.157	0.157	tINS	RR	44	-	inst_apm64_top/u_apm64_top/u_dqce_clk_x4/CLKOUT
0.510	0.353	tNET	RR	5	R0C60	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_dqs/FCLK
0.937	0.428	tC2Q	RF	8	R0C60	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_dqs/RPOINT[2]
0.937	0.000	tNET	FF	1	IOT63[B]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[1].u_ides8_mem/RADDR[2]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
2.500	2.500					active clock edge time
2.500	0.000					mem_clk
2.500	0.000	tCL	RR	1	PLL_R[0]	u_Gowin_PLL/PLLA_inst/CLKOUT0
2.500	0.000	tNET	RR	3	-	inst_apm64_top/u_apm64_top/u_dqce_clk_x4/CLKIN
2.657	0.157	tINS	RR	44	-	inst_apm64_top/u_apm64_top/u_dqce_clk_x4/CLKOUT
3.010	0.353	tNET	RR	1	IOT63[B]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[1].u_ides8_mem/FCLK
3.010	0.000	tSu		1	IOT63[B]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[1].u_ides8_mem

Path Statistics:

Clock Skew	0.000
Setup Relationship	2.500
Logic Level	1
Arrival Clock Path Delay	cell: 0.157, 30.769%; route: 0.353, 69.231%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.428, 100.000%
Required Clock Path Delay	cell: 0.157, 30.769%; route: 0.353, 69.231%

Path20

Path Summary:

Slack	2.072
Data Arrival Time	0.937
Data Required Time	3.010
From	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_dqs
To	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[1].u_ides8_mem
Launch Clk	mem_clk:[R]
Latch Clk	mem_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					mem_clk
0.000	0.000	tCL	RR	1	PLL_R[0]	u_Gowin_PLL/PLLA_inst/CLKOUT0
0.000	0.000	tNET	RR	3	-	inst_apm64_top/u_apm64_top/u_dqce_clk_x4/CLKIN
0.157	0.157	tINS	RR	44	-	inst_apm64_top/u_apm64_top/u_dqce_clk_x4/CLKOUT
0.510	0.353	tNET	RR	5	R0C60	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_dqs/FCLK
0.937	0.428	tC2Q	RF	8	R0C60	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_dqs/RPOINT[1]
0.937	0.000	tNET	FF	1	IOT63[B]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[1].u_ides8_mem/RADDR[1]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
2.500	2.500					active clock edge time
2.500	0.000					mem_clk
2.500	0.000	tCL	RR	1	PLL_R[0]	u_Gowin_PLL/PLLA_inst/CLKOUT0
2.500	0.000	tNET	RR	3	-	inst_apm64_top/u_apm64_top/u_dqce_clk_x4/CLKIN
2.657	0.157	tINS	RR	44	-	inst_apm64_top/u_apm64_top/u_dqce_clk_x4/CLKOUT
3.010	0.353	tNET	RR	1	IOT63[B]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[1].u_ides8_mem/FCLK
3.010	0.000	tSu		1	IOT63[B]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[1].u_ides8_mem

Path Statistics:

Clock Skew	0.000
Setup Relationship	2.500
Logic Level	1
Arrival Clock Path Delay	cell: 0.157, 30.769%; route: 0.353, 69.231%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.428, 100.000%
Required Clock Path Delay	cell: 0.157, 30.769%; route: 0.353, 69.231%

Path21

Path Summary:

Slack	2.072
Data Arrival Time	0.937
Data Required Time	3.010
From	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_dqs
To	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[1].u_ides8_mem
Launch Clk	mem_clk:[R]
Latch Clk	mem_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					mem_clk
0.000	0.000	tCL	RR	1	PLL_R[0]	u_Gowin_PLL/PLLA_inst/CLKOUT0
0.000	0.000	tNET	RR	3	-	inst_apm64_top/u_apm64_top/u_dqce_clk_x4/CLKIN
0.157	0.157	tINS	RR	44	-	inst_apm64_top/u_apm64_top/u_dqce_clk_x4/CLKOUT
0.510	0.353	tNET	RR	5	R0C60	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_dqs/FCLK
0.937	0.428	tC2Q	RF	8	R0C60	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_dqs/RPOINT[0]
0.937	0.000	tNET	FF	1	IOT63[B]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[1].u_ides8_mem/RADDR[0]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
2.500	2.500					active clock edge time
2.500	0.000					mem_clk
2.500	0.000	tCL	RR	1	PLL_R[0]	u_Gowin_PLL/PLLA_inst/CLKOUT0
2.500	0.000	tNET	RR	3	-	inst_apm64_top/u_apm64_top/u_dqce_clk_x4/CLKIN
2.657	0.157	tINS	RR	44	-	inst_apm64_top/u_apm64_top/u_dqce_clk_x4/CLKOUT
3.010	0.353	tNET	RR	1	IOT63[B]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[1].u_ides8_mem/FCLK
3.010	0.000	tSu		1	IOT63[B]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[1].u_ides8_mem

Path Statistics:

Clock Skew	0.000
Setup Relationship	2.500
Logic Level	1
Arrival Clock Path Delay	cell: 0.157, 30.769%; route: 0.353, 69.231%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.428, 100.000%
Required Clock Path Delay	cell: 0.157, 30.769%; route: 0.353, 69.231%

Path22

Path Summary:

Slack	2.072
Data Arrival Time	0.937
Data Required Time	3.010
From	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_dqs
To	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[0].u_ides8_mem
Launch Clk	mem_clk:[R]
Latch Clk	mem_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					mem_clk
0.000	0.000	tCL	RR	1	PLL_R[0]	u_Gowin_PLL/PLLA_inst/CLKOUT0
0.000	0.000	tNET	RR	3	-	inst_apm64_top/u_apm64_top/u_dqce_clk_x4/CLKIN
0.157	0.157	tINS	RR	44	-	inst_apm64_top/u_apm64_top/u_dqce_clk_x4/CLKOUT
0.510	0.353	tNET	RR	5	R0C60	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_dqs/FCLK
0.937	0.428	tC2Q	RF	8	R0C60	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_dqs/RPOINT[2]
0.937	0.000	tNET	FF	1	IOT63[A]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[0].u_ides8_mem/RADDR[2]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
2.500	2.500					active clock edge time
2.500	0.000					mem_clk
2.500	0.000	tCL	RR	1	PLL_R[0]	u_Gowin_PLL/PLLA_inst/CLKOUT0
2.500	0.000	tNET	RR	3	-	inst_apm64_top/u_apm64_top/u_dqce_clk_x4/CLKIN
2.657	0.157	tINS	RR	44	-	inst_apm64_top/u_apm64_top/u_dqce_clk_x4/CLKOUT
3.010	0.353	tNET	RR	1	IOT63[A]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[0].u_ides8_mem/FCLK
3.010	0.000	tSu		1	IOT63[A]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[0].u_ides8_mem

Path Statistics:

Clock Skew	0.000
Setup Relationship	2.500
Logic Level	1
Arrival Clock Path Delay	cell: 0.157, 30.769%; route: 0.353, 69.231%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.428, 100.000%
Required Clock Path Delay	cell: 0.157, 30.769%; route: 0.353, 69.231%

Path23

Path Summary:

Slack	2.072
Data Arrival Time	0.937
Data Required Time	3.010
From	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_dqs
To	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[0].u_ides8_mem
Launch Clk	mem_clk:[R]
Latch Clk	mem_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					mem_clk
0.000	0.000	tCL	RR	1	PLL_R[0]	u_Gowin_PLL/PLLA_inst/CLKOUT0
0.000	0.000	tNET	RR	3	-	inst_apm64_top/u_apm64_top/u_dqce_clk_x4/CLKIN
0.157	0.157	tINS	RR	44	-	inst_apm64_top/u_apm64_top/u_dqce_clk_x4/CLKOUT
0.510	0.353	tNET	RR	5	R0C60	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_dqs/FCLK
0.937	0.428	tC2Q	RF	8	R0C60	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_dqs/RPOINT[1]
0.937	0.000	tNET	FF	1	IOT63[A]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[0].u_ides8_mem/RADDR[1]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
2.500	2.500					active clock edge time
2.500	0.000					mem_clk
2.500	0.000	tCL	RR	1	PLL_R[0]	u_Gowin_PLL/PLLA_inst/CLKOUT0
2.500	0.000	tNET	RR	3	-	inst_apm64_top/u_apm64_top/u_dqce_clk_x4/CLKIN
2.657	0.157	tINS	RR	44	-	inst_apm64_top/u_apm64_top/u_dqce_clk_x4/CLKOUT
3.010	0.353	tNET	RR	1	IOT63[A]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[0].u_ides8_mem/FCLK
3.010	0.000	tSu		1	IOT63[A]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[0].u_ides8_mem

Path Statistics:

Clock Skew	0.000
Setup Relationship	2.500
Logic Level	1
Arrival Clock Path Delay	cell: 0.157, 30.769%; route: 0.353, 69.231%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.428, 100.000%
Required Clock Path Delay	cell: 0.157, 30.769%; route: 0.353, 69.231%

Path24

Path Summary:

Slack	2.072
Data Arrival Time	0.937
Data Required Time	3.010
From	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_dqs
To	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[0].u_ides8_mem
Launch Clk	mem_clk:[R]
Latch Clk	mem_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					mem_clk
0.000	0.000	tCL	RR	1	PLL_R[0]	u_Gowin_PLL/PLLA_inst/CLKOUT0
0.000	0.000	tNET	RR	3	-	inst_apm64_top/u_apm64_top/u_dqce_clk_x4/CLKIN
0.157	0.157	tINS	RR	44	-	inst_apm64_top/u_apm64_top/u_dqce_clk_x4/CLKOUT
0.510	0.353	tNET	RR	5	R0C60	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_dqs/FCLK
0.937	0.428	tC2Q	RF	8	R0C60	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_dqs/RPOINT[0]
0.937	0.000	tNET	FF	1	IOT63[A]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[0].u_ides8_mem/RADDR[0]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
2.500	2.500					active clock edge time
2.500	0.000					mem_clk
2.500	0.000	tCL	RR	1	PLL_R[0]	u_Gowin_PLL/PLLA_inst/CLKOUT0
2.500	0.000	tNET	RR	3	-	inst_apm64_top/u_apm64_top/u_dqce_clk_x4/CLKIN
2.657	0.157	tINS	RR	44	-	inst_apm64_top/u_apm64_top/u_dqce_clk_x4/CLKOUT
3.010	0.353	tNET	RR	1	IOT63[A]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[0].u_ides8_mem/FCLK
3.010	0.000	tSu		1	IOT63[A]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[0].u_ides8_mem

Path Statistics:

Clock Skew	0.000
Setup Relationship	2.500
Logic Level	1
Arrival Clock Path Delay	cell: 0.157, 30.769%; route: 0.353, 69.231%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.428, 100.000%
Required Clock Path Delay	cell: 0.157, 30.769%; route: 0.353, 69.231%

Path25

Path Summary:

Slack	2.072
Data Arrival Time	0.937
Data Required Time	3.010
From	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[0].u_apm64_data_lane/u_dqs
To	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[0].u_apm64_data_lane/iserdes_gen[7].u_ides8_mem
Launch Clk	mem_clk:[R]
Latch Clk	mem_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					mem_clk
0.000	0.000	tCL	RR	1	PLL_R[0]	u_Gowin_PLL/PLLA_inst/CLKOUT0
0.000	0.000	tNET	RR	3	-	inst_apm64_top/u_apm64_top/u_dqce_clk_x4/CLKIN
0.157	0.157	tINS	RR	44	-	inst_apm64_top/u_apm64_top/u_dqce_clk_x4/CLKOUT
0.510	0.353	tNET	RR	5	R0C82	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[0].u_apm64_data_lane/u_dqs/FCLK
0.937	0.428	tC2Q	RF	8	R0C82	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[0].u_apm64_data_lane/u_dqs/RPOINT[2]
0.937	0.000	tNET	FF	1	IOT83[B]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[0].u_apm64_data_lane/iserdes_gen[7].u_ides8_mem/RADDR[2]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
2.500	2.500					active clock edge time
2.500	0.000					mem_clk
2.500	0.000	tCL	RR	1	PLL_R[0]	u_Gowin_PLL/PLLA_inst/CLKOUT0
2.500	0.000	tNET	RR	3	-	inst_apm64_top/u_apm64_top/u_dqce_clk_x4/CLKIN
2.657	0.157	tINS	RR	44	-	inst_apm64_top/u_apm64_top/u_dqce_clk_x4/CLKOUT
3.010	0.353	tNET	RR	1	IOT83[B]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[0].u_apm64_data_lane/iserdes_gen[7].u_ides8_mem/FCLK
3.010	0.000	tSu		1	IOT83[B]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[0].u_apm64_data_lane/iserdes_gen[7].u_ides8_mem

Path Statistics:

Clock Skew	0.000
Setup Relationship	2.500
Logic Level	1
Arrival Clock Path Delay	cell: 0.157, 30.769%; route: 0.353, 69.231%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.428, 100.000%
Required Clock Path Delay	cell: 0.157, 30.769%; route: 0.353, 69.231%

Hold Analysis Report

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	0.157
Data Arrival Time	0.961
Data Required Time	0.803
From	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[0].u_apm64_data_lane/dqs_dx_1_s0
To	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_dqs_gen
Launch Clk	userclk:[R]
Latch Clk	userclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					userclk
0.000	0.000	tCL	RR	2337	TOPSIDE[0]	inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
0.720	0.720	tNET	RR	1	R2C61[0][A]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[0].u_apm64_data_lane/dqs_dx_1_s0/CLK
0.864	0.144	tC2Q	RR	4	R2C61[0][A]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[0].u_apm64_data_lane/dqs_dx_1_s0/Q
0.961	0.097	tNET	RR	1	IOT61[A]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_dqs_gen/D2

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					userclk
0.000	0.000	tCL	RR	2337	TOPSIDE[0]	inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
0.722	0.722	tNET	RR	1	IOT61[A]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_dqs_gen/PCLK
0.803	0.082	tHld		1	IOT61[A]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_dqs_gen

Path Statistics:

Clock Skew	0.002
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.720, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.097, 40.249%; tC2Q: 0.144, 59.751%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.722, 100.000%

Path2

Path Summary:

Slack	0.157
Data Arrival Time	0.961
Data Required Time	0.803
From	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[0].u_apm64_data_lane/dqs_dx_1_s0
To	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_dqs_gen
Launch Clk	userclk:[R]
Latch Clk	userclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					userclk
0.000	0.000	tCL	RR	2337	TOPSIDE[0]	inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
0.720	0.720	tNET	RR	1	R2C61[0][A]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[0].u_apm64_data_lane/dqs_dx_1_s0/CLK
0.864	0.144	tC2Q	RR	4	R2C61[0][A]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[0].u_apm64_data_lane/dqs_dx_1_s0/Q
0.961	0.097	tNET	RR	1	IOT61[A]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_dqs_gen/D0

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					userclk
0.000	0.000	tCL	RR	2337	TOPSIDE[0]	inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
0.722	0.722	tNET	RR	1	IOT61[A]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_dqs_gen/PCLK
0.803	0.082	tHld		1	IOT61[A]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_dqs_gen

Path Statistics:

Clock Skew	0.002
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.720, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.097, 40.249%; tC2Q: 0.144, 59.751%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.722, 100.000%

Path3

Path Summary:

Slack	0.166
Data Arrival Time	21.507
Data Required Time	21.341
From	u_test/error_int1_3_s0
To	led_1_s2
Launch Clk	userclk:[R]
Latch Clk	clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					userclk
20.000	0.000	tCL	RR	2337	TOPSIDE[0]	inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
20.706	0.706	tNET	RR	1	R26C19[2][B]	u_test/error_int1_3_s0/CLK
20.850	0.144	tC2Q	RR	1	R26C19[2][B]	u_test/error_int1_3_s0/Q
20.943	0.093	tNET	RR	1	R27C19[3][A]	n74_s3/I3
21.091	0.148	tINS	RR	1	R27C19[3][A]	n74_s3/F
21.094	0.003	tNET	RR	1	R27C19[2][A]	n74_s1/I1
21.298	0.204	tINS	RR	1	R27C19[2][A]	n74_s1/F
21.301	0.003	tNET	RR	1	R27C19[1][B]	n74_s0/I2
21.507	0.206	tINS	RF	1	R27C19[1][B]	n74_s0/F
21.507	0.000	tNET	FF	1	R27C19[1][B]	led_1_s2/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clkin
20.000	0.000	tCL	RR	1	IOB26[A]	clk_ibuf/I
20.581	0.581	tINS	RR	81	IOB26[A]	clk_ibuf/O
21.281	0.700	tNET	RR	1	R27C19[1][B]	led_1_s2/CLK
21.316	0.035	tUnc				led_1_s2
21.341	0.025	tHld		1	R27C19[1][B]	led_1_s2

Path Statistics:

Clock Skew	0.575
Hold Relationship	0.000
Logic Level	4
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.706, 100.000%
Arrival Data Path Delay	cell: 0.558, 69.663%; route: 0.099, 12.360%; tC2Q: 0.144, 17.978%
Required Clock Path Delay	cell: 0.581, 45.352%; route: 0.700, 54.648%

Path4

Path Summary:

Slack	0.275
Data Arrival Time	1.009
Data Required Time	0.734
From	u_test/wcnt_4_s1
To	u_test/wcnt_4_s1
Launch Clk	userclk:[R]
Latch Clk	userclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					userclk
0.000	0.000	tCL	RR	2337	TOPSIDE[0]	inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
0.709	0.709	tNET	RR	1	R24C10[1][A]	u_test/wcnt_4_s1/CLK
0.850	0.141	tC2Q	RF	3	R24C10[1][A]	u_test/wcnt_4_s1/Q
0.856	0.006	tNET	FF	1	R24C10[1][A]	u_test/n1459_s3/I0
1.009	0.153	tINS	FF	1	R24C10[1][A]	u_test/n1459_s3/F
1.009	0.000	tNET	FF	1	R24C10[1][A]	u_test/wcnt_4_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					userclk
0.000	0.000	tCL	RR	2337	TOPSIDE[0]	inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
0.709	0.709	tNET	RR	1	R24C10[1][A]	u_test/wcnt_4_s1/CLK
0.734	0.025	tHld		1	R24C10[1][A]	u_test/wcnt_4_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.709, 100.000%
Arrival Data Path Delay	cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.709, 100.000%

Path5

Path Summary:

Slack	0.275
Data Arrival Time	1.001
Data Required Time	0.726
From	inst_apm64_top/u_apm64_top/u_apsram_ctrl/ctrl_cnt_1_s0
To	inst_apm64_top/u_apm64_top/u_apsram_ctrl/ctrl_cnt_1_s0
Launch Clk	userclk:[R]
Latch Clk	userclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					userclk
0.000	0.000	tCL	RR	2337	TOPSIDE[0]	inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
0.701	0.701	tNET	RR	1	R27C11[0][A]	inst_apm64_top/u_apm64_top/u_apsram_ctrl/ctrl_cnt_1_s0/CLK
0.842	0.141	tC2Q	RF	5	R27C11[0][A]	inst_apm64_top/u_apm64_top/u_apsram_ctrl/ctrl_cnt_1_s0/Q
0.848	0.006	tNET	FF	1	R27C11[0][A]	inst_apm64_top/u_apm64_top/u_apsram_ctrl/n1138_s2/I2
1.001	0.153	tINS	FF	1	R27C11[0][A]	inst_apm64_top/u_apm64_top/u_apsram_ctrl/n1138_s2/F
1.001	0.000	tNET	FF	1	R27C11[0][A]	inst_apm64_top/u_apm64_top/u_apsram_ctrl/ctrl_cnt_1_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					userclk
0.000	0.000	tCL	RR	2337	TOPSIDE[0]	inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
0.701	0.701	tNET	RR	1	R27C11[0][A]	inst_apm64_top/u_apm64_top/u_apsram_ctrl/ctrl_cnt_1_s0/CLK
0.726	0.025	tHld		1	R27C11[0][A]	inst_apm64_top/u_apm64_top/u_apsram_ctrl/ctrl_cnt_1_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.701, 100.000%
Arrival Data Path Delay	cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.701, 100.000%

Path6

Path Summary:

Slack	0.275
Data Arrival Time	1.001
Data Required Time	0.726
From	inst_apm64_top/u_apm64_top/u_apsram_ctrl/tXHS_cnt_13_s0
To	inst_apm64_top/u_apm64_top/u_apsram_ctrl/tXHS_cnt_13_s0
Launch Clk	userclk:[R]
Latch Clk	userclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					userclk
0.000	0.000	tCL	RR	2337	TOPSIDE[0]	inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
0.701	0.701	tNET	RR	1	R27C5[1][A]	inst_apm64_top/u_apm64_top/u_apsram_ctrl/tXHS_cnt_13_s0/CLK
0.842	0.141	tC2Q	RF	3	R27C5[1][A]	inst_apm64_top/u_apm64_top/u_apsram_ctrl/tXHS_cnt_13_s0/Q
0.848	0.006	tNET	FF	1	R27C5[1][A]	inst_apm64_top/u_apm64_top/u_apsram_ctrl/n218_s1/I2
1.001	0.153	tINS	FF	1	R27C5[1][A]	inst_apm64_top/u_apm64_top/u_apsram_ctrl/n218_s1/F
1.001	0.000	tNET	FF	1	R27C5[1][A]	inst_apm64_top/u_apm64_top/u_apsram_ctrl/tXHS_cnt_13_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					userclk
0.000	0.000	tCL	RR	2337	TOPSIDE[0]	inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
0.701	0.701	tNET	RR	1	R27C5[1][A]	inst_apm64_top/u_apm64_top/u_apsram_ctrl/tXHS_cnt_13_s0/CLK
0.726	0.025	tHld		1	R27C5[1][A]	inst_apm64_top/u_apm64_top/u_apsram_ctrl/tXHS_cnt_13_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.701, 100.000%
Arrival Data Path Delay	cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.701, 100.000%

Path7

Path Summary:

Slack	0.275
Data Arrival Time	1.011
Data Required Time	0.736
From	inst_apm64_top/u_apm64_top/u_apsram_init/readback_check_0_s26
To	inst_apm64_top/u_apm64_top/u_apsram_init/readback_check_0_s26
Launch Clk	userclk:[R]
Latch Clk	userclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					userclk
0.000	0.000	tCL	RR	2337	TOPSIDE[0]	inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
0.711	0.711	tNET	RR	1	R7C11[0][A]	inst_apm64_top/u_apm64_top/u_apsram_init/readback_check_0_s26/CLK
0.852	0.141	tC2Q	RF	2	R7C11[0][A]	inst_apm64_top/u_apm64_top/u_apsram_init/readback_check_0_s26/Q
0.858	0.006	tNET	FF	1	R7C11[0][A]	inst_apm64_top/u_apm64_top/u_apsram_init/n2667_s4/I1
1.011	0.153	tINS	FF	1	R7C11[0][A]	inst_apm64_top/u_apm64_top/u_apsram_init/n2667_s4/F
1.011	0.000	tNET	FF	1	R7C11[0][A]	inst_apm64_top/u_apm64_top/u_apsram_init/readback_check_0_s26/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					userclk
0.000	0.000	tCL	RR	2337	TOPSIDE[0]	inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
0.711	0.711	tNET	RR	1	R7C11[0][A]	inst_apm64_top/u_apm64_top/u_apsram_init/readback_check_0_s26/CLK
0.736	0.025	tHld		1	R7C11[0][A]	inst_apm64_top/u_apm64_top/u_apsram_init/readback_check_0_s26

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.711, 100.000%
Arrival Data Path Delay	cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.711, 100.000%

Path8

Path Summary:

Slack	0.275
Data Arrival Time	1.007
Data Required Time	0.732
From	inst_apm64_top/u_apm64_top/u_apsram_init/rclk_sel_reg_4_s1
To	inst_apm64_top/u_apm64_top/u_apsram_init/rclk_sel_reg_4_s1
Launch Clk	userclk:[R]
Latch Clk	userclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					userclk
0.000	0.000	tCL	RR	2337	TOPSIDE[0]	inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
0.707	0.707	tNET	RR	1	R7C6[1][A]	inst_apm64_top/u_apm64_top/u_apsram_init/rclk_sel_reg_4_s1/CLK
0.848	0.141	tC2Q	RF	5	R7C6[1][A]	inst_apm64_top/u_apm64_top/u_apsram_init/rclk_sel_reg_4_s1/Q
0.854	0.006	tNET	FF	1	R7C6[1][A]	inst_apm64_top/u_apm64_top/u_apsram_init/n2752_s2/I1
1.007	0.153	tINS	FF	1	R7C6[1][A]	inst_apm64_top/u_apm64_top/u_apsram_init/n2752_s2/F
1.007	0.000	tNET	FF	1	R7C6[1][A]	inst_apm64_top/u_apm64_top/u_apsram_init/rclk_sel_reg_4_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					userclk
0.000	0.000	tCL	RR	2337	TOPSIDE[0]	inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
0.707	0.707	tNET	RR	1	R7C6[1][A]	inst_apm64_top/u_apm64_top/u_apsram_init/rclk_sel_reg_4_s1/CLK
0.732	0.025	tHld		1	R7C6[1][A]	inst_apm64_top/u_apm64_top/u_apsram_init/rclk_sel_reg_4_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.707, 100.000%
Arrival Data Path Delay	cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.707, 100.000%

Path9

Path Summary:

Slack	0.275
Data Arrival Time	1.011
Data Required Time	0.736
From	inst_apm64_top/u_apm64_top/u_apsram_init/rmove_cnt_9_s1
To	inst_apm64_top/u_apm64_top/u_apsram_init/rmove_cnt_9_s1
Launch Clk	userclk:[R]
Latch Clk	userclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					userclk
0.000	0.000	tCL	RR	2337	TOPSIDE[0]	inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
0.711	0.711	tNET	RR	1	R7C13[1][A]	inst_apm64_top/u_apm64_top/u_apsram_init/rmove_cnt_9_s1/CLK
0.852	0.141	tC2Q	RF	4	R7C13[1][A]	inst_apm64_top/u_apm64_top/u_apsram_init/rmove_cnt_9_s1/Q
0.858	0.006	tNET	FF	1	R7C13[1][A]	inst_apm64_top/u_apm64_top/u_apsram_init/n136_s3/I1
1.011	0.153	tINS	FF	1	R7C13[1][A]	inst_apm64_top/u_apm64_top/u_apsram_init/n136_s3/F
1.011	0.000	tNET	FF	1	R7C13[1][A]	inst_apm64_top/u_apm64_top/u_apsram_init/rmove_cnt_9_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					userclk
0.000	0.000	tCL	RR	2337	TOPSIDE[0]	inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
0.711	0.711	tNET	RR	1	R7C13[1][A]	inst_apm64_top/u_apm64_top/u_apsram_init/rmove_cnt_9_s1/CLK
0.736	0.025	tHld		1	R7C13[1][A]	inst_apm64_top/u_apm64_top/u_apsram_init/rmove_cnt_9_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.711, 100.000%
Arrival Data Path Delay	cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.711, 100.000%

Path10

Path Summary:

Slack	0.275
Data Arrival Time	1.001
Data Required Time	0.726
From	inst_apm64_top/u_apm64_top/u_apsram_init/rdback_check_cnt_2_s1
To	inst_apm64_top/u_apm64_top/u_apsram_init/rdback_check_cnt_2_s1
Launch Clk	userclk:[R]
Latch Clk	userclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					userclk
0.000	0.000	tCL	RR	2337	TOPSIDE[0]	inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
0.701	0.701	tNET	RR	1	R9C7[0][A]	inst_apm64_top/u_apm64_top/u_apsram_init/rdback_check_cnt_2_s1/CLK
0.842	0.141	tC2Q	RF	2	R9C7[0][A]	inst_apm64_top/u_apm64_top/u_apsram_init/rdback_check_cnt_2_s1/Q
0.848	0.006	tNET	FF	1	R9C7[0][A]	inst_apm64_top/u_apm64_top/u_apsram_init/n2615_s1/I2
1.001	0.153	tINS	FF	1	R9C7[0][A]	inst_apm64_top/u_apm64_top/u_apsram_init/n2615_s1/F
1.001	0.000	tNET	FF	1	R9C7[0][A]	inst_apm64_top/u_apm64_top/u_apsram_init/rdback_check_cnt_2_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					userclk
0.000	0.000	tCL	RR	2337	TOPSIDE[0]	inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
0.701	0.701	tNET	RR	1	R9C7[0][A]	inst_apm64_top/u_apm64_top/u_apsram_init/rdback_check_cnt_2_s1/CLK
0.726	0.025	tHld		1	R9C7[0][A]	inst_apm64_top/u_apm64_top/u_apsram_init/rdback_check_cnt_2_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.701, 100.000%
Arrival Data Path Delay	cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.701, 100.000%

Path11

Path Summary:

Slack	0.275
Data Arrival Time	1.001
Data Required Time	0.726
From	inst_apm64_top/u_apm64_top/u_apsram_init/tRST_cnt_2_s0
To	inst_apm64_top/u_apm64_top/u_apsram_init/tRST_cnt_2_s0
Launch Clk	userclk:[R]
Latch Clk	userclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					userclk
0.000	0.000	tCL	RR	2337	TOPSIDE[0]	inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
0.701	0.701	tNET	RR	1	R9C9[0][A]	inst_apm64_top/u_apm64_top/u_apsram_init/tRST_cnt_2_s0/CLK
0.842	0.141	tC2Q	RF	4	R9C9[0][A]	inst_apm64_top/u_apm64_top/u_apsram_init/tRST_cnt_2_s0/Q
0.848	0.006	tNET	FF	1	R9C9[0][A]	inst_apm64_top/u_apm64_top/u_apsram_init/n1167_s3/I1
1.001	0.153	tINS	FF	1	R9C9[0][A]	inst_apm64_top/u_apm64_top/u_apsram_init/n1167_s3/F
1.001	0.000	tNET	FF	1	R9C9[0][A]	inst_apm64_top/u_apm64_top/u_apsram_init/tRST_cnt_2_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					userclk
0.000	0.000	tCL	RR	2337	TOPSIDE[0]	inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
0.701	0.701	tNET	RR	1	R9C9[0][A]	inst_apm64_top/u_apm64_top/u_apsram_init/tRST_cnt_2_s0/CLK
0.726	0.025	tHld		1	R9C9[0][A]	inst_apm64_top/u_apm64_top/u_apsram_init/tRST_cnt_2_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.701, 100.000%
Arrival Data Path Delay	cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.701, 100.000%

Path12

Path Summary:

Slack	0.275
Data Arrival Time	0.978
Data Required Time	0.703
From	inst_apm64_top/u_apm64_top/u_apsram_ctrl/ctrl_tRFC_done_s6
To	inst_apm64_top/u_apm64_top/u_apsram_ctrl/ctrl_tRFC_done_s6
Launch Clk	userclk:[R]
Latch Clk	userclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					userclk
0.000	0.000	tCL	RR	2337	TOPSIDE[0]	inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
0.678	0.678	tNET	RR	1	R30C10[0][A]	inst_apm64_top/u_apm64_top/u_apsram_ctrl/ctrl_tRFC_done_s6/CLK
0.819	0.141	tC2Q	RF	5	R30C10[0][A]	inst_apm64_top/u_apm64_top/u_apsram_ctrl/ctrl_tRFC_done_s6/Q
0.825	0.006	tNET	FF	1	R30C10[0][A]	inst_apm64_top/u_apm64_top/u_apsram_ctrl/n1248_s4/I1
0.978	0.153	tINS	FF	1	R30C10[0][A]	inst_apm64_top/u_apm64_top/u_apsram_ctrl/n1248_s4/F
0.978	0.000	tNET	FF	1	R30C10[0][A]	inst_apm64_top/u_apm64_top/u_apsram_ctrl/ctrl_tRFC_done_s6/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					userclk
0.000	0.000	tCL	RR	2337	TOPSIDE[0]	inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
0.678	0.678	tNET	RR	1	R30C10[0][A]	inst_apm64_top/u_apm64_top/u_apsram_ctrl/ctrl_tRFC_done_s6/CLK
0.703	0.025	tHld		1	R30C10[0][A]	inst_apm64_top/u_apm64_top/u_apsram_ctrl/ctrl_tRFC_done_s6

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.678, 100.000%
Arrival Data Path Delay	cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.678, 100.000%

Path13

Path Summary:

Slack	0.275
Data Arrival Time	0.982
Data Required Time	0.707
From	inst_apm64_top/u_apm64_top/u_apsram_ctrl/tcphr_cnt_3_s1
To	inst_apm64_top/u_apm64_top/u_apsram_ctrl/tcphr_cnt_3_s1
Launch Clk	userclk:[R]
Latch Clk	userclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					userclk
0.000	0.000	tCL	RR	2337	TOPSIDE[0]	inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
0.682	0.682	tNET	RR	1	R31C10[0][A]	inst_apm64_top/u_apm64_top/u_apsram_ctrl/tcphr_cnt_3_s1/CLK
0.823	0.141	tC2Q	RF	3	R31C10[0][A]	inst_apm64_top/u_apm64_top/u_apsram_ctrl/tcphr_cnt_3_s1/Q
0.829	0.006	tNET	FF	1	R31C10[0][A]	inst_apm64_top/u_apm64_top/u_apsram_ctrl/n1204_s1/I2
0.982	0.153	tINS	FF	1	R31C10[0][A]	inst_apm64_top/u_apm64_top/u_apsram_ctrl/n1204_s1/F
0.982	0.000	tNET	FF	1	R31C10[0][A]	inst_apm64_top/u_apm64_top/u_apsram_ctrl/tcphr_cnt_3_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					userclk
0.000	0.000	tCL	RR	2337	TOPSIDE[0]	inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
0.682	0.682	tNET	RR	1	R31C10[0][A]	inst_apm64_top/u_apm64_top/u_apsram_ctrl/tcphr_cnt_3_s1/CLK
0.707	0.025	tHld		1	R31C10[0][A]	inst_apm64_top/u_apm64_top/u_apsram_ctrl/tcphr_cnt_3_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.682, 100.000%
Arrival Data Path Delay	cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.682, 100.000%

Path14

Path Summary:

Slack	0.275
Data Arrival Time	0.982
Data Required Time	0.707
From	inst_apm64_top/u_apm64_top/u_apsram_ctrl/tcphr_cnt_6_s1
To	inst_apm64_top/u_apm64_top/u_apsram_ctrl/tcphr_cnt_6_s1
Launch Clk	userclk:[R]
Latch Clk	userclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					userclk
0.000	0.000	tCL	RR	2337	TOPSIDE[0]	inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
0.682	0.682	tNET	RR	1	R30C11[1][A]	inst_apm64_top/u_apm64_top/u_apsram_ctrl/tcphr_cnt_6_s1/CLK
0.823	0.141	tC2Q	RF	3	R30C11[1][A]	inst_apm64_top/u_apm64_top/u_apsram_ctrl/tcphr_cnt_6_s1/Q
0.829	0.006	tNET	FF	1	R30C11[1][A]	inst_apm64_top/u_apm64_top/u_apsram_ctrl/n1201_s1/I0
0.982	0.153	tINS	FF	1	R30C11[1][A]	inst_apm64_top/u_apm64_top/u_apsram_ctrl/n1201_s1/F
0.982	0.000	tNET	FF	1	R30C11[1][A]	inst_apm64_top/u_apm64_top/u_apsram_ctrl/tcphr_cnt_6_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					userclk
0.000	0.000	tCL	RR	2337	TOPSIDE[0]	inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
0.682	0.682	tNET	RR	1	R30C11[1][A]	inst_apm64_top/u_apm64_top/u_apsram_ctrl/tcphr_cnt_6_s1/CLK
0.707	0.025	tHld		1	R30C11[1][A]	inst_apm64_top/u_apm64_top/u_apsram_ctrl/tcphr_cnt_6_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.682, 100.000%
Arrival Data Path Delay	cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.682, 100.000%

Path15

Path Summary:

Slack	0.275
Data Arrival Time	0.986
Data Required Time	0.711
From	inst_apm64_top/u_apm64_top/u_apsram_ctrl/prescaler_cnt_0_s0
To	inst_apm64_top/u_apm64_top/u_apsram_ctrl/prescaler_cnt_0_s0
Launch Clk	userclk:[R]
Latch Clk	userclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					userclk
0.000	0.000	tCL	RR	2337	TOPSIDE[0]	inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
0.686	0.686	tNET	RR	1	R30C4[0][A]	inst_apm64_top/u_apm64_top/u_apsram_ctrl/prescaler_cnt_0_s0/CLK
0.827	0.141	tC2Q	RF	4	R30C4[0][A]	inst_apm64_top/u_apm64_top/u_apsram_ctrl/prescaler_cnt_0_s0/Q
0.833	0.006	tNET	FF	1	R30C4[0][A]	inst_apm64_top/u_apm64_top/u_apsram_ctrl/n1311_s2/I0
0.986	0.153	tINS	FF	1	R30C4[0][A]	inst_apm64_top/u_apm64_top/u_apsram_ctrl/n1311_s2/F
0.986	0.000	tNET	FF	1	R30C4[0][A]	inst_apm64_top/u_apm64_top/u_apsram_ctrl/prescaler_cnt_0_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					userclk
0.000	0.000	tCL	RR	2337	TOPSIDE[0]	inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
0.686	0.686	tNET	RR	1	R30C4[0][A]	inst_apm64_top/u_apm64_top/u_apsram_ctrl/prescaler_cnt_0_s0/CLK
0.711	0.025	tHld		1	R30C4[0][A]	inst_apm64_top/u_apm64_top/u_apsram_ctrl/prescaler_cnt_0_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.686, 100.000%
Arrival Data Path Delay	cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.686, 100.000%

Path16

Path Summary:

Slack	0.275
Data Arrival Time	0.997
Data Required Time	0.722
From	inst_apm64_top/u_apm64_top/u_apsram_ctrl/ctrl_cnt_7_s0
To	inst_apm64_top/u_apm64_top/u_apsram_ctrl/ctrl_cnt_7_s0
Launch Clk	userclk:[R]
Latch Clk	userclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					userclk
0.000	0.000	tCL	RR	2337	TOPSIDE[0]	inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
0.697	0.697	tNET	RR	1	R27C10[0][A]	inst_apm64_top/u_apm64_top/u_apsram_ctrl/ctrl_cnt_7_s0/CLK
0.838	0.141	tC2Q	RF	2	R27C10[0][A]	inst_apm64_top/u_apm64_top/u_apsram_ctrl/ctrl_cnt_7_s0/Q
0.844	0.006	tNET	FF	1	R27C10[0][A]	inst_apm64_top/u_apm64_top/u_apsram_ctrl/n1132_s2/I3
0.997	0.153	tINS	FF	1	R27C10[0][A]	inst_apm64_top/u_apm64_top/u_apsram_ctrl/n1132_s2/F
0.997	0.000	tNET	FF	1	R27C10[0][A]	inst_apm64_top/u_apm64_top/u_apsram_ctrl/ctrl_cnt_7_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					userclk
0.000	0.000	tCL	RR	2337	TOPSIDE[0]	inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
0.697	0.697	tNET	RR	1	R27C10[0][A]	inst_apm64_top/u_apm64_top/u_apsram_ctrl/ctrl_cnt_7_s0/CLK
0.722	0.025	tHld		1	R27C10[0][A]	inst_apm64_top/u_apm64_top/u_apsram_ctrl/ctrl_cnt_7_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.697, 100.000%
Arrival Data Path Delay	cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.697, 100.000%

Path17

Path Summary:

Slack	0.275
Data Arrival Time	0.987
Data Required Time	0.712
From	inst_apm64_top/u_apm64_top/u_apsram_ctrl/rw_burst_cnt_2_s0
To	inst_apm64_top/u_apm64_top/u_apsram_ctrl/rw_burst_cnt_2_s0
Launch Clk	userclk:[R]
Latch Clk	userclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					userclk
0.000	0.000	tCL	RR	2337	TOPSIDE[0]	inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
0.687	0.687	tNET	RR	1	R29C18[0][A]	inst_apm64_top/u_apm64_top/u_apsram_ctrl/rw_burst_cnt_2_s0/CLK
0.828	0.141	tC2Q	RF	4	R29C18[0][A]	inst_apm64_top/u_apm64_top/u_apsram_ctrl/rw_burst_cnt_2_s0/Q
0.834	0.006	tNET	FF	1	R29C18[0][A]	inst_apm64_top/u_apm64_top/u_apsram_ctrl/n1054_s1/I3
0.987	0.153	tINS	FF	1	R29C18[0][A]	inst_apm64_top/u_apm64_top/u_apsram_ctrl/n1054_s1/F
0.987	0.000	tNET	FF	1	R29C18[0][A]	inst_apm64_top/u_apm64_top/u_apsram_ctrl/rw_burst_cnt_2_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					userclk
0.000	0.000	tCL	RR	2337	TOPSIDE[0]	inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
0.687	0.687	tNET	RR	1	R29C18[0][A]	inst_apm64_top/u_apm64_top/u_apsram_ctrl/rw_burst_cnt_2_s0/CLK
0.712	0.025	tHld		1	R29C18[0][A]	inst_apm64_top/u_apm64_top/u_apsram_ctrl/rw_burst_cnt_2_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.687, 100.000%
Arrival Data Path Delay	cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.687, 100.000%

Path18

Path Summary:

Slack	0.275
Data Arrival Time	0.995
Data Required Time	0.720
From	inst_apm64_top/u_apm64_top/u_apsram_ctrl/c_state.CMDR_WAITE_s0
To	inst_apm64_top/u_apm64_top/u_apsram_ctrl/c_state.CMDR_WAITE_s0
Launch Clk	userclk:[R]
Latch Clk	userclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					userclk
0.000	0.000	tCL	RR	2337	TOPSIDE[0]	inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
0.695	0.695	tNET	RR	1	R29C12[0][A]	inst_apm64_top/u_apm64_top/u_apsram_ctrl/c_state.CMDR_WAITE_s0/CLK
0.836	0.141	tC2Q	RF	12	R29C12[0][A]	inst_apm64_top/u_apm64_top/u_apsram_ctrl/c_state.CMDR_WAITE_s0/Q
0.842	0.006	tNET	FF	1	R29C12[0][A]	inst_apm64_top/u_apm64_top/u_apsram_ctrl/n_state.CMDR_WAITE_s29/I2
0.995	0.153	tINS	FF	1	R29C12[0][A]	inst_apm64_top/u_apm64_top/u_apsram_ctrl/n_state.CMDR_WAITE_s29/F
0.995	0.000	tNET	FF	1	R29C12[0][A]	inst_apm64_top/u_apm64_top/u_apsram_ctrl/c_state.CMDR_WAITE_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					userclk
0.000	0.000	tCL	RR	2337	TOPSIDE[0]	inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
0.695	0.695	tNET	RR	1	R29C12[0][A]	inst_apm64_top/u_apm64_top/u_apsram_ctrl/c_state.CMDR_WAITE_s0/CLK
0.720	0.025	tHld		1	R29C12[0][A]	inst_apm64_top/u_apm64_top/u_apsram_ctrl/c_state.CMDR_WAITE_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.695, 100.000%
Arrival Data Path Delay	cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.695, 100.000%

Path19

Path Summary:

Slack	0.275
Data Arrival Time	0.990
Data Required Time	0.715
From	inst_apm64_top/u_apm64_top/u_apsram_ctrl/tXPHS_cnt_2_s0
To	inst_apm64_top/u_apm64_top/u_apsram_ctrl/tXPHS_cnt_2_s0
Launch Clk	userclk:[R]
Latch Clk	userclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					userclk
0.000	0.000	tCL	RR	2337	TOPSIDE[0]	inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
0.690	0.690	tNET	RR	1	R32C7[0][A]	inst_apm64_top/u_apm64_top/u_apsram_ctrl/tXPHS_cnt_2_s0/CLK
0.831	0.141	tC2Q	RF	4	R32C7[0][A]	inst_apm64_top/u_apm64_top/u_apsram_ctrl/tXPHS_cnt_2_s0/Q
0.837	0.006	tNET	FF	1	R32C7[0][A]	inst_apm64_top/u_apm64_top/u_apsram_ctrl/n171_s3/I0
0.990	0.153	tINS	FF	1	R32C7[0][A]	inst_apm64_top/u_apm64_top/u_apsram_ctrl/n171_s3/F
0.990	0.000	tNET	FF	1	R32C7[0][A]	inst_apm64_top/u_apm64_top/u_apsram_ctrl/tXPHS_cnt_2_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					userclk
0.000	0.000	tCL	RR	2337	TOPSIDE[0]	inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
0.690	0.690	tNET	RR	1	R32C7[0][A]	inst_apm64_top/u_apm64_top/u_apsram_ctrl/tXPHS_cnt_2_s0/CLK
0.715	0.025	tHld		1	R32C7[0][A]	inst_apm64_top/u_apm64_top/u_apsram_ctrl/tXPHS_cnt_2_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.690, 100.000%
Arrival Data Path Delay	cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.690, 100.000%

Path20

Path Summary:

Slack	0.275
Data Arrival Time	0.986
Data Required Time	0.711
From	inst_apm64_top/u_apm64_top/u_apsram_ctrl/tHS_cnt_2_s0
To	inst_apm64_top/u_apm64_top/u_apsram_ctrl/tHS_cnt_2_s0
Launch Clk	userclk:[R]
Latch Clk	userclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					userclk
0.000	0.000	tCL	RR	2337	TOPSIDE[0]	inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
0.686	0.686	tNET	RR	1	R32C6[1][A]	inst_apm64_top/u_apm64_top/u_apsram_ctrl/tHS_cnt_2_s0/CLK
0.827	0.141	tC2Q	RF	3	R32C6[1][A]	inst_apm64_top/u_apm64_top/u_apsram_ctrl/tHS_cnt_2_s0/Q
0.833	0.006	tNET	FF	1	R32C6[1][A]	inst_apm64_top/u_apm64_top/u_apsram_ctrl/n130_s1/I3
0.986	0.153	tINS	FF	1	R32C6[1][A]	inst_apm64_top/u_apm64_top/u_apsram_ctrl/n130_s1/F
0.986	0.000	tNET	FF	1	R32C6[1][A]	inst_apm64_top/u_apm64_top/u_apsram_ctrl/tHS_cnt_2_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					userclk
0.000	0.000	tCL	RR	2337	TOPSIDE[0]	inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
0.686	0.686	tNET	RR	1	R32C6[1][A]	inst_apm64_top/u_apm64_top/u_apsram_ctrl/tHS_cnt_2_s0/CLK
0.711	0.025	tHld		1	R32C6[1][A]	inst_apm64_top/u_apm64_top/u_apsram_ctrl/tHS_cnt_2_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.686, 100.000%
Arrival Data Path Delay	cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.686, 100.000%

Path21

Path Summary:

Slack	0.275
Data Arrival Time	0.978
Data Required Time	0.703
From	inst_apm64_top/u_apm64_top/u_apsram_ctrl/tHS_cnt_3_s0
To	inst_apm64_top/u_apm64_top/u_apsram_ctrl/tHS_cnt_3_s0
Launch Clk	userclk:[R]
Latch Clk	userclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					userclk
0.000	0.000	tCL	RR	2337	TOPSIDE[0]	inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
0.678	0.678	tNET	RR	1	R30C6[0][A]	inst_apm64_top/u_apm64_top/u_apsram_ctrl/tHS_cnt_3_s0/CLK
0.819	0.141	tC2Q	RF	4	R30C6[0][A]	inst_apm64_top/u_apm64_top/u_apsram_ctrl/tHS_cnt_3_s0/Q
0.825	0.006	tNET	FF	1	R30C6[0][A]	inst_apm64_top/u_apm64_top/u_apsram_ctrl/n129_s3/I2
0.978	0.153	tINS	FF	1	R30C6[0][A]	inst_apm64_top/u_apm64_top/u_apsram_ctrl/n129_s3/F
0.978	0.000	tNET	FF	1	R30C6[0][A]	inst_apm64_top/u_apm64_top/u_apsram_ctrl/tHS_cnt_3_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					userclk
0.000	0.000	tCL	RR	2337	TOPSIDE[0]	inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
0.678	0.678	tNET	RR	1	R30C6[0][A]	inst_apm64_top/u_apm64_top/u_apsram_ctrl/tHS_cnt_3_s0/CLK
0.703	0.025	tHld		1	R30C6[0][A]	inst_apm64_top/u_apm64_top/u_apsram_ctrl/tHS_cnt_3_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.678, 100.000%
Arrival Data Path Delay	cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.678, 100.000%

Path22

Path Summary:

Slack	0.275
Data Arrival Time	0.978
Data Required Time	0.703
From	inst_apm64_top/u_apm64_top/u_apsram_ctrl/tHS_cnt_7_s0
To	inst_apm64_top/u_apm64_top/u_apsram_ctrl/tHS_cnt_7_s0
Launch Clk	userclk:[R]
Latch Clk	userclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					userclk
0.000	0.000	tCL	RR	2337	TOPSIDE[0]	inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
0.678	0.678	tNET	RR	1	R30C6[1][A]	inst_apm64_top/u_apm64_top/u_apsram_ctrl/tHS_cnt_7_s0/CLK
0.819	0.141	tC2Q	RF	5	R30C6[1][A]	inst_apm64_top/u_apm64_top/u_apsram_ctrl/tHS_cnt_7_s0/Q
0.825	0.006	tNET	FF	1	R30C6[1][A]	inst_apm64_top/u_apm64_top/u_apsram_ctrl/n125_s3/I2
0.978	0.153	tINS	FF	1	R30C6[1][A]	inst_apm64_top/u_apm64_top/u_apsram_ctrl/n125_s3/F
0.978	0.000	tNET	FF	1	R30C6[1][A]	inst_apm64_top/u_apm64_top/u_apsram_ctrl/tHS_cnt_7_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					userclk
0.000	0.000	tCL	RR	2337	TOPSIDE[0]	inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
0.678	0.678	tNET	RR	1	R30C6[1][A]	inst_apm64_top/u_apm64_top/u_apsram_ctrl/tHS_cnt_7_s0/CLK
0.703	0.025	tHld		1	R30C6[1][A]	inst_apm64_top/u_apm64_top/u_apsram_ctrl/tHS_cnt_7_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.678, 100.000%
Arrival Data Path Delay	cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.678, 100.000%

Path23

Path Summary:

Slack	0.275
Data Arrival Time	0.986
Data Required Time	0.711
From	inst_apm64_top/u_apm64_top/u_apsram_ctrl/tHS_cnt_8_s0
To	inst_apm64_top/u_apm64_top/u_apsram_ctrl/tHS_cnt_8_s0
Launch Clk	userclk:[R]
Latch Clk	userclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					userclk
0.000	0.000	tCL	RR	2337	TOPSIDE[0]	inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
0.686	0.686	tNET	RR	1	R32C6[0][A]	inst_apm64_top/u_apm64_top/u_apsram_ctrl/tHS_cnt_8_s0/CLK
0.827	0.141	tC2Q	RF	4	R32C6[0][A]	inst_apm64_top/u_apm64_top/u_apsram_ctrl/tHS_cnt_8_s0/Q
0.833	0.006	tNET	FF	1	R32C6[0][A]	inst_apm64_top/u_apm64_top/u_apsram_ctrl/n124_s1/I3
0.986	0.153	tINS	FF	1	R32C6[0][A]	inst_apm64_top/u_apm64_top/u_apsram_ctrl/n124_s1/F
0.986	0.000	tNET	FF	1	R32C6[0][A]	inst_apm64_top/u_apm64_top/u_apsram_ctrl/tHS_cnt_8_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					userclk
0.000	0.000	tCL	RR	2337	TOPSIDE[0]	inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
0.686	0.686	tNET	RR	1	R32C6[0][A]	inst_apm64_top/u_apm64_top/u_apsram_ctrl/tHS_cnt_8_s0/CLK
0.711	0.025	tHld		1	R32C6[0][A]	inst_apm64_top/u_apm64_top/u_apsram_ctrl/tHS_cnt_8_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.686, 100.000%
Arrival Data Path Delay	cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.686, 100.000%

Path24

Path Summary:

Slack	0.275
Data Arrival Time	0.991
Data Required Time	0.716
From	inst_apm64_top/u_apm64_top/u_apsram_ctrl/tXSR_cnt_1_s0
To	inst_apm64_top/u_apm64_top/u_apsram_ctrl/tXSR_cnt_1_s0
Launch Clk	userclk:[R]
Latch Clk	userclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					userclk
0.000	0.000	tCL	RR	2337	TOPSIDE[0]	inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
0.691	0.691	tNET	RR	1	R29C11[1][A]	inst_apm64_top/u_apm64_top/u_apsram_ctrl/tXSR_cnt_1_s0/CLK
0.832	0.141	tC2Q	RF	3	R29C11[1][A]	inst_apm64_top/u_apm64_top/u_apsram_ctrl/tXSR_cnt_1_s0/Q
0.838	0.006	tNET	FF	1	R29C11[1][A]	inst_apm64_top/u_apm64_top/u_apsram_ctrl/n75_s1/I1
0.991	0.153	tINS	FF	1	R29C11[1][A]	inst_apm64_top/u_apm64_top/u_apsram_ctrl/n75_s1/F
0.991	0.000	tNET	FF	1	R29C11[1][A]	inst_apm64_top/u_apm64_top/u_apsram_ctrl/tXSR_cnt_1_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					userclk
0.000	0.000	tCL	RR	2337	TOPSIDE[0]	inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
0.691	0.691	tNET	RR	1	R29C11[1][A]	inst_apm64_top/u_apm64_top/u_apsram_ctrl/tXSR_cnt_1_s0/CLK
0.716	0.025	tHld		1	R29C11[1][A]	inst_apm64_top/u_apm64_top/u_apsram_ctrl/tXSR_cnt_1_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.691, 100.000%
Arrival Data Path Delay	cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.691, 100.000%

Path25

Path Summary:

Slack	0.275
Data Arrival Time	0.997
Data Required Time	0.722
From	inst_apm64_top/u_apm64_top/u_cmd_fifo/addr_2_s1
To	inst_apm64_top/u_apm64_top/u_cmd_fifo/addr_2_s1
Launch Clk	userclk:[R]
Latch Clk	userclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					userclk
0.000	0.000	tCL	RR	2337	TOPSIDE[0]	inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
0.697	0.697	tNET	RR	1	R17C7[1][A]	inst_apm64_top/u_apm64_top/u_cmd_fifo/addr_2_s1/CLK
0.838	0.141	tC2Q	RF	3	R17C7[1][A]	inst_apm64_top/u_apm64_top/u_cmd_fifo/addr_2_s1/Q
0.844	0.006	tNET	FF	1	R17C7[1][A]	inst_apm64_top/u_apm64_top/u_cmd_fifo/n57_s0/I2
0.997	0.153	tINS	FF	1	R17C7[1][A]	inst_apm64_top/u_apm64_top/u_cmd_fifo/n57_s0/F
0.997	0.000	tNET	FF	1	R17C7[1][A]	inst_apm64_top/u_apm64_top/u_cmd_fifo/addr_2_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					userclk
0.000	0.000	tCL	RR	2337	TOPSIDE[0]	inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
0.697	0.697	tNET	RR	1	R17C7[1][A]	inst_apm64_top/u_apm64_top/u_cmd_fifo/addr_2_s1/CLK
0.722	0.025	tHld		1	R17C7[1][A]	inst_apm64_top/u_apm64_top/u_cmd_fifo/addr_2_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.697, 100.000%
Arrival Data Path Delay	cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.697, 100.000%

Recovery Analysis Report

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	4.993
Data Arrival Time	6.108
Data Required Time	11.101
From	inst_apm64_top/u_apm64_top/u_apsram_sync/dll_rst_s0
To	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[0].u_apm64_data_lane/u_dqs
Launch Clk	clkin:[R]
Latch Clk	userclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOB26[A]	clk_ibuf/I
0.587	0.587	tINS	RR	81	IOB26[A]	clk_ibuf/O
2.159	1.572	tNET	RR	1	R2C2[1][A]	inst_apm64_top/u_apm64_top/u_apsram_sync/dll_rst_s0/CLK
2.465	0.306	tC2Q	RR	3	R2C2[1][A]	inst_apm64_top/u_apm64_top/u_apsram_sync/dll_rst_s0/Q
3.452	0.987	tNET	RR	1	R9C20[3][B]	inst_apm64_top/u_apm64_top/u_apsram_sync/ddr_rsti_s0/I1
3.798	0.346	tINS	RF	1549	R9C20[3][B]	inst_apm64_top/u_apm64_top/u_apsram_sync/ddr_rsti_s0/F
6.108	2.309	tNET	FF	10	R0C82	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[0].u_apm64_data_lane/u_dqs/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					userclk
10.000	0.000	tCL	RR	2337	TOPSIDE[0]	inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
11.565	1.565	tNET	RR	1	R0C82	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[0].u_apm64_data_lane/u_dqs/PCLK
11.530	-0.035	tUnc				inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[0].u_apm64_data_lane/u_dqs
11.101	-0.429	tSu		1	R0C82	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[0].u_apm64_data_lane/u_dqs

Path Statistics:

Clock Skew	-0.594
Setup Relationship	10.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.587, 27.181%; route: 1.572, 72.819%
Arrival Data Path Delay	cell: 0.346, 8.763%; route: 3.296, 83.486%; tC2Q: 0.306, 7.750%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.565, 100.000%

Path2

Path Summary:

Slack	5.008
Data Arrival Time	6.108
Data Required Time	11.116
From	inst_apm64_top/u_apm64_top/u_apsram_sync/dll_rst_s0
To	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_dqs
Launch Clk	clkin:[R]
Latch Clk	userclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOB26[A]	clk_ibuf/I
0.587	0.587	tINS	RR	81	IOB26[A]	clk_ibuf/O
2.159	1.572	tNET	RR	1	R2C2[1][A]	inst_apm64_top/u_apm64_top/u_apsram_sync/dll_rst_s0/CLK
2.465	0.306	tC2Q	RR	3	R2C2[1][A]	inst_apm64_top/u_apm64_top/u_apsram_sync/dll_rst_s0/Q
3.452	0.987	tNET	RR	1	R9C20[3][B]	inst_apm64_top/u_apm64_top/u_apsram_sync/ddr_rsti_s0/I1
3.798	0.346	tINS	RF	1549	R9C20[3][B]	inst_apm64_top/u_apm64_top/u_apsram_sync/ddr_rsti_s0/F
6.108	2.309	tNET	FF	10	R0C60	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_dqs/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					userclk
10.000	0.000	tCL	RR	2337	TOPSIDE[0]	inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
11.580	1.580	tNET	RR	1	R0C60	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_dqs/PCLK
11.545	-0.035	tUnc				inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_dqs
11.116	-0.429	tSu		1	R0C60	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_dqs

Path Statistics:

Clock Skew	-0.579
Setup Relationship	10.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.587, 27.181%; route: 1.572, 72.819%
Arrival Data Path Delay	cell: 0.346, 8.763%; route: 3.296, 83.486%; tC2Q: 0.306, 7.750%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.580, 100.000%

Path3

Path Summary:

Slack	5.132
Data Arrival Time	6.077
Data Required Time	11.208
From	inst_apm64_top/u_apm64_top/u_apsram_sync/dll_rst_s0
To	inst_apm64_top/u_apm64_top/u_apsram_init/timer_cnt0_4_s3
Launch Clk	clkin:[R]
Latch Clk	userclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOB26[A]	clk_ibuf/I
0.587	0.587	tINS	RR	81	IOB26[A]	clk_ibuf/O
2.159	1.572	tNET	RR	1	R2C2[1][A]	inst_apm64_top/u_apm64_top/u_apsram_sync/dll_rst_s0/CLK
2.465	0.306	tC2Q	RR	3	R2C2[1][A]	inst_apm64_top/u_apm64_top/u_apsram_sync/dll_rst_s0/Q
3.452	0.987	tNET	RR	1	R9C20[3][B]	inst_apm64_top/u_apm64_top/u_apsram_sync/ddr_rsti_s0/I1
3.798	0.346	tINS	RF	1549	R9C20[3][B]	inst_apm64_top/u_apm64_top/u_apsram_sync/ddr_rsti_s0/F
6.077	2.278	tNET	FF	1	R13C6[0][A]	inst_apm64_top/u_apm64_top/u_apsram_init/timer_cnt0_4_s3/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					userclk
10.000	0.000	tCL	RR	2337	TOPSIDE[0]	inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
11.521	1.521	tNET	RR	1	R13C6[0][A]	inst_apm64_top/u_apm64_top/u_apsram_init/timer_cnt0_4_s3/CLK
11.486	-0.035	tUnc				inst_apm64_top/u_apm64_top/u_apsram_init/timer_cnt0_4_s3
11.208	-0.278	tSu		1	R13C6[0][A]	inst_apm64_top/u_apm64_top/u_apsram_init/timer_cnt0_4_s3

Path Statistics:

Clock Skew	-0.638
Setup Relationship	10.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.587, 27.181%; route: 1.572, 72.819%
Arrival Data Path Delay	cell: 0.346, 8.833%; route: 3.265, 83.356%; tC2Q: 0.306, 7.812%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.521, 100.000%

Path4

Path Summary:

Slack	5.132
Data Arrival Time	6.077
Data Required Time	11.208
From	inst_apm64_top/u_apm64_top/u_apsram_sync/dll_rst_s0
To	inst_apm64_top/u_apm64_top/u_apsram_init/rdback_check_cnt_5_s1
Launch Clk	clkin:[R]
Latch Clk	userclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOB26[A]	clk_ibuf/I
0.587	0.587	tINS	RR	81	IOB26[A]	clk_ibuf/O
2.159	1.572	tNET	RR	1	R2C2[1][A]	inst_apm64_top/u_apm64_top/u_apsram_sync/dll_rst_s0/CLK
2.465	0.306	tC2Q	RR	3	R2C2[1][A]	inst_apm64_top/u_apm64_top/u_apsram_sync/dll_rst_s0/Q
3.452	0.987	tNET	RR	1	R9C20[3][B]	inst_apm64_top/u_apm64_top/u_apsram_sync/ddr_rsti_s0/I1
3.798	0.346	tINS	RF	1549	R9C20[3][B]	inst_apm64_top/u_apm64_top/u_apsram_sync/ddr_rsti_s0/F
6.077	2.278	tNET	FF	1	R13C6[2][A]	inst_apm64_top/u_apm64_top/u_apsram_init/rdback_check_cnt_5_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					userclk
10.000	0.000	tCL	RR	2337	TOPSIDE[0]	inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
11.521	1.521	tNET	RR	1	R13C6[2][A]	inst_apm64_top/u_apm64_top/u_apsram_init/rdback_check_cnt_5_s1/CLK
11.486	-0.035	tUnc				inst_apm64_top/u_apm64_top/u_apsram_init/rdback_check_cnt_5_s1
11.208	-0.278	tSu		1	R13C6[2][A]	inst_apm64_top/u_apm64_top/u_apsram_init/rdback_check_cnt_5_s1

Path Statistics:

Clock Skew	-0.638
Setup Relationship	10.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.587, 27.181%; route: 1.572, 72.819%
Arrival Data Path Delay	cell: 0.346, 8.833%; route: 3.265, 83.356%; tC2Q: 0.306, 7.812%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.521, 100.000%

Path5

Path Summary:

Slack	5.132
Data Arrival Time	6.077
Data Required Time	11.208
From	inst_apm64_top/u_apm64_top/u_apsram_sync/dll_rst_s0
To	inst_apm64_top/u_apm64_top/u_apsram_init/timer_cnt0_3_s1
Launch Clk	clkin:[R]
Latch Clk	userclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOB26[A]	clk_ibuf/I
0.587	0.587	tINS	RR	81	IOB26[A]	clk_ibuf/O
2.159	1.572	tNET	RR	1	R2C2[1][A]	inst_apm64_top/u_apm64_top/u_apsram_sync/dll_rst_s0/CLK
2.465	0.306	tC2Q	RR	3	R2C2[1][A]	inst_apm64_top/u_apm64_top/u_apsram_sync/dll_rst_s0/Q
3.452	0.987	tNET	RR	1	R9C20[3][B]	inst_apm64_top/u_apm64_top/u_apsram_sync/ddr_rsti_s0/I1
3.798	0.346	tINS	RF	1549	R9C20[3][B]	inst_apm64_top/u_apm64_top/u_apsram_sync/ddr_rsti_s0/F
6.077	2.278	tNET	FF	1	R13C6[1][B]	inst_apm64_top/u_apm64_top/u_apsram_init/timer_cnt0_3_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					userclk
10.000	0.000	tCL	RR	2337	TOPSIDE[0]	inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
11.521	1.521	tNET	RR	1	R13C6[1][B]	inst_apm64_top/u_apm64_top/u_apsram_init/timer_cnt0_3_s1/CLK
11.486	-0.035	tUnc				inst_apm64_top/u_apm64_top/u_apsram_init/timer_cnt0_3_s1
11.208	-0.278	tSu		1	R13C6[1][B]	inst_apm64_top/u_apm64_top/u_apsram_init/timer_cnt0_3_s1

Path Statistics:

Clock Skew	-0.638
Setup Relationship	10.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.587, 27.181%; route: 1.572, 72.819%
Arrival Data Path Delay	cell: 0.346, 8.833%; route: 3.265, 83.356%; tC2Q: 0.306, 7.812%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.521, 100.000%

Path6

Path Summary:

Slack	5.132
Data Arrival Time	6.077
Data Required Time	11.208
From	inst_apm64_top/u_apm64_top/u_apsram_sync/dll_rst_s0
To	inst_apm64_top/u_apm64_top/u_apsram_init/timer_cnt0_5_s1
Launch Clk	clkin:[R]
Latch Clk	userclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOB26[A]	clk_ibuf/I
0.587	0.587	tINS	RR	81	IOB26[A]	clk_ibuf/O
2.159	1.572	tNET	RR	1	R2C2[1][A]	inst_apm64_top/u_apm64_top/u_apsram_sync/dll_rst_s0/CLK
2.465	0.306	tC2Q	RR	3	R2C2[1][A]	inst_apm64_top/u_apm64_top/u_apsram_sync/dll_rst_s0/Q
3.452	0.987	tNET	RR	1	R9C20[3][B]	inst_apm64_top/u_apm64_top/u_apsram_sync/ddr_rsti_s0/I1
3.798	0.346	tINS	RF	1549	R9C20[3][B]	inst_apm64_top/u_apm64_top/u_apsram_sync/ddr_rsti_s0/F
6.077	2.278	tNET	FF	1	R13C6[1][A]	inst_apm64_top/u_apm64_top/u_apsram_init/timer_cnt0_5_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					userclk
10.000	0.000	tCL	RR	2337	TOPSIDE[0]	inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
11.521	1.521	tNET	RR	1	R13C6[1][A]	inst_apm64_top/u_apm64_top/u_apsram_init/timer_cnt0_5_s1/CLK
11.486	-0.035	tUnc				inst_apm64_top/u_apm64_top/u_apsram_init/timer_cnt0_5_s1
11.208	-0.278	tSu		1	R13C6[1][A]	inst_apm64_top/u_apm64_top/u_apsram_init/timer_cnt0_5_s1

Path Statistics:

Clock Skew	-0.638
Setup Relationship	10.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.587, 27.181%; route: 1.572, 72.819%
Arrival Data Path Delay	cell: 0.346, 8.833%; route: 3.265, 83.356%; tC2Q: 0.306, 7.812%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.521, 100.000%

Path7

Path Summary:

Slack	5.132
Data Arrival Time	6.077
Data Required Time	11.208
From	inst_apm64_top/u_apm64_top/u_apsram_sync/dll_rst_s0
To	inst_apm64_top/u_apm64_top/u_apsram_init/write_done_s0
Launch Clk	clkin:[R]
Latch Clk	userclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOB26[A]	clk_ibuf/I
0.587	0.587	tINS	RR	81	IOB26[A]	clk_ibuf/O
2.159	1.572	tNET	RR	1	R2C2[1][A]	inst_apm64_top/u_apm64_top/u_apsram_sync/dll_rst_s0/CLK
2.465	0.306	tC2Q	RR	3	R2C2[1][A]	inst_apm64_top/u_apm64_top/u_apsram_sync/dll_rst_s0/Q
3.452	0.987	tNET	RR	1	R9C20[3][B]	inst_apm64_top/u_apm64_top/u_apsram_sync/ddr_rsti_s0/I1
3.798	0.346	tINS	RF	1549	R9C20[3][B]	inst_apm64_top/u_apm64_top/u_apsram_sync/ddr_rsti_s0/F
6.077	2.278	tNET	FF	1	R13C6[0][B]	inst_apm64_top/u_apm64_top/u_apsram_init/write_done_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					userclk
10.000	0.000	tCL	RR	2337	TOPSIDE[0]	inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
11.521	1.521	tNET	RR	1	R13C6[0][B]	inst_apm64_top/u_apm64_top/u_apsram_init/write_done_s0/CLK
11.486	-0.035	tUnc				inst_apm64_top/u_apm64_top/u_apsram_init/write_done_s0
11.208	-0.278	tSu		1	R13C6[0][B]	inst_apm64_top/u_apm64_top/u_apsram_init/write_done_s0

Path Statistics:

Clock Skew	-0.638
Setup Relationship	10.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.587, 27.181%; route: 1.572, 72.819%
Arrival Data Path Delay	cell: 0.346, 8.833%; route: 3.265, 83.356%; tC2Q: 0.306, 7.812%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.521, 100.000%

Path8

Path Summary:

Slack	5.132
Data Arrival Time	6.077
Data Required Time	11.208
From	inst_apm64_top/u_apm64_top/u_apsram_sync/dll_rst_s0
To	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/of_RdData_reg_10_s0
Launch Clk	clkin:[R]
Latch Clk	userclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOB26[A]	clk_ibuf/I
0.587	0.587	tINS	RR	81	IOB26[A]	clk_ibuf/O
2.159	1.572	tNET	RR	1	R2C2[1][A]	inst_apm64_top/u_apm64_top/u_apsram_sync/dll_rst_s0/CLK
2.465	0.306	tC2Q	RR	3	R2C2[1][A]	inst_apm64_top/u_apm64_top/u_apsram_sync/dll_rst_s0/Q
3.452	0.987	tNET	RR	1	R9C20[3][B]	inst_apm64_top/u_apm64_top/u_apsram_sync/ddr_rsti_s0/I1
3.798	0.346	tINS	RF	1549	R9C20[3][B]	inst_apm64_top/u_apm64_top/u_apsram_sync/ddr_rsti_s0/F
6.077	2.278	tNET	FF	1	R31C30[1][A]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/of_RdData_reg_10_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					userclk
10.000	0.000	tCL	RR	2337	TOPSIDE[0]	inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
11.521	1.521	tNET	RR	1	R31C30[1][A]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/of_RdData_reg_10_s0/CLK
11.486	-0.035	tUnc				inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/of_RdData_reg_10_s0
11.208	-0.278	tSu		1	R31C30[1][A]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/of_RdData_reg_10_s0

Path Statistics:

Clock Skew	-0.638
Setup Relationship	10.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.587, 27.181%; route: 1.572, 72.819%
Arrival Data Path Delay	cell: 0.346, 8.833%; route: 3.265, 83.356%; tC2Q: 0.306, 7.812%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.521, 100.000%

Path9

Path Summary:

Slack	5.132
Data Arrival Time	6.081
Data Required Time	11.213
From	inst_apm64_top/u_apm64_top/u_apsram_sync/dll_rst_s0
To	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/of_RdData_reg_18_s0
Launch Clk	clkin:[R]
Latch Clk	userclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOB26[A]	clk_ibuf/I
0.587	0.587	tINS	RR	81	IOB26[A]	clk_ibuf/O
2.159	1.572	tNET	RR	1	R2C2[1][A]	inst_apm64_top/u_apm64_top/u_apsram_sync/dll_rst_s0/CLK
2.465	0.306	tC2Q	RR	3	R2C2[1][A]	inst_apm64_top/u_apm64_top/u_apsram_sync/dll_rst_s0/Q
3.452	0.987	tNET	RR	1	R9C20[3][B]	inst_apm64_top/u_apm64_top/u_apsram_sync/ddr_rsti_s0/I1
3.798	0.346	tINS	RF	1549	R9C20[3][B]	inst_apm64_top/u_apm64_top/u_apsram_sync/ddr_rsti_s0/F
6.081	2.283	tNET	FF	1	R32C22[0][A]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/of_RdData_reg_18_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					userclk
10.000	0.000	tCL	RR	2337	TOPSIDE[0]	inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
11.526	1.526	tNET	RR	1	R32C22[0][A]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/of_RdData_reg_18_s0/CLK
11.491	-0.035	tUnc				inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/of_RdData_reg_18_s0
11.213	-0.278	tSu		1	R32C22[0][A]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/of_RdData_reg_18_s0

Path Statistics:

Clock Skew	-0.633
Setup Relationship	10.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.587, 27.181%; route: 1.572, 72.819%
Arrival Data Path Delay	cell: 0.346, 8.822%; route: 3.270, 83.376%; tC2Q: 0.306, 7.802%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.526, 100.000%

Path10

Path Summary:

Slack	5.132
Data Arrival Time	6.081
Data Required Time	11.213
From	inst_apm64_top/u_apm64_top/u_apsram_sync/dll_rst_s0
To	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/of_RdData_reg_25_s0
Launch Clk	clkin:[R]
Latch Clk	userclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOB26[A]	clk_ibuf/I
0.587	0.587	tINS	RR	81	IOB26[A]	clk_ibuf/O
2.159	1.572	tNET	RR	1	R2C2[1][A]	inst_apm64_top/u_apm64_top/u_apsram_sync/dll_rst_s0/CLK
2.465	0.306	tC2Q	RR	3	R2C2[1][A]	inst_apm64_top/u_apm64_top/u_apsram_sync/dll_rst_s0/Q
3.452	0.987	tNET	RR	1	R9C20[3][B]	inst_apm64_top/u_apm64_top/u_apsram_sync/ddr_rsti_s0/I1
3.798	0.346	tINS	RF	1549	R9C20[3][B]	inst_apm64_top/u_apm64_top/u_apsram_sync/ddr_rsti_s0/F
6.081	2.283	tNET	FF	1	R32C26[0][A]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/of_RdData_reg_25_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					userclk
10.000	0.000	tCL	RR	2337	TOPSIDE[0]	inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
11.526	1.526	tNET	RR	1	R32C26[0][A]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/of_RdData_reg_25_s0/CLK
11.491	-0.035	tUnc				inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/of_RdData_reg_25_s0
11.213	-0.278	tSu		1	R32C26[0][A]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/of_RdData_reg_25_s0

Path Statistics:

Clock Skew	-0.633
Setup Relationship	10.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.587, 27.181%; route: 1.572, 72.819%
Arrival Data Path Delay	cell: 0.346, 8.822%; route: 3.270, 83.376%; tC2Q: 0.306, 7.802%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.526, 100.000%

Path11

Path Summary:

Slack	5.132
Data Arrival Time	6.077
Data Required Time	11.208
From	inst_apm64_top/u_apm64_top/u_apsram_sync/dll_rst_s0
To	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/wr_dq_r_14_s0
Launch Clk	clkin:[R]
Latch Clk	userclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOB26[A]	clk_ibuf/I
0.587	0.587	tINS	RR	81	IOB26[A]	clk_ibuf/O
2.159	1.572	tNET	RR	1	R2C2[1][A]	inst_apm64_top/u_apm64_top/u_apsram_sync/dll_rst_s0/CLK
2.465	0.306	tC2Q	RR	3	R2C2[1][A]	inst_apm64_top/u_apm64_top/u_apsram_sync/dll_rst_s0/Q
3.452	0.987	tNET	RR	1	R9C20[3][B]	inst_apm64_top/u_apm64_top/u_apsram_sync/ddr_rsti_s0/I1
3.798	0.346	tINS	RF	1549	R9C20[3][B]	inst_apm64_top/u_apm64_top/u_apsram_sync/ddr_rsti_s0/F
6.077	2.278	tNET	FF	1	R31C30[3][A]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/wr_dq_r_14_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					userclk
10.000	0.000	tCL	RR	2337	TOPSIDE[0]	inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
11.521	1.521	tNET	RR	1	R31C30[3][A]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/wr_dq_r_14_s0/CLK
11.486	-0.035	tUnc				inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/wr_dq_r_14_s0
11.208	-0.278	tSu		1	R31C30[3][A]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/wr_dq_r_14_s0

Path Statistics:

Clock Skew	-0.638
Setup Relationship	10.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.587, 27.181%; route: 1.572, 72.819%
Arrival Data Path Delay	cell: 0.346, 8.833%; route: 3.265, 83.356%; tC2Q: 0.306, 7.812%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.521, 100.000%

Path12

Path Summary:

Slack	5.132
Data Arrival Time	6.077
Data Required Time	11.208
From	inst_apm64_top/u_apm64_top/u_apsram_sync/dll_rst_s0
To	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/wr_dq_r_15_s0
Launch Clk	clkin:[R]
Latch Clk	userclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOB26[A]	clk_ibuf/I
0.587	0.587	tINS	RR	81	IOB26[A]	clk_ibuf/O
2.159	1.572	tNET	RR	1	R2C2[1][A]	inst_apm64_top/u_apm64_top/u_apsram_sync/dll_rst_s0/CLK
2.465	0.306	tC2Q	RR	3	R2C2[1][A]	inst_apm64_top/u_apm64_top/u_apsram_sync/dll_rst_s0/Q
3.452	0.987	tNET	RR	1	R9C20[3][B]	inst_apm64_top/u_apm64_top/u_apsram_sync/ddr_rsti_s0/I1
3.798	0.346	tINS	RF	1549	R9C20[3][B]	inst_apm64_top/u_apm64_top/u_apsram_sync/ddr_rsti_s0/F
6.077	2.278	tNET	FF	1	R31C30[2][A]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/wr_dq_r_15_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					userclk
10.000	0.000	tCL	RR	2337	TOPSIDE[0]	inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
11.521	1.521	tNET	RR	1	R31C30[2][A]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/wr_dq_r_15_s0/CLK
11.486	-0.035	tUnc				inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/wr_dq_r_15_s0
11.208	-0.278	tSu		1	R31C30[2][A]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/wr_dq_r_15_s0

Path Statistics:

Clock Skew	-0.638
Setup Relationship	10.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.587, 27.181%; route: 1.572, 72.819%
Arrival Data Path Delay	cell: 0.346, 8.833%; route: 3.265, 83.356%; tC2Q: 0.306, 7.812%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.521, 100.000%

Path13

Path Summary:

Slack	5.132
Data Arrival Time	6.081
Data Required Time	11.213
From	inst_apm64_top/u_apm64_top/u_apsram_sync/dll_rst_s0
To	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/wr_dq_r_22_s0
Launch Clk	clkin:[R]
Latch Clk	userclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOB26[A]	clk_ibuf/I
0.587	0.587	tINS	RR	81	IOB26[A]	clk_ibuf/O
2.159	1.572	tNET	RR	1	R2C2[1][A]	inst_apm64_top/u_apm64_top/u_apsram_sync/dll_rst_s0/CLK
2.465	0.306	tC2Q	RR	3	R2C2[1][A]	inst_apm64_top/u_apm64_top/u_apsram_sync/dll_rst_s0/Q
3.452	0.987	tNET	RR	1	R9C20[3][B]	inst_apm64_top/u_apm64_top/u_apsram_sync/ddr_rsti_s0/I1
3.798	0.346	tINS	RF	1549	R9C20[3][B]	inst_apm64_top/u_apm64_top/u_apsram_sync/ddr_rsti_s0/F
6.081	2.283	tNET	FF	1	R32C22[1][B]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/wr_dq_r_22_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					userclk
10.000	0.000	tCL	RR	2337	TOPSIDE[0]	inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
11.526	1.526	tNET	RR	1	R32C22[1][B]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/wr_dq_r_22_s0/CLK
11.491	-0.035	tUnc				inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/wr_dq_r_22_s0
11.213	-0.278	tSu		1	R32C22[1][B]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/wr_dq_r_22_s0

Path Statistics:

Clock Skew	-0.633
Setup Relationship	10.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.587, 27.181%; route: 1.572, 72.819%
Arrival Data Path Delay	cell: 0.346, 8.822%; route: 3.270, 83.376%; tC2Q: 0.306, 7.802%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.526, 100.000%

Path14

Path Summary:

Slack	5.132
Data Arrival Time	6.081
Data Required Time	11.213
From	inst_apm64_top/u_apm64_top/u_apsram_sync/dll_rst_s0
To	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/wr_dq_r_29_s0
Launch Clk	clkin:[R]
Latch Clk	userclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOB26[A]	clk_ibuf/I
0.587	0.587	tINS	RR	81	IOB26[A]	clk_ibuf/O
2.159	1.572	tNET	RR	1	R2C2[1][A]	inst_apm64_top/u_apm64_top/u_apsram_sync/dll_rst_s0/CLK
2.465	0.306	tC2Q	RR	3	R2C2[1][A]	inst_apm64_top/u_apm64_top/u_apsram_sync/dll_rst_s0/Q
3.452	0.987	tNET	RR	1	R9C20[3][B]	inst_apm64_top/u_apm64_top/u_apsram_sync/ddr_rsti_s0/I1
3.798	0.346	tINS	RF	1549	R9C20[3][B]	inst_apm64_top/u_apm64_top/u_apsram_sync/ddr_rsti_s0/F
6.081	2.283	tNET	FF	1	R32C26[1][B]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/wr_dq_r_29_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					userclk
10.000	0.000	tCL	RR	2337	TOPSIDE[0]	inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
11.526	1.526	tNET	RR	1	R32C26[1][B]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/wr_dq_r_29_s0/CLK
11.491	-0.035	tUnc				inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/wr_dq_r_29_s0
11.213	-0.278	tSu		1	R32C26[1][B]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/wr_dq_r_29_s0

Path Statistics:

Clock Skew	-0.633
Setup Relationship	10.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.587, 27.181%; route: 1.572, 72.819%
Arrival Data Path Delay	cell: 0.346, 8.822%; route: 3.270, 83.376%; tC2Q: 0.306, 7.802%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.526, 100.000%

Path15

Path Summary:

Slack	5.132
Data Arrival Time	6.077
Data Required Time	11.208
From	inst_apm64_top/u_apm64_top/u_apsram_sync/dll_rst_s0
To	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/wr_dq_15_s0
Launch Clk	clkin:[R]
Latch Clk	userclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOB26[A]	clk_ibuf/I
0.587	0.587	tINS	RR	81	IOB26[A]	clk_ibuf/O
2.159	1.572	tNET	RR	1	R2C2[1][A]	inst_apm64_top/u_apm64_top/u_apsram_sync/dll_rst_s0/CLK
2.465	0.306	tC2Q	RR	3	R2C2[1][A]	inst_apm64_top/u_apm64_top/u_apsram_sync/dll_rst_s0/Q
3.452	0.987	tNET	RR	1	R9C20[3][B]	inst_apm64_top/u_apm64_top/u_apsram_sync/ddr_rsti_s0/I1
3.798	0.346	tINS	RF	1549	R9C20[3][B]	inst_apm64_top/u_apm64_top/u_apsram_sync/ddr_rsti_s0/F
6.077	2.278	tNET	FF	1	R31C30[2][B]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/wr_dq_15_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					userclk
10.000	0.000	tCL	RR	2337	TOPSIDE[0]	inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
11.521	1.521	tNET	RR	1	R31C30[2][B]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/wr_dq_15_s0/CLK
11.486	-0.035	tUnc				inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/wr_dq_15_s0
11.208	-0.278	tSu		1	R31C30[2][B]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/wr_dq_15_s0

Path Statistics:

Clock Skew	-0.638
Setup Relationship	10.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.587, 27.181%; route: 1.572, 72.819%
Arrival Data Path Delay	cell: 0.346, 8.833%; route: 3.265, 83.356%; tC2Q: 0.306, 7.812%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.521, 100.000%

Path16

Path Summary:

Slack	5.132
Data Arrival Time	6.081
Data Required Time	11.213
From	inst_apm64_top/u_apm64_top/u_apsram_sync/dll_rst_s0
To	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/wr_dq_22_s0
Launch Clk	clkin:[R]
Latch Clk	userclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOB26[A]	clk_ibuf/I
0.587	0.587	tINS	RR	81	IOB26[A]	clk_ibuf/O
2.159	1.572	tNET	RR	1	R2C2[1][A]	inst_apm64_top/u_apm64_top/u_apsram_sync/dll_rst_s0/CLK
2.465	0.306	tC2Q	RR	3	R2C2[1][A]	inst_apm64_top/u_apm64_top/u_apsram_sync/dll_rst_s0/Q
3.452	0.987	tNET	RR	1	R9C20[3][B]	inst_apm64_top/u_apm64_top/u_apsram_sync/ddr_rsti_s0/I1
3.798	0.346	tINS	RF	1549	R9C20[3][B]	inst_apm64_top/u_apm64_top/u_apsram_sync/ddr_rsti_s0/F
6.081	2.283	tNET	FF	1	R32C22[2][A]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/wr_dq_22_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					userclk
10.000	0.000	tCL	RR	2337	TOPSIDE[0]	inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
11.526	1.526	tNET	RR	1	R32C22[2][A]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/wr_dq_22_s0/CLK
11.491	-0.035	tUnc				inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/wr_dq_22_s0
11.213	-0.278	tSu		1	R32C22[2][A]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/wr_dq_22_s0

Path Statistics:

Clock Skew	-0.633
Setup Relationship	10.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.587, 27.181%; route: 1.572, 72.819%
Arrival Data Path Delay	cell: 0.346, 8.822%; route: 3.270, 83.376%; tC2Q: 0.306, 7.802%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.526, 100.000%

Path17

Path Summary:

Slack	5.132
Data Arrival Time	6.081
Data Required Time	11.213
From	inst_apm64_top/u_apm64_top/u_apsram_sync/dll_rst_s0
To	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/wr_dq_29_s0
Launch Clk	clkin:[R]
Latch Clk	userclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOB26[A]	clk_ibuf/I
0.587	0.587	tINS	RR	81	IOB26[A]	clk_ibuf/O
2.159	1.572	tNET	RR	1	R2C2[1][A]	inst_apm64_top/u_apm64_top/u_apsram_sync/dll_rst_s0/CLK
2.465	0.306	tC2Q	RR	3	R2C2[1][A]	inst_apm64_top/u_apm64_top/u_apsram_sync/dll_rst_s0/Q
3.452	0.987	tNET	RR	1	R9C20[3][B]	inst_apm64_top/u_apm64_top/u_apsram_sync/ddr_rsti_s0/I1
3.798	0.346	tINS	RF	1549	R9C20[3][B]	inst_apm64_top/u_apm64_top/u_apsram_sync/ddr_rsti_s0/F
6.081	2.283	tNET	FF	1	R32C26[2][A]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/wr_dq_29_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					userclk
10.000	0.000	tCL	RR	2337	TOPSIDE[0]	inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
11.526	1.526	tNET	RR	1	R32C26[2][A]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/wr_dq_29_s0/CLK
11.491	-0.035	tUnc				inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/wr_dq_29_s0
11.213	-0.278	tSu		1	R32C26[2][A]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/wr_dq_29_s0

Path Statistics:

Clock Skew	-0.633
Setup Relationship	10.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.587, 27.181%; route: 1.572, 72.819%
Arrival Data Path Delay	cell: 0.346, 8.822%; route: 3.270, 83.376%; tC2Q: 0.306, 7.802%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.526, 100.000%

Path18

Path Summary:

Slack	5.132
Data Arrival Time	6.077
Data Required Time	11.208
From	inst_apm64_top/u_apm64_top/u_apsram_sync/dll_rst_s0
To	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/wr_dq_d1_15_s0
Launch Clk	clkin:[R]
Latch Clk	userclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOB26[A]	clk_ibuf/I
0.587	0.587	tINS	RR	81	IOB26[A]	clk_ibuf/O
2.159	1.572	tNET	RR	1	R2C2[1][A]	inst_apm64_top/u_apm64_top/u_apsram_sync/dll_rst_s0/CLK
2.465	0.306	tC2Q	RR	3	R2C2[1][A]	inst_apm64_top/u_apm64_top/u_apsram_sync/dll_rst_s0/Q
3.452	0.987	tNET	RR	1	R9C20[3][B]	inst_apm64_top/u_apm64_top/u_apsram_sync/ddr_rsti_s0/I1
3.798	0.346	tINS	RF	1549	R9C20[3][B]	inst_apm64_top/u_apm64_top/u_apsram_sync/ddr_rsti_s0/F
6.077	2.278	tNET	FF	1	R31C30[0][B]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/wr_dq_d1_15_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					userclk
10.000	0.000	tCL	RR	2337	TOPSIDE[0]	inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
11.521	1.521	tNET	RR	1	R31C30[0][B]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/wr_dq_d1_15_s0/CLK
11.486	-0.035	tUnc				inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/wr_dq_d1_15_s0
11.208	-0.278	tSu		1	R31C30[0][B]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/wr_dq_d1_15_s0

Path Statistics:

Clock Skew	-0.638
Setup Relationship	10.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.587, 27.181%; route: 1.572, 72.819%
Arrival Data Path Delay	cell: 0.346, 8.833%; route: 3.265, 83.356%; tC2Q: 0.306, 7.812%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.521, 100.000%

Path19

Path Summary:

Slack	5.132
Data Arrival Time	6.081
Data Required Time	11.213
From	inst_apm64_top/u_apm64_top/u_apsram_sync/dll_rst_s0
To	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/wr_dq_d1_22_s0
Launch Clk	clkin:[R]
Latch Clk	userclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOB26[A]	clk_ibuf/I
0.587	0.587	tINS	RR	81	IOB26[A]	clk_ibuf/O
2.159	1.572	tNET	RR	1	R2C2[1][A]	inst_apm64_top/u_apm64_top/u_apsram_sync/dll_rst_s0/CLK
2.465	0.306	tC2Q	RR	3	R2C2[1][A]	inst_apm64_top/u_apm64_top/u_apsram_sync/dll_rst_s0/Q
3.452	0.987	tNET	RR	1	R9C20[3][B]	inst_apm64_top/u_apm64_top/u_apsram_sync/ddr_rsti_s0/I1
3.798	0.346	tINS	RF	1549	R9C20[3][B]	inst_apm64_top/u_apm64_top/u_apsram_sync/ddr_rsti_s0/F
6.081	2.283	tNET	FF	1	R32C22[1][A]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/wr_dq_d1_22_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					userclk
10.000	0.000	tCL	RR	2337	TOPSIDE[0]	inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
11.526	1.526	tNET	RR	1	R32C22[1][A]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/wr_dq_d1_22_s0/CLK
11.491	-0.035	tUnc				inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/wr_dq_d1_22_s0
11.213	-0.278	tSu		1	R32C22[1][A]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/wr_dq_d1_22_s0

Path Statistics:

Clock Skew	-0.633
Setup Relationship	10.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.587, 27.181%; route: 1.572, 72.819%
Arrival Data Path Delay	cell: 0.346, 8.822%; route: 3.270, 83.376%; tC2Q: 0.306, 7.802%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.526, 100.000%

Path20

Path Summary:

Slack	5.132
Data Arrival Time	6.081
Data Required Time	11.213
From	inst_apm64_top/u_apm64_top/u_apsram_sync/dll_rst_s0
To	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/wr_dq_d1_29_s0
Launch Clk	clkin:[R]
Latch Clk	userclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOB26[A]	clk_ibuf/I
0.587	0.587	tINS	RR	81	IOB26[A]	clk_ibuf/O
2.159	1.572	tNET	RR	1	R2C2[1][A]	inst_apm64_top/u_apm64_top/u_apsram_sync/dll_rst_s0/CLK
2.465	0.306	tC2Q	RR	3	R2C2[1][A]	inst_apm64_top/u_apm64_top/u_apsram_sync/dll_rst_s0/Q
3.452	0.987	tNET	RR	1	R9C20[3][B]	inst_apm64_top/u_apm64_top/u_apsram_sync/ddr_rsti_s0/I1
3.798	0.346	tINS	RF	1549	R9C20[3][B]	inst_apm64_top/u_apm64_top/u_apsram_sync/ddr_rsti_s0/F
6.081	2.283	tNET	FF	1	R32C26[1][A]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/wr_dq_d1_29_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					userclk
10.000	0.000	tCL	RR	2337	TOPSIDE[0]	inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
11.526	1.526	tNET	RR	1	R32C26[1][A]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/wr_dq_d1_29_s0/CLK
11.491	-0.035	tUnc				inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/wr_dq_d1_29_s0
11.213	-0.278	tSu		1	R32C26[1][A]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/wr_dq_d1_29_s0

Path Statistics:

Clock Skew	-0.633
Setup Relationship	10.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.587, 27.181%; route: 1.572, 72.819%
Arrival Data Path Delay	cell: 0.346, 8.822%; route: 3.270, 83.376%; tC2Q: 0.306, 7.802%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.526, 100.000%

Path21

Path Summary:

Slack	5.132
Data Arrival Time	6.077
Data Required Time	11.208
From	inst_apm64_top/u_apm64_top/u_apsram_sync/dll_rst_s0
To	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/wr_dq_d_14_s0
Launch Clk	clkin:[R]
Latch Clk	userclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOB26[A]	clk_ibuf/I
0.587	0.587	tINS	RR	81	IOB26[A]	clk_ibuf/O
2.159	1.572	tNET	RR	1	R2C2[1][A]	inst_apm64_top/u_apm64_top/u_apsram_sync/dll_rst_s0/CLK
2.465	0.306	tC2Q	RR	3	R2C2[1][A]	inst_apm64_top/u_apm64_top/u_apsram_sync/dll_rst_s0/Q
3.452	0.987	tNET	RR	1	R9C20[3][B]	inst_apm64_top/u_apm64_top/u_apsram_sync/ddr_rsti_s0/I1
3.798	0.346	tINS	RF	1549	R9C20[3][B]	inst_apm64_top/u_apm64_top/u_apsram_sync/ddr_rsti_s0/F
6.077	2.278	tNET	FF	1	R31C30[1][B]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/wr_dq_d_14_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					userclk
10.000	0.000	tCL	RR	2337	TOPSIDE[0]	inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
11.521	1.521	tNET	RR	1	R31C30[1][B]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/wr_dq_d_14_s0/CLK
11.486	-0.035	tUnc				inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/wr_dq_d_14_s0
11.208	-0.278	tSu		1	R31C30[1][B]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/wr_dq_d_14_s0

Path Statistics:

Clock Skew	-0.638
Setup Relationship	10.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.587, 27.181%; route: 1.572, 72.819%
Arrival Data Path Delay	cell: 0.346, 8.833%; route: 3.265, 83.356%; tC2Q: 0.306, 7.812%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.521, 100.000%

Path22

Path Summary:

Slack	5.132
Data Arrival Time	6.077
Data Required Time	11.208
From	inst_apm64_top/u_apm64_top/u_apsram_sync/dll_rst_s0
To	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/wr_dq_d_15_s0
Launch Clk	clkin:[R]
Latch Clk	userclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOB26[A]	clk_ibuf/I
0.587	0.587	tINS	RR	81	IOB26[A]	clk_ibuf/O
2.159	1.572	tNET	RR	1	R2C2[1][A]	inst_apm64_top/u_apm64_top/u_apsram_sync/dll_rst_s0/CLK
2.465	0.306	tC2Q	RR	3	R2C2[1][A]	inst_apm64_top/u_apm64_top/u_apsram_sync/dll_rst_s0/Q
3.452	0.987	tNET	RR	1	R9C20[3][B]	inst_apm64_top/u_apm64_top/u_apsram_sync/ddr_rsti_s0/I1
3.798	0.346	tINS	RF	1549	R9C20[3][B]	inst_apm64_top/u_apm64_top/u_apsram_sync/ddr_rsti_s0/F
6.077	2.278	tNET	FF	1	R31C30[0][A]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/wr_dq_d_15_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					userclk
10.000	0.000	tCL	RR	2337	TOPSIDE[0]	inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
11.521	1.521	tNET	RR	1	R31C30[0][A]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/wr_dq_d_15_s0/CLK
11.486	-0.035	tUnc				inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/wr_dq_d_15_s0
11.208	-0.278	tSu		1	R31C30[0][A]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/wr_dq_d_15_s0

Path Statistics:

Clock Skew	-0.638
Setup Relationship	10.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.587, 27.181%; route: 1.572, 72.819%
Arrival Data Path Delay	cell: 0.346, 8.833%; route: 3.265, 83.356%; tC2Q: 0.306, 7.812%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.521, 100.000%

Path23

Path Summary:

Slack	5.132
Data Arrival Time	6.081
Data Required Time	11.213
From	inst_apm64_top/u_apm64_top/u_apsram_sync/dll_rst_s0
To	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/wr_dq_d_22_s0
Launch Clk	clkin:[R]
Latch Clk	userclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOB26[A]	clk_ibuf/I
0.587	0.587	tINS	RR	81	IOB26[A]	clk_ibuf/O
2.159	1.572	tNET	RR	1	R2C2[1][A]	inst_apm64_top/u_apm64_top/u_apsram_sync/dll_rst_s0/CLK
2.465	0.306	tC2Q	RR	3	R2C2[1][A]	inst_apm64_top/u_apm64_top/u_apsram_sync/dll_rst_s0/Q
3.452	0.987	tNET	RR	1	R9C20[3][B]	inst_apm64_top/u_apm64_top/u_apsram_sync/ddr_rsti_s0/I1
3.798	0.346	tINS	RF	1549	R9C20[3][B]	inst_apm64_top/u_apm64_top/u_apsram_sync/ddr_rsti_s0/F
6.081	2.283	tNET	FF	1	R32C22[0][B]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/wr_dq_d_22_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					userclk
10.000	0.000	tCL	RR	2337	TOPSIDE[0]	inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
11.526	1.526	tNET	RR	1	R32C22[0][B]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/wr_dq_d_22_s0/CLK
11.491	-0.035	tUnc				inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/wr_dq_d_22_s0
11.213	-0.278	tSu		1	R32C22[0][B]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/wr_dq_d_22_s0

Path Statistics:

Clock Skew	-0.633
Setup Relationship	10.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.587, 27.181%; route: 1.572, 72.819%
Arrival Data Path Delay	cell: 0.346, 8.822%; route: 3.270, 83.376%; tC2Q: 0.306, 7.802%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.526, 100.000%

Path24

Path Summary:

Slack	5.132
Data Arrival Time	6.081
Data Required Time	11.213
From	inst_apm64_top/u_apm64_top/u_apsram_sync/dll_rst_s0
To	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/wr_dq_d_29_s0
Launch Clk	clkin:[R]
Latch Clk	userclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOB26[A]	clk_ibuf/I
0.587	0.587	tINS	RR	81	IOB26[A]	clk_ibuf/O
2.159	1.572	tNET	RR	1	R2C2[1][A]	inst_apm64_top/u_apm64_top/u_apsram_sync/dll_rst_s0/CLK
2.465	0.306	tC2Q	RR	3	R2C2[1][A]	inst_apm64_top/u_apm64_top/u_apsram_sync/dll_rst_s0/Q
3.452	0.987	tNET	RR	1	R9C20[3][B]	inst_apm64_top/u_apm64_top/u_apsram_sync/ddr_rsti_s0/I1
3.798	0.346	tINS	RF	1549	R9C20[3][B]	inst_apm64_top/u_apm64_top/u_apsram_sync/ddr_rsti_s0/F
6.081	2.283	tNET	FF	1	R32C26[0][B]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/wr_dq_d_29_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					userclk
10.000	0.000	tCL	RR	2337	TOPSIDE[0]	inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
11.526	1.526	tNET	RR	1	R32C26[0][B]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/wr_dq_d_29_s0/CLK
11.491	-0.035	tUnc				inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/wr_dq_d_29_s0
11.213	-0.278	tSu		1	R32C26[0][B]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/wr_dq_d_29_s0

Path Statistics:

Clock Skew	-0.633
Setup Relationship	10.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.587, 27.181%; route: 1.572, 72.819%
Arrival Data Path Delay	cell: 0.346, 8.822%; route: 3.270, 83.376%; tC2Q: 0.306, 7.802%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.526, 100.000%

Path25

Path Summary:

Slack	5.132
Data Arrival Time	6.077
Data Required Time	11.208
From	inst_apm64_top/u_apm64_top/u_apsram_sync/dll_rst_s0
To	inst_apm64_top/u_apm64_top/rdbk_data_71_s1
Launch Clk	clkin:[R]
Latch Clk	userclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOB26[A]	clk_ibuf/I
0.587	0.587	tINS	RR	81	IOB26[A]	clk_ibuf/O
2.159	1.572	tNET	RR	1	R2C2[1][A]	inst_apm64_top/u_apm64_top/u_apsram_sync/dll_rst_s0/CLK
2.465	0.306	tC2Q	RR	3	R2C2[1][A]	inst_apm64_top/u_apm64_top/u_apsram_sync/dll_rst_s0/Q
3.452	0.987	tNET	RR	1	R9C20[3][B]	inst_apm64_top/u_apm64_top/u_apsram_sync/ddr_rsti_s0/I1
3.798	0.346	tINS	RF	1549	R9C20[3][B]	inst_apm64_top/u_apm64_top/u_apsram_sync/ddr_rsti_s0/F
6.077	2.278	tNET	FF	1	R13C10[1][B]	inst_apm64_top/u_apm64_top/rdbk_data_71_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					userclk
10.000	0.000	tCL	RR	2337	TOPSIDE[0]	inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
11.521	1.521	tNET	RR	1	R13C10[1][B]	inst_apm64_top/u_apm64_top/rdbk_data_71_s1/CLK
11.486	-0.035	tUnc				inst_apm64_top/u_apm64_top/rdbk_data_71_s1
11.208	-0.278	tSu		1	R13C10[1][B]	inst_apm64_top/u_apm64_top/rdbk_data_71_s1

Path Statistics:

Clock Skew	-0.638
Setup Relationship	10.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.587, 27.181%; route: 1.572, 72.819%
Arrival Data Path Delay	cell: 0.346, 8.833%; route: 3.265, 83.356%; tC2Q: 0.306, 7.812%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.521, 100.000%

Removal Analysis Report

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	1.215
Data Arrival Time	2.451
Data Required Time	1.236
From	u_reset_key/key_1_s0
To	cnt_7_s0
Launch Clk	clkin:[R]
Latch Clk	clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOB26[A]	clk_ibuf/I
0.581	0.581	tINS	RR	81	IOB26[A]	clk_ibuf/O
1.302	0.721	tNET	RR	1	R21C22[0][A]	u_reset_key/key_1_s0/CLK
1.446	0.144	tC2Q	RR	557	R21C22[0][A]	u_reset_key/key_1_s0/Q
2.451	1.005	tNET	RR	1	R27C21[0][A]	cnt_7_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOB26[A]	clk_ibuf/I
0.581	0.581	tINS	RR	81	IOB26[A]	clk_ibuf/O
1.289	0.708	tNET	RR	1	R27C21[0][A]	cnt_7_s0/CLK
1.236	-0.053	tHld		1	R27C21[0][A]	cnt_7_s0

Path Statistics:

Clock Skew	-0.013
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.581, 44.621%; route: 0.721, 55.379%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.005, 87.467%; tC2Q: 0.144, 12.533%
Required Clock Path Delay	cell: 0.581, 45.071%; route: 0.708, 54.929%

Path2

Path Summary:

Slack	1.215
Data Arrival Time	2.451
Data Required Time	1.236
From	u_reset_key/key_1_s0
To	cnt_8_s0
Launch Clk	clkin:[R]
Latch Clk	clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOB26[A]	clk_ibuf/I
0.581	0.581	tINS	RR	81	IOB26[A]	clk_ibuf/O
1.302	0.721	tNET	RR	1	R21C22[0][A]	u_reset_key/key_1_s0/CLK
1.446	0.144	tC2Q	RR	557	R21C22[0][A]	u_reset_key/key_1_s0/Q
2.451	1.005	tNET	RR	1	R27C21[0][B]	cnt_8_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOB26[A]	clk_ibuf/I
0.581	0.581	tINS	RR	81	IOB26[A]	clk_ibuf/O
1.289	0.708	tNET	RR	1	R27C21[0][B]	cnt_8_s0/CLK
1.236	-0.053	tHld		1	R27C21[0][B]	cnt_8_s0

Path Statistics:

Clock Skew	-0.013
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.581, 44.621%; route: 0.721, 55.379%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.005, 87.467%; tC2Q: 0.144, 12.533%
Required Clock Path Delay	cell: 0.581, 45.071%; route: 0.708, 54.929%

Path3

Path Summary:

Slack	1.215
Data Arrival Time	2.451
Data Required Time	1.236
From	u_reset_key/key_1_s0
To	cnt_9_s0
Launch Clk	clkin:[R]
Latch Clk	clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOB26[A]	clk_ibuf/I
0.581	0.581	tINS	RR	81	IOB26[A]	clk_ibuf/O
1.302	0.721	tNET	RR	1	R21C22[0][A]	u_reset_key/key_1_s0/CLK
1.446	0.144	tC2Q	RR	557	R21C22[0][A]	u_reset_key/key_1_s0/Q
2.451	1.005	tNET	RR	1	R27C21[1][A]	cnt_9_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOB26[A]	clk_ibuf/I
0.581	0.581	tINS	RR	81	IOB26[A]	clk_ibuf/O
1.289	0.708	tNET	RR	1	R27C21[1][A]	cnt_9_s0/CLK
1.236	-0.053	tHld		1	R27C21[1][A]	cnt_9_s0

Path Statistics:

Clock Skew	-0.013
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.581, 44.621%; route: 0.721, 55.379%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.005, 87.467%; tC2Q: 0.144, 12.533%
Required Clock Path Delay	cell: 0.581, 45.071%; route: 0.708, 54.929%

Path4

Path Summary:

Slack	1.215
Data Arrival Time	2.451
Data Required Time	1.236
From	u_reset_key/key_1_s0
To	cnt_10_s0
Launch Clk	clkin:[R]
Latch Clk	clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOB26[A]	clk_ibuf/I
0.581	0.581	tINS	RR	81	IOB26[A]	clk_ibuf/O
1.302	0.721	tNET	RR	1	R21C22[0][A]	u_reset_key/key_1_s0/CLK
1.446	0.144	tC2Q	RR	557	R21C22[0][A]	u_reset_key/key_1_s0/Q
2.451	1.005	tNET	RR	1	R27C21[1][B]	cnt_10_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOB26[A]	clk_ibuf/I
0.581	0.581	tINS	RR	81	IOB26[A]	clk_ibuf/O
1.289	0.708	tNET	RR	1	R27C21[1][B]	cnt_10_s0/CLK
1.236	-0.053	tHld		1	R27C21[1][B]	cnt_10_s0

Path Statistics:

Clock Skew	-0.013
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.581, 44.621%; route: 0.721, 55.379%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.005, 87.467%; tC2Q: 0.144, 12.533%
Required Clock Path Delay	cell: 0.581, 45.071%; route: 0.708, 54.929%

Path5

Path Summary:

Slack	1.215
Data Arrival Time	2.451
Data Required Time	1.236
From	u_reset_key/key_1_s0
To	cnt_11_s0
Launch Clk	clkin:[R]
Latch Clk	clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOB26[A]	clk_ibuf/I
0.581	0.581	tINS	RR	81	IOB26[A]	clk_ibuf/O
1.302	0.721	tNET	RR	1	R21C22[0][A]	u_reset_key/key_1_s0/CLK
1.446	0.144	tC2Q	RR	557	R21C22[0][A]	u_reset_key/key_1_s0/Q
2.451	1.005	tNET	RR	1	R27C21[2][A]	cnt_11_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOB26[A]	clk_ibuf/I
0.581	0.581	tINS	RR	81	IOB26[A]	clk_ibuf/O
1.289	0.708	tNET	RR	1	R27C21[2][A]	cnt_11_s0/CLK
1.236	-0.053	tHld		1	R27C21[2][A]	cnt_11_s0

Path Statistics:

Clock Skew	-0.013
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.581, 44.621%; route: 0.721, 55.379%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.005, 87.467%; tC2Q: 0.144, 12.533%
Required Clock Path Delay	cell: 0.581, 45.071%; route: 0.708, 54.929%

Path6

Path Summary:

Slack	1.215
Data Arrival Time	2.451
Data Required Time	1.236
From	u_reset_key/key_1_s0
To	cnt_12_s0
Launch Clk	clkin:[R]
Latch Clk	clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOB26[A]	clk_ibuf/I
0.581	0.581	tINS	RR	81	IOB26[A]	clk_ibuf/O
1.302	0.721	tNET	RR	1	R21C22[0][A]	u_reset_key/key_1_s0/CLK
1.446	0.144	tC2Q	RR	557	R21C22[0][A]	u_reset_key/key_1_s0/Q
2.451	1.005	tNET	RR	1	R27C21[2][B]	cnt_12_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOB26[A]	clk_ibuf/I
0.581	0.581	tINS	RR	81	IOB26[A]	clk_ibuf/O
1.289	0.708	tNET	RR	1	R27C21[2][B]	cnt_12_s0/CLK
1.236	-0.053	tHld		1	R27C21[2][B]	cnt_12_s0

Path Statistics:

Clock Skew	-0.013
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.581, 44.621%; route: 0.721, 55.379%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.005, 87.467%; tC2Q: 0.144, 12.533%
Required Clock Path Delay	cell: 0.581, 45.071%; route: 0.708, 54.929%

Path7

Path Summary:

Slack	1.215
Data Arrival Time	2.437
Data Required Time	1.222
From	u_reset_key/key_1_s0
To	inst_apm64_top/u_apm64_top/u_apsram_sync/flag_0_s4
Launch Clk	clkin:[R]
Latch Clk	clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOB26[A]	clk_ibuf/I
0.581	0.581	tINS	RR	81	IOB26[A]	clk_ibuf/O
1.302	0.721	tNET	RR	1	R21C22[0][A]	u_reset_key/key_1_s0/CLK
1.446	0.144	tC2Q	RR	557	R21C22[0][A]	u_reset_key/key_1_s0/Q
2.437	0.991	tNET	RR	1	R11C20[2][A]	inst_apm64_top/u_apm64_top/u_apsram_sync/flag_0_s4/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOB26[A]	clk_ibuf/I
0.581	0.581	tINS	RR	81	IOB26[A]	clk_ibuf/O
1.275	0.694	tNET	RR	1	R11C20[2][A]	inst_apm64_top/u_apm64_top/u_apsram_sync/flag_0_s4/CLK
1.222	-0.053	tHld		1	R11C20[2][A]	inst_apm64_top/u_apm64_top/u_apsram_sync/flag_0_s4

Path Statistics:

Clock Skew	-0.027
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.581, 44.621%; route: 0.721, 55.379%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.991, 87.313%; tC2Q: 0.144, 12.687%
Required Clock Path Delay	cell: 0.581, 45.566%; route: 0.694, 54.434%

Path8

Path Summary:

Slack	1.215
Data Arrival Time	2.437
Data Required Time	1.222
From	u_reset_key/key_1_s0
To	inst_apm64_top/u_apm64_top/u_apsram_sync/cs_memsync_4_s0
Launch Clk	clkin:[R]
Latch Clk	clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOB26[A]	clk_ibuf/I
0.581	0.581	tINS	RR	81	IOB26[A]	clk_ibuf/O
1.302	0.721	tNET	RR	1	R21C22[0][A]	u_reset_key/key_1_s0/CLK
1.446	0.144	tC2Q	RR	557	R21C22[0][A]	u_reset_key/key_1_s0/Q
2.437	0.991	tNET	RR	1	R11C20[0][A]	inst_apm64_top/u_apm64_top/u_apsram_sync/cs_memsync_4_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOB26[A]	clk_ibuf/I
0.581	0.581	tINS	RR	81	IOB26[A]	clk_ibuf/O
1.275	0.694	tNET	RR	1	R11C20[0][A]	inst_apm64_top/u_apm64_top/u_apsram_sync/cs_memsync_4_s0/CLK
1.222	-0.053	tHld		1	R11C20[0][A]	inst_apm64_top/u_apm64_top/u_apsram_sync/cs_memsync_4_s0

Path Statistics:

Clock Skew	-0.027
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.581, 44.621%; route: 0.721, 55.379%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.991, 87.313%; tC2Q: 0.144, 12.687%
Required Clock Path Delay	cell: 0.581, 45.566%; route: 0.694, 54.434%

Path9

Path Summary:

Slack	1.219
Data Arrival Time	2.451
Data Required Time	1.232
From	u_reset_key/key_1_s0
To	cnt_1_s0
Launch Clk	clkin:[R]
Latch Clk	clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOB26[A]	clk_ibuf/I
0.581	0.581	tINS	RR	81	IOB26[A]	clk_ibuf/O
1.302	0.721	tNET	RR	1	R21C22[0][A]	u_reset_key/key_1_s0/CLK
1.446	0.144	tC2Q	RR	557	R21C22[0][A]	u_reset_key/key_1_s0/Q
2.451	1.005	tNET	RR	1	R27C20[0][A]	cnt_1_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOB26[A]	clk_ibuf/I
0.581	0.581	tINS	RR	81	IOB26[A]	clk_ibuf/O
1.285	0.704	tNET	RR	1	R27C20[0][A]	cnt_1_s0/CLK
1.232	-0.053	tHld		1	R27C20[0][A]	cnt_1_s0

Path Statistics:

Clock Skew	-0.017
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.581, 44.621%; route: 0.721, 55.379%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.005, 87.467%; tC2Q: 0.144, 12.533%
Required Clock Path Delay	cell: 0.581, 45.211%; route: 0.704, 54.789%

Path10

Path Summary:

Slack	1.219
Data Arrival Time	2.451
Data Required Time	1.232
From	u_reset_key/key_1_s0
To	cnt_2_s0
Launch Clk	clkin:[R]
Latch Clk	clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOB26[A]	clk_ibuf/I
0.581	0.581	tINS	RR	81	IOB26[A]	clk_ibuf/O
1.302	0.721	tNET	RR	1	R21C22[0][A]	u_reset_key/key_1_s0/CLK
1.446	0.144	tC2Q	RR	557	R21C22[0][A]	u_reset_key/key_1_s0/Q
2.451	1.005	tNET	RR	1	R27C20[0][B]	cnt_2_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOB26[A]	clk_ibuf/I
0.581	0.581	tINS	RR	81	IOB26[A]	clk_ibuf/O
1.285	0.704	tNET	RR	1	R27C20[0][B]	cnt_2_s0/CLK
1.232	-0.053	tHld		1	R27C20[0][B]	cnt_2_s0

Path Statistics:

Clock Skew	-0.017
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.581, 44.621%; route: 0.721, 55.379%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.005, 87.467%; tC2Q: 0.144, 12.533%
Required Clock Path Delay	cell: 0.581, 45.211%; route: 0.704, 54.789%

Path11

Path Summary:

Slack	1.219
Data Arrival Time	2.451
Data Required Time	1.232
From	u_reset_key/key_1_s0
To	cnt_3_s0
Launch Clk	clkin:[R]
Latch Clk	clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOB26[A]	clk_ibuf/I
0.581	0.581	tINS	RR	81	IOB26[A]	clk_ibuf/O
1.302	0.721	tNET	RR	1	R21C22[0][A]	u_reset_key/key_1_s0/CLK
1.446	0.144	tC2Q	RR	557	R21C22[0][A]	u_reset_key/key_1_s0/Q
2.451	1.005	tNET	RR	1	R27C20[1][A]	cnt_3_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOB26[A]	clk_ibuf/I
0.581	0.581	tINS	RR	81	IOB26[A]	clk_ibuf/O
1.285	0.704	tNET	RR	1	R27C20[1][A]	cnt_3_s0/CLK
1.232	-0.053	tHld		1	R27C20[1][A]	cnt_3_s0

Path Statistics:

Clock Skew	-0.017
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.581, 44.621%; route: 0.721, 55.379%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.005, 87.467%; tC2Q: 0.144, 12.533%
Required Clock Path Delay	cell: 0.581, 45.211%; route: 0.704, 54.789%

Path12

Path Summary:

Slack	1.219
Data Arrival Time	2.451
Data Required Time	1.232
From	u_reset_key/key_1_s0
To	cnt_4_s0
Launch Clk	clkin:[R]
Latch Clk	clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOB26[A]	clk_ibuf/I
0.581	0.581	tINS	RR	81	IOB26[A]	clk_ibuf/O
1.302	0.721	tNET	RR	1	R21C22[0][A]	u_reset_key/key_1_s0/CLK
1.446	0.144	tC2Q	RR	557	R21C22[0][A]	u_reset_key/key_1_s0/Q
2.451	1.005	tNET	RR	1	R27C20[1][B]	cnt_4_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOB26[A]	clk_ibuf/I
0.581	0.581	tINS	RR	81	IOB26[A]	clk_ibuf/O
1.285	0.704	tNET	RR	1	R27C20[1][B]	cnt_4_s0/CLK
1.232	-0.053	tHld		1	R27C20[1][B]	cnt_4_s0

Path Statistics:

Clock Skew	-0.017
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.581, 44.621%; route: 0.721, 55.379%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.005, 87.467%; tC2Q: 0.144, 12.533%
Required Clock Path Delay	cell: 0.581, 45.211%; route: 0.704, 54.789%

Path13

Path Summary:

Slack	1.219
Data Arrival Time	2.451
Data Required Time	1.232
From	u_reset_key/key_1_s0
To	cnt_5_s0
Launch Clk	clkin:[R]
Latch Clk	clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOB26[A]	clk_ibuf/I
0.581	0.581	tINS	RR	81	IOB26[A]	clk_ibuf/O
1.302	0.721	tNET	RR	1	R21C22[0][A]	u_reset_key/key_1_s0/CLK
1.446	0.144	tC2Q	RR	557	R21C22[0][A]	u_reset_key/key_1_s0/Q
2.451	1.005	tNET	RR	1	R27C20[2][A]	cnt_5_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOB26[A]	clk_ibuf/I
0.581	0.581	tINS	RR	81	IOB26[A]	clk_ibuf/O
1.285	0.704	tNET	RR	1	R27C20[2][A]	cnt_5_s0/CLK
1.232	-0.053	tHld		1	R27C20[2][A]	cnt_5_s0

Path Statistics:

Clock Skew	-0.017
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.581, 44.621%; route: 0.721, 55.379%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.005, 87.467%; tC2Q: 0.144, 12.533%
Required Clock Path Delay	cell: 0.581, 45.211%; route: 0.704, 54.789%

Path14

Path Summary:

Slack	1.219
Data Arrival Time	2.451
Data Required Time	1.232
From	u_reset_key/key_1_s0
To	cnt_6_s0
Launch Clk	clkin:[R]
Latch Clk	clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOB26[A]	clk_ibuf/I
0.581	0.581	tINS	RR	81	IOB26[A]	clk_ibuf/O
1.302	0.721	tNET	RR	1	R21C22[0][A]	u_reset_key/key_1_s0/CLK
1.446	0.144	tC2Q	RR	557	R21C22[0][A]	u_reset_key/key_1_s0/Q
2.451	1.005	tNET	RR	1	R27C20[2][B]	cnt_6_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOB26[A]	clk_ibuf/I
0.581	0.581	tINS	RR	81	IOB26[A]	clk_ibuf/O
1.285	0.704	tNET	RR	1	R27C20[2][B]	cnt_6_s0/CLK
1.232	-0.053	tHld		1	R27C20[2][B]	cnt_6_s0

Path Statistics:

Clock Skew	-0.017
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.581, 44.621%; route: 0.721, 55.379%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.005, 87.467%; tC2Q: 0.144, 12.533%
Required Clock Path Delay	cell: 0.581, 45.211%; route: 0.704, 54.789%

Path15

Path Summary:

Slack	1.219
Data Arrival Time	2.451
Data Required Time	1.232
From	u_reset_key/key_1_s0
To	cnt_13_s0
Launch Clk	clkin:[R]
Latch Clk	clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOB26[A]	clk_ibuf/I
0.581	0.581	tINS	RR	81	IOB26[A]	clk_ibuf/O
1.302	0.721	tNET	RR	1	R21C22[0][A]	u_reset_key/key_1_s0/CLK
1.446	0.144	tC2Q	RR	557	R21C22[0][A]	u_reset_key/key_1_s0/Q
2.451	1.005	tNET	RR	1	R27C22[0][A]	cnt_13_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOB26[A]	clk_ibuf/I
0.581	0.581	tINS	RR	81	IOB26[A]	clk_ibuf/O
1.285	0.704	tNET	RR	1	R27C22[0][A]	cnt_13_s0/CLK
1.232	-0.053	tHld		1	R27C22[0][A]	cnt_13_s0

Path Statistics:

Clock Skew	-0.017
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.581, 44.621%; route: 0.721, 55.379%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.005, 87.467%; tC2Q: 0.144, 12.533%
Required Clock Path Delay	cell: 0.581, 45.211%; route: 0.704, 54.789%

Path16

Path Summary:

Slack	1.219
Data Arrival Time	2.451
Data Required Time	1.232
From	u_reset_key/key_1_s0
To	cnt_14_s0
Launch Clk	clkin:[R]
Latch Clk	clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOB26[A]	clk_ibuf/I
0.581	0.581	tINS	RR	81	IOB26[A]	clk_ibuf/O
1.302	0.721	tNET	RR	1	R21C22[0][A]	u_reset_key/key_1_s0/CLK
1.446	0.144	tC2Q	RR	557	R21C22[0][A]	u_reset_key/key_1_s0/Q
2.451	1.005	tNET	RR	1	R27C22[0][B]	cnt_14_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOB26[A]	clk_ibuf/I
0.581	0.581	tINS	RR	81	IOB26[A]	clk_ibuf/O
1.285	0.704	tNET	RR	1	R27C22[0][B]	cnt_14_s0/CLK
1.232	-0.053	tHld		1	R27C22[0][B]	cnt_14_s0

Path Statistics:

Clock Skew	-0.017
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.581, 44.621%; route: 0.721, 55.379%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.005, 87.467%; tC2Q: 0.144, 12.533%
Required Clock Path Delay	cell: 0.581, 45.211%; route: 0.704, 54.789%

Path17

Path Summary:

Slack	1.219
Data Arrival Time	2.451
Data Required Time	1.232
From	u_reset_key/key_1_s0
To	cnt_15_s0
Launch Clk	clkin:[R]
Latch Clk	clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOB26[A]	clk_ibuf/I
0.581	0.581	tINS	RR	81	IOB26[A]	clk_ibuf/O
1.302	0.721	tNET	RR	1	R21C22[0][A]	u_reset_key/key_1_s0/CLK
1.446	0.144	tC2Q	RR	557	R21C22[0][A]	u_reset_key/key_1_s0/Q
2.451	1.005	tNET	RR	1	R27C22[1][A]	cnt_15_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOB26[A]	clk_ibuf/I
0.581	0.581	tINS	RR	81	IOB26[A]	clk_ibuf/O
1.285	0.704	tNET	RR	1	R27C22[1][A]	cnt_15_s0/CLK
1.232	-0.053	tHld		1	R27C22[1][A]	cnt_15_s0

Path Statistics:

Clock Skew	-0.017
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.581, 44.621%; route: 0.721, 55.379%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.005, 87.467%; tC2Q: 0.144, 12.533%
Required Clock Path Delay	cell: 0.581, 45.211%; route: 0.704, 54.789%

Path18

Path Summary:

Slack	1.219
Data Arrival Time	2.451
Data Required Time	1.232
From	u_reset_key/key_1_s0
To	cnt_16_s0
Launch Clk	clkin:[R]
Latch Clk	clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOB26[A]	clk_ibuf/I
0.581	0.581	tINS	RR	81	IOB26[A]	clk_ibuf/O
1.302	0.721	tNET	RR	1	R21C22[0][A]	u_reset_key/key_1_s0/CLK
1.446	0.144	tC2Q	RR	557	R21C22[0][A]	u_reset_key/key_1_s0/Q
2.451	1.005	tNET	RR	1	R27C22[1][B]	cnt_16_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOB26[A]	clk_ibuf/I
0.581	0.581	tINS	RR	81	IOB26[A]	clk_ibuf/O
1.285	0.704	tNET	RR	1	R27C22[1][B]	cnt_16_s0/CLK
1.232	-0.053	tHld		1	R27C22[1][B]	cnt_16_s0

Path Statistics:

Clock Skew	-0.017
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.581, 44.621%; route: 0.721, 55.379%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.005, 87.467%; tC2Q: 0.144, 12.533%
Required Clock Path Delay	cell: 0.581, 45.211%; route: 0.704, 54.789%

Path19

Path Summary:

Slack	1.219
Data Arrival Time	2.451
Data Required Time	1.232
From	u_reset_key/key_1_s0
To	cnt_17_s0
Launch Clk	clkin:[R]
Latch Clk	clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOB26[A]	clk_ibuf/I
0.581	0.581	tINS	RR	81	IOB26[A]	clk_ibuf/O
1.302	0.721	tNET	RR	1	R21C22[0][A]	u_reset_key/key_1_s0/CLK
1.446	0.144	tC2Q	RR	557	R21C22[0][A]	u_reset_key/key_1_s0/Q
2.451	1.005	tNET	RR	1	R27C22[2][A]	cnt_17_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOB26[A]	clk_ibuf/I
0.581	0.581	tINS	RR	81	IOB26[A]	clk_ibuf/O
1.285	0.704	tNET	RR	1	R27C22[2][A]	cnt_17_s0/CLK
1.232	-0.053	tHld		1	R27C22[2][A]	cnt_17_s0

Path Statistics:

Clock Skew	-0.017
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.581, 44.621%; route: 0.721, 55.379%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.005, 87.467%; tC2Q: 0.144, 12.533%
Required Clock Path Delay	cell: 0.581, 45.211%; route: 0.704, 54.789%

Path20

Path Summary:

Slack	1.219
Data Arrival Time	2.451
Data Required Time	1.232
From	u_reset_key/key_1_s0
To	cnt_18_s0
Launch Clk	clkin:[R]
Latch Clk	clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOB26[A]	clk_ibuf/I
0.581	0.581	tINS	RR	81	IOB26[A]	clk_ibuf/O
1.302	0.721	tNET	RR	1	R21C22[0][A]	u_reset_key/key_1_s0/CLK
1.446	0.144	tC2Q	RR	557	R21C22[0][A]	u_reset_key/key_1_s0/Q
2.451	1.005	tNET	RR	1	R27C22[2][B]	cnt_18_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOB26[A]	clk_ibuf/I
0.581	0.581	tINS	RR	81	IOB26[A]	clk_ibuf/O
1.285	0.704	tNET	RR	1	R27C22[2][B]	cnt_18_s0/CLK
1.232	-0.053	tHld		1	R27C22[2][B]	cnt_18_s0

Path Statistics:

Clock Skew	-0.017
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.581, 44.621%; route: 0.721, 55.379%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.005, 87.467%; tC2Q: 0.144, 12.533%
Required Clock Path Delay	cell: 0.581, 45.211%; route: 0.704, 54.789%

Path21

Path Summary:

Slack	1.219
Data Arrival Time	2.456
Data Required Time	1.237
From	u_reset_key/key_1_s0
To	cnt_0_s0
Launch Clk	clkin:[R]
Latch Clk	clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOB26[A]	clk_ibuf/I
0.581	0.581	tINS	RR	81	IOB26[A]	clk_ibuf/O
1.302	0.721	tNET	RR	1	R21C22[0][A]	u_reset_key/key_1_s0/CLK
1.446	0.144	tC2Q	RR	557	R21C22[0][A]	u_reset_key/key_1_s0/Q
2.456	1.010	tNET	RR	1	R26C20[2][A]	cnt_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOB26[A]	clk_ibuf/I
0.581	0.581	tINS	RR	81	IOB26[A]	clk_ibuf/O
1.290	0.709	tNET	RR	1	R26C20[2][A]	cnt_0_s0/CLK
1.237	-0.053	tHld		1	R26C20[2][A]	cnt_0_s0

Path Statistics:

Clock Skew	-0.012
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.581, 44.621%; route: 0.721, 55.379%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.010, 87.522%; tC2Q: 0.144, 12.478%
Required Clock Path Delay	cell: 0.581, 45.036%; route: 0.709, 54.964%

Path22

Path Summary:

Slack	1.222
Data Arrival Time	2.473
Data Required Time	1.251
From	u_reset_key/key_1_s0
To	inst_apm64_top/u_apm64_top/u_apsram_sync/lock_cnt_1_s3
Launch Clk	clkin:[R]
Latch Clk	clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOB26[A]	clk_ibuf/I
0.581	0.581	tINS	RR	81	IOB26[A]	clk_ibuf/O
1.302	0.721	tNET	RR	1	R21C22[0][A]	u_reset_key/key_1_s0/CLK
1.446	0.144	tC2Q	RR	557	R21C22[0][A]	u_reset_key/key_1_s0/Q
2.473	1.027	tNET	RR	1	R20C18[0][A]	inst_apm64_top/u_apm64_top/u_apsram_sync/lock_cnt_1_s3/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOB26[A]	clk_ibuf/I
0.581	0.581	tINS	RR	81	IOB26[A]	clk_ibuf/O
1.304	0.723	tNET	RR	1	R20C18[0][A]	inst_apm64_top/u_apm64_top/u_apsram_sync/lock_cnt_1_s3/CLK
1.251	-0.053	tHld		1	R20C18[0][A]	inst_apm64_top/u_apm64_top/u_apsram_sync/lock_cnt_1_s3

Path Statistics:

Clock Skew	0.002
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.581, 44.621%; route: 0.721, 55.379%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.027, 87.703%; tC2Q: 0.144, 12.297%
Required Clock Path Delay	cell: 0.581, 44.561%; route: 0.723, 55.439%

Path23

Path Summary:

Slack	1.222
Data Arrival Time	2.468
Data Required Time	1.245
From	u_reset_key/key_1_s0
To	inst_apm64_top/u_apm64_top/u_apsram_sync/lock_cnt_4_s3
Launch Clk	clkin:[R]
Latch Clk	clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOB26[A]	clk_ibuf/I
0.581	0.581	tINS	RR	81	IOB26[A]	clk_ibuf/O
1.302	0.721	tNET	RR	1	R21C22[0][A]	u_reset_key/key_1_s0/CLK
1.446	0.144	tC2Q	RR	557	R21C22[0][A]	u_reset_key/key_1_s0/Q
2.468	1.022	tNET	RR	1	R23C20[2][A]	inst_apm64_top/u_apm64_top/u_apsram_sync/lock_cnt_4_s3/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOB26[A]	clk_ibuf/I
0.581	0.581	tINS	RR	81	IOB26[A]	clk_ibuf/O
1.298	0.718	tNET	RR	1	R23C20[2][A]	inst_apm64_top/u_apm64_top/u_apsram_sync/lock_cnt_4_s3/CLK
1.245	-0.053	tHld		1	R23C20[2][A]	inst_apm64_top/u_apm64_top/u_apsram_sync/lock_cnt_4_s3

Path Statistics:

Clock Skew	-0.003
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.581, 44.621%; route: 0.721, 55.379%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.022, 87.647%; tC2Q: 0.144, 12.353%
Required Clock Path Delay	cell: 0.581, 44.741%; route: 0.718, 55.259%

Path24

Path Summary:

Slack	1.222
Data Arrival Time	2.473
Data Required Time	1.251
From	u_reset_key/key_1_s0
To	inst_apm64_top/u_apm64_top/u_apsram_sync/lock_cnt_7_s3
Launch Clk	clkin:[R]
Latch Clk	clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOB26[A]	clk_ibuf/I
0.581	0.581	tINS	RR	81	IOB26[A]	clk_ibuf/O
1.302	0.721	tNET	RR	1	R21C22[0][A]	u_reset_key/key_1_s0/CLK
1.446	0.144	tC2Q	RR	557	R21C22[0][A]	u_reset_key/key_1_s0/Q
2.473	1.027	tNET	RR	1	R20C20[0][A]	inst_apm64_top/u_apm64_top/u_apsram_sync/lock_cnt_7_s3/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOB26[A]	clk_ibuf/I
0.581	0.581	tINS	RR	81	IOB26[A]	clk_ibuf/O
1.304	0.723	tNET	RR	1	R20C20[0][A]	inst_apm64_top/u_apm64_top/u_apsram_sync/lock_cnt_7_s3/CLK
1.251	-0.053	tHld		1	R20C20[0][A]	inst_apm64_top/u_apm64_top/u_apsram_sync/lock_cnt_7_s3

Path Statistics:

Clock Skew	0.002
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.581, 44.621%; route: 0.721, 55.379%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.027, 87.703%; tC2Q: 0.144, 12.297%
Required Clock Path Delay	cell: 0.581, 44.561%; route: 0.723, 55.439%

Path25

Path Summary:

Slack	1.222
Data Arrival Time	2.473
Data Required Time	1.251
From	u_reset_key/key_1_s0
To	inst_apm64_top/u_apm64_top/u_apsram_sync/lock_cnt_10_s3
Launch Clk	clkin:[R]
Latch Clk	clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOB26[A]	clk_ibuf/I
0.581	0.581	tINS	RR	81	IOB26[A]	clk_ibuf/O
1.302	0.721	tNET	RR	1	R21C22[0][A]	u_reset_key/key_1_s0/CLK
1.446	0.144	tC2Q	RR	557	R21C22[0][A]	u_reset_key/key_1_s0/Q
2.473	1.027	tNET	RR	1	R20C20[2][A]	inst_apm64_top/u_apm64_top/u_apsram_sync/lock_cnt_10_s3/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOB26[A]	clk_ibuf/I
0.581	0.581	tINS	RR	81	IOB26[A]	clk_ibuf/O
1.304	0.723	tNET	RR	1	R20C20[2][A]	inst_apm64_top/u_apm64_top/u_apsram_sync/lock_cnt_10_s3/CLK
1.251	-0.053	tHld		1	R20C20[2][A]	inst_apm64_top/u_apm64_top/u_apsram_sync/lock_cnt_10_s3

Path Statistics:

Clock Skew	0.002
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.581, 44.621%; route: 0.721, 55.379%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.027, 87.703%; tC2Q: 0.144, 12.297%
Required Clock Path Delay	cell: 0.581, 44.561%; route: 0.723, 55.439%

Minimum Pulse Width Report:

Report Command:report_min_pulse_width -nworst 10 -detail

MPW1

MPW Summary:

Slack:	3.290
Actual Width:	4.152
Required Width:	0.862
Type:	Low Pulse Width
Clock:	userclk
Objects:	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[0].u_apm64_data_lane/u_out_fifo/mem2_mem2_0_1_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			userclk
5.000	0.000	tCL	FF	inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
6.548	1.548	tNET	FF	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[0].u_apm64_data_lane/u_out_fifo/mem2_mem2_0_1_s/CLKA

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			userclk
10.000	0.000	tCL	RR	inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
10.700	0.700	tNET	RR	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[0].u_apm64_data_lane/u_out_fifo/mem2_mem2_0_1_s/CLKA

MPW2

MPW Summary:

Slack:	3.290
Actual Width:	4.152
Required Width:	0.862
Type:	Low Pulse Width
Clock:	userclk
Objects:	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[0].u_apm64_data_lane/u_in_fifo/mem0_mem0_0_0_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			userclk
5.000	0.000	tCL	FF	inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
6.548	1.548	tNET	FF	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[0].u_apm64_data_lane/u_in_fifo/mem0_mem0_0_0_s/CLKA

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			userclk
10.000	0.000	tCL	RR	inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
10.700	0.700	tNET	RR	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[0].u_apm64_data_lane/u_in_fifo/mem0_mem0_0_0_s/CLKA

MPW3

MPW Summary:

Slack:	3.290
Actual Width:	4.152
Required Width:	0.862
Type:	Low Pulse Width
Clock:	userclk
Objects:	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[0].u_apm64_data_lane/u_in_fifo/mem0_mem0_0_1_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			userclk
5.000	0.000	tCL	FF	inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
6.548	1.548	tNET	FF	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[0].u_apm64_data_lane/u_in_fifo/mem0_mem0_0_1_s/CLKB

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			userclk
10.000	0.000	tCL	RR	inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
10.700	0.700	tNET	RR	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[0].u_apm64_data_lane/u_in_fifo/mem0_mem0_0_1_s/CLKB

MPW4

MPW Summary:

Slack:	3.290
Actual Width:	4.152
Required Width:	0.862
Type:	Low Pulse Width
Clock:	userclk
Objects:	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_out_fifo/mem2_mem2_0_0_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			userclk
5.000	0.000	tCL	FF	inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
6.548	1.548	tNET	FF	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_out_fifo/mem2_mem2_0_0_s/CLKB

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			userclk
10.000	0.000	tCL	RR	inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
10.700	0.700	tNET	RR	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_out_fifo/mem2_mem2_0_0_s/CLKB

MPW5

MPW Summary:

Slack:	3.290
Actual Width:	4.152
Required Width:	0.862
Type:	Low Pulse Width
Clock:	userclk
Objects:	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_in_fifo/mem0_mem0_0_0_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			userclk
5.000	0.000	tCL	FF	inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
6.548	1.548	tNET	FF	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_in_fifo/mem0_mem0_0_0_s/CLKB

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			userclk
10.000	0.000	tCL	RR	inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
10.700	0.700	tNET	RR	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_in_fifo/mem0_mem0_0_0_s/CLKB

MPW6

MPW Summary:

Slack:	3.290
Actual Width:	4.152
Required Width:	0.862
Type:	Low Pulse Width
Clock:	userclk
Objects:	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[0].u_apm64_data_lane/u_out_fifo/gowin_add_SDPX9B_mem2_mem2_0_0_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			userclk
5.000	0.000	tCL	FF	inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
6.548	1.548	tNET	FF	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[0].u_apm64_data_lane/u_out_fifo/gowin_add_SDPX9B_mem2_mem2_0_0_s/CLKB

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			userclk
10.000	0.000	tCL	RR	inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
10.700	0.700	tNET	RR	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[0].u_apm64_data_lane/u_out_fifo/gowin_add_SDPX9B_mem2_mem2_0_0_s/CLKB

MPW7

MPW Summary:

Slack:	3.290
Actual Width:	4.152
Required Width:	0.862
Type:	Low Pulse Width
Clock:	userclk
Objects:	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_out_fifo/gowin_add_SDPX9B_mem2_mem2_0_1_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			userclk
5.000	0.000	tCL	FF	inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
6.548	1.548	tNET	FF	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_out_fifo/gowin_add_SDPX9B_mem2_mem2_0_1_s/CLKA

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			userclk
10.000	0.000	tCL	RR	inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
10.700	0.700	tNET	RR	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_out_fifo/gowin_add_SDPX9B_mem2_mem2_0_1_s/CLKA

MPW8

MPW Summary:

Slack:	3.290
Actual Width:	4.152
Required Width:	0.862
Type:	Low Pulse Width
Clock:	userclk
Objects:	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_in_fifo/gowin_add_SDPB_mem0_mem0_0_1_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			userclk
5.000	0.000	tCL	FF	inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
6.548	1.548	tNET	FF	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_in_fifo/gowin_add_SDPB_mem0_mem0_0_1_s/CLKA

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			userclk
10.000	0.000	tCL	RR	inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
10.700	0.700	tNET	RR	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_in_fifo/gowin_add_SDPB_mem0_mem0_0_1_s/CLKA

MPW9

MPW Summary:

Slack:	3.292
Actual Width:	4.154
Required Width:	0.862
Type:	High Pulse Width
Clock:	userclk
Objects:	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[0].u_apm64_data_lane/u_out_fifo/mem2_mem2_0_1_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			userclk
0.000	0.000	tCL	RR	inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
1.551	1.551	tNET	RR	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[0].u_apm64_data_lane/u_out_fifo/mem2_mem2_0_1_s/CLKA

Early clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			userclk
5.000	0.000	tCL	FF	inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
5.705	0.705	tNET	FF	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[0].u_apm64_data_lane/u_out_fifo/mem2_mem2_0_1_s/CLKA

MPW10

MPW Summary:

Slack:	3.292
Actual Width:	4.154
Required Width:	0.862
Type:	High Pulse Width
Clock:	userclk
Objects:	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[0].u_apm64_data_lane/u_in_fifo/mem0_mem0_0_0_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			userclk
0.000	0.000	tCL	RR	inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
1.551	1.551	tNET	RR	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[0].u_apm64_data_lane/u_in_fifo/mem0_mem0_0_0_s/CLKA

Early clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			userclk
5.000	0.000	tCL	FF	inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
5.705	0.705	tNET	FF	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[0].u_apm64_data_lane/u_in_fifo/mem0_mem0_0_0_s/CLKA

High Fanout Nets Report:

Report Command:report_high_fanout_nets -max_nets 10

FANOUT	NET NAME	WORST SLACK	MAX DELAY
2337	clk_x1	2.453	1.580
1549	ddr_rsti	4.993	2.403
339	init_calib_Z	3.267	2.107
173	config_done_Z	3.353	3.715
129	rd_data_valid_d0	7.286	2.162
129	n89_6	2.480	3.801
129	rd_data_valid_init[0]	6.940	2.478
129	rd_data_valid_init[1]	6.674	2.614
122	c_state_data_lane[5]	3.386	2.183
113	n965_5	5.529	2.138

Route Congestions Report:

Report Command:report_route_congestion -max_grids 10

GRID LOC	ROUTE CONGESTIONS
R10C21	55.56%
R11C20	52.78%
R10C24	50.00%
R10C20	48.61%
R10C22	48.61%
R10C30	47.22%
R10C23	47.22%
R28C20	45.83%
R12C11	44.44%
R12C20	44.44%

Timing Exceptions Report:

Setup Analysis Report

Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Hold Analysis Report

Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Recovery Analysis Report

Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Removal Analysis Report

Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Timing Constraints Report:

SDC Command Type	State	Detail Command
TC_CLOCK	Actived	create_clock -name clkin -period 20 -waveform {0 10} [get_ports {clk}]
TC_CLOCK	Actived	create_clock -name mem_clk -period 2.5 -waveform {0 1.25} [get_nets {memory_clk}]
TC_GENERATED_CLOCK	Actived	create_generated_clock -name userclk -source [get_nets {memory_clk}] -master_clock mem_clk -divide_by 4 -duty_cycle 50 [get_pins {inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT}]
TC_CLOCK_GROUP	Actived	set_clock_groups -asynchronous -group [get_clocks {clkin}] -group [get_clocks {mem_clk}]
TC_CLOCK_GROUP	Actived	set_clock_groups -asynchronous -group [get_clocks {userclk}] -group [get_clocks {mem_clk}]