Power Messages

Report Title	Power Analysis Report
Design File	E:\memory\apm26408a\Gowin_UHS_PSRAM_Memory_Interface_refDesign\UHS_PSRAM_V2.0_64Mbit\project\fpga_project\impl\gwsynthesis\fpga_project.vg
Physical Constraints File	E:\memory\apm26408a\Gowin_UHS_PSRAM_Memory_Interface_refDesign\UHS_PSRAM_V2.0_64Mbit\project\fpga_project\src\fpga_project.cst
Timing Constraints File	E:\memory\apm26408a\Gowin_UHS_PSRAM_Memory_Interface_refDesign\UHS_PSRAM_V2.0_64Mbit\project\fpga_project\src\fpga_project.sdc
Tool Version	V1.9.10.01 (64-bit)
Part Number	GW5AR-LV25UG256PC2/I1
Device	GW5AR-25
Device Version	A
Created Time	Thu Aug 8 18:54:23 2024
Legal Announcement	Copyright (C)2014-2024 Gowin Semiconductor Corporation. All rights reserved.

Configure Information:

Grade	Commercial
Process	Typical
Ambient Temperature	25.000
Use Custom Theta JA	false
Heat Sink	None
Air Flow	LFM_0
Use Custom Theta SA	false
Board Thermal Model	None
Use Custom Theta JB	false
Related Vcd File
Related Saif File
Filter Glitches	false
Default IO Toggle Rate	0.125
Default Remain Toggle Rate	0.125

Power Summary

Power Information:

Total Power (mW)	238.588
Quiescent Power (mW)	52.103
Dynamic Power (mW)	186.485

Thermal Information:

Junction Temperature	31.537
Theta JA	27.400
Max Allowed Ambient Temperature	78.463

Supply Information:

Voltage Source	Voltage	Dynamic Current(mA)	Quiescent Current(mA)	Power(mW)
VCC	0.900	138.202	29.998	151.380
VCCX	3.300	2.741	3.000	18.946
VCCIO18	1.800	2.631	0.847	6.261
VCCIO33	3.300	0.113	0.146	0.855
VCC_LDO	3.300	14.529	4.000	61.147

Power Details

Power By Block Type:

Block Type	Total Power(mW)	Static Power(mW)	Average Toggle Rate(millions of transitions/sec)
Logic	1.569	NA	12.268
IO	23.382	6.423	62.364
BSRAM	86.832	NA	NA
PLL	47.947	NA	NA
DDRDLL	33.178	NA	NA
DQS	83.268	NA	NA

Power By Hierarchy:

Hierarchy Entity	Total Power(mW)	Block Dynamic Power(mW)
top	252.794	252.794(252.756)
top/inst_apm64_top/	204.484	204.484(204.484)
top/inst_apm64_top/u_apm64_top/	204.484	204.484(171.058)
top/inst_apm64_top/u_apm64_top/u_apsram_ctrl/	0.146	0.146(0.000)
top/inst_apm64_top/u_apm64_top/u_apsram_init/	0.325	0.325(0.000)
top/inst_apm64_top/u_apm64_top/u_apsram_sync/	0.015	0.015(0.000)
top/inst_apm64_top/u_apm64_top/u_apsram_wd/	170.516	170.516(170.514)
top/inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[0].u_apm64_data_lane/	85.231	85.231(43.416)
top/inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[0].u_apm64_data_lane/u_in_fifo/	21.514	21.514(0.000)
top/inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[0].u_apm64_data_lane/u_out_fifo/	21.902	21.902(0.000)
top/inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/	85.218	85.218(43.416)
top/inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_in_fifo/	21.514	21.514(0.000)
top/inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_out_fifo/	21.902	21.902(0.000)
top/inst_apm64_top/u_apm64_top/u_apsram_wd/fifo_ctrl_in_gen[0].u_fifo_ctrl/	0.014	0.014(0.000)
top/inst_apm64_top/u_apm64_top/u_apsram_wd/fifo_ctrl_in_gen[1].u_fifo_ctrl/	0.014	0.014(0.000)
top/inst_apm64_top/u_apm64_top/u_apsram_wd/u_apm64_cmd_lane/	0.019	0.019(0.000)
top/inst_apm64_top/u_apm64_top/u_apsram_wd/u_fifo_ctrl/	0.017	0.017(0.000)
top/inst_apm64_top/u_apm64_top/u_cmd_fifo/	0.057	0.057(0.000)
top/u_Gowin_PLL/	47.947	47.947(0.000)
top/u_reset_key/	0.030	0.030(0.000)
top/u_test/	0.295	0.295(0.000)

Power By Clock Domain:

Clock Domain	Clock Frequency(Mhz)	Total Dynamic Power(mW)
userclk	100.000	88.244
clkin	50.000	48.029
NO CLOCK DOMAIN	0.000	0.000
mem_clk	400.000	116.521